From 2d63e6a3d97132449451c2f66fe24a2dc4e2938f Mon Sep 17 00:00:00 2001
From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Date: Wed, 21 Sep 2022 11:13:41 +0200
Subject: [PATCH 001/875] scripts: coccicheck: use "grep -E" instead of "egrep"

The latest version of grep claims that egrep is now obsolete so the build
now contains warnings that look like:
        egrep: warning: egrep is obsolescent; using grep -E
fix this up by moving the vdso Makefile to use "grep -E" instead.

Cc: Julia Lawall <Julia.Lawall@inria.fr>
Cc: Nicolas Palix <nicolas.palix@imag.fr>
Cc: cocci@inria.fr
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 scripts/coccicheck | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scripts/coccicheck b/scripts/coccicheck
index caba0bff6da7e..2956fce8fa4fc 100755
--- a/scripts/coccicheck
+++ b/scripts/coccicheck
@@ -47,7 +47,7 @@ FLAGS="--very-quiet"
 # inspected there.
 #
 # --profile will not output if --very-quiet is used, so avoid it.
-echo $SPFLAGS | egrep -e "--profile|--show-trying" 2>&1 > /dev/null
+echo $SPFLAGS | grep -E -e "--profile|--show-trying" 2>&1 > /dev/null
 if [ $? -eq 0 ]; then
 	FLAGS="--quiet"
 fi
-- 
GitLab


From bd6ae049b7be4785082e5c3c0a80e8c9e3ff2fc6 Mon Sep 17 00:00:00 2001
From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
Date: Fri, 9 Sep 2022 19:12:31 +0300
Subject: [PATCH 002/875] fs/ntfs3: Add comments about cluster size

This commit adds additional info about CONFIG_NTFS3_64BIT_CLUSTER

Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/frecord.c |  2 +-
 fs/ntfs3/record.c  |  4 ++++
 fs/ntfs3/super.c   | 24 ++++++++++++++++++++++++
 3 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/fs/ntfs3/frecord.c b/fs/ntfs3/frecord.c
index 381a38a06ec22..b752d83cf4605 100644
--- a/fs/ntfs3/frecord.c
+++ b/fs/ntfs3/frecord.c
@@ -557,7 +557,7 @@ static int ni_repack(struct ntfs_inode *ni)
 		}
 
 		if (!mi_p) {
-			/* Do not try if not enogh free space. */
+			/* Do not try if not enough free space. */
 			if (le32_to_cpu(mi->mrec->used) + 8 >= rs)
 				continue;
 
diff --git a/fs/ntfs3/record.c b/fs/ntfs3/record.c
index 7d2fac5ee2156..c8741cfa421fe 100644
--- a/fs/ntfs3/record.c
+++ b/fs/ntfs3/record.c
@@ -537,6 +537,10 @@ bool mi_resize_attr(struct mft_inode *mi, struct ATTRIB *attr, int bytes)
 	return true;
 }
 
+/*
+ * Pack runs in MFT record.
+ * If failed record is not changed.
+ */
 int mi_pack_runs(struct mft_inode *mi, struct ATTRIB *attr,
 		 struct runs_tree *run, CLST len)
 {
diff --git a/fs/ntfs3/super.c b/fs/ntfs3/super.c
index 47012c9bf505e..683687ca8542b 100644
--- a/fs/ntfs3/super.c
+++ b/fs/ntfs3/super.c
@@ -21,6 +21,30 @@
  * https://docs.microsoft.com/en-us/windows/wsl/file-permissions
  * It stores uid/gid/mode/dev in xattr
  *
+ * ntfs allows up to 2^64 clusters per volume.
+ * It means you should use 64 bits lcn to operate with ntfs.
+ * Implementation of ntfs.sys uses only 32 bits lcn.
+ * Default ntfs3 uses 32 bits lcn too.
+ * ntfs3 built with CONFIG_NTFS3_64BIT_CLUSTER (ntfs3_64) uses 64 bits per lcn.
+ *
+ *
+ *     ntfs limits, cluster size is 4K (2^12)
+ * -----------------------------------------------------------------------------
+ * | Volume size   | Clusters | ntfs.sys | ntfs3  | ntfs3_64 | mkntfs | chkdsk |
+ * -----------------------------------------------------------------------------
+ * | < 16T, 2^44   |  < 2^32  |  yes     |  yes   |   yes    |  yes   |  yes   |
+ * | > 16T, 2^44   |  > 2^32  |  no      |  no    |   yes    |  yes   |  yes   |
+ * ----------------------------------------------------------|------------------
+ *
+ * To mount large volumes as ntfs one should use large cluster size (up to 2M)
+ * The maximum volume size in this case is 2^32 * 2^21 = 2^53 = 8P
+ *
+ *     ntfs limits, cluster size is 2M (2^31)
+ * -----------------------------------------------------------------------------
+ * | < 8P, 2^54    |  < 2^32  |  yes     |  yes   |   yes    |  yes   |  yes   |
+ * | > 8P, 2^54    |  > 2^32  |  no      |  no    |   yes    |  yes   |  yes   |
+ * ----------------------------------------------------------|------------------
+ *
  */
 
 #include <linux/blkdev.h>
-- 
GitLab


From 098250db5dfcc01161fd64e9bce5b012280a85b3 Mon Sep 17 00:00:00 2001
From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
Date: Mon, 12 Sep 2022 18:28:51 +0300
Subject: [PATCH 003/875] fs/ntfs3: Add hidedotfiles option

With this option all files with filename[0] == '.'
will have FILE_ATTRIBUTE_HIDDEN attribute.

Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/inode.c   | 4 ++++
 fs/ntfs3/ntfs_fs.h | 1 +
 fs/ntfs3/super.c   | 5 +++++
 3 files changed, 10 insertions(+)

diff --git a/fs/ntfs3/inode.c b/fs/ntfs3/inode.c
index 51363d4e8636b..40b8565815a24 100644
--- a/fs/ntfs3/inode.c
+++ b/fs/ntfs3/inode.c
@@ -1257,6 +1257,10 @@ struct inode *ntfs_create_inode(struct user_namespace *mnt_userns,
 		fa = FILE_ATTRIBUTE_ARCHIVE;
 	}
 
+	/* If option "hidedotfiles" then set hidden attribute for dot files. */
+	if (sbi->options->hide_dot_files && name->name[0] == '.')
+		fa |= FILE_ATTRIBUTE_HIDDEN;
+
 	if (!(mode & 0222))
 		fa |= FILE_ATTRIBUTE_READONLY;
 
diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h
index 2c791222c4e27..cd680ada50abf 100644
--- a/fs/ntfs3/ntfs_fs.h
+++ b/fs/ntfs3/ntfs_fs.h
@@ -97,6 +97,7 @@ struct ntfs_mount_options {
 	unsigned sparse : 1; /* Create sparse files. */
 	unsigned showmeta : 1; /* Show meta files. */
 	unsigned nohidden : 1; /* Do not show hidden files. */
+	unsigned hide_dot_files : 1; /* Set hidden flag on dot files. */
 	unsigned force : 1; /* RW mount dirty volume. */
 	unsigned noacsrules : 1; /* Exclude acs rules. */
 	unsigned prealloc : 1; /* Preallocate space when file is growing. */
diff --git a/fs/ntfs3/super.c b/fs/ntfs3/super.c
index 683687ca8542b..5346280203d95 100644
--- a/fs/ntfs3/super.c
+++ b/fs/ntfs3/super.c
@@ -247,6 +247,7 @@ enum Opt {
 	Opt_force,
 	Opt_sparse,
 	Opt_nohidden,
+	Opt_hide_dot_files,
 	Opt_showmeta,
 	Opt_acl,
 	Opt_iocharset,
@@ -266,6 +267,7 @@ static const struct fs_parameter_spec ntfs_fs_parameters[] = {
 	fsparam_flag_no("force",		Opt_force),
 	fsparam_flag_no("sparse",		Opt_sparse),
 	fsparam_flag_no("hidden",		Opt_nohidden),
+	fsparam_flag_no("hidedotfiles",		Opt_hide_dot_files),
 	fsparam_flag_no("acl",			Opt_acl),
 	fsparam_flag_no("showmeta",		Opt_showmeta),
 	fsparam_flag_no("prealloc",		Opt_prealloc),
@@ -354,6 +356,9 @@ static int ntfs_fs_parse_param(struct fs_context *fc,
 	case Opt_nohidden:
 		opts->nohidden = result.negated ? 1 : 0;
 		break;
+	case Opt_hide_dot_files:
+		opts->hide_dot_files = result.negated ? 1 : 0;
+		break;
 	case Opt_acl:
 		if (!result.negated)
 #ifdef CONFIG_NTFS3_FS_POSIX_ACL
-- 
GitLab


From ae6b47b5653e986e1dcaeb1ca7d13a04aeefdcfe Mon Sep 17 00:00:00 2001
From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
Date: Mon, 12 Sep 2022 18:54:06 +0300
Subject: [PATCH 004/875] fs/ntfs3: Change destroy_inode to free_inode

Many filesystems already use free_inode callback,
so we will use it too from now on.

Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/super.c | 20 ++++----------------
 1 file changed, 4 insertions(+), 16 deletions(-)

diff --git a/fs/ntfs3/super.c b/fs/ntfs3/super.c
index 5346280203d95..87d9eabf98476 100644
--- a/fs/ntfs3/super.c
+++ b/fs/ntfs3/super.c
@@ -435,27 +435,18 @@ static struct inode *ntfs_alloc_inode(struct super_block *sb)
 		return NULL;
 
 	memset(ni, 0, offsetof(struct ntfs_inode, vfs_inode));
-
 	mutex_init(&ni->ni_lock);
-
 	return &ni->vfs_inode;
 }
 
-static void ntfs_i_callback(struct rcu_head *head)
+static void ntfs_free_inode(struct inode *inode)
 {
-	struct inode *inode = container_of(head, struct inode, i_rcu);
 	struct ntfs_inode *ni = ntfs_i(inode);
 
 	mutex_destroy(&ni->ni_lock);
-
 	kmem_cache_free(ntfs_inode_cachep, ni);
 }
 
-static void ntfs_destroy_inode(struct inode *inode)
-{
-	call_rcu(&inode->i_rcu, ntfs_i_callback);
-}
-
 static void init_once(void *foo)
 {
 	struct ntfs_inode *ni = foo;
@@ -621,7 +612,7 @@ static int ntfs_sync_fs(struct super_block *sb, int wait)
 
 static const struct super_operations ntfs_sops = {
 	.alloc_inode = ntfs_alloc_inode,
-	.destroy_inode = ntfs_destroy_inode,
+	.free_inode = ntfs_free_inode,
 	.evict_inode = ntfs_evict_inode,
 	.put_super = ntfs_put_super,
 	.statfs = ntfs_statfs,
@@ -1517,11 +1508,8 @@ out1:
 
 static void __exit exit_ntfs_fs(void)
 {
-	if (ntfs_inode_cachep) {
-		rcu_barrier();
-		kmem_cache_destroy(ntfs_inode_cachep);
-	}
-
+	rcu_barrier();
+	kmem_cache_destroy(ntfs_inode_cachep);
 	unregister_filesystem(&ntfs_fs_type);
 	ntfs3_exit_bitmap();
 }
-- 
GitLab


From a3a956c78efaa202b1d75190136671cf6e87bfbe Mon Sep 17 00:00:00 2001
From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
Date: Fri, 23 Sep 2022 12:42:18 +0300
Subject: [PATCH 005/875] fs/ntfs3: Add option "nocase"

This commit adds mount option and additional functions.

Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/index.c   |   2 +-
 fs/ntfs3/namei.c   | 139 +++++++++++++++++++++++++++++++++++++++++++++
 fs/ntfs3/ntfs_fs.h |   4 ++
 fs/ntfs3/super.c   |   6 ++
 fs/ntfs3/upcase.c  |  12 ++++
 5 files changed, 162 insertions(+), 1 deletion(-)

diff --git a/fs/ntfs3/index.c b/fs/ntfs3/index.c
index 440328147e7e3..613036f9c6e66 100644
--- a/fs/ntfs3/index.c
+++ b/fs/ntfs3/index.c
@@ -47,7 +47,7 @@ static int cmp_fnames(const void *key1, size_t l1, const void *key2, size_t l2,
 	if (l2 < fsize2)
 		return -1;
 
-	both_case = f2->type != FILE_NAME_DOS /*&& !sbi->options.nocase*/;
+	both_case = f2->type != FILE_NAME_DOS && !sbi->options->nocase;
 	if (!l1) {
 		const struct le_str *s2 = (struct le_str *)&f2->name_len;
 
diff --git a/fs/ntfs3/namei.c b/fs/ntfs3/namei.c
index bc22cc321a74b..315763eb05ff2 100644
--- a/fs/ntfs3/namei.c
+++ b/fs/ntfs3/namei.c
@@ -7,6 +7,7 @@
 
 #include <linux/fs.h>
 #include <linux/nls.h>
+#include <linux/ctype.h>
 
 #include "debug.h"
 #include "ntfs.h"
@@ -355,6 +356,138 @@ struct dentry *ntfs3_get_parent(struct dentry *child)
 	return ERR_PTR(-ENOENT);
 }
 
+/*
+ * dentry_operations::d_hash
+ */
+static int ntfs_d_hash(const struct dentry *dentry, struct qstr *name)
+{
+	struct ntfs_sb_info *sbi;
+	const char *n = name->name;
+	unsigned int len = name->len;
+	unsigned long hash;
+	struct cpu_str *uni;
+	unsigned int c;
+	int err;
+
+	/* First try fast implementation. */
+	hash = init_name_hash(dentry);
+
+	for (;;) {
+		if (!len--) {
+			name->hash = end_name_hash(hash);
+			return 0;
+		}
+
+		c = *n++;
+		if (c >= 0x80)
+			break;
+
+		hash = partial_name_hash(toupper(c), hash);
+	}
+
+	/*
+	 * Try slow way with current upcase table
+	 */
+	uni = __getname();
+	if (!uni)
+		return -ENOMEM;
+
+	sbi = dentry->d_sb->s_fs_info;
+
+	err = ntfs_nls_to_utf16(sbi, name->name, name->len, uni, NTFS_NAME_LEN,
+				UTF16_HOST_ENDIAN);
+	if (err < 0)
+		goto out;
+
+	if (!err) {
+		err = -EINVAL;
+		goto out;
+	}
+
+	hash = ntfs_names_hash(uni->name, uni->len, sbi->upcase,
+			       init_name_hash(dentry));
+	name->hash = end_name_hash(hash);
+	err = 0;
+
+out:
+	__putname(uni);
+	return err;
+}
+
+/*
+ * dentry_operations::d_compare
+ */
+static int ntfs_d_compare(const struct dentry *dentry, unsigned int len1,
+			  const char *str, const struct qstr *name)
+{
+	struct ntfs_sb_info *sbi;
+	int ret;
+	const char *n1 = str;
+	const char *n2 = name->name;
+	unsigned int len2 = name->len;
+	unsigned int lm = min(len1, len2);
+	unsigned char c1, c2;
+	struct cpu_str *uni1, *uni2;
+
+	/* First try fast implementation. */
+	for (;;) {
+		if (!lm--) {
+			ret = len1 == len2 ? 0 : 1;
+			goto out;
+		}
+
+		if ((c1 = *n1++) == (c2 = *n2++))
+			continue;
+
+		if (c1 >= 0x80 || c2 >= 0x80)
+			break;
+
+		if (toupper(c1) != toupper(c2)) {
+			ret = 1;
+			goto out;
+		}
+	}
+
+	/*
+	 * Try slow way with current upcase table
+	 */
+	sbi = dentry->d_sb->s_fs_info;
+	uni1 = __getname();
+	if (!uni1)
+		return -ENOMEM;
+
+	ret = ntfs_nls_to_utf16(sbi, str, len1, uni1, NTFS_NAME_LEN,
+				UTF16_HOST_ENDIAN);
+	if (ret < 0)
+		goto out;
+
+	if (!ret) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	uni2 = Add2Ptr(uni1, 2048);
+
+	ret = ntfs_nls_to_utf16(sbi, name->name, name->len, uni2, NTFS_NAME_LEN,
+				UTF16_HOST_ENDIAN);
+	if (ret < 0)
+		goto out;
+
+	if (!ret) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	ret = !ntfs_cmp_names(uni1->name, uni1->len, uni2->name, uni2->len,
+			      sbi->upcase, false)
+		      ? 0
+		      : 1;
+
+out:
+	__putname(uni1);
+	return ret;
+}
+
 // clang-format off
 const struct inode_operations ntfs_dir_inode_operations = {
 	.lookup		= ntfs_lookup,
@@ -382,4 +515,10 @@ const struct inode_operations ntfs_special_inode_operations = {
 	.get_acl	= ntfs_get_acl,
 	.set_acl	= ntfs_set_acl,
 };
+
+const struct dentry_operations ntfs_dentry_ops = {
+	.d_hash		= ntfs_d_hash,
+	.d_compare	= ntfs_d_compare,
+};
+
 // clang-format on
diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h
index cd680ada50abf..6c1c7ef3b2d6a 100644
--- a/fs/ntfs3/ntfs_fs.h
+++ b/fs/ntfs3/ntfs_fs.h
@@ -101,6 +101,7 @@ struct ntfs_mount_options {
 	unsigned force : 1; /* RW mount dirty volume. */
 	unsigned noacsrules : 1; /* Exclude acs rules. */
 	unsigned prealloc : 1; /* Preallocate space when file is growing. */
+	unsigned nocase : 1; /* case insensitive. */
 };
 
 /* Special value to unpack and deallocate. */
@@ -721,6 +722,7 @@ struct dentry *ntfs3_get_parent(struct dentry *child);
 
 extern const struct inode_operations ntfs_dir_inode_operations;
 extern const struct inode_operations ntfs_special_inode_operations;
+extern const struct dentry_operations ntfs_dentry_ops;
 
 /* Globals from record.c */
 int mi_get(struct ntfs_sb_info *sbi, CLST rno, struct mft_inode **mi);
@@ -840,6 +842,8 @@ int ntfs_cmp_names(const __le16 *s1, size_t l1, const __le16 *s2, size_t l2,
 		   const u16 *upcase, bool bothcase);
 int ntfs_cmp_names_cpu(const struct cpu_str *uni1, const struct le_str *uni2,
 		       const u16 *upcase, bool bothcase);
+unsigned long ntfs_names_hash(const u16 *name, size_t len, const u16 *upcase,
+			      unsigned long hash);
 
 /* globals from xattr.c */
 #ifdef CONFIG_NTFS3_FS_POSIX_ACL
diff --git a/fs/ntfs3/super.c b/fs/ntfs3/super.c
index 87d9eabf98476..d72a27abf1c83 100644
--- a/fs/ntfs3/super.c
+++ b/fs/ntfs3/super.c
@@ -253,6 +253,7 @@ enum Opt {
 	Opt_iocharset,
 	Opt_prealloc,
 	Opt_noacsrules,
+	Opt_nocase,
 	Opt_err,
 };
 
@@ -272,6 +273,7 @@ static const struct fs_parameter_spec ntfs_fs_parameters[] = {
 	fsparam_flag_no("showmeta",		Opt_showmeta),
 	fsparam_flag_no("prealloc",		Opt_prealloc),
 	fsparam_flag_no("acsrules",		Opt_noacsrules),
+	fsparam_flag_no("nocase",		Opt_nocase),
 	fsparam_string("iocharset",		Opt_iocharset),
 	{}
 };
@@ -383,6 +385,9 @@ static int ntfs_fs_parse_param(struct fs_context *fc,
 	case Opt_noacsrules:
 		opts->noacsrules = result.negated ? 1 : 0;
 		break;
+	case Opt_nocase:
+		opts->nocase = result.negated ? 1 : 0;
+		break;
 	default:
 		/* Should not be here unless we forget add case. */
 		return -EINVAL;
@@ -936,6 +941,7 @@ static int ntfs_fill_super(struct super_block *sb, struct fs_context *fc)
 	sb->s_export_op = &ntfs_export_ops;
 	sb->s_time_gran = NTFS_TIME_GRAN; // 100 nsec
 	sb->s_xattr = ntfs_xattr_handlers;
+	sb->s_d_op = sbi->options->nocase ? &ntfs_dentry_ops : NULL;
 
 	sbi->options->nls = ntfs_load_nls(sbi->options->nls_name);
 	if (IS_ERR(sbi->options->nls)) {
diff --git a/fs/ntfs3/upcase.c b/fs/ntfs3/upcase.c
index b5e8256fd710d..7681eefacb4b4 100644
--- a/fs/ntfs3/upcase.c
+++ b/fs/ntfs3/upcase.c
@@ -102,3 +102,15 @@ case_insentive:
 	diff2 = l1 - l2;
 	return diff2 ? diff2 : diff1;
 }
+
+/* Helper function for ntfs_d_hash. */
+unsigned long ntfs_names_hash(const u16 *name, size_t len, const u16 *upcase,
+			      unsigned long hash)
+{
+	while (len--) {
+		unsigned int c = upcase_unicode_char(upcase, *name++);
+		hash = partial_name_hash(c, hash);
+	}
+
+	return hash;
+}
-- 
GitLab


From 43f03acbc1ec73beea9700f46f9cfdec388614d2 Mon Sep 17 00:00:00 2001
From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
Date: Fri, 23 Sep 2022 13:35:22 +0300
Subject: [PATCH 006/875] fs/ntfs3: Rename variables and add comment

After renaming we don't need to split code in two lines.

Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/frecord.c |  1 +
 fs/ntfs3/fslog.c   | 24 +++++++++++-------------
 2 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/fs/ntfs3/frecord.c b/fs/ntfs3/frecord.c
index b752d83cf4605..179b06762bdbf 100644
--- a/fs/ntfs3/frecord.c
+++ b/fs/ntfs3/frecord.c
@@ -3265,6 +3265,7 @@ int ni_write_inode(struct inode *inode, int sync, const char *hint)
 			modified = true;
 		}
 
+		/* std attribute is always in primary MFT record. */
 		if (modified)
 			ni->mi.dirty = true;
 
diff --git a/fs/ntfs3/fslog.c b/fs/ntfs3/fslog.c
index e7c494005122c..200e22b7871d0 100644
--- a/fs/ntfs3/fslog.c
+++ b/fs/ntfs3/fslog.c
@@ -3048,7 +3048,7 @@ static int do_action(struct ntfs_log *log, struct OPEN_ATTR_ENRTY *oe,
 	struct NEW_ATTRIBUTE_SIZES *new_sz;
 	struct ATTR_FILE_NAME *fname;
 	struct OpenAttr *oa, *oa2;
-	u32 nsize, t32, asize, used, esize, bmp_off, bmp_bits;
+	u32 nsize, t32, asize, used, esize, off, bits;
 	u16 id, id2;
 	u32 record_size = sbi->record_size;
 	u64 t64;
@@ -3635,30 +3635,28 @@ move_data:
 		break;
 
 	case SetBitsInNonresidentBitMap:
-		bmp_off =
-			le32_to_cpu(((struct BITMAP_RANGE *)data)->bitmap_off);
-		bmp_bits = le32_to_cpu(((struct BITMAP_RANGE *)data)->bits);
+		off = le32_to_cpu(((struct BITMAP_RANGE *)data)->bitmap_off);
+		bits = le32_to_cpu(((struct BITMAP_RANGE *)data)->bits);
 
-		if (cbo + (bmp_off + 7) / 8 > lco ||
-		    cbo + ((bmp_off + bmp_bits + 7) / 8) > lco) {
+		if (cbo + (off + 7) / 8 > lco ||
+		    cbo + ((off + bits + 7) / 8) > lco) {
 			goto dirty_vol;
 		}
 
-		__bitmap_set(Add2Ptr(buffer_le, roff), bmp_off, bmp_bits);
+		__bitmap_set(Add2Ptr(buffer_le, roff), off, bits);
 		a_dirty = true;
 		break;
 
 	case ClearBitsInNonresidentBitMap:
-		bmp_off =
-			le32_to_cpu(((struct BITMAP_RANGE *)data)->bitmap_off);
-		bmp_bits = le32_to_cpu(((struct BITMAP_RANGE *)data)->bits);
+		off = le32_to_cpu(((struct BITMAP_RANGE *)data)->bitmap_off);
+		bits = le32_to_cpu(((struct BITMAP_RANGE *)data)->bits);
 
-		if (cbo + (bmp_off + 7) / 8 > lco ||
-		    cbo + ((bmp_off + bmp_bits + 7) / 8) > lco) {
+		if (cbo + (off + 7) / 8 > lco ||
+		    cbo + ((off + bits + 7) / 8) > lco) {
 			goto dirty_vol;
 		}
 
-		__bitmap_clear(Add2Ptr(buffer_le, roff), bmp_off, bmp_bits);
+		__bitmap_clear(Add2Ptr(buffer_le, roff), off, bits);
 		a_dirty = true;
 		break;
 
-- 
GitLab


From 0b66046266690454dc04e6307bcff4a5605b42a1 Mon Sep 17 00:00:00 2001
From: edward lo <edward.lo@ambergroup.io>
Date: Mon, 1 Aug 2022 15:37:31 +0800
Subject: [PATCH 007/875] fs/ntfs3: Validate BOOT record_size

When the NTFS BOOT record_size field < 0, it represents a
shift value. However, there is no sanity check on the shift result
and the sbi->record_bits calculation through blksize_bits() assumes
the size always > 256, which could lead to NPD while mounting a
malformed NTFS image.

[  318.675159] BUG: kernel NULL pointer dereference, address: 0000000000000158
[  318.675682] #PF: supervisor read access in kernel mode
[  318.675869] #PF: error_code(0x0000) - not-present page
[  318.676246] PGD 0 P4D 0
[  318.676502] Oops: 0000 [#1] PREEMPT SMP NOPTI
[  318.676934] CPU: 0 PID: 259 Comm: mount Not tainted 5.19.0 #5
[  318.677289] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org 04/01/2014
[  318.678136] RIP: 0010:ni_find_attr+0x2d/0x1c0
[  318.678656] Code: 89 ca 4d 89 c7 41 56 41 55 41 54 41 89 cc 55 48 89 fd 53 48 89 d3 48 83 ec 20 65 48 8b 04 25 28 00 00 00 48 89 44 24 180
[  318.679848] RSP: 0018:ffffa6c8c0297bd8 EFLAGS: 00000246
[  318.680104] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000080
[  318.680790] RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000000000000
[  318.681679] RBP: 0000000000000000 R08: 0000000000000000 R09: 0000000000000000
[  318.682577] R10: 0000000000000000 R11: 0000000000000005 R12: 0000000000000080
[  318.683015] R13: ffff8d5582e68400 R14: 0000000000000100 R15: 0000000000000000
[  318.683618] FS:  00007fd9e1c81e40(0000) GS:ffff8d55fdc00000(0000) knlGS:0000000000000000
[  318.684280] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[  318.684651] CR2: 0000000000000158 CR3: 0000000002e1a000 CR4: 00000000000006f0
[  318.685623] Call Trace:
[  318.686607]  <TASK>
[  318.686872]  ? ntfs_alloc_inode+0x1a/0x60
[  318.687235]  attr_load_runs_vcn+0x2b/0xa0
[  318.687468]  mi_read+0xbb/0x250
[  318.687576]  ntfs_iget5+0x114/0xd90
[  318.687750]  ntfs_fill_super+0x588/0x11b0
[  318.687953]  ? put_ntfs+0x130/0x130
[  318.688065]  ? snprintf+0x49/0x70
[  318.688164]  ? put_ntfs+0x130/0x130
[  318.688256]  get_tree_bdev+0x16a/0x260
[  318.688407]  vfs_get_tree+0x20/0xb0
[  318.688519]  path_mount+0x2dc/0x9b0
[  318.688877]  do_mount+0x74/0x90
[  318.689142]  __x64_sys_mount+0x89/0xd0
[  318.689636]  do_syscall_64+0x3b/0x90
[  318.689998]  entry_SYSCALL_64_after_hwframe+0x63/0xcd
[  318.690318] RIP: 0033:0x7fd9e133c48a
[  318.690687] Code: 48 8b 0d 11 fa 2a 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 49 89 ca b8 a5 00 00 008
[  318.691357] RSP: 002b:00007ffd374406c8 EFLAGS: 00000202 ORIG_RAX: 00000000000000a5
[  318.691632] RAX: ffffffffffffffda RBX: 0000564d0b051080 RCX: 00007fd9e133c48a
[  318.691920] RDX: 0000564d0b051280 RSI: 0000564d0b051300 RDI: 0000564d0b0596a0
[  318.692123] RBP: 0000000000000000 R08: 0000564d0b0512a0 R09: 0000000000000020
[  318.692349] R10: 00000000c0ed0000 R11: 0000000000000202 R12: 0000564d0b0596a0
[  318.692673] R13: 0000564d0b051280 R14: 0000000000000000 R15: 00000000ffffffff
[  318.693007]  </TASK>
[  318.693271] Modules linked in:
[  318.693614] CR2: 0000000000000158
[  318.694446] ---[ end trace 0000000000000000 ]---
[  318.694779] RIP: 0010:ni_find_attr+0x2d/0x1c0
[  318.694952] Code: 89 ca 4d 89 c7 41 56 41 55 41 54 41 89 cc 55 48 89 fd 53 48 89 d3 48 83 ec 20 65 48 8b 04 25 28 00 00 00 48 89 44 24 180
[  318.696042] RSP: 0018:ffffa6c8c0297bd8 EFLAGS: 00000246
[  318.696531] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000080
[  318.698114] RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000000000000
[  318.699286] RBP: 0000000000000000 R08: 0000000000000000 R09: 0000000000000000
[  318.699795] R10: 0000000000000000 R11: 0000000000000005 R12: 0000000000000080
[  318.700236] R13: ffff8d5582e68400 R14: 0000000000000100 R15: 0000000000000000
[  318.700973] FS:  00007fd9e1c81e40(0000) GS:ffff8d55fdc00000(0000) knlGS:0000000000000000
[  318.701688] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[  318.702190] CR2: 0000000000000158 CR3: 0000000002e1a000 CR4: 00000000000006f0
[  318.726510] mount (259) used greatest stack depth: 13320 bytes left

This patch adds a sanity check.

Signed-off-by: edward lo <edward.lo@ambergroup.io>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/super.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/ntfs3/super.c b/fs/ntfs3/super.c
index d72a27abf1c83..af9b7947df64e 100644
--- a/fs/ntfs3/super.c
+++ b/fs/ntfs3/super.c
@@ -814,7 +814,7 @@ static int ntfs_init_from_boot(struct super_block *sb, u32 sector_size,
 						 : (u32)boot->record_size
 							   << sbi->cluster_bits;
 
-	if (record_size > MAXIMUM_BYTES_PER_MFT)
+	if (record_size > MAXIMUM_BYTES_PER_MFT || record_size < SECTOR_SIZE)
 		goto out;
 
 	sbi->record_bits = blksize_bits(record_size);
-- 
GitLab


From e19c6277652efba203af4ecd8eed4bd30a0054c9 Mon Sep 17 00:00:00 2001
From: edward lo <edward.lo@ambergroup.io>
Date: Mon, 1 Aug 2022 18:20:51 +0800
Subject: [PATCH 008/875] fs/ntfs3: Add overflow check for attribute size

The offset addition could overflow and pass the used size check given an
attribute with very large size (e.g., 0xffffff7f) while parsing MFT
attributes. This could lead to out-of-bound memory R/W if we try to
access the next attribute derived by Add2Ptr(attr, asize)

[   32.963847] BUG: unable to handle page fault for address: ffff956a83c76067
[   32.964301] #PF: supervisor read access in kernel mode
[   32.964526] #PF: error_code(0x0000) - not-present page
[   32.964893] PGD 4dc01067 P4D 4dc01067 PUD 0
[   32.965316] Oops: 0000 [#1] PREEMPT SMP NOPTI
[   32.965727] CPU: 0 PID: 243 Comm: mount Not tainted 5.19.0+ #6
[   32.966050] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org 04/01/2014
[   32.966628] RIP: 0010:mi_enum_attr+0x44/0x110
[   32.967239] Code: 89 f0 48 29 c8 48 89 c1 39 c7 0f 86 94 00 00 00 8b 56 04 83 fa 17 0f 86 88 00 00 00 89 d0 01 ca 48 01 f0 8d 4a 08 39 f9a
[   32.968101] RSP: 0018:ffffba15c06a7c38 EFLAGS: 00000283
[   32.968364] RAX: ffff956a83c76067 RBX: ffff956983c76050 RCX: 000000000000006f
[   32.968651] RDX: 0000000000000067 RSI: ffff956983c760e8 RDI: 00000000000001c8
[   32.968963] RBP: ffffba15c06a7c38 R08: 0000000000000064 R09: 00000000ffffff7f
[   32.969249] R10: 0000000000000007 R11: ffff956983c760e8 R12: ffff95698225e000
[   32.969870] R13: 0000000000000000 R14: ffffba15c06a7cd8 R15: ffff95698225e170
[   32.970655] FS:  00007fdab8189e40(0000) GS:ffff9569fdc00000(0000) knlGS:0000000000000000
[   32.971098] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[   32.971378] CR2: ffff956a83c76067 CR3: 0000000002c58000 CR4: 00000000000006f0
[   32.972098] Call Trace:
[   32.972842]  <TASK>
[   32.973341]  ni_enum_attr_ex+0xda/0xf0
[   32.974087]  ntfs_iget5+0x1db/0xde0
[   32.974386]  ? slab_post_alloc_hook+0x53/0x270
[   32.974778]  ? ntfs_fill_super+0x4c7/0x12a0
[   32.975115]  ntfs_fill_super+0x5d6/0x12a0
[   32.975336]  get_tree_bdev+0x175/0x270
[   32.975709]  ? put_ntfs+0x150/0x150
[   32.975956]  ntfs_fs_get_tree+0x15/0x20
[   32.976191]  vfs_get_tree+0x2a/0xc0
[   32.976374]  ? capable+0x19/0x20
[   32.976572]  path_mount+0x484/0xaa0
[   32.977025]  ? putname+0x57/0x70
[   32.977380]  do_mount+0x80/0xa0
[   32.977555]  __x64_sys_mount+0x8b/0xe0
[   32.978105]  do_syscall_64+0x3b/0x90
[   32.978830]  entry_SYSCALL_64_after_hwframe+0x63/0xcd
[   32.979311] RIP: 0033:0x7fdab72e948a
[   32.980015] Code: 48 8b 0d 11 fa 2a 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 49 89 ca b8 a5 00 00 008
[   32.981251] RSP: 002b:00007ffd15b87588 EFLAGS: 00000206 ORIG_RAX: 00000000000000a5
[   32.981832] RAX: ffffffffffffffda RBX: 0000557de0aaf060 RCX: 00007fdab72e948a
[   32.982234] RDX: 0000557de0aaf260 RSI: 0000557de0aaf2e0 RDI: 0000557de0ab7ce0
[   32.982714] RBP: 0000000000000000 R08: 0000557de0aaf280 R09: 0000000000000020
[   32.983046] R10: 00000000c0ed0000 R11: 0000000000000206 R12: 0000557de0ab7ce0
[   32.983494] R13: 0000557de0aaf260 R14: 0000000000000000 R15: 00000000ffffffff
[   32.984094]  </TASK>
[   32.984352] Modules linked in:
[   32.984753] CR2: ffff956a83c76067
[   32.985911] ---[ end trace 0000000000000000 ]---
[   32.986555] RIP: 0010:mi_enum_attr+0x44/0x110
[   32.987217] Code: 89 f0 48 29 c8 48 89 c1 39 c7 0f 86 94 00 00 00 8b 56 04 83 fa 17 0f 86 88 00 00 00 89 d0 01 ca 48 01 f0 8d 4a 08 39 f9a
[   32.988232] RSP: 0018:ffffba15c06a7c38 EFLAGS: 00000283
[   32.988532] RAX: ffff956a83c76067 RBX: ffff956983c76050 RCX: 000000000000006f
[   32.988916] RDX: 0000000000000067 RSI: ffff956983c760e8 RDI: 00000000000001c8
[   32.989356] RBP: ffffba15c06a7c38 R08: 0000000000000064 R09: 00000000ffffff7f
[   32.989994] R10: 0000000000000007 R11: ffff956983c760e8 R12: ffff95698225e000
[   32.990415] R13: 0000000000000000 R14: ffffba15c06a7cd8 R15: ffff95698225e170
[   32.991011] FS:  00007fdab8189e40(0000) GS:ffff9569fdc00000(0000) knlGS:0000000000000000
[   32.991524] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[   32.991936] CR2: ffff956a83c76067 CR3: 0000000002c58000 CR4: 00000000000006f0

This patch adds an overflow check

Signed-off-by: edward lo <edward.lo@ambergroup.io>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/record.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/fs/ntfs3/record.c b/fs/ntfs3/record.c
index c8741cfa421fe..66eb11e0965ef 100644
--- a/fs/ntfs3/record.c
+++ b/fs/ntfs3/record.c
@@ -220,6 +220,11 @@ struct ATTRIB *mi_enum_attr(struct mft_inode *mi, struct ATTRIB *attr)
 			return NULL;
 		}
 
+		if (off + asize < off) {
+			/* overflow check */
+			return NULL;
+		}
+
 		attr = Add2Ptr(attr, asize);
 		off += asize;
 	}
-- 
GitLab


From 6db620863f8528ed9a9aa5ad323b26554a17881d Mon Sep 17 00:00:00 2001
From: Edward Lo <edward.lo@ambergroup.io>
Date: Sat, 6 Aug 2022 00:47:27 +0800
Subject: [PATCH 009/875] fs/ntfs3: Validate data run offset

This adds sanity checks for data run offset. We should make sure data
run offset is legit before trying to unpack them, otherwise we may
encounter use-after-free or some unexpected memory access behaviors.

[   82.940342] BUG: KASAN: use-after-free in run_unpack+0x2e3/0x570
[   82.941180] Read of size 1 at addr ffff888008a8487f by task mount/240
[   82.941670]
[   82.942069] CPU: 0 PID: 240 Comm: mount Not tainted 5.19.0+ #15
[   82.942482] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org 04/01/2014
[   82.943720] Call Trace:
[   82.944204]  <TASK>
[   82.944471]  dump_stack_lvl+0x49/0x63
[   82.944908]  print_report.cold+0xf5/0x67b
[   82.945141]  ? __wait_on_bit+0x106/0x120
[   82.945750]  ? run_unpack+0x2e3/0x570
[   82.946626]  kasan_report+0xa7/0x120
[   82.947046]  ? run_unpack+0x2e3/0x570
[   82.947280]  __asan_load1+0x51/0x60
[   82.947483]  run_unpack+0x2e3/0x570
[   82.947709]  ? memcpy+0x4e/0x70
[   82.947927]  ? run_pack+0x7a0/0x7a0
[   82.948158]  run_unpack_ex+0xad/0x3f0
[   82.948399]  ? mi_enum_attr+0x14a/0x200
[   82.948717]  ? run_unpack+0x570/0x570
[   82.949072]  ? ni_enum_attr_ex+0x1b2/0x1c0
[   82.949332]  ? ni_fname_type.part.0+0xd0/0xd0
[   82.949611]  ? mi_read+0x262/0x2c0
[   82.949970]  ? ntfs_cmp_names_cpu+0x125/0x180
[   82.950249]  ntfs_iget5+0x632/0x1870
[   82.950621]  ? ntfs_get_block_bmap+0x70/0x70
[   82.951192]  ? evict+0x223/0x280
[   82.951525]  ? iput.part.0+0x286/0x320
[   82.951969]  ntfs_fill_super+0x1321/0x1e20
[   82.952436]  ? put_ntfs+0x1d0/0x1d0
[   82.952822]  ? vsprintf+0x20/0x20
[   82.953188]  ? mutex_unlock+0x81/0xd0
[   82.953379]  ? set_blocksize+0x95/0x150
[   82.954001]  get_tree_bdev+0x232/0x370
[   82.954438]  ? put_ntfs+0x1d0/0x1d0
[   82.954700]  ntfs_fs_get_tree+0x15/0x20
[   82.955049]  vfs_get_tree+0x4c/0x130
[   82.955292]  path_mount+0x645/0xfd0
[   82.955615]  ? putname+0x80/0xa0
[   82.955955]  ? finish_automount+0x2e0/0x2e0
[   82.956310]  ? kmem_cache_free+0x110/0x390
[   82.956723]  ? putname+0x80/0xa0
[   82.957023]  do_mount+0xd6/0xf0
[   82.957411]  ? path_mount+0xfd0/0xfd0
[   82.957638]  ? __kasan_check_write+0x14/0x20
[   82.957948]  __x64_sys_mount+0xca/0x110
[   82.958310]  do_syscall_64+0x3b/0x90
[   82.958719]  entry_SYSCALL_64_after_hwframe+0x63/0xcd
[   82.959341] RIP: 0033:0x7fd0d1ce948a
[   82.960193] Code: 48 8b 0d 11 fa 2a 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 49 89 ca b8 a5 00 00 008
[   82.961532] RSP: 002b:00007ffe59ff69a8 EFLAGS: 00000202 ORIG_RAX: 00000000000000a5
[   82.962527] RAX: ffffffffffffffda RBX: 0000564dcc107060 RCX: 00007fd0d1ce948a
[   82.963266] RDX: 0000564dcc107260 RSI: 0000564dcc1072e0 RDI: 0000564dcc10fce0
[   82.963686] RBP: 0000000000000000 R08: 0000564dcc107280 R09: 0000000000000020
[   82.964272] R10: 00000000c0ed0000 R11: 0000000000000202 R12: 0000564dcc10fce0
[   82.964785] R13: 0000564dcc107260 R14: 0000000000000000 R15: 00000000ffffffff

Signed-off-by: Edward Lo <edward.lo@ambergroup.io>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/attrib.c   | 13 +++++++++++++
 fs/ntfs3/attrlist.c |  5 +++++
 fs/ntfs3/frecord.c  | 14 ++++++++++++++
 fs/ntfs3/fslog.c    |  9 +++++++++
 fs/ntfs3/inode.c    |  5 +++++
 5 files changed, 46 insertions(+)

diff --git a/fs/ntfs3/attrib.c b/fs/ntfs3/attrib.c
index 71f870d497aed..0d354560d3235 100644
--- a/fs/ntfs3/attrib.c
+++ b/fs/ntfs3/attrib.c
@@ -101,6 +101,10 @@ static int attr_load_runs(struct ATTRIB *attr, struct ntfs_inode *ni,
 
 	asize = le32_to_cpu(attr->size);
 	run_off = le16_to_cpu(attr->nres.run_off);
+
+	if (run_off > asize)
+		return -EINVAL;
+
 	err = run_unpack_ex(run, ni->mi.sbi, ni->mi.rno, svcn, evcn,
 			    vcn ? *vcn : svcn, Add2Ptr(attr, run_off),
 			    asize - run_off);
@@ -1232,6 +1236,10 @@ int attr_load_runs_vcn(struct ntfs_inode *ni, enum ATTR_TYPE type,
 	}
 
 	ro = le16_to_cpu(attr->nres.run_off);
+
+	if (ro > le32_to_cpu(attr->size))
+		return -EINVAL;
+
 	err = run_unpack_ex(run, ni->mi.sbi, ni->mi.rno, svcn, evcn, svcn,
 			    Add2Ptr(attr, ro), le32_to_cpu(attr->size) - ro);
 	if (err < 0)
@@ -1901,6 +1909,11 @@ int attr_collapse_range(struct ntfs_inode *ni, u64 vbo, u64 bytes)
 			u16 le_sz;
 			u16 roff = le16_to_cpu(attr->nres.run_off);
 
+			if (roff > le32_to_cpu(attr->size)) {
+				err = -EINVAL;
+				goto out;
+			}
+
 			run_unpack_ex(RUN_DEALLOCATE, sbi, ni->mi.rno, svcn,
 				      evcn1 - 1, svcn, Add2Ptr(attr, roff),
 				      le32_to_cpu(attr->size) - roff);
diff --git a/fs/ntfs3/attrlist.c b/fs/ntfs3/attrlist.c
index bad6d8a849a24..c0c6bcbc8c05c 100644
--- a/fs/ntfs3/attrlist.c
+++ b/fs/ntfs3/attrlist.c
@@ -68,6 +68,11 @@ int ntfs_load_attr_list(struct ntfs_inode *ni, struct ATTRIB *attr)
 
 		run_init(&ni->attr_list.run);
 
+		if (run_off > le32_to_cpu(attr->size)) {
+			err = -EINVAL;
+			goto out;
+		}
+
 		err = run_unpack_ex(&ni->attr_list.run, ni->mi.sbi, ni->mi.rno,
 				    0, le64_to_cpu(attr->nres.evcn), 0,
 				    Add2Ptr(attr, run_off),
diff --git a/fs/ntfs3/frecord.c b/fs/ntfs3/frecord.c
index 179b06762bdbf..70a80f9412f77 100644
--- a/fs/ntfs3/frecord.c
+++ b/fs/ntfs3/frecord.c
@@ -568,6 +568,12 @@ static int ni_repack(struct ntfs_inode *ni)
 		}
 
 		roff = le16_to_cpu(attr->nres.run_off);
+
+		if (roff > le32_to_cpu(attr->size)) {
+			err = -EINVAL;
+			break;
+		}
+
 		err = run_unpack(&run, sbi, ni->mi.rno, svcn, evcn, svcn,
 				 Add2Ptr(attr, roff),
 				 le32_to_cpu(attr->size) - roff);
@@ -1589,6 +1595,9 @@ int ni_delete_all(struct ntfs_inode *ni)
 		asize = le32_to_cpu(attr->size);
 		roff = le16_to_cpu(attr->nres.run_off);
 
+		if (roff > asize)
+			return -EINVAL;
+
 		/* run==1 means unpack and deallocate. */
 		run_unpack_ex(RUN_DEALLOCATE, sbi, ni->mi.rno, svcn, evcn, svcn,
 			      Add2Ptr(attr, roff), asize - roff);
@@ -2291,6 +2300,11 @@ remove_wof:
 		asize = le32_to_cpu(attr->size);
 		roff = le16_to_cpu(attr->nres.run_off);
 
+		if (roff > asize) {
+			err = -EINVAL;
+			goto out;
+		}
+
 		/*run==1  Means unpack and deallocate. */
 		run_unpack_ex(RUN_DEALLOCATE, sbi, ni->mi.rno, svcn, evcn, svcn,
 			      Add2Ptr(attr, roff), asize - roff);
diff --git a/fs/ntfs3/fslog.c b/fs/ntfs3/fslog.c
index 200e22b7871d0..d94c071324a8f 100644
--- a/fs/ntfs3/fslog.c
+++ b/fs/ntfs3/fslog.c
@@ -2727,6 +2727,9 @@ static inline bool check_attr(const struct MFT_REC *rec,
 			return false;
 		}
 
+		if (run_off > asize)
+			return false;
+
 		if (run_unpack(NULL, sbi, 0, svcn, evcn, svcn,
 			       Add2Ptr(attr, run_off), asize - run_off) < 0) {
 			return false;
@@ -4769,6 +4772,12 @@ fake_attr:
 		u16 roff = le16_to_cpu(attr->nres.run_off);
 		CLST svcn = le64_to_cpu(attr->nres.svcn);
 
+		if (roff > t32) {
+			kfree(oa->attr);
+			oa->attr = NULL;
+			goto fake_attr;
+		}
+
 		err = run_unpack(&oa->run0, sbi, inode->i_ino, svcn,
 				 le64_to_cpu(attr->nres.evcn), svcn,
 				 Add2Ptr(attr, roff), t32 - roff);
diff --git a/fs/ntfs3/inode.c b/fs/ntfs3/inode.c
index 40b8565815a24..9a4185fa05adb 100644
--- a/fs/ntfs3/inode.c
+++ b/fs/ntfs3/inode.c
@@ -364,6 +364,11 @@ next_attr:
 attr_unpack_run:
 	roff = le16_to_cpu(attr->nres.run_off);
 
+	if (roff > asize) {
+		err = -EINVAL;
+		goto out;
+	}
+
 	t64 = le64_to_cpu(attr->nres.svcn);
 	err = run_unpack_ex(run, sbi, ino, t64, le64_to_cpu(attr->nres.evcn),
 			    t64, Add2Ptr(attr, roff), asize - roff);
-- 
GitLab


From 2681631c29739509eec59cc0b34e977bb04c6cf1 Mon Sep 17 00:00:00 2001
From: Edward Lo <edward.lo@ambergroup.io>
Date: Sun, 7 Aug 2022 01:05:18 +0800
Subject: [PATCH 010/875] fs/ntfs3: Add null pointer check to
 attr_load_runs_vcn

Some metadata files are handled before MFT. This adds a null pointer
check for some corner cases that could lead to NPD while reading these
metadata files for a malformed NTFS image.

[  240.190827] BUG: kernel NULL pointer dereference, address: 0000000000000158
[  240.191583] #PF: supervisor read access in kernel mode
[  240.191956] #PF: error_code(0x0000) - not-present page
[  240.192391] PGD 0 P4D 0
[  240.192897] Oops: 0000 [#1] PREEMPT SMP KASAN NOPTI
[  240.193805] CPU: 0 PID: 242 Comm: mount Tainted: G    B             5.19.0+ #17
[  240.194477] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org 04/01/2014
[  240.195152] RIP: 0010:ni_find_attr+0xae/0x300
[  240.195679] Code: c8 48 c7 45 88 c0 4e 5e 86 c7 00 f1 f1 f1 f1 c7 40 04 00 f3 f3 f3 65 48 8b 04 25 28 00 00 00 48 89 45 d0 31 c0 e8 e2 d9f
[  240.196642] RSP: 0018:ffff88800812f690 EFLAGS: 00000286
[  240.197019] RAX: 0000000000000001 RBX: 0000000000000000 RCX: ffffffff85ef037a
[  240.197523] RDX: 0000000000000001 RSI: 0000000000000008 RDI: ffffffff88e95f60
[  240.197877] RBP: ffff88800812f738 R08: 0000000000000001 R09: fffffbfff11d2bed
[  240.198292] R10: ffffffff88e95f67 R11: fffffbfff11d2bec R12: 0000000000000000
[  240.198647] R13: 0000000000000080 R14: 0000000000000000 R15: 0000000000000000
[  240.199410] FS:  00007f233c33be40(0000) GS:ffff888058200000(0000) knlGS:0000000000000000
[  240.199895] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[  240.200314] CR2: 0000000000000158 CR3: 0000000004d32000 CR4: 00000000000006f0
[  240.200839] Call Trace:
[  240.201104]  <TASK>
[  240.201502]  ? ni_load_mi+0x80/0x80
[  240.202297]  ? ___slab_alloc+0x465/0x830
[  240.202614]  attr_load_runs_vcn+0x8c/0x1a0
[  240.202886]  ? __kasan_slab_alloc+0x32/0x90
[  240.203157]  ? attr_data_write_resident+0x250/0x250
[  240.203543]  mi_read+0x133/0x2c0
[  240.203785]  mi_get+0x70/0x140
[  240.204012]  ni_load_mi_ex+0xfa/0x190
[  240.204346]  ? ni_std5+0x90/0x90
[  240.204588]  ? __kasan_kmalloc+0x88/0xb0
[  240.204859]  ni_enum_attr_ex+0xf1/0x1c0
[  240.205107]  ? ni_fname_type.part.0+0xd0/0xd0
[  240.205600]  ? ntfs_load_attr_list+0xbe/0x300
[  240.205864]  ? ntfs_cmp_names_cpu+0x125/0x180
[  240.206157]  ntfs_iget5+0x56c/0x1870
[  240.206510]  ? ntfs_get_block_bmap+0x70/0x70
[  240.206776]  ? __kasan_kmalloc+0x88/0xb0
[  240.207030]  ? set_blocksize+0x95/0x150
[  240.207545]  ntfs_fill_super+0xb8f/0x1e20
[  240.207839]  ? put_ntfs+0x1d0/0x1d0
[  240.208069]  ? vsprintf+0x20/0x20
[  240.208467]  ? mutex_unlock+0x81/0xd0
[  240.208846]  ? set_blocksize+0x95/0x150
[  240.209221]  get_tree_bdev+0x232/0x370
[  240.209804]  ? put_ntfs+0x1d0/0x1d0
[  240.210519]  ntfs_fs_get_tree+0x15/0x20
[  240.210991]  vfs_get_tree+0x4c/0x130
[  240.211455]  path_mount+0x645/0xfd0
[  240.211806]  ? putname+0x80/0xa0
[  240.212112]  ? finish_automount+0x2e0/0x2e0
[  240.212559]  ? kmem_cache_free+0x110/0x390
[  240.212906]  ? putname+0x80/0xa0
[  240.213329]  do_mount+0xd6/0xf0
[  240.213829]  ? path_mount+0xfd0/0xfd0
[  240.214246]  ? __kasan_check_write+0x14/0x20
[  240.214774]  __x64_sys_mount+0xca/0x110
[  240.215080]  do_syscall_64+0x3b/0x90
[  240.215442]  entry_SYSCALL_64_after_hwframe+0x63/0xcd
[  240.215811] RIP: 0033:0x7f233b4e948a
[  240.216104] Code: 48 8b 0d 11 fa 2a 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 49 89 ca b8 a5 00 00 008
[  240.217615] RSP: 002b:00007fff02211ec8 EFLAGS: 00000202 ORIG_RAX: 00000000000000a5
[  240.218718] RAX: ffffffffffffffda RBX: 0000561cdc35b060 RCX: 00007f233b4e948a
[  240.219556] RDX: 0000561cdc35b260 RSI: 0000561cdc35b2e0 RDI: 0000561cdc363af0
[  240.219975] RBP: 0000000000000000 R08: 0000561cdc35b280 R09: 0000000000000020
[  240.220403] R10: 00000000c0ed0000 R11: 0000000000000202 R12: 0000561cdc363af0
[  240.220803] R13: 0000561cdc35b260 R14: 0000000000000000 R15: 00000000ffffffff
[  240.221256]  </TASK>
[  240.221567] Modules linked in:
[  240.222028] CR2: 0000000000000158
[  240.223291] ---[ end trace 0000000000000000 ]---
[  240.223669] RIP: 0010:ni_find_attr+0xae/0x300
[  240.224058] Code: c8 48 c7 45 88 c0 4e 5e 86 c7 00 f1 f1 f1 f1 c7 40 04 00 f3 f3 f3 65 48 8b 04 25 28 00 00 00 48 89 45 d0 31 c0 e8 e2 d9f
[  240.225033] RSP: 0018:ffff88800812f690 EFLAGS: 00000286
[  240.225968] RAX: 0000000000000001 RBX: 0000000000000000 RCX: ffffffff85ef037a
[  240.226624] RDX: 0000000000000001 RSI: 0000000000000008 RDI: ffffffff88e95f60
[  240.227307] RBP: ffff88800812f738 R08: 0000000000000001 R09: fffffbfff11d2bed
[  240.227816] R10: ffffffff88e95f67 R11: fffffbfff11d2bec R12: 0000000000000000
[  240.228330] R13: 0000000000000080 R14: 0000000000000000 R15: 0000000000000000
[  240.228729] FS:  00007f233c33be40(0000) GS:ffff888058200000(0000) knlGS:0000000000000000
[  240.229281] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[  240.230298] CR2: 0000000000000158 CR3: 0000000004d32000 CR4: 00000000000006f0

Signed-off-by: Edward Lo <edward.lo@ambergroup.io>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/attrib.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/fs/ntfs3/attrib.c b/fs/ntfs3/attrib.c
index 0d354560d3235..578c2bcfb1d93 100644
--- a/fs/ntfs3/attrib.c
+++ b/fs/ntfs3/attrib.c
@@ -1221,6 +1221,11 @@ int attr_load_runs_vcn(struct ntfs_inode *ni, enum ATTR_TYPE type,
 	CLST svcn, evcn;
 	u16 ro;
 
+	if (!ni) {
+		/* Is record corrupted? */
+		return -ENOENT;
+	}
+
 	attr = ni_find_attr(ni, NULL, NULL, type, name, name_len, &vcn, NULL);
 	if (!attr) {
 		/* Is record corrupted? */
-- 
GitLab


From f27b92ec0926efa3eadcebb97a90faba12e16041 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marc=20Aur=C3=A8le=20La=20France?= <tsi@tuyoix.net>
Date: Wed, 10 Aug 2022 14:28:04 -0600
Subject: [PATCH 011/875] fs/ntfs3: Fix [df]mask display in /proc/mounts
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

ntfs3's dmask and fmask mount options are 16-bit quantities but are displayed
as 1-extended 32-bit values in /proc/mounts.  Fix this by circumventing
integer promotion.

Signed-off-by: Marc Aurèle La France <tsi@tuyoix.net>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/super.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/fs/ntfs3/super.c b/fs/ntfs3/super.c
index af9b7947df64e..27a36a0b08ec9 100644
--- a/fs/ntfs3/super.c
+++ b/fs/ntfs3/super.c
@@ -544,9 +544,9 @@ static int ntfs_show_options(struct seq_file *m, struct dentry *root)
 	seq_printf(m, ",gid=%u",
 		  from_kgid_munged(user_ns, opts->fs_gid));
 	if (opts->fmask)
-		seq_printf(m, ",fmask=%04o", ~opts->fs_fmask_inv);
+		seq_printf(m, ",fmask=%04o", opts->fs_fmask_inv ^ 0xffff);
 	if (opts->dmask)
-		seq_printf(m, ",dmask=%04o", ~opts->fs_dmask_inv);
+		seq_printf(m, ",dmask=%04o", opts->fs_dmask_inv ^ 0xffff);
 	if (opts->nls)
 		seq_printf(m, ",iocharset=%s", opts->nls->charset);
 	else
-- 
GitLab


From 6d5c9e79b726cc473d40e9cb60976dbe8e669624 Mon Sep 17 00:00:00 2001
From: Alon Zahavi <zahavi.alon@gmail.com>
Date: Mon, 15 Aug 2022 14:07:12 +0300
Subject: [PATCH 012/875] fs/ntfs3: Fix attr_punch_hole() null pointer
 derenference

The bug occours due to a misuse of `attr` variable instead of `attr_b`.
`attr` is being initialized as NULL, then being derenfernced
as `attr->res.data_size`.

This bug causes a crash of the ntfs3 driver itself,
If compiled directly to the kernel, it crashes the whole system.

Signed-off-by: Alon Zahavi <zahavi.alon@gmail.com>
Co-developed-by: Tal Lossos <tallossos@gmail.com>
Signed-off-by: Tal Lossos <tallossos@gmail.com>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/attrib.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/ntfs3/attrib.c b/fs/ntfs3/attrib.c
index 578c2bcfb1d93..63169529b52c4 100644
--- a/fs/ntfs3/attrib.c
+++ b/fs/ntfs3/attrib.c
@@ -2038,7 +2038,7 @@ int attr_punch_hole(struct ntfs_inode *ni, u64 vbo, u64 bytes, u32 *frame_size)
 		return -ENOENT;
 
 	if (!attr_b->non_res) {
-		u32 data_size = le32_to_cpu(attr->res.data_size);
+		u32 data_size = le32_to_cpu(attr_b->res.data_size);
 		u32 from, to;
 
 		if (vbo > data_size)
-- 
GitLab


From 92f017c4aee6e2bb79593adeacccbea3afe62223 Mon Sep 17 00:00:00 2001
From: Kenneth Lee <klee33@uw.edu>
Date: Thu, 18 Aug 2022 22:51:17 -0700
Subject: [PATCH 013/875] fs/ntfs3: Use kmalloc_array for allocating multiple
 elements

Prefer using kmalloc_array(a, b) over kmalloc(a * b) as this
improves semantics since kmalloc is intended for allocating an
array of memory.

Signed-off-by: Kenneth Lee <klee33@uw.edu>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/bitmap.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/ntfs3/bitmap.c b/fs/ntfs3/bitmap.c
index 5d44ceac855b7..1675c9a697884 100644
--- a/fs/ntfs3/bitmap.c
+++ b/fs/ntfs3/bitmap.c
@@ -1324,7 +1324,7 @@ int wnd_extend(struct wnd_bitmap *wnd, size_t new_bits)
 		new_last = wbits;
 
 	if (new_wnd != wnd->nwnd) {
-		new_free = kmalloc(new_wnd * sizeof(u16), GFP_NOFS);
+		new_free = kmalloc_array(new_wnd, sizeof(u16), GFP_NOFS);
 		if (!new_free)
 			return -ENOMEM;
 
-- 
GitLab


From 51e76a232f8c037f1d9e9922edc25b003d5f3414 Mon Sep 17 00:00:00 2001
From: Shigeru Yoshida <syoshida@redhat.com>
Date: Tue, 23 Aug 2022 19:32:05 +0900
Subject: [PATCH 014/875] fs/ntfs3: Fix memory leak on ntfs_fill_super() error
 path

syzbot reported kmemleak as below:

BUG: memory leak
unreferenced object 0xffff8880122f1540 (size 32):
  comm "a.out", pid 6664, jiffies 4294939771 (age 25.500s)
  hex dump (first 32 bytes):
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
    00 00 00 00 00 00 00 00 ed ff ed ff 00 00 00 00  ................
  backtrace:
    [<ffffffff81b16052>] ntfs_init_fs_context+0x22/0x1c0
    [<ffffffff8164aaa7>] alloc_fs_context+0x217/0x430
    [<ffffffff81626dd4>] path_mount+0x704/0x1080
    [<ffffffff81627e7c>] __x64_sys_mount+0x18c/0x1d0
    [<ffffffff84593e14>] do_syscall_64+0x34/0xb0
    [<ffffffff84600087>] entry_SYSCALL_64_after_hwframe+0x63/0xcd

This patch fixes this issue by freeing mount options on error path of
ntfs_fill_super().

Reported-by: syzbot+9d67170b20e8f94351c8@syzkaller.appspotmail.com
Signed-off-by: Shigeru Yoshida <syoshida@redhat.com>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/super.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/fs/ntfs3/super.c b/fs/ntfs3/super.c
index 27a36a0b08ec9..569f38a2a51fc 100644
--- a/fs/ntfs3/super.c
+++ b/fs/ntfs3/super.c
@@ -1307,6 +1307,7 @@ out:
 	 * Free resources here.
 	 * ntfs_fs_free will be called with fc->s_fs_info = NULL
 	 */
+	put_mount_options(sbi->options);
 	put_ntfs(sbi);
 	sb->s_fs_info = NULL;
 
-- 
GitLab


From caad9dd8792a2622737b7273cb34835fd9536cd2 Mon Sep 17 00:00:00 2001
From: Shigeru Yoshida <syoshida@redhat.com>
Date: Tue, 23 Aug 2022 23:46:25 +0900
Subject: [PATCH 015/875] fs/ntfs3: Avoid UBSAN error on
 true_sectors_per_clst()

syzbot reported UBSAN error as below:

[   76.901829][ T6677] ================================================================================
[   76.903908][ T6677] UBSAN: shift-out-of-bounds in fs/ntfs3/super.c:675:13
[   76.905363][ T6677] shift exponent -247 is negative

This patch avoid this error.

Link: https://syzkaller.appspot.com/bug?id=b0299c09a14aababf0f1c862dd4ebc8ab9eb0179
Fixes: a3b774342fa7 (fs/ntfs3: validate BOOT sectors_per_clusters)
Cc: Author: Randy Dunlap <rdunlap@infradead.org>
Reported-by: syzbot+35b87c668935bb55e666@syzkaller.appspotmail.com
Signed-off-by: Shigeru Yoshida <syoshida@redhat.com>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/super.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/ntfs3/super.c b/fs/ntfs3/super.c
index 569f38a2a51fc..ff70e2a5f3acb 100644
--- a/fs/ntfs3/super.c
+++ b/fs/ntfs3/super.c
@@ -697,7 +697,7 @@ static u32 true_sectors_per_clst(const struct NTFS_BOOT *boot)
 	if (boot->sectors_per_clusters <= 0x80)
 		return boot->sectors_per_clusters;
 	if (boot->sectors_per_clusters >= 0xf4) /* limit shift to 2MB max */
-		return 1U << (0 - boot->sectors_per_clusters);
+		return 1U << -(s8)boot->sectors_per_clusters;
 	return -EINVAL;
 }
 
-- 
GitLab


From 0a4e7ce6bc03389d75bc62eb6de66cb5efc55839 Mon Sep 17 00:00:00 2001
From: Daniel Pinto <danielpinto52@gmail.com>
Date: Wed, 7 Sep 2022 02:45:13 +0100
Subject: [PATCH 016/875] fs/ntfs3: Fix junction point resolution

The ntfs3 file system driver does not convert the target path of
junction points to a proper Linux path. As junction points targets
are always absolute paths (they start with a drive letter), all
junctions will result in broken links.

Translate the targets of junction points to relative paths so they
point to directories inside the mounted volume. Note that Windows
allows junction points to reference directories in another drive.
However, as there is no way to know which drive the junctions refer
to, we assume they always target the same file system they are in.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=214833
Signed-off-by: Daniel Pinto <danielpinto52@gmail.com>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/inode.c | 103 ++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 101 insertions(+), 2 deletions(-)

diff --git a/fs/ntfs3/inode.c b/fs/ntfs3/inode.c
index 9a4185fa05adb..b1832b482c175 100644
--- a/fs/ntfs3/inode.c
+++ b/fs/ntfs3/inode.c
@@ -1758,7 +1758,101 @@ void ntfs_evict_inode(struct inode *inode)
 	ni_clear(ntfs_i(inode));
 }
 
-static noinline int ntfs_readlink_hlp(struct inode *inode, char *buffer,
+/*
+ * ntfs_translate_junction
+ *
+ * Translate a Windows junction target to the Linux equivalent.
+ * On junctions, targets are always absolute (they include the drive
+ * letter). We have no way of knowing if the target is for the current
+ * mounted device or not so we just assume it is.
+ */
+static int ntfs_translate_junction(const struct super_block *sb,
+				   const struct dentry *link_de, char *target,
+				   int target_len, int target_max)
+{
+	int tl_len, err = target_len;
+	char *link_path_buffer = NULL, *link_path;
+	char *translated = NULL;
+	char *target_start;
+	int copy_len;
+
+	link_path_buffer = kmalloc(PATH_MAX, GFP_NOFS);
+	if (!link_path_buffer) {
+		err = -ENOMEM;
+		goto out;
+	}
+	/* Get link path, relative to mount point */
+	link_path = dentry_path_raw(link_de, link_path_buffer, PATH_MAX);
+	if (IS_ERR(link_path)) {
+		ntfs_err(sb, "Error getting link path");
+		err = -EINVAL;
+		goto out;
+	}
+
+	translated = kmalloc(PATH_MAX, GFP_NOFS);
+	if (!translated) {
+		err = -ENOMEM;
+		goto out;
+	}
+
+	/* Make translated path a relative path to mount point */
+	strcpy(translated, "./");
+	++link_path;	/* Skip leading / */
+	for (tl_len = sizeof("./") - 1; *link_path; ++link_path) {
+		if (*link_path == '/') {
+			if (PATH_MAX - tl_len < sizeof("../")) {
+				ntfs_err(sb, "Link path %s has too many components",
+					 link_path);
+				err = -EINVAL;
+				goto out;
+			}
+			strcpy(translated + tl_len, "../");
+			tl_len += sizeof("../") - 1;
+		}
+	}
+
+	/* Skip drive letter */
+	target_start = target;
+	while (*target_start && *target_start != ':')
+		++target_start;
+
+	if (!*target_start) {
+		ntfs_err(sb, "Link target (%s) missing drive separator", target);
+		err = -EINVAL;
+		goto out;
+	}
+
+	/* Skip drive separator and leading /, if exists */
+	target_start += 1 + (target_start[1] == '/');
+	copy_len = target_len - (target_start - target);
+
+	if (PATH_MAX - tl_len <= copy_len) {
+		ntfs_err(sb, "Link target %s too large for buffer (%d <= %d)",
+			 target_start, PATH_MAX - tl_len, copy_len);
+		err = -EINVAL;
+		goto out;
+	}
+
+	/* translated path has a trailing / and target_start does not */
+	strcpy(translated + tl_len, target_start);
+	tl_len += copy_len;
+	if (target_max <= tl_len) {
+		ntfs_err(sb, "Target path %s too large for buffer (%d <= %d)",
+			 translated, target_max, tl_len);
+		err = -EINVAL;
+		goto out;
+	}
+	strcpy(target, translated);
+	err = tl_len;
+
+out:
+	kfree(link_path_buffer);
+	kfree(translated);
+	return err;
+}
+
+static noinline int ntfs_readlink_hlp(const struct dentry *link_de,
+				      struct inode *inode, char *buffer,
 				      int buflen)
 {
 	int i, err = -EINVAL;
@@ -1901,6 +1995,11 @@ static noinline int ntfs_readlink_hlp(struct inode *inode, char *buffer,
 
 	/* Always set last zero. */
 	buffer[err] = 0;
+
+	/* If this is a junction, translate the link target. */
+	if (rp->ReparseTag == IO_REPARSE_TAG_MOUNT_POINT)
+		err = ntfs_translate_junction(sb, link_de, buffer, err, buflen);
+
 out:
 	kfree(to_free);
 	return err;
@@ -1919,7 +2018,7 @@ static const char *ntfs_get_link(struct dentry *de, struct inode *inode,
 	if (!ret)
 		return ERR_PTR(-ENOMEM);
 
-	err = ntfs_readlink_hlp(inode, ret, PAGE_SIZE);
+	err = ntfs_readlink_hlp(de, inode, ret, PAGE_SIZE);
 	if (err < 0) {
 		kfree(ret);
 		return ERR_PTR(err);
-- 
GitLab


From c1ca8ef0262b25493631ecbd9cb8c9893e1481a1 Mon Sep 17 00:00:00 2001
From: Edward Lo <edward.lo@ambergroup.io>
Date: Fri, 9 Sep 2022 09:03:10 +0800
Subject: [PATCH 017/875] fs/ntfs3: Add null pointer check for inode operations

This adds a sanity check for the i_op pointer of the inode which is
returned after reading Root directory MFT record. We should check the
i_op is valid before trying to create the root dentry, otherwise we may
encounter a NPD while mounting a image with a funny Root directory MFT
record.

[  114.484325] BUG: kernel NULL pointer dereference, address: 0000000000000008
[  114.484811] #PF: supervisor read access in kernel mode
[  114.485084] #PF: error_code(0x0000) - not-present page
[  114.485606] PGD 0 P4D 0
[  114.485975] Oops: 0000 [#1] PREEMPT SMP KASAN NOPTI
[  114.486570] CPU: 0 PID: 237 Comm: mount Tainted: G    B              6.0.0-rc4 #28
[  114.486977] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org 04/01/2014
[  114.488169] RIP: 0010:d_flags_for_inode+0xe0/0x110
[  114.488816] Code: 24 f7 ff 49 83 3e 00 74 41 41 83 cd 02 66 44 89 6b 02 eb 92 48 8d 7b 20 e8 6d 24 f7 ff 4c 8b 73 20 49 8d 7e 08 e8 60 241
[  114.490326] RSP: 0018:ffff8880065e7aa8 EFLAGS: 00000296
[  114.490695] RAX: 0000000000000001 RBX: ffff888008ccd750 RCX: ffffffff84af2aea
[  114.490986] RDX: 0000000000000001 RSI: 0000000000000008 RDI: ffffffff87abd020
[  114.491364] RBP: ffff8880065e7ac8 R08: 0000000000000001 R09: fffffbfff0f57a05
[  114.491675] R10: ffffffff87abd027 R11: fffffbfff0f57a04 R12: 0000000000000000
[  114.491954] R13: 0000000000000008 R14: 0000000000000000 R15: ffff888008ccd750
[  114.492397] FS:  00007fdc8a627e40(0000) GS:ffff888058200000(0000) knlGS:0000000000000000
[  114.492797] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[  114.493150] CR2: 0000000000000008 CR3: 00000000013ba000 CR4: 00000000000006f0
[  114.493671] Call Trace:
[  114.493890]  <TASK>
[  114.494075]  __d_instantiate+0x24/0x1c0
[  114.494505]  d_instantiate.part.0+0x35/0x50
[  114.494754]  d_make_root+0x53/0x80
[  114.494998]  ntfs_fill_super+0x1232/0x1b50
[  114.495260]  ? put_ntfs+0x1d0/0x1d0
[  114.495499]  ? vsprintf+0x20/0x20
[  114.495723]  ? set_blocksize+0x95/0x150
[  114.495964]  get_tree_bdev+0x232/0x370
[  114.496272]  ? put_ntfs+0x1d0/0x1d0
[  114.496502]  ntfs_fs_get_tree+0x15/0x20
[  114.496859]  vfs_get_tree+0x4c/0x130
[  114.497099]  path_mount+0x654/0xfe0
[  114.497507]  ? putname+0x80/0xa0
[  114.497933]  ? finish_automount+0x2e0/0x2e0
[  114.498362]  ? putname+0x80/0xa0
[  114.498571]  ? kmem_cache_free+0x1c4/0x440
[  114.498819]  ? putname+0x80/0xa0
[  114.499069]  do_mount+0xd6/0xf0
[  114.499343]  ? path_mount+0xfe0/0xfe0
[  114.499683]  ? __kasan_check_write+0x14/0x20
[  114.500133]  __x64_sys_mount+0xca/0x110
[  114.500592]  do_syscall_64+0x3b/0x90
[  114.500930]  entry_SYSCALL_64_after_hwframe+0x63/0xcd
[  114.501294] RIP: 0033:0x7fdc898e948a
[  114.501542] Code: 48 8b 0d 11 fa 2a 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 49 89 ca b8 a5 00 00 008
[  114.502716] RSP: 002b:00007ffd793e58f8 EFLAGS: 00000202 ORIG_RAX: 00000000000000a5
[  114.503175] RAX: ffffffffffffffda RBX: 0000564b2228f060 RCX: 00007fdc898e948a
[  114.503588] RDX: 0000564b2228f260 RSI: 0000564b2228f2e0 RDI: 0000564b22297ce0
[  114.504925] RBP: 0000000000000000 R08: 0000564b2228f280 R09: 0000000000000020
[  114.505484] R10: 00000000c0ed0000 R11: 0000000000000202 R12: 0000564b22297ce0
[  114.505823] R13: 0000564b2228f260 R14: 0000000000000000 R15: 00000000ffffffff
[  114.506562]  </TASK>
[  114.506887] Modules linked in:
[  114.507648] CR2: 0000000000000008
[  114.508884] ---[ end trace 0000000000000000 ]---
[  114.509675] RIP: 0010:d_flags_for_inode+0xe0/0x110
[  114.510140] Code: 24 f7 ff 49 83 3e 00 74 41 41 83 cd 02 66 44 89 6b 02 eb 92 48 8d 7b 20 e8 6d 24 f7 ff 4c 8b 73 20 49 8d 7e 08 e8 60 241
[  114.511762] RSP: 0018:ffff8880065e7aa8 EFLAGS: 00000296
[  114.512401] RAX: 0000000000000001 RBX: ffff888008ccd750 RCX: ffffffff84af2aea
[  114.513103] RDX: 0000000000000001 RSI: 0000000000000008 RDI: ffffffff87abd020
[  114.513512] RBP: ffff8880065e7ac8 R08: 0000000000000001 R09: fffffbfff0f57a05
[  114.513831] R10: ffffffff87abd027 R11: fffffbfff0f57a04 R12: 0000000000000000
[  114.514757] R13: 0000000000000008 R14: 0000000000000000 R15: ffff888008ccd750
[  114.515411] FS:  00007fdc8a627e40(0000) GS:ffff888058200000(0000) knlGS:0000000000000000
[  114.515794] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[  114.516208] CR2: 0000000000000008 CR3: 00000000013ba000 CR4: 00000000000006f0

Signed-off-by: Edward Lo <edward.lo@ambergroup.io>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/super.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/fs/ntfs3/super.c b/fs/ntfs3/super.c
index ff70e2a5f3acb..1e2c04e48f98f 100644
--- a/fs/ntfs3/super.c
+++ b/fs/ntfs3/super.c
@@ -1286,9 +1286,9 @@ load_root:
 	ref.low = cpu_to_le32(MFT_REC_ROOT);
 	ref.seq = cpu_to_le16(MFT_REC_ROOT);
 	inode = ntfs_iget5(sb, &ref, &NAME_ROOT);
-	if (IS_ERR(inode)) {
+	if (IS_ERR(inode) || !inode->i_op) {
 		ntfs_err(sb, "Failed to load root.");
-		err = PTR_ERR(inode);
+		err = IS_ERR(inode) ? PTR_ERR(inode) : -EINVAL;
 		goto out;
 	}
 
-- 
GitLab


From 4f1dc7d9756e66f3f876839ea174df2e656b7f79 Mon Sep 17 00:00:00 2001
From: Edward Lo <edward.lo@ambergroup.io>
Date: Fri, 9 Sep 2022 09:04:00 +0800
Subject: [PATCH 018/875] fs/ntfs3: Validate attribute name offset

Although the attribute name length is checked before comparing it to
some common names (e.g., $I30), the offset isn't. This adds a sanity
check for the attribute name offset, guarantee the validity and prevent
possible out-of-bound memory accesses.

[  191.720056] BUG: unable to handle page fault for address: ffffebde00000008
[  191.721060] #PF: supervisor read access in kernel mode
[  191.721586] #PF: error_code(0x0000) - not-present page
[  191.722079] PGD 0 P4D 0
[  191.722571] Oops: 0000 [#1] PREEMPT SMP KASAN NOPTI
[  191.723179] CPU: 0 PID: 244 Comm: mount Not tainted 6.0.0-rc4 #28
[  191.723749] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org 04/01/2014
[  191.724832] RIP: 0010:kfree+0x56/0x3b0
[  191.725870] Code: 80 48 01 d8 0f 82 65 03 00 00 48 c7 c2 00 00 00 80 48 2b 15 2c 06 dd 01 48 01 d0 48 c1 e8 0c 48 c1 e0 06 48 03 05 0a 069
[  191.727375] RSP: 0018:ffff8880076f7878 EFLAGS: 00000286
[  191.727897] RAX: ffffebde00000000 RBX: 0000000000000040 RCX: ffffffff8528d5b9
[  191.728531] RDX: 0000777f80000000 RSI: ffffffff8522d49c RDI: 0000000000000040
[  191.729183] RBP: ffff8880076f78a0 R08: 0000000000000000 R09: 0000000000000000
[  191.729628] R10: ffff888008949fd8 R11: ffffed10011293fd R12: 0000000000000040
[  191.730158] R13: ffff888008949f98 R14: ffff888008949ec0 R15: ffff888008949fb0
[  191.730645] FS:  00007f3520cd7e40(0000) GS:ffff88805ba00000(0000) knlGS:0000000000000000
[  191.731328] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[  191.731667] CR2: ffffebde00000008 CR3: 0000000009704000 CR4: 00000000000006f0
[  191.732568] Call Trace:
[  191.733231]  <TASK>
[  191.733860]  kvfree+0x2c/0x40
[  191.734632]  ni_clear+0x180/0x290
[  191.735085]  ntfs_evict_inode+0x45/0x70
[  191.735495]  evict+0x199/0x280
[  191.735996]  iput.part.0+0x286/0x320
[  191.736438]  iput+0x32/0x50
[  191.736811]  iget_failed+0x23/0x30
[  191.737270]  ntfs_iget5+0x337/0x1890
[  191.737629]  ? ntfs_clear_mft_tail+0x20/0x260
[  191.738201]  ? ntfs_get_block_bmap+0x70/0x70
[  191.738482]  ? ntfs_objid_init+0xf6/0x140
[  191.738779]  ? ntfs_reparse_init+0x140/0x140
[  191.739266]  ntfs_fill_super+0x121b/0x1b50
[  191.739623]  ? put_ntfs+0x1d0/0x1d0
[  191.739984]  ? asm_sysvec_apic_timer_interrupt+0x1b/0x20
[  191.740466]  ? put_ntfs+0x1d0/0x1d0
[  191.740787]  ? sb_set_blocksize+0x6a/0x80
[  191.741272]  get_tree_bdev+0x232/0x370
[  191.741829]  ? put_ntfs+0x1d0/0x1d0
[  191.742669]  ntfs_fs_get_tree+0x15/0x20
[  191.743132]  vfs_get_tree+0x4c/0x130
[  191.743457]  path_mount+0x654/0xfe0
[  191.743938]  ? putname+0x80/0xa0
[  191.744271]  ? finish_automount+0x2e0/0x2e0
[  191.744582]  ? putname+0x80/0xa0
[  191.745053]  ? kmem_cache_free+0x1c4/0x440
[  191.745403]  ? putname+0x80/0xa0
[  191.745616]  do_mount+0xd6/0xf0
[  191.745887]  ? path_mount+0xfe0/0xfe0
[  191.746287]  ? __kasan_check_write+0x14/0x20
[  191.746582]  __x64_sys_mount+0xca/0x110
[  191.746850]  do_syscall_64+0x3b/0x90
[  191.747122]  entry_SYSCALL_64_after_hwframe+0x63/0xcd
[  191.747517] RIP: 0033:0x7f351fee948a
[  191.748332] Code: 48 8b 0d 11 fa 2a 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 49 89 ca b8 a5 00 00 008
[  191.749341] RSP: 002b:00007ffd51cf3af8 EFLAGS: 00000202 ORIG_RAX: 00000000000000a5
[  191.749960] RAX: ffffffffffffffda RBX: 000055b903733060 RCX: 00007f351fee948a
[  191.750589] RDX: 000055b903733260 RSI: 000055b9037332e0 RDI: 000055b90373bce0
[  191.751115] RBP: 0000000000000000 R08: 000055b903733280 R09: 0000000000000020
[  191.751537] R10: 00000000c0ed0000 R11: 0000000000000202 R12: 000055b90373bce0
[  191.751946] R13: 000055b903733260 R14: 0000000000000000 R15: 00000000ffffffff
[  191.752519]  </TASK>
[  191.752782] Modules linked in:
[  191.753785] CR2: ffffebde00000008
[  191.754937] ---[ end trace 0000000000000000 ]---
[  191.755429] RIP: 0010:kfree+0x56/0x3b0
[  191.755725] Code: 80 48 01 d8 0f 82 65 03 00 00 48 c7 c2 00 00 00 80 48 2b 15 2c 06 dd 01 48 01 d0 48 c1 e8 0c 48 c1 e0 06 48 03 05 0a 069
[  191.756744] RSP: 0018:ffff8880076f7878 EFLAGS: 00000286
[  191.757218] RAX: ffffebde00000000 RBX: 0000000000000040 RCX: ffffffff8528d5b9
[  191.757580] RDX: 0000777f80000000 RSI: ffffffff8522d49c RDI: 0000000000000040
[  191.758016] RBP: ffff8880076f78a0 R08: 0000000000000000 R09: 0000000000000000
[  191.758570] R10: ffff888008949fd8 R11: ffffed10011293fd R12: 0000000000000040
[  191.758957] R13: ffff888008949f98 R14: ffff888008949ec0 R15: ffff888008949fb0
[  191.759317] FS:  00007f3520cd7e40(0000) GS:ffff88805ba00000(0000) knlGS:0000000000000000
[  191.759711] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[  191.760118] CR2: ffffebde00000008 CR3: 0000000009704000 CR4: 00000000000006f0

Signed-off-by: Edward Lo <edward.lo@ambergroup.io>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/inode.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/fs/ntfs3/inode.c b/fs/ntfs3/inode.c
index b1832b482c175..8b6fa7cd27848 100644
--- a/fs/ntfs3/inode.c
+++ b/fs/ntfs3/inode.c
@@ -129,6 +129,9 @@ next_attr:
 	rsize = attr->non_res ? 0 : le32_to_cpu(attr->res.data_size);
 	asize = le32_to_cpu(attr->size);
 
+	if (le16_to_cpu(attr->name_off) + attr->name_len > asize)
+		goto out;
+
 	switch (attr->type) {
 	case ATTR_STD:
 		if (attr->non_res ||
-- 
GitLab


From e001e60869390686809663c02bceb1d3922548fb Mon Sep 17 00:00:00 2001
From: Dan Carpenter <dan.carpenter@oracle.com>
Date: Mon, 12 Sep 2022 18:08:51 +0300
Subject: [PATCH 019/875] fs/ntfs3: Harden against integer overflows

Smatch complains that the "add_bytes" is not to be trusted.  Use
size_add() to prevent an integer overflow.

Fixes: be71b5cba2e6 ("fs/ntfs3: Add attrib operations")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/xattr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/ntfs3/xattr.c b/fs/ntfs3/xattr.c
index 6ae1f56b7358f..2b4019ecd004a 100644
--- a/fs/ntfs3/xattr.c
+++ b/fs/ntfs3/xattr.c
@@ -107,7 +107,7 @@ static int ntfs_read_ea(struct ntfs_inode *ni, struct EA_FULL **ea,
 		return -EFBIG;
 
 	/* Allocate memory for packed Ea. */
-	ea_p = kmalloc(size + add_bytes, GFP_NOFS);
+	ea_p = kmalloc(size_add(size, add_bytes), GFP_NOFS);
 	if (!ea_p)
 		return -ENOMEM;
 
-- 
GitLab


From 4d42ecda239cc13738d6fd84d098a32e67b368b9 Mon Sep 17 00:00:00 2001
From: Edward Lo <edward.lo@ambergroup.io>
Date: Thu, 22 Sep 2022 15:30:44 +0800
Subject: [PATCH 020/875] fs/ntfs3: Validate buffer length while parsing index

indx_read is called when we have some NTFS directory operations that
need more information from the index buffers. This adds a sanity check
to make sure the returned index buffer length is legit, or we may have
some out-of-bound memory accesses.

[  560.897595] BUG: KASAN: slab-out-of-bounds in hdr_find_e.isra.0+0x10c/0x320
[  560.898321] Read of size 2 at addr ffff888009497238 by task exp/245
[  560.898760]
[  560.899129] CPU: 0 PID: 245 Comm: exp Not tainted 6.0.0-rc6 #37
[  560.899505] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org 04/01/2014
[  560.900170] Call Trace:
[  560.900407]  <TASK>
[  560.900732]  dump_stack_lvl+0x49/0x63
[  560.901108]  print_report.cold+0xf5/0x689
[  560.901395]  ? hdr_find_e.isra.0+0x10c/0x320
[  560.901716]  kasan_report+0xa7/0x130
[  560.901950]  ? hdr_find_e.isra.0+0x10c/0x320
[  560.902208]  __asan_load2+0x68/0x90
[  560.902427]  hdr_find_e.isra.0+0x10c/0x320
[  560.902846]  ? cmp_uints+0xe0/0xe0
[  560.903363]  ? cmp_sdh+0x90/0x90
[  560.903883]  ? ntfs_bread_run+0x190/0x190
[  560.904196]  ? rwsem_down_read_slowpath+0x750/0x750
[  560.904969]  ? ntfs_fix_post_read+0xe0/0x130
[  560.905259]  ? __kasan_check_write+0x14/0x20
[  560.905599]  ? up_read+0x1a/0x90
[  560.905853]  ? indx_read+0x22c/0x380
[  560.906096]  indx_find+0x2ef/0x470
[  560.906352]  ? indx_find_buffer+0x2d0/0x2d0
[  560.906692]  ? __kasan_kmalloc+0x88/0xb0
[  560.906977]  dir_search_u+0x196/0x2f0
[  560.907220]  ? ntfs_nls_to_utf16+0x450/0x450
[  560.907464]  ? __kasan_check_write+0x14/0x20
[  560.907747]  ? mutex_lock+0x8f/0xe0
[  560.907970]  ? __mutex_lock_slowpath+0x20/0x20
[  560.908214]  ? kmem_cache_alloc+0x143/0x4b0
[  560.908459]  ntfs_lookup+0xe0/0x100
[  560.908788]  __lookup_slow+0x116/0x220
[  560.909050]  ? lookup_fast+0x1b0/0x1b0
[  560.909309]  ? lookup_fast+0x13f/0x1b0
[  560.909601]  walk_component+0x187/0x230
[  560.909944]  link_path_walk.part.0+0x3f0/0x660
[  560.910285]  ? handle_lookup_down+0x90/0x90
[  560.910618]  ? path_init+0x642/0x6e0
[  560.911084]  ? percpu_counter_add_batch+0x6e/0xf0
[  560.912559]  ? __alloc_file+0x114/0x170
[  560.913008]  path_openat+0x19c/0x1d10
[  560.913419]  ? getname_flags+0x73/0x2b0
[  560.913815]  ? kasan_save_stack+0x3a/0x50
[  560.914125]  ? kasan_save_stack+0x26/0x50
[  560.914542]  ? __kasan_slab_alloc+0x6d/0x90
[  560.914924]  ? kmem_cache_alloc+0x143/0x4b0
[  560.915339]  ? getname_flags+0x73/0x2b0
[  560.915647]  ? getname+0x12/0x20
[  560.916114]  ? __x64_sys_open+0x4c/0x60
[  560.916460]  ? path_lookupat.isra.0+0x230/0x230
[  560.916867]  ? __isolate_free_page+0x2e0/0x2e0
[  560.917194]  do_filp_open+0x15c/0x1f0
[  560.917448]  ? may_open_dev+0x60/0x60
[  560.917696]  ? expand_files+0xa4/0x3a0
[  560.917923]  ? __kasan_check_write+0x14/0x20
[  560.918185]  ? _raw_spin_lock+0x88/0xdb
[  560.918409]  ? _raw_spin_lock_irqsave+0x100/0x100
[  560.918783]  ? _find_next_bit+0x4a/0x130
[  560.919026]  ? _raw_spin_unlock+0x19/0x40
[  560.919276]  ? alloc_fd+0x14b/0x2d0
[  560.919635]  do_sys_openat2+0x32a/0x4b0
[  560.920035]  ? file_open_root+0x230/0x230
[  560.920336]  ? __rcu_read_unlock+0x5b/0x280
[  560.920813]  do_sys_open+0x99/0xf0
[  560.921208]  ? filp_open+0x60/0x60
[  560.921482]  ? exit_to_user_mode_prepare+0x49/0x180
[  560.921867]  __x64_sys_open+0x4c/0x60
[  560.922128]  do_syscall_64+0x3b/0x90
[  560.922369]  entry_SYSCALL_64_after_hwframe+0x63/0xcd
[  560.923030] RIP: 0033:0x7f7dff2e4469
[  560.923681] Code: 00 f3 c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 088
[  560.924451] RSP: 002b:00007ffd41a210b8 EFLAGS: 00000206 ORIG_RAX: 0000000000000002
[  560.925168] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f7dff2e4469
[  560.925655] RDX: 0000000000000000 RSI: 0000000000000002 RDI: 00007ffd41a211f0
[  560.926085] RBP: 00007ffd41a252a0 R08: 00007f7dff60fba0 R09: 00007ffd41a25388
[  560.926405] R10: 0000000000400b80 R11: 0000000000000206 R12: 00000000004004e0
[  560.926867] R13: 00007ffd41a25380 R14: 0000000000000000 R15: 0000000000000000
[  560.927241]  </TASK>
[  560.927491]
[  560.927755] Allocated by task 245:
[  560.928409]  kasan_save_stack+0x26/0x50
[  560.929271]  __kasan_kmalloc+0x88/0xb0
[  560.929778]  __kmalloc+0x192/0x320
[  560.930023]  indx_read+0x249/0x380
[  560.930224]  indx_find+0x2a2/0x470
[  560.930695]  dir_search_u+0x196/0x2f0
[  560.930892]  ntfs_lookup+0xe0/0x100
[  560.931115]  __lookup_slow+0x116/0x220
[  560.931323]  walk_component+0x187/0x230
[  560.931570]  link_path_walk.part.0+0x3f0/0x660
[  560.931791]  path_openat+0x19c/0x1d10
[  560.932008]  do_filp_open+0x15c/0x1f0
[  560.932226]  do_sys_openat2+0x32a/0x4b0
[  560.932413]  do_sys_open+0x99/0xf0
[  560.932709]  __x64_sys_open+0x4c/0x60
[  560.933417]  do_syscall_64+0x3b/0x90
[  560.933776]  entry_SYSCALL_64_after_hwframe+0x63/0xcd
[  560.934235]
[  560.934486] The buggy address belongs to the object at ffff888009497000
[  560.934486]  which belongs to the cache kmalloc-512 of size 512
[  560.935239] The buggy address is located 56 bytes to the right of
[  560.935239]  512-byte region [ffff888009497000, ffff888009497200)
[  560.936153]
[  560.937326] The buggy address belongs to the physical page:
[  560.938228] page:0000000062a3dfae refcount:1 mapcount:0 mapping:0000000000000000 index:0x0 pfn:0x9496
[  560.939616] head:0000000062a3dfae order:1 compound_mapcount:0 compound_pincount:0
[  560.940219] flags: 0xfffffc0010200(slab|head|node=0|zone=1|lastcpupid=0x1fffff)
[  560.942702] raw: 000fffffc0010200 ffffea0000164f80 dead000000000005 ffff888001041c80
[  560.943932] raw: 0000000000000000 0000000080080008 00000001ffffffff 0000000000000000
[  560.944568] page dumped because: kasan: bad access detected
[  560.945735]
[  560.946112] Memory state around the buggy address:
[  560.946870]  ffff888009497100: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
[  560.947242]  ffff888009497180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
[  560.947611] >ffff888009497200: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
[  560.947915]                                         ^
[  560.948249]  ffff888009497280: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
[  560.948687]  ffff888009497300: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc

Signed-off-by: Edward Lo <edward.lo@ambergroup.io>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/index.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/fs/ntfs3/index.c b/fs/ntfs3/index.c
index 613036f9c6e66..bc656868cf8a8 100644
--- a/fs/ntfs3/index.c
+++ b/fs/ntfs3/index.c
@@ -1017,6 +1017,12 @@ ok:
 		err = 0;
 	}
 
+	/* check for index header length */
+	if (offsetof(struct INDEX_BUFFER, ihdr) + ib->ihdr.used > bytes) {
+		err = -EINVAL;
+		goto out;
+	}
+
 	in->index = ib;
 	*node = in;
 
-- 
GitLab


From 54e45702b648b7c0000e90b3e9b890e367e16ea8 Mon Sep 17 00:00:00 2001
From: Edward Lo <edward.lo@ambergroup.io>
Date: Fri, 23 Sep 2022 00:50:23 +0800
Subject: [PATCH 021/875] fs/ntfs3: Validate resident attribute name

Though we already have some sanity checks while enumerating attributes,
resident attribute names aren't included. This patch checks the resident
attribute names are in the valid ranges.

[  259.209031] BUG: KASAN: slab-out-of-bounds in ni_create_attr_list+0x1e1/0x850
[  259.210770] Write of size 426 at addr ffff88800632f2b2 by task exp/255
[  259.211551]
[  259.212035] CPU: 0 PID: 255 Comm: exp Not tainted 6.0.0-rc6 #37
[  259.212955] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org 04/01/2014
[  259.214387] Call Trace:
[  259.214640]  <TASK>
[  259.214895]  dump_stack_lvl+0x49/0x63
[  259.215284]  print_report.cold+0xf5/0x689
[  259.215565]  ? kasan_poison+0x3c/0x50
[  259.215778]  ? kasan_unpoison+0x28/0x60
[  259.215991]  ? ni_create_attr_list+0x1e1/0x850
[  259.216270]  kasan_report+0xa7/0x130
[  259.216481]  ? ni_create_attr_list+0x1e1/0x850
[  259.216719]  kasan_check_range+0x15a/0x1d0
[  259.216939]  memcpy+0x3c/0x70
[  259.217136]  ni_create_attr_list+0x1e1/0x850
[  259.217945]  ? __rcu_read_unlock+0x5b/0x280
[  259.218384]  ? ni_remove_attr+0x2e0/0x2e0
[  259.218712]  ? kernel_text_address+0xcf/0xe0
[  259.219064]  ? __kernel_text_address+0x12/0x40
[  259.219434]  ? arch_stack_walk+0x9e/0xf0
[  259.219668]  ? __this_cpu_preempt_check+0x13/0x20
[  259.219904]  ? sysvec_apic_timer_interrupt+0x57/0xc0
[  259.220140]  ? asm_sysvec_apic_timer_interrupt+0x1b/0x20
[  259.220561]  ni_ins_attr_ext+0x52c/0x5c0
[  259.220984]  ? ni_create_attr_list+0x850/0x850
[  259.221532]  ? run_deallocate+0x120/0x120
[  259.221972]  ? vfs_setxattr+0x128/0x300
[  259.222688]  ? setxattr+0x126/0x140
[  259.222921]  ? path_setxattr+0x164/0x180
[  259.223431]  ? __x64_sys_setxattr+0x6d/0x80
[  259.223828]  ? entry_SYSCALL_64_after_hwframe+0x63/0xcd
[  259.224417]  ? mi_find_attr+0x3c/0xf0
[  259.224772]  ni_insert_attr+0x1ba/0x420
[  259.225216]  ? ni_ins_attr_ext+0x5c0/0x5c0
[  259.225504]  ? ntfs_read_ea+0x119/0x450
[  259.225775]  ni_insert_resident+0xc0/0x1c0
[  259.226316]  ? ni_insert_nonresident+0x400/0x400
[  259.227001]  ? __kasan_kmalloc+0x88/0xb0
[  259.227468]  ? __kmalloc+0x192/0x320
[  259.227773]  ntfs_set_ea+0x6bf/0xb30
[  259.228216]  ? ftrace_graph_ret_addr+0x2a/0xb0
[  259.228494]  ? entry_SYSCALL_64_after_hwframe+0x63/0xcd
[  259.228838]  ? ntfs_read_ea+0x450/0x450
[  259.229098]  ? is_bpf_text_address+0x24/0x40
[  259.229418]  ? kernel_text_address+0xcf/0xe0
[  259.229681]  ? __kernel_text_address+0x12/0x40
[  259.229948]  ? unwind_get_return_address+0x3a/0x60
[  259.230271]  ? write_profile+0x270/0x270
[  259.230537]  ? arch_stack_walk+0x9e/0xf0
[  259.230836]  ntfs_setxattr+0x114/0x5c0
[  259.231099]  ? ntfs_set_acl_ex+0x2e0/0x2e0
[  259.231529]  ? evm_protected_xattr_common+0x6d/0x100
[  259.231817]  ? posix_xattr_acl+0x13/0x80
[  259.232073]  ? evm_protect_xattr+0x1f7/0x440
[  259.232351]  __vfs_setxattr+0xda/0x120
[  259.232635]  ? xattr_resolve_name+0x180/0x180
[  259.232912]  __vfs_setxattr_noperm+0x93/0x300
[  259.233219]  __vfs_setxattr_locked+0x141/0x160
[  259.233492]  ? kasan_poison+0x3c/0x50
[  259.233744]  vfs_setxattr+0x128/0x300
[  259.234002]  ? __vfs_setxattr_locked+0x160/0x160
[  259.234837]  do_setxattr+0xb8/0x170
[  259.235567]  ? vmemdup_user+0x53/0x90
[  259.236212]  setxattr+0x126/0x140
[  259.236491]  ? do_setxattr+0x170/0x170
[  259.236791]  ? debug_smp_processor_id+0x17/0x20
[  259.237232]  ? kasan_quarantine_put+0x57/0x180
[  259.237605]  ? putname+0x80/0xa0
[  259.237870]  ? __kasan_slab_free+0x11c/0x1b0
[  259.238234]  ? putname+0x80/0xa0
[  259.238500]  ? preempt_count_sub+0x18/0xc0
[  259.238775]  ? __mnt_want_write+0xaa/0x100
[  259.238990]  ? mnt_want_write+0x8b/0x150
[  259.239290]  path_setxattr+0x164/0x180
[  259.239605]  ? setxattr+0x140/0x140
[  259.239849]  ? debug_smp_processor_id+0x17/0x20
[  259.240174]  ? fpregs_assert_state_consistent+0x67/0x80
[  259.240411]  __x64_sys_setxattr+0x6d/0x80
[  259.240715]  do_syscall_64+0x3b/0x90
[  259.240934]  entry_SYSCALL_64_after_hwframe+0x63/0xcd
[  259.241697] RIP: 0033:0x7fc6b26e4469
[  259.242647] Code: 00 f3 c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 088
[  259.244512] RSP: 002b:00007ffc3c7841f8 EFLAGS: 00000217 ORIG_RAX: 00000000000000bc
[  259.245086] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007fc6b26e4469
[  259.246025] RDX: 00007ffc3c784380 RSI: 00007ffc3c7842e0 RDI: 00007ffc3c784238
[  259.246961] RBP: 00007ffc3c788410 R08: 0000000000000001 R09: 00007ffc3c7884f8
[  259.247775] R10: 000000000000007f R11: 0000000000000217 R12: 00000000004004e0
[  259.248534] R13: 00007ffc3c7884f0 R14: 0000000000000000 R15: 0000000000000000
[  259.249368]  </TASK>
[  259.249644]
[  259.249888] Allocated by task 255:
[  259.250283]  kasan_save_stack+0x26/0x50
[  259.250957]  __kasan_kmalloc+0x88/0xb0
[  259.251826]  __kmalloc+0x192/0x320
[  259.252745]  ni_create_attr_list+0x11e/0x850
[  259.253298]  ni_ins_attr_ext+0x52c/0x5c0
[  259.253685]  ni_insert_attr+0x1ba/0x420
[  259.253974]  ni_insert_resident+0xc0/0x1c0
[  259.254311]  ntfs_set_ea+0x6bf/0xb30
[  259.254629]  ntfs_setxattr+0x114/0x5c0
[  259.254859]  __vfs_setxattr+0xda/0x120
[  259.255155]  __vfs_setxattr_noperm+0x93/0x300
[  259.255445]  __vfs_setxattr_locked+0x141/0x160
[  259.255862]  vfs_setxattr+0x128/0x300
[  259.256251]  do_setxattr+0xb8/0x170
[  259.256522]  setxattr+0x126/0x140
[  259.256911]  path_setxattr+0x164/0x180
[  259.257308]  __x64_sys_setxattr+0x6d/0x80
[  259.257637]  do_syscall_64+0x3b/0x90
[  259.257970]  entry_SYSCALL_64_after_hwframe+0x63/0xcd
[  259.258550]
[  259.258772] The buggy address belongs to the object at ffff88800632f000
[  259.258772]  which belongs to the cache kmalloc-1k of size 1024
[  259.260190] The buggy address is located 690 bytes inside of
[  259.260190]  1024-byte region [ffff88800632f000, ffff88800632f400)
[  259.261412]
[  259.261743] The buggy address belongs to the physical page:
[  259.262354] page:0000000081e8cac9 refcount:1 mapcount:0 mapping:0000000000000000 index:0x0 pfn:0x632c
[  259.263722] head:0000000081e8cac9 order:2 compound_mapcount:0 compound_pincount:0
[  259.264284] flags: 0xfffffc0010200(slab|head|node=0|zone=1|lastcpupid=0x1fffff)
[  259.265312] raw: 000fffffc0010200 ffffea0000060d00 dead000000000004 ffff888001041dc0
[  259.265772] raw: 0000000000000000 0000000080080008 00000001ffffffff 0000000000000000
[  259.266305] page dumped because: kasan: bad access detected
[  259.266588]
[  259.266728] Memory state around the buggy address:
[  259.267225]  ffff88800632f300: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
[  259.267841]  ffff88800632f380: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
[  259.269111] >ffff88800632f400: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
[  259.269626]                    ^
[  259.270162]  ffff88800632f480: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
[  259.270810]  ffff88800632f500: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc

Signed-off-by: Edward Lo <edward.lo@ambergroup.io>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/record.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/fs/ntfs3/record.c b/fs/ntfs3/record.c
index 66eb11e0965ef..a952cd7aa7a4b 100644
--- a/fs/ntfs3/record.c
+++ b/fs/ntfs3/record.c
@@ -265,6 +265,11 @@ struct ATTRIB *mi_enum_attr(struct mft_inode *mi, struct ATTRIB *attr)
 		if (t16 + t32 > asize)
 			return NULL;
 
+		if (attr->name_len &&
+		    le16_to_cpu(attr->name_off) + sizeof(short) * attr->name_len > t16) {
+			return NULL;
+		}
+
 		return attr;
 	}
 
-- 
GitLab


From 887bfc546097fbe8071dac13b2fef73b77920899 Mon Sep 17 00:00:00 2001
From: Hawkins Jiawei <yin31149@gmail.com>
Date: Fri, 23 Sep 2022 19:09:04 +0800
Subject: [PATCH 022/875] fs/ntfs3: Fix slab-out-of-bounds read in run_unpack

Syzkaller reports slab-out-of-bounds bug as follows:
==================================================================
BUG: KASAN: slab-out-of-bounds in run_unpack+0x8b7/0x970 fs/ntfs3/run.c:944
Read of size 1 at addr ffff88801bbdff02 by task syz-executor131/3611

[...]
Call Trace:
 <TASK>
 __dump_stack lib/dump_stack.c:88 [inline]
 dump_stack_lvl+0xcd/0x134 lib/dump_stack.c:106
 print_address_description mm/kasan/report.c:317 [inline]
 print_report.cold+0x2ba/0x719 mm/kasan/report.c:433
 kasan_report+0xb1/0x1e0 mm/kasan/report.c:495
 run_unpack+0x8b7/0x970 fs/ntfs3/run.c:944
 run_unpack_ex+0xb0/0x7c0 fs/ntfs3/run.c:1057
 ntfs_read_mft fs/ntfs3/inode.c:368 [inline]
 ntfs_iget5+0xc20/0x3280 fs/ntfs3/inode.c:501
 ntfs_loadlog_and_replay+0x124/0x5d0 fs/ntfs3/fsntfs.c:272
 ntfs_fill_super+0x1eff/0x37f0 fs/ntfs3/super.c:1018
 get_tree_bdev+0x440/0x760 fs/super.c:1323
 vfs_get_tree+0x89/0x2f0 fs/super.c:1530
 do_new_mount fs/namespace.c:3040 [inline]
 path_mount+0x1326/0x1e20 fs/namespace.c:3370
 do_mount fs/namespace.c:3383 [inline]
 __do_sys_mount fs/namespace.c:3591 [inline]
 __se_sys_mount fs/namespace.c:3568 [inline]
 __x64_sys_mount+0x27f/0x300 fs/namespace.c:3568
 do_syscall_x64 arch/x86/entry/common.c:50 [inline]
 do_syscall_64+0x35/0xb0 arch/x86/entry/common.c:80
 entry_SYSCALL_64_after_hwframe+0x63/0xcd
 [...]
 </TASK>

The buggy address belongs to the physical page:
page:ffffea00006ef600 refcount:1 mapcount:0 mapping:0000000000000000 index:0x0 pfn:0x1bbd8
head:ffffea00006ef600 order:3 compound_mapcount:0 compound_pincount:0
flags: 0xfff00000010200(slab|head|node=0|zone=1|lastcpupid=0x7ff)
page dumped because: kasan: bad access detected

Memory state around the buggy address:
 ffff88801bbdfe00: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
 ffff88801bbdfe80: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
>ffff88801bbdff00: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
                   ^
 ffff88801bbdff80: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
 ffff88801bbe0000: fa fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
==================================================================

Kernel will tries to read record and parse MFT from disk in
ntfs_read_mft().

Yet the problem is that during enumerating attributes in record,
kernel doesn't check whether run_off field loading from the disk
is a valid value.

To be more specific, if attr->nres.run_off is larger than attr->size,
kernel will passes an invalid argument run_buf_size in
run_unpack_ex(), which having an integer overflow. Then this invalid
argument will triggers the slab-out-of-bounds Read bug as above.

This patch solves it by adding the sanity check between
the offset to packed runs and attribute size.

link: https://lore.kernel.org/all/0000000000009145fc05e94bd5c3@google.com/#t
Reported-and-tested-by: syzbot+8d6fbb27a6aded64b25b@syzkaller.appspotmail.com
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/inode.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/fs/ntfs3/inode.c b/fs/ntfs3/inode.c
index 8b6fa7cd27848..e9cf00d147331 100644
--- a/fs/ntfs3/inode.c
+++ b/fs/ntfs3/inode.c
@@ -373,6 +373,13 @@ attr_unpack_run:
 	}
 
 	t64 = le64_to_cpu(attr->nres.svcn);
+
+	/* offset to packed runs is out-of-bounds */
+	if (roff > asize) {
+		err = -EINVAL;
+		goto out;
+	}
+
 	err = run_unpack_ex(run, sbi, ino, t64, le64_to_cpu(attr->nres.evcn),
 			    t64, Add2Ptr(attr, roff), asize - roff);
 	if (err < 0)
-- 
GitLab


From d45da67caedacd500879de5e649360cc70777af7 Mon Sep 17 00:00:00 2001
From: Yuan Can <yuancan@huawei.com>
Date: Sat, 24 Sep 2022 06:32:04 +0000
Subject: [PATCH 023/875] fs/ntfs3: Use strcmp to determine attribute type

The way of determin attribute type is just matching
name with the predefined string, do this with strcmp
to simplify the code.

Signed-off-by: Yuan Can <yuancan@huawei.com>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/xattr.c | 44 ++++++++++++++------------------------------
 1 file changed, 14 insertions(+), 30 deletions(-)

diff --git a/fs/ntfs3/xattr.c b/fs/ntfs3/xattr.c
index 2b4019ecd004a..aeee5fb120925 100644
--- a/fs/ntfs3/xattr.c
+++ b/fs/ntfs3/xattr.c
@@ -781,11 +781,9 @@ static int ntfs_getxattr(const struct xattr_handler *handler, struct dentry *de,
 {
 	int err;
 	struct ntfs_inode *ni = ntfs_i(inode);
-	size_t name_len = strlen(name);
 
 	/* Dispatch request. */
-	if (name_len == sizeof(SYSTEM_DOS_ATTRIB) - 1 &&
-	    !memcmp(name, SYSTEM_DOS_ATTRIB, sizeof(SYSTEM_DOS_ATTRIB))) {
+	if (!strcmp(name, SYSTEM_DOS_ATTRIB)) {
 		/* system.dos_attrib */
 		if (!buffer) {
 			err = sizeof(u8);
@@ -798,8 +796,7 @@ static int ntfs_getxattr(const struct xattr_handler *handler, struct dentry *de,
 		goto out;
 	}
 
-	if (name_len == sizeof(SYSTEM_NTFS_ATTRIB) - 1 &&
-	    !memcmp(name, SYSTEM_NTFS_ATTRIB, sizeof(SYSTEM_NTFS_ATTRIB))) {
+	if (!strcmp(name, SYSTEM_NTFS_ATTRIB)) {
 		/* system.ntfs_attrib */
 		if (!buffer) {
 			err = sizeof(u32);
@@ -812,8 +809,7 @@ static int ntfs_getxattr(const struct xattr_handler *handler, struct dentry *de,
 		goto out;
 	}
 
-	if (name_len == sizeof(SYSTEM_NTFS_SECURITY) - 1 &&
-	    !memcmp(name, SYSTEM_NTFS_SECURITY, sizeof(SYSTEM_NTFS_SECURITY))) {
+	if (!strcmp(name, SYSTEM_NTFS_SECURITY)) {
 		/* system.ntfs_security*/
 		struct SECURITY_DESCRIPTOR_RELATIVE *sd = NULL;
 		size_t sd_size = 0;
@@ -853,16 +849,12 @@ static int ntfs_getxattr(const struct xattr_handler *handler, struct dentry *de,
 	}
 
 #ifdef CONFIG_NTFS3_FS_POSIX_ACL
-	if ((name_len == sizeof(XATTR_NAME_POSIX_ACL_ACCESS) - 1 &&
-	     !memcmp(name, XATTR_NAME_POSIX_ACL_ACCESS,
-		     sizeof(XATTR_NAME_POSIX_ACL_ACCESS))) ||
-	    (name_len == sizeof(XATTR_NAME_POSIX_ACL_DEFAULT) - 1 &&
-	     !memcmp(name, XATTR_NAME_POSIX_ACL_DEFAULT,
-		     sizeof(XATTR_NAME_POSIX_ACL_DEFAULT)))) {
+	if (!strcmp(name, XATTR_NAME_POSIX_ACL_ACCESS) ||
+	    !strcmp(name, XATTR_NAME_POSIX_ACL_DEFAULT)) {
 		/* TODO: init_user_ns? */
 		err = ntfs_xattr_get_acl(
 			&init_user_ns, inode,
-			name_len == sizeof(XATTR_NAME_POSIX_ACL_ACCESS) - 1
+			strlen(name) == sizeof(XATTR_NAME_POSIX_ACL_ACCESS) - 1
 				? ACL_TYPE_ACCESS
 				: ACL_TYPE_DEFAULT,
 			buffer, size);
@@ -870,7 +862,7 @@ static int ntfs_getxattr(const struct xattr_handler *handler, struct dentry *de,
 	}
 #endif
 	/* Deal with NTFS extended attribute. */
-	err = ntfs_get_ea(inode, name, name_len, buffer, size, NULL);
+	err = ntfs_get_ea(inode, name, strlen(name), buffer, size, NULL);
 
 out:
 	return err;
@@ -887,20 +879,17 @@ static noinline int ntfs_setxattr(const struct xattr_handler *handler,
 {
 	int err = -EINVAL;
 	struct ntfs_inode *ni = ntfs_i(inode);
-	size_t name_len = strlen(name);
 	enum FILE_ATTRIBUTE new_fa;
 
 	/* Dispatch request. */
-	if (name_len == sizeof(SYSTEM_DOS_ATTRIB) - 1 &&
-	    !memcmp(name, SYSTEM_DOS_ATTRIB, sizeof(SYSTEM_DOS_ATTRIB))) {
+	if (!strcmp(name, SYSTEM_DOS_ATTRIB)) {
 		if (sizeof(u8) != size)
 			goto out;
 		new_fa = cpu_to_le32(*(u8 *)value);
 		goto set_new_fa;
 	}
 
-	if (name_len == sizeof(SYSTEM_NTFS_ATTRIB) - 1 &&
-	    !memcmp(name, SYSTEM_NTFS_ATTRIB, sizeof(SYSTEM_NTFS_ATTRIB))) {
+	if (!strcmp(name, SYSTEM_NTFS_ATTRIB)) {
 		if (size != sizeof(u32))
 			goto out;
 		new_fa = cpu_to_le32(*(u32 *)value);
@@ -938,8 +927,7 @@ set_new_fa:
 		goto out;
 	}
 
-	if (name_len == sizeof(SYSTEM_NTFS_SECURITY) - 1 &&
-	    !memcmp(name, SYSTEM_NTFS_SECURITY, sizeof(SYSTEM_NTFS_SECURITY))) {
+	if (!strcmp(name, SYSTEM_NTFS_SECURITY)) {
 		/* system.ntfs_security*/
 		__le32 security_id;
 		bool inserted;
@@ -982,15 +970,11 @@ set_new_fa:
 	}
 
 #ifdef CONFIG_NTFS3_FS_POSIX_ACL
-	if ((name_len == sizeof(XATTR_NAME_POSIX_ACL_ACCESS) - 1 &&
-	     !memcmp(name, XATTR_NAME_POSIX_ACL_ACCESS,
-		     sizeof(XATTR_NAME_POSIX_ACL_ACCESS))) ||
-	    (name_len == sizeof(XATTR_NAME_POSIX_ACL_DEFAULT) - 1 &&
-	     !memcmp(name, XATTR_NAME_POSIX_ACL_DEFAULT,
-		     sizeof(XATTR_NAME_POSIX_ACL_DEFAULT)))) {
+	if (!strcmp(name, XATTR_NAME_POSIX_ACL_ACCESS) ||
+	    !strcmp(name, XATTR_NAME_POSIX_ACL_DEFAULT)) {
 		err = ntfs_xattr_set_acl(
 			mnt_userns, inode,
-			name_len == sizeof(XATTR_NAME_POSIX_ACL_ACCESS) - 1
+			strlen(name) == sizeof(XATTR_NAME_POSIX_ACL_ACCESS) - 1
 				? ACL_TYPE_ACCESS
 				: ACL_TYPE_DEFAULT,
 			value, size);
@@ -998,7 +982,7 @@ set_new_fa:
 	}
 #endif
 	/* Deal with NTFS extended attribute. */
-	err = ntfs_set_ea(inode, name, name_len, value, size, flags, 0);
+	err = ntfs_set_ea(inode, name, strlen(name), value, size, flags, 0);
 
 out:
 	inode->i_ctime = current_time(inode);
-- 
GitLab


From 65fcf3872f83d63fb7268e05d4b02640df14126e Mon Sep 17 00:00:00 2001
From: Shengjiu Wang <shengjiu.wang@nxp.com>
Date: Tue, 18 Oct 2022 21:44:04 +0800
Subject: [PATCH 024/875] remoteproc: core: Auto select rproc-virtio device id

With multiple remoteproc device, there will below error:

sysfs: cannot create duplicate filename '/bus/platform/devices/rproc-virtio.0'

The rvdev_data.index is duplicate, that cause issue, so
need to use the PLATFORM_DEVID_AUTO instead. After fixing
device name it becomes something like:
/bus/platform/devices/rproc-virtio.2.auto

Fixes: 1d7b61c06dc3 ("remoteproc: virtio: Create platform device for the remoteproc_virtio")
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Reviewed-by: Mukesh Ojha <quic_mojha@quicinc.com>
Tested-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/1666100644-27010-1-git-send-email-shengjiu.wang@nxp.com
[Fixed typographical error in comment block]
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/remoteproc/remoteproc_core.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
index 8768cb64f560c..cb1d414a23896 100644
--- a/drivers/remoteproc/remoteproc_core.c
+++ b/drivers/remoteproc/remoteproc_core.c
@@ -509,7 +509,13 @@ static int rproc_handle_vdev(struct rproc *rproc, void *ptr,
 	rvdev_data.rsc_offset = offset;
 	rvdev_data.rsc = rsc;
 
-	pdev = platform_device_register_data(dev, "rproc-virtio", rvdev_data.index, &rvdev_data,
+	/*
+	 * When there is more than one remote processor, rproc->nb_vdev number is
+	 * same for each separate instances of "rproc". If rvdev_data.index is used
+	 * as device id, then we get duplication in sysfs, so need to use
+	 * PLATFORM_DEVID_AUTO to auto select device id.
+	 */
+	pdev = platform_device_register_data(dev, "rproc-virtio", PLATFORM_DEVID_AUTO, &rvdev_data,
 					     sizeof(rvdev_data));
 	if (IS_ERR(pdev)) {
 		dev_err(dev, "failed to create rproc-virtio device\n");
-- 
GitLab


From 47e6ab07018edebf94ce873cf50a05ec76ff2dde Mon Sep 17 00:00:00 2001
From: Shengjiu Wang <shengjiu.wang@nxp.com>
Date: Fri, 30 Sep 2022 15:50:16 +0800
Subject: [PATCH 025/875] remoteproc: imx_dsp_rproc: Add mutex protection for
 workqueue

The workqueue may execute late even after remoteproc is stopped or
stopping, some resources (rpmsg device and endpoint) have been
released in rproc_stop_subdevices(), then rproc_vq_interrupt()
accessing these resources will cause kennel dump.

Call trace:
 virtqueue_add_split+0x1ac/0x560
 virtqueue_add_inbuf+0x4c/0x60
 rpmsg_recv_done+0x15c/0x294
 vring_interrupt+0x6c/0xa4
 rproc_vq_interrupt+0x30/0x50
 imx_dsp_rproc_vq_work+0x24/0x40 [imx_dsp_rproc]
 process_one_work+0x1d0/0x354
 worker_thread+0x13c/0x470
 kthread+0x154/0x160
 ret_from_fork+0x10/0x20

Add mutex protection in imx_dsp_rproc_vq_work(), if the state is
not running, then just skip calling rproc_vq_interrupt().

Also the flush workqueue operation can't be added in rproc stop
for the same reason. The call sequence is

rproc_shutdown
-> rproc_stop
   ->rproc_stop_subdevices
   ->rproc->ops->stop()
     ->imx_dsp_rproc_stop
       ->flush_work
         -> rproc_vq_interrupt

The resource needed by rproc_vq_interrupt has been released in
rproc_stop_subdevices, so flush_work is not safe to be called in
imx_dsp_rproc_stop.

Fixes: ec0e5549f358 ("remoteproc: imx_dsp_rproc: Add remoteproc driver for DSP on i.MX")
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Cc: stable <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/1664524216-19949-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/remoteproc/imx_dsp_rproc.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/remoteproc/imx_dsp_rproc.c b/drivers/remoteproc/imx_dsp_rproc.c
index 899aa8dd12f07..95da1cbefacf0 100644
--- a/drivers/remoteproc/imx_dsp_rproc.c
+++ b/drivers/remoteproc/imx_dsp_rproc.c
@@ -347,9 +347,6 @@ static int imx_dsp_rproc_stop(struct rproc *rproc)
 	struct device *dev = rproc->dev.parent;
 	int ret = 0;
 
-	/* Make sure work is finished */
-	flush_work(&priv->rproc_work);
-
 	if (rproc->state == RPROC_CRASHED) {
 		priv->flags &= ~REMOTE_IS_READY;
 		return 0;
@@ -432,9 +429,18 @@ static void imx_dsp_rproc_vq_work(struct work_struct *work)
 {
 	struct imx_dsp_rproc *priv = container_of(work, struct imx_dsp_rproc,
 						  rproc_work);
+	struct rproc *rproc = priv->rproc;
+
+	mutex_lock(&rproc->lock);
+
+	if (rproc->state != RPROC_RUNNING)
+		goto unlock_mutex;
 
 	rproc_vq_interrupt(priv->rproc, 0);
 	rproc_vq_interrupt(priv->rproc, 1);
+
+unlock_mutex:
+	mutex_unlock(&rproc->lock);
 }
 
 /**
-- 
GitLab


From 190362e03bed3f7bde7635f14c955fc9ed96eb78 Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Fri, 21 Oct 2022 12:15:20 +0800
Subject: [PATCH 026/875] dt-bindings: remoteproc: imx_rproc: Support i.MX8QXP

Add i.MX8QXP compatible

Add a new property fsl,resource-id for SoC which supports SCFW.
This property is used to check whether remote process is under control
of Linux or not.

Add fsl,entry-address to specify the entry address which used by SCFW
to kick M4.

To i.MX8QM/QXP, when M4 is in the same hardware partition with Cortex-A
cores, need power up M4 through SCFW, then M4 could start. So introduce
power-domains property.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20221021041526.3696483-2-peng.fan@oss.nxp.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 .../bindings/remoteproc/fsl,imx-rproc.yaml        | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml
index 3a1f59ad79e23..70322e57b6ffd 100644
--- a/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml
@@ -22,6 +22,7 @@ properties:
       - fsl,imx8mn-cm7
       - fsl,imx8mp-cm7
       - fsl,imx8mq-cm4
+      - fsl,imx8qxp-cm4
       - fsl,imx8ulp-cm33
       - fsl,imx93-cm33
 
@@ -54,12 +55,26 @@ properties:
     minItems: 1
     maxItems: 32
 
+  power-domains:
+    maxItems: 8
+
   fsl,auto-boot:
     $ref: /schemas/types.yaml#/definitions/flag
     description:
       Indicate whether need to load the default firmware and start the remote
       processor automatically.
 
+  fsl,entry-address:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Specify CPU entry address for SCU enabled processor.
+
+  fsl,resource-id:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      This property is to specify the resource id of the remote processor in SoC
+      which supports SCFW
+
 required:
   - compatible
 
-- 
GitLab


From 505066645f3f14c15abd0875654fbc7b0610ca2e Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Fri, 21 Oct 2022 12:15:21 +0800
Subject: [PATCH 027/875] dt-bindings: remoteproc: imx_rproc: Support i.MX8QM

Add i.MX8QM compatible.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20221021041526.3696483-3-peng.fan@oss.nxp.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml
index 70322e57b6ffd..ad3b8d4ccd91c 100644
--- a/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml
@@ -22,6 +22,7 @@ properties:
       - fsl,imx8mn-cm7
       - fsl,imx8mp-cm7
       - fsl,imx8mq-cm4
+      - fsl,imx8qm-cm4
       - fsl,imx8qxp-cm4
       - fsl,imx8ulp-cm33
       - fsl,imx93-cm33
-- 
GitLab


From 5e50aef2632e74db58d61c8e86bd767dc28a7970 Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Fri, 21 Oct 2022 12:15:22 +0800
Subject: [PATCH 028/875] remoteproc: imx_rproc: Support attaching to i.MX8QXP
 M4

When M4 is kicked by SCFW, M4 runs in its own hardware partition, Linux
could only do IPC with M4, it could not start, stop, update image.

We disable recovery reboot when M4 is managed by SCFW, because
remoteproc core still not support M4 auto-recovery without loading
image.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20221021041526.3696483-4-peng.fan@oss.nxp.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/remoteproc/imx_rproc.c | 108 ++++++++++++++++++++++++++++++++-
 1 file changed, 107 insertions(+), 1 deletion(-)

diff --git a/drivers/remoteproc/imx_rproc.c b/drivers/remoteproc/imx_rproc.c
index 7cc4fd207e2d8..5bbba69556833 100644
--- a/drivers/remoteproc/imx_rproc.c
+++ b/drivers/remoteproc/imx_rproc.c
@@ -6,6 +6,7 @@
 #include <linux/arm-smccc.h>
 #include <linux/clk.h>
 #include <linux/err.h>
+#include <linux/firmware/imx/sci.h>
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
 #include <linux/mailbox_client.h>
@@ -59,6 +60,8 @@
 #define IMX_SIP_RPROC_STARTED		0x01
 #define IMX_SIP_RPROC_STOP		0x02
 
+#define IMX_SC_IRQ_GROUP_REBOOTED	5
+
 /**
  * struct imx_rproc_mem - slim internal memory structure
  * @cpu_addr: MPU virtual address of the memory region
@@ -89,6 +92,10 @@ struct imx_rproc {
 	struct work_struct		rproc_work;
 	struct workqueue_struct		*workqueue;
 	void __iomem			*rsc_table;
+	struct imx_sc_ipc		*ipc_handle;
+	struct notifier_block		rproc_nb;
+	u32				rproc_pt;	/* partition id */
+	u32				rsrc_id;	/* resource id */
 };
 
 static const struct imx_rproc_att imx_rproc_att_imx93[] = {
@@ -117,6 +124,18 @@ static const struct imx_rproc_att imx_rproc_att_imx93[] = {
 	{ 0xD0000000, 0xa0000000, 0x10000000, 0 },
 };
 
+static const struct imx_rproc_att imx_rproc_att_imx8qxp[] = {
+	{ 0x08000000, 0x08000000, 0x10000000, 0 },
+	/* TCML/U */
+	{ 0x1FFE0000, 0x34FE0000, 0x00040000, ATT_OWN | ATT_IOMEM },
+	/* OCRAM(Low 96KB) */
+	{ 0x21000000, 0x00100000, 0x00018000, 0 },
+	/* OCRAM */
+	{ 0x21100000, 0x00100000, 0x00040000, 0 },
+	/* DDR (Data) */
+	{ 0x80000000, 0x80000000, 0x60000000, 0 },
+};
+
 static const struct imx_rproc_att imx_rproc_att_imx8mn[] = {
 	/* dev addr , sys addr  , size	    , flags */
 	/* ITCM   */
@@ -255,6 +274,12 @@ static const struct imx_rproc_dcfg imx_rproc_cfg_imx8mq = {
 	.method		= IMX_RPROC_MMIO,
 };
 
+static const struct imx_rproc_dcfg imx_rproc_cfg_imx8qxp = {
+	.att		= imx_rproc_att_imx8qxp,
+	.att_size	= ARRAY_SIZE(imx_rproc_att_imx8qxp),
+	.method		= IMX_RPROC_SCU_API,
+};
+
 static const struct imx_rproc_dcfg imx_rproc_cfg_imx8ulp = {
 	.att		= imx_rproc_att_imx8ulp,
 	.att_size	= ARRAY_SIZE(imx_rproc_att_imx8ulp),
@@ -680,6 +705,37 @@ static void imx_rproc_free_mbox(struct rproc *rproc)
 	mbox_free_channel(priv->rx_ch);
 }
 
+static void imx_rproc_put_scu(struct rproc *rproc)
+{
+	struct imx_rproc *priv = rproc->priv;
+	const struct imx_rproc_dcfg *dcfg = priv->dcfg;
+
+	if (dcfg->method != IMX_RPROC_SCU_API)
+		return;
+
+	if (imx_sc_rm_is_resource_owned(priv->ipc_handle, priv->rsrc_id))
+		return;
+
+	imx_scu_irq_group_enable(IMX_SC_IRQ_GROUP_REBOOTED, BIT(priv->rproc_pt), false);
+	imx_scu_irq_unregister_notifier(&priv->rproc_nb);
+}
+
+static int imx_rproc_partition_notify(struct notifier_block *nb,
+				      unsigned long event, void *group)
+{
+	struct imx_rproc *priv = container_of(nb, struct imx_rproc, rproc_nb);
+
+	/* Ignore other irqs */
+	if (!((event & BIT(priv->rproc_pt)) && (*(u8 *)group == IMX_SC_IRQ_GROUP_REBOOTED)))
+		return 0;
+
+	rproc_report_crash(priv->rproc, RPROC_WATCHDOG);
+
+	pr_info("Partition%d reset!\n", priv->rproc_pt);
+
+	return 0;
+}
+
 static int imx_rproc_detect_mode(struct imx_rproc *priv)
 {
 	struct regmap_config config = { .name = "imx-rproc" };
@@ -689,6 +745,7 @@ static int imx_rproc_detect_mode(struct imx_rproc *priv)
 	struct arm_smccc_res res;
 	int ret;
 	u32 val;
+	u8 pt;
 
 	switch (dcfg->method) {
 	case IMX_RPROC_NONE:
@@ -699,6 +756,51 @@ static int imx_rproc_detect_mode(struct imx_rproc *priv)
 		if (res.a0)
 			priv->rproc->state = RPROC_DETACHED;
 		return 0;
+	case IMX_RPROC_SCU_API:
+		ret = imx_scu_get_handle(&priv->ipc_handle);
+		if (ret)
+			return ret;
+		ret = of_property_read_u32(dev->of_node, "fsl,resource-id", &priv->rsrc_id);
+		if (ret) {
+			dev_err(dev, "No fsl,resource-id property\n");
+			return ret;
+		}
+
+		/*
+		 * If Mcore resource is not owned by Acore partition, It is kicked by ROM,
+		 * and Linux could only do IPC with Mcore and nothing else.
+		 */
+		if (imx_sc_rm_is_resource_owned(priv->ipc_handle, priv->rsrc_id))
+			return 0;
+
+		priv->rproc->state = RPROC_DETACHED;
+		priv->rproc->recovery_disabled = true;
+
+		/* Get partition id and enable irq in SCFW */
+		ret = imx_sc_rm_get_resource_owner(priv->ipc_handle, priv->rsrc_id, &pt);
+		if (ret) {
+			dev_err(dev, "not able to get resource owner\n");
+			return ret;
+		}
+
+		priv->rproc_pt = pt;
+		priv->rproc_nb.notifier_call = imx_rproc_partition_notify;
+
+		ret = imx_scu_irq_register_notifier(&priv->rproc_nb);
+		if (ret) {
+			dev_err(dev, "register scu notifier failed, %d\n", ret);
+			return ret;
+		}
+
+		ret = imx_scu_irq_group_enable(IMX_SC_IRQ_GROUP_REBOOTED, BIT(priv->rproc_pt),
+					       true);
+		if (ret) {
+			imx_scu_irq_unregister_notifier(&priv->rproc_nb);
+			dev_err(dev, "Enable irq failed, %d\n", ret);
+			return ret;
+		}
+
+		return 0;
 	default:
 		break;
 	}
@@ -803,7 +905,7 @@ static int imx_rproc_probe(struct platform_device *pdev)
 
 	ret = imx_rproc_clk_enable(priv);
 	if (ret)
-		goto err_put_mbox;
+		goto err_put_scu;
 
 	INIT_WORK(&priv->rproc_work, imx_rproc_vq_work);
 
@@ -820,6 +922,8 @@ static int imx_rproc_probe(struct platform_device *pdev)
 
 err_put_clk:
 	clk_disable_unprepare(priv->clk);
+err_put_scu:
+	imx_rproc_put_scu(rproc);
 err_put_mbox:
 	imx_rproc_free_mbox(rproc);
 err_put_wkq:
@@ -837,6 +941,7 @@ static int imx_rproc_remove(struct platform_device *pdev)
 
 	clk_disable_unprepare(priv->clk);
 	rproc_del(rproc);
+	imx_rproc_put_scu(rproc);
 	imx_rproc_free_mbox(rproc);
 	destroy_workqueue(priv->workqueue);
 	rproc_free(rproc);
@@ -852,6 +957,7 @@ static const struct of_device_id imx_rproc_of_match[] = {
 	{ .compatible = "fsl,imx8mm-cm4", .data = &imx_rproc_cfg_imx8mq },
 	{ .compatible = "fsl,imx8mn-cm7", .data = &imx_rproc_cfg_imx8mn },
 	{ .compatible = "fsl,imx8mp-cm7", .data = &imx_rproc_cfg_imx8mn },
+	{ .compatible = "fsl,imx8qxp-cm4", .data = &imx_rproc_cfg_imx8qxp },
 	{ .compatible = "fsl,imx8ulp-cm33", .data = &imx_rproc_cfg_imx8ulp },
 	{ .compatible = "fsl,imx93-cm33", .data = &imx_rproc_cfg_imx93 },
 	{},
-- 
GitLab


From c94ea666dc81e8164de1ee4b3b564af0e7cd942b Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Fri, 21 Oct 2022 12:15:23 +0800
Subject: [PATCH 029/875] remoteproc: imx_rproc: Support kicking Mcore from
 Linux for i.MX8QXP

When M4 is in the same hardware partition with Cortex-A, it
could be start/stop by Linux.

Added power domain to make sure M4 could run, it requires several power
domains to work. Make clock always optional for i.MX8QXP, because
SCFW handles it when power up M4 core.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20221021041526.3696483-5-peng.fan@oss.nxp.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/remoteproc/imx_rproc.c | 96 ++++++++++++++++++++++++++++++++--
 1 file changed, 93 insertions(+), 3 deletions(-)

diff --git a/drivers/remoteproc/imx_rproc.c b/drivers/remoteproc/imx_rproc.c
index 5bbba69556833..372cb4a346b0d 100644
--- a/drivers/remoteproc/imx_rproc.c
+++ b/drivers/remoteproc/imx_rproc.c
@@ -16,6 +16,7 @@
 #include <linux/of_reserved_mem.h>
 #include <linux/of_device.h>
 #include <linux/platform_device.h>
+#include <linux/pm_domain.h>
 #include <linux/regmap.h>
 #include <linux/remoteproc.h>
 #include <linux/workqueue.h>
@@ -79,6 +80,8 @@ struct imx_rproc_mem {
 #define ATT_OWN		BIT(1)
 #define ATT_IOMEM	BIT(2)
 
+static int imx_rproc_detach_pd(struct rproc *rproc);
+
 struct imx_rproc {
 	struct device			*dev;
 	struct regmap			*regmap;
@@ -96,6 +99,10 @@ struct imx_rproc {
 	struct notifier_block		rproc_nb;
 	u32				rproc_pt;	/* partition id */
 	u32				rsrc_id;	/* resource id */
+	u32				entry;		/* cpu start address */
+	int                             num_pd;
+	struct device                   **pd_dev;
+	struct device_link              **pd_dev_link;
 };
 
 static const struct imx_rproc_att imx_rproc_att_imx93[] = {
@@ -335,6 +342,9 @@ static int imx_rproc_start(struct rproc *rproc)
 		arm_smccc_smc(IMX_SIP_RPROC, IMX_SIP_RPROC_START, 0, 0, 0, 0, 0, 0, &res);
 		ret = res.a0;
 		break;
+	case IMX_RPROC_SCU_API:
+		ret = imx_sc_pm_cpu_start(priv->ipc_handle, priv->rsrc_id, true, priv->entry);
+		break;
 	default:
 		return -EOPNOTSUPP;
 	}
@@ -364,6 +374,9 @@ static int imx_rproc_stop(struct rproc *rproc)
 		if (res.a1)
 			dev_info(dev, "Not in wfi, force stopped\n");
 		break;
+	case IMX_RPROC_SCU_API:
+		ret = imx_sc_pm_cpu_start(priv->ipc_handle, priv->rsrc_id, false, priv->entry);
+		break;
 	default:
 		return -EOPNOTSUPP;
 	}
@@ -713,8 +726,10 @@ static void imx_rproc_put_scu(struct rproc *rproc)
 	if (dcfg->method != IMX_RPROC_SCU_API)
 		return;
 
-	if (imx_sc_rm_is_resource_owned(priv->ipc_handle, priv->rsrc_id))
+	if (imx_sc_rm_is_resource_owned(priv->ipc_handle, priv->rsrc_id)) {
+		imx_rproc_detach_pd(rproc);
 		return;
+	}
 
 	imx_scu_irq_group_enable(IMX_SC_IRQ_GROUP_REBOOTED, BIT(priv->rproc_pt), false);
 	imx_scu_irq_unregister_notifier(&priv->rproc_nb);
@@ -736,6 +751,77 @@ static int imx_rproc_partition_notify(struct notifier_block *nb,
 	return 0;
 }
 
+static int imx_rproc_attach_pd(struct imx_rproc *priv)
+{
+	struct device *dev = priv->dev;
+	int ret, i;
+
+	/*
+	 * If there is only one power-domain entry, the platform driver framework
+	 * will handle it, no need handle it in this driver.
+	 */
+	priv->num_pd = of_count_phandle_with_args(dev->of_node, "power-domains",
+						  "#power-domain-cells");
+	if (priv->num_pd <= 1)
+		return 0;
+
+	priv->pd_dev = devm_kmalloc_array(dev, priv->num_pd, sizeof(*priv->pd_dev), GFP_KERNEL);
+	if (!priv->pd_dev)
+		return -ENOMEM;
+
+	priv->pd_dev_link = devm_kmalloc_array(dev, priv->num_pd, sizeof(*priv->pd_dev_link),
+					       GFP_KERNEL);
+
+	if (!priv->pd_dev_link)
+		return -ENOMEM;
+
+	for (i = 0; i < priv->num_pd; i++) {
+		priv->pd_dev[i] = dev_pm_domain_attach_by_id(dev, i);
+		if (IS_ERR(priv->pd_dev[i])) {
+			ret = PTR_ERR(priv->pd_dev[i]);
+			goto detach_pd;
+		}
+
+		priv->pd_dev_link[i] = device_link_add(dev, priv->pd_dev[i], DL_FLAG_STATELESS |
+						       DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE);
+		if (!priv->pd_dev_link[i]) {
+			dev_pm_domain_detach(priv->pd_dev[i], false);
+			ret = -EINVAL;
+			goto detach_pd;
+		}
+	}
+
+	return 0;
+
+detach_pd:
+	while (--i >= 0) {
+		device_link_del(priv->pd_dev_link[i]);
+		dev_pm_domain_detach(priv->pd_dev[i], false);
+	}
+
+	return ret;
+}
+
+static int imx_rproc_detach_pd(struct rproc *rproc)
+{
+	struct imx_rproc *priv = rproc->priv;
+	int i;
+
+	/*
+	 * If there is only one power-domain entry, the platform driver framework
+	 * will handle it, no need handle it in this driver.
+	 */
+	if (priv->num_pd <= 1)
+		return 0;
+
+	for (i = 0; i < priv->num_pd; i++) {
+		device_link_del(priv->pd_dev_link[i]);
+		dev_pm_domain_detach(priv->pd_dev[i], false);
+	}
+
+	return 0;
+}
+
 static int imx_rproc_detect_mode(struct imx_rproc *priv)
 {
 	struct regmap_config config = { .name = "imx-rproc" };
@@ -770,8 +856,12 @@ static int imx_rproc_detect_mode(struct imx_rproc *priv)
 		 * If Mcore resource is not owned by Acore partition, It is kicked by ROM,
 		 * and Linux could only do IPC with Mcore and nothing else.
 		 */
-		if (imx_sc_rm_is_resource_owned(priv->ipc_handle, priv->rsrc_id))
-			return 0;
+		if (imx_sc_rm_is_resource_owned(priv->ipc_handle, priv->rsrc_id)) {
+			if (of_property_read_u32(dev->of_node, "fsl,entry-address", &priv->entry))
+				return -EINVAL;
+
+			return imx_rproc_attach_pd(priv);
+		}
 
 		priv->rproc->state = RPROC_DETACHED;
 		priv->rproc->recovery_disabled = true;
-- 
GitLab


From fcd382b23dcf16732964aca491660da676c3c44f Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Fri, 21 Oct 2022 12:15:24 +0800
Subject: [PATCH 030/875] remoteproc: imx_rproc: Support i.MX8QM

Most logic are same as i.MX8QXP, but i.MX8QM has two general purpose
M4 cores, the two cores runs independently and they have different resource
id, different start address from SCFW view.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20221021041526.3696483-6-peng.fan@oss.nxp.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/remoteproc/imx_rproc.c | 47 +++++++++++++++++++++++++++++++---
 1 file changed, 44 insertions(+), 3 deletions(-)

diff --git a/drivers/remoteproc/imx_rproc.c b/drivers/remoteproc/imx_rproc.c
index 372cb4a346b0d..917e6db395729 100644
--- a/drivers/remoteproc/imx_rproc.c
+++ b/drivers/remoteproc/imx_rproc.c
@@ -3,6 +3,7 @@
  * Copyright (c) 2017 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
  */
 
+#include <dt-bindings/firmware/imx/rsrc.h>
 #include <linux/arm-smccc.h>
 #include <linux/clk.h>
 #include <linux/err.h>
@@ -75,10 +76,13 @@ struct imx_rproc_mem {
 	size_t size;
 };
 
-/* att flags */
+/* att flags: lower 16 bits specifying core, higher 16 bits for flags  */
 /* M4 own area. Can be mapped at probe */
-#define ATT_OWN		BIT(1)
-#define ATT_IOMEM	BIT(2)
+#define ATT_OWN         BIT(31)
+#define ATT_IOMEM       BIT(30)
+
+#define ATT_CORE_MASK   0xffff
+#define ATT_CORE(I)     BIT((I))
 
 static int imx_rproc_detach_pd(struct rproc *rproc);
 
@@ -101,6 +105,7 @@ struct imx_rproc {
 	u32				rsrc_id;	/* resource id */
 	u32				entry;		/* cpu start address */
 	int                             num_pd;
+	u32				core_index;
 	struct device                   **pd_dev;
 	struct device_link              **pd_dev_link;
 };
@@ -131,6 +136,19 @@ static const struct imx_rproc_att imx_rproc_att_imx93[] = {
 	{ 0xD0000000, 0xa0000000, 0x10000000, 0 },
 };
 
+static const struct imx_rproc_att imx_rproc_att_imx8qm[] = {
+	/* dev addr , sys addr  , size      , flags */
+	{ 0x08000000, 0x08000000, 0x10000000, 0},
+	/* TCML */
+	{ 0x1FFE0000, 0x34FE0000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(0)},
+	{ 0x1FFE0000, 0x38FE0000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(1)},
+	/* TCMU */
+	{ 0x20000000, 0x35000000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(0)},
+	{ 0x20000000, 0x39000000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(1)},
+	/* DDR (Data) */
+	{ 0x80000000, 0x80000000, 0x60000000, 0 },
+};
+
 static const struct imx_rproc_att imx_rproc_att_imx8qxp[] = {
 	{ 0x08000000, 0x08000000, 0x10000000, 0 },
 	/* TCML/U */
@@ -281,6 +299,12 @@ static const struct imx_rproc_dcfg imx_rproc_cfg_imx8mq = {
 	.method		= IMX_RPROC_MMIO,
 };
 
+static const struct imx_rproc_dcfg imx_rproc_cfg_imx8qm = {
+	.att            = imx_rproc_att_imx8qm,
+	.att_size       = ARRAY_SIZE(imx_rproc_att_imx8qm),
+	.method         = IMX_RPROC_SCU_API,
+};
+
 static const struct imx_rproc_dcfg imx_rproc_cfg_imx8qxp = {
 	.att		= imx_rproc_att_imx8qxp,
 	.att_size	= ARRAY_SIZE(imx_rproc_att_imx8qxp),
@@ -397,6 +421,17 @@ static int imx_rproc_da_to_sys(struct imx_rproc *priv, u64 da,
 	for (i = 0; i < dcfg->att_size; i++) {
 		const struct imx_rproc_att *att = &dcfg->att[i];
 
+		/*
+		 * Ignore entries not belong to current core:
+		 * i.MX8QM has dual general M4_[0,1] cores, M4_0's own entries
+		 * has "ATT_CORE(0) & BIT(0)" true, M4_1's own entries has
+		 * "ATT_CORE(1) & BIT(1)" true.
+		 */
+		if (att->flags & ATT_CORE_MASK) {
+			if (!((BIT(priv->core_index)) & (att->flags & ATT_CORE_MASK)))
+				continue;
+		}
+
 		if (da >= att->da && da + len < att->da + att->size) {
 			unsigned int offset = da - att->da;
 
@@ -852,6 +887,11 @@ static int imx_rproc_detect_mode(struct imx_rproc *priv)
 			return ret;
 		}
 
+		if (priv->rsrc_id == IMX_SC_R_M4_1_PID0)
+			priv->core_index = 1;
+		else
+			priv->core_index = 0;
+
 		/*
 		 * If Mcore resource is not owned by Acore partition, It is kicked by ROM,
 		 * and Linux could only do IPC with Mcore and nothing else.
@@ -1048,6 +1088,7 @@ static const struct of_device_id imx_rproc_of_match[] = {
 	{ .compatible = "fsl,imx8mn-cm7", .data = &imx_rproc_cfg_imx8mn },
 	{ .compatible = "fsl,imx8mp-cm7", .data = &imx_rproc_cfg_imx8mn },
 	{ .compatible = "fsl,imx8qxp-cm4", .data = &imx_rproc_cfg_imx8qxp },
+	{ .compatible = "fsl,imx8qm-cm4", .data = &imx_rproc_cfg_imx8qm },
 	{ .compatible = "fsl,imx8ulp-cm33", .data = &imx_rproc_cfg_imx8ulp },
 	{ .compatible = "fsl,imx93-cm33", .data = &imx_rproc_cfg_imx93 },
 	{},
-- 
GitLab


From 99b142cf7191b08adcd23f700ea0a3d7dffdd0c1 Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Fri, 21 Oct 2022 12:15:25 +0800
Subject: [PATCH 031/875] remoteproc: imx_rproc: Request mbox channel later

It is possible that when remote processor crash, the communication
channel will be broken with garbage value in mailbox, such as
when Linux is issuing a message through mailbox, remote processor
crashes, we need free & rebuild the mailbox channels to make sure
no garbage value in mailbox channels.

So move the request/free to start/stop for managing remote procesosr in
Linux, move to attach/detach for remote processor is out of control of
Linux.

Previous, we just request mbox when attach for CM4 boot early before
Linux, but if mbox defer probe, remoteproc core will do resource cleanup
and corrupt resource table for later probe.

So move request mbox ealier and still keep mbox request when attach
for self recovery case, but keep a check when request/free mbox.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20221021041526.3696483-7-peng.fan@oss.nxp.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/remoteproc/imx_rproc.c | 48 ++++++++++++++++++++++++++++++++--
 1 file changed, 46 insertions(+), 2 deletions(-)

diff --git a/drivers/remoteproc/imx_rproc.c b/drivers/remoteproc/imx_rproc.c
index 917e6db395729..dda4e8a12adf1 100644
--- a/drivers/remoteproc/imx_rproc.c
+++ b/drivers/remoteproc/imx_rproc.c
@@ -84,6 +84,8 @@ struct imx_rproc_mem {
 #define ATT_CORE_MASK   0xffff
 #define ATT_CORE(I)     BIT((I))
 
+static int imx_rproc_xtr_mbox_init(struct rproc *rproc);
+static void imx_rproc_free_mbox(struct rproc *rproc);
 static int imx_rproc_detach_pd(struct rproc *rproc);
 
 struct imx_rproc {
@@ -357,6 +359,10 @@ static int imx_rproc_start(struct rproc *rproc)
 	struct arm_smccc_res res;
 	int ret;
 
+	ret = imx_rproc_xtr_mbox_init(rproc);
+	if (ret)
+		return ret;
+
 	switch (dcfg->method) {
 	case IMX_RPROC_MMIO:
 		ret = regmap_update_bits(priv->regmap, dcfg->src_reg, dcfg->src_mask,
@@ -407,6 +413,8 @@ static int imx_rproc_stop(struct rproc *rproc)
 
 	if (ret)
 		dev_err(dev, "Failed to stop remote core\n");
+	else
+		imx_rproc_free_mbox(rproc);
 
 	return ret;
 }
@@ -592,6 +600,22 @@ static void imx_rproc_kick(struct rproc *rproc, int vqid)
 
 static int imx_rproc_attach(struct rproc *rproc)
 {
+	return imx_rproc_xtr_mbox_init(rproc);
+}
+
+static int imx_rproc_detach(struct rproc *rproc)
+{
+	struct imx_rproc *priv = rproc->priv;
+	const struct imx_rproc_dcfg *dcfg = priv->dcfg;
+
+	if (dcfg->method != IMX_RPROC_SCU_API)
+		return -EOPNOTSUPP;
+
+	if (imx_sc_rm_is_resource_owned(priv->ipc_handle, priv->rsrc_id))
+		return -EOPNOTSUPP;
+
+	imx_rproc_free_mbox(rproc);
+
 	return 0;
 }
 
@@ -610,6 +634,7 @@ static struct resource_table *imx_rproc_get_loaded_rsc_table(struct rproc *rproc
 static const struct rproc_ops imx_rproc_ops = {
 	.prepare	= imx_rproc_prepare,
 	.attach		= imx_rproc_attach,
+	.detach		= imx_rproc_detach,
 	.start		= imx_rproc_start,
 	.stop		= imx_rproc_stop,
 	.kick		= imx_rproc_kick,
@@ -720,6 +745,18 @@ static int imx_rproc_xtr_mbox_init(struct rproc *rproc)
 	struct device *dev = priv->dev;
 	struct mbox_client *cl;
 
+	/*
+	 * stop() and detach() will free the mbox channels, so need
+	 * to request mbox channels in start() and attach().
+	 *
+	 * Because start() and attach() not able to handle mbox defer
+	 * probe, imx_rproc_xtr_mbox_init is also called in probe().
+	 * The check is to avoid request mbox again when start() or
+	 * attach() after probe() returns success.
+	 */
+	if (priv->tx_ch && priv->rx_ch)
+		return 0;
+
 	if (!of_get_property(dev->of_node, "mbox-names", NULL))
 		return 0;
 
@@ -749,8 +786,15 @@ static void imx_rproc_free_mbox(struct rproc *rproc)
 {
 	struct imx_rproc *priv = rproc->priv;
 
-	mbox_free_channel(priv->tx_ch);
-	mbox_free_channel(priv->rx_ch);
+	if (priv->tx_ch) {
+		mbox_free_channel(priv->tx_ch);
+		priv->tx_ch = NULL;
+	}
+
+	if (priv->rx_ch) {
+		mbox_free_channel(priv->rx_ch);
+		priv->rx_ch = NULL;
+	}
 }
 
 static void imx_rproc_put_scu(struct rproc *rproc)
-- 
GitLab


From 6eed169c7fefd9cdbbccb5ba7a98470cc0c09c63 Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Fri, 21 Oct 2022 12:15:26 +0800
Subject: [PATCH 032/875] remoteproc: imx_rproc: Enable attach recovery for
 i.MX8QM/QXP

i.MX8QM/QXP M4 could recover without help from Linux, so to support it:
 - enable feature RPROC_FEAT_ATTACH_ON_RECOVERY
 - set recovery_disabled as false

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20221021041526.3696483-8-peng.fan@oss.nxp.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/remoteproc/imx_rproc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/remoteproc/imx_rproc.c b/drivers/remoteproc/imx_rproc.c
index dda4e8a12adf1..2c471e46f4ca8 100644
--- a/drivers/remoteproc/imx_rproc.c
+++ b/drivers/remoteproc/imx_rproc.c
@@ -948,7 +948,8 @@ static int imx_rproc_detect_mode(struct imx_rproc *priv)
 		}
 
 		priv->rproc->state = RPROC_DETACHED;
-		priv->rproc->recovery_disabled = true;
+		priv->rproc->recovery_disabled = false;
+		rproc_set_feature(priv->rproc, RPROC_FEAT_ATTACH_ON_RECOVERY);
 
 		/* Get partition id and enable irq in SCFW */
 		ret = imx_sc_rm_get_resource_owner(priv->ipc_handle, priv->rsrc_id, &pt);
-- 
GitLab


From 0d6d7c61ffeedc782b651a080ad6543ad45314b6 Mon Sep 17 00:00:00 2001
From: Nathan Chancellor <nathan@kernel.org>
Date: Tue, 4 Oct 2022 07:41:45 -0700
Subject: [PATCH 033/875] fs/ntfs3: Don't use uni1 uninitialized in
 ntfs_d_compare()

Clang warns:

  fs/ntfs3/namei.c:445:7: error: variable 'uni1' is used uninitialized whenever 'if' condition is true [-Werror,-Wsometimes-uninitialized]
                  if (toupper(c1) != toupper(c2)) {
                      ^~~~~~~~~~~~~~~~~~~~~~~~~~
  ./include/linux/ctype.h:64:20: note: expanded from macro 'toupper'
  #define toupper(c) __toupper(c)
                    ^
  fs/ntfs3/namei.c:487:12: note: uninitialized use occurs here
          __putname(uni1);
                    ^~~~
  ./include/linux/fs.h:2789:65: note: expanded from macro '__putname'
  #define __putname(name)         kmem_cache_free(names_cachep, (void *)(name))
                                                                        ^~~~
  fs/ntfs3/namei.c:445:3: note: remove the 'if' if its condition is always false
                  if (toupper(c1) != toupper(c2)) {
                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  fs/ntfs3/namei.c:434:7: error: variable 'uni1' is used uninitialized whenever 'if' condition is true [-Werror,-Wsometimes-uninitialized]
                  if (!lm--) {
                      ^~~~~
  fs/ntfs3/namei.c:487:12: note: uninitialized use occurs here
          __putname(uni1);
                    ^~~~
  ./include/linux/fs.h:2789:65: note: expanded from macro '__putname'
  #define __putname(name)         kmem_cache_free(names_cachep, (void *)(name))
                                                                        ^~~~
  fs/ntfs3/namei.c:434:3: note: remove the 'if' if its condition is always false
                  if (!lm--) {
                  ^~~~~~~~~~~~
  fs/ntfs3/namei.c:430:22: note: initialize the variable 'uni1' to silence this warning
          struct cpu_str *uni1, *uni2;
                              ^
                              = NULL
  2 errors generated.

There is no point in calling __putname() in these particular error
paths, as there has been no corresponding __getname() call yet. Just
return directly in these blocks to clear up the warning.

Fixes: a3a956c78efa ("fs/ntfs3: Add option "nocase"")
Link: https://github.com/ClangBuiltLinux/linux/issues/1729
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/namei.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/fs/ntfs3/namei.c b/fs/ntfs3/namei.c
index 315763eb05ff2..5d3a6ce3f05f4 100644
--- a/fs/ntfs3/namei.c
+++ b/fs/ntfs3/namei.c
@@ -431,10 +431,8 @@ static int ntfs_d_compare(const struct dentry *dentry, unsigned int len1,
 
 	/* First try fast implementation. */
 	for (;;) {
-		if (!lm--) {
-			ret = len1 == len2 ? 0 : 1;
-			goto out;
-		}
+		if (!lm--)
+			return len1 == len2 ? 0 : 1;
 
 		if ((c1 = *n1++) == (c2 = *n2++))
 			continue;
@@ -442,10 +440,8 @@ static int ntfs_d_compare(const struct dentry *dentry, unsigned int len1,
 		if (c1 >= 0x80 || c2 >= 0x80)
 			break;
 
-		if (toupper(c1) != toupper(c2)) {
-			ret = 1;
-			goto out;
-		}
+		if (toupper(c1) != toupper(c2))
+			return 1;
 	}
 
 	/*
-- 
GitLab


From f271946117dde2ca8741b8138b347b2d68e6ad56 Mon Sep 17 00:00:00 2001
From: Jon Hunter <jonathanh@nvidia.com>
Date: Fri, 28 Oct 2022 13:33:55 +0100
Subject: [PATCH 034/875] pwm: tegra: Improve required rate calculation
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

For the case where dev_pm_opp_set_rate() is called to set the PWM clock
rate, the requested rate is calculated as ...

 required_clk_rate = (NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH;

The above calculation may lead to rounding errors because the
NSEC_PER_SEC is divided by 'period_ns' before applying the
PWM_DUTY_WIDTH multiplication factor. For example, if the period is
45334ns, the above calculation yields a rate of 5646848Hz instead of
5646976Hz. Fix this by applying the multiplication factor before
dividing and using the DIV_ROUND_UP macro which yields the expected
result of 5646976Hz.

Fixes: 1d7796bdb63a ("pwm: tegra: Support dynamic clock frequency configuration")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-tegra.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index dad9978c91861..b05ea2e8acccb 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -145,8 +145,8 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 		 * source clock rate as required_clk_rate, PWM controller will
 		 * be able to configure the requested period.
 		 */
-		required_clk_rate =
-			(NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH;
+		required_clk_rate = DIV_ROUND_UP_ULL(NSEC_PER_SEC << PWM_DUTY_WIDTH,
+						     period_ns);
 
 		err = dev_pm_opp_set_rate(pc->dev, required_clk_rate);
 		if (err < 0)
-- 
GitLab


From 5eccd0d9fabc4d2ab8d2a0c056fb1d7e2ff892fc Mon Sep 17 00:00:00 2001
From: Jon Hunter <jonathanh@nvidia.com>
Date: Fri, 28 Oct 2022 13:33:56 +0100
Subject: [PATCH 035/875] pwm: tegra: Ensure the clock rate is not less than
 needed
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When dynamically scaling the PWM clock, the function
dev_pm_opp_set_rate() may set the PWM clock to a rate that is lower than
what is required. The clock rate requested when calling
dev_pm_opp_set_rate() is the minimum clock rate that is needed to drive
the PWM to achieve the required period. Hence, if the actual clock
rate is less than the requested clock rate, then the required period
cannot be achieved and configuring the PWM fails. Fix this by
calling clk_round_rate() to check if the clock rate that will be provided
is sufficient and if not, double the required clock rate to ensure the
required period can be attained.

Fixes: 8c193f4714df ("pwm: tegra: Optimize period calculation")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-tegra.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index b05ea2e8acccb..6fc4b69a3ba71 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -148,6 +148,17 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 		required_clk_rate = DIV_ROUND_UP_ULL(NSEC_PER_SEC << PWM_DUTY_WIDTH,
 						     period_ns);
 
+		if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate))
+			/*
+			 * required_clk_rate is a lower bound for the input
+			 * rate; for lower rates there is no value for PWM_SCALE
+			 * that yields a period less than or equal to the
+			 * requested period. Hence, for lower rates, double the
+			 * required_clk_rate to get a clock rate that can meet
+			 * the requested period.
+			 */
+			required_clk_rate *= 2;
+
 		err = dev_pm_opp_set_rate(pc->dev, required_clk_rate);
 		if (err < 0)
 			return -EINVAL;
-- 
GitLab


From dd1f1da4ada5d8ac774c2ebe97230637820b3323 Mon Sep 17 00:00:00 2001
From: Steven Price <steven.price@arm.com>
Date: Thu, 10 Nov 2022 11:45:48 +0000
Subject: [PATCH 036/875] pwm: tegra: Fix 32 bit build
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The value of NSEC_PER_SEC << PWM_DUTY_WIDTH doesn't fix within a 32 bit
integer causing a build warning/error (and the value truncated):

  drivers/pwm/pwm-tegra.c: In function ‘tegra_pwm_config’:
  drivers/pwm/pwm-tegra.c:148:53: error: result of ‘1000000000 << 8’ requires 39 bits to represent, but ‘long int’ only has 32 bits [-Werror=shift-overflow=]
    148 |   required_clk_rate = DIV_ROUND_UP_ULL(NSEC_PER_SEC << PWM_DUTY_WIDTH,
        |                                                     ^~

Explicitly cast to a u64 to ensure the correct result.

Fixes: cfcb68817fb3 ("pwm: tegra: Improve required rate calculation")
Signed-off-by: Steven Price <steven.price@arm.com>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
---
 drivers/pwm/pwm-tegra.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 6fc4b69a3ba71..249dc01932979 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -145,7 +145,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 		 * source clock rate as required_clk_rate, PWM controller will
 		 * be able to configure the requested period.
 		 */
-		required_clk_rate = DIV_ROUND_UP_ULL(NSEC_PER_SEC << PWM_DUTY_WIDTH,
+		required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH,
 						     period_ns);
 
 		if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate))
-- 
GitLab


From bfcdbae0523bd95eb75a739ffb6221a37109881e Mon Sep 17 00:00:00 2001
From: Edward Lo <edward.lo@ambergroup.io>
Date: Fri, 30 Sep 2022 09:58:40 +0800
Subject: [PATCH 037/875] fs/ntfs3: Validate index root when initialize NTFS
 security

This enhances the sanity check for $SDH and $SII while initializing NTFS
security, guarantees these index root are legit.

[  162.459513] BUG: KASAN: use-after-free in hdr_find_e.isra.0+0x10c/0x320
[  162.460176] Read of size 2 at addr ffff8880037bca99 by task mount/243
[  162.460851]
[  162.461252] CPU: 0 PID: 243 Comm: mount Not tainted 6.0.0-rc7 #42
[  162.461744] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org 04/01/2014
[  162.462609] Call Trace:
[  162.462954]  <TASK>
[  162.463276]  dump_stack_lvl+0x49/0x63
[  162.463822]  print_report.cold+0xf5/0x689
[  162.464608]  ? unwind_get_return_address+0x3a/0x60
[  162.465766]  ? hdr_find_e.isra.0+0x10c/0x320
[  162.466975]  kasan_report+0xa7/0x130
[  162.467506]  ? _raw_spin_lock_irq+0xc0/0xf0
[  162.467998]  ? hdr_find_e.isra.0+0x10c/0x320
[  162.468536]  __asan_load2+0x68/0x90
[  162.468923]  hdr_find_e.isra.0+0x10c/0x320
[  162.469282]  ? cmp_uints+0xe0/0xe0
[  162.469557]  ? cmp_sdh+0x90/0x90
[  162.469864]  ? ni_find_attr+0x214/0x300
[  162.470217]  ? ni_load_mi+0x80/0x80
[  162.470479]  ? entry_SYSCALL_64_after_hwframe+0x63/0xcd
[  162.470931]  ? ntfs_bread_run+0x190/0x190
[  162.471307]  ? indx_get_root+0xe4/0x190
[  162.471556]  ? indx_get_root+0x140/0x190
[  162.471833]  ? indx_init+0x1e0/0x1e0
[  162.472069]  ? fnd_clear+0x115/0x140
[  162.472363]  ? _raw_spin_lock_irqsave+0x100/0x100
[  162.472731]  indx_find+0x184/0x470
[  162.473461]  ? sysvec_apic_timer_interrupt+0x57/0xc0
[  162.474429]  ? indx_find_buffer+0x2d0/0x2d0
[  162.474704]  ? do_syscall_64+0x3b/0x90
[  162.474962]  dir_search_u+0x196/0x2f0
[  162.475381]  ? ntfs_nls_to_utf16+0x450/0x450
[  162.475661]  ? ntfs_security_init+0x3d6/0x440
[  162.475906]  ? is_sd_valid+0x180/0x180
[  162.476191]  ntfs_extend_init+0x13f/0x2c0
[  162.476496]  ? ntfs_fix_post_read+0x130/0x130
[  162.476861]  ? iput.part.0+0x286/0x320
[  162.477325]  ntfs_fill_super+0x11e0/0x1b50
[  162.477709]  ? put_ntfs+0x1d0/0x1d0
[  162.477970]  ? vsprintf+0x20/0x20
[  162.478258]  ? set_blocksize+0x95/0x150
[  162.478538]  get_tree_bdev+0x232/0x370
[  162.478789]  ? put_ntfs+0x1d0/0x1d0
[  162.479038]  ntfs_fs_get_tree+0x15/0x20
[  162.479374]  vfs_get_tree+0x4c/0x130
[  162.479729]  path_mount+0x654/0xfe0
[  162.480124]  ? putname+0x80/0xa0
[  162.480484]  ? finish_automount+0x2e0/0x2e0
[  162.480894]  ? putname+0x80/0xa0
[  162.481467]  ? kmem_cache_free+0x1c4/0x440
[  162.482280]  ? putname+0x80/0xa0
[  162.482714]  do_mount+0xd6/0xf0
[  162.483264]  ? path_mount+0xfe0/0xfe0
[  162.484782]  ? __kasan_check_write+0x14/0x20
[  162.485593]  __x64_sys_mount+0xca/0x110
[  162.486024]  do_syscall_64+0x3b/0x90
[  162.486543]  entry_SYSCALL_64_after_hwframe+0x63/0xcd
[  162.487141] RIP: 0033:0x7f9d374e948a
[  162.488324] Code: 48 8b 0d 11 fa 2a 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 49 89 ca b8 a5 00 00 008
[  162.489728] RSP: 002b:00007ffe30e73d18 EFLAGS: 00000206 ORIG_RAX: 00000000000000a5
[  162.490971] RAX: ffffffffffffffda RBX: 0000561cdb43a060 RCX: 00007f9d374e948a
[  162.491669] RDX: 0000561cdb43a260 RSI: 0000561cdb43a2e0 RDI: 0000561cdb442af0
[  162.492050] RBP: 0000000000000000 R08: 0000561cdb43a280 R09: 0000000000000020
[  162.492459] R10: 00000000c0ed0000 R11: 0000000000000206 R12: 0000561cdb442af0
[  162.493183] R13: 0000561cdb43a260 R14: 0000000000000000 R15: 00000000ffffffff
[  162.493644]  </TASK>
[  162.493908]
[  162.494214] The buggy address belongs to the physical page:
[  162.494761] page:000000003e38a3d5 refcount:0 mapcount:0 mapping:0000000000000000 index:0x0 pfn:0x37bc
[  162.496064] flags: 0xfffffc0000000(node=0|zone=1|lastcpupid=0x1fffff)
[  162.497278] raw: 000fffffc0000000 ffffea00000df1c8 ffffea00000df008 0000000000000000
[  162.498928] raw: 0000000000000000 0000000000240000 00000000ffffffff 0000000000000000
[  162.500542] page dumped because: kasan: bad access detected
[  162.501057]
[  162.501242] Memory state around the buggy address:
[  162.502230]  ffff8880037bc980: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
[  162.502977]  ffff8880037bca00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
[  162.503522] >ffff8880037bca80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
[  162.503963]                             ^
[  162.504370]  ffff8880037bcb00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
[  162.504766]  ffff8880037bcb80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff

Signed-off-by: Edward Lo <edward.lo@ambergroup.io>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/fsntfs.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/fs/ntfs3/fsntfs.c b/fs/ntfs3/fsntfs.c
index 4ed15f64b17f6..b6e22bcb929ba 100644
--- a/fs/ntfs3/fsntfs.c
+++ b/fs/ntfs3/fsntfs.c
@@ -1849,9 +1849,10 @@ int ntfs_security_init(struct ntfs_sb_info *sbi)
 		goto out;
 	}
 
-	root_sdh = resident_data(attr);
+	root_sdh = resident_data_ex(attr, sizeof(struct INDEX_ROOT));
 	if (root_sdh->type != ATTR_ZERO ||
-	    root_sdh->rule != NTFS_COLLATION_TYPE_SECURITY_HASH) {
+	    root_sdh->rule != NTFS_COLLATION_TYPE_SECURITY_HASH ||
+	    offsetof(struct INDEX_ROOT, ihdr) + root_sdh->ihdr.used > attr->res.data_size) {
 		err = -EINVAL;
 		goto out;
 	}
@@ -1867,9 +1868,10 @@ int ntfs_security_init(struct ntfs_sb_info *sbi)
 		goto out;
 	}
 
-	root_sii = resident_data(attr);
+	root_sii = resident_data_ex(attr, sizeof(struct INDEX_ROOT));
 	if (root_sii->type != ATTR_ZERO ||
-	    root_sii->rule != NTFS_COLLATION_TYPE_UINT) {
+	    root_sii->rule != NTFS_COLLATION_TYPE_UINT ||
+	    offsetof(struct INDEX_ROOT, ihdr) + root_sii->ihdr.used > attr->res.data_size) {
 		err = -EINVAL;
 		goto out;
 	}
-- 
GitLab


From 557d19675a470bb0a98beccec38c5dc3735c20fa Mon Sep 17 00:00:00 2001
From: Abdun Nihaal <abdun.nihaal@gmail.com>
Date: Sat, 1 Oct 2022 12:30:24 +0530
Subject: [PATCH 038/875] fs/ntfs3: Fix slab-out-of-bounds read in ntfs_trim_fs

Syzbot reports an out of bound access in ntfs_trim_fs.
The cause of this is using a loop termination condition that compares
window index (iw) with wnd->nbits instead of wnd->nwnd, due to which the
index used for wnd->free_bits exceeds the size of the array allocated.

Fix the loop condition.

Fixes: 3f3b442b5ad2 ("fs/ntfs3: Add bitmap")
Link: https://syzkaller.appspot.com/bug?extid=b892240eac461e488d51
Reported-by: syzbot+b892240eac461e488d51@syzkaller.appspotmail.com
Signed-off-by: Abdun Nihaal <abdun.nihaal@gmail.com>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/bitmap.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/ntfs3/bitmap.c b/fs/ntfs3/bitmap.c
index 1675c9a697884..629c1ee97268a 100644
--- a/fs/ntfs3/bitmap.c
+++ b/fs/ntfs3/bitmap.c
@@ -1424,7 +1424,7 @@ int ntfs_trim_fs(struct ntfs_sb_info *sbi, struct fstrim_range *range)
 
 	down_read_nested(&wnd->rw_lock, BITMAP_MUTEX_CLUSTERS);
 
-	for (; iw < wnd->nbits; iw++, wbit = 0) {
+	for (; iw < wnd->nwnd; iw++, wbit = 0) {
 		CLST lcn_wnd = iw * wbits;
 		struct buffer_head *bh;
 
-- 
GitLab


From 0d0f659bf713662fabed973f9996b8f23c59ca51 Mon Sep 17 00:00:00 2001
From: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp>
Date: Sun, 2 Oct 2022 23:39:15 +0900
Subject: [PATCH 039/875] fs/ntfs3: Use __GFP_NOWARN allocation at wnd_init()

syzbot is reporting too large allocation at wnd_init() [1], for a crafted
filesystem can become wnd->nwnd close to UINT_MAX. Add __GFP_NOWARN in
order to avoid too large allocation warning, than exhausting memory by
using kvcalloc().

Link: https://syzkaller.appspot.com/bug?extid=fa4648a5446460b7b963 [1]
Reported-by: syzot <syzbot+fa4648a5446460b7b963@syzkaller.appspotmail.com>
Signed-off-by: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/bitmap.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/ntfs3/bitmap.c b/fs/ntfs3/bitmap.c
index 629c1ee97268a..badaaaf302ddf 100644
--- a/fs/ntfs3/bitmap.c
+++ b/fs/ntfs3/bitmap.c
@@ -661,7 +661,7 @@ int wnd_init(struct wnd_bitmap *wnd, struct super_block *sb, size_t nbits)
 	if (!wnd->bits_last)
 		wnd->bits_last = wbits;
 
-	wnd->free_bits = kcalloc(wnd->nwnd, sizeof(u16), GFP_NOFS);
+	wnd->free_bits = kcalloc(wnd->nwnd, sizeof(u16), GFP_NOFS | __GFP_NOWARN);
 	if (!wnd->free_bits)
 		return -ENOMEM;
 
-- 
GitLab


From 59bfd7a483da36bd202532a3d9ea1f14f3bf3aaf Mon Sep 17 00:00:00 2001
From: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp>
Date: Sun, 2 Oct 2022 23:54:11 +0900
Subject: [PATCH 040/875] fs/ntfs3: Use __GFP_NOWARN allocation at
 ntfs_fill_super()

syzbot is reporting too large allocation at ntfs_fill_super() [1], for a
crafted filesystem can contain bogus inode->i_size. Add __GFP_NOWARN in
order to avoid too large allocation warning, than exhausting memory by
using kvmalloc().

Link: https://syzkaller.appspot.com/bug?extid=33f3faaa0c08744f7d40 [1]
Reported-by: syzot <syzbot+33f3faaa0c08744f7d40@syzkaller.appspotmail.com>
Signed-off-by: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/super.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/ntfs3/super.c b/fs/ntfs3/super.c
index 1e2c04e48f98f..2fd1367a59820 100644
--- a/fs/ntfs3/super.c
+++ b/fs/ntfs3/super.c
@@ -1167,7 +1167,7 @@ static int ntfs_fill_super(struct super_block *sb, struct fs_context *fc)
 		goto put_inode_out;
 	}
 	bytes = inode->i_size;
-	sbi->def_table = t = kmalloc(bytes, GFP_NOFS);
+	sbi->def_table = t = kmalloc(bytes, GFP_NOFS | __GFP_NOWARN);
 	if (!t) {
 		err = -ENOMEM;
 		goto put_inode_out;
-- 
GitLab


From 019d22eb0eb707fc099e6e8fad9b3933236a06d0 Mon Sep 17 00:00:00 2001
From: Abdun Nihaal <abdun.nihaal@gmail.com>
Date: Tue, 4 Oct 2022 08:45:02 +0530
Subject: [PATCH 041/875] fs/ntfs3: Validate attribute data and valid sizes

The data_size and valid_size fields of non resident attributes should be
less than the its alloc_size field, but this is not checked in
ntfs_read_mft function.

Syzbot reports a allocation order warning due to a large unchecked value
of data_size getting assigned to inode->i_size which is then passed to
kcalloc.

Add sanity check for ensuring that the data_size and valid_size fields
are not larger than alloc_size field.

Link: https://syzkaller.appspot.com/bug?extid=fa4648a5446460b7b963
Reported-and-tested-by: syzbot+fa4648a5446460b7b963@syzkaller.appspotmail.com
Fixes: (82cae269cfa95) fs/ntfs3: Add initialization of super block
Signed-off-by: Abdun Nihaal <abdun.nihaal@gmail.com>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/inode.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/fs/ntfs3/inode.c b/fs/ntfs3/inode.c
index e9cf00d147331..9c244029be753 100644
--- a/fs/ntfs3/inode.c
+++ b/fs/ntfs3/inode.c
@@ -132,6 +132,13 @@ next_attr:
 	if (le16_to_cpu(attr->name_off) + attr->name_len > asize)
 		goto out;
 
+	if (attr->non_res) {
+		t64 = le64_to_cpu(attr->nres.alloc_size);
+		if (le64_to_cpu(attr->nres.data_size) > t64 ||
+		    le64_to_cpu(attr->nres.valid_size) > t64)
+			goto out;
+	}
+
 	switch (attr->type) {
 	case ATTR_STD:
 		if (attr->non_res ||
-- 
GitLab


From 75b5e47201329537c8b88531a59aab2cbcec8d61 Mon Sep 17 00:00:00 2001
From: Nathan Chancellor <nathan@kernel.org>
Date: Tue, 4 Oct 2022 16:23:59 -0700
Subject: [PATCH 042/875] fs/ntfs3: Eliminate unnecessary ternary operator in
 ntfs_d_compare()

'a == b ? 0 : 1' is logically equivalent to 'a != b'.

Suggested-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/namei.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/ntfs3/namei.c b/fs/ntfs3/namei.c
index 5d3a6ce3f05f4..6b0d2c01d6ffc 100644
--- a/fs/ntfs3/namei.c
+++ b/fs/ntfs3/namei.c
@@ -432,7 +432,7 @@ static int ntfs_d_compare(const struct dentry *dentry, unsigned int len1,
 	/* First try fast implementation. */
 	for (;;) {
 		if (!lm--)
-			return len1 == len2 ? 0 : 1;
+			return len1 != len2;
 
 		if ((c1 = *n1++) == (c2 = *n2++))
 			continue;
-- 
GitLab


From 1d07a9dfa19914ad27bdb9ec9ac0baa2329b2ae3 Mon Sep 17 00:00:00 2001
From: Daniel Pinto <danielpinto52@gmail.com>
Date: Mon, 10 Oct 2022 12:14:31 +0100
Subject: [PATCH 043/875] fs/ntfs3: Add windows_names mount option

When enabled, the windows_names mount option prevents the creation
of files or directories with names not allowed by Windows. Use
the same option name as NTFS-3G for compatibility.

Signed-off-by: Daniel Pinto <danielpinto52@gmail.com>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/frecord.c |   7 ++-
 fs/ntfs3/fsntfs.c  | 104 +++++++++++++++++++++++++++++++++++++++++++++
 fs/ntfs3/inode.c   |   7 +++
 fs/ntfs3/ntfs_fs.h |   2 +
 fs/ntfs3/super.c   |   7 +++
 5 files changed, 126 insertions(+), 1 deletion(-)

diff --git a/fs/ntfs3/frecord.c b/fs/ntfs3/frecord.c
index 70a80f9412f77..ce5e8f3b1acab 100644
--- a/fs/ntfs3/frecord.c
+++ b/fs/ntfs3/frecord.c
@@ -3011,6 +3011,7 @@ int ni_add_name(struct ntfs_inode *dir_ni, struct ntfs_inode *ni,
 		struct NTFS_DE *de)
 {
 	int err;
+	struct ntfs_sb_info *sbi = ni->mi.sbi;
 	struct ATTRIB *attr;
 	struct ATTR_LIST_ENTRY *le;
 	struct mft_inode *mi;
@@ -3018,6 +3019,10 @@ int ni_add_name(struct ntfs_inode *dir_ni, struct ntfs_inode *ni,
 	struct ATTR_FILE_NAME *de_name = (struct ATTR_FILE_NAME *)(de + 1);
 	u16 de_key_size = le16_to_cpu(de->key_size);
 
+	if (sbi->options->windows_names &&
+	    !valid_windows_name(sbi, (struct le_str *)&de_name->name_len))
+		return -EINVAL;
+
 	mi_get_ref(&ni->mi, &de->ref);
 	mi_get_ref(&dir_ni->mi, &de_name->home);
 
@@ -3036,7 +3041,7 @@ int ni_add_name(struct ntfs_inode *dir_ni, struct ntfs_inode *ni,
 	memcpy(Add2Ptr(attr, SIZEOF_RESIDENT), de_name, de_key_size);
 
 	/* Insert new name into directory. */
-	err = indx_insert_entry(&dir_ni->dir, dir_ni, de, ni->mi.sbi, NULL, 0);
+	err = indx_insert_entry(&dir_ni->dir, dir_ni, de, sbi, NULL, 0);
 	if (err)
 		ni_remove_attr_le(ni, attr, mi, le);
 
diff --git a/fs/ntfs3/fsntfs.c b/fs/ntfs3/fsntfs.c
index b6e22bcb929ba..0992fb2e4eb74 100644
--- a/fs/ntfs3/fsntfs.c
+++ b/fs/ntfs3/fsntfs.c
@@ -98,6 +98,30 @@ const __le16 WOF_NAME[17] = {
 };
 #endif
 
+static const __le16 CON_NAME[3] = {
+	cpu_to_le16('C'), cpu_to_le16('O'), cpu_to_le16('N'),
+};
+
+static const __le16 NUL_NAME[3] = {
+	cpu_to_le16('N'), cpu_to_le16('U'), cpu_to_le16('L'),
+};
+
+static const __le16 AUX_NAME[3] = {
+	cpu_to_le16('A'), cpu_to_le16('U'), cpu_to_le16('X'),
+};
+
+static const __le16 PRN_NAME[3] = {
+	cpu_to_le16('P'), cpu_to_le16('R'), cpu_to_le16('N'),
+};
+
+static const __le16 COM_NAME[3] = {
+	cpu_to_le16('C'), cpu_to_le16('O'), cpu_to_le16('M'),
+};
+
+static const __le16 LPT_NAME[3] = {
+	cpu_to_le16('L'), cpu_to_le16('P'), cpu_to_le16('T'),
+};
+
 // clang-format on
 
 /*
@@ -2504,3 +2528,83 @@ int run_deallocate(struct ntfs_sb_info *sbi, struct runs_tree *run, bool trim)
 
 	return 0;
 }
+
+static inline bool name_has_forbidden_chars(const struct le_str *fname)
+{
+	int i, ch;
+
+	/* check for forbidden chars */
+	for (i = 0; i < fname->len; ++i) {
+		ch = le16_to_cpu(fname->name[i]);
+
+		/* control chars */
+		if (ch < 0x20)
+			return true;
+
+		switch (ch) {
+		/* disallowed by Windows */
+		case '\\':
+		case '/':
+		case ':':
+		case '*':
+		case '?':
+		case '<':
+		case '>':
+		case '|':
+		case '\"':
+			return true;
+
+		default:
+			/* allowed char */
+			break;
+		}
+	}
+
+	/* file names cannot end with space or . */
+	if (fname->len > 0) {
+		ch = le16_to_cpu(fname->name[fname->len - 1]);
+		if (ch == ' ' || ch == '.')
+			return true;
+	}
+
+	return false;
+}
+
+static inline bool is_reserved_name(struct ntfs_sb_info *sbi,
+				    const struct le_str *fname)
+{
+	int port_digit;
+	const __le16 *name = fname->name;
+	int len = fname->len;
+	u16 *upcase = sbi->upcase;
+
+	/* check for 3 chars reserved names (device names) */
+	/* name by itself or with any extension is forbidden */
+	if (len == 3 || (len > 3 && le16_to_cpu(name[3]) == '.'))
+		if (!ntfs_cmp_names(name, 3, CON_NAME, 3, upcase, false) ||
+		    !ntfs_cmp_names(name, 3, NUL_NAME, 3, upcase, false) ||
+		    !ntfs_cmp_names(name, 3, AUX_NAME, 3, upcase, false) ||
+		    !ntfs_cmp_names(name, 3, PRN_NAME, 3, upcase, false))
+			return true;
+
+	/* check for 4 chars reserved names (port name followed by 1..9) */
+	/* name by itself or with any extension is forbidden */
+	if (len == 4 || (len > 4 && le16_to_cpu(name[4]) == '.')) {
+		port_digit = le16_to_cpu(name[3]);
+		if (port_digit >= '1' && port_digit <= '9')
+			if (!ntfs_cmp_names(name, 3, COM_NAME, 3, upcase, false) ||
+			    !ntfs_cmp_names(name, 3, LPT_NAME, 3, upcase, false))
+				return true;
+	}
+
+	return false;
+}
+
+/*
+ * valid_windows_name - Check if a file name is valid in Windows.
+ */
+bool valid_windows_name(struct ntfs_sb_info *sbi, const struct le_str *fname)
+{
+	return !name_has_forbidden_chars(fname) &&
+	       !is_reserved_name(sbi, fname);
+}
diff --git a/fs/ntfs3/inode.c b/fs/ntfs3/inode.c
index 9c244029be753..a2522fc41240f 100644
--- a/fs/ntfs3/inode.c
+++ b/fs/ntfs3/inode.c
@@ -1368,6 +1368,13 @@ struct inode *ntfs_create_inode(struct user_namespace *mnt_userns,
 	mi_get_ref(&ni->mi, &new_de->ref);
 
 	fname = (struct ATTR_FILE_NAME *)(new_de + 1);
+
+	if (sbi->options->windows_names &&
+	    !valid_windows_name(sbi, (struct le_str *)&fname->name_len)) {
+		err = -EINVAL;
+		goto out4;
+	}
+
 	mi_get_ref(&dir_ni->mi, &fname->home);
 	fname->dup.cr_time = fname->dup.m_time = fname->dup.c_time =
 		fname->dup.a_time = std5->cr_time;
diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h
index 6c1c7ef3b2d6a..ebfb720fc4fd3 100644
--- a/fs/ntfs3/ntfs_fs.h
+++ b/fs/ntfs3/ntfs_fs.h
@@ -98,6 +98,7 @@ struct ntfs_mount_options {
 	unsigned showmeta : 1; /* Show meta files. */
 	unsigned nohidden : 1; /* Do not show hidden files. */
 	unsigned hide_dot_files : 1; /* Set hidden flag on dot files. */
+	unsigned windows_names : 1; /* Disallow names forbidden by Windows. */
 	unsigned force : 1; /* RW mount dirty volume. */
 	unsigned noacsrules : 1; /* Exclude acs rules. */
 	unsigned prealloc : 1; /* Preallocate space when file is growing. */
@@ -645,6 +646,7 @@ int ntfs_remove_reparse(struct ntfs_sb_info *sbi, __le32 rtag,
 			const struct MFT_REF *ref);
 void mark_as_free_ex(struct ntfs_sb_info *sbi, CLST lcn, CLST len, bool trim);
 int run_deallocate(struct ntfs_sb_info *sbi, struct runs_tree *run, bool trim);
+bool valid_windows_name(struct ntfs_sb_info *sbi, const struct le_str *name);
 
 /* Globals from index.c */
 int indx_used_bit(struct ntfs_index *indx, struct ntfs_inode *ni, size_t *bit);
diff --git a/fs/ntfs3/super.c b/fs/ntfs3/super.c
index 2fd1367a59820..a91852b17c2d1 100644
--- a/fs/ntfs3/super.c
+++ b/fs/ntfs3/super.c
@@ -248,6 +248,7 @@ enum Opt {
 	Opt_sparse,
 	Opt_nohidden,
 	Opt_hide_dot_files,
+	Opt_windows_names,
 	Opt_showmeta,
 	Opt_acl,
 	Opt_iocharset,
@@ -269,6 +270,7 @@ static const struct fs_parameter_spec ntfs_fs_parameters[] = {
 	fsparam_flag_no("sparse",		Opt_sparse),
 	fsparam_flag_no("hidden",		Opt_nohidden),
 	fsparam_flag_no("hidedotfiles",		Opt_hide_dot_files),
+	fsparam_flag_no("windows_names",	Opt_windows_names),
 	fsparam_flag_no("acl",			Opt_acl),
 	fsparam_flag_no("showmeta",		Opt_showmeta),
 	fsparam_flag_no("prealloc",		Opt_prealloc),
@@ -361,6 +363,9 @@ static int ntfs_fs_parse_param(struct fs_context *fc,
 	case Opt_hide_dot_files:
 		opts->hide_dot_files = result.negated ? 1 : 0;
 		break;
+	case Opt_windows_names:
+		opts->windows_names = result.negated ? 0 : 1;
+		break;
 	case Opt_acl:
 		if (!result.negated)
 #ifdef CONFIG_NTFS3_FS_POSIX_ACL
@@ -561,6 +566,8 @@ static int ntfs_show_options(struct seq_file *m, struct dentry *root)
 		seq_puts(m, ",showmeta");
 	if (opts->nohidden)
 		seq_puts(m, ",nohidden");
+	if (opts->windows_names)
+		seq_puts(m, ",windows_names");
 	if (opts->force)
 		seq_puts(m, ",force");
 	if (opts->noacsrules)
-- 
GitLab


From d683c67c5f50802b9b14ea29d89d66a25327e965 Mon Sep 17 00:00:00 2001
From: Daniel Pinto <danielpinto52@gmail.com>
Date: Mon, 10 Oct 2022 12:16:29 +0100
Subject: [PATCH 044/875] fs/ntfs3: Document windows_names mount option

Add documentation for windows_names mount option.

Signed-off-by: Daniel Pinto <danielpinto52@gmail.com>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 Documentation/filesystems/ntfs3.rst | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/filesystems/ntfs3.rst b/Documentation/filesystems/ntfs3.rst
index d67ccd22c63b1..cda8e0e010d45 100644
--- a/Documentation/filesystems/ntfs3.rst
+++ b/Documentation/filesystems/ntfs3.rst
@@ -75,6 +75,14 @@ this table marked with no it means default is without **no**.
      - Files with the Windows-specific SYSTEM (FILE_ATTRIBUTE_SYSTEM) attribute
        will be marked as system immutable files.
 
+   * - windows_names
+     - Prevents the creation of files and directories with a name not allowed
+       by Windows, either because it contains some not allowed character (which
+       are the characters " * / : < > ? \\ | and those whose code is less than
+       0x20), because the name (with or without extension) is a reserved file
+       name (CON, AUX, NUL, PRN, LPT1-9, COM1-9) or because the last character
+       is a space or a dot. Existing such files can still be read and renamed.
+
    * - discard
      - Enable support of the TRIM command for improved performance on delete
        operations, which is recommended for use with the solid-state drives
-- 
GitLab


From 4c9ba192c73f52dc1d549fcfeb109b725fea8950 Mon Sep 17 00:00:00 2001
From: Daniel Pinto <danielpinto52@gmail.com>
Date: Mon, 10 Oct 2022 12:30:15 +0100
Subject: [PATCH 045/875] fs/ntfs3: Fix hidedotfiles mount option by reversing
 behaviour

Currently, the hidedotfiles mount option is behaving in the reverse
way of what would be expected: enabling it disables setting the
hidden attribute on files or directories with names starting with a
dot and disabling it enables the setting.

Reverse the behaviour of the hidedotfiles mount option so it matches
what is expected.

Signed-off-by: Daniel Pinto <danielpinto52@gmail.com>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/super.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/ntfs3/super.c b/fs/ntfs3/super.c
index a91852b17c2d1..0207cafbab08e 100644
--- a/fs/ntfs3/super.c
+++ b/fs/ntfs3/super.c
@@ -361,7 +361,7 @@ static int ntfs_fs_parse_param(struct fs_context *fc,
 		opts->nohidden = result.negated ? 1 : 0;
 		break;
 	case Opt_hide_dot_files:
-		opts->hide_dot_files = result.negated ? 1 : 0;
+		opts->hide_dot_files = result.negated ? 0 : 1;
 		break;
 	case Opt_windows_names:
 		opts->windows_names = result.negated ? 0 : 1;
-- 
GitLab


From 66223324cba4290ba45c612fe1e31a265636ad2d Mon Sep 17 00:00:00 2001
From: Daniel Pinto <danielpinto52@gmail.com>
Date: Mon, 10 Oct 2022 12:32:12 +0100
Subject: [PATCH 046/875] fs/ntfs3: Make hidedotfiles mount option work when
 renaming files

Currently, the hidedotfiles mount option only has an effect when
creating new files. Removing or adding the starting dot when moving
or renaming files does not update the hidden attribute.

Make hidedotfiles also set or uset the hidden attribute when a file
gains or loses its starting dot by being moved or renamed.

Signed-off-by: Daniel Pinto <danielpinto52@gmail.com>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/frecord.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/fs/ntfs3/frecord.c b/fs/ntfs3/frecord.c
index ce5e8f3b1acab..392efa0270f85 100644
--- a/fs/ntfs3/frecord.c
+++ b/fs/ntfs3/frecord.c
@@ -3023,6 +3023,15 @@ int ni_add_name(struct ntfs_inode *dir_ni, struct ntfs_inode *ni,
 	    !valid_windows_name(sbi, (struct le_str *)&de_name->name_len))
 		return -EINVAL;
 
+	/* If option "hidedotfiles" then set hidden attribute for dot files. */
+	if (ni->mi.sbi->options->hide_dot_files) {
+		if (de_name->name_len > 0 &&
+		    le16_to_cpu(de_name->name[0]) == '.')
+			ni->std_fa |= FILE_ATTRIBUTE_HIDDEN;
+		else
+			ni->std_fa &= ~FILE_ATTRIBUTE_HIDDEN;
+	}
+
 	mi_get_ref(&ni->mi, &de->ref);
 	mi_get_ref(&dir_ni->mi, &de_name->home);
 
-- 
GitLab


From 19b424501d8588a3111e50fa3d7d926594e78449 Mon Sep 17 00:00:00 2001
From: Daniel Pinto <danielpinto52@gmail.com>
Date: Mon, 10 Oct 2022 12:34:06 +0100
Subject: [PATCH 047/875] fs/ntfs3: Add hidedotfiles to the list of enabled
 mount options

Currently, the ntfs3 driver does return the hidedotfiles mount
option in the list of enabled mount options. This can confuse
users who may doubt they enabled the option when not seeing in
the list provided by the mount command.

Add hidedotfiles mount option to the list of enabled options
provided by the mount command when it is enabled.

Signed-off-by: Daniel Pinto <danielpinto52@gmail.com>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/super.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/fs/ntfs3/super.c b/fs/ntfs3/super.c
index 0207cafbab08e..464703701ed49 100644
--- a/fs/ntfs3/super.c
+++ b/fs/ntfs3/super.c
@@ -568,6 +568,8 @@ static int ntfs_show_options(struct seq_file *m, struct dentry *root)
 		seq_puts(m, ",nohidden");
 	if (opts->windows_names)
 		seq_puts(m, ",windows_names");
+	if (opts->hide_dot_files)
+		seq_puts(m, ",hidedotfiles");
 	if (opts->force)
 		seq_puts(m, ",force");
 	if (opts->noacsrules)
-- 
GitLab


From 60adc860ca7d7a95d5befd2d3c3e644d23706b2c Mon Sep 17 00:00:00 2001
From: Daniel Pinto <danielpinto52@gmail.com>
Date: Mon, 10 Oct 2022 12:35:46 +0100
Subject: [PATCH 048/875] fs/ntfs3: Document the hidedotfiles mount option

Add documentation for the hidedotfiles mount option.

Signed-off-by: Daniel Pinto <danielpinto52@gmail.com>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 Documentation/filesystems/ntfs3.rst | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/filesystems/ntfs3.rst b/Documentation/filesystems/ntfs3.rst
index cda8e0e010d45..3a20ecd13d45e 100644
--- a/Documentation/filesystems/ntfs3.rst
+++ b/Documentation/filesystems/ntfs3.rst
@@ -75,6 +75,12 @@ this table marked with no it means default is without **no**.
      - Files with the Windows-specific SYSTEM (FILE_ATTRIBUTE_SYSTEM) attribute
        will be marked as system immutable files.
 
+   * - hidedotfiles
+     - Updates the Windows-specific HIDDEN (FILE_ATTRIBUTE_HIDDEN) attribute
+       when creating and moving or renaming files. Files whose names start
+       with a dot will have the HIDDEN attribute set and files whose names
+       do not start with a dot will have it unset.
+
    * - windows_names
      - Prevents the creation of files and directories with a name not allowed
        by Windows, either because it contains some not allowed character (which
-- 
GitLab


From dc0fcc99b1756c3c703326aa0015ed73fc4e9a73 Mon Sep 17 00:00:00 2001
From: Daniel Pinto <danielpinto52@gmail.com>
Date: Mon, 10 Oct 2022 12:37:13 +0100
Subject: [PATCH 049/875] fs/ntfs3: Rename hidedotfiles mount option to
 hide_dot_files

The hidedotfiles mount option provides the same functionality as
the NTFS-3G hide_dot_files mount option. As such, it should be
named the same for compatibility with NTGS-3G.

Rename the hidedotfiles to hide_dot_files for compatbility with
NTFS-3G.

Signed-off-by: Daniel Pinto <danielpinto52@gmail.com>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 Documentation/filesystems/ntfs3.rst | 2 +-
 fs/ntfs3/frecord.c                  | 2 +-
 fs/ntfs3/inode.c                    | 2 +-
 fs/ntfs3/super.c                    | 4 ++--
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/Documentation/filesystems/ntfs3.rst b/Documentation/filesystems/ntfs3.rst
index 3a20ecd13d45e..7b1e78cf01ad9 100644
--- a/Documentation/filesystems/ntfs3.rst
+++ b/Documentation/filesystems/ntfs3.rst
@@ -75,7 +75,7 @@ this table marked with no it means default is without **no**.
      - Files with the Windows-specific SYSTEM (FILE_ATTRIBUTE_SYSTEM) attribute
        will be marked as system immutable files.
 
-   * - hidedotfiles
+   * - hide_dot_files
      - Updates the Windows-specific HIDDEN (FILE_ATTRIBUTE_HIDDEN) attribute
        when creating and moving or renaming files. Files whose names start
        with a dot will have the HIDDEN attribute set and files whose names
diff --git a/fs/ntfs3/frecord.c b/fs/ntfs3/frecord.c
index 392efa0270f85..3b309b9a5e293 100644
--- a/fs/ntfs3/frecord.c
+++ b/fs/ntfs3/frecord.c
@@ -3023,7 +3023,7 @@ int ni_add_name(struct ntfs_inode *dir_ni, struct ntfs_inode *ni,
 	    !valid_windows_name(sbi, (struct le_str *)&de_name->name_len))
 		return -EINVAL;
 
-	/* If option "hidedotfiles" then set hidden attribute for dot files. */
+	/* If option "hide_dot_files" then set hidden attribute for dot files. */
 	if (ni->mi.sbi->options->hide_dot_files) {
 		if (de_name->name_len > 0 &&
 		    le16_to_cpu(de_name->name[0]) == '.')
diff --git a/fs/ntfs3/inode.c b/fs/ntfs3/inode.c
index a2522fc41240f..3977e98e3fa35 100644
--- a/fs/ntfs3/inode.c
+++ b/fs/ntfs3/inode.c
@@ -1279,7 +1279,7 @@ struct inode *ntfs_create_inode(struct user_namespace *mnt_userns,
 		fa = FILE_ATTRIBUTE_ARCHIVE;
 	}
 
-	/* If option "hidedotfiles" then set hidden attribute for dot files. */
+	/* If option "hide_dot_files" then set hidden attribute for dot files. */
 	if (sbi->options->hide_dot_files && name->name[0] == '.')
 		fa |= FILE_ATTRIBUTE_HIDDEN;
 
diff --git a/fs/ntfs3/super.c b/fs/ntfs3/super.c
index 464703701ed49..59a831bd0c9b4 100644
--- a/fs/ntfs3/super.c
+++ b/fs/ntfs3/super.c
@@ -269,7 +269,7 @@ static const struct fs_parameter_spec ntfs_fs_parameters[] = {
 	fsparam_flag_no("force",		Opt_force),
 	fsparam_flag_no("sparse",		Opt_sparse),
 	fsparam_flag_no("hidden",		Opt_nohidden),
-	fsparam_flag_no("hidedotfiles",		Opt_hide_dot_files),
+	fsparam_flag_no("hide_dot_files",	Opt_hide_dot_files),
 	fsparam_flag_no("windows_names",	Opt_windows_names),
 	fsparam_flag_no("acl",			Opt_acl),
 	fsparam_flag_no("showmeta",		Opt_showmeta),
@@ -569,7 +569,7 @@ static int ntfs_show_options(struct seq_file *m, struct dentry *root)
 	if (opts->windows_names)
 		seq_puts(m, ",windows_names");
 	if (opts->hide_dot_files)
-		seq_puts(m, ",hidedotfiles");
+		seq_puts(m, ",hide_dot_files");
 	if (opts->force)
 		seq_puts(m, ",force");
 	if (opts->noacsrules)
-- 
GitLab


From 0d19f3d71394b0b03b8775c958b3354fa2259609 Mon Sep 17 00:00:00 2001
From: Daniel Pinto <danielpinto52@gmail.com>
Date: Mon, 10 Oct 2022 12:44:27 +0100
Subject: [PATCH 050/875] fs/ntfs3: Add system.ntfs_attrib_be extended
 attribute

NTFS-3G provides the system.ntfs_attrib_be extended attribute, which
has the same value as system.ntfs_attrib but represented in big-endian.
Some utilities rely on the existence of this extended attribute.

Improves compatibility with NTFS-3G by adding the system.ntfs_attrib_be
extended attribute.

Signed-off-by: Daniel Pinto <danielpinto52@gmail.com>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/xattr.c | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/fs/ntfs3/xattr.c b/fs/ntfs3/xattr.c
index aeee5fb120925..8620a7b4b3e63 100644
--- a/fs/ntfs3/xattr.c
+++ b/fs/ntfs3/xattr.c
@@ -15,9 +15,10 @@
 #include "ntfs_fs.h"
 
 // clang-format off
-#define SYSTEM_DOS_ATTRIB    "system.dos_attrib"
-#define SYSTEM_NTFS_ATTRIB   "system.ntfs_attrib"
-#define SYSTEM_NTFS_SECURITY "system.ntfs_security"
+#define SYSTEM_DOS_ATTRIB     "system.dos_attrib"
+#define SYSTEM_NTFS_ATTRIB    "system.ntfs_attrib"
+#define SYSTEM_NTFS_ATTRIB_BE "system.ntfs_attrib_be"
+#define SYSTEM_NTFS_SECURITY  "system.ntfs_security"
 // clang-format on
 
 static inline size_t unpacked_ea_size(const struct EA_FULL *ea)
@@ -796,7 +797,8 @@ static int ntfs_getxattr(const struct xattr_handler *handler, struct dentry *de,
 		goto out;
 	}
 
-	if (!strcmp(name, SYSTEM_NTFS_ATTRIB)) {
+	if (!strcmp(name, SYSTEM_NTFS_ATTRIB) ||
+	    !strcmp(name, SYSTEM_NTFS_ATTRIB_BE)) {
 		/* system.ntfs_attrib */
 		if (!buffer) {
 			err = sizeof(u32);
@@ -805,6 +807,8 @@ static int ntfs_getxattr(const struct xattr_handler *handler, struct dentry *de,
 		} else {
 			err = sizeof(u32);
 			*(u32 *)buffer = le32_to_cpu(ni->std_fa);
+			if (!strcmp(name, SYSTEM_NTFS_ATTRIB_BE))
+				*(u32 *)buffer = cpu_to_be32(*(u32 *)buffer);
 		}
 		goto out;
 	}
@@ -889,10 +893,14 @@ static noinline int ntfs_setxattr(const struct xattr_handler *handler,
 		goto set_new_fa;
 	}
 
-	if (!strcmp(name, SYSTEM_NTFS_ATTRIB)) {
+	if (!strcmp(name, SYSTEM_NTFS_ATTRIB) ||
+	    !strcmp(name, SYSTEM_NTFS_ATTRIB_BE)) {
 		if (size != sizeof(u32))
 			goto out;
-		new_fa = cpu_to_le32(*(u32 *)value);
+		if (!strcmp(name, SYSTEM_NTFS_ATTRIB_BE))
+			new_fa = cpu_to_le32(be32_to_cpu(*(u32 *)value));
+		else
+			new_fa = cpu_to_le32(*(u32 *)value);
 
 		if (S_ISREG(inode->i_mode)) {
 			/* Process compressed/sparsed in special way. */
-- 
GitLab


From d49436c34448e01eb6ab85413af87de73c99494d Mon Sep 17 00:00:00 2001
From: Daniel Pinto <danielpinto52@gmail.com>
Date: Mon, 10 Oct 2022 12:46:12 +0100
Subject: [PATCH 051/875] fs/ntfs3: Document system.ntfs_attrib_be extended
 attribute

Add documentation for system.ntfs_attrib_be extended attribute.

Signed-off-by: Daniel Pinto <danielpinto52@gmail.com>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 Documentation/filesystems/ntfs3.rst | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/filesystems/ntfs3.rst b/Documentation/filesystems/ntfs3.rst
index 7b1e78cf01ad9..5aa102bd72c2f 100644
--- a/Documentation/filesystems/ntfs3.rst
+++ b/Documentation/filesystems/ntfs3.rst
@@ -25,6 +25,11 @@ versions up to 3.1. File system type to use on mount is *ntfs3*.
 	  Note: Applied to empty files, this allows to switch type between
 	  sparse(0x200), compressed(0x800) and normal.
 
+	- *system.ntfs_attrib_be* gets/sets ntfs file/dir attributes.
+
+	  Same value as system.ntfs_attrib but always represent as big-endian
+	  (endianness of system.ntfs_attrib is the same as of the CPU).
+
 Mount Options
 =============
 
-- 
GitLab


From 658015167a8432b88f5d032e9d85d8fd50e5bf2c Mon Sep 17 00:00:00 2001
From: Dan Carpenter <dan.carpenter@oracle.com>
Date: Sat, 15 Oct 2022 11:28:55 +0300
Subject: [PATCH 052/875] fs/ntfs3: Delete duplicate condition in
 ntfs_read_mft()

There were two patches which addressed the same bug and added the same
condition:

commit 6db620863f85 ("fs/ntfs3: Validate data run offset")
commit 887bfc546097 ("fs/ntfs3: Fix slab-out-of-bounds read in run_unpack")

Delete one condition.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/inode.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/fs/ntfs3/inode.c b/fs/ntfs3/inode.c
index 3977e98e3fa35..763dd982a43a7 100644
--- a/fs/ntfs3/inode.c
+++ b/fs/ntfs3/inode.c
@@ -381,12 +381,6 @@ attr_unpack_run:
 
 	t64 = le64_to_cpu(attr->nres.svcn);
 
-	/* offset to packed runs is out-of-bounds */
-	if (roff > asize) {
-		err = -EINVAL;
-		goto out;
-	}
-
 	err = run_unpack_ex(run, sbi, ino, t64, le64_to_cpu(attr->nres.evcn),
 			    t64, Add2Ptr(attr, roff), asize - roff);
 	if (err < 0)
-- 
GitLab


From ecfbd57cf9c5ca225184ae266ce44ae473792132 Mon Sep 17 00:00:00 2001
From: Yin Xiujiang <yinxiujiang@kylinos.cn>
Date: Mon, 6 Dec 2021 10:40:45 +0800
Subject: [PATCH 053/875] fs/ntfs3: Fix slab-out-of-bounds in r_page

When PAGE_SIZE is 64K, if read_log_page is called by log_read_rst for
the first time, the size of *buffer would be equal to
DefaultLogPageSize(4K).But for *buffer operations like memcpy,
if the memory area size(n) which being assigned to buffer is larger
than 4K (log->page_size(64K) or bytes(64K-page_off)), it will cause
an out of boundary error.
 Call trace:
  [...]
  kasan_report+0x44/0x130
  check_memory_region+0xf8/0x1a0
  memcpy+0xc8/0x100
  ntfs_read_run_nb+0x20c/0x460
  read_log_page+0xd0/0x1f4
  log_read_rst+0x110/0x75c
  log_replay+0x1e8/0x4aa0
  ntfs_loadlog_and_replay+0x290/0x2d0
  ntfs_fill_super+0x508/0xec0
  get_tree_bdev+0x1fc/0x34c
  [...]

Fix this by setting variable r_page to NULL in log_read_rst.

Signed-off-by: Yin Xiujiang <yinxiujiang@kylinos.cn>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/fslog.c | 26 ++------------------------
 1 file changed, 2 insertions(+), 24 deletions(-)

diff --git a/fs/ntfs3/fslog.c b/fs/ntfs3/fslog.c
index d94c071324a8f..54bdbed03e541 100644
--- a/fs/ntfs3/fslog.c
+++ b/fs/ntfs3/fslog.c
@@ -1132,7 +1132,7 @@ static int read_log_page(struct ntfs_log *log, u32 vbo,
 		return -EINVAL;
 
 	if (!*buffer) {
-		to_free = kmalloc(bytes, GFP_NOFS);
+		to_free = kmalloc(log->page_size, GFP_NOFS);
 		if (!to_free)
 			return -ENOMEM;
 		*buffer = to_free;
@@ -1180,10 +1180,7 @@ static int log_read_rst(struct ntfs_log *log, u32 l_size, bool first,
 			struct restart_info *info)
 {
 	u32 skip, vbo;
-	struct RESTART_HDR *r_page = kmalloc(DefaultLogPageSize, GFP_NOFS);
-
-	if (!r_page)
-		return -ENOMEM;
+	struct RESTART_HDR *r_page = NULL;
 
 	/* Determine which restart area we are looking for. */
 	if (first) {
@@ -1197,7 +1194,6 @@ static int log_read_rst(struct ntfs_log *log, u32 l_size, bool first,
 	/* Loop continuously until we succeed. */
 	for (; vbo < l_size; vbo = 2 * vbo + skip, skip = 0) {
 		bool usa_error;
-		u32 sys_page_size;
 		bool brst, bchk;
 		struct RESTART_AREA *ra;
 
@@ -1251,24 +1247,6 @@ static int log_read_rst(struct ntfs_log *log, u32 l_size, bool first,
 			goto check_result;
 		}
 
-		/* Read the entire restart area. */
-		sys_page_size = le32_to_cpu(r_page->sys_page_size);
-		if (DefaultLogPageSize != sys_page_size) {
-			kfree(r_page);
-			r_page = kzalloc(sys_page_size, GFP_NOFS);
-			if (!r_page)
-				return -ENOMEM;
-
-			if (read_log_page(log, vbo,
-					  (struct RECORD_PAGE_HDR **)&r_page,
-					  &usa_error)) {
-				/* Ignore any errors. */
-				kfree(r_page);
-				r_page = NULL;
-				continue;
-			}
-		}
-
 		if (is_client_area_valid(r_page, usa_error)) {
 			info->valid_page = true;
 			ra = Add2Ptr(r_page, le16_to_cpu(r_page->ra_off));
-- 
GitLab


From 90c1cd540cc81023c5826891f3793ea159c4562e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thomas=20K=C3=BChnel?= <thomas.kuehnel@avm.de>
Date: Tue, 7 Dec 2021 11:24:53 +0100
Subject: [PATCH 054/875] fs/ntfs3: Fix endian conversion in ni_fname_name
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

ni_fname_name called ntfs_cmp_names_cpu which assumes that the first
string is in CPU byte order and the second one in little endian.
In this case both strings are little endian so ntfs_cmp_names is the
correct function to call.

Signed-off-by: Thomas Kühnel <thomas.kuehnel@avm.de>
Reviewed-by: Nicolas Schier <n.schier@avm.de>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/frecord.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/fs/ntfs3/frecord.c b/fs/ntfs3/frecord.c
index 3b309b9a5e293..039247ab5b0b7 100644
--- a/fs/ntfs3/frecord.c
+++ b/fs/ntfs3/frecord.c
@@ -1645,6 +1645,7 @@ struct ATTR_FILE_NAME *ni_fname_name(struct ntfs_inode *ni,
 {
 	struct ATTRIB *attr = NULL;
 	struct ATTR_FILE_NAME *fname;
+       struct le_str *fns;
 
 	if (le)
 		*le = NULL;
@@ -1668,7 +1669,8 @@ next:
 	if (uni->len != fname->name_len)
 		goto next;
 
-	if (ntfs_cmp_names_cpu(uni, (struct le_str *)&fname->name_len, NULL,
+	fns = (struct le_str *)&fname->name_len;
+	if (ntfs_cmp_names(uni->name, uni->len, fns->name, fns->len, NULL,
 			       false))
 		goto next;
 
-- 
GitLab


From 88a8d0d2482f60596eec875ba5ba62901d8274ff Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thomas=20K=C3=BChnel?= <thomas.kuehnel@avm.de>
Date: Tue, 7 Dec 2021 11:24:54 +0100
Subject: [PATCH 055/875] fs/ntfs3: Add functions to modify LE bitmaps
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

__bitmap_set/__bitmap_clear only works with bitmaps in CPU order.
Define a variant of these functions in ntfs3 to handle modifying bitmaps
read from the filesystem.

Signed-off-by: Thomas Kühnel <thomas.kuehnel@avm.de>
Reviewed-by: Nicolas Schier <n.schier@avm.de>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/bitmap.c  | 46 +++++++++++++++++++++++++++++++++++++++++++---
 fs/ntfs3/fslog.c   |  4 ++--
 fs/ntfs3/ntfs_fs.h |  3 +++
 3 files changed, 48 insertions(+), 5 deletions(-)

diff --git a/fs/ntfs3/bitmap.c b/fs/ntfs3/bitmap.c
index badaaaf302ddf..c114983b248e3 100644
--- a/fs/ntfs3/bitmap.c
+++ b/fs/ntfs3/bitmap.c
@@ -736,7 +736,7 @@ int wnd_set_free(struct wnd_bitmap *wnd, size_t bit, size_t bits)
 
 		lock_buffer(bh);
 
-		__bitmap_clear(buf, wbit, op);
+		ntfs_bitmap_clear_le(buf, wbit, op);
 
 		wnd->free_bits[iw] += op;
 
@@ -788,7 +788,7 @@ int wnd_set_used(struct wnd_bitmap *wnd, size_t bit, size_t bits)
 
 		lock_buffer(bh);
 
-		__bitmap_set(buf, wbit, op);
+		ntfs_bitmap_set_le(buf, wbit, op);
 		wnd->free_bits[iw] -= op;
 
 		set_buffer_uptodate(bh);
@@ -1363,7 +1363,7 @@ int wnd_extend(struct wnd_bitmap *wnd, size_t new_bits)
 		lock_buffer(bh);
 		buf = (ulong *)bh->b_data;
 
-		__bitmap_clear(buf, b0, blocksize * 8 - b0);
+		ntfs_bitmap_clear_le(buf, b0, blocksize * 8 - b0);
 		frb = wbits - __bitmap_weight(buf, wbits);
 		wnd->total_zeroes += frb - wnd->free_bits[iw];
 		wnd->free_bits[iw] = frb;
@@ -1481,3 +1481,43 @@ out:
 
 	return err;
 }
+
+void ntfs_bitmap_set_le(unsigned long *map, unsigned int start, int len)
+{
+	unsigned long *p = map + BIT_WORD(start);
+	const unsigned int size = start + len;
+	int bits_to_set = BITS_PER_LONG - (start % BITS_PER_LONG);
+	unsigned long mask_to_set = cpu_to_le32(BITMAP_FIRST_WORD_MASK(start));
+
+	while (len - bits_to_set >= 0) {
+		*p |= mask_to_set;
+		len -= bits_to_set;
+		bits_to_set = BITS_PER_LONG;
+		mask_to_set = ~0UL;
+		p++;
+	}
+	if (len) {
+		mask_to_set &= cpu_to_le32(BITMAP_LAST_WORD_MASK(size));
+		*p |= mask_to_set;
+	}
+}
+
+void ntfs_bitmap_clear_le(unsigned long *map, unsigned int start, int len)
+{
+	unsigned long *p = map + BIT_WORD(start);
+	const unsigned int size = start + len;
+	int bits_to_clear = BITS_PER_LONG - (start % BITS_PER_LONG);
+	unsigned long mask_to_clear = cpu_to_le32(BITMAP_FIRST_WORD_MASK(start));
+
+	while (len - bits_to_clear >= 0) {
+		*p &= ~mask_to_clear;
+		len -= bits_to_clear;
+		bits_to_clear = BITS_PER_LONG;
+		mask_to_clear = ~0UL;
+		p++;
+	}
+	if (len) {
+		mask_to_clear &= cpu_to_le32(BITMAP_LAST_WORD_MASK(size));
+		*p &= ~mask_to_clear;
+	}
+}
diff --git a/fs/ntfs3/fslog.c b/fs/ntfs3/fslog.c
index 54bdbed03e541..5289c25b1ee43 100644
--- a/fs/ntfs3/fslog.c
+++ b/fs/ntfs3/fslog.c
@@ -3624,7 +3624,7 @@ move_data:
 			goto dirty_vol;
 		}
 
-		__bitmap_set(Add2Ptr(buffer_le, roff), off, bits);
+		ntfs_bitmap_set_le(Add2Ptr(buffer_le, roff), off, bits);
 		a_dirty = true;
 		break;
 
@@ -3637,7 +3637,7 @@ move_data:
 			goto dirty_vol;
 		}
 
-		__bitmap_clear(Add2Ptr(buffer_le, roff), off, bits);
+		ntfs_bitmap_clear_le(Add2Ptr(buffer_le, roff), off, bits);
 		a_dirty = true;
 		break;
 
diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h
index ebfb720fc4fd3..205ca35259dab 100644
--- a/fs/ntfs3/ntfs_fs.h
+++ b/fs/ntfs3/ntfs_fs.h
@@ -839,6 +839,9 @@ int wnd_extend(struct wnd_bitmap *wnd, size_t new_bits);
 void wnd_zone_set(struct wnd_bitmap *wnd, size_t Lcn, size_t Len);
 int ntfs_trim_fs(struct ntfs_sb_info *sbi, struct fstrim_range *range);
 
+void ntfs_bitmap_set_le(unsigned long *map, unsigned int start, int len);
+void ntfs_bitmap_clear_le(unsigned long *map, unsigned int start, int len);
+
 /* Globals from upcase.c */
 int ntfs_cmp_names(const __le16 *s1, size_t l1, const __le16 *s2, size_t l2,
 		   const u16 *upcase, bool bothcase);
-- 
GitLab


From 095d8ce635c116bb7813d865adfbccde8094d920 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thomas=20K=C3=BChnel?= <thomas.kuehnel@avm.de>
Date: Tue, 7 Dec 2021 11:24:55 +0100
Subject: [PATCH 056/875] fs/ntfs3: Use _le variants of bitops functions
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The functions from bitops.h already have _le variants so use them to
prevent invalid reads/writes of the bitmap on big endian systems.

Signed-off-by: Thomas Kühnel <thomas.kuehnel@avm.de>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/bitmap.c | 10 +++++-----
 fs/ntfs3/fsntfs.c |  8 ++++----
 fs/ntfs3/index.c  | 14 +++++++-------
 3 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/fs/ntfs3/bitmap.c b/fs/ntfs3/bitmap.c
index c114983b248e3..dcb786b300f1f 100644
--- a/fs/ntfs3/bitmap.c
+++ b/fs/ntfs3/bitmap.c
@@ -66,7 +66,7 @@ static size_t wnd_scan(const ulong *buf, size_t wbit, u32 wpos, u32 wend,
 	while (wpos < wend) {
 		size_t free_len;
 		u32 free_bits, end;
-		u32 used = find_next_zero_bit(buf, wend, wpos);
+		u32 used = find_next_zero_bit_le(buf, wend, wpos);
 
 		if (used >= wend) {
 			if (*b_len < *prev_tail) {
@@ -92,7 +92,7 @@ static size_t wnd_scan(const ulong *buf, size_t wbit, u32 wpos, u32 wend,
 		 * Now we have a fragment [wpos, wend) staring with 0.
 		 */
 		end = wpos + to_alloc - *prev_tail;
-		free_bits = find_next_bit(buf, min(end, wend), wpos);
+		free_bits = find_next_bit_le(buf, min(end, wend), wpos);
 
 		free_len = *prev_tail + free_bits - wpos;
 
@@ -574,7 +574,7 @@ static int wnd_rescan(struct wnd_bitmap *wnd)
 			wbits = wnd->nbits - wbit;
 
 		do {
-			used = find_next_zero_bit(buf, wbits, wpos);
+			used = find_next_zero_bit_le(buf, wbits, wpos);
 
 			if (used > wpos && prev_tail) {
 				wnd_add_free_ext(wnd, wbit + wpos - prev_tail,
@@ -590,7 +590,7 @@ static int wnd_rescan(struct wnd_bitmap *wnd)
 				break;
 			}
 
-			frb = find_next_bit(buf, wbits, wpos);
+			frb = find_next_bit_le(buf, wbits, wpos);
 			if (frb >= wbits) {
 				/* Keep last free block. */
 				prev_tail += frb - wpos;
@@ -1449,7 +1449,7 @@ int ntfs_trim_fs(struct ntfs_sb_info *sbi, struct fstrim_range *range)
 		buf = (ulong *)bh->b_data;
 
 		for (; wbit < wbits; wbit++) {
-			if (!test_bit(wbit, buf)) {
+			if (!test_bit_le(wbit, buf)) {
 				if (!len)
 					lcn = lcn_wnd + wbit;
 				len += 1;
diff --git a/fs/ntfs3/fsntfs.c b/fs/ntfs3/fsntfs.c
index 0992fb2e4eb74..f45520a0d5398 100644
--- a/fs/ntfs3/fsntfs.c
+++ b/fs/ntfs3/fsntfs.c
@@ -642,13 +642,13 @@ next:
 						 NULL, 0, NULL, NULL))
 					goto next;
 
-				__clear_bit(ir - MFT_REC_RESERVED,
+				__clear_bit_le(ir - MFT_REC_RESERVED,
 					    &sbi->mft.reserved_bitmap);
 			}
 		}
 
 		/* Scan 5 bits for zero. Bit 0 == MFT_REC_RESERVED */
-		zbit = find_next_zero_bit(&sbi->mft.reserved_bitmap,
+		zbit = find_next_zero_bit_le(&sbi->mft.reserved_bitmap,
 					  MFT_REC_FREE, MFT_REC_RESERVED);
 		if (zbit >= MFT_REC_FREE) {
 			sbi->mft.next_reserved = MFT_REC_FREE;
@@ -716,7 +716,7 @@ found:
 	if (*rno >= MFT_REC_FREE)
 		wnd_set_used(wnd, *rno, 1);
 	else if (*rno >= MFT_REC_RESERVED && sbi->mft.reserved_bitmap_inited)
-		__set_bit(*rno - MFT_REC_RESERVED, &sbi->mft.reserved_bitmap);
+		__set_bit_le(*rno - MFT_REC_RESERVED, &sbi->mft.reserved_bitmap);
 
 out:
 	if (!mft)
@@ -744,7 +744,7 @@ void ntfs_mark_rec_free(struct ntfs_sb_info *sbi, CLST rno, bool is_mft)
 		else
 			wnd_set_free(wnd, rno, 1);
 	} else if (rno >= MFT_REC_RESERVED && sbi->mft.reserved_bitmap_inited) {
-		__clear_bit(rno - MFT_REC_RESERVED, &sbi->mft.reserved_bitmap);
+		__clear_bit_le(rno - MFT_REC_RESERVED, &sbi->mft.reserved_bitmap);
 	}
 
 	if (rno < wnd_zone_bit(wnd))
diff --git a/fs/ntfs3/index.c b/fs/ntfs3/index.c
index bc656868cf8a8..50c90d7e8a78b 100644
--- a/fs/ntfs3/index.c
+++ b/fs/ntfs3/index.c
@@ -323,7 +323,7 @@ static int indx_mark_used(struct ntfs_index *indx, struct ntfs_inode *ni,
 	if (err)
 		return err;
 
-	__set_bit(bit - bbuf.bit, bbuf.buf);
+	__set_bit_le(bit - bbuf.bit, bbuf.buf);
 
 	bmp_buf_put(&bbuf, true);
 
@@ -343,7 +343,7 @@ static int indx_mark_free(struct ntfs_index *indx, struct ntfs_inode *ni,
 	if (err)
 		return err;
 
-	__clear_bit(bit - bbuf.bit, bbuf.buf);
+	__clear_bit_le(bit - bbuf.bit, bbuf.buf);
 
 	bmp_buf_put(&bbuf, true);
 
@@ -457,7 +457,7 @@ next_run:
 
 static bool scan_for_free(const ulong *buf, u32 bit, u32 bits, size_t *ret)
 {
-	size_t pos = find_next_zero_bit(buf, bits, bit);
+	size_t pos = find_next_zero_bit_le(buf, bits, bit);
 
 	if (pos >= bits)
 		return false;
@@ -489,7 +489,7 @@ static int indx_find_free(struct ntfs_index *indx, struct ntfs_inode *ni,
 
 	if (!b->non_res) {
 		u32 nbits = 8 * le32_to_cpu(b->res.data_size);
-		size_t pos = find_next_zero_bit(resident_data(b), nbits, 0);
+		size_t pos = find_next_zero_bit_le(resident_data(b), nbits, 0);
 
 		if (pos < nbits)
 			*bit = pos;
@@ -505,7 +505,7 @@ static int indx_find_free(struct ntfs_index *indx, struct ntfs_inode *ni,
 
 static bool scan_for_used(const ulong *buf, u32 bit, u32 bits, size_t *ret)
 {
-	size_t pos = find_next_bit(buf, bits, bit);
+	size_t pos = find_next_bit_le(buf, bits, bit);
 
 	if (pos >= bits)
 		return false;
@@ -536,7 +536,7 @@ int indx_used_bit(struct ntfs_index *indx, struct ntfs_inode *ni, size_t *bit)
 
 	if (!b->non_res) {
 		u32 nbits = le32_to_cpu(b->res.data_size) * 8;
-		size_t pos = find_next_bit(resident_data(b), nbits, from);
+		size_t pos = find_next_bit_le(resident_data(b), nbits, from);
 
 		if (pos < nbits)
 			*bit = pos;
@@ -1953,7 +1953,7 @@ static int indx_shrink(struct ntfs_index *indx, struct ntfs_inode *ni,
 		if (bit >= nbits)
 			return 0;
 
-		pos = find_next_bit(bm, nbits, bit);
+		pos = find_next_bit_le(bm, nbits, bit);
 		if (pos < nbits)
 			return 0;
 	} else {
-- 
GitLab


From 08811ba59a61e8147c869e2d056c37ab8ca5ebde Mon Sep 17 00:00:00 2001
From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
Date: Thu, 6 Oct 2022 19:42:24 +0300
Subject: [PATCH 057/875] fs/ntfs3: Add ntfs_bitmap_weight_le function and
 refactoring

Added ntfs_bitmap_weight_le function.
Changed argument types of bits/bitmap functions.

Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/bitfunc.c |   4 +-
 fs/ntfs3/bitmap.c  | 100 +++++++++++++++++++++++++--------------------
 fs/ntfs3/ntfs_fs.h |  11 ++---
 3 files changed, 63 insertions(+), 52 deletions(-)

diff --git a/fs/ntfs3/bitfunc.c b/fs/ntfs3/bitfunc.c
index 50d838093790a..25a4d4896aa93 100644
--- a/fs/ntfs3/bitfunc.c
+++ b/fs/ntfs3/bitfunc.c
@@ -30,7 +30,7 @@ static const u8 zero_mask[] = { 0xFF, 0xFE, 0xFC, 0xF8, 0xF0,
  *
  * Return: True if all bits [bit, bit+nbits) are zeros "0".
  */
-bool are_bits_clear(const ulong *lmap, size_t bit, size_t nbits)
+bool are_bits_clear(const void *lmap, size_t bit, size_t nbits)
 {
 	size_t pos = bit & 7;
 	const u8 *map = (u8 *)lmap + (bit >> 3);
@@ -78,7 +78,7 @@ bool are_bits_clear(const ulong *lmap, size_t bit, size_t nbits)
  *
  * Return: True if all bits [bit, bit+nbits) are ones "1".
  */
-bool are_bits_set(const ulong *lmap, size_t bit, size_t nbits)
+bool are_bits_set(const void *lmap, size_t bit, size_t nbits)
 {
 	u8 mask;
 	size_t pos = bit & 7;
diff --git a/fs/ntfs3/bitmap.c b/fs/ntfs3/bitmap.c
index dcb786b300f1f..a51805a3d91fa 100644
--- a/fs/ntfs3/bitmap.c
+++ b/fs/ntfs3/bitmap.c
@@ -59,7 +59,7 @@ void ntfs3_exit_bitmap(void)
  *
  * Return: -1 if not found.
  */
-static size_t wnd_scan(const ulong *buf, size_t wbit, u32 wpos, u32 wend,
+static size_t wnd_scan(const void *buf, size_t wbit, u32 wpos, u32 wend,
 		       size_t to_alloc, size_t *prev_tail, size_t *b_pos,
 		       size_t *b_len)
 {
@@ -504,7 +504,6 @@ static int wnd_rescan(struct wnd_bitmap *wnd)
 	u8 cluster_bits = sbi->cluster_bits;
 	u32 wbits = 8 * sb->s_blocksize;
 	u32 used, frb;
-	const ulong *buf;
 	size_t wpos, wbit, iw, vbo;
 	struct buffer_head *bh = NULL;
 	CLST lcn, clen;
@@ -558,9 +557,7 @@ static int wnd_rescan(struct wnd_bitmap *wnd)
 			goto out;
 		}
 
-		buf = (ulong *)bh->b_data;
-
-		used = __bitmap_weight(buf, wbits);
+		used = ntfs_bitmap_weight_le(bh->b_data, wbits);
 		if (used < wbits) {
 			frb = wbits - used;
 			wnd->free_bits[iw] = frb;
@@ -574,7 +571,7 @@ static int wnd_rescan(struct wnd_bitmap *wnd)
 			wbits = wnd->nbits - wbit;
 
 		do {
-			used = find_next_zero_bit_le(buf, wbits, wpos);
+			used = find_next_zero_bit_le(bh->b_data, wbits, wpos);
 
 			if (used > wpos && prev_tail) {
 				wnd_add_free_ext(wnd, wbit + wpos - prev_tail,
@@ -590,7 +587,7 @@ static int wnd_rescan(struct wnd_bitmap *wnd)
 				break;
 			}
 
-			frb = find_next_bit_le(buf, wbits, wpos);
+			frb = find_next_bit_le(bh->b_data, wbits, wpos);
 			if (frb >= wbits) {
 				/* Keep last free block. */
 				prev_tail += frb - wpos;
@@ -718,7 +715,6 @@ int wnd_set_free(struct wnd_bitmap *wnd, size_t bit, size_t bits)
 
 	while (iw < wnd->nwnd && bits) {
 		u32 tail, op;
-		ulong *buf;
 
 		if (iw + 1 == wnd->nwnd)
 			wbits = wnd->bits_last;
@@ -732,11 +728,9 @@ int wnd_set_free(struct wnd_bitmap *wnd, size_t bit, size_t bits)
 			break;
 		}
 
-		buf = (ulong *)bh->b_data;
-
 		lock_buffer(bh);
 
-		ntfs_bitmap_clear_le(buf, wbit, op);
+		ntfs_bitmap_clear_le(bh->b_data, wbit, op);
 
 		wnd->free_bits[iw] += op;
 
@@ -771,7 +765,6 @@ int wnd_set_used(struct wnd_bitmap *wnd, size_t bit, size_t bits)
 
 	while (iw < wnd->nwnd && bits) {
 		u32 tail, op;
-		ulong *buf;
 
 		if (unlikely(iw + 1 == wnd->nwnd))
 			wbits = wnd->bits_last;
@@ -784,11 +777,10 @@ int wnd_set_used(struct wnd_bitmap *wnd, size_t bit, size_t bits)
 			err = PTR_ERR(bh);
 			break;
 		}
-		buf = (ulong *)bh->b_data;
 
 		lock_buffer(bh);
 
-		ntfs_bitmap_set_le(buf, wbit, op);
+		ntfs_bitmap_set_le(bh->b_data, wbit, op);
 		wnd->free_bits[iw] -= op;
 
 		set_buffer_uptodate(bh);
@@ -836,7 +828,7 @@ static bool wnd_is_free_hlp(struct wnd_bitmap *wnd, size_t bit, size_t bits)
 			if (IS_ERR(bh))
 				return false;
 
-			ret = are_bits_clear((ulong *)bh->b_data, wbit, op);
+			ret = are_bits_clear(bh->b_data, wbit, op);
 
 			put_bh(bh);
 			if (!ret)
@@ -928,7 +920,7 @@ use_wnd:
 			if (IS_ERR(bh))
 				goto out;
 
-			ret = are_bits_set((ulong *)bh->b_data, wbit, op);
+			ret = are_bits_set(bh->b_data, wbit, op);
 			put_bh(bh);
 			if (!ret)
 				goto out;
@@ -959,7 +951,6 @@ size_t wnd_find(struct wnd_bitmap *wnd, size_t to_alloc, size_t hint,
 	size_t fnd, max_alloc, b_len, b_pos;
 	size_t iw, prev_tail, nwnd, wbit, ebit, zbit, zend;
 	size_t to_alloc0 = to_alloc;
-	const ulong *buf;
 	const struct e_node *e;
 	const struct rb_node *pr, *cr;
 	u8 log2_bits;
@@ -1185,14 +1176,13 @@ Again:
 					continue;
 				}
 
-				buf = (ulong *)bh->b_data;
-
 				/* Scan range [wbit, zbit). */
 				if (wpos < wzbit) {
 					/* Scan range [wpos, zbit). */
-					fnd = wnd_scan(buf, wbit, wpos, wzbit,
-						       to_alloc, &prev_tail,
-						       &b_pos, &b_len);
+					fnd = wnd_scan(bh->b_data, wbit, wpos,
+						       wzbit, to_alloc,
+						       &prev_tail, &b_pos,
+						       &b_len);
 					if (fnd != MINUS_ONE_T) {
 						put_bh(bh);
 						goto found;
@@ -1203,7 +1193,7 @@ Again:
 
 				/* Scan range [zend, ebit). */
 				if (wzend < wbits) {
-					fnd = wnd_scan(buf, wbit,
+					fnd = wnd_scan(bh->b_data, wbit,
 						       max(wzend, wpos), wbits,
 						       to_alloc, &prev_tail,
 						       &b_pos, &b_len);
@@ -1242,11 +1232,9 @@ Again:
 			continue;
 		}
 
-		buf = (ulong *)bh->b_data;
-
 		/* Scan range [wpos, eBits). */
-		fnd = wnd_scan(buf, wbit, wpos, wbits, to_alloc, &prev_tail,
-			       &b_pos, &b_len);
+		fnd = wnd_scan(bh->b_data, wbit, wpos, wbits, to_alloc,
+			       &prev_tail, &b_pos, &b_len);
 		put_bh(bh);
 		if (fnd != MINUS_ONE_T)
 			goto found;
@@ -1344,7 +1332,6 @@ int wnd_extend(struct wnd_bitmap *wnd, size_t new_bits)
 		size_t frb;
 		u64 vbo, lbo, bytes;
 		struct buffer_head *bh;
-		ulong *buf;
 
 		if (iw + 1 == new_wnd)
 			wbits = new_last;
@@ -1361,10 +1348,9 @@ int wnd_extend(struct wnd_bitmap *wnd, size_t new_bits)
 			return -EIO;
 
 		lock_buffer(bh);
-		buf = (ulong *)bh->b_data;
 
-		ntfs_bitmap_clear_le(buf, b0, blocksize * 8 - b0);
-		frb = wbits - __bitmap_weight(buf, wbits);
+		ntfs_bitmap_clear_le(bh->b_data, b0, blocksize * 8 - b0);
+		frb = wbits - ntfs_bitmap_weight_le(bh->b_data, wbits);
 		wnd->total_zeroes += frb - wnd->free_bits[iw];
 		wnd->free_bits[iw] = frb;
 
@@ -1411,7 +1397,6 @@ int ntfs_trim_fs(struct ntfs_sb_info *sbi, struct fstrim_range *range)
 	CLST lcn_from = bytes_to_cluster(sbi, range->start);
 	size_t iw = lcn_from >> (sb->s_blocksize_bits + 3);
 	u32 wbit = lcn_from & (wbits - 1);
-	const ulong *buf;
 	CLST lcn_to;
 
 	if (!minlen)
@@ -1446,10 +1431,8 @@ int ntfs_trim_fs(struct ntfs_sb_info *sbi, struct fstrim_range *range)
 			break;
 		}
 
-		buf = (ulong *)bh->b_data;
-
 		for (; wbit < wbits; wbit++) {
-			if (!test_bit_le(wbit, buf)) {
+			if (!test_bit_le(wbit, bh->b_data)) {
 				if (!len)
 					lcn = lcn_wnd + wbit;
 				len += 1;
@@ -1482,42 +1465,69 @@ out:
 	return err;
 }
 
-void ntfs_bitmap_set_le(unsigned long *map, unsigned int start, int len)
+#if BITS_PER_LONG == 64
+typedef __le64 bitmap_ulong;
+#define cpu_to_ul(x) cpu_to_le64(x)
+#define ul_to_cpu(x) le64_to_cpu(x)
+#else
+typedef __le32 bitmap_ulong;
+#define cpu_to_ul(x) cpu_to_le32(x)
+#define ul_to_cpu(x) le32_to_cpu(x)
+#endif
+
+void ntfs_bitmap_set_le(void *map, unsigned int start, int len)
 {
-	unsigned long *p = map + BIT_WORD(start);
+	bitmap_ulong *p = (bitmap_ulong *)map + BIT_WORD(start);
 	const unsigned int size = start + len;
 	int bits_to_set = BITS_PER_LONG - (start % BITS_PER_LONG);
-	unsigned long mask_to_set = cpu_to_le32(BITMAP_FIRST_WORD_MASK(start));
+	bitmap_ulong mask_to_set = cpu_to_ul(BITMAP_FIRST_WORD_MASK(start));
 
 	while (len - bits_to_set >= 0) {
 		*p |= mask_to_set;
 		len -= bits_to_set;
 		bits_to_set = BITS_PER_LONG;
-		mask_to_set = ~0UL;
+		mask_to_set = cpu_to_ul(~0UL);
 		p++;
 	}
 	if (len) {
-		mask_to_set &= cpu_to_le32(BITMAP_LAST_WORD_MASK(size));
+		mask_to_set &= cpu_to_ul(BITMAP_LAST_WORD_MASK(size));
 		*p |= mask_to_set;
 	}
 }
 
-void ntfs_bitmap_clear_le(unsigned long *map, unsigned int start, int len)
+void ntfs_bitmap_clear_le(void *map, unsigned int start, int len)
 {
-	unsigned long *p = map + BIT_WORD(start);
+	bitmap_ulong *p = (bitmap_ulong *)map + BIT_WORD(start);
 	const unsigned int size = start + len;
 	int bits_to_clear = BITS_PER_LONG - (start % BITS_PER_LONG);
-	unsigned long mask_to_clear = cpu_to_le32(BITMAP_FIRST_WORD_MASK(start));
+	bitmap_ulong mask_to_clear = cpu_to_ul(BITMAP_FIRST_WORD_MASK(start));
 
 	while (len - bits_to_clear >= 0) {
 		*p &= ~mask_to_clear;
 		len -= bits_to_clear;
 		bits_to_clear = BITS_PER_LONG;
-		mask_to_clear = ~0UL;
+		mask_to_clear = cpu_to_ul(~0UL);
 		p++;
 	}
 	if (len) {
-		mask_to_clear &= cpu_to_le32(BITMAP_LAST_WORD_MASK(size));
+		mask_to_clear &= cpu_to_ul(BITMAP_LAST_WORD_MASK(size));
 		*p &= ~mask_to_clear;
 	}
 }
+
+unsigned int ntfs_bitmap_weight_le(const void *bitmap, int bits)
+{
+	const ulong *bmp = bitmap;
+	unsigned int k, lim = bits / BITS_PER_LONG;
+	unsigned int w = 0;
+
+	for (k = 0; k < lim; k++)
+		w += hweight_long(bmp[k]);
+
+	if (bits % BITS_PER_LONG) {
+		w += hweight_long(ul_to_cpu(((bitmap_ulong *)bitmap)[k]) &
+				  BITMAP_LAST_WORD_MASK(bits));
+	}
+
+	return w;
+}
diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h
index 205ca35259dab..070ede6bee197 100644
--- a/fs/ntfs3/ntfs_fs.h
+++ b/fs/ntfs3/ntfs_fs.h
@@ -472,9 +472,9 @@ static inline size_t al_aligned(size_t size)
 }
 
 /* Globals from bitfunc.c */
-bool are_bits_clear(const ulong *map, size_t bit, size_t nbits);
-bool are_bits_set(const ulong *map, size_t bit, size_t nbits);
-size_t get_set_bits_ex(const ulong *map, size_t bit, size_t nbits);
+bool are_bits_clear(const void *map, size_t bit, size_t nbits);
+bool are_bits_set(const void *map, size_t bit, size_t nbits);
+size_t get_set_bits_ex(const void *map, size_t bit, size_t nbits);
 
 /* Globals from dir.c */
 int ntfs_utf16_to_nls(struct ntfs_sb_info *sbi, const __le16 *name, u32 len,
@@ -839,8 +839,9 @@ int wnd_extend(struct wnd_bitmap *wnd, size_t new_bits);
 void wnd_zone_set(struct wnd_bitmap *wnd, size_t Lcn, size_t Len);
 int ntfs_trim_fs(struct ntfs_sb_info *sbi, struct fstrim_range *range);
 
-void ntfs_bitmap_set_le(unsigned long *map, unsigned int start, int len);
-void ntfs_bitmap_clear_le(unsigned long *map, unsigned int start, int len);
+void ntfs_bitmap_set_le(void *map, unsigned int start, int len);
+void ntfs_bitmap_clear_le(void *map, unsigned int start, int len);
+unsigned int ntfs_bitmap_weight_le(const void *bitmap, int bits);
 
 /* Globals from upcase.c */
 int ntfs_cmp_names(const __le16 *s1, size_t l1, const __le16 *s2, size_t l2,
-- 
GitLab


From 9144b43820610bfb69c9821c39839ffe05f2e6b2 Mon Sep 17 00:00:00 2001
From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
Date: Thu, 6 Oct 2022 19:58:11 +0300
Subject: [PATCH 058/875] fs/ntfs3: Fix sparse problems

Fixing various problems, detected by sparse.

Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/attrib.c  |  7 ++++---
 fs/ntfs3/dir.c     |  4 ++--
 fs/ntfs3/frecord.c |  3 +--
 fs/ntfs3/namei.c   | 13 ++++++-------
 4 files changed, 13 insertions(+), 14 deletions(-)

diff --git a/fs/ntfs3/attrib.c b/fs/ntfs3/attrib.c
index 63169529b52c4..b2f54fab40012 100644
--- a/fs/ntfs3/attrib.c
+++ b/fs/ntfs3/attrib.c
@@ -2308,7 +2308,8 @@ int attr_insert_range(struct ntfs_inode *ni, u64 vbo, u64 bytes)
 
 		if (!attr_b->non_res) {
 			/* Still resident. */
-			char *data = Add2Ptr(attr_b, attr_b->res.data_off);
+			char *data = Add2Ptr(attr_b,
+					     le16_to_cpu(attr_b->res.data_off));
 
 			memmove(data + bytes, data, bytes);
 			memset(data, 0, bytes);
@@ -2400,8 +2401,8 @@ int attr_insert_range(struct ntfs_inode *ni, u64 vbo, u64 bytes)
 	if (vbo <= ni->i_valid)
 		ni->i_valid += bytes;
 
-	attr_b->nres.data_size = le64_to_cpu(data_size + bytes);
-	attr_b->nres.alloc_size = le64_to_cpu(alloc_size + bytes);
+	attr_b->nres.data_size = cpu_to_le64(data_size + bytes);
+	attr_b->nres.alloc_size = cpu_to_le64(alloc_size + bytes);
 
 	/* ni->valid may be not equal valid_size (temporary). */
 	if (ni->i_valid > data_size + bytes)
diff --git a/fs/ntfs3/dir.c b/fs/ntfs3/dir.c
index fb438d6040409..063a6654199bc 100644
--- a/fs/ntfs3/dir.c
+++ b/fs/ntfs3/dir.c
@@ -26,8 +26,8 @@ int ntfs_utf16_to_nls(struct ntfs_sb_info *sbi, const __le16 *name, u32 len,
 
 	if (!nls) {
 		/* UTF-16 -> UTF-8 */
-		ret = utf16s_to_utf8s(name, len, UTF16_LITTLE_ENDIAN, buf,
-				      buf_len);
+		ret = utf16s_to_utf8s((wchar_t *)name, len, UTF16_LITTLE_ENDIAN,
+				      buf, buf_len);
 		buf[ret] = '\0';
 		return ret;
 	}
diff --git a/fs/ntfs3/frecord.c b/fs/ntfs3/frecord.c
index 039247ab5b0b7..ff938d3cd5efe 100644
--- a/fs/ntfs3/frecord.c
+++ b/fs/ntfs3/frecord.c
@@ -1670,8 +1670,7 @@ next:
 		goto next;
 
 	fns = (struct le_str *)&fname->name_len;
-	if (ntfs_cmp_names(uni->name, uni->len, fns->name, fns->len, NULL,
-			       false))
+	if (ntfs_cmp_names_cpu(uni, fns, NULL, false))
 		goto next;
 
 	return fname;
diff --git a/fs/ntfs3/namei.c b/fs/ntfs3/namei.c
index 6b0d2c01d6ffc..ad6d16dec9f06 100644
--- a/fs/ntfs3/namei.c
+++ b/fs/ntfs3/namei.c
@@ -427,7 +427,8 @@ static int ntfs_d_compare(const struct dentry *dentry, unsigned int len1,
 	unsigned int len2 = name->len;
 	unsigned int lm = min(len1, len2);
 	unsigned char c1, c2;
-	struct cpu_str *uni1, *uni2;
+	struct cpu_str *uni1;
+	struct le_str *uni2;
 
 	/* First try fast implementation. */
 	for (;;) {
@@ -464,8 +465,9 @@ static int ntfs_d_compare(const struct dentry *dentry, unsigned int len1,
 
 	uni2 = Add2Ptr(uni1, 2048);
 
-	ret = ntfs_nls_to_utf16(sbi, name->name, name->len, uni2, NTFS_NAME_LEN,
-				UTF16_HOST_ENDIAN);
+	ret = ntfs_nls_to_utf16(sbi, name->name, name->len,
+				(struct cpu_str *)uni2, NTFS_NAME_LEN,
+				UTF16_LITTLE_ENDIAN);
 	if (ret < 0)
 		goto out;
 
@@ -474,10 +476,7 @@ static int ntfs_d_compare(const struct dentry *dentry, unsigned int len1,
 		goto out;
 	}
 
-	ret = !ntfs_cmp_names(uni1->name, uni1->len, uni2->name, uni2->len,
-			      sbi->upcase, false)
-		      ? 0
-		      : 1;
+	ret = !ntfs_cmp_names_cpu(uni1, uni2, sbi->upcase, false) ? 0 : 1;
 
 out:
 	__putname(uni1);
-- 
GitLab


From 3929042111de8cb283489ef4ea184103e3443536 Mon Sep 17 00:00:00 2001
From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
Date: Thu, 6 Oct 2022 20:04:53 +0300
Subject: [PATCH 059/875] fs/ntfs3: Remove unused functions

Removed attr_must_be_resident and ntfs_query_def.

Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/attrib.c  | 27 ---------------------------
 fs/ntfs3/fsntfs.c  | 29 -----------------------------
 fs/ntfs3/ntfs_fs.h |  2 --
 3 files changed, 58 deletions(-)

diff --git a/fs/ntfs3/attrib.c b/fs/ntfs3/attrib.c
index b2f54fab40012..7c00656151fb5 100644
--- a/fs/ntfs3/attrib.c
+++ b/fs/ntfs3/attrib.c
@@ -54,33 +54,6 @@ static inline u64 get_pre_allocated(u64 size)
 	return ret;
 }
 
-/*
- * attr_must_be_resident
- *
- * Return: True if attribute must be resident.
- */
-static inline bool attr_must_be_resident(struct ntfs_sb_info *sbi,
-					 enum ATTR_TYPE type)
-{
-	const struct ATTR_DEF_ENTRY *de;
-
-	switch (type) {
-	case ATTR_STD:
-	case ATTR_NAME:
-	case ATTR_ID:
-	case ATTR_LABEL:
-	case ATTR_VOL_INFO:
-	case ATTR_ROOT:
-	case ATTR_EA_INFO:
-		return true;
-	default:
-		de = ntfs_query_def(sbi, type);
-		if (de && (de->flags & NTFS_ATTR_MUST_BE_RESIDENT))
-			return true;
-		return false;
-	}
-}
-
 /*
  * attr_load_runs - Load all runs stored in @attr.
  */
diff --git a/fs/ntfs3/fsntfs.c b/fs/ntfs3/fsntfs.c
index f45520a0d5398..b7c68ca65bac2 100644
--- a/fs/ntfs3/fsntfs.c
+++ b/fs/ntfs3/fsntfs.c
@@ -345,35 +345,6 @@ out:
 	return err;
 }
 
-/*
- * ntfs_query_def
- *
- * Return: Current ATTR_DEF_ENTRY for given attribute type.
- */
-const struct ATTR_DEF_ENTRY *ntfs_query_def(struct ntfs_sb_info *sbi,
-					    enum ATTR_TYPE type)
-{
-	int type_in = le32_to_cpu(type);
-	size_t min_idx = 0;
-	size_t max_idx = sbi->def_entries - 1;
-
-	while (min_idx <= max_idx) {
-		size_t i = min_idx + ((max_idx - min_idx) >> 1);
-		const struct ATTR_DEF_ENTRY *entry = sbi->def_table + i;
-		int diff = le32_to_cpu(entry->type) - type_in;
-
-		if (!diff)
-			return entry;
-		if (diff < 0)
-			min_idx = i + 1;
-		else if (i)
-			max_idx = i - 1;
-		else
-			return NULL;
-	}
-	return NULL;
-}
-
 /*
  * ntfs_look_for_free_space - Look for a free space in bitmap.
  */
diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h
index 070ede6bee197..6e23553104331 100644
--- a/fs/ntfs3/ntfs_fs.h
+++ b/fs/ntfs3/ntfs_fs.h
@@ -585,8 +585,6 @@ int ntfs_fix_post_read(struct NTFS_RECORD_HEADER *rhdr, size_t bytes,
 		       bool simple);
 int ntfs_extend_init(struct ntfs_sb_info *sbi);
 int ntfs_loadlog_and_replay(struct ntfs_inode *ni, struct ntfs_sb_info *sbi);
-const struct ATTR_DEF_ENTRY *ntfs_query_def(struct ntfs_sb_info *sbi,
-					    enum ATTR_TYPE Type);
 int ntfs_look_for_free_space(struct ntfs_sb_info *sbi, CLST lcn, CLST len,
 			     CLST *new_lcn, CLST *new_len,
 			     enum ALLOCATE_OPT opt);
-- 
GitLab


From ba1189288905dc33c16a8e56d6af9c8d1bc5ca8f Mon Sep 17 00:00:00 2001
From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
Date: Thu, 6 Oct 2022 20:19:38 +0300
Subject: [PATCH 060/875] fs/ntfs3: Simplify ntfs_update_mftmirr function

Make err assignment in one place.

Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/fsntfs.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/fs/ntfs3/fsntfs.c b/fs/ntfs3/fsntfs.c
index b7c68ca65bac2..b68a7b7802629 100644
--- a/fs/ntfs3/fsntfs.c
+++ b/fs/ntfs3/fsntfs.c
@@ -825,7 +825,6 @@ void ntfs_update_mftmirr(struct ntfs_sb_info *sbi, int wait)
 	if (!(sbi->flags & NTFS_FLAGS_MFTMIRR))
 		return;
 
-	err = 0;
 	bytes = sbi->mft.recs_mirr << sbi->record_bits;
 	block1 = sbi->mft.lbo >> sb->s_blocksize_bits;
 	block2 = sbi->mft.lbo2 >> sb->s_blocksize_bits;
@@ -855,8 +854,7 @@ void ntfs_update_mftmirr(struct ntfs_sb_info *sbi, int wait)
 		put_bh(bh1);
 		bh1 = NULL;
 
-		if (wait)
-			err = sync_dirty_buffer(bh2);
+		err = wait ? sync_dirty_buffer(bh2) : 0;
 
 		put_bh(bh2);
 		if (err)
-- 
GitLab


From 2f56a3f8d824d34525951483e95b0ed04c5954bf Mon Sep 17 00:00:00 2001
From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
Date: Fri, 7 Oct 2022 13:57:28 +0300
Subject: [PATCH 061/875] fs/ntfs3: Fixing work with sparse clusters

Simplify logic in ntfs_extend_initialized_size, ntfs_sparse_cluster
and ntfs_fallocate.

Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/file.c  | 45 ++++++++++++---------------------------------
 fs/ntfs3/inode.c |  7 ++++++-
 2 files changed, 18 insertions(+), 34 deletions(-)

diff --git a/fs/ntfs3/file.c b/fs/ntfs3/file.c
index 4f2ffc7ef296f..96ba3f5a8470e 100644
--- a/fs/ntfs3/file.c
+++ b/fs/ntfs3/file.c
@@ -128,25 +128,9 @@ static int ntfs_extend_initialized_size(struct file *file,
 				goto out;
 
 			if (lcn == SPARSE_LCN) {
-				loff_t vbo = (loff_t)vcn << bits;
-				loff_t to = vbo + ((loff_t)clen << bits);
-
-				if (to <= new_valid) {
-					ni->i_valid = to;
-					pos = to;
-					goto next;
-				}
-
-				if (vbo < pos) {
-					pos = vbo;
-				} else {
-					to = (new_valid >> bits) << bits;
-					if (pos < to) {
-						ni->i_valid = to;
-						pos = to;
-						goto next;
-					}
-				}
+				pos = ((loff_t)clen + vcn) << bits;
+				ni->i_valid = pos;
+				goto next;
 			}
 		}
 
@@ -279,8 +263,9 @@ void ntfs_sparse_cluster(struct inode *inode, struct page *page0, CLST vcn,
 {
 	struct address_space *mapping = inode->i_mapping;
 	struct ntfs_sb_info *sbi = inode->i_sb->s_fs_info;
-	u64 vbo = (u64)vcn << sbi->cluster_bits;
-	u64 bytes = (u64)len << sbi->cluster_bits;
+	u8 cluster_bits = sbi->cluster_bits;
+	u64 vbo = (u64)vcn << cluster_bits;
+	u64 bytes = (u64)len << cluster_bits;
 	u32 blocksize = 1 << inode->i_blkbits;
 	pgoff_t idx0 = page0 ? page0->index : -1;
 	loff_t vbo_clst = vbo & sbi->cluster_mask_inv;
@@ -329,11 +314,10 @@ void ntfs_sparse_cluster(struct inode *inode, struct page *page0, CLST vcn,
 
 		zero_user_segment(page, from, to);
 
-		if (!partial) {
-			if (!PageUptodate(page))
-				SetPageUptodate(page);
-			set_page_dirty(page);
-		}
+		if (!partial)
+			SetPageUptodate(page);
+		flush_dcache_page(page);
+		set_page_dirty(page);
 
 		if (idx != idx0) {
 			unlock_page(page);
@@ -341,7 +325,6 @@ void ntfs_sparse_cluster(struct inode *inode, struct page *page0, CLST vcn,
 		}
 		cond_resched();
 	}
-	mark_inode_dirty(inode);
 }
 
 /*
@@ -588,11 +571,7 @@ static long ntfs_fallocate(struct file *file, int mode, loff_t vbo, loff_t len)
 		u32 frame_size;
 		loff_t mask, vbo_a, end_a, tmp;
 
-		err = filemap_write_and_wait_range(mapping, vbo, end - 1);
-		if (err)
-			goto out;
-
-		err = filemap_write_and_wait_range(mapping, end, LLONG_MAX);
+		err = filemap_write_and_wait_range(mapping, vbo, LLONG_MAX);
 		if (err)
 			goto out;
 
@@ -693,7 +672,7 @@ static long ntfs_fallocate(struct file *file, int mode, loff_t vbo, loff_t len)
 			goto out;
 
 		if (is_supported_holes) {
-			CLST vcn_v = ni->i_valid >> sbi->cluster_bits;
+			CLST vcn_v = bytes_to_cluster(sbi, ni->i_valid);
 			CLST vcn = vbo >> sbi->cluster_bits;
 			CLST cend = bytes_to_cluster(sbi, end);
 			CLST lcn, clen;
diff --git a/fs/ntfs3/inode.c b/fs/ntfs3/inode.c
index 763dd982a43a7..d8d00ffe7a1f7 100644
--- a/fs/ntfs3/inode.c
+++ b/fs/ntfs3/inode.c
@@ -646,7 +646,12 @@ static noinline int ntfs_get_block_vbo(struct inode *inode, u64 vbo,
 			bh->b_size = block_size;
 			off = vbo & (PAGE_SIZE - 1);
 			set_bh_page(bh, page, off);
-			ll_rw_block(REQ_OP_READ, 1, &bh);
+
+			lock_buffer(bh);
+			bh->b_end_io = end_buffer_read_sync;
+			get_bh(bh);
+			submit_bh(REQ_OP_READ, bh);
+
 			wait_on_buffer(bh);
 			if (!buffer_uptodate(bh)) {
 				err = -EIO;
-- 
GitLab


From c380b52f6c5702cc4bdda5e6d456d6c19a201a0b Mon Sep 17 00:00:00 2001
From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
Date: Fri, 7 Oct 2022 14:02:36 +0300
Subject: [PATCH 062/875] fs/ntfs3: Change new sparse cluster processing

Remove ntfs_sparse_cluster.
Zero clusters in attr_allocate_clusters.
Fixes xfstest generic/263

Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/attrib.c  | 176 +++++++++++++++++++++++++++++++--------------
 fs/ntfs3/file.c    | 146 +++++++++----------------------------
 fs/ntfs3/frecord.c |   2 +-
 fs/ntfs3/index.c   |   4 +-
 fs/ntfs3/inode.c   |  12 ++--
 fs/ntfs3/ntfs_fs.h |   7 +-
 6 files changed, 166 insertions(+), 181 deletions(-)

diff --git a/fs/ntfs3/attrib.c b/fs/ntfs3/attrib.c
index 7c00656151fb5..eda83a37a0c3f 100644
--- a/fs/ntfs3/attrib.c
+++ b/fs/ntfs3/attrib.c
@@ -149,7 +149,7 @@ out:
 int attr_allocate_clusters(struct ntfs_sb_info *sbi, struct runs_tree *run,
 			   CLST vcn, CLST lcn, CLST len, CLST *pre_alloc,
 			   enum ALLOCATE_OPT opt, CLST *alen, const size_t fr,
-			   CLST *new_lcn)
+			   CLST *new_lcn, CLST *new_len)
 {
 	int err;
 	CLST flen, vcn0 = vcn, pre = pre_alloc ? *pre_alloc : 0;
@@ -169,20 +169,36 @@ int attr_allocate_clusters(struct ntfs_sb_info *sbi, struct runs_tree *run,
 		if (err)
 			goto out;
 
-		if (new_lcn && vcn == vcn0)
-			*new_lcn = lcn;
+		if (vcn == vcn0) {
+			/* Return the first fragment. */
+			if (new_lcn)
+				*new_lcn = lcn;
+			if (new_len)
+				*new_len = flen;
+		}
 
 		/* Add new fragment into run storage. */
-		if (!run_add_entry(run, vcn, lcn, flen, opt == ALLOCATE_MFT)) {
+		if (!run_add_entry(run, vcn, lcn, flen, opt & ALLOCATE_MFT)) {
 			/* Undo last 'ntfs_look_for_free_space' */
 			mark_as_free_ex(sbi, lcn, len, false);
 			err = -ENOMEM;
 			goto out;
 		}
 
+		if (opt & ALLOCATE_ZERO) {
+			u8 shift = sbi->cluster_bits - SECTOR_SHIFT;
+
+			err = blkdev_issue_zeroout(sbi->sb->s_bdev,
+						   (sector_t)lcn << shift,
+						   (sector_t)flen << shift,
+						   GFP_NOFS, 0);
+			if (err)
+				goto out;
+		}
+
 		vcn += flen;
 
-		if (flen >= len || opt == ALLOCATE_MFT ||
+		if (flen >= len || (opt & ALLOCATE_MFT) ||
 		    (fr && run->count - cnt >= fr)) {
 			*alen = vcn - vcn0;
 			return 0;
@@ -257,7 +273,8 @@ int attr_make_nonresident(struct ntfs_inode *ni, struct ATTRIB *attr,
 		const char *data = resident_data(attr);
 
 		err = attr_allocate_clusters(sbi, run, 0, 0, len, NULL,
-					     ALLOCATE_DEF, &alen, 0, NULL);
+					     ALLOCATE_DEF, &alen, 0, NULL,
+					     NULL);
 		if (err)
 			goto out1;
 
@@ -552,13 +569,13 @@ add_alloc_in_same_attr_seg:
 			/* ~3 bytes per fragment. */
 			err = attr_allocate_clusters(
 				sbi, run, vcn, lcn, to_allocate, &pre_alloc,
-				is_mft ? ALLOCATE_MFT : 0, &alen,
+				is_mft ? ALLOCATE_MFT : ALLOCATE_DEF, &alen,
 				is_mft ? 0
 				       : (sbi->record_size -
 					  le32_to_cpu(rec->used) + 8) /
 							 3 +
 						 1,
-				NULL);
+				NULL, NULL);
 			if (err)
 				goto out;
 		}
@@ -855,8 +872,19 @@ bad_inode:
 	return err;
 }
 
+/*
+ * attr_data_get_block - Returns 'lcn' and 'len' for given 'vcn'.
+ *
+ * @new == NULL means just to get current mapping for 'vcn'
+ * @new != NULL means allocate real cluster if 'vcn' maps to hole
+ * @zero - zeroout new allocated clusters
+ *
+ *  NOTE:
+ *  - @new != NULL is called only for sparsed or compressed attributes.
+ *  - new allocated clusters are zeroed via blkdev_issue_zeroout.
+ */
 int attr_data_get_block(struct ntfs_inode *ni, CLST vcn, CLST clen, CLST *lcn,
-			CLST *len, bool *new)
+			CLST *len, bool *new, bool zero)
 {
 	int err = 0;
 	struct runs_tree *run = &ni->file.run;
@@ -865,29 +893,27 @@ int attr_data_get_block(struct ntfs_inode *ni, CLST vcn, CLST clen, CLST *lcn,
 	struct ATTRIB *attr = NULL, *attr_b;
 	struct ATTR_LIST_ENTRY *le, *le_b;
 	struct mft_inode *mi, *mi_b;
-	CLST hint, svcn, to_alloc, evcn1, next_svcn, asize, end;
+	CLST hint, svcn, to_alloc, evcn1, next_svcn, asize, end, vcn0, alen;
+	unsigned fr;
 	u64 total_size;
-	u32 clst_per_frame;
-	bool ok;
 
 	if (new)
 		*new = false;
 
+	/* Try to find in cache. */
 	down_read(&ni->file.run_lock);
-	ok = run_lookup_entry(run, vcn, lcn, len, NULL);
+	if (!run_lookup_entry(run, vcn, lcn, len, NULL))
+		*len = 0;
 	up_read(&ni->file.run_lock);
 
-	if (ok && (*lcn != SPARSE_LCN || !new)) {
-		/* Normal way. */
-		return 0;
+	if (*len) {
+		if (*lcn != SPARSE_LCN || !new)
+			return 0; /* Fast normal way without allocation. */
+		else if (clen > *len)
+			clen = *len;
 	}
 
-	if (!clen)
-		clen = 1;
-
-	if (ok && clen > *len)
-		clen = *len;
-
+	/* No cluster in cache or we need to allocate cluster in hole. */
 	sbi = ni->mi.sbi;
 	cluster_bits = sbi->cluster_bits;
 
@@ -913,12 +939,6 @@ int attr_data_get_block(struct ntfs_inode *ni, CLST vcn, CLST clen, CLST *lcn,
 		goto out;
 	}
 
-	clst_per_frame = 1u << attr_b->nres.c_unit;
-	to_alloc = (clen + clst_per_frame - 1) & ~(clst_per_frame - 1);
-
-	if (vcn + to_alloc > asize)
-		to_alloc = asize - vcn;
-
 	svcn = le64_to_cpu(attr_b->nres.svcn);
 	evcn1 = le64_to_cpu(attr_b->nres.evcn) + 1;
 
@@ -937,36 +957,68 @@ int attr_data_get_block(struct ntfs_inode *ni, CLST vcn, CLST clen, CLST *lcn,
 		evcn1 = le64_to_cpu(attr->nres.evcn) + 1;
 	}
 
+	/* Load in cache actual information. */
 	err = attr_load_runs(attr, ni, run, NULL);
 	if (err)
 		goto out;
 
-	if (!ok) {
-		ok = run_lookup_entry(run, vcn, lcn, len, NULL);
-		if (ok && (*lcn != SPARSE_LCN || !new)) {
-			/* Normal way. */
-			err = 0;
-			goto ok;
-		}
+	if (!*len) {
+		if (run_lookup_entry(run, vcn, lcn, len, NULL)) {
+			if (*lcn != SPARSE_LCN || !new)
+				goto ok; /* Slow normal way without allocation. */
 
-		if (!ok && !new) {
-			*len = 0;
-			err = 0;
+			if (clen > *len)
+				clen = *len;
+		} else if (!new) {
+			/* Here we may return -ENOENT.
+			 * In any case caller gets zero length. */
 			goto ok;
 		}
-
-		if (ok && clen > *len) {
-			clen = *len;
-			to_alloc = (clen + clst_per_frame - 1) &
-				   ~(clst_per_frame - 1);
-		}
 	}
 
 	if (!is_attr_ext(attr_b)) {
+		/* The code below only for sparsed or compressed attributes. */
 		err = -EINVAL;
 		goto out;
 	}
 
+	vcn0 = vcn;
+	to_alloc = clen;
+	fr = (sbi->record_size - le32_to_cpu(mi->mrec->used) + 8) / 3 + 1;
+	/* Allocate frame aligned clusters.
+	 * ntfs.sys usually uses 16 clusters per frame for sparsed or compressed.
+	 * ntfs3 uses 1 cluster per frame for new created sparsed files. */
+	if (attr_b->nres.c_unit) {
+		CLST clst_per_frame = 1u << attr_b->nres.c_unit;
+		CLST cmask = ~(clst_per_frame - 1);
+
+		/* Get frame aligned vcn and to_alloc. */
+		vcn = vcn0 & cmask;
+		to_alloc = ((vcn0 + clen + clst_per_frame - 1) & cmask) - vcn;
+		if (fr < clst_per_frame)
+			fr = clst_per_frame;
+		zero = true;
+
+		/* Check if 'vcn' and 'vcn0' in different attribute segments. */
+		if (vcn < svcn || evcn1 <= vcn) {
+			/* Load attribute for truncated vcn. */
+			attr = ni_find_attr(ni, attr_b, &le, ATTR_DATA, NULL, 0,
+					    &vcn, &mi);
+			if (!attr) {
+				err = -EINVAL;
+				goto out;
+			}
+			svcn = le64_to_cpu(attr->nres.svcn);
+			evcn1 = le64_to_cpu(attr->nres.evcn) + 1;
+			err = attr_load_runs(attr, ni, run, NULL);
+			if (err)
+				goto out;
+		}
+	}
+
+	if (vcn + to_alloc > asize)
+		to_alloc = asize - vcn;
+
 	/* Get the last LCN to allocate from. */
 	hint = 0;
 
@@ -980,18 +1032,33 @@ int attr_data_get_block(struct ntfs_inode *ni, CLST vcn, CLST clen, CLST *lcn,
 		hint = -1;
 	}
 
-	err = attr_allocate_clusters(
-		sbi, run, vcn, hint + 1, to_alloc, NULL, 0, len,
-		(sbi->record_size - le32_to_cpu(mi->mrec->used) + 8) / 3 + 1,
-		lcn);
+	/* Allocate and zeroout new clusters. */
+	err = attr_allocate_clusters(sbi, run, vcn, hint + 1, to_alloc, NULL,
+				     zero ? ALLOCATE_ZERO : ALLOCATE_DEF, &alen,
+				     fr, lcn, len);
 	if (err)
 		goto out;
 	*new = true;
 
-	end = vcn + *len;
-
+	end = vcn + alen;
 	total_size = le64_to_cpu(attr_b->nres.total_size) +
-		     ((u64)*len << cluster_bits);
+		     ((u64)alen << cluster_bits);
+
+	if (vcn != vcn0) {
+		if (!run_lookup_entry(run, vcn0, lcn, len, NULL)) {
+			err = -EINVAL;
+			goto out;
+		}
+		if (*lcn == SPARSE_LCN) {
+			/* Internal error. Should not happened. */
+			WARN_ON(1);
+			err = -EINVAL;
+			goto out;
+		}
+		/* Check case when vcn0 + len overlaps new allocated clusters. */
+		if (vcn0 + *len > end)
+			*len = end - vcn0;
+	}
 
 repack:
 	err = mi_pack_runs(mi, attr, run, max(end, evcn1) - svcn);
@@ -1516,7 +1583,7 @@ int attr_allocate_frame(struct ntfs_inode *ni, CLST frame, size_t compr_size,
 	struct ATTRIB *attr = NULL, *attr_b;
 	struct ATTR_LIST_ENTRY *le, *le_b;
 	struct mft_inode *mi, *mi_b;
-	CLST svcn, evcn1, next_svcn, lcn, len;
+	CLST svcn, evcn1, next_svcn, len;
 	CLST vcn, end, clst_data;
 	u64 total_size, valid_size, data_size;
 
@@ -1592,8 +1659,9 @@ int attr_allocate_frame(struct ntfs_inode *ni, CLST frame, size_t compr_size,
 		}
 
 		err = attr_allocate_clusters(sbi, run, vcn + clst_data,
-					     hint + 1, len - clst_data, NULL, 0,
-					     &alen, 0, &lcn);
+					     hint + 1, len - clst_data, NULL,
+					     ALLOCATE_DEF, &alen, 0, NULL,
+					     NULL);
 		if (err)
 			goto out;
 
diff --git a/fs/ntfs3/file.c b/fs/ntfs3/file.c
index 96ba3f5a8470e..63aef132e5292 100644
--- a/fs/ntfs3/file.c
+++ b/fs/ntfs3/file.c
@@ -122,8 +122,8 @@ static int ntfs_extend_initialized_size(struct file *file,
 			bits = sbi->cluster_bits;
 			vcn = pos >> bits;
 
-			err = attr_data_get_block(ni, vcn, 0, &lcn, &clen,
-						  NULL);
+			err = attr_data_get_block(ni, vcn, 1, &lcn, &clen, NULL,
+						  false);
 			if (err)
 				goto out;
 
@@ -180,18 +180,18 @@ static int ntfs_zero_range(struct inode *inode, u64 vbo, u64 vbo_to)
 	struct address_space *mapping = inode->i_mapping;
 	u32 blocksize = 1 << inode->i_blkbits;
 	pgoff_t idx = vbo >> PAGE_SHIFT;
-	u32 z_start = vbo & (PAGE_SIZE - 1);
+	u32 from = vbo & (PAGE_SIZE - 1);
 	pgoff_t idx_end = (vbo_to + PAGE_SIZE - 1) >> PAGE_SHIFT;
 	loff_t page_off;
 	struct buffer_head *head, *bh;
-	u32 bh_next, bh_off, z_end;
+	u32 bh_next, bh_off, to;
 	sector_t iblock;
 	struct page *page;
 
-	for (; idx < idx_end; idx += 1, z_start = 0) {
+	for (; idx < idx_end; idx += 1, from = 0) {
 		page_off = (loff_t)idx << PAGE_SHIFT;
-		z_end = (page_off + PAGE_SIZE) > vbo_to ? (vbo_to - page_off)
-							: PAGE_SIZE;
+		to = (page_off + PAGE_SIZE) > vbo_to ? (vbo_to - page_off)
+						     : PAGE_SIZE;
 		iblock = page_off >> inode->i_blkbits;
 
 		page = find_or_create_page(mapping, idx,
@@ -208,7 +208,7 @@ static int ntfs_zero_range(struct inode *inode, u64 vbo, u64 vbo_to)
 		do {
 			bh_next = bh_off + blocksize;
 
-			if (bh_next <= z_start || bh_off >= z_end)
+			if (bh_next <= from || bh_off >= to)
 				continue;
 
 			if (!buffer_mapped(bh)) {
@@ -242,7 +242,7 @@ static int ntfs_zero_range(struct inode *inode, u64 vbo, u64 vbo_to)
 		} while (bh_off = bh_next, iblock += 1,
 			 head != (bh = bh->b_this_page));
 
-		zero_user_segment(page, z_start, z_end);
+		zero_user_segment(page, from, to);
 
 		unlock_page(page);
 		put_page(page);
@@ -253,80 +253,6 @@ out:
 	return err;
 }
 
-/*
- * ntfs_sparse_cluster - Helper function to zero a new allocated clusters.
- *
- * NOTE: 512 <= cluster size <= 2M
- */
-void ntfs_sparse_cluster(struct inode *inode, struct page *page0, CLST vcn,
-			 CLST len)
-{
-	struct address_space *mapping = inode->i_mapping;
-	struct ntfs_sb_info *sbi = inode->i_sb->s_fs_info;
-	u8 cluster_bits = sbi->cluster_bits;
-	u64 vbo = (u64)vcn << cluster_bits;
-	u64 bytes = (u64)len << cluster_bits;
-	u32 blocksize = 1 << inode->i_blkbits;
-	pgoff_t idx0 = page0 ? page0->index : -1;
-	loff_t vbo_clst = vbo & sbi->cluster_mask_inv;
-	loff_t end = ntfs_up_cluster(sbi, vbo + bytes);
-	pgoff_t idx = vbo_clst >> PAGE_SHIFT;
-	u32 from = vbo_clst & (PAGE_SIZE - 1);
-	pgoff_t idx_end = (end + PAGE_SIZE - 1) >> PAGE_SHIFT;
-	loff_t page_off;
-	u32 to;
-	bool partial;
-	struct page *page;
-
-	for (; idx < idx_end; idx += 1, from = 0) {
-		page = idx == idx0 ? page0 : grab_cache_page(mapping, idx);
-
-		if (!page)
-			continue;
-
-		page_off = (loff_t)idx << PAGE_SHIFT;
-		to = (page_off + PAGE_SIZE) > end ? (end - page_off)
-						  : PAGE_SIZE;
-		partial = false;
-
-		if ((from || PAGE_SIZE != to) &&
-		    likely(!page_has_buffers(page))) {
-			create_empty_buffers(page, blocksize, 0);
-		}
-
-		if (page_has_buffers(page)) {
-			struct buffer_head *head, *bh;
-			u32 bh_off = 0;
-
-			bh = head = page_buffers(page);
-			do {
-				u32 bh_next = bh_off + blocksize;
-
-				if (from <= bh_off && bh_next <= to) {
-					set_buffer_uptodate(bh);
-					mark_buffer_dirty(bh);
-				} else if (!buffer_uptodate(bh)) {
-					partial = true;
-				}
-				bh_off = bh_next;
-			} while (head != (bh = bh->b_this_page));
-		}
-
-		zero_user_segment(page, from, to);
-
-		if (!partial)
-			SetPageUptodate(page);
-		flush_dcache_page(page);
-		set_page_dirty(page);
-
-		if (idx != idx0) {
-			unlock_page(page);
-			put_page(page);
-		}
-		cond_resched();
-	}
-}
-
 /*
  * ntfs_file_mmap - file_operations::mmap
  */
@@ -368,13 +294,9 @@ static int ntfs_file_mmap(struct file *file, struct vm_area_struct *vma)
 
 			for (; vcn < end; vcn += len) {
 				err = attr_data_get_block(ni, vcn, 1, &lcn,
-							  &len, &new);
+							  &len, &new, true);
 				if (err)
 					goto out;
-
-				if (!new)
-					continue;
-				ntfs_sparse_cluster(inode, NULL, vcn, 1);
 			}
 		}
 
@@ -518,7 +440,8 @@ static long ntfs_fallocate(struct file *file, int mode, loff_t vbo, loff_t len)
 	struct ntfs_sb_info *sbi = sb->s_fs_info;
 	struct ntfs_inode *ni = ntfs_i(inode);
 	loff_t end = vbo + len;
-	loff_t vbo_down = round_down(vbo, PAGE_SIZE);
+	loff_t vbo_down = round_down(vbo, max_t(unsigned long,
+						sbi->cluster_size, PAGE_SIZE));
 	bool is_supported_holes = is_sparsed(ni) || is_compressed(ni);
 	loff_t i_size, new_size;
 	bool map_locked;
@@ -571,7 +494,8 @@ static long ntfs_fallocate(struct file *file, int mode, loff_t vbo, loff_t len)
 		u32 frame_size;
 		loff_t mask, vbo_a, end_a, tmp;
 
-		err = filemap_write_and_wait_range(mapping, vbo, LLONG_MAX);
+		err = filemap_write_and_wait_range(mapping, vbo_down,
+						   LLONG_MAX);
 		if (err)
 			goto out;
 
@@ -672,39 +596,35 @@ static long ntfs_fallocate(struct file *file, int mode, loff_t vbo, loff_t len)
 			goto out;
 
 		if (is_supported_holes) {
-			CLST vcn_v = bytes_to_cluster(sbi, ni->i_valid);
 			CLST vcn = vbo >> sbi->cluster_bits;
 			CLST cend = bytes_to_cluster(sbi, end);
+			CLST cend_v = bytes_to_cluster(sbi, ni->i_valid);
 			CLST lcn, clen;
 			bool new;
 
+			if (cend_v > cend)
+				cend_v = cend;
+
 			/*
-			 * Allocate but do not zero new clusters. (see below comments)
-			 * This breaks security: One can read unused on-disk areas.
+			 * Allocate and zero new clusters.
 			 * Zeroing these clusters may be too long.
-			 * Maybe we should check here for root rights?
+			 */
+			for (; vcn < cend_v; vcn += clen) {
+				err = attr_data_get_block(ni, vcn, cend_v - vcn,
+							  &lcn, &clen, &new,
+							  true);
+				if (err)
+					goto out;
+			}
+			/*
+			 * Allocate but not zero new clusters.
 			 */
 			for (; vcn < cend; vcn += clen) {
 				err = attr_data_get_block(ni, vcn, cend - vcn,
-							  &lcn, &clen, &new);
+							  &lcn, &clen, &new,
+							  false);
 				if (err)
 					goto out;
-				if (!new || vcn >= vcn_v)
-					continue;
-
-				/*
-				 * Unwritten area.
-				 * NTFS is not able to store several unwritten areas.
-				 * Activate 'ntfs_sparse_cluster' to zero new allocated clusters.
-				 *
-				 * Dangerous in case:
-				 * 1G of sparsed clusters + 1 cluster of data =>
-				 * valid_size == 1G + 1 cluster
-				 * fallocate(1G) will zero 1G and this can be very long
-				 * xfstest 016/086 will fail without 'ntfs_sparse_cluster'.
-				 */
-				ntfs_sparse_cluster(inode, NULL, vcn,
-						    min(vcn_v - vcn, clen));
 			}
 		}
 
@@ -925,8 +845,8 @@ static ssize_t ntfs_compress_write(struct kiocb *iocb, struct iov_iter *from)
 		frame_vbo = valid & ~(frame_size - 1);
 		off = valid & (frame_size - 1);
 
-		err = attr_data_get_block(ni, frame << NTFS_LZNT_CUNIT, 0, &lcn,
-					  &clen, NULL);
+		err = attr_data_get_block(ni, frame << NTFS_LZNT_CUNIT, 1, &lcn,
+					  &clen, NULL, false);
 		if (err)
 			goto out;
 
diff --git a/fs/ntfs3/frecord.c b/fs/ntfs3/frecord.c
index ff938d3cd5efe..f1df52dfab74b 100644
--- a/fs/ntfs3/frecord.c
+++ b/fs/ntfs3/frecord.c
@@ -2224,7 +2224,7 @@ int ni_decompress_file(struct ntfs_inode *ni)
 
 		for (vcn = vbo >> sbi->cluster_bits; vcn < end; vcn += clen) {
 			err = attr_data_get_block(ni, vcn, cend - vcn, &lcn,
-						  &clen, &new);
+						  &clen, &new, false);
 			if (err)
 				goto out;
 		}
diff --git a/fs/ntfs3/index.c b/fs/ntfs3/index.c
index 50c90d7e8a78b..bc9ab93db1d0e 100644
--- a/fs/ntfs3/index.c
+++ b/fs/ntfs3/index.c
@@ -1347,8 +1347,8 @@ static int indx_create_allocate(struct ntfs_index *indx, struct ntfs_inode *ni,
 
 	run_init(&run);
 
-	err = attr_allocate_clusters(sbi, &run, 0, 0, len, NULL, 0, &alen, 0,
-				     NULL);
+	err = attr_allocate_clusters(sbi, &run, 0, 0, len, NULL, ALLOCATE_DEF,
+				     &alen, 0, NULL, NULL);
 	if (err)
 		goto out;
 
diff --git a/fs/ntfs3/inode.c b/fs/ntfs3/inode.c
index d8d00ffe7a1f7..bf56e78de653f 100644
--- a/fs/ntfs3/inode.c
+++ b/fs/ntfs3/inode.c
@@ -577,7 +577,8 @@ static noinline int ntfs_get_block_vbo(struct inode *inode, u64 vbo,
 	off = vbo & sbi->cluster_mask;
 	new = false;
 
-	err = attr_data_get_block(ni, vcn, 1, &lcn, &len, create ? &new : NULL);
+	err = attr_data_get_block(ni, vcn, 1, &lcn, &len, create ? &new : NULL,
+				  create && sbi->cluster_size > PAGE_SIZE);
 	if (err)
 		goto out;
 
@@ -595,11 +596,8 @@ static noinline int ntfs_get_block_vbo(struct inode *inode, u64 vbo,
 		WARN_ON(1);
 	}
 
-	if (new) {
+	if (new)
 		set_buffer_new(bh);
-		if ((len << cluster_bits) > block_size)
-			ntfs_sparse_cluster(inode, page, vcn, len);
-	}
 
 	lbo = ((u64)lcn << cluster_bits) + off;
 
@@ -1537,8 +1535,8 @@ struct inode *ntfs_create_inode(struct user_namespace *mnt_userns,
 				cpu_to_le64(ntfs_up_cluster(sbi, nsize));
 
 			err = attr_allocate_clusters(sbi, &ni->file.run, 0, 0,
-						     clst, NULL, 0, &alen, 0,
-						     NULL);
+						     clst, NULL, ALLOCATE_DEF,
+						     &alen, 0, NULL, NULL);
 			if (err)
 				goto out5;
 
diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h
index 6e23553104331..5269d4e66685b 100644
--- a/fs/ntfs3/ntfs_fs.h
+++ b/fs/ntfs3/ntfs_fs.h
@@ -127,6 +127,7 @@ struct ntfs_buffers {
 enum ALLOCATE_OPT {
 	ALLOCATE_DEF = 0, // Allocate all clusters.
 	ALLOCATE_MFT = 1, // Allocate for MFT.
+	ALLOCATE_ZERO = 2, // Zeroout new allocated clusters
 };
 
 enum bitmap_mutex_classes {
@@ -415,7 +416,7 @@ enum REPARSE_SIGN {
 int attr_allocate_clusters(struct ntfs_sb_info *sbi, struct runs_tree *run,
 			   CLST vcn, CLST lcn, CLST len, CLST *pre_alloc,
 			   enum ALLOCATE_OPT opt, CLST *alen, const size_t fr,
-			   CLST *new_lcn);
+			   CLST *new_lcn, CLST *new_len);
 int attr_make_nonresident(struct ntfs_inode *ni, struct ATTRIB *attr,
 			  struct ATTR_LIST_ENTRY *le, struct mft_inode *mi,
 			  u64 new_size, struct runs_tree *run,
@@ -425,7 +426,7 @@ int attr_set_size(struct ntfs_inode *ni, enum ATTR_TYPE type,
 		  u64 new_size, const u64 *new_valid, bool keep_prealloc,
 		  struct ATTRIB **ret);
 int attr_data_get_block(struct ntfs_inode *ni, CLST vcn, CLST clen, CLST *lcn,
-			CLST *len, bool *new);
+			CLST *len, bool *new, bool zero);
 int attr_data_read_resident(struct ntfs_inode *ni, struct page *page);
 int attr_data_write_resident(struct ntfs_inode *ni, struct page *page);
 int attr_load_runs_vcn(struct ntfs_inode *ni, enum ATTR_TYPE type,
@@ -490,8 +491,6 @@ extern const struct file_operations ntfs_dir_operations;
 /* Globals from file.c */
 int ntfs_getattr(struct user_namespace *mnt_userns, const struct path *path,
 		 struct kstat *stat, u32 request_mask, u32 flags);
-void ntfs_sparse_cluster(struct inode *inode, struct page *page0, CLST vcn,
-			 CLST len);
 int ntfs3_setattr(struct user_namespace *mnt_userns, struct dentry *dentry,
 		  struct iattr *attr);
 int ntfs_file_open(struct inode *inode, struct file *file);
-- 
GitLab


From 07f4aa9dd245661414a2db0574bed9bc5736ccfd Mon Sep 17 00:00:00 2001
From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
Date: Fri, 7 Oct 2022 18:55:03 +0300
Subject: [PATCH 063/875] fs/ntfs3: Fix wrong indentations

Also simplifying code.

Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/fslog.c | 3 +--
 fs/ntfs3/index.c | 8 ++++----
 fs/ntfs3/inode.c | 8 +++++---
 3 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/fs/ntfs3/fslog.c b/fs/ntfs3/fslog.c
index 5289c25b1ee43..e61545b9772e8 100644
--- a/fs/ntfs3/fslog.c
+++ b/fs/ntfs3/fslog.c
@@ -4824,8 +4824,7 @@ next_dirty_page_vcn:
 		goto out;
 	}
 	attr = oa->attr;
-	t64 = le64_to_cpu(attr->nres.alloc_size);
-	if (size > t64) {
+	if (size > le64_to_cpu(attr->nres.alloc_size)) {
 		attr->nres.valid_size = attr->nres.data_size =
 			attr->nres.alloc_size = cpu_to_le64(size);
 	}
diff --git a/fs/ntfs3/index.c b/fs/ntfs3/index.c
index bc9ab93db1d0e..a2e1e07b5bb8f 100644
--- a/fs/ntfs3/index.c
+++ b/fs/ntfs3/index.c
@@ -625,9 +625,8 @@ void fnd_clear(struct ntfs_fnd *fnd)
 static int fnd_push(struct ntfs_fnd *fnd, struct indx_node *n,
 		    struct NTFS_DE *e)
 {
-	int i;
+	int i = fnd->level;
 
-	i = fnd->level;
 	if (i < 0 || i >= ARRAY_SIZE(fnd->nodes))
 		return -EINVAL;
 	fnd->nodes[i] = n;
@@ -2121,9 +2120,10 @@ static int indx_get_entry_to_replace(struct ntfs_index *indx,
 	fnd->de[level] = e;
 	indx_write(indx, ni, n, 0);
 
-	/* Check to see if this action created an empty leaf. */
-	if (ib_is_leaf(ib) && ib_is_empty(ib))
+	if (ib_is_leaf(ib) && ib_is_empty(ib)) {
+		/* An empty leaf. */
 		return 0;
+	}
 
 out:
 	fnd_clear(fnd);
diff --git a/fs/ntfs3/inode.c b/fs/ntfs3/inode.c
index bf56e78de653f..45a4ddc0bcdc8 100644
--- a/fs/ntfs3/inode.c
+++ b/fs/ntfs3/inode.c
@@ -1818,11 +1818,12 @@ static int ntfs_translate_junction(const struct super_block *sb,
 
 	/* Make translated path a relative path to mount point */
 	strcpy(translated, "./");
-	++link_path;	/* Skip leading / */
+	++link_path; /* Skip leading / */
 	for (tl_len = sizeof("./") - 1; *link_path; ++link_path) {
 		if (*link_path == '/') {
 			if (PATH_MAX - tl_len < sizeof("../")) {
-				ntfs_err(sb, "Link path %s has too many components",
+				ntfs_err(sb,
+					 "Link path %s has too many components",
 					 link_path);
 				err = -EINVAL;
 				goto out;
@@ -1838,7 +1839,8 @@ static int ntfs_translate_junction(const struct super_block *sb,
 		++target_start;
 
 	if (!*target_start) {
-		ntfs_err(sb, "Link target (%s) missing drive separator", target);
+		ntfs_err(sb, "Link target (%s) missing drive separator",
+			 target);
 		err = -EINVAL;
 		goto out;
 	}
-- 
GitLab


From 2b108260ea2c9ec07651aea4911d7e2e6ab560f7 Mon Sep 17 00:00:00 2001
From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
Date: Fri, 7 Oct 2022 19:53:30 +0300
Subject: [PATCH 064/875] fs/ntfs3: atomic_open implementation

Added ntfs_atomic_open function.
Relaxed locking in ntfs_create_inode.

Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/inode.c |  24 ++++++++++--
 fs/ntfs3/namei.c | 100 +++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 120 insertions(+), 4 deletions(-)

diff --git a/fs/ntfs3/inode.c b/fs/ntfs3/inode.c
index 45a4ddc0bcdc8..7e369d69d3f22 100644
--- a/fs/ntfs3/inode.c
+++ b/fs/ntfs3/inode.c
@@ -1184,6 +1184,18 @@ out:
 	return ERR_PTR(err);
 }
 
+/*
+ * ntfs_create_inode
+ *
+ * Helper function for:
+ * - ntfs_create
+ * - ntfs_mknod
+ * - ntfs_symlink
+ * - ntfs_mkdir
+ * - ntfs_atomic_open
+ * 
+ * NOTE: if fnd != NULL (ntfs_atomic_open) then @dir is locked
+ */
 struct inode *ntfs_create_inode(struct user_namespace *mnt_userns,
 				struct inode *dir, struct dentry *dentry,
 				const struct cpu_str *uni, umode_t mode,
@@ -1213,7 +1225,8 @@ struct inode *ntfs_create_inode(struct user_namespace *mnt_userns,
 	struct REPARSE_DATA_BUFFER *rp = NULL;
 	bool rp_inserted = false;
 
-	ni_lock_dir(dir_ni);
+	if (!fnd)
+		ni_lock_dir(dir_ni);
 
 	dir_root = indx_get_root(&dir_ni->dir, dir_ni, NULL, NULL);
 	if (!dir_root) {
@@ -1583,7 +1596,8 @@ struct inode *ntfs_create_inode(struct user_namespace *mnt_userns,
 		goto out6;
 
 	/* Unlock parent directory before ntfs_init_acl. */
-	ni_unlock(dir_ni);
+	if (!fnd)
+		ni_unlock(dir_ni);
 
 	inode->i_generation = le16_to_cpu(rec->seq);
 
@@ -1643,7 +1657,8 @@ struct inode *ntfs_create_inode(struct user_namespace *mnt_userns,
 out7:
 
 	/* Undo 'indx_insert_entry'. */
-	ni_lock_dir(dir_ni);
+	if (!fnd)
+		ni_lock_dir(dir_ni);
 	indx_delete_entry(&dir_ni->dir, dir_ni, new_de + 1,
 			  le16_to_cpu(new_de->key_size), sbi);
 	/* ni_unlock(dir_ni); will be called later. */
@@ -1671,7 +1686,8 @@ out2:
 
 out1:
 	if (err) {
-		ni_unlock(dir_ni);
+		if (!fnd)
+			ni_unlock(dir_ni);
 		return ERR_PTR(err);
 	}
 
diff --git a/fs/ntfs3/namei.c b/fs/ntfs3/namei.c
index ad6d16dec9f06..daff8d0cd63dc 100644
--- a/fs/ntfs3/namei.c
+++ b/fs/ntfs3/namei.c
@@ -8,6 +8,7 @@
 #include <linux/fs.h>
 #include <linux/nls.h>
 #include <linux/ctype.h>
+#include <linux/posix_acl.h>
 
 #include "debug.h"
 #include "ntfs.h"
@@ -334,6 +335,104 @@ out:
 	return err;
 }
 
+/*
+ * ntfs_atomic_open
+ *
+ * inode_operations::atomic_open
+ */
+static int ntfs_atomic_open(struct inode *dir, struct dentry *dentry,
+			    struct file *file, u32 flags, umode_t mode)
+{
+	int err;
+	struct inode *inode;
+	struct ntfs_fnd *fnd = NULL;
+	struct ntfs_inode *ni = ntfs_i(dir);
+	struct dentry *d = NULL;
+	struct cpu_str *uni = __getname();
+	bool locked = false;
+
+	if (!uni)
+		return -ENOMEM;
+
+	err = ntfs_nls_to_utf16(ni->mi.sbi, dentry->d_name.name,
+				dentry->d_name.len, uni, NTFS_NAME_LEN,
+				UTF16_HOST_ENDIAN);
+	if (err < 0)
+		goto out;
+
+#ifdef CONFIG_NTFS3_FS_POSIX_ACL
+	if (IS_POSIXACL(dir)) {
+		/* 
+		 * Load in cache current acl to avoid ni_lock(dir):
+		 * ntfs_create_inode -> ntfs_init_acl -> posix_acl_create ->
+		 * ntfs_get_acl -> ntfs_get_acl_ex -> ni_lock
+		 */
+		struct posix_acl *p = get_acl(dir, ACL_TYPE_DEFAULT);
+
+		if (IS_ERR(p)) {
+			err = PTR_ERR(p);
+			goto out;
+		}
+		posix_acl_release(p);
+	}
+#endif
+
+	if (d_in_lookup(dentry)) {
+		ni_lock_dir(ni);
+		locked = true;
+		fnd = fnd_get();
+		if (!fnd) {
+			err = -ENOMEM;
+			goto out1;
+		}
+
+		d = d_splice_alias(dir_search_u(dir, uni, fnd), dentry);
+		if (IS_ERR(d)) {
+			err = PTR_ERR(d);
+			d = NULL;
+			goto out2;
+		}
+
+		if (d)
+			dentry = d;
+	}
+
+	if (!(flags & O_CREAT) || d_really_is_positive(dentry)) {
+		err = finish_no_open(file, d);
+		goto out2;
+	}
+
+	file->f_mode |= FMODE_CREATED;
+
+	/*
+	 * fnd contains tree's path to insert to.
+	 * If fnd is not NULL then dir is locked.
+	 */
+
+	/*
+	 * Unfortunately I don't know how to get here correct 'struct nameidata *nd'
+	 * or 'struct user_namespace *mnt_userns'.
+	 * See atomic_open in fs/namei.c.
+	 * This is why xfstest/633 failed.
+	 * Looks like ntfs_atomic_open must accept 'struct user_namespace *mnt_userns' as argument.
+	 */
+
+	inode = ntfs_create_inode(&init_user_ns, dir, dentry, uni, mode, 0,
+				  NULL, 0, fnd);
+	err = IS_ERR(inode) ? PTR_ERR(inode)
+			    : finish_open(file, dentry, ntfs_file_open);
+	dput(d);
+
+out2:
+	fnd_put(fnd);
+out1:
+	if (locked)
+		ni_unlock(ni);
+out:
+	__putname(uni);
+	return err;
+}
+
 struct dentry *ntfs3_get_parent(struct dentry *child)
 {
 	struct inode *inode = d_inode(child);
@@ -500,6 +599,7 @@ const struct inode_operations ntfs_dir_inode_operations = {
 	.setattr	= ntfs3_setattr,
 	.getattr	= ntfs_getattr,
 	.listxattr	= ntfs_listxattr,
+	.atomic_open	= ntfs_atomic_open,
 	.fiemap		= ntfs_fiemap,
 };
 
-- 
GitLab


From ad26a9c84510af7252e582e811de970433a9758f Mon Sep 17 00:00:00 2001
From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
Date: Fri, 7 Oct 2022 20:08:06 +0300
Subject: [PATCH 065/875] fs/ntfs3: Fixing wrong logic in attr_set_size and
 ntfs_fallocate

There were 2 problems:
- in some cases we lost dirty flag;
- cluster allocation can be called even when it wasn't needed.
Fixes xfstest generic/465

Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/attrib.c | 25 +++++++++++--------------
 fs/ntfs3/file.c   | 30 ++++++++++++++++++------------
 fs/ntfs3/index.c  |  9 +++++++++
 fs/ntfs3/inode.c  | 17 +++++------------
 4 files changed, 43 insertions(+), 38 deletions(-)

diff --git a/fs/ntfs3/attrib.c b/fs/ntfs3/attrib.c
index eda83a37a0c3f..91ea73e6f4fe2 100644
--- a/fs/ntfs3/attrib.c
+++ b/fs/ntfs3/attrib.c
@@ -414,6 +414,7 @@ int attr_set_size(struct ntfs_inode *ni, enum ATTR_TYPE type,
 	CLST alen, vcn, lcn, new_alen, old_alen, svcn, evcn;
 	CLST next_svcn, pre_alloc = -1, done = 0;
 	bool is_ext, is_bad = false;
+	bool dirty = false;
 	u32 align;
 	struct MFT_REC *rec;
 
@@ -434,8 +435,10 @@ again:
 			return err;
 
 		/* Return if file is still resident. */
-		if (!attr_b->non_res)
+		if (!attr_b->non_res) {
+			dirty = true;
 			goto ok1;
+		}
 
 		/* Layout of records may be changed, so do a full search. */
 		goto again;
@@ -458,7 +461,7 @@ again_1:
 
 	if (keep_prealloc && new_size < old_size) {
 		attr_b->nres.data_size = cpu_to_le64(new_size);
-		mi_b->dirty = true;
+		mi_b->dirty = dirty = true;
 		goto ok;
 	}
 
@@ -504,7 +507,7 @@ next_le:
 
 		if (new_alloc <= old_alloc) {
 			attr_b->nres.data_size = cpu_to_le64(new_size);
-			mi_b->dirty = true;
+			mi_b->dirty = dirty = true;
 			goto ok;
 		}
 
@@ -595,7 +598,7 @@ pack_runs:
 		next_svcn = le64_to_cpu(attr->nres.evcn) + 1;
 		new_alloc_tmp = (u64)next_svcn << cluster_bits;
 		attr_b->nres.alloc_size = cpu_to_le64(new_alloc_tmp);
-		mi_b->dirty = true;
+		mi_b->dirty = dirty = true;
 
 		if (next_svcn >= vcn && !to_allocate) {
 			/* Normal way. Update attribute and exit. */
@@ -681,7 +684,7 @@ pack_runs:
 		old_valid = old_size = old_alloc = (u64)vcn << cluster_bits;
 		attr_b->nres.valid_size = attr_b->nres.data_size =
 			attr_b->nres.alloc_size = cpu_to_le64(old_size);
-		mi_b->dirty = true;
+		mi_b->dirty = dirty = true;
 		goto again_1;
 	}
 
@@ -743,7 +746,7 @@ pack_runs:
 				attr_b->nres.valid_size =
 					attr_b->nres.alloc_size;
 		}
-		mi_b->dirty = true;
+		mi_b->dirty = dirty = true;
 
 		err = run_deallocate_ex(sbi, run, vcn, evcn - vcn + 1, &dlen,
 					true);
@@ -804,16 +807,9 @@ ok1:
 	if (ret)
 		*ret = attr_b;
 
-	/* Update inode_set_bytes. */
 	if (((type == ATTR_DATA && !name_len) ||
 	     (type == ATTR_ALLOC && name == I30_NAME))) {
-		bool dirty = false;
-
-		if (ni->vfs_inode.i_size != new_size) {
-			ni->vfs_inode.i_size = new_size;
-			dirty = true;
-		}
-
+		/* Update inode_set_bytes. */
 		if (attr_b->non_res) {
 			new_alloc = le64_to_cpu(attr_b->nres.alloc_size);
 			if (inode_get_bytes(&ni->vfs_inode) != new_alloc) {
@@ -822,6 +818,7 @@ ok1:
 			}
 		}
 
+		/* Don't forget to update duplicate information in parent. */
 		if (dirty) {
 			ni->ni_flags |= NI_FLAG_UPDATE_PARENT;
 			mark_inode_dirty(&ni->vfs_inode);
diff --git a/fs/ntfs3/file.c b/fs/ntfs3/file.c
index 63aef132e5292..511e58f2b0f8b 100644
--- a/fs/ntfs3/file.c
+++ b/fs/ntfs3/file.c
@@ -337,7 +337,6 @@ static int ntfs_extend(struct inode *inode, loff_t pos, size_t count,
 		err = ntfs_set_size(inode, end);
 		if (err)
 			goto out;
-		inode->i_size = end;
 	}
 
 	if (extend_init && !is_compressed(ni)) {
@@ -588,12 +587,14 @@ static long ntfs_fallocate(struct file *file, int mode, loff_t vbo, loff_t len)
 		if (err)
 			goto out;
 
-		/*
-		 * Allocate clusters, do not change 'valid' size.
-		 */
-		err = ntfs_set_size(inode, new_size);
-		if (err)
-			goto out;
+		if (new_size > i_size) {
+			/*
+			 * Allocate clusters, do not change 'valid' size.
+			 */
+			err = ntfs_set_size(inode, new_size);
+			if (err)
+				goto out;
+		}
 
 		if (is_supported_holes) {
 			CLST vcn = vbo >> sbi->cluster_bits;
@@ -635,6 +636,8 @@ static long ntfs_fallocate(struct file *file, int mode, loff_t vbo, loff_t len)
 					    &ni->file.run, i_size, &ni->i_valid,
 					    true, NULL);
 			ni_unlock(ni);
+		} else if (new_size > i_size) {
+			inode->i_size = new_size;
 		}
 	}
 
@@ -678,7 +681,7 @@ int ntfs3_setattr(struct user_namespace *mnt_userns, struct dentry *dentry,
 		goto out;
 
 	if (ia_valid & ATTR_SIZE) {
-		loff_t oldsize = inode->i_size;
+		loff_t newsize, oldsize;
 
 		if (WARN_ON(ni->ni_flags & NI_FLAG_COMPRESSED_MASK)) {
 			/* Should never be here, see ntfs_file_open(). */
@@ -686,16 +689,19 @@ int ntfs3_setattr(struct user_namespace *mnt_userns, struct dentry *dentry,
 			goto out;
 		}
 		inode_dio_wait(inode);
+		oldsize = inode->i_size;
+		newsize = attr->ia_size;
 
-		if (attr->ia_size <= oldsize)
-			err = ntfs_truncate(inode, attr->ia_size);
-		else if (attr->ia_size > oldsize)
-			err = ntfs_extend(inode, attr->ia_size, 0, NULL);
+		if (newsize <= oldsize)
+			err = ntfs_truncate(inode, newsize);
+		else
+			err = ntfs_extend(inode, newsize, 0, NULL);
 
 		if (err)
 			goto out;
 
 		ni->ni_flags |= NI_FLAG_UPDATE_PARENT;
+		inode->i_size = newsize;
 	}
 
 	setattr_copy(mnt_userns, inode, attr);
diff --git a/fs/ntfs3/index.c b/fs/ntfs3/index.c
index a2e1e07b5bb8f..35369ae5c438c 100644
--- a/fs/ntfs3/index.c
+++ b/fs/ntfs3/index.c
@@ -1445,6 +1445,9 @@ static int indx_add_allocate(struct ntfs_index *indx, struct ntfs_inode *ni,
 		goto out1;
 	}
 
+	if (in->name == I30_NAME)
+		ni->vfs_inode.i_size = data_size;
+
 	*vbn = bit << indx->idx2vbn_bits;
 
 	return 0;
@@ -1978,6 +1981,9 @@ static int indx_shrink(struct ntfs_index *indx, struct ntfs_inode *ni,
 	if (err)
 		return err;
 
+	if (in->name == I30_NAME)
+		ni->vfs_inode.i_size = new_data;
+
 	bpb = bitmap_size(bit);
 	if (bpb * 8 == nbits)
 		return 0;
@@ -2461,6 +2467,9 @@ int indx_delete_entry(struct ntfs_index *indx, struct ntfs_inode *ni,
 
 		err = attr_set_size(ni, ATTR_ALLOC, in->name, in->name_len,
 				    &indx->alloc_run, 0, NULL, false, NULL);
+		if (in->name == I30_NAME)
+			ni->vfs_inode.i_size = 0;
+
 		err = ni_remove_attr(ni, ATTR_ALLOC, in->name, in->name_len,
 				     false, NULL);
 		run_close(&indx->alloc_run);
diff --git a/fs/ntfs3/inode.c b/fs/ntfs3/inode.c
index 7e369d69d3f22..1afe6246aa935 100644
--- a/fs/ntfs3/inode.c
+++ b/fs/ntfs3/inode.c
@@ -551,17 +551,6 @@ static noinline int ntfs_get_block_vbo(struct inode *inode, u64 vbo,
 	clear_buffer_new(bh);
 	clear_buffer_uptodate(bh);
 
-	/* Direct write uses 'create=0'. */
-	if (!create && vbo >= ni->i_valid) {
-		/* Out of valid. */
-		return 0;
-	}
-
-	if (vbo >= inode->i_size) {
-		/* Out of size. */
-		return 0;
-	}
-
 	if (is_resident(ni)) {
 		ni_lock(ni);
 		err = attr_data_read_resident(ni, page);
@@ -625,7 +614,6 @@ static noinline int ntfs_get_block_vbo(struct inode *inode, u64 vbo,
 		}
 	} else if (vbo >= valid) {
 		/* Read out of valid data. */
-		/* Should never be here 'cause already checked. */
 		clear_buffer_mapped(bh);
 	} else if (vbo + bytes <= valid) {
 		/* Normal read. */
@@ -975,6 +963,11 @@ int ntfs_write_end(struct file *file, struct address_space *mapping,
 			dirty = true;
 		}
 
+		if (pos + err > inode->i_size) {
+			inode->i_size = pos + err;
+			dirty = true;
+		}
+
 		if (dirty)
 			mark_inode_dirty(inode);
 	}
-- 
GitLab


From 0ad9dfcb8d3fd6ef91983ccb93fafbf9e3115796 Mon Sep 17 00:00:00 2001
From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
Date: Fri, 7 Oct 2022 20:16:15 +0300
Subject: [PATCH 066/875] fs/ntfs3: Changing locking in ntfs_rename

In some cases we can be in deadlock
because we tried to lock the same dir.

Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/namei.c   | 4 ++++
 fs/ntfs3/ntfs_fs.h | 6 ++++++
 2 files changed, 10 insertions(+)

diff --git a/fs/ntfs3/namei.c b/fs/ntfs3/namei.c
index daff8d0cd63dc..0e72d2067804f 100644
--- a/fs/ntfs3/namei.c
+++ b/fs/ntfs3/namei.c
@@ -305,6 +305,8 @@ static int ntfs_rename(struct user_namespace *mnt_userns, struct inode *dir,
 
 	ni_lock_dir(dir_ni);
 	ni_lock(ni);
+	if (dir_ni != new_dir_ni)
+		ni_lock_dir2(new_dir_ni);
 
 	is_bad = false;
 	err = ni_rename(dir_ni, new_dir_ni, ni, de, new_de, &is_bad);
@@ -328,6 +330,8 @@ static int ntfs_rename(struct user_namespace *mnt_userns, struct inode *dir,
 			ntfs_sync_inode(inode);
 	}
 
+	if (dir_ni != new_dir_ni)
+		ni_unlock(new_dir_ni);
 	ni_unlock(ni);
 	ni_unlock(dir_ni);
 out:
diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h
index 5269d4e66685b..776993ae498b2 100644
--- a/fs/ntfs3/ntfs_fs.h
+++ b/fs/ntfs3/ntfs_fs.h
@@ -334,6 +334,7 @@ enum ntfs_inode_mutex_lock_class {
 	NTFS_INODE_MUTEX_REPARSE,
 	NTFS_INODE_MUTEX_NORMAL,
 	NTFS_INODE_MUTEX_PARENT,
+	NTFS_INODE_MUTEX_PARENT2,
 };
 
 /*
@@ -1121,6 +1122,11 @@ static inline void ni_lock_dir(struct ntfs_inode *ni)
 	mutex_lock_nested(&ni->ni_lock, NTFS_INODE_MUTEX_PARENT);
 }
 
+static inline void ni_lock_dir2(struct ntfs_inode *ni)
+{
+	mutex_lock_nested(&ni->ni_lock, NTFS_INODE_MUTEX_PARENT2);
+}
+
 static inline void ni_unlock(struct ntfs_inode *ni)
 {
 	mutex_unlock(&ni->ni_lock);
-- 
GitLab


From 910013f7c7ba9fb82ce33536c58212907ca05969 Mon Sep 17 00:00:00 2001
From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
Date: Fri, 7 Oct 2022 20:20:14 +0300
Subject: [PATCH 067/875] fs/ntfs3: Restore correct state after ENOSPC in
 attr_data_get_block

Added new function ntfs_check_for_free_space.
Added undo mechanism in attr_data_get_block.
Fixes xfstest generic/083

Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/attrib.c  | 141 +++++++++++++++++++++++++++++----------------
 fs/ntfs3/fsntfs.c  |  33 +++++++++++
 fs/ntfs3/ntfs_fs.h |   1 +
 3 files changed, 125 insertions(+), 50 deletions(-)

diff --git a/fs/ntfs3/attrib.c b/fs/ntfs3/attrib.c
index 91ea73e6f4fe2..5e6bafb10f42d 100644
--- a/fs/ntfs3/attrib.c
+++ b/fs/ntfs3/attrib.c
@@ -891,8 +891,10 @@ int attr_data_get_block(struct ntfs_inode *ni, CLST vcn, CLST clen, CLST *lcn,
 	struct ATTR_LIST_ENTRY *le, *le_b;
 	struct mft_inode *mi, *mi_b;
 	CLST hint, svcn, to_alloc, evcn1, next_svcn, asize, end, vcn0, alen;
+	CLST alloc, evcn;
 	unsigned fr;
-	u64 total_size;
+	u64 total_size, total_size0;
+	int step = 0;
 
 	if (new)
 		*new = false;
@@ -932,7 +934,12 @@ int attr_data_get_block(struct ntfs_inode *ni, CLST vcn, CLST clen, CLST *lcn,
 
 	asize = le64_to_cpu(attr_b->nres.alloc_size) >> cluster_bits;
 	if (vcn >= asize) {
-		err = -EINVAL;
+		if (new) {
+			err = -EINVAL;
+		} else {
+			*len = 1;
+			*lcn = SPARSE_LCN;
+		}
 		goto out;
 	}
 
@@ -1036,10 +1043,12 @@ int attr_data_get_block(struct ntfs_inode *ni, CLST vcn, CLST clen, CLST *lcn,
 	if (err)
 		goto out;
 	*new = true;
+	step = 1;
 
 	end = vcn + alen;
-	total_size = le64_to_cpu(attr_b->nres.total_size) +
-		     ((u64)alen << cluster_bits);
+	/* Save 'total_size0' to restore if error. */
+	total_size0 = le64_to_cpu(attr_b->nres.total_size);
+	total_size = total_size0 + ((u64)alen << cluster_bits);
 
 	if (vcn != vcn0) {
 		if (!run_lookup_entry(run, vcn0, lcn, len, NULL)) {
@@ -1081,7 +1090,7 @@ repack:
 		if (!ni->attr_list.size) {
 			err = ni_create_attr_list(ni);
 			if (err)
-				goto out;
+				goto undo1;
 			/* Layout of records is changed. */
 			le_b = NULL;
 			attr_b = ni_find_attr(ni, NULL, &le_b, ATTR_DATA, NULL,
@@ -1098,67 +1107,83 @@ repack:
 		}
 	}
 
+	/* 
+	 * The code below may require additional cluster (to extend attribute list)
+	 * and / or one MFT record 
+	 * It is too complex to undo operations if -ENOSPC occurs deep inside 
+	 * in 'ni_insert_nonresident'.
+	 * Return in advance -ENOSPC here if there are no free cluster and no free MFT.
+	 */
+	if (!ntfs_check_for_free_space(sbi, 1, 1)) {
+		/* Undo step 1. */
+		err = -ENOSPC;
+		goto undo1;
+	}
+
+	step = 2;
 	svcn = evcn1;
 
 	/* Estimate next attribute. */
 	attr = ni_find_attr(ni, attr, &le, ATTR_DATA, NULL, 0, &svcn, &mi);
 
-	if (attr) {
-		CLST alloc = bytes_to_cluster(
-			sbi, le64_to_cpu(attr_b->nres.alloc_size));
-		CLST evcn = le64_to_cpu(attr->nres.evcn);
-
-		if (end < next_svcn)
-			end = next_svcn;
-		while (end > evcn) {
-			/* Remove segment [svcn : evcn). */
-			mi_remove_attr(NULL, mi, attr);
-
-			if (!al_remove_le(ni, le)) {
-				err = -EINVAL;
-				goto out;
-			}
+	if (!attr) {
+		/* Insert new attribute segment. */
+		goto ins_ext;
+	}
 
-			if (evcn + 1 >= alloc) {
-				/* Last attribute segment. */
-				evcn1 = evcn + 1;
-				goto ins_ext;
-			}
+	/* Try to update existed attribute segment. */
+	alloc = bytes_to_cluster(sbi, le64_to_cpu(attr_b->nres.alloc_size));
+	evcn = le64_to_cpu(attr->nres.evcn);
 
-			if (ni_load_mi(ni, le, &mi)) {
-				attr = NULL;
-				goto out;
-			}
+	if (end < next_svcn)
+		end = next_svcn;
+	while (end > evcn) {
+		/* Remove segment [svcn : evcn). */
+		mi_remove_attr(NULL, mi, attr);
 
-			attr = mi_find_attr(mi, NULL, ATTR_DATA, NULL, 0,
-					    &le->id);
-			if (!attr) {
-				err = -EINVAL;
-				goto out;
-			}
-			svcn = le64_to_cpu(attr->nres.svcn);
-			evcn = le64_to_cpu(attr->nres.evcn);
+		if (!al_remove_le(ni, le)) {
+			err = -EINVAL;
+			goto out;
 		}
 
-		if (end < svcn)
-			end = svcn;
+		if (evcn + 1 >= alloc) {
+			/* Last attribute segment. */
+			evcn1 = evcn + 1;
+			goto ins_ext;
+		}
 
-		err = attr_load_runs(attr, ni, run, &end);
-		if (err)
+		if (ni_load_mi(ni, le, &mi)) {
+			attr = NULL;
 			goto out;
+		}
 
-		evcn1 = evcn + 1;
-		attr->nres.svcn = cpu_to_le64(next_svcn);
-		err = mi_pack_runs(mi, attr, run, evcn1 - next_svcn);
-		if (err)
+		attr = mi_find_attr(mi, NULL, ATTR_DATA, NULL, 0, &le->id);
+		if (!attr) {
+			err = -EINVAL;
 			goto out;
+		}
+		svcn = le64_to_cpu(attr->nres.svcn);
+		evcn = le64_to_cpu(attr->nres.evcn);
+	}
 
-		le->vcn = cpu_to_le64(next_svcn);
-		ni->attr_list.dirty = true;
-		mi->dirty = true;
+	if (end < svcn)
+		end = svcn;
+
+	err = attr_load_runs(attr, ni, run, &end);
+	if (err)
+		goto out;
+
+	evcn1 = evcn + 1;
+	attr->nres.svcn = cpu_to_le64(next_svcn);
+	err = mi_pack_runs(mi, attr, run, evcn1 - next_svcn);
+	if (err)
+		goto out;
+
+	le->vcn = cpu_to_le64(next_svcn);
+	ni->attr_list.dirty = true;
+	mi->dirty = true;
+	next_svcn = le64_to_cpu(attr->nres.evcn) + 1;
 
-		next_svcn = le64_to_cpu(attr->nres.evcn) + 1;
-	}
 ins_ext:
 	if (evcn1 > next_svcn) {
 		err = ni_insert_nonresident(ni, ATTR_DATA, NULL, 0, run,
@@ -1170,10 +1195,26 @@ ins_ext:
 ok:
 	run_truncate_around(run, vcn);
 out:
+	if (err && step > 1) {
+		/* Too complex to restore. */
+		_ntfs_bad_inode(&ni->vfs_inode);
+	}
 	up_write(&ni->file.run_lock);
 	ni_unlock(ni);
 
 	return err;
+
+undo1:
+	/* Undo step1. */
+	attr_b->nres.total_size = cpu_to_le64(total_size0);
+	inode_set_bytes(&ni->vfs_inode, total_size0);
+
+	if (run_deallocate_ex(sbi, run, vcn, alen, NULL, false) ||
+	    !run_add_entry(run, vcn, SPARSE_LCN, alen, false) ||
+	    mi_pack_runs(mi, attr, run, max(end, evcn1) - svcn)) {
+		_ntfs_bad_inode(&ni->vfs_inode);
+	}
+	goto out;
 }
 
 int attr_data_read_resident(struct ntfs_inode *ni, struct page *page)
diff --git a/fs/ntfs3/fsntfs.c b/fs/ntfs3/fsntfs.c
index b68a7b7802629..4f04e8594a8fe 100644
--- a/fs/ntfs3/fsntfs.c
+++ b/fs/ntfs3/fsntfs.c
@@ -443,6 +443,39 @@ up_write:
 	return err;
 }
 
+/*
+ * ntfs_check_for_free_space
+ *
+ * Check if it is possible to allocate 'clen' clusters and 'mlen' Mft records
+ */
+bool ntfs_check_for_free_space(struct ntfs_sb_info *sbi, CLST clen, CLST mlen)
+{
+	size_t free, zlen, avail;
+	struct wnd_bitmap *wnd;
+
+	wnd = &sbi->used.bitmap;
+	down_read_nested(&wnd->rw_lock, BITMAP_MUTEX_CLUSTERS);
+	free = wnd_zeroes(wnd);
+	zlen = wnd_zone_len(wnd);
+	up_read(&wnd->rw_lock);
+
+	if (free < zlen + clen)
+		return false;
+
+	avail = free - (zlen + clen);
+
+	wnd = &sbi->mft.bitmap;
+	down_read_nested(&wnd->rw_lock, BITMAP_MUTEX_MFT);
+	free = wnd_zeroes(wnd);
+	zlen = wnd_zone_len(wnd);
+	up_read(&wnd->rw_lock);
+
+	if (free >= zlen + mlen)
+		return true;
+
+	return avail >= bytes_to_cluster(sbi, mlen << sbi->record_bits);
+}
+
 /*
  * ntfs_extend_mft - Allocate additional MFT records.
  *
diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h
index 776993ae498b2..bfb7493c52164 100644
--- a/fs/ntfs3/ntfs_fs.h
+++ b/fs/ntfs3/ntfs_fs.h
@@ -588,6 +588,7 @@ int ntfs_loadlog_and_replay(struct ntfs_inode *ni, struct ntfs_sb_info *sbi);
 int ntfs_look_for_free_space(struct ntfs_sb_info *sbi, CLST lcn, CLST len,
 			     CLST *new_lcn, CLST *new_len,
 			     enum ALLOCATE_OPT opt);
+bool ntfs_check_for_free_space(struct ntfs_sb_info *sbi, CLST clen, CLST mlen);
 int ntfs_look_free_mft(struct ntfs_sb_info *sbi, CLST *rno, bool mft,
 		       struct ntfs_inode *ni, struct mft_inode **mi);
 void ntfs_mark_rec_free(struct ntfs_sb_info *sbi, CLST rno, bool is_mft);
-- 
GitLab


From 6f80ed14d76c730f7943777ba259cd32870e6433 Mon Sep 17 00:00:00 2001
From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
Date: Fri, 7 Oct 2022 20:23:19 +0300
Subject: [PATCH 068/875] fs/ntfs3: Correct ntfs_check_for_free_space

zlen in some cases was bigger than correct value.

Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/fsntfs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/ntfs3/fsntfs.c b/fs/ntfs3/fsntfs.c
index 4f04e8594a8fe..6a1e000fd2b53 100644
--- a/fs/ntfs3/fsntfs.c
+++ b/fs/ntfs3/fsntfs.c
@@ -456,7 +456,7 @@ bool ntfs_check_for_free_space(struct ntfs_sb_info *sbi, CLST clen, CLST mlen)
 	wnd = &sbi->used.bitmap;
 	down_read_nested(&wnd->rw_lock, BITMAP_MUTEX_CLUSTERS);
 	free = wnd_zeroes(wnd);
-	zlen = wnd_zone_len(wnd);
+	zlen = min_t(size_t, NTFS_MIN_MFT_ZONE, wnd_zone_len(wnd));
 	up_read(&wnd->rw_lock);
 
 	if (free < zlen + clen)
-- 
GitLab


From 0e8235d28f3a0e9eda9f02ff67ee566d5f42b66b Mon Sep 17 00:00:00 2001
From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
Date: Mon, 10 Oct 2022 13:15:33 +0300
Subject: [PATCH 069/875] fs/ntfs3: Check fields while reading

Added new functions index_hdr_check and index_buf_check.
Now we check all stuff for correctness while reading from disk.
Also fixed bug with stale nfs data.

Reported-by: van fantasy <g1042620637@gmail.com>
Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/index.c   |  84 ++++++++++++++++++++++++++++++----
 fs/ntfs3/inode.c   |  18 ++++----
 fs/ntfs3/ntfs_fs.h |   4 +-
 fs/ntfs3/run.c     |   7 ++-
 fs/ntfs3/xattr.c   | 109 +++++++++++++++++++++++++++++----------------
 5 files changed, 164 insertions(+), 58 deletions(-)

diff --git a/fs/ntfs3/index.c b/fs/ntfs3/index.c
index 35369ae5c438c..51ab759546403 100644
--- a/fs/ntfs3/index.c
+++ b/fs/ntfs3/index.c
@@ -605,11 +605,58 @@ static const struct NTFS_DE *hdr_insert_head(struct INDEX_HDR *hdr,
 	return e;
 }
 
+/*
+ * index_hdr_check
+ *
+ * return true if INDEX_HDR is valid
+ */
+static bool index_hdr_check(const struct INDEX_HDR *hdr, u32 bytes)
+{
+	u32 end = le32_to_cpu(hdr->used);
+	u32 tot = le32_to_cpu(hdr->total);
+	u32 off = le32_to_cpu(hdr->de_off);
+
+	if (!IS_ALIGNED(off, 8) || tot > bytes || end > tot ||
+	    off + sizeof(struct NTFS_DE) > end) {
+		/* incorrect index buffer. */
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * index_buf_check
+ *
+ * return true if INDEX_BUFFER seems is valid
+ */
+static bool index_buf_check(const struct INDEX_BUFFER *ib, u32 bytes,
+			    const CLST *vbn)
+{
+	const struct NTFS_RECORD_HEADER *rhdr = &ib->rhdr;
+	u16 fo = le16_to_cpu(rhdr->fix_off);
+	u16 fn = le16_to_cpu(rhdr->fix_num);
+
+	if (bytes <= offsetof(struct INDEX_BUFFER, ihdr) ||
+	    rhdr->sign != NTFS_INDX_SIGNATURE ||
+	    fo < sizeof(struct INDEX_BUFFER)
+	    /* Check index buffer vbn. */
+	    || (vbn && *vbn != le64_to_cpu(ib->vbn)) || (fo % sizeof(short)) ||
+	    fo + fn * sizeof(short) >= bytes ||
+	    fn != ((bytes >> SECTOR_SHIFT) + 1)) {
+		/* incorrect index buffer. */
+		return false;
+	}
+
+	return index_hdr_check(&ib->ihdr,
+			       bytes - offsetof(struct INDEX_BUFFER, ihdr));
+}
+
 void fnd_clear(struct ntfs_fnd *fnd)
 {
 	int i;
 
-	for (i = 0; i < fnd->level; i++) {
+	for (i = fnd->level - 1; i >= 0; i--) {
 		struct indx_node *n = fnd->nodes[i];
 
 		if (!n)
@@ -819,9 +866,16 @@ int indx_init(struct ntfs_index *indx, struct ntfs_sb_info *sbi,
 	u32 t32;
 	const struct INDEX_ROOT *root = resident_data(attr);
 
+	t32 = le32_to_cpu(attr->res.data_size);
+	if (t32 <= offsetof(struct INDEX_ROOT, ihdr) ||
+	    !index_hdr_check(&root->ihdr,
+			     t32 - offsetof(struct INDEX_ROOT, ihdr))) {
+		goto out;
+	}
+
 	/* Check root fields. */
 	if (!root->index_block_clst)
-		return -EINVAL;
+		goto out;
 
 	indx->type = type;
 	indx->idx2vbn_bits = __ffs(root->index_block_clst);
@@ -833,19 +887,19 @@ int indx_init(struct ntfs_index *indx, struct ntfs_sb_info *sbi,
 	if (t32 < sbi->cluster_size) {
 		/* Index record is smaller than a cluster, use 512 blocks. */
 		if (t32 != root->index_block_clst * SECTOR_SIZE)
-			return -EINVAL;
+			goto out;
 
 		/* Check alignment to a cluster. */
 		if ((sbi->cluster_size >> SECTOR_SHIFT) &
 		    (root->index_block_clst - 1)) {
-			return -EINVAL;
+			goto out;
 		}
 
 		indx->vbn2vbo_bits = SECTOR_SHIFT;
 	} else {
 		/* Index record must be a multiple of cluster size. */
 		if (t32 != root->index_block_clst << sbi->cluster_bits)
-			return -EINVAL;
+			goto out;
 
 		indx->vbn2vbo_bits = sbi->cluster_bits;
 	}
@@ -853,7 +907,14 @@ int indx_init(struct ntfs_index *indx, struct ntfs_sb_info *sbi,
 	init_rwsem(&indx->run_lock);
 
 	indx->cmp = get_cmp_func(root);
-	return indx->cmp ? 0 : -EINVAL;
+	if (!indx->cmp)
+		goto out;
+
+	return 0;
+
+out:
+	ntfs_set_state(sbi, NTFS_DIRTY_DIRTY);
+	return -EINVAL;
 }
 
 static struct indx_node *indx_new(struct ntfs_index *indx,
@@ -1011,6 +1072,13 @@ int indx_read(struct ntfs_index *indx, struct ntfs_inode *ni, CLST vbn,
 		goto out;
 
 ok:
+	if (!index_buf_check(ib, bytes, &vbn)) {
+		ntfs_inode_err(&ni->vfs_inode, "directory corrupted");
+		ntfs_set_state(ni->mi.sbi, NTFS_DIRTY_ERROR);
+		err = -EINVAL;
+		goto out;
+	}
+
 	if (err == -E_NTFS_FIXUP) {
 		ntfs_write_bh(ni->mi.sbi, &ib->rhdr, &in->nb, 0);
 		err = 0;
@@ -1601,9 +1669,9 @@ static int indx_insert_into_root(struct ntfs_index *indx, struct ntfs_inode *ni,
 
 	if (err) {
 		/* Restore root. */
-		if (mi_resize_attr(mi, attr, -ds_root))
+		if (mi_resize_attr(mi, attr, -ds_root)) {
 			memcpy(attr, a_root, asize);
-		else {
+		} else {
 			/* Bug? */
 			ntfs_set_state(sbi, NTFS_DIRTY_ERROR);
 		}
diff --git a/fs/ntfs3/inode.c b/fs/ntfs3/inode.c
index 1afe6246aa935..31bc94f879409 100644
--- a/fs/ntfs3/inode.c
+++ b/fs/ntfs3/inode.c
@@ -81,7 +81,7 @@ static struct inode *ntfs_read_mft(struct inode *inode,
 			 le16_to_cpu(ref->seq), le16_to_cpu(rec->seq));
 		goto out;
 	} else if (!is_rec_inuse(rec)) {
-		err = -EINVAL;
+		err = -ESTALE;
 		ntfs_err(sb, "Inode r=%x is not in use!", (u32)ino);
 		goto out;
 	}
@@ -92,8 +92,10 @@ static struct inode *ntfs_read_mft(struct inode *inode,
 		goto out;
 	}
 
-	if (!is_rec_base(rec))
-		goto Ok;
+	if (!is_rec_base(rec)) {
+		err = -EINVAL;
+		goto out;
+	}
 
 	/* Record should contain $I30 root. */
 	is_dir = rec->flags & RECORD_FLAG_DIR;
@@ -466,7 +468,6 @@ end_enum:
 		inode->i_flags |= S_NOSEC;
 	}
 
-Ok:
 	if (ino == MFT_REC_MFT && !sb->s_root)
 		sbi->mft.ni = NULL;
 
@@ -520,6 +521,9 @@ struct inode *ntfs_iget5(struct super_block *sb, const struct MFT_REF *ref,
 		_ntfs_bad_inode(inode);
 	}
 
+	if (IS_ERR(inode) && name)
+		ntfs_set_state(sb->s_fs_info, NTFS_DIRTY_ERROR);
+
 	return inode;
 }
 
@@ -1660,10 +1664,8 @@ out6:
 		ntfs_remove_reparse(sbi, IO_REPARSE_TAG_SYMLINK, &new_de->ref);
 
 out5:
-	if (S_ISDIR(mode) || run_is_empty(&ni->file.run))
-		goto out4;
-
-	run_deallocate(sbi, &ni->file.run, false);
+	if (!S_ISDIR(mode))
+		run_deallocate(sbi, &ni->file.run, false);
 
 out4:
 	clear_rec_inuse(rec);
diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h
index bfb7493c52164..8dd835626c7e9 100644
--- a/fs/ntfs3/ntfs_fs.h
+++ b/fs/ntfs3/ntfs_fs.h
@@ -797,12 +797,12 @@ int run_pack(const struct runs_tree *run, CLST svcn, CLST len, u8 *run_buf,
 	     u32 run_buf_size, CLST *packed_vcns);
 int run_unpack(struct runs_tree *run, struct ntfs_sb_info *sbi, CLST ino,
 	       CLST svcn, CLST evcn, CLST vcn, const u8 *run_buf,
-	       u32 run_buf_size);
+	       int run_buf_size);
 
 #ifdef NTFS3_CHECK_FREE_CLST
 int run_unpack_ex(struct runs_tree *run, struct ntfs_sb_info *sbi, CLST ino,
 		  CLST svcn, CLST evcn, CLST vcn, const u8 *run_buf,
-		  u32 run_buf_size);
+		  int run_buf_size);
 #else
 #define run_unpack_ex run_unpack
 #endif
diff --git a/fs/ntfs3/run.c b/fs/ntfs3/run.c
index aaaa0d3d35a24..12d8682f33b53 100644
--- a/fs/ntfs3/run.c
+++ b/fs/ntfs3/run.c
@@ -919,12 +919,15 @@ out:
  */
 int run_unpack(struct runs_tree *run, struct ntfs_sb_info *sbi, CLST ino,
 	       CLST svcn, CLST evcn, CLST vcn, const u8 *run_buf,
-	       u32 run_buf_size)
+	       int run_buf_size)
 {
 	u64 prev_lcn, vcn64, lcn, next_vcn;
 	const u8 *run_last, *run_0;
 	bool is_mft = ino == MFT_REC_MFT;
 
+	if (run_buf_size < 0)
+		return -EINVAL;
+
 	/* Check for empty. */
 	if (evcn + 1 == svcn)
 		return 0;
@@ -1046,7 +1049,7 @@ int run_unpack(struct runs_tree *run, struct ntfs_sb_info *sbi, CLST ino,
  */
 int run_unpack_ex(struct runs_tree *run, struct ntfs_sb_info *sbi, CLST ino,
 		  CLST svcn, CLST evcn, CLST vcn, const u8 *run_buf,
-		  u32 run_buf_size)
+		  int run_buf_size)
 {
 	int ret, err;
 	CLST next_vcn, lcn, len;
diff --git a/fs/ntfs3/xattr.c b/fs/ntfs3/xattr.c
index 8620a7b4b3e63..dd33071175134 100644
--- a/fs/ntfs3/xattr.c
+++ b/fs/ntfs3/xattr.c
@@ -43,28 +43,26 @@ static inline size_t packed_ea_size(const struct EA_FULL *ea)
  * Assume there is at least one xattr in the list.
  */
 static inline bool find_ea(const struct EA_FULL *ea_all, u32 bytes,
-			   const char *name, u8 name_len, u32 *off)
+			   const char *name, u8 name_len, u32 *off, u32 *ea_sz)
 {
-	*off = 0;
+	u32 ea_size;
 
-	if (!ea_all || !bytes)
+	*off = 0;
+	if (!ea_all)
 		return false;
 
-	for (;;) {
+	for (; *off < bytes; *off += ea_size) {
 		const struct EA_FULL *ea = Add2Ptr(ea_all, *off);
-		u32 next_off = *off + unpacked_ea_size(ea);
-
-		if (next_off > bytes)
-			return false;
-
+		ea_size = unpacked_ea_size(ea);
 		if (ea->name_len == name_len &&
-		    !memcmp(ea->name, name, name_len))
+		    !memcmp(ea->name, name, name_len)) {
+			if (ea_sz)
+				*ea_sz = ea_size;
 			return true;
-
-		*off = next_off;
-		if (next_off >= bytes)
-			return false;
+		}
 	}
+
+	return false;
 }
 
 /*
@@ -75,12 +73,12 @@ static inline bool find_ea(const struct EA_FULL *ea_all, u32 bytes,
 static int ntfs_read_ea(struct ntfs_inode *ni, struct EA_FULL **ea,
 			size_t add_bytes, const struct EA_INFO **info)
 {
-	int err;
+	int err = -EINVAL;
 	struct ntfs_sb_info *sbi = ni->mi.sbi;
 	struct ATTR_LIST_ENTRY *le = NULL;
 	struct ATTRIB *attr_info, *attr_ea;
 	void *ea_p;
-	u32 size;
+	u32 size, off, ea_size;
 
 	static_assert(le32_to_cpu(ATTR_EA_INFO) < le32_to_cpu(ATTR_EA));
 
@@ -97,24 +95,31 @@ static int ntfs_read_ea(struct ntfs_inode *ni, struct EA_FULL **ea,
 
 	*info = resident_data_ex(attr_info, sizeof(struct EA_INFO));
 	if (!*info)
-		return -EINVAL;
+		goto out;
 
 	/* Check Ea limit. */
 	size = le32_to_cpu((*info)->size);
-	if (size > sbi->ea_max_size)
-		return -EFBIG;
+	if (size > sbi->ea_max_size) {
+		err = -EFBIG;
+		goto out;
+	}
+
+	if (attr_size(attr_ea) > sbi->ea_max_size) {
+		err = -EFBIG;
+		goto out;
+	}
 
-	if (attr_size(attr_ea) > sbi->ea_max_size)
-		return -EFBIG;
+	if (!size) {
+		/* EA info persists, but xattr is empty. Looks like EA problem. */
+		goto out;
+	}
 
 	/* Allocate memory for packed Ea. */
 	ea_p = kmalloc(size_add(size, add_bytes), GFP_NOFS);
 	if (!ea_p)
 		return -ENOMEM;
 
-	if (!size) {
-		/* EA info persists, but xattr is empty. Looks like EA problem. */
-	} else if (attr_ea->non_res) {
+	if (attr_ea->non_res) {
 		struct runs_tree run;
 
 		run_init(&run);
@@ -125,24 +130,52 @@ static int ntfs_read_ea(struct ntfs_inode *ni, struct EA_FULL **ea,
 		run_close(&run);
 
 		if (err)
-			goto out;
+			goto out1;
 	} else {
 		void *p = resident_data_ex(attr_ea, size);
 
-		if (!p) {
-			err = -EINVAL;
-			goto out;
-		}
+		if (!p)
+			goto out1;
 		memcpy(ea_p, p, size);
 	}
 
 	memset(Add2Ptr(ea_p, size), 0, add_bytes);
+
+	/* Check all attributes for consistency. */
+	for (off = 0; off < size; off += ea_size) {
+		const struct EA_FULL *ef = Add2Ptr(ea_p, off);
+		u32 bytes = size - off;
+
+		/* Check if we can use field ea->size. */
+		if (bytes < sizeof(ef->size))
+			goto out1;
+
+		if (ef->size) {
+			ea_size = le32_to_cpu(ef->size);
+			if (ea_size > bytes)
+				goto out1;
+			continue;
+		}
+
+		/* Check if we can use fields ef->name_len and ef->elength. */
+		if (bytes < offsetof(struct EA_FULL, name))
+			goto out1;
+
+		ea_size = ALIGN(struct_size(ef, name,
+					    1 + ef->name_len +
+						    le16_to_cpu(ef->elength)),
+				4);
+		if (ea_size > bytes)
+			goto out1;
+	}
+
 	*ea = ea_p;
 	return 0;
 
-out:
+out1:
 	kfree(ea_p);
-	*ea = NULL;
+out:
+	ntfs_set_state(sbi, NTFS_DIRTY_DIRTY);
 	return err;
 }
 
@@ -164,6 +197,7 @@ static ssize_t ntfs_list_ea(struct ntfs_inode *ni, char *buffer,
 	const struct EA_FULL *ea;
 	u32 off, size;
 	int err;
+	int ea_size;
 	size_t ret;
 
 	err = ntfs_read_ea(ni, &ea_all, 0, &info);
@@ -176,8 +210,9 @@ static ssize_t ntfs_list_ea(struct ntfs_inode *ni, char *buffer,
 	size = le32_to_cpu(info->size);
 
 	/* Enumerate all xattrs. */
-	for (ret = 0, off = 0; off < size; off += unpacked_ea_size(ea)) {
+	for (ret = 0, off = 0; off < size; off += ea_size) {
 		ea = Add2Ptr(ea_all, off);
+		ea_size = unpacked_ea_size(ea);
 
 		if (buffer) {
 			if (ret + ea->name_len + 1 > bytes_per_buffer) {
@@ -228,7 +263,8 @@ static int ntfs_get_ea(struct inode *inode, const char *name, size_t name_len,
 		goto out;
 
 	/* Enumerate all xattrs. */
-	if (!find_ea(ea_all, le32_to_cpu(info->size), name, name_len, &off)) {
+	if (!find_ea(ea_all, le32_to_cpu(info->size), name, name_len, &off,
+		     NULL)) {
 		err = -ENODATA;
 		goto out;
 	}
@@ -270,7 +306,7 @@ static noinline int ntfs_set_ea(struct inode *inode, const char *name,
 	struct EA_FULL *new_ea;
 	struct EA_FULL *ea_all = NULL;
 	size_t add, new_pack;
-	u32 off, size;
+	u32 off, size, ea_sz;
 	__le16 size_pack;
 	struct ATTRIB *attr;
 	struct ATTR_LIST_ENTRY *le;
@@ -305,9 +341,8 @@ static noinline int ntfs_set_ea(struct inode *inode, const char *name,
 		size_pack = ea_info.size_pack;
 	}
 
-	if (info && find_ea(ea_all, size, name, name_len, &off)) {
+	if (info && find_ea(ea_all, size, name, name_len, &off, &ea_sz)) {
 		struct EA_FULL *ea;
-		size_t ea_sz;
 
 		if (flags & XATTR_CREATE) {
 			err = -EEXIST;
@@ -330,8 +365,6 @@ static noinline int ntfs_set_ea(struct inode *inode, const char *name,
 		if (ea->flags & FILE_NEED_EA)
 			le16_add_cpu(&ea_info.count, -1);
 
-		ea_sz = unpacked_ea_size(ea);
-
 		le16_add_cpu(&ea_info.size_pack, 0 - packed_ea_size(ea));
 
 		memmove(ea, Add2Ptr(ea, ea_sz), size - off - ea_sz);
-- 
GitLab


From e31195a3ac71e7e50793163f933695231cb16513 Mon Sep 17 00:00:00 2001
From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
Date: Tue, 11 Oct 2022 20:00:36 +0300
Subject: [PATCH 070/875] fs/ntfs3: Fix incorrect if in ntfs_set_acl_ex

We need to update ctime too with mode.
Fixes xfstest generic/307

Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/xattr.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/fs/ntfs3/xattr.c b/fs/ntfs3/xattr.c
index dd33071175134..cfd59bb0f9de1 100644
--- a/fs/ntfs3/xattr.c
+++ b/fs/ntfs3/xattr.c
@@ -638,10 +638,9 @@ static noinline int ntfs_set_acl_ex(struct user_namespace *mnt_userns,
 		err = 0; /* Removing non existed xattr. */
 	if (!err) {
 		set_cached_acl(inode, type, acl);
-		if (inode->i_mode != mode) {
-			inode->i_mode = mode;
-			mark_inode_dirty(inode);
-		}
+		inode->i_mode = mode;
+		inode->i_ctime = current_time(inode);
+		mark_inode_dirty(inode);
 	}
 
 out:
-- 
GitLab


From 97a6815e50619377704e6566fb2b77c1aa4e2647 Mon Sep 17 00:00:00 2001
From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
Date: Tue, 11 Oct 2022 20:12:02 +0300
Subject: [PATCH 071/875] fs/ntfs3: Use ALIGN kernel macro

This way code will be more readable.

Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/fsntfs.c  | 2 +-
 fs/ntfs3/ntfs.h    | 1 -
 fs/ntfs3/ntfs_fs.h | 2 ++
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/fs/ntfs3/fsntfs.c b/fs/ntfs3/fsntfs.c
index 6a1e000fd2b53..567563771bf89 100644
--- a/fs/ntfs3/fsntfs.c
+++ b/fs/ntfs3/fsntfs.c
@@ -503,7 +503,7 @@ static int ntfs_extend_mft(struct ntfs_sb_info *sbi)
 	struct ATTRIB *attr;
 	struct wnd_bitmap *wnd = &sbi->mft.bitmap;
 
-	new_mft_total = (wnd->nbits + MFT_INCREASE_CHUNK + 127) & (CLST)~127;
+	new_mft_total = ALIGN(wnd->nbits + NTFS_MFT_INCREASE_STEP, 128);
 	new_mft_bytes = (u64)new_mft_total << sbi->record_bits;
 
 	/* Step 1: Resize $MFT::DATA. */
diff --git a/fs/ntfs3/ntfs.h b/fs/ntfs3/ntfs.h
index 9cc396b117bfd..9f764bf4ed0a0 100644
--- a/fs/ntfs3/ntfs.h
+++ b/fs/ntfs3/ntfs.h
@@ -84,7 +84,6 @@ typedef u32 CLST;
 
 #define COMPRESSION_UNIT     4
 #define COMPRESS_MAX_CLUSTER 0x1000
-#define MFT_INCREASE_CHUNK   1024
 
 enum RECORD_NUM {
 	MFT_REC_MFT		= 0,
diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h
index 8dd835626c7e9..1ab8bbaf8eaa8 100644
--- a/fs/ntfs3/ntfs_fs.h
+++ b/fs/ntfs3/ntfs_fs.h
@@ -199,6 +199,8 @@ struct ntfs_index {
 
 /* Minimum MFT zone. */
 #define NTFS_MIN_MFT_ZONE 100
+/* Step to increase the MFT. */
+#define NTFS_MFT_INCREASE_STEP 1024
 
 /* Ntfs file system in-core superblock data. */
 struct ntfs_sb_info {
-- 
GitLab


From 60ce8dfde03558bfc290cd915c60fa243ba2ae84 Mon Sep 17 00:00:00 2001
From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
Date: Tue, 11 Oct 2022 20:15:28 +0300
Subject: [PATCH 072/875] fs/ntfs3: Fix wrong if in hdr_first_de

We need to check used bytes instead of total.

Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/ntfs.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/fs/ntfs3/ntfs.h b/fs/ntfs3/ntfs.h
index 9f764bf4ed0a0..86ea1826d0998 100644
--- a/fs/ntfs3/ntfs.h
+++ b/fs/ntfs3/ntfs.h
@@ -714,12 +714,13 @@ static inline struct NTFS_DE *hdr_first_de(const struct INDEX_HDR *hdr)
 {
 	u32 de_off = le32_to_cpu(hdr->de_off);
 	u32 used = le32_to_cpu(hdr->used);
-	struct NTFS_DE *e = Add2Ptr(hdr, de_off);
+	struct NTFS_DE *e;
 	u16 esize;
 
-	if (de_off >= used || de_off >= le32_to_cpu(hdr->total))
+	if (de_off >= used || de_off + sizeof(struct NTFS_DE) > used )
 		return NULL;
 
+	e = Add2Ptr(hdr, de_off);
 	esize = le16_to_cpu(e->size);
 	if (esize < sizeof(struct NTFS_DE) || de_off + esize > used)
 		return NULL;
-- 
GitLab


From ec5fc72013762500867c9cef96fed89dc7161832 Mon Sep 17 00:00:00 2001
From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
Date: Tue, 11 Oct 2022 20:19:36 +0300
Subject: [PATCH 073/875] fs/ntfs3: Improve checking of bad clusters

Added new function wnd_set_used_safe.
Load $BadClus before $AttrDef instead of before $Bitmap.

Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/bitmap.c  | 38 +++++++++++++++++++++++++++
 fs/ntfs3/ntfs_fs.h |  2 ++
 fs/ntfs3/run.c     | 21 ++-------------
 fs/ntfs3/super.c   | 64 ++++++++++++++++++++++++++++------------------
 4 files changed, 81 insertions(+), 44 deletions(-)

diff --git a/fs/ntfs3/bitmap.c b/fs/ntfs3/bitmap.c
index a51805a3d91fa..723fb64e65316 100644
--- a/fs/ntfs3/bitmap.c
+++ b/fs/ntfs3/bitmap.c
@@ -800,6 +800,44 @@ int wnd_set_used(struct wnd_bitmap *wnd, size_t bit, size_t bits)
 	return err;
 }
 
+/*
+ * wnd_set_used_safe - Mark the bits range from bit to bit + bits as used.
+ *
+ * Unlikely wnd_set_used/wnd_set_free this function is not full trusted.
+ * It scans every bit in bitmap and marks free bit as used.
+ * @done - how many bits were marked as used.
+ *
+ * NOTE: normally *done should be 0.
+ */
+int wnd_set_used_safe(struct wnd_bitmap *wnd, size_t bit, size_t bits,
+		      size_t *done)
+{
+	size_t i, from = 0, len = 0;
+	int err = 0;
+
+	*done = 0;
+	for (i = 0; i < bits; i++) {
+		if (wnd_is_free(wnd, bit + i, 1)) {
+			if (!len)
+				from = bit + i;
+			len += 1;
+		} else if (len) {
+			err = wnd_set_used(wnd, from, len);
+			*done += len;
+			len = 0;
+			if (err)
+				break;
+		}
+	}
+
+	if (len) {
+		/* last fragment. */
+		err = wnd_set_used(wnd, from, len);
+		*done += len;
+	}
+	return err;
+}
+
 /*
  * wnd_is_free_hlp
  *
diff --git a/fs/ntfs3/ntfs_fs.h b/fs/ntfs3/ntfs_fs.h
index 1ab8bbaf8eaa8..5cefcfa521187 100644
--- a/fs/ntfs3/ntfs_fs.h
+++ b/fs/ntfs3/ntfs_fs.h
@@ -828,6 +828,8 @@ static inline size_t wnd_zeroes(const struct wnd_bitmap *wnd)
 int wnd_init(struct wnd_bitmap *wnd, struct super_block *sb, size_t nbits);
 int wnd_set_free(struct wnd_bitmap *wnd, size_t bit, size_t bits);
 int wnd_set_used(struct wnd_bitmap *wnd, size_t bit, size_t bits);
+int wnd_set_used_safe(struct wnd_bitmap *wnd, size_t bit, size_t bits,
+		      size_t *done);
 bool wnd_is_free(struct wnd_bitmap *wnd, size_t bit, size_t bits);
 bool wnd_is_used(struct wnd_bitmap *wnd, size_t bit, size_t bits);
 
diff --git a/fs/ntfs3/run.c b/fs/ntfs3/run.c
index 12d8682f33b53..a5af71cd8d14b 100644
--- a/fs/ntfs3/run.c
+++ b/fs/ntfs3/run.c
@@ -1096,25 +1096,8 @@ int run_unpack_ex(struct runs_tree *run, struct ntfs_sb_info *sbi, CLST ino,
 
 		if (down_write_trylock(&wnd->rw_lock)) {
 			/* Mark all zero bits as used in range [lcn, lcn+len). */
-			CLST i, lcn_f = 0, len_f = 0;
-
-			err = 0;
-			for (i = 0; i < len; i++) {
-				if (wnd_is_free(wnd, lcn + i, 1)) {
-					if (!len_f)
-						lcn_f = lcn + i;
-					len_f += 1;
-				} else if (len_f) {
-					err = wnd_set_used(wnd, lcn_f, len_f);
-					len_f = 0;
-					if (err)
-						break;
-				}
-			}
-
-			if (len_f)
-				err = wnd_set_used(wnd, lcn_f, len_f);
-
+			size_t done;
+			err = wnd_set_used_safe(wnd, lcn, len, &done);
 			up_write(&wnd->rw_lock);
 			if (err)
 				return err;
diff --git a/fs/ntfs3/super.c b/fs/ntfs3/super.c
index 59a831bd0c9b4..ef4ea3f21905f 100644
--- a/fs/ntfs3/super.c
+++ b/fs/ntfs3/super.c
@@ -930,7 +930,7 @@ static int ntfs_fill_super(struct super_block *sb, struct fs_context *fc)
 	struct block_device *bdev = sb->s_bdev;
 	struct inode *inode;
 	struct ntfs_inode *ni;
-	size_t i, tt;
+	size_t i, tt, bad_len, bad_frags;
 	CLST vcn, lcn, len;
 	struct ATTRIB *attr;
 	const struct VOLUME_INFO *info;
@@ -1100,30 +1100,6 @@ static int ntfs_fill_super(struct super_block *sb, struct fs_context *fc)
 
 	sbi->mft.ni = ni;
 
-	/* Load $BadClus. */
-	ref.low = cpu_to_le32(MFT_REC_BADCLUST);
-	ref.seq = cpu_to_le16(MFT_REC_BADCLUST);
-	inode = ntfs_iget5(sb, &ref, &NAME_BADCLUS);
-	if (IS_ERR(inode)) {
-		ntfs_err(sb, "Failed to load $BadClus.");
-		err = PTR_ERR(inode);
-		goto out;
-	}
-
-	ni = ntfs_i(inode);
-
-	for (i = 0; run_get_entry(&ni->file.run, i, &vcn, &lcn, &len); i++) {
-		if (lcn == SPARSE_LCN)
-			continue;
-
-		if (!sbi->bad_clusters)
-			ntfs_notice(sb, "Volume contains bad blocks");
-
-		sbi->bad_clusters += len;
-	}
-
-	iput(inode);
-
 	/* Load $Bitmap. */
 	ref.low = cpu_to_le32(MFT_REC_BITMAP);
 	ref.seq = cpu_to_le16(MFT_REC_BITMAP);
@@ -1161,6 +1137,44 @@ static int ntfs_fill_super(struct super_block *sb, struct fs_context *fc)
 	if (err)
 		goto out;
 
+	/* Load $BadClus. */
+	ref.low = cpu_to_le32(MFT_REC_BADCLUST);
+	ref.seq = cpu_to_le16(MFT_REC_BADCLUST);
+	inode = ntfs_iget5(sb, &ref, &NAME_BADCLUS);
+	if (IS_ERR(inode)) {
+		err = PTR_ERR(inode);
+		ntfs_err(sb, "Failed to load $BadClus (%d).", err);
+		goto out;
+	}
+
+	ni = ntfs_i(inode);
+	bad_len = bad_frags = 0;
+	for (i = 0; run_get_entry(&ni->file.run, i, &vcn, &lcn, &len); i++) {
+		if (lcn == SPARSE_LCN)
+			continue;
+
+		bad_len += len;
+		bad_frags += 1;
+		if (sb_rdonly(sb))
+			continue;
+
+		if (wnd_set_used_safe(&sbi->used.bitmap, lcn, len, &tt) || tt) {
+			/* Bad blocks marked as free in bitmap. */
+			ntfs_set_state(sbi, NTFS_DIRTY_ERROR);
+		}
+	}
+	if (bad_len) {
+		/*
+		 * Notice about bad blocks.
+		 * In normal cases these blocks are marked as used in bitmap.
+		 * And we never allocate space in it.
+		 */
+		ntfs_notice(sb,
+			    "Volume contains %zu bad blocks in %zu fragments.",
+			    bad_len, bad_frags);
+	}
+	iput(inode);
+
 	/* Load $AttrDef. */
 	ref.low = cpu_to_le32(MFT_REC_ATTR);
 	ref.seq = cpu_to_le16(MFT_REC_ATTR);
-- 
GitLab


From 36963cf225f890f97fd84af0a82d323043edd0f1 Mon Sep 17 00:00:00 2001
From: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
Date: Tue, 11 Oct 2022 20:21:03 +0300
Subject: [PATCH 074/875] fs/ntfs3: Make if more readable

This way it looks better.

Signed-off-by: Konstantin Komarov <almaz.alexandrovich@paragon-software.com>
---
 fs/ntfs3/record.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/fs/ntfs3/record.c b/fs/ntfs3/record.c
index a952cd7aa7a4b..defce6a5c8e1b 100644
--- a/fs/ntfs3/record.c
+++ b/fs/ntfs3/record.c
@@ -265,10 +265,9 @@ struct ATTRIB *mi_enum_attr(struct mft_inode *mi, struct ATTRIB *attr)
 		if (t16 + t32 > asize)
 			return NULL;
 
-		if (attr->name_len &&
-		    le16_to_cpu(attr->name_off) + sizeof(short) * attr->name_len > t16) {
+		t32 = sizeof(short) * attr->name_len;
+		if (t32 && le16_to_cpu(attr->name_off) + t32 > t16)
 			return NULL;
-		}
 
 		return attr;
 	}
-- 
GitLab


From ee18f2715e85f4ef051851a0c4831ee7ad7d83b3 Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Wed, 2 Nov 2022 19:14:10 +0800
Subject: [PATCH 075/875] remoteproc: imx_rproc: Correct i.MX93 DRAM mapping

According to updated reference mannual, the M33 DRAM view of
0x[C,D]0000000 maps to A55 0xC0000000, so correct it.

Fixes: 9222fabf0e39 ("remoteproc: imx_rproc: Support i.MX93")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: stable <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20221102111410.38737-1-peng.fan@oss.nxp.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/remoteproc/imx_rproc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/remoteproc/imx_rproc.c b/drivers/remoteproc/imx_rproc.c
index 2c471e46f4ca8..9fc978e0393ce 100644
--- a/drivers/remoteproc/imx_rproc.c
+++ b/drivers/remoteproc/imx_rproc.c
@@ -134,8 +134,8 @@ static const struct imx_rproc_att imx_rproc_att_imx93[] = {
 	{ 0x80000000, 0x80000000, 0x10000000, 0 },
 	{ 0x90000000, 0x80000000, 0x10000000, 0 },
 
-	{ 0xC0000000, 0xa0000000, 0x10000000, 0 },
-	{ 0xD0000000, 0xa0000000, 0x10000000, 0 },
+	{ 0xC0000000, 0xC0000000, 0x10000000, 0 },
+	{ 0xD0000000, 0xC0000000, 0x10000000, 0 },
 };
 
 static const struct imx_rproc_att imx_rproc_att_imx8qm[] = {
-- 
GitLab


From e63ae3f836e66bf956072a0d6dd09fbe2d45bf7a Mon Sep 17 00:00:00 2001
From: ye xingchen <ye.xingchen@zte.com.cn>
Date: Thu, 17 Nov 2022 15:41:06 +0800
Subject: [PATCH 076/875] remoteproc: core: Use device_match_of_node()

Replace the open-code with device_match_of_node().

Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
Link: https://lore.kernel.org/r/202211171541061366938@zte.com.cn
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/remoteproc/remoteproc_core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
index cb1d414a23896..11c165ddf1fca 100644
--- a/drivers/remoteproc/remoteproc_core.c
+++ b/drivers/remoteproc/remoteproc_core.c
@@ -2112,7 +2112,7 @@ struct rproc *rproc_get_by_phandle(phandle phandle)
 
 	rcu_read_lock();
 	list_for_each_entry_rcu(r, &rproc_list, node) {
-		if (r->dev.parent && r->dev.parent->of_node == np) {
+		if (r->dev.parent && device_match_of_node(r->dev.parent, np)) {
 			/* prevent underlying implementation from being removed */
 			if (!try_module_get(r->dev.parent->driver->owner)) {
 				dev_err(&r->dev, "can't get owner\n");
-- 
GitLab


From 5719efcc5abb34ceb47b03e58709d99713f80db1 Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Mon, 21 Nov 2022 17:13:02 +0100
Subject: [PATCH 077/875] dt-bindings: pwm: renesas,pwm-rcar: Add r8a779g0
 support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Document support for the PWM timers in the Renesas R-Car V4H (R8A779G0)
SoC.

Based on a patch in the BSP by CongDang.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml
index 1c94acbc2b4a0..4c80970106877 100644
--- a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml
+++ b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml
@@ -35,6 +35,7 @@ properties:
           - renesas,pwm-r8a77980  # R-Car V3H
           - renesas,pwm-r8a77990  # R-Car E3
           - renesas,pwm-r8a77995  # R-Car D3
+          - renesas,pwm-r8a779g0  # R-Car V4H
       - const: renesas,pwm-rcar
 
   reg:
-- 
GitLab


From 50315945d178eebec4e8e2c50c265767ddb926eb Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Mon, 21 Nov 2022 17:13:42 +0100
Subject: [PATCH 078/875] dt-bindings: pwm: renesas,tpu: Add r8a779g0 support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Document support for the 16-Bit Timer Pulse Unit (TPU) in the Renesas
R-Car V4H (R8A779G0) SoC.

Based on a patch in the BSP by CongDang.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml
index c6b2ab56b7fea..a3e52b22dd180 100644
--- a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml
@@ -40,6 +40,7 @@ properties:
           - renesas,tpu-r8a77970  # R-Car V3M
           - renesas,tpu-r8a77980  # R-Car V3H
           - renesas,tpu-r8a779a0  # R-Car V3U
+          - renesas,tpu-r8a779g0  # R-Car V4H
       - const: renesas,tpu
 
   reg:
-- 
GitLab


From d5f30a7da8ea8e6450250275cec5670cee3c4264 Mon Sep 17 00:00:00 2001
From: "Steven Rostedt (Google)" <rostedt@goodmis.org>
Date: Thu, 17 Nov 2022 21:42:49 -0500
Subject: [PATCH 079/875] tracing: Fix race where eprobes can be called before
 the event

The flag that tells the event to call its triggers after reading the event
is set for eprobes after the eprobe is enabled. This leads to a race where
the eprobe may be triggered at the beginning of the event where the record
information is NULL. The eprobe then dereferences the NULL record causing
a NULL kernel pointer bug.

Test for a NULL record to keep this from happening.

Link: https://lore.kernel.org/linux-trace-kernel/20221116192552.1066630-1-rafaelmendsr@gmail.com/
Link: https://lore.kernel.org/all/20221117214249.2addbe10@gandalf.local.home/

Cc: stable@vger.kernel.org
Fixes: 7491e2c442781 ("tracing: Add a probe that attaches to trace events")
Reported-by: Rafael Mendonca <rafaelmendsr@gmail.com>
Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>
Acked-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
Signed-off-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
---
 kernel/trace/trace_eprobe.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/kernel/trace/trace_eprobe.c b/kernel/trace/trace_eprobe.c
index 123d2c0a6b688..352b65e2b9105 100644
--- a/kernel/trace/trace_eprobe.c
+++ b/kernel/trace/trace_eprobe.c
@@ -564,6 +564,9 @@ static void eprobe_trigger_func(struct event_trigger_data *data,
 {
 	struct eprobe_data *edata = data->private_data;
 
+	if (unlikely(!rec))
+		return;
+
 	__eprobe_trace_func(edata, rec);
 }
 
-- 
GitLab


From 63a4dc0a0bb0e9bfeb2c88ccda81abdde4cdd6b8 Mon Sep 17 00:00:00 2001
From: Li Hua <hucool.lihua@huawei.com>
Date: Mon, 21 Nov 2022 11:06:20 +0800
Subject: [PATCH 080/875] test_kprobes: Fix implicit declaration error of
 test_kprobes
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

If KPROBES_SANITY_TEST and ARCH_CORRECT_STACKTRACE_ON_KRETPROBE is enabled, but
STACKTRACE is not set. Build failed as below:

lib/test_kprobes.c: In function ‘stacktrace_return_handler’:
lib/test_kprobes.c:228:8: error: implicit declaration of function ‘stack_trace_save’; did you mean ‘stacktrace_driver’? [-Werror=implicit-function-declaration]
  ret = stack_trace_save(stack_buf, STACK_BUF_SIZE, 0);
        ^~~~~~~~~~~~~~~~
        stacktrace_driver
cc1: all warnings being treated as errors
scripts/Makefile.build:250: recipe for target 'lib/test_kprobes.o' failed
make[2]: *** [lib/test_kprobes.o] Error 1

To fix this error, Select STACKTRACE if ARCH_CORRECT_STACKTRACE_ON_KRETPROBE is enabled.

Link: https://lore.kernel.org/all/20221121030620.63181-1-hucool.lihua@huawei.com/

Fixes: 1f6d3a8f5e39 ("kprobes: Add a test case for stacktrace from kretprobe handler")
Cc: stable@vger.kernel.org
Signed-off-by: Li Hua <hucool.lihua@huawei.com>
Acked-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
Signed-off-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
---
 lib/Kconfig.debug | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index c3c0b077ade33..a1005415f0f48 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -2107,6 +2107,7 @@ config KPROBES_SANITY_TEST
 	depends on DEBUG_KERNEL
 	depends on KPROBES
 	depends on KUNIT
+	select STACKTRACE if ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
 	default KUNIT_ALL_TESTS
 	help
 	  This option provides for testing basic kprobes functionality on
-- 
GitLab


From ba4fde74fc7fdd5ef37066a42721f37621cb80f2 Mon Sep 17 00:00:00 2001
From: Tanmay Shah <tanmay.shah@amd.com>
Date: Mon, 14 Nov 2022 15:39:35 -0800
Subject: [PATCH 081/875] dt-bindings: remoteproc: Add Xilinx RPU subsystem
 bindings

Xilinx ZynqMP platform has dual-core ARM Cortex R5 Realtime Processing
Unit(RPU) subsystem. This patch adds dt-bindings for RPU subsystem
(cluster).

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221114233940.2096237-2-tanmay.shah@amd.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 .../remoteproc/xlnx,zynqmp-r5fss.yaml         | 135 ++++++++++++++++++
 include/dt-bindings/power/xlnx-zynqmp-power.h |   6 +
 2 files changed, 141 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml

diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml
new file mode 100644
index 0000000000000..9f677367dd9f7
--- /dev/null
+++ b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx R5F processor subsystem
+
+maintainers:
+  - Ben Levinsky <ben.levinsky@amd.com>
+  - Tanmay Shah <tanmay.shah@amd.com>
+
+description: |
+  The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
+  real-time processing based on the Cortex-R5F processor core from ARM.
+  The Cortex-R5F processor implements the Arm v7-R architecture and includes a
+  floating-point unit that implements the Arm VFPv3 instruction set.
+
+properties:
+  compatible:
+    const: xlnx,zynqmp-r5fss
+
+  xlnx,cluster-mode:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1, 2]
+    description: |
+      The RPU MPCore can operate in split mode (Dual-processor performance), Safety
+      lock-step mode(Both RPU cores execute the same code in lock-step,
+      clock-for-clock) or Single CPU mode (RPU core 0 is held in reset while
+      core 1 runs normally). The processor does not support dynamic configuration.
+      Switching between modes is only permitted immediately after a processor reset.
+      If set to  1 then lockstep mode and if 0 then split mode.
+      If set to  2 then single CPU mode. When not defined, default will be lockstep mode.
+      In summary,
+      0: split mode
+      1: lockstep mode (default)
+      2: single cpu mode
+
+patternProperties:
+  "^r5f-[a-f0-9]+$":
+    type: object
+    description: |
+      The RPU is located in the Low Power Domain of the Processor Subsystem.
+      Each processor includes separate L1 instruction and data caches and
+      tightly coupled memories (TCM). System memory is cacheable, but the TCM
+      memory space is non-cacheable.
+
+      Each RPU contains one 64KB memory and two 32KB memories that
+      are accessed via the TCM A and B port interfaces, for a total of 128KB
+      per processor. In lock-step mode, the processor has access to 256KB of
+      TCM memory.
+
+    properties:
+      compatible:
+        const: xlnx,zynqmp-r5f
+
+      power-domains:
+        maxItems: 1
+
+      mboxes:
+        minItems: 1
+        items:
+          - description: mailbox channel to send data to RPU
+          - description: mailbox channel to receive data from RPU
+
+      mbox-names:
+        minItems: 1
+        items:
+          - const: tx
+          - const: rx
+
+      sram:
+        $ref: /schemas/types.yaml#/definitions/phandle-array
+        minItems: 1
+        maxItems: 8
+        items:
+          maxItems: 1
+        description: |
+          phandles to one or more reserved on-chip SRAM regions. Other than TCM,
+          the RPU can execute instructions and access data from the OCM memory,
+          the main DDR memory, and other system memories.
+
+          The regions should be defined as child nodes of the respective SRAM
+          node, and should be defined as per the generic bindings in
+          Documentation/devicetree/bindings/sram/sram.yaml
+
+      memory-region:
+        description: |
+          List of phandles to the reserved memory regions associated with the
+          remoteproc device. This is variable and describes the memories shared with
+          the remote processor (e.g. remoteproc firmware and carveouts, rpmsg
+          vrings, ...). This reserved memory region will be allocated in DDR memory.
+        minItems: 1
+        maxItems: 8
+        items:
+          - description: region used for RPU firmware image section
+          - description: vdev buffer
+          - description: vring0
+          - description: vring1
+        additionalItems: true
+
+    required:
+      - compatible
+      - power-domains
+
+    unevaluatedProperties: false
+
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    remoteproc {
+        compatible = "xlnx,zynqmp-r5fss";
+        xlnx,cluster-mode = <1>;
+
+        r5f-0 {
+            compatible = "xlnx,zynqmp-r5f";
+            power-domains = <&zynqmp_firmware 0x7>;
+            memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>;
+            mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>;
+            mbox-names = "tx", "rx";
+        };
+
+        r5f-1 {
+            compatible = "xlnx,zynqmp-r5f";
+            power-domains = <&zynqmp_firmware 0x8>;
+            memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, <&rpu1vdev0vring0>, <&rpu1vdev0vring1>;
+            mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>;
+            mbox-names = "tx", "rx";
+        };
+    };
+...
diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h
index 0d9a412fd5e04..618024cbb20dc 100644
--- a/include/dt-bindings/power/xlnx-zynqmp-power.h
+++ b/include/dt-bindings/power/xlnx-zynqmp-power.h
@@ -6,6 +6,12 @@
 #ifndef _DT_BINDINGS_ZYNQMP_POWER_H
 #define _DT_BINDINGS_ZYNQMP_POWER_H
 
+#define		PD_RPU_0	7
+#define		PD_RPU_1	8
+#define		PD_R5_0_ATCM	15
+#define		PD_R5_0_BTCM	16
+#define		PD_R5_1_ATCM	17
+#define		PD_R5_1_BTCM	18
 #define		PD_USB_0	22
 #define		PD_USB_1	23
 #define		PD_TTC_0	24
-- 
GitLab


From 400f6af048930bce01419f5d1e50bebc03429e35 Mon Sep 17 00:00:00 2001
From: Tanmay Shah <tanmay.shah@amd.com>
Date: Mon, 14 Nov 2022 15:39:36 -0800
Subject: [PATCH 082/875] arm64: dts: xilinx: zynqmp: Add RPU subsystem device
 node

RPU subsystem can be configured in cluster-mode or split mode.
Also each r5 core has separate power domains.

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20221114233940.2096237-3-tanmay.shah@amd.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 33 ++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index a549265e55f6e..c0f60833c0ae2 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -100,6 +100,22 @@
 		};
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		rproc_0_fw_image: memory@3ed00000 {
+			no-map;
+			reg = <0x0 0x3ed00000 0x0 0x40000>;
+		};
+
+		rproc_1_fw_image: memory@3ef00000 {
+			no-map;
+			reg = <0x0 0x3ef00000 0x0 0x40000>;
+		};
+	};
+
 	zynqmp_ipi: zynqmp_ipi {
 		compatible = "xlnx,zynqmp-ipi-mailbox";
 		interrupt-parent = <&gic>;
@@ -203,6 +219,23 @@
 		ranges;
 	};
 
+	remoteproc {
+		compatible = "xlnx,zynqmp-r5fss";
+		xlnx,cluster-mode = <1>;
+
+		r5f-0 {
+			compatible = "xlnx,zynqmp-r5f";
+			power-domains = <&zynqmp_firmware PD_RPU_0>;
+			memory-region = <&rproc_0_fw_image>;
+		};
+
+		r5f-1 {
+			compatible = "xlnx,zynqmp-r5f";
+			power-domains = <&zynqmp_firmware PD_RPU_1>;
+			memory-region = <&rproc_1_fw_image>;
+		};
+	};
+
 	amba: axi {
 		compatible = "simple-bus";
 		#address-cells = <2>;
-- 
GitLab


From b2bd0a8c3ab11f355392c7b81aec5187fc0d562e Mon Sep 17 00:00:00 2001
From: Ben Levinsky <ben.levinsky@amd.com>
Date: Mon, 14 Nov 2022 15:39:37 -0800
Subject: [PATCH 083/875] firmware: xilinx: Add ZynqMP firmware ioctl enums for
 RPU configuration.

Add ZynqMP firmware ioctl enums for RPU configuration and TCM Nodes for
later use via request_node and release_node

Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20221114233940.2096237-4-tanmay.shah@amd.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 include/linux/firmware/xlnx-zynqmp.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 76d2b3ebad847..bdbf855b5eef0 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -135,6 +135,10 @@ enum pm_ret_status {
 };
 
 enum pm_ioctl_id {
+	IOCTL_GET_RPU_OPER_MODE = 0,
+	IOCTL_SET_RPU_OPER_MODE = 1,
+	IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
+	IOCTL_TCM_COMB_CONFIG = 3,
 	IOCTL_SD_DLL_RESET = 6,
 	IOCTL_SET_SD_TAPDELAY = 7,
 	IOCTL_SET_PLL_FRAC_MODE = 8,
@@ -175,6 +179,21 @@ enum pm_query_id {
 	PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
 };
 
+enum rpu_oper_mode {
+	PM_RPU_MODE_LOCKSTEP = 0,
+	PM_RPU_MODE_SPLIT = 1,
+};
+
+enum rpu_boot_mem {
+	PM_RPU_BOOTMEM_LOVEC = 0,
+	PM_RPU_BOOTMEM_HIVEC = 1,
+};
+
+enum rpu_tcm_comb {
+	PM_RPU_TCM_SPLIT = 0,
+	PM_RPU_TCM_COMB = 1,
+};
+
 enum zynqmp_pm_reset_action {
 	PM_RESET_ACTION_RELEASE = 0,
 	PM_RESET_ACTION_ASSERT = 1,
-- 
GitLab


From da22a04f4727694e2c562ae4eb61daf77eef0427 Mon Sep 17 00:00:00 2001
From: Ben Levinsky <ben.levinsky@amd.com>
Date: Mon, 14 Nov 2022 15:39:38 -0800
Subject: [PATCH 084/875] firmware: xilinx: Add shutdown/wakeup APIs

Add shutdown/wakeup a resource eemi operations to shutdown
or bringup a resource.

Note alignment of args matches convention of other fn's in this file.
The reason being that the long fn name results in aligned args that
otherwise go over 80 chars so shift right to avoid this

Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20221114233940.2096237-5-tanmay.shah@amd.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/firmware/xilinx/zynqmp.c     | 35 ++++++++++++++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h | 23 ++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index ff5cabe70a2b2..1865e43ed7e7a 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -1159,6 +1159,41 @@ int zynqmp_pm_release_node(const u32 node)
 }
 EXPORT_SYMBOL_GPL(zynqmp_pm_release_node);
 
+/**
+ * zynqmp_pm_force_pwrdwn - PM call to request for another PU or subsystem to
+ *             be powered down forcefully
+ * @node:  Node ID of the targeted PU or subsystem
+ * @ack:   Flag to specify whether acknowledge is requested
+ *
+ * Return: status, either success or error+reason
+ */
+int zynqmp_pm_force_pwrdwn(const u32 node,
+			   const enum zynqmp_pm_request_ack ack)
+{
+	return zynqmp_pm_invoke_fn(PM_FORCE_POWERDOWN, node, ack, 0, 0, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_force_pwrdwn);
+
+/**
+ * zynqmp_pm_request_wake - PM call to wake up selected master or subsystem
+ * @node:  Node ID of the master or subsystem
+ * @set_addr:  Specifies whether the address argument is relevant
+ * @address:   Address from which to resume when woken up
+ * @ack:   Flag to specify whether acknowledge requested
+ *
+ * Return: status, either success or error+reason
+ */
+int zynqmp_pm_request_wake(const u32 node,
+			   const bool set_addr,
+			   const u64 address,
+			   const enum zynqmp_pm_request_ack ack)
+{
+	/* set_addr flag is encoded into 1st bit of address */
+	return zynqmp_pm_invoke_fn(PM_REQUEST_WAKEUP, node, address | set_addr,
+				   address >> 32, ack, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_request_wake);
+
 /**
  * zynqmp_pm_set_requirement() - PM call to set requirement for PM slaves
  * @node:		Node ID of the slave
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index bdbf855b5eef0..ad3f2bd0c4704 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -12,6 +12,7 @@
 
 #ifndef __FIRMWARE_ZYNQMP_H__
 #define __FIRMWARE_ZYNQMP_H__
+#include <linux/types.h>
 
 #include <linux/err.h>
 
@@ -87,6 +88,8 @@ enum pm_api_cb_id {
 enum pm_api_id {
 	PM_GET_API_VERSION = 1,
 	PM_REGISTER_NOTIFIER = 5,
+	PM_FORCE_POWERDOWN = 8,
+	PM_REQUEST_WAKEUP = 10,
 	PM_SYSTEM_SHUTDOWN = 12,
 	PM_REQUEST_NODE = 13,
 	PM_RELEASE_NODE = 14,
@@ -521,6 +524,12 @@ int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
 int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value);
 int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload);
 int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset);
+int zynqmp_pm_force_pwrdwn(const u32 target,
+			   const enum zynqmp_pm_request_ack ack);
+int zynqmp_pm_request_wake(const u32 node,
+			   const bool set_addr,
+			   const u64 address,
+			   const enum zynqmp_pm_request_ack ack);
 int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
 int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
 			     u32 value);
@@ -795,6 +804,20 @@ static inline int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset)
 	return -ENODEV;
 }
 
+static inline int zynqmp_pm_force_pwrdwn(const u32 target,
+					 const enum zynqmp_pm_request_ack ack)
+{
+	return -ENODEV;
+}
+
+static inline int zynqmp_pm_request_wake(const u32 node,
+					 const bool set_addr,
+					 const u64 address,
+					 const enum zynqmp_pm_request_ack ack)
+{
+	return -ENODEV;
+}
+
 static inline int zynqmp_pm_set_sd_config(u32 node,
 					  enum pm_sd_config_type config,
 					  u32 value)
-- 
GitLab


From a5e56980cfb7ecaeb9a207c74e2e90ec544f0bc0 Mon Sep 17 00:00:00 2001
From: Ben Levinsky <ben.levinsky@amd.com>
Date: Mon, 14 Nov 2022 15:39:39 -0800
Subject: [PATCH 085/875] firmware: xilinx: Add RPU configuration APIs

This patch adds APIs to access to configure RPU and its
processor-specific memory.

That is query the run-time mode of RPU as either split or lockstep as well
as API to set this mode. In addition add APIs to access configuration of
the RPUs' tightly coupled memory (TCM).

Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20221114233940.2096237-6-tanmay.shah@amd.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/firmware/xilinx/zynqmp.c     | 62 ++++++++++++++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h | 18 ++++++++
 2 files changed, 80 insertions(+)

diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 1865e43ed7e7a..e4981e7f35003 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -1159,6 +1159,68 @@ int zynqmp_pm_release_node(const u32 node)
 }
 EXPORT_SYMBOL_GPL(zynqmp_pm_release_node);
 
+/**
+ * zynqmp_pm_get_rpu_mode() - Get RPU mode
+ * @node_id:	Node ID of the device
+ * @rpu_mode:	return by reference value
+ *		either split or lockstep
+ *
+ * Return:	return 0 on success or error+reason.
+ *		if success, then  rpu_mode will be set
+ *		to current rpu mode.
+ */
+int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode)
+{
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
+
+	ret = zynqmp_pm_invoke_fn(PM_IOCTL, node_id,
+				  IOCTL_GET_RPU_OPER_MODE, 0, 0, ret_payload);
+
+	/* only set rpu_mode if no error */
+	if (ret == XST_PM_SUCCESS)
+		*rpu_mode = ret_payload[0];
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_get_rpu_mode);
+
+/**
+ * zynqmp_pm_set_rpu_mode() - Set RPU mode
+ * @node_id:	Node ID of the device
+ * @rpu_mode:	Argument 1 to requested IOCTL call. either split or lockstep
+ *
+ *		This function is used to set RPU mode to split or
+ *		lockstep
+ *
+ * Return:	Returns status, either success or error+reason
+ */
+int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode)
+{
+	return zynqmp_pm_invoke_fn(PM_IOCTL, node_id,
+				   IOCTL_SET_RPU_OPER_MODE, (u32)rpu_mode,
+				   0, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_set_rpu_mode);
+
+/**
+ * zynqmp_pm_set_tcm_config - configure TCM
+ * @node_id:	Firmware specific TCM subsystem ID
+ * @tcm_mode:	Argument 1 to requested IOCTL call
+ *              either PM_RPU_TCM_COMB or PM_RPU_TCM_SPLIT
+ *
+ * This function is used to set RPU mode to split or combined
+ *
+ * Return: status: 0 for success, else failure
+ */
+int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode)
+{
+	return zynqmp_pm_invoke_fn(PM_IOCTL, node_id,
+				   IOCTL_TCM_COMB_CONFIG, (u32)tcm_mode, 0,
+				   NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_set_tcm_config);
+
 /**
  * zynqmp_pm_force_pwrdwn - PM call to request for another PU or subsystem to
  *             be powered down forcefully
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index ad3f2bd0c4704..cf92e739fa3b2 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -530,6 +530,9 @@ int zynqmp_pm_request_wake(const u32 node,
 			   const bool set_addr,
 			   const u64 address,
 			   const enum zynqmp_pm_request_ack ack);
+int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode);
+int zynqmp_pm_set_rpu_mode(u32 node_id, u32 arg1);
+int zynqmp_pm_set_tcm_config(u32 node_id, u32 arg1);
 int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
 int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
 			     u32 value);
@@ -818,6 +821,21 @@ static inline int zynqmp_pm_request_wake(const u32 node,
 	return -ENODEV;
 }
 
+static inline int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode)
+{
+	return -ENODEV;
+}
+
+static inline int zynqmp_pm_set_rpu_mode(u32 node_id, u32 arg1)
+{
+	return -ENODEV;
+}
+
+static inline int zynqmp_pm_set_tcm_config(u32 node_id, u32 arg1)
+{
+	return -ENODEV;
+}
+
 static inline int zynqmp_pm_set_sd_config(u32 node,
 					  enum pm_sd_config_type config,
 					  u32 value)
-- 
GitLab


From 6b291e8020a8bd90e94ee13d61f251040425c90d Mon Sep 17 00:00:00 2001
From: Tanmay Shah <tanmay.shah@amd.com>
Date: Mon, 14 Nov 2022 15:39:40 -0800
Subject: [PATCH 086/875] drivers: remoteproc: Add Xilinx r5 remoteproc driver

This driver enables r5f dual core Real time Processing Unit subsystem
available on Xilinx Zynq Ultrascale MPSoC Platform. RPU subsystem
(cluster) can be configured in different modes e.g. split mode in which
two r5f cores work independent of each other and lock-step mode in which
both r5f cores execute same code clock-for-clock and notify if the
result is different.

The Xilinx r5 Remoteproc Driver boots the RPU cores via calls to the Xilinx
Platform Management Unit that handles the R5 configuration, memory access
and R5 lifecycle management. The interface to this manager is done in this
driver via zynqmp_pm_* function calls.

Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Reported-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/r/20221114233940.2096237-7-tanmay.shah@amd.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/remoteproc/Kconfig              |   13 +
 drivers/remoteproc/Makefile             |    1 +
 drivers/remoteproc/xlnx_r5_remoteproc.c | 1067 +++++++++++++++++++++++
 3 files changed, 1081 insertions(+)
 create mode 100644 drivers/remoteproc/xlnx_r5_remoteproc.c

diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index 1660197866531..a850e9f486dd6 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -352,6 +352,19 @@ config TI_K3_R5_REMOTEPROC
 	  It's safe to say N here if you're not interested in utilizing
 	  a slave processor.
 
+config XLNX_R5_REMOTEPROC
+	tristate "Xilinx R5 remoteproc support"
+	depends on PM && ARCH_ZYNQMP
+	select ZYNQMP_FIRMWARE
+	select RPMSG_VIRTIO
+	select MAILBOX
+	select ZYNQMP_IPI_MBOX
+	help
+	  Say y or m here to support Xilinx R5 remote processors via the remote
+	  processor framework.
+
+	  It's safe to say N if not interested in using RPU r5f cores.
+
 endif # REMOTEPROC
 
 endmenu
diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
index 5478c7cb9e07b..91314a9b43cef 100644
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -38,3 +38,4 @@ obj-$(CONFIG_ST_SLIM_REMOTEPROC)	+= st_slim_rproc.o
 obj-$(CONFIG_STM32_RPROC)		+= stm32_rproc.o
 obj-$(CONFIG_TI_K3_DSP_REMOTEPROC)	+= ti_k3_dsp_remoteproc.o
 obj-$(CONFIG_TI_K3_R5_REMOTEPROC)	+= ti_k3_r5_remoteproc.o
+obj-$(CONFIG_XLNX_R5_REMOTEPROC)	+= xlnx_r5_remoteproc.o
diff --git a/drivers/remoteproc/xlnx_r5_remoteproc.c b/drivers/remoteproc/xlnx_r5_remoteproc.c
new file mode 100644
index 0000000000000..2db57d3941555
--- /dev/null
+++ b/drivers/remoteproc/xlnx_r5_remoteproc.c
@@ -0,0 +1,1067 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ZynqMP R5 Remote Processor driver
+ *
+ */
+
+#include <dt-bindings/power/xlnx-zynqmp-power.h>
+#include <linux/dma-mapping.h>
+#include <linux/firmware/xlnx-zynqmp.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/of_reserved_mem.h>
+#include <linux/platform_device.h>
+#include <linux/remoteproc.h>
+#include <linux/slab.h>
+
+#include "remoteproc_internal.h"
+
+/*
+ * settings for RPU cluster mode which
+ * reflects possible values of xlnx,cluster-mode dt-property
+ */
+enum zynqmp_r5_cluster_mode {
+	SPLIT_MODE = 0, /* When cores run as separate processor */
+	LOCKSTEP_MODE = 1, /* cores execute same code in lockstep,clk-for-clk */
+	SINGLE_CPU_MODE = 2, /* core0 is held in reset and only core1 runs */
+};
+
+/**
+ * struct mem_bank_data - Memory Bank description
+ *
+ * @addr: Start address of memory bank
+ * @size: Size of Memory bank
+ * @pm_domain_id: Power-domains id of memory bank for firmware to turn on/off
+ * @bank_name: name of the bank for remoteproc framework
+ */
+struct mem_bank_data {
+	phys_addr_t addr;
+	size_t size;
+	u32 pm_domain_id;
+	char *bank_name;
+};
+
+/*
+ * Hardcoded TCM bank values. This will be removed once TCM bindings are
+ * accepted for system-dt specifications and upstreamed in linux kernel
+ */
+static const struct mem_bank_data zynqmp_tcm_banks[] = {
+	{0xffe00000UL, 0x10000UL, PD_R5_0_ATCM, "atcm0"}, /* TCM 64KB each */
+	{0xffe20000UL, 0x10000UL, PD_R5_0_BTCM, "btcm0"},
+	{0xffe90000UL, 0x10000UL, PD_R5_1_ATCM, "atcm1"},
+	{0xffeb0000UL, 0x10000UL, PD_R5_1_BTCM, "btcm1"},
+};
+
+/**
+ * struct zynqmp_r5_core
+ *
+ * @dev: device of RPU instance
+ * @np: device node of RPU instance
+ * @tcm_bank_count: number TCM banks accessible to this RPU
+ * @tcm_banks: array of each TCM bank data
+ * @rmem_count: Number of reserved mem regions
+ * @rmem: reserved memory region nodes from device tree
+ * @rproc: rproc handle
+ * @pm_domain_id: RPU CPU power domain id
+ */
+struct zynqmp_r5_core {
+	struct device *dev;
+	struct device_node *np;
+	int tcm_bank_count;
+	struct mem_bank_data **tcm_banks;
+	int rmem_count;
+	struct reserved_mem **rmem;
+	struct rproc *rproc;
+	u32 pm_domain_id;
+};
+
+/**
+ * struct zynqmp_r5_cluster
+ *
+ * @dev: r5f subsystem cluster device node
+ * @mode: cluster mode of type zynqmp_r5_cluster_mode
+ * @core_count: number of r5 cores used for this cluster mode
+ * @r5_cores: Array of pointers pointing to r5 core
+ */
+struct zynqmp_r5_cluster {
+	struct device *dev;
+	enum  zynqmp_r5_cluster_mode mode;
+	int core_count;
+	struct zynqmp_r5_core **r5_cores;
+};
+
+/*
+ * zynqmp_r5_set_mode()
+ *
+ * set RPU cluster and TCM operation mode
+ *
+ * @r5_core: pointer to zynqmp_r5_core type object
+ * @fw_reg_val: value expected by firmware to configure RPU cluster mode
+ * @tcm_mode: value expected by fw to configure TCM mode (lockstep or split)
+ *
+ * Return: 0 for success and < 0 for failure
+ */
+static int zynqmp_r5_set_mode(struct zynqmp_r5_core *r5_core,
+			      enum rpu_oper_mode fw_reg_val,
+			      enum rpu_tcm_comb tcm_mode)
+{
+	int ret;
+
+	ret = zynqmp_pm_set_rpu_mode(r5_core->pm_domain_id, fw_reg_val);
+	if (ret < 0) {
+		dev_err(r5_core->dev, "failed to set RPU mode\n");
+		return ret;
+	}
+
+	ret = zynqmp_pm_set_tcm_config(r5_core->pm_domain_id, tcm_mode);
+	if (ret < 0)
+		dev_err(r5_core->dev, "failed to configure TCM\n");
+
+	return ret;
+}
+
+/*
+ * zynqmp_r5_rproc_start()
+ * @rproc: single R5 core's corresponding rproc instance
+ *
+ * Start R5 Core from designated boot address.
+ *
+ * return 0 on success, otherwise non-zero value on failure
+ */
+static int zynqmp_r5_rproc_start(struct rproc *rproc)
+{
+	struct zynqmp_r5_core *r5_core = rproc->priv;
+	enum rpu_boot_mem bootmem;
+	int ret;
+
+	/*
+	 * The exception vector pointers (EVP) refer to the base-address of
+	 * exception vectors (for reset, IRQ, FIQ, etc). The reset-vector
+	 * starts at the base-address and subsequent vectors are on 4-byte
+	 * boundaries.
+	 *
+	 * Exception vectors can start either from 0x0000_0000 (LOVEC) or
+	 * from 0xFFFF_0000 (HIVEC) which is mapped in the OCM (On-Chip Memory)
+	 *
+	 * Usually firmware will put Exception vectors at LOVEC.
+	 *
+	 * It is not recommend that you change the exception vector.
+	 * Changing the EVP to HIVEC will result in increased interrupt latency
+	 * and jitter. Also, if the OCM is secured and the Cortex-R5F processor
+	 * is non-secured, then the Cortex-R5F processor cannot access the
+	 * HIVEC exception vectors in the OCM.
+	 */
+	bootmem = (rproc->bootaddr >= 0xFFFC0000) ?
+		   PM_RPU_BOOTMEM_HIVEC : PM_RPU_BOOTMEM_LOVEC;
+
+	dev_dbg(r5_core->dev, "RPU boot addr 0x%llx from %s.", rproc->bootaddr,
+		bootmem == PM_RPU_BOOTMEM_HIVEC ? "OCM" : "TCM");
+
+	ret = zynqmp_pm_request_wake(r5_core->pm_domain_id, 1,
+				     bootmem, ZYNQMP_PM_REQUEST_ACK_NO);
+	if (ret)
+		dev_err(r5_core->dev,
+			"failed to start RPU = 0x%x\n", r5_core->pm_domain_id);
+	return ret;
+}
+
+/*
+ * zynqmp_r5_rproc_stop()
+ * @rproc: single R5 core's corresponding rproc instance
+ *
+ * Power down  R5 Core.
+ *
+ * return 0 on success, otherwise non-zero value on failure
+ */
+static int zynqmp_r5_rproc_stop(struct rproc *rproc)
+{
+	struct zynqmp_r5_core *r5_core = rproc->priv;
+	int ret;
+
+	ret = zynqmp_pm_force_pwrdwn(r5_core->pm_domain_id,
+				     ZYNQMP_PM_REQUEST_ACK_BLOCKING);
+	if (ret)
+		dev_err(r5_core->dev, "failed to stop remoteproc RPU %d\n", ret);
+
+	return ret;
+}
+
+/*
+ * zynqmp_r5_mem_region_map()
+ * @rproc: single R5 core's corresponding rproc instance
+ * @mem: mem descriptor to map reserved memory-regions
+ *
+ * Callback to map va for memory-region's carveout.
+ *
+ * return 0 on success, otherwise non-zero value on failure
+ */
+static int zynqmp_r5_mem_region_map(struct rproc *rproc,
+				    struct rproc_mem_entry *mem)
+{
+	void __iomem *va;
+
+	va = ioremap_wc(mem->dma, mem->len);
+	if (IS_ERR_OR_NULL(va))
+		return -ENOMEM;
+
+	mem->va = (void *)va;
+
+	return 0;
+}
+
+/*
+ * zynqmp_r5_rproc_mem_unmap
+ * @rproc: single R5 core's corresponding rproc instance
+ * @mem: mem entry to unmap
+ *
+ * Unmap memory-region carveout
+ *
+ * return: always returns 0
+ */
+static int zynqmp_r5_mem_region_unmap(struct rproc *rproc,
+				      struct rproc_mem_entry *mem)
+{
+	iounmap((void __iomem *)mem->va);
+	return 0;
+}
+
+/*
+ * add_mem_regions_carveout()
+ * @rproc: single R5 core's corresponding rproc instance
+ *
+ * Construct rproc mem carveouts from memory-region property nodes
+ *
+ * return 0 on success, otherwise non-zero value on failure
+ */
+static int add_mem_regions_carveout(struct rproc *rproc)
+{
+	struct rproc_mem_entry *rproc_mem;
+	struct zynqmp_r5_core *r5_core;
+	struct reserved_mem *rmem;
+	int i, num_mem_regions;
+
+	r5_core = (struct zynqmp_r5_core *)rproc->priv;
+	num_mem_regions = r5_core->rmem_count;
+
+	for (i = 0; i < num_mem_regions; i++) {
+		rmem = r5_core->rmem[i];
+
+		if (!strncmp(rmem->name, "vdev0buffer", strlen("vdev0buffer"))) {
+			/* Init reserved memory for vdev buffer */
+			rproc_mem = rproc_of_resm_mem_entry_init(&rproc->dev, i,
+								 rmem->size,
+								 rmem->base,
+								 rmem->name);
+		} else {
+			/* Register associated reserved memory regions */
+			rproc_mem = rproc_mem_entry_init(&rproc->dev, NULL,
+							 (dma_addr_t)rmem->base,
+							 rmem->size, rmem->base,
+							 zynqmp_r5_mem_region_map,
+							 zynqmp_r5_mem_region_unmap,
+							 rmem->name);
+		}
+
+		if (!rproc_mem)
+			return -ENOMEM;
+
+		rproc_add_carveout(rproc, rproc_mem);
+
+		dev_dbg(&rproc->dev, "reserved mem carveout %s addr=%llx, size=0x%llx",
+			rmem->name, rmem->base, rmem->size);
+	}
+
+	return 0;
+}
+
+/*
+ * tcm_mem_unmap()
+ * @rproc: single R5 core's corresponding rproc instance
+ * @mem: tcm mem entry to unmap
+ *
+ * Unmap TCM banks when powering down R5 core.
+ *
+ * return always 0
+ */
+static int tcm_mem_unmap(struct rproc *rproc, struct rproc_mem_entry *mem)
+{
+	iounmap((void __iomem *)mem->va);
+
+	return 0;
+}
+
+/*
+ * tcm_mem_map()
+ * @rproc: single R5 core's corresponding rproc instance
+ * @mem: tcm memory entry descriptor
+ *
+ * Given TCM bank entry, this func setup virtual address for TCM bank
+ * remoteproc carveout. It also takes care of va to da address translation
+ *
+ * return 0 on success, otherwise non-zero value on failure
+ */
+static int tcm_mem_map(struct rproc *rproc,
+		       struct rproc_mem_entry *mem)
+{
+	void __iomem *va;
+
+	va = ioremap_wc(mem->dma, mem->len);
+	if (IS_ERR_OR_NULL(va))
+		return -ENOMEM;
+
+	/* Update memory entry va */
+	mem->va = (void *)va;
+
+	/* clear TCMs */
+	memset_io(va, 0, mem->len);
+
+	/*
+	 * The R5s expect their TCM banks to be at address 0x0 and 0x2000,
+	 * while on the Linux side they are at 0xffexxxxx.
+	 *
+	 * Zero out the high 12 bits of the address. This will give
+	 * expected values for TCM Banks 0A and 0B (0x0 and 0x20000).
+	 */
+	mem->da &= 0x000fffff;
+
+	/*
+	 * TCM Banks 1A and 1B still have to be translated.
+	 *
+	 * Below handle these two banks' absolute addresses (0xffe90000 and
+	 * 0xffeb0000) and convert to the expected relative addresses
+	 * (0x0 and 0x20000).
+	 */
+	if (mem->da == 0x90000 || mem->da == 0xB0000)
+		mem->da -= 0x90000;
+
+	/* if translated TCM bank address is not valid report error */
+	if (mem->da != 0x0 && mem->da != 0x20000) {
+		dev_err(&rproc->dev, "invalid TCM address: %x\n", mem->da);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+/*
+ * add_tcm_carveout_split_mode()
+ * @rproc: single R5 core's corresponding rproc instance
+ *
+ * allocate and add remoteproc carveout for TCM memory in split mode
+ *
+ * return 0 on success, otherwise non-zero value on failure
+ */
+static int add_tcm_carveout_split_mode(struct rproc *rproc)
+{
+	struct rproc_mem_entry *rproc_mem;
+	struct zynqmp_r5_core *r5_core;
+	int i, num_banks, ret;
+	phys_addr_t bank_addr;
+	struct device *dev;
+	u32 pm_domain_id;
+	size_t bank_size;
+	char *bank_name;
+
+	r5_core = (struct zynqmp_r5_core *)rproc->priv;
+	dev = r5_core->dev;
+	num_banks = r5_core->tcm_bank_count;
+
+	/*
+	 * Power-on Each 64KB TCM,
+	 * register its address space, map and unmap functions
+	 * and add carveouts accordingly
+	 */
+	for (i = 0; i < num_banks; i++) {
+		bank_addr = r5_core->tcm_banks[i]->addr;
+		bank_name = r5_core->tcm_banks[i]->bank_name;
+		bank_size = r5_core->tcm_banks[i]->size;
+		pm_domain_id = r5_core->tcm_banks[i]->pm_domain_id;
+
+		ret = zynqmp_pm_request_node(pm_domain_id,
+					     ZYNQMP_PM_CAPABILITY_ACCESS, 0,
+					     ZYNQMP_PM_REQUEST_ACK_BLOCKING);
+		if (ret < 0) {
+			dev_err(dev, "failed to turn on TCM 0x%x", pm_domain_id);
+			goto release_tcm_split;
+		}
+
+		dev_dbg(dev, "TCM carveout split mode %s addr=%llx, size=0x%lx",
+			bank_name, bank_addr, bank_size);
+
+		rproc_mem = rproc_mem_entry_init(dev, NULL, bank_addr,
+						 bank_size, bank_addr,
+						 tcm_mem_map, tcm_mem_unmap,
+						 bank_name);
+		if (!rproc_mem) {
+			ret = -ENOMEM;
+			zynqmp_pm_release_node(pm_domain_id);
+			goto release_tcm_split;
+		}
+
+		rproc_add_carveout(rproc, rproc_mem);
+	}
+
+	return 0;
+
+release_tcm_split:
+	/* If failed, Turn off all TCM banks turned on before */
+	for (i--; i >= 0; i--) {
+		pm_domain_id = r5_core->tcm_banks[i]->pm_domain_id;
+		zynqmp_pm_release_node(pm_domain_id);
+	}
+	return ret;
+}
+
+/*
+ * add_tcm_carveout_lockstep_mode()
+ * @rproc: single R5 core's corresponding rproc instance
+ *
+ * allocate and add remoteproc carveout for TCM memory in lockstep mode
+ *
+ * return 0 on success, otherwise non-zero value on failure
+ */
+static int add_tcm_carveout_lockstep_mode(struct rproc *rproc)
+{
+	struct rproc_mem_entry *rproc_mem;
+	struct zynqmp_r5_core *r5_core;
+	int i, num_banks, ret;
+	phys_addr_t bank_addr;
+	size_t bank_size = 0;
+	struct device *dev;
+	u32 pm_domain_id;
+	char *bank_name;
+
+	r5_core = (struct zynqmp_r5_core *)rproc->priv;
+	dev = r5_core->dev;
+
+	/* Go through zynqmp banks for r5 node */
+	num_banks = r5_core->tcm_bank_count;
+
+	/*
+	 * In lockstep mode, TCM is contiguous memory block
+	 * However, each TCM block still needs to be enabled individually.
+	 * So, Enable each TCM block individually, but add their size
+	 * to create contiguous memory region.
+	 */
+	bank_addr = r5_core->tcm_banks[0]->addr;
+	bank_name = r5_core->tcm_banks[0]->bank_name;
+
+	for (i = 0; i < num_banks; i++) {
+		bank_size += r5_core->tcm_banks[i]->size;
+		pm_domain_id = r5_core->tcm_banks[i]->pm_domain_id;
+
+		/* Turn on each TCM bank individually */
+		ret = zynqmp_pm_request_node(pm_domain_id,
+					     ZYNQMP_PM_CAPABILITY_ACCESS, 0,
+					     ZYNQMP_PM_REQUEST_ACK_BLOCKING);
+		if (ret < 0) {
+			dev_err(dev, "failed to turn on TCM 0x%x", pm_domain_id);
+			goto release_tcm_lockstep;
+		}
+	}
+
+	dev_dbg(dev, "TCM add carveout lockstep mode %s addr=0x%llx, size=0x%lx",
+		bank_name, bank_addr, bank_size);
+
+	/* Register TCM address range, TCM map and unmap functions */
+	rproc_mem = rproc_mem_entry_init(dev, NULL, bank_addr,
+					 bank_size, bank_addr,
+					 tcm_mem_map, tcm_mem_unmap,
+					 bank_name);
+	if (!rproc_mem) {
+		ret = -ENOMEM;
+		goto release_tcm_lockstep;
+	}
+
+	/* If registration is success, add carveouts */
+	rproc_add_carveout(rproc, rproc_mem);
+
+	return 0;
+
+release_tcm_lockstep:
+	/* If failed, Turn off all TCM banks turned on before */
+	for (i--; i >= 0; i--) {
+		pm_domain_id = r5_core->tcm_banks[i]->pm_domain_id;
+		zynqmp_pm_release_node(pm_domain_id);
+	}
+	return ret;
+}
+
+/*
+ * add_tcm_banks()
+ * @rproc: single R5 core's corresponding rproc instance
+ *
+ * allocate and add remoteproc carveouts for TCM memory based on cluster mode
+ *
+ * return 0 on success, otherwise non-zero value on failure
+ */
+static int add_tcm_banks(struct rproc *rproc)
+{
+	struct zynqmp_r5_cluster *cluster;
+	struct zynqmp_r5_core *r5_core;
+	struct device *dev;
+
+	r5_core = (struct zynqmp_r5_core *)rproc->priv;
+	if (!r5_core)
+		return -EINVAL;
+
+	dev = r5_core->dev;
+
+	cluster = dev_get_drvdata(dev->parent);
+	if (!cluster) {
+		dev_err(dev->parent, "Invalid driver data\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * In lockstep mode TCM banks are one contiguous memory region of 256Kb
+	 * In split mode, each TCM bank is 64Kb and not contiguous.
+	 * We add memory carveouts accordingly.
+	 */
+	if (cluster->mode == SPLIT_MODE)
+		return add_tcm_carveout_split_mode(rproc);
+	else if (cluster->mode == LOCKSTEP_MODE)
+		return add_tcm_carveout_lockstep_mode(rproc);
+
+	return -EINVAL;
+}
+
+/*
+ * zynqmp_r5_parse_fw()
+ * @rproc: single R5 core's corresponding rproc instance
+ * @fw: ptr to firmware to be loaded onto r5 core
+ *
+ * get resource table if available
+ *
+ * return 0 on success, otherwise non-zero value on failure
+ */
+static int zynqmp_r5_parse_fw(struct rproc *rproc, const struct firmware *fw)
+{
+	int ret;
+
+	ret = rproc_elf_load_rsc_table(rproc, fw);
+	if (ret == -EINVAL) {
+		/*
+		 * resource table only required for IPC.
+		 * if not present, this is not necessarily an error;
+		 * for example, loading r5 hello world application
+		 * so simply inform user and keep going.
+		 */
+		dev_info(&rproc->dev, "no resource table found.\n");
+		ret = 0;
+	}
+	return ret;
+}
+
+/**
+ * zynqmp_r5_rproc_prepare()
+ * adds carveouts for TCM bank and reserved memory regions
+ *
+ * @rproc: Device node of each rproc
+ *
+ * Return: 0 for success else < 0 error code
+ */
+static int zynqmp_r5_rproc_prepare(struct rproc *rproc)
+{
+	int ret;
+
+	ret = add_tcm_banks(rproc);
+	if (ret) {
+		dev_err(&rproc->dev, "failed to get TCM banks, err %d\n", ret);
+		return ret;
+	}
+
+	ret = add_mem_regions_carveout(rproc);
+	if (ret) {
+		dev_err(&rproc->dev, "failed to get reserve mem regions %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+/**
+ * zynqmp_r5_rproc_unprepare()
+ * Turns off TCM banks using power-domain id
+ *
+ * @rproc: Device node of each rproc
+ *
+ * Return: always 0
+ */
+static int zynqmp_r5_rproc_unprepare(struct rproc *rproc)
+{
+	struct zynqmp_r5_core *r5_core;
+	u32 pm_domain_id;
+	int i;
+
+	r5_core = (struct zynqmp_r5_core *)rproc->priv;
+
+	for (i = 0; i < r5_core->tcm_bank_count; i++) {
+		pm_domain_id = r5_core->tcm_banks[i]->pm_domain_id;
+		if (zynqmp_pm_release_node(pm_domain_id))
+			dev_warn(r5_core->dev,
+				 "can't turn off TCM bank 0x%x", pm_domain_id);
+	}
+
+	return 0;
+}
+
+static const struct rproc_ops zynqmp_r5_rproc_ops = {
+	.prepare	= zynqmp_r5_rproc_prepare,
+	.unprepare	= zynqmp_r5_rproc_unprepare,
+	.start		= zynqmp_r5_rproc_start,
+	.stop		= zynqmp_r5_rproc_stop,
+	.load		= rproc_elf_load_segments,
+	.parse_fw	= zynqmp_r5_parse_fw,
+	.find_loaded_rsc_table = rproc_elf_find_loaded_rsc_table,
+	.sanity_check	= rproc_elf_sanity_check,
+	.get_boot_addr	= rproc_elf_get_boot_addr,
+};
+
+/**
+ * zynqmp_r5_add_rproc_core()
+ * Allocate and add struct rproc object for each r5f core
+ * This is called for each individual r5f core
+ *
+ * @cdev: Device node of each r5 core
+ *
+ * Return: zynqmp_r5_core object for success else error code pointer
+ */
+static struct zynqmp_r5_core *zynqmp_r5_add_rproc_core(struct device *cdev)
+{
+	struct zynqmp_r5_core *r5_core;
+	struct rproc *r5_rproc;
+	int ret;
+
+	/* Set up DMA mask */
+	ret = dma_set_coherent_mask(cdev, DMA_BIT_MASK(32));
+	if (ret)
+		return ERR_PTR(ret);
+
+	/* Allocate remoteproc instance */
+	r5_rproc = rproc_alloc(cdev, dev_name(cdev),
+			       &zynqmp_r5_rproc_ops,
+			       NULL, sizeof(struct zynqmp_r5_core));
+	if (!r5_rproc) {
+		dev_err(cdev, "failed to allocate memory for rproc instance\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	r5_rproc->auto_boot = false;
+	r5_core = (struct zynqmp_r5_core *)r5_rproc->priv;
+	r5_core->dev = cdev;
+	r5_core->np = dev_of_node(cdev);
+	if (!r5_core->np) {
+		dev_err(cdev, "can't get device node for r5 core\n");
+		ret = -EINVAL;
+		goto free_rproc;
+	}
+
+	/* Add R5 remoteproc core */
+	ret = rproc_add(r5_rproc);
+	if (ret) {
+		dev_err(cdev, "failed to add r5 remoteproc\n");
+		goto free_rproc;
+	}
+
+	r5_core->rproc = r5_rproc;
+	return r5_core;
+
+free_rproc:
+	rproc_free(r5_rproc);
+	return ERR_PTR(ret);
+}
+
+/**
+ * zynqmp_r5_get_tcm_node()
+ * Ideally this function should parse tcm node and store information
+ * in r5_core instance. For now, Hardcoded TCM information is used.
+ * This approach is used as TCM bindings for system-dt is being developed
+ *
+ * @cluster: pointer to zynqmp_r5_cluster type object
+ *
+ * Return: 0 for success and < 0 error code for failure.
+ */
+static int zynqmp_r5_get_tcm_node(struct zynqmp_r5_cluster *cluster)
+{
+	struct device *dev = cluster->dev;
+	struct zynqmp_r5_core *r5_core;
+	int tcm_bank_count, tcm_node;
+	int i, j;
+
+	tcm_bank_count = ARRAY_SIZE(zynqmp_tcm_banks);
+
+	/* count per core tcm banks */
+	tcm_bank_count = tcm_bank_count / cluster->core_count;
+
+	/*
+	 * r5 core 0 will use all of TCM banks in lockstep mode.
+	 * In split mode, r5 core0 will use 128k and r5 core1 will use another
+	 * 128k. Assign TCM banks to each core accordingly
+	 */
+	tcm_node = 0;
+	for (i = 0; i < cluster->core_count; i++) {
+		r5_core = cluster->r5_cores[i];
+		r5_core->tcm_banks = devm_kcalloc(dev, tcm_bank_count,
+						  sizeof(struct mem_bank_data *),
+						  GFP_KERNEL);
+		if (!r5_core->tcm_banks)
+			return -ENOMEM;
+
+		for (j = 0; j < tcm_bank_count; j++) {
+			/*
+			 * Use pre-defined TCM reg values.
+			 * Eventually this should be replaced by values
+			 * parsed from dts.
+			 */
+			r5_core->tcm_banks[j] =
+				(struct mem_bank_data *)&zynqmp_tcm_banks[tcm_node];
+			tcm_node++;
+		}
+
+		r5_core->tcm_bank_count = tcm_bank_count;
+	}
+
+	return 0;
+}
+
+/**
+ * zynqmp_r5_get_mem_region_node()
+ * parse memory-region property and get reserved mem regions
+ *
+ * @r5_core: pointer to zynqmp_r5_core type object
+ *
+ * Return: 0 for success and error code for failure.
+ */
+static int zynqmp_r5_get_mem_region_node(struct zynqmp_r5_core *r5_core)
+{
+	struct device_node *np, *rmem_np;
+	struct reserved_mem **rmem;
+	int res_mem_count, i;
+	struct device *dev;
+
+	dev = r5_core->dev;
+	np = r5_core->np;
+
+	res_mem_count = of_property_count_elems_of_size(np, "memory-region",
+							sizeof(phandle));
+	if (res_mem_count <= 0) {
+		dev_warn(dev, "failed to get memory-region property %d\n",
+			 res_mem_count);
+		return 0;
+	}
+
+	rmem = devm_kcalloc(dev, res_mem_count,
+			    sizeof(struct reserved_mem *), GFP_KERNEL);
+	if (!rmem)
+		return -ENOMEM;
+
+	for (i = 0; i < res_mem_count; i++) {
+		rmem_np = of_parse_phandle(np, "memory-region", i);
+		if (!rmem_np)
+			goto release_rmem;
+
+		rmem[i] = of_reserved_mem_lookup(rmem_np);
+		if (!rmem[i]) {
+			of_node_put(rmem_np);
+			goto release_rmem;
+		}
+
+		of_node_put(rmem_np);
+	}
+
+	r5_core->rmem_count = res_mem_count;
+	r5_core->rmem = rmem;
+	return 0;
+
+release_rmem:
+	return -EINVAL;
+}
+
+/*
+ * zynqmp_r5_core_init()
+ * Create and initialize zynqmp_r5_core type object
+ *
+ * @cluster: pointer to zynqmp_r5_cluster type object
+ * @fw_reg_val: value expected by firmware to configure RPU cluster mode
+ * @tcm_mode: value expected by fw to configure TCM mode (lockstep or split)
+ *
+ * Return: 0 for success and error code for failure.
+ */
+static int zynqmp_r5_core_init(struct zynqmp_r5_cluster *cluster,
+			       enum rpu_oper_mode fw_reg_val,
+			       enum rpu_tcm_comb tcm_mode)
+{
+	struct device *dev = cluster->dev;
+	struct zynqmp_r5_core *r5_core;
+	int ret, i;
+
+	ret = zynqmp_r5_get_tcm_node(cluster);
+	if (ret < 0) {
+		dev_err(dev, "can't get tcm node, err %d\n", ret);
+		return ret;
+	}
+
+	for (i = 0; i < cluster->core_count; i++) {
+		r5_core = cluster->r5_cores[i];
+
+		ret = zynqmp_r5_get_mem_region_node(r5_core);
+		if (ret)
+			dev_warn(dev, "memory-region prop failed %d\n", ret);
+
+		/* Initialize r5 cores with power-domains parsed from dts */
+		ret = of_property_read_u32_index(r5_core->np, "power-domains",
+						 1, &r5_core->pm_domain_id);
+		if (ret) {
+			dev_err(dev, "failed to get power-domains property\n");
+			return ret;
+		}
+
+		ret = zynqmp_r5_set_mode(r5_core, fw_reg_val, tcm_mode);
+		if (ret) {
+			dev_err(dev, "failed to set r5 cluster mode %d, err %d\n",
+				cluster->mode, ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * zynqmp_r5_cluster_init()
+ * Create and initialize zynqmp_r5_cluster type object
+ *
+ * @cluster: pointer to zynqmp_r5_cluster type object
+ *
+ * Return: 0 for success and error code for failure.
+ */
+static int zynqmp_r5_cluster_init(struct zynqmp_r5_cluster *cluster)
+{
+	enum zynqmp_r5_cluster_mode cluster_mode = LOCKSTEP_MODE;
+	struct device *dev = cluster->dev;
+	struct device_node *dev_node = dev_of_node(dev);
+	struct platform_device *child_pdev;
+	struct zynqmp_r5_core **r5_cores;
+	enum rpu_oper_mode fw_reg_val;
+	struct device **child_devs;
+	struct device_node *child;
+	enum rpu_tcm_comb tcm_mode;
+	int core_count, ret, i;
+
+	ret = of_property_read_u32(dev_node, "xlnx,cluster-mode", &cluster_mode);
+
+	/*
+	 * on success returns 0, if not defined then returns -EINVAL,
+	 * In that case, default is LOCKSTEP mode. Other than that
+	 * returns relative error code < 0.
+	 */
+	if (ret != -EINVAL && ret != 0) {
+		dev_err(dev, "Invalid xlnx,cluster-mode property\n");
+		return ret;
+	}
+
+	/*
+	 * For now driver only supports split mode and lockstep mode.
+	 * fail driver probe if either of that is not set in dts.
+	 */
+	if (cluster_mode == LOCKSTEP_MODE) {
+		tcm_mode = PM_RPU_TCM_COMB;
+		fw_reg_val = PM_RPU_MODE_LOCKSTEP;
+	} else if (cluster_mode == SPLIT_MODE) {
+		tcm_mode = PM_RPU_TCM_SPLIT;
+		fw_reg_val = PM_RPU_MODE_SPLIT;
+	} else {
+		dev_err(dev, "driver does not support cluster mode %d\n", cluster_mode);
+		return -EINVAL;
+	}
+
+	/*
+	 * Number of cores is decided by number of child nodes of
+	 * r5f subsystem node in dts. If Split mode is used in dts
+	 * 2 child nodes are expected.
+	 * In lockstep mode if two child nodes are available,
+	 * only use first child node and consider it as core0
+	 * and ignore core1 dt node.
+	 */
+	core_count = of_get_available_child_count(dev_node);
+	if (core_count == 0) {
+		dev_err(dev, "Invalid number of r5 cores %d", core_count);
+		return -EINVAL;
+	} else if (cluster_mode == SPLIT_MODE && core_count != 2) {
+		dev_err(dev, "Invalid number of r5 cores for split mode\n");
+		return -EINVAL;
+	} else if (cluster_mode == LOCKSTEP_MODE && core_count == 2) {
+		dev_warn(dev, "Only r5 core0 will be used\n");
+		core_count = 1;
+	}
+
+	child_devs = kcalloc(core_count, sizeof(struct device *), GFP_KERNEL);
+	if (!child_devs)
+		return -ENOMEM;
+
+	r5_cores = kcalloc(core_count,
+			   sizeof(struct zynqmp_r5_core *), GFP_KERNEL);
+	if (!r5_cores) {
+		kfree(child_devs);
+		return -ENOMEM;
+	}
+
+	i = 0;
+	for_each_available_child_of_node(dev_node, child) {
+		child_pdev = of_find_device_by_node(child);
+		if (!child_pdev) {
+			of_node_put(child);
+			ret = -ENODEV;
+			goto release_r5_cores;
+		}
+
+		child_devs[i] = &child_pdev->dev;
+
+		/* create and add remoteproc instance of type struct rproc */
+		r5_cores[i] = zynqmp_r5_add_rproc_core(&child_pdev->dev);
+		if (IS_ERR(r5_cores[i])) {
+			of_node_put(child);
+			ret = PTR_ERR(r5_cores[i]);
+			r5_cores[i] = NULL;
+			goto release_r5_cores;
+		}
+
+		/*
+		 * If two child nodes are available in dts in lockstep mode,
+		 * then ignore second child node.
+		 */
+		if (cluster_mode == LOCKSTEP_MODE) {
+			of_node_put(child);
+			break;
+		}
+
+		i++;
+	}
+
+	cluster->mode = cluster_mode;
+	cluster->core_count = core_count;
+	cluster->r5_cores = r5_cores;
+
+	ret = zynqmp_r5_core_init(cluster, fw_reg_val, tcm_mode);
+	if (ret < 0) {
+		dev_err(dev, "failed to init r5 core err %d\n", ret);
+		cluster->core_count = 0;
+		cluster->r5_cores = NULL;
+
+		/*
+		 * at this point rproc resources for each core are allocated.
+		 * adjust index to free resources in reverse order
+		 */
+		i = core_count - 1;
+		goto release_r5_cores;
+	}
+
+	kfree(child_devs);
+	return 0;
+
+release_r5_cores:
+	while (i >= 0) {
+		put_device(child_devs[i]);
+		if (r5_cores[i]) {
+			of_reserved_mem_device_release(r5_cores[i]->dev);
+			rproc_del(r5_cores[i]->rproc);
+			rproc_free(r5_cores[i]->rproc);
+		}
+		i--;
+	}
+	kfree(r5_cores);
+	kfree(child_devs);
+	return ret;
+}
+
+static void zynqmp_r5_cluster_exit(void *data)
+{
+	struct platform_device *pdev = (struct platform_device *)data;
+	struct zynqmp_r5_cluster *cluster;
+	struct zynqmp_r5_core *r5_core;
+	int i;
+
+	cluster = (struct zynqmp_r5_cluster *)platform_get_drvdata(pdev);
+	if (!cluster)
+		return;
+
+	for (i = 0; i < cluster->core_count; i++) {
+		r5_core = cluster->r5_cores[i];
+		of_reserved_mem_device_release(r5_core->dev);
+		put_device(r5_core->dev);
+		rproc_del(r5_core->rproc);
+		rproc_free(r5_core->rproc);
+	}
+
+	kfree(cluster->r5_cores);
+	kfree(cluster);
+	platform_set_drvdata(pdev, NULL);
+}
+
+/*
+ * zynqmp_r5_remoteproc_probe()
+ * parse device-tree, initialize hardware and allocate required resources
+ * and remoteproc ops
+ *
+ * @pdev: domain platform device for R5 cluster
+ *
+ * Return: 0 for success and < 0 for failure.
+ */
+static int zynqmp_r5_remoteproc_probe(struct platform_device *pdev)
+{
+	struct zynqmp_r5_cluster *cluster;
+	struct device *dev = &pdev->dev;
+	int ret;
+
+	cluster = kzalloc(sizeof(*cluster), GFP_KERNEL);
+	if (!cluster)
+		return -ENOMEM;
+
+	cluster->dev = dev;
+
+	ret = devm_of_platform_populate(dev);
+	if (ret) {
+		dev_err_probe(dev, ret, "failed to populate platform dev\n");
+		kfree(cluster);
+		return ret;
+	}
+
+	/* wire in so each core can be cleaned up at driver remove */
+	platform_set_drvdata(pdev, cluster);
+
+	ret = zynqmp_r5_cluster_init(cluster);
+	if (ret) {
+		kfree(cluster);
+		platform_set_drvdata(pdev, NULL);
+		dev_err_probe(dev, ret, "Invalid r5f subsystem device tree\n");
+		return ret;
+	}
+
+	ret = devm_add_action_or_reset(dev, zynqmp_r5_cluster_exit, pdev);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+/* Match table for OF platform binding */
+static const struct of_device_id zynqmp_r5_remoteproc_match[] = {
+	{ .compatible = "xlnx,zynqmp-r5fss", },
+	{ /* end of list */ },
+};
+MODULE_DEVICE_TABLE(of, zynqmp_r5_remoteproc_match);
+
+static struct platform_driver zynqmp_r5_remoteproc_driver = {
+	.probe = zynqmp_r5_remoteproc_probe,
+	.driver = {
+		.name = "zynqmp_r5_remoteproc",
+		.of_match_table = zynqmp_r5_remoteproc_match,
+	},
+};
+module_platform_driver(zynqmp_r5_remoteproc_driver);
+
+MODULE_DESCRIPTION("Xilinx R5F remote processor driver");
+MODULE_AUTHOR("Xilinx Inc.");
+MODULE_LICENSE("GPL");
-- 
GitLab


From 0c76ef3f26d5ef2ac2c21b47e7620cff35809fbb Mon Sep 17 00:00:00 2001
From: Li Huafei <lihuafei1@huawei.com>
Date: Sat, 26 Nov 2022 19:43:16 +0800
Subject: [PATCH 087/875] kprobes: Fix check for probe enabled in kill_kprobe()

In kill_kprobe(), the check whether disarm_kprobe_ftrace() needs to be
called always fails. This is because before that we set the
KPROBE_FLAG_GONE flag for kprobe so that "!kprobe_disabled(p)" is always
false.

The disarm_kprobe_ftrace() call introduced by commit:

  0cb2f1372baa ("kprobes: Fix NULL pointer dereference at kprobe_ftrace_handler")

to fix the NULL pointer reference problem. When the probe is enabled, if
we do not disarm it, this problem still exists.

Fix it by putting the probe enabled check before setting the
KPROBE_FLAG_GONE flag.

Link: https://lore.kernel.org/all/20221126114316.201857-1-lihuafei1@huawei.com/

Fixes: 3031313eb3d54 ("kprobes: Fix to check probe enabled before disarm_kprobe_ftrace()")
Signed-off-by: Li Huafei <lihuafei1@huawei.com>
Acked-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
Reviewed-by: Steven Rostedt (Google) <rostedt@goodmis.org>
Signed-off-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
---
 kernel/kprobes.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/kernel/kprobes.c b/kernel/kprobes.c
index 3050631e528d9..a35074f0daa1a 100644
--- a/kernel/kprobes.c
+++ b/kernel/kprobes.c
@@ -2364,6 +2364,14 @@ static void kill_kprobe(struct kprobe *p)
 
 	lockdep_assert_held(&kprobe_mutex);
 
+	/*
+	 * The module is going away. We should disarm the kprobe which
+	 * is using ftrace, because ftrace framework is still available at
+	 * 'MODULE_STATE_GOING' notification.
+	 */
+	if (kprobe_ftrace(p) && !kprobe_disabled(p) && !kprobes_all_disarmed)
+		disarm_kprobe_ftrace(p);
+
 	p->flags |= KPROBE_FLAG_GONE;
 	if (kprobe_aggrprobe(p)) {
 		/*
@@ -2380,14 +2388,6 @@ static void kill_kprobe(struct kprobe *p)
 	 * the original probed function (which will be freed soon) any more.
 	 */
 	arch_remove_kprobe(p);
-
-	/*
-	 * The module is going away. We should disarm the kprobe which
-	 * is using ftrace, because ftrace framework is still available at
-	 * 'MODULE_STATE_GOING' notification.
-	 */
-	if (kprobe_ftrace(p) && !kprobe_disabled(p) && !kprobes_all_disarmed)
-		disarm_kprobe_ftrace(p);
 }
 
 /* Disable one kprobe */
-- 
GitLab


From 731c47930f63883bae5de0293241f851042cbd77 Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Mon, 24 Oct 2022 21:52:11 +0100
Subject: [PATCH 088/875] pwm: jz4740: Force dependency on Device Tree
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Ingenic SoCs all require CONFIG_OF, so there is no case where we want to
use this driver without CONFIG_OF.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/Kconfig      |  2 +-
 drivers/pwm/pwm-jz4740.c | 10 ++++------
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 60d13a949bc58..1fe420a45f913 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -283,7 +283,7 @@ config PWM_IQS620A
 config PWM_JZ4740
 	tristate "Ingenic JZ47xx PWM support"
 	depends on MIPS || COMPILE_TEST
-	depends on COMMON_CLK
+	depends on COMMON_CLK && OF
 	select MFD_SYSCON
 	help
 	  Generic PWM framework driver for Ingenic JZ47xx based
diff --git a/drivers/pwm/pwm-jz4740.c b/drivers/pwm/pwm-jz4740.c
index a5fdf97c0d2ec..1a1a651c2cce9 100644
--- a/drivers/pwm/pwm-jz4740.c
+++ b/drivers/pwm/pwm-jz4740.c
@@ -248,19 +248,18 @@ static int jz4740_pwm_probe(struct platform_device *pdev)
 	return devm_pwmchip_add(dev, &jz4740->chip);
 }
 
-static const struct soc_info __maybe_unused jz4740_soc_info = {
+static const struct soc_info jz4740_soc_info = {
 	.num_pwms = 8,
 };
 
-static const struct soc_info __maybe_unused jz4725b_soc_info = {
+static const struct soc_info jz4725b_soc_info = {
 	.num_pwms = 6,
 };
 
-static const struct soc_info __maybe_unused x1000_soc_info = {
+static const struct soc_info x1000_soc_info = {
 	.num_pwms = 5,
 };
 
-#ifdef CONFIG_OF
 static const struct of_device_id jz4740_pwm_dt_ids[] = {
 	{ .compatible = "ingenic,jz4740-pwm", .data = &jz4740_soc_info },
 	{ .compatible = "ingenic,jz4725b-pwm", .data = &jz4725b_soc_info },
@@ -268,12 +267,11 @@ static const struct of_device_id jz4740_pwm_dt_ids[] = {
 	{},
 };
 MODULE_DEVICE_TABLE(of, jz4740_pwm_dt_ids);
-#endif
 
 static struct platform_driver jz4740_pwm_driver = {
 	.driver = {
 		.name = "jz4740-pwm",
-		.of_match_table = of_match_ptr(jz4740_pwm_dt_ids),
+		.of_match_table = jz4740_pwm_dt_ids,
 	},
 	.probe = jz4740_pwm_probe,
 };
-- 
GitLab


From 69ba53dac3b16a3b0aa65e7817901e67bc554b32 Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Mon, 24 Oct 2022 21:52:12 +0100
Subject: [PATCH 089/875] pwm: jz4740: Depend on MACH_INGENIC instead of MIPS
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The MACH_INGENIC Kconfig option will be selected when building a kernel
targeting Ingenic SoCs, but also when compiling a generic MIPS kernel
that happens to support Ingenic SoCs.

Therefore, if MACH_INGENIC is not set, we know that we're not even
trying to build a generic kernel that supports these SoCs, and we can
hide the options to compile the SoC-specific drivers.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 1fe420a45f913..cb623d0702f6d 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -282,7 +282,7 @@ config PWM_IQS620A
 
 config PWM_JZ4740
 	tristate "Ingenic JZ47xx PWM support"
-	depends on MIPS || COMPILE_TEST
+	depends on MACH_INGENIC || COMPILE_TEST
 	depends on COMMON_CLK && OF
 	select MFD_SYSCON
 	help
-- 
GitLab


From 7d9199995412fd30ea79e24d6c29f04a9b5d49ee Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Mon, 24 Oct 2022 21:52:13 +0100
Subject: [PATCH 090/875] pwm: jz4740: Use regmap_{set,clear}_bits
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Simplify a bit the code by using regmap_set_bits() and
regmap_clear_bits() instead of regmap_update_bits() when possible.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-jz4740.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/pwm/pwm-jz4740.c b/drivers/pwm/pwm-jz4740.c
index 1a1a651c2cce9..3b7067f6cd0dc 100644
--- a/drivers/pwm/pwm-jz4740.c
+++ b/drivers/pwm/pwm-jz4740.c
@@ -88,8 +88,7 @@ static int jz4740_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 	struct jz4740_pwm_chip *jz = to_jz4740(chip);
 
 	/* Enable PWM output */
-	regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm),
-			   TCU_TCSR_PWM_EN, TCU_TCSR_PWM_EN);
+	regmap_set_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN);
 
 	/* Start counter */
 	regmap_write(jz->map, TCU_REG_TESR, BIT(pwm->hwpwm));
@@ -113,8 +112,7 @@ static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 	 * In TCU2 mode (channel 1/2 on JZ4750+), this must be done before the
 	 * counter is stopped, while in TCU1 mode the order does not matter.
 	 */
-	regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm),
-			   TCU_TCSR_PWM_EN, 0);
+	regmap_clear_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN);
 
 	/* Stop counter */
 	regmap_write(jz->map, TCU_REG_TECR, BIT(pwm->hwpwm));
@@ -184,8 +182,8 @@ static int jz4740_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 	regmap_write(jz4740->map, TCU_REG_TDFRc(pwm->hwpwm), period);
 
 	/* Set abrupt shutdown */
-	regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
-			   TCU_TCSR_PWM_SD, TCU_TCSR_PWM_SD);
+	regmap_set_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
+			TCU_TCSR_PWM_SD);
 
 	/*
 	 * Set polarity.
-- 
GitLab


From 6456ab5d7ccd4fae6e136025480ad4ad91a7c795 Mon Sep 17 00:00:00 2001
From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Date: Sat, 26 Nov 2022 12:13:27 +0100
Subject: [PATCH 091/875] scsi: libfc: Include the correct header

This file does not use rcu, so there is no point in including
<linux/rculist.h>.

The dependency has been removed in commit fa519f701d27 ("scsi: libfc: fixup
'sleeping function called from invalid context'") It turned a
list_for_each_entry_rcu() into a list_for_each_entry().

So just #include <linux/list.h> now.

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/960f34418358f0c35e645aa2cf7e0ec7fe6b60b9.1669461197.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
---
 drivers/scsi/libfc/fc_disc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/scsi/libfc/fc_disc.c b/drivers/scsi/libfc/fc_disc.c
index 0f32ded246d0b..384f48ff64d72 100644
--- a/drivers/scsi/libfc/fc_disc.c
+++ b/drivers/scsi/libfc/fc_disc.c
@@ -24,7 +24,7 @@
 #include <linux/slab.h>
 #include <linux/err.h>
 #include <linux/export.h>
-#include <linux/rculist.h>
+#include <linux/list.h>
 
 #include <asm/unaligned.h>
 
-- 
GitLab


From 9f5436f47c58463f91bfeebcc4613138625098c2 Mon Sep 17 00:00:00 2001
From: Johannes Thumshirn <johannes.thumshirn@wdc.com>
Date: Wed, 30 Nov 2022 02:36:16 -0800
Subject: [PATCH 092/875] scsi: sd: sd_zbc: Trace zone append emulation

Add tracepoints to the SCSI zone append emulation in order to trace the
zone start to write-pointer aligned LBA translation and the corresponding
completion.

Signed-off-by: Johannes Thumshirn <johannes.thumshirn@wdc.com>
Link: https://lore.kernel.org/r/d103bcf5f90139143469f2a0084c74bd9e03ad4a.1669804487.git.johannes.thumshirn@wdc.com
Reviewed-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Jason Yan <yanaijie@huawei.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
---
 drivers/scsi/sd_trace.h | 84 +++++++++++++++++++++++++++++++++++++++++
 drivers/scsi/sd_zbc.c   |  6 +++
 2 files changed, 90 insertions(+)
 create mode 100644 drivers/scsi/sd_trace.h

diff --git a/drivers/scsi/sd_trace.h b/drivers/scsi/sd_trace.h
new file mode 100644
index 0000000000000..cba3c0b825bab
--- /dev/null
+++ b/drivers/scsi/sd_trace.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022 Western Digital Corporation or its affiliates.
+ */
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM sd
+
+#undef TRACE_INCLUDE_FILE
+#define TRACE_INCLUDE_FILE sd_trace
+
+#if !defined(_SD_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
+#include <scsi/scsi_cmnd.h>
+#include <scsi/scsi_host.h>
+#include <linux/tracepoint.h>
+
+TRACE_EVENT(scsi_prepare_zone_append,
+
+	    TP_PROTO(struct scsi_cmnd *cmnd, sector_t lba,
+		     unsigned int wp_offset),
+
+	    TP_ARGS(cmnd, lba, wp_offset),
+
+	    TP_STRUCT__entry(
+		     __field( unsigned int, host_no )
+		     __field( unsigned int, channel )
+		     __field( unsigned int, id )
+		     __field( unsigned int, lun )
+		     __field( sector_t,     lba )
+		     __field( unsigned int, wp_offset )
+	    ),
+
+	    TP_fast_assign(
+		__entry->host_no	= cmnd->device->host->host_no;
+		__entry->channel	= cmnd->device->channel;
+		__entry->id		= cmnd->device->id;
+		__entry->lun		= cmnd->device->lun;
+		__entry->lba		= lba;
+		__entry->wp_offset	= wp_offset;
+	    ),
+
+	    TP_printk("host_no=%u, channel=%u id=%u lun=%u lba=%llu wp_offset=%u",
+		      __entry->host_no, __entry->channel, __entry->id,
+		      __entry->lun, __entry->lba, __entry->wp_offset)
+);
+
+TRACE_EVENT(scsi_zone_wp_update,
+
+	    TP_PROTO(struct scsi_cmnd *cmnd, sector_t rq_sector,
+		     unsigned int wp_offset, unsigned int good_bytes),
+
+	    TP_ARGS(cmnd, rq_sector, wp_offset, good_bytes),
+
+	    TP_STRUCT__entry(
+		     __field( unsigned int, host_no )
+		     __field( unsigned int, channel )
+		     __field( unsigned int, id )
+		     __field( unsigned int, lun )
+		     __field( sector_t,     rq_sector )
+		     __field( unsigned int, wp_offset )
+		     __field( unsigned int, good_bytes )
+	    ),
+
+	    TP_fast_assign(
+		__entry->host_no	= cmnd->device->host->host_no;
+		__entry->channel	= cmnd->device->channel;
+		__entry->id		= cmnd->device->id;
+		__entry->lun		= cmnd->device->lun;
+		__entry->rq_sector	= rq_sector;
+		__entry->wp_offset	= wp_offset;
+		__entry->good_bytes	= good_bytes;
+	    ),
+
+	    TP_printk("host_no=%u, channel=%u id=%u lun=%u rq_sector=%llu" \
+		      " wp_offset=%u good_bytes=%u",
+		      __entry->host_no, __entry->channel, __entry->id,
+		      __entry->lun, __entry->rq_sector, __entry->wp_offset,
+		      __entry->good_bytes)
+);
+#endif /* _SD_TRACE_H */
+
+/* This part must be outside protection */
+#undef TRACE_INCLUDE_PATH
+#define TRACE_INCLUDE_PATH ../../drivers/scsi
+#include <trace/define_trace.h>
diff --git a/drivers/scsi/sd_zbc.c b/drivers/scsi/sd_zbc.c
index b163bf936acc7..62abebbaf2e7e 100644
--- a/drivers/scsi/sd_zbc.c
+++ b/drivers/scsi/sd_zbc.c
@@ -20,6 +20,9 @@
 
 #include "sd.h"
 
+#define CREATE_TRACE_POINTS
+#include "sd_trace.h"
+
 /**
  * sd_zbc_get_zone_wp_offset - Get zone write pointer offset.
  * @zone: Zone for which to return the write pointer offset.
@@ -450,6 +453,7 @@ blk_status_t sd_zbc_prepare_zone_append(struct scsi_cmnd *cmd, sector_t *lba,
 			break;
 		}
 
+		trace_scsi_prepare_zone_append(cmd, *lba, wp_offset);
 		*lba += wp_offset;
 	}
 	spin_unlock_irqrestore(&sdkp->zones_wp_offset_lock, flags);
@@ -558,6 +562,8 @@ static unsigned int sd_zbc_zone_wp_update(struct scsi_cmnd *cmd,
 
 	switch (op) {
 	case REQ_OP_ZONE_APPEND:
+		trace_scsi_zone_wp_update(cmd, rq->__sector,
+				  sdkp->zones_wp_offset[zno], good_bytes);
 		rq->__sector += sdkp->zones_wp_offset[zno];
 		fallthrough;
 	case REQ_OP_WRITE_ZEROES:
-- 
GitLab


From 255c4f4a6d5b60cfcd218d8fdae517b886ff155a Mon Sep 17 00:00:00 2001
From: Mike Christie <michael.christie@oracle.com>
Date: Mon, 21 Nov 2022 21:26:00 -0600
Subject: [PATCH 093/875] block: Add error codes for common PR failures

If a PR operation fails we can return a device-specific error which is
impossible to handle in some cases because we could have a mix of devices
when DM is used, or future users like LIO only knows it's interacting with
a block device so it doesn't know the type.

This patch adds a new pr_status enum so drivers can convert errors to a
common type which can be handled by the caller.

Signed-off-by: Mike Christie <michael.christie@oracle.com>
Link: https://lore.kernel.org/r/20221122032603.32766-2-michael.christie@oracle.com
Reviewed-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Chaitanya Kulkarni <kch@nvidia.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
---
 include/uapi/linux/pr.h | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/include/uapi/linux/pr.h b/include/uapi/linux/pr.h
index ccc78cbf1221b..d8126415966f3 100644
--- a/include/uapi/linux/pr.h
+++ b/include/uapi/linux/pr.h
@@ -4,6 +4,23 @@
 
 #include <linux/types.h>
 
+enum pr_status {
+	PR_STS_SUCCESS			= 0x0,
+	/*
+	 * The following error codes are based on SCSI, because the interface
+	 * was originally created for it and has existing users.
+	 */
+	/* Generic device failure. */
+	PR_STS_IOERR			= 0x2,
+	PR_STS_RESERVATION_CONFLICT	= 0x18,
+	/* Temporary path failure that can be retried. */
+	PR_STS_RETRY_PATH_FAILURE	= 0xe0000,
+	/* The request was failed due to a fast failure timer. */
+	PR_STS_PATH_FAST_FAILED		= 0xf0000,
+	/* The path cannot be reached and has been marked as failed. */
+	PR_STS_PATH_FAILED		= 0x10000,
+};
+
 enum pr_type {
 	PR_WRITE_EXCLUSIVE		= 1,
 	PR_EXCLUSIVE_ACCESS		= 2,
-- 
GitLab


From c9293c1199ecd3cfa07931ec3630f37dba1ca1b8 Mon Sep 17 00:00:00 2001
From: Mike Christie <michael.christie@oracle.com>
Date: Mon, 21 Nov 2022 21:26:01 -0600
Subject: [PATCH 094/875] scsi: core: Rename status_byte to sg_status_byte

The next patch adds a helper status_byte function that works like
host_byte, so this patch renames the old status_byte to sg_status_byte
since it's only used for SG IO.

Signed-off-by: Mike Christie <michael.christie@oracle.com>
Link: https://lore.kernel.org/r/20221122032603.32766-3-michael.christie@oracle.com
Reviewed-by: Chaitanya Kulkarni <kch@nvidia.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
---
 drivers/scsi/scsi_ioctl.c | 2 +-
 drivers/scsi/sg.c         | 2 +-
 include/scsi/sg.h         | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/scsi/scsi_ioctl.c b/drivers/scsi/scsi_ioctl.c
index fdd47565a3115..1126a265d5ee2 100644
--- a/drivers/scsi/scsi_ioctl.c
+++ b/drivers/scsi/scsi_ioctl.c
@@ -376,7 +376,7 @@ static int scsi_complete_sghdr_rq(struct request *rq, struct sg_io_hdr *hdr,
 	 * fill in all the output members
 	 */
 	hdr->status = scmd->result & 0xff;
-	hdr->masked_status = status_byte(scmd->result);
+	hdr->masked_status = sg_status_byte(scmd->result);
 	hdr->msg_status = COMMAND_COMPLETE;
 	hdr->host_status = host_byte(scmd->result);
 	hdr->driver_status = 0;
diff --git a/drivers/scsi/sg.c b/drivers/scsi/sg.c
index ce34a8ad53b4e..d61d8d0d16581 100644
--- a/drivers/scsi/sg.c
+++ b/drivers/scsi/sg.c
@@ -1349,7 +1349,7 @@ sg_rq_end_io(struct request *rq, blk_status_t status)
 		struct scsi_sense_hdr sshdr;
 
 		srp->header.status = 0xff & result;
-		srp->header.masked_status = status_byte(result);
+		srp->header.masked_status = sg_status_byte(result);
 		srp->header.msg_status = COMMAND_COMPLETE;
 		srp->header.host_status = host_byte(result);
 		srp->header.driver_status = driver_byte(result);
diff --git a/include/scsi/sg.h b/include/scsi/sg.h
index 068e35d365575..af31cecd9012a 100644
--- a/include/scsi/sg.h
+++ b/include/scsi/sg.h
@@ -159,7 +159,7 @@ struct compat_sg_io_hdr {
 #define TASK_ABORTED         0x20
 
 /* Obsolete status_byte() declaration */
-#define status_byte(result) (((result) >> 1) & 0x7f)
+#define sg_status_byte(result) (((result) >> 1) & 0x7f)
 
 typedef struct sg_scsi_id { /* used by SG_GET_SCSI_ID ioctl() */
     int host_no;        /* as in "scsi<n>" where 'n' is one of 0, 1, 2 etc */
-- 
GitLab


From 04b3c8c0025a1d91a0e133e9b2734a002960f472 Mon Sep 17 00:00:00 2001
From: Mike Christie <michael.christie@oracle.com>
Date: Mon, 21 Nov 2022 21:26:02 -0600
Subject: [PATCH 095/875] scsi: sd: Convert SCSI errors to PR errors

This converts the SCSI errors we commonly see during PR handling to PR_STS
errors or -Exyz errors. pr_ops callers can then handle SCSI and NVMe errors
without knowing the device types.

Signed-off-by: Mike Christie <michael.christie@oracle.com>
Link: https://lore.kernel.org/r/20221122032603.32766-4-michael.christie@oracle.com
Reviewed-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Chaitanya Kulkarni <kch@nvidia.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
---
 drivers/scsi/sd.c   | 35 ++++++++++++++++++++++++++++++++++-
 include/scsi/scsi.h |  1 +
 2 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/drivers/scsi/sd.c b/drivers/scsi/sd.c
index faa2b55d1a21a..47dafe6b8a66d 100644
--- a/drivers/scsi/sd.c
+++ b/drivers/scsi/sd.c
@@ -1709,6 +1709,36 @@ static char sd_pr_type(enum pr_type type)
 	}
 };
 
+static int sd_scsi_to_pr_err(struct scsi_sense_hdr *sshdr, int result)
+{
+	switch (host_byte(result)) {
+	case DID_TRANSPORT_MARGINAL:
+	case DID_TRANSPORT_DISRUPTED:
+	case DID_BUS_BUSY:
+		return PR_STS_RETRY_PATH_FAILURE;
+	case DID_NO_CONNECT:
+		return PR_STS_PATH_FAILED;
+	case DID_TRANSPORT_FAILFAST:
+		return PR_STS_PATH_FAST_FAILED;
+	}
+
+	switch (status_byte(result)) {
+	case SAM_STAT_RESERVATION_CONFLICT:
+		return PR_STS_RESERVATION_CONFLICT;
+	case SAM_STAT_CHECK_CONDITION:
+		if (!scsi_sense_valid(sshdr))
+			return PR_STS_IOERR;
+
+		if (sshdr->sense_key == ILLEGAL_REQUEST &&
+		    (sshdr->asc == 0x26 || sshdr->asc == 0x24))
+			return -EINVAL;
+
+		fallthrough;
+	default:
+		return PR_STS_IOERR;
+	}
+}
+
 static int sd_pr_command(struct block_device *bdev, u8 sa,
 		u64 key, u64 sa_key, u8 type, u8 flags)
 {
@@ -1737,7 +1767,10 @@ static int sd_pr_command(struct block_device *bdev, u8 sa,
 		scsi_print_sense_hdr(sdev, NULL, &sshdr);
 	}
 
-	return result;
+	if (result <= 0)
+		return result;
+
+	return sd_scsi_to_pr_err(&sshdr, result);
 }
 
 static int sd_pr_register(struct block_device *bdev, u64 old_key, u64 new_key,
diff --git a/include/scsi/scsi.h b/include/scsi/scsi.h
index 3e46859774c85..ec093594ba53d 100644
--- a/include/scsi/scsi.h
+++ b/include/scsi/scsi.h
@@ -121,6 +121,7 @@ enum scsi_disposition {
  *      msg_byte    (unused)
  *      host_byte   = set by low-level driver to indicate status.
  */
+#define status_byte(result) (result & 0xff)
 #define host_byte(result)   (((result) >> 16) & 0xff)
 
 #define sense_class(sense)  (((sense) >> 4) & 0x7)
-- 
GitLab


From 7fb42780d06c3417b21c3f31b6b99fd8e9ca6084 Mon Sep 17 00:00:00 2001
From: Mike Christie <michael.christie@oracle.com>
Date: Mon, 21 Nov 2022 21:26:03 -0600
Subject: [PATCH 096/875] nvme: Convert NVMe errors to PR errors

This converts the NVMe errors we commonly see during PR handling to PR_STS
errors or -Exyz errors. pr_ops callers can then handle SCSI and NVMe errors
without knowing the device types.

Signed-off-by: Mike Christie <michael.christie@oracle.com>
Link: https://lore.kernel.org/r/20221122032603.32766-5-michael.christie@oracle.com
Reviewed-by: Chaitanya Kulkarni <kch@nvidia.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
---
 drivers/nvme/host/core.c | 33 +++++++++++++++++++++++++++++++--
 1 file changed, 31 insertions(+), 2 deletions(-)

diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c
index 059737c1a2c19..5ccc9962332f5 100644
--- a/drivers/nvme/host/core.c
+++ b/drivers/nvme/host/core.c
@@ -2104,11 +2104,34 @@ static int nvme_send_ns_pr_command(struct nvme_ns *ns, struct nvme_command *c,
 	return nvme_submit_sync_cmd(ns->queue, c, data, 16);
 }
 
+static int nvme_sc_to_pr_err(int nvme_sc)
+{
+	if (nvme_is_path_error(nvme_sc))
+		return PR_STS_PATH_FAILED;
+
+	switch (nvme_sc) {
+	case NVME_SC_SUCCESS:
+		return PR_STS_SUCCESS;
+	case NVME_SC_RESERVATION_CONFLICT:
+		return PR_STS_RESERVATION_CONFLICT;
+	case NVME_SC_ONCS_NOT_SUPPORTED:
+		return -EOPNOTSUPP;
+	case NVME_SC_BAD_ATTRIBUTES:
+	case NVME_SC_INVALID_OPCODE:
+	case NVME_SC_INVALID_FIELD:
+	case NVME_SC_INVALID_NS:
+		return -EINVAL;
+	default:
+		return PR_STS_IOERR;
+	}
+}
+
 static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
 				u64 key, u64 sa_key, u8 op)
 {
 	struct nvme_command c = { };
 	u8 data[16] = { 0, };
+	int ret;
 
 	put_unaligned_le64(key, &data[0]);
 	put_unaligned_le64(sa_key, &data[8]);
@@ -2118,8 +2141,14 @@ static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
 
 	if (IS_ENABLED(CONFIG_NVME_MULTIPATH) &&
 	    bdev->bd_disk->fops == &nvme_ns_head_ops)
-		return nvme_send_ns_head_pr_command(bdev, &c, data);
-	return nvme_send_ns_pr_command(bdev->bd_disk->private_data, &c, data);
+		ret = nvme_send_ns_head_pr_command(bdev, &c, data);
+	else
+		ret = nvme_send_ns_pr_command(bdev->bd_disk->private_data, &c,
+					      data);
+	if (ret < 0)
+		return ret;
+
+	return nvme_sc_to_pr_err(ret);
 }
 
 static int nvme_pr_register(struct block_device *bdev, u64 old,
-- 
GitLab


From 68ad83188d782b2ecef2e41ac245d27e0710fe8e Mon Sep 17 00:00:00 2001
From: Arun Easi <aeasi@marvell.com>
Date: Tue, 29 Nov 2022 01:26:34 -0800
Subject: [PATCH 097/875] scsi: qla2xxx: Fix crash when I/O abort times out

While performing CPU hotplug, a crash with the following stack was seen:

Call Trace:
     qla24xx_process_response_queue+0x42a/0x970 [qla2xxx]
     qla2x00_start_nvme_mq+0x3a2/0x4b0 [qla2xxx]
     qla_nvme_post_cmd+0x166/0x240 [qla2xxx]
     nvme_fc_start_fcp_op.part.0+0x119/0x2e0 [nvme_fc]
     blk_mq_dispatch_rq_list+0x17b/0x610
     __blk_mq_sched_dispatch_requests+0xb0/0x140
     blk_mq_sched_dispatch_requests+0x30/0x60
     __blk_mq_run_hw_queue+0x35/0x90
     __blk_mq_delay_run_hw_queue+0x161/0x180
     blk_execute_rq+0xbe/0x160
     __nvme_submit_sync_cmd+0x16f/0x220 [nvme_core]
     nvmf_connect_admin_queue+0x11a/0x170 [nvme_fabrics]
     nvme_fc_create_association.cold+0x50/0x3dc [nvme_fc]
     nvme_fc_connect_ctrl_work+0x19/0x30 [nvme_fc]
     process_one_work+0x1e8/0x3c0

On abort timeout, completion was called without checking if the I/O was
already completed.

Verify that I/O and abort request are indeed outstanding before attempting
completion.

Fixes: 71c80b75ce8f ("scsi: qla2xxx: Do command completion on abort timeout")
Reported-by: Marco Patalano <mpatalan@redhat.com>
Tested-by: Marco Patalano <mpatalan@redhat.com>
Cc: stable@vger.kernel.org
Signed-off-by: Arun Easi <aeasi@marvell.com>
Signed-off-by: Nilesh Javali <njavali@marvell.com>
Link: https://lore.kernel.org/r/20221129092634.15347-1-njavali@marvell.com
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
---
 drivers/scsi/qla2xxx/qla_init.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c
index ce4c5d728407d..8d9ecabb1aac1 100644
--- a/drivers/scsi/qla2xxx/qla_init.c
+++ b/drivers/scsi/qla2xxx/qla_init.c
@@ -110,6 +110,7 @@ static void qla24xx_abort_iocb_timeout(void *data)
 	struct qla_qpair *qpair = sp->qpair;
 	u32 handle;
 	unsigned long flags;
+	int sp_found = 0, cmdsp_found = 0;
 
 	if (sp->cmd_sp)
 		ql_dbg(ql_dbg_async, sp->vha, 0x507c,
@@ -124,18 +125,21 @@ static void qla24xx_abort_iocb_timeout(void *data)
 	spin_lock_irqsave(qpair->qp_lock_ptr, flags);
 	for (handle = 1; handle < qpair->req->num_outstanding_cmds; handle++) {
 		if (sp->cmd_sp && (qpair->req->outstanding_cmds[handle] ==
-		    sp->cmd_sp))
+		    sp->cmd_sp)) {
 			qpair->req->outstanding_cmds[handle] = NULL;
+			cmdsp_found = 1;
+		}
 
 		/* removing the abort */
 		if (qpair->req->outstanding_cmds[handle] == sp) {
 			qpair->req->outstanding_cmds[handle] = NULL;
+			sp_found = 1;
 			break;
 		}
 	}
 	spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
 
-	if (sp->cmd_sp) {
+	if (cmdsp_found && sp->cmd_sp) {
 		/*
 		 * This done function should take care of
 		 * original command ref: INIT
@@ -143,8 +147,10 @@ static void qla24xx_abort_iocb_timeout(void *data)
 		sp->cmd_sp->done(sp->cmd_sp, QLA_OS_TIMER_EXPIRED);
 	}
 
-	abt->u.abt.comp_status = cpu_to_le16(CS_TIMEOUT);
-	sp->done(sp, QLA_OS_TIMER_EXPIRED);
+	if (sp_found) {
+		abt->u.abt.comp_status = cpu_to_le16(CS_TIMEOUT);
+		sp->done(sp, QLA_OS_TIMER_EXPIRED);
+	}
 }
 
 static void qla24xx_abort_sp_done(srb_t *sp, int res)
-- 
GitLab


From 6e0149a55379d6b91948cf6e94e700eb7dbaa518 Mon Sep 17 00:00:00 2001
From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Date: Sun, 27 Nov 2022 13:59:25 +0100
Subject: [PATCH 098/875] 9p/fs: Remove unneeded idr.h #include

The 9p fs does not use IDR or IDA functionalities. So there is no point in
including <linux/idr.h>.
Remove it.

Link: https://lkml.kernel.org/r/3d1e0ed9714eaee7e18d9f5b0b4bfa49b00b286d.1669553950.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Reviewed-by: Christian Schoenebeck <linux_oss@crudebyte.com>
[Dominique: reword subject]
Signed-off-by: Dominique Martinet <asmadeus@codewreck.org>
---
 fs/9p/fid.c            | 1 -
 fs/9p/v9fs.c           | 1 -
 fs/9p/vfs_addr.c       | 1 -
 fs/9p/vfs_dentry.c     | 1 -
 fs/9p/vfs_dir.c        | 1 -
 fs/9p/vfs_file.c       | 1 -
 fs/9p/vfs_inode.c      | 1 -
 fs/9p/vfs_inode_dotl.c | 1 -
 fs/9p/vfs_super.c      | 1 -
 9 files changed, 9 deletions(-)

diff --git a/fs/9p/fid.c b/fs/9p/fid.c
index 23cf9b2fbfe43..805151114e961 100644
--- a/fs/9p/fid.c
+++ b/fs/9p/fid.c
@@ -11,7 +11,6 @@
 #include <linux/fs.h>
 #include <linux/slab.h>
 #include <linux/sched.h>
-#include <linux/idr.h>
 #include <net/9p/9p.h>
 #include <net/9p/client.h>
 
diff --git a/fs/9p/v9fs.c b/fs/9p/v9fs.c
index 0129de2ea31ae..3a9c4517265fa 100644
--- a/fs/9p/v9fs.c
+++ b/fs/9p/v9fs.c
@@ -14,7 +14,6 @@
 #include <linux/sched.h>
 #include <linux/cred.h>
 #include <linux/parser.h>
-#include <linux/idr.h>
 #include <linux/slab.h>
 #include <linux/seq_file.h>
 #include <net/9p/9p.h>
diff --git a/fs/9p/vfs_addr.c b/fs/9p/vfs_addr.c
index 47b9a1122f344..93373486ab043 100644
--- a/fs/9p/vfs_addr.c
+++ b/fs/9p/vfs_addr.c
@@ -14,7 +14,6 @@
 #include <linux/string.h>
 #include <linux/inet.h>
 #include <linux/pagemap.h>
-#include <linux/idr.h>
 #include <linux/sched.h>
 #include <linux/swap.h>
 #include <linux/uio.h>
diff --git a/fs/9p/vfs_dentry.c b/fs/9p/vfs_dentry.c
index f89f01734587b..65fa2df5e49b7 100644
--- a/fs/9p/vfs_dentry.c
+++ b/fs/9p/vfs_dentry.c
@@ -15,7 +15,6 @@
 #include <linux/string.h>
 #include <linux/inet.h>
 #include <linux/namei.h>
-#include <linux/idr.h>
 #include <linux/sched.h>
 #include <linux/slab.h>
 #include <net/9p/9p.h>
diff --git a/fs/9p/vfs_dir.c b/fs/9p/vfs_dir.c
index 000fbaae9b180..1675a196c2ba7 100644
--- a/fs/9p/vfs_dir.c
+++ b/fs/9p/vfs_dir.c
@@ -14,7 +14,6 @@
 #include <linux/string.h>
 #include <linux/sched.h>
 #include <linux/inet.h>
-#include <linux/idr.h>
 #include <linux/slab.h>
 #include <linux/uio.h>
 #include <linux/fscache.h>
diff --git a/fs/9p/vfs_file.c b/fs/9p/vfs_file.c
index aec43ba837992..b740017634ef1 100644
--- a/fs/9p/vfs_file.c
+++ b/fs/9p/vfs_file.c
@@ -18,7 +18,6 @@
 #include <linux/pagemap.h>
 #include <linux/utsname.h>
 #include <linux/uaccess.h>
-#include <linux/idr.h>
 #include <linux/uio.h>
 #include <linux/slab.h>
 #include <net/9p/9p.h>
diff --git a/fs/9p/vfs_inode.c b/fs/9p/vfs_inode.c
index 4d1a4a8d92772..27a04a226d973 100644
--- a/fs/9p/vfs_inode.c
+++ b/fs/9p/vfs_inode.c
@@ -17,7 +17,6 @@
 #include <linux/string.h>
 #include <linux/inet.h>
 #include <linux/namei.h>
-#include <linux/idr.h>
 #include <linux/sched.h>
 #include <linux/slab.h>
 #include <linux/xattr.h>
diff --git a/fs/9p/vfs_inode_dotl.c b/fs/9p/vfs_inode_dotl.c
index 5cfa4b4f070f4..8696e8899c270 100644
--- a/fs/9p/vfs_inode_dotl.c
+++ b/fs/9p/vfs_inode_dotl.c
@@ -15,7 +15,6 @@
 #include <linux/string.h>
 #include <linux/inet.h>
 #include <linux/namei.h>
-#include <linux/idr.h>
 #include <linux/sched.h>
 #include <linux/slab.h>
 #include <linux/xattr.h>
diff --git a/fs/9p/vfs_super.c b/fs/9p/vfs_super.c
index 2d9ee073d12c3..266c4693e20c5 100644
--- a/fs/9p/vfs_super.c
+++ b/fs/9p/vfs_super.c
@@ -15,7 +15,6 @@
 #include <linux/inet.h>
 #include <linux/pagemap.h>
 #include <linux/mount.h>
-#include <linux/idr.h>
 #include <linux/sched.h>
 #include <linux/slab.h>
 #include <linux/statfs.h>
-- 
GitLab


From 31fff92c9cadbca4cd294bcdff285ca3fc9bad7c Mon Sep 17 00:00:00 2001
From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Date: Sun, 27 Nov 2022 15:46:45 +0100
Subject: [PATCH 099/875] 9p/net: Remove unneeded idr.h #include

The 9p net files don't use IDR or IDA functionalities. So there is no point
in including <linux/idr.h>.
Remove it.

Link: https://lkml.kernel.org/r/9e386018601d7e4a9e5d7da8fc3e9555ebb25c87.1669560387.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Reviewed-by: Christian Schoenebeck <linux_oss@crudebyte.com>
Signed-off-by: Dominique Martinet <asmadeus@codewreck.org>
---
 net/9p/trans_fd.c     | 1 -
 net/9p/trans_rdma.c   | 1 -
 net/9p/trans_virtio.c | 1 -
 3 files changed, 3 deletions(-)

diff --git a/net/9p/trans_fd.c b/net/9p/trans_fd.c
index eeea0a6a75b68..06ec9f7d3318c 100644
--- a/net/9p/trans_fd.c
+++ b/net/9p/trans_fd.c
@@ -20,7 +20,6 @@
 #include <linux/un.h>
 #include <linux/uaccess.h>
 #include <linux/inet.h>
-#include <linux/idr.h>
 #include <linux/file.h>
 #include <linux/parser.h>
 #include <linux/slab.h>
diff --git a/net/9p/trans_rdma.c b/net/9p/trans_rdma.c
index 6ff706760676e..33a9ac6f2d552 100644
--- a/net/9p/trans_rdma.c
+++ b/net/9p/trans_rdma.c
@@ -21,7 +21,6 @@
 #include <linux/un.h>
 #include <linux/uaccess.h>
 #include <linux/inet.h>
-#include <linux/idr.h>
 #include <linux/file.h>
 #include <linux/parser.h>
 #include <linux/semaphore.h>
diff --git a/net/9p/trans_virtio.c b/net/9p/trans_virtio.c
index e757f06013043..19bccfa0d593e 100644
--- a/net/9p/trans_virtio.c
+++ b/net/9p/trans_virtio.c
@@ -22,7 +22,6 @@
 #include <linux/un.h>
 #include <linux/uaccess.h>
 #include <linux/inet.h>
-#include <linux/idr.h>
 #include <linux/file.h>
 #include <linux/highmem.h>
 #include <linux/slab.h>
-- 
GitLab


From 26273ade77f54716e30dfd40ac6e85ceb54ac0f9 Mon Sep 17 00:00:00 2001
From: Schspa Shi <schspa@gmail.com>
Date: Thu, 1 Dec 2022 11:33:10 +0800
Subject: [PATCH 100/875] 9p: set req refcount to zero to avoid uninitialized
 usage

When a new request is allocated, the refcount will be zero if it is
reused, but if the request is newly allocated from slab, it is not fully
initialized before being added to idr.

If the p9_read_work got a response before the refcount initiated. It will
use a uninitialized req, which will result in a bad request data struct.

Here is the logs from syzbot.

Corrupted memory at 0xffff88807eade00b [ 0xff 0x07 0x00 0x00 0x00 0x00
0x00 0x00 . . . . . . . . ] (in kfence-#110):
 p9_fcall_fini net/9p/client.c:248 [inline]
 p9_req_put net/9p/client.c:396 [inline]
 p9_req_put+0x208/0x250 net/9p/client.c:390
 p9_client_walk+0x247/0x540 net/9p/client.c:1165
 clone_fid fs/9p/fid.h:21 [inline]
 v9fs_fid_xattr_set+0xe4/0x2b0 fs/9p/xattr.c:118
 v9fs_xattr_set fs/9p/xattr.c:100 [inline]
 v9fs_xattr_handler_set+0x6f/0x120 fs/9p/xattr.c:159
 __vfs_setxattr+0x119/0x180 fs/xattr.c:182
 __vfs_setxattr_noperm+0x129/0x5f0 fs/xattr.c:216
 __vfs_setxattr_locked+0x1d3/0x260 fs/xattr.c:277
 vfs_setxattr+0x143/0x340 fs/xattr.c:309
 setxattr+0x146/0x160 fs/xattr.c:617
 path_setxattr+0x197/0x1c0 fs/xattr.c:636
 __do_sys_setxattr fs/xattr.c:652 [inline]
 __se_sys_setxattr fs/xattr.c:648 [inline]
 __ia32_sys_setxattr+0xc0/0x160 fs/xattr.c:648
 do_syscall_32_irqs_on arch/x86/entry/common.c:112 [inline]
 __do_fast_syscall_32+0x65/0xf0 arch/x86/entry/common.c:178
 do_fast_syscall_32+0x33/0x70 arch/x86/entry/common.c:203
 entry_SYSENTER_compat_after_hwframe+0x70/0x82

Below is a similar scenario, the scenario in the syzbot log looks more
complicated than this one, but this patch can fix it.

     T21124                   p9_read_work
======================== second trans =================================
p9_client_walk
  p9_client_rpc
    p9_client_prepare_req
      p9_tag_alloc
        req = kmem_cache_alloc(p9_req_cache, GFP_NOFS);
        tag = idr_alloc
        << preempted >>
        req->tc.tag = tag;
                            /* req->[refcount/tag] == uninitialized */
                            m->rreq = p9_tag_lookup(m->client, m->rc.tag);
                              /* increments uninitalized refcount */

        refcount_set(&req->refcount, 2);
                            /* cb drops one ref */
                            p9_client_cb(req)
                            /* reader thread drops its ref:
                               request is incorrectly freed */
                            p9_req_put(req)
    /* use after free and ref underflow */
    p9_req_put(req)

To fix it, we can initialize the refcount to zero before add to idr.

Link: https://lkml.kernel.org/r/20221201033310.18589-1-schspa@gmail.com
Cc: stable@vger.kernel.org # 6.0+ due to 6cda12864cb0 ("9p: Drop kref usage")
Fixes: 728356dedeff ("9p: Add refcount to p9_req_t")
Reported-by: syzbot+8f1060e2aaf8ca55220b@syzkaller.appspotmail.com
Signed-off-by: Schspa Shi <schspa@gmail.com>
Reviewed-by: Christian Schoenebeck <linux_oss@crudebyte.com>
Signed-off-by: Dominique Martinet <asmadeus@codewreck.org>
---
 net/9p/client.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/net/9p/client.c b/net/9p/client.c
index aaa37b07e30a5..b554f8357f967 100644
--- a/net/9p/client.c
+++ b/net/9p/client.c
@@ -297,6 +297,11 @@ p9_tag_alloc(struct p9_client *c, int8_t type, uint t_size, uint r_size,
 	p9pdu_reset(&req->rc);
 	req->t_err = 0;
 	req->status = REQ_STATUS_ALLOC;
+	/* refcount needs to be set to 0 before inserting into the idr
+	 * so p9_tag_lookup does not accept a request that is not fully
+	 * initialized. refcount_set to 2 below will mark request ready.
+	 */
+	refcount_set(&req->refcount, 0);
 	init_waitqueue_head(&req->wq);
 	INIT_LIST_HEAD(&req->req_list);
 
-- 
GitLab


From f15e006b831384aaec4b4f13265c0dff88ef09dd Mon Sep 17 00:00:00 2001
From: Dominique Martinet <asmadeus@codewreck.org>
Date: Tue, 22 Nov 2022 09:06:56 +0900
Subject: [PATCH 101/875] 9p/xen: do not memcpy header into req->rc

while 'h' is packed and can be assumed to match the request payload,
req->rc is a struct p9_fcall which is not packed and that memcpy
could be wrong.

Fix this by copying each fields individually instead.

Reported-by: Christian Schoenebeck <linux_oss@crudebyte.com>
Reviewed-by: Christian Schoenebeck <linux_oss@crudebyte.com>
Suggested-by: Stefano Stabellini <sstabellini@kernel.org>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Link: https://lkml.kernel.org/r/alpine.DEB.2.22.394.2211211454540.1049131@ubuntu-linux-20-04-desktop
Link: https://lkml.kernel.org/r/20221122001025.119121-1-asmadeus@codewreck.org
Signed-off-by: Dominique Martinet <asmadeus@codewreck.org>
---
 net/9p/trans_xen.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/net/9p/trans_xen.c b/net/9p/trans_xen.c
index aaa5fd364691b..de2d2ca8819a1 100644
--- a/net/9p/trans_xen.c
+++ b/net/9p/trans_xen.c
@@ -216,7 +216,9 @@ static void p9_xen_response(struct work_struct *work)
 			goto recv_error;
 		}
 
-		memcpy(&req->rc, &h, sizeof(h));
+		req->rc.size = h.size;
+		req->rc.id = h.id;
+		req->rc.tag = h.tag;
 		req->rc.offset = 0;
 
 		masked_cons = xen_9pfs_mask(cons, XEN_9PFS_RING_SIZE(ring));
-- 
GitLab


From 97d73d978271ade27fc751ad606f23c1c4c43678 Mon Sep 17 00:00:00 2001
From: Cezary Rojewski <cezary.rojewski@intel.com>
Date: Fri, 2 Dec 2022 16:28:26 +0100
Subject: [PATCH 102/875] ALSA: hda: Allow for compress stream to
 hdac_ext_stream assignment

Currently only PCM streams can enlist hdac_stream for their data
transfer. Add cstream field to hdac_ext_stream to expose possibility of
compress stream assignment in place of PCM one.
Limited to HOST-type only as there no other users on the horizon.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Acked-by: Takashi Iwai <tiwai@suse.de>
Link: https://lore.kernel.org/r/20221202152841.672536-2-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 include/sound/hdaudio_ext.h     |  2 ++
 sound/hda/ext/hdac_ext_stream.c | 41 +++++++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/include/sound/hdaudio_ext.h b/include/sound/hdaudio_ext.h
index 68ab89211de28..511211f4a2b66 100644
--- a/include/sound/hdaudio_ext.h
+++ b/include/sound/hdaudio_ext.h
@@ -75,6 +75,8 @@ struct hdac_ext_stream *snd_hdac_ext_stream_assign(struct hdac_bus *bus,
 					   struct snd_pcm_substream *substream,
 					   int type);
 void snd_hdac_ext_stream_release(struct hdac_ext_stream *hext_stream, int type);
+struct hdac_ext_stream *snd_hdac_ext_cstream_assign(struct hdac_bus *bus,
+						    struct snd_compr_stream *cstream);
 void snd_hdac_ext_stream_decouple_locked(struct hdac_bus *bus,
 					 struct hdac_ext_stream *hext_stream, bool decouple);
 void snd_hdac_ext_stream_decouple(struct hdac_bus *bus,
diff --git a/sound/hda/ext/hdac_ext_stream.c b/sound/hda/ext/hdac_ext_stream.c
index 2a071a09224de..11b7119cc47e6 100644
--- a/sound/hda/ext/hdac_ext_stream.c
+++ b/sound/hda/ext/hdac_ext_stream.c
@@ -14,6 +14,7 @@
 #include <sound/pcm.h>
 #include <sound/hda_register.h>
 #include <sound/hdaudio_ext.h>
+#include <sound/compress_driver.h>
 
 /**
  * snd_hdac_ext_stream_init - initialize each stream (aka device)
@@ -367,3 +368,43 @@ void snd_hdac_ext_stream_release(struct hdac_ext_stream *hext_stream, int type)
 
 }
 EXPORT_SYMBOL_GPL(snd_hdac_ext_stream_release);
+
+/**
+ * snd_hdac_ext_cstream_assign - assign a host stream for compress
+ * @bus: HD-audio core bus
+ * @cstream: Compress stream to assign
+ *
+ * Assign an unused host stream for the given compress stream.
+ * If no stream is free, NULL is returned. Stream is decoupled
+ * before assignment.
+ */
+struct hdac_ext_stream *snd_hdac_ext_cstream_assign(struct hdac_bus *bus,
+						    struct snd_compr_stream *cstream)
+{
+	struct hdac_ext_stream *res = NULL;
+	struct hdac_stream *hstream;
+
+	spin_lock_irq(&bus->reg_lock);
+	list_for_each_entry(hstream, &bus->stream_list, list) {
+		struct hdac_ext_stream *hext_stream = stream_to_hdac_ext_stream(hstream);
+
+		if (hstream->direction != cstream->direction)
+			continue;
+
+		if (!hstream->opened) {
+			res = hext_stream;
+			break;
+		}
+	}
+
+	if (res) {
+		snd_hdac_ext_stream_decouple_locked(bus, res, true);
+		res->hstream.opened = 1;
+		res->hstream.running = 0;
+		res->hstream.cstream = cstream;
+	}
+	spin_unlock_irq(&bus->reg_lock);
+
+	return res;
+}
+EXPORT_SYMBOL_GPL(snd_hdac_ext_cstream_assign);
-- 
GitLab


From f6b1254664a0a15c8bbe0a17b2c86840aa38d3d7 Mon Sep 17 00:00:00 2001
From: Cezary Rojewski <cezary.rojewski@intel.com>
Date: Fri, 2 Dec 2022 16:28:27 +0100
Subject: [PATCH 103/875] ALSA: hda: Prepare for compress stream support

Before introducing compress specific changes, adjust BDL and parameters
setup functions so these are not tightly coupled with PCM streams.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Acked-by: Takashi Iwai <tiwai@suse.de>
Link: https://lore.kernel.org/r/20221202152841.672536-3-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/hda/hdac_stream.c | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/sound/hda/hdac_stream.c b/sound/hda/hdac_stream.c
index 3b250ee7f6a7b..8a12c63479148 100644
--- a/sound/hda/hdac_stream.c
+++ b/sound/hda/hdac_stream.c
@@ -487,11 +487,15 @@ int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
 {
 	struct hdac_bus *bus = azx_dev->bus;
 	struct snd_pcm_substream *substream = azx_dev->substream;
-	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct snd_pcm_runtime *runtime;
+	struct snd_dma_buffer *dmab;
 	__le32 *bdl;
 	int i, ofs, periods, period_bytes;
 	int pos_adj, pos_align;
 
+	runtime = substream->runtime;
+	dmab = snd_pcm_get_dma_buf(substream);
+
 	/* reset BDL address */
 	snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 	snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
@@ -505,7 +509,7 @@ int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
 	azx_dev->frags = 0;
 
 	pos_adj = bus->bdl_pos_adj;
-	if (!azx_dev->no_period_wakeup && pos_adj > 0) {
+	if (runtime && !azx_dev->no_period_wakeup && pos_adj > 0) {
 		pos_align = pos_adj;
 		pos_adj = DIV_ROUND_UP(pos_adj * runtime->rate, 48000);
 		if (!pos_adj)
@@ -518,8 +522,7 @@ int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
 				 pos_adj);
 			pos_adj = 0;
 		} else {
-			ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
-					 azx_dev,
+			ofs = setup_bdle(bus, dmab, azx_dev,
 					 &bdl, ofs, pos_adj, true);
 			if (ofs < 0)
 				goto error;
@@ -529,13 +532,11 @@ int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
 
 	for (i = 0; i < periods; i++) {
 		if (i == periods - 1 && pos_adj)
-			ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
-					 azx_dev, &bdl, ofs,
-					 period_bytes - pos_adj, 0);
+			ofs = setup_bdle(bus, dmab, azx_dev,
+					 &bdl, ofs, period_bytes - pos_adj, 0);
 		else
-			ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
-					 azx_dev, &bdl, ofs,
-					 period_bytes,
+			ofs = setup_bdle(bus, dmab, azx_dev,
+					 &bdl, ofs, period_bytes,
 					 !azx_dev->no_period_wakeup);
 		if (ofs < 0)
 			goto error;
@@ -560,26 +561,25 @@ EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
 				 unsigned int format_val)
 {
-
-	unsigned int bufsize, period_bytes;
 	struct snd_pcm_substream *substream = azx_dev->substream;
-	struct snd_pcm_runtime *runtime;
+	unsigned int bufsize, period_bytes;
+	unsigned int no_period_wakeup;
 	int err;
 
 	if (!substream)
 		return -EINVAL;
-	runtime = substream->runtime;
 	bufsize = snd_pcm_lib_buffer_bytes(substream);
 	period_bytes = snd_pcm_lib_period_bytes(substream);
+	no_period_wakeup = substream->runtime->no_period_wakeup;
 
 	if (bufsize != azx_dev->bufsize ||
 	    period_bytes != azx_dev->period_bytes ||
 	    format_val != azx_dev->format_val ||
-	    runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
+	    no_period_wakeup != azx_dev->no_period_wakeup) {
 		azx_dev->bufsize = bufsize;
 		azx_dev->period_bytes = period_bytes;
 		azx_dev->format_val = format_val;
-		azx_dev->no_period_wakeup = runtime->no_period_wakeup;
+		azx_dev->no_period_wakeup = no_period_wakeup;
 		err = snd_hdac_stream_setup_periods(azx_dev);
 		if (err < 0)
 			return err;
-- 
GitLab


From 3e9582267e3a06bfd9622dbd2304a8cfac977b43 Mon Sep 17 00:00:00 2001
From: Cezary Rojewski <cezary.rojewski@intel.com>
Date: Fri, 2 Dec 2022 16:28:28 +0100
Subject: [PATCH 104/875] ALSA: hda: Interrupt servicing and BDL setup for
 compress streams

Account for compress streams when receiving and servicing buffer
completed interrupts. In case of compress stream enlisting hdac_stream
for data transfer, setup BDL entries much like it is the case for PCM
streams.

Signed-off-by: Divya Prakash <divya1.prakash@intel.com>
Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Acked-by: Takashi Iwai <tiwai@suse.de>
Link: https://lore.kernel.org/r/20221202152841.672536-4-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/hda/hdac_controller.c |  4 ++--
 sound/hda/hdac_stream.c     | 27 ++++++++++++++++++++-------
 2 files changed, 22 insertions(+), 9 deletions(-)

diff --git a/sound/hda/hdac_controller.c b/sound/hda/hdac_controller.c
index 9a60bfdb39bac..3c7af65582491 100644
--- a/sound/hda/hdac_controller.c
+++ b/sound/hda/hdac_controller.c
@@ -578,8 +578,8 @@ int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
 			sd_status = snd_hdac_stream_readb(azx_dev, SD_STS);
 			snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
 			handled |= 1 << azx_dev->index;
-			if (!azx_dev->substream || !azx_dev->running ||
-			    !(sd_status & SD_INT_COMPLETE))
+			if ((!azx_dev->substream && !azx_dev->cstream) ||
+			    !azx_dev->running || !(sd_status & SD_INT_COMPLETE))
 				continue;
 			if (ack)
 				ack(bus, azx_dev);
diff --git a/sound/hda/hdac_stream.c b/sound/hda/hdac_stream.c
index 8a12c63479148..8f625402505f8 100644
--- a/sound/hda/hdac_stream.c
+++ b/sound/hda/hdac_stream.c
@@ -7,6 +7,7 @@
 #include <linux/delay.h>
 #include <linux/export.h>
 #include <linux/clocksource.h>
+#include <sound/compress_driver.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
 #include <sound/hdaudio.h>
@@ -487,14 +488,19 @@ int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
 {
 	struct hdac_bus *bus = azx_dev->bus;
 	struct snd_pcm_substream *substream = azx_dev->substream;
-	struct snd_pcm_runtime *runtime;
+	struct snd_compr_stream *cstream = azx_dev->cstream;
+	struct snd_pcm_runtime *runtime = NULL;
 	struct snd_dma_buffer *dmab;
 	__le32 *bdl;
 	int i, ofs, periods, period_bytes;
 	int pos_adj, pos_align;
 
-	runtime = substream->runtime;
-	dmab = snd_pcm_get_dma_buf(substream);
+	if (substream) {
+		runtime = substream->runtime;
+		dmab = snd_pcm_get_dma_buf(substream);
+	} else if (cstream) {
+		dmab = snd_pcm_get_dma_buf(cstream);
+	}
 
 	/* reset BDL address */
 	snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
@@ -562,15 +568,22 @@ int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
 				 unsigned int format_val)
 {
 	struct snd_pcm_substream *substream = azx_dev->substream;
+	struct snd_compr_stream *cstream = azx_dev->cstream;
 	unsigned int bufsize, period_bytes;
 	unsigned int no_period_wakeup;
 	int err;
 
-	if (!substream)
+	if (substream) {
+		bufsize = snd_pcm_lib_buffer_bytes(substream);
+		period_bytes = snd_pcm_lib_period_bytes(substream);
+		no_period_wakeup = substream->runtime->no_period_wakeup;
+	} else if (cstream) {
+		bufsize = cstream->runtime->buffer_size;
+		period_bytes = cstream->runtime->fragment_size;
+		no_period_wakeup = 0;
+	} else {
 		return -EINVAL;
-	bufsize = snd_pcm_lib_buffer_bytes(substream);
-	period_bytes = snd_pcm_lib_period_bytes(substream);
-	no_period_wakeup = substream->runtime->no_period_wakeup;
+	}
 
 	if (bufsize != azx_dev->bufsize ||
 	    period_bytes != azx_dev->period_bytes ||
-- 
GitLab


From bb03099bf2253fcd1a4d57e6f5ee4e8000911e77 Mon Sep 17 00:00:00 2001
From: Cezary Rojewski <cezary.rojewski@intel.com>
Date: Fri, 2 Dec 2022 16:28:29 +0100
Subject: [PATCH 105/875] ASoC: Intel: avs: Introduce
 avs_log_buffer_status_locked()

Simplify locking of firmware log gathering by providing single location
for such purpose.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20221202152841.672536-5-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/avs/apl.c |  5 +----
 sound/soc/intel/avs/avs.h | 12 ++++++++++++
 sound/soc/intel/avs/ipc.c |  2 +-
 sound/soc/intel/avs/skl.c |  7 +------
 4 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/sound/soc/intel/avs/apl.c b/sound/soc/intel/avs/apl.c
index 7c8ce98eda9dd..821d5a9ad25fc 100644
--- a/sound/soc/intel/avs/apl.c
+++ b/sound/soc/intel/avs/apl.c
@@ -50,7 +50,6 @@ static int apl_enable_logs(struct avs_dev *adev, enum avs_log_enable enable, u32
 static int apl_log_buffer_status(struct avs_dev *adev, union avs_notify_msg *msg)
 {
 	struct apl_log_buffer_layout layout;
-	unsigned long flags;
 	void __iomem *addr, *buf;
 
 	addr = avs_log_buffer_addr(adev, msg->log.core);
@@ -59,7 +58,6 @@ static int apl_log_buffer_status(struct avs_dev *adev, union avs_notify_msg *msg
 
 	memcpy_fromio(&layout, addr, sizeof(layout));
 
-	spin_lock_irqsave(&adev->dbg.trace_lock, flags);
 	if (!kfifo_initialized(&adev->dbg.trace_fifo))
 		/* consume the logs regardless of consumer presence */
 		goto update_read_ptr;
@@ -78,7 +76,6 @@ static int apl_log_buffer_status(struct avs_dev *adev, union avs_notify_msg *msg
 	wake_up(&adev->dbg.trace_waitq);
 
 update_read_ptr:
-	spin_unlock_irqrestore(&adev->dbg.trace_lock, flags);
 	writel(layout.write_ptr, addr);
 	return 0;
 }
@@ -140,7 +137,7 @@ static int apl_coredump(struct avs_dev *adev, union avs_notify_msg *msg)
 		 * gathered before dumping stack
 		 */
 		lbs_msg.log.core = msg->ext.coredump.core_id;
-		avs_dsp_op(adev, log_buffer_status, &lbs_msg);
+		avs_log_buffer_status_locked(adev, &lbs_msg);
 	}
 
 	pos = dump + AVS_FW_REGS_SIZE;
diff --git a/sound/soc/intel/avs/avs.h b/sound/soc/intel/avs/avs.h
index 8d05b27608fe5..1c89af6240d28 100644
--- a/sound/soc/intel/avs/avs.h
+++ b/sound/soc/intel/avs/avs.h
@@ -344,6 +344,18 @@ unsigned int __kfifo_fromio_locked(struct kfifo *fifo, const void __iomem *src,
 			 (avs_sram_addr(adev, AVS_DEBUG_WINDOW) + __offset); \
 })
 
+static inline int avs_log_buffer_status_locked(struct avs_dev *adev, union avs_notify_msg *msg)
+{
+	unsigned long flags;
+	int ret;
+
+	spin_lock_irqsave(&adev->dbg.trace_lock, flags);
+	ret = avs_dsp_op(adev, log_buffer_status, msg);
+	spin_unlock_irqrestore(&adev->dbg.trace_lock, flags);
+
+	return ret;
+}
+
 struct apl_log_buffer_layout {
 	u32 read_ptr;
 	u32 write_ptr;
diff --git a/sound/soc/intel/avs/ipc.c b/sound/soc/intel/avs/ipc.c
index af8a260093f4c..bdf013c3dd12e 100644
--- a/sound/soc/intel/avs/ipc.c
+++ b/sound/soc/intel/avs/ipc.c
@@ -266,7 +266,7 @@ static void avs_dsp_process_notification(struct avs_dev *adev, u64 header)
 		break;
 
 	case AVS_NOTIFY_LOG_BUFFER_STATUS:
-		avs_dsp_op(adev, log_buffer_status, &msg);
+		avs_log_buffer_status_locked(adev, &msg);
 		break;
 
 	case AVS_NOTIFY_EXCEPTION_CAUGHT:
diff --git a/sound/soc/intel/avs/skl.c b/sound/soc/intel/avs/skl.c
index dc98b5cf900f2..ff690e99d9601 100644
--- a/sound/soc/intel/avs/skl.c
+++ b/sound/soc/intel/avs/skl.c
@@ -55,15 +55,11 @@ int skl_log_buffer_offset(struct avs_dev *adev, u32 core)
 static int
 skl_log_buffer_status(struct avs_dev *adev, union avs_notify_msg *msg)
 {
-	unsigned long flags;
 	void __iomem *buf;
 	u16 size, write, offset;
 
-	spin_lock_irqsave(&adev->dbg.trace_lock, flags);
-	if (!kfifo_initialized(&adev->dbg.trace_fifo)) {
-		spin_unlock_irqrestore(&adev->dbg.trace_lock, flags);
+	if (!kfifo_initialized(&adev->dbg.trace_fifo))
 		return 0;
-	}
 
 	size = avs_log_buffer_size(adev) / 2;
 	write = readl(avs_sram_addr(adev, AVS_FW_REGS_WINDOW) + FW_REGS_DBG_LOG_WP(msg->log.core));
@@ -74,7 +70,6 @@ skl_log_buffer_status(struct avs_dev *adev, union avs_notify_msg *msg)
 	buf = avs_log_buffer_addr(adev, msg->log.core) + offset;
 	__kfifo_fromio_locked(&adev->dbg.trace_fifo, buf, size, &adev->dbg.fifo_lock);
 	wake_up(&adev->dbg.trace_waitq);
-	spin_unlock_irqrestore(&adev->dbg.trace_lock, flags);
 
 	return 0;
 }
-- 
GitLab


From 58029b7734ec84738aeb8fb391e625832bb6b0a6 Mon Sep 17 00:00:00 2001
From: Cezary Rojewski <cezary.rojewski@intel.com>
Date: Fri, 2 Dec 2022 16:28:30 +0100
Subject: [PATCH 106/875] ASoC: Intel: avs: Drop fifo_lock

Log gathering is already locked, thanks to ->trace_lock.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20221202152841.672536-6-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/avs/apl.c   | 9 ++++-----
 sound/soc/intel/avs/avs.h   | 4 +---
 sound/soc/intel/avs/skl.c   | 2 +-
 sound/soc/intel/avs/utils.c | 6 +-----
 4 files changed, 7 insertions(+), 14 deletions(-)

diff --git a/sound/soc/intel/avs/apl.c b/sound/soc/intel/avs/apl.c
index 821d5a9ad25fc..66672ffd95dfd 100644
--- a/sound/soc/intel/avs/apl.c
+++ b/sound/soc/intel/avs/apl.c
@@ -65,13 +65,12 @@ static int apl_log_buffer_status(struct avs_dev *adev, union avs_notify_msg *msg
 	buf = apl_log_payload_addr(addr);
 
 	if (layout.read_ptr > layout.write_ptr) {
-		__kfifo_fromio_locked(&adev->dbg.trace_fifo, buf + layout.read_ptr,
-				      apl_log_payload_size(adev) - layout.read_ptr,
-				      &adev->dbg.fifo_lock);
+		__kfifo_fromio(&adev->dbg.trace_fifo, buf + layout.read_ptr,
+			       apl_log_payload_size(adev) - layout.read_ptr);
 		layout.read_ptr = 0;
 	}
-	__kfifo_fromio_locked(&adev->dbg.trace_fifo, buf + layout.read_ptr,
-			      layout.write_ptr - layout.read_ptr, &adev->dbg.fifo_lock);
+	__kfifo_fromio(&adev->dbg.trace_fifo, buf + layout.read_ptr,
+		       layout.write_ptr - layout.read_ptr);
 
 	wake_up(&adev->dbg.trace_waitq);
 
diff --git a/sound/soc/intel/avs/avs.h b/sound/soc/intel/avs/avs.h
index 1c89af6240d28..957151ecf39ac 100644
--- a/sound/soc/intel/avs/avs.h
+++ b/sound/soc/intel/avs/avs.h
@@ -95,7 +95,6 @@ struct avs_fw_entry {
 
 struct avs_debug {
 	struct kfifo trace_fifo;
-	spinlock_t fifo_lock;	/* serialize I/O for trace_fifo */
 	spinlock_t trace_lock;	/* serialize debug window I/O between each LOG_BUFFER_STATUS */
 	wait_queue_head_t trace_waitq;
 	u32 aging_timer_period;
@@ -331,8 +330,7 @@ void avs_unregister_all_boards(struct avs_dev *adev);
 
 /* Firmware tracing helpers */
 
-unsigned int __kfifo_fromio_locked(struct kfifo *fifo, const void __iomem *src, unsigned int len,
-				   spinlock_t *lock);
+unsigned int __kfifo_fromio(struct kfifo *fifo, const void __iomem *src, unsigned int len);
 
 #define avs_log_buffer_size(adev) \
 	((adev)->fw_cfg.trace_log_bytes / (adev)->hw_cfg.dsp_cores)
diff --git a/sound/soc/intel/avs/skl.c b/sound/soc/intel/avs/skl.c
index ff690e99d9601..936cd44eb73e5 100644
--- a/sound/soc/intel/avs/skl.c
+++ b/sound/soc/intel/avs/skl.c
@@ -68,7 +68,7 @@ skl_log_buffer_status(struct avs_dev *adev, union avs_notify_msg *msg)
 
 	/* Address is guaranteed to exist in SRAM2. */
 	buf = avs_log_buffer_addr(adev, msg->log.core) + offset;
-	__kfifo_fromio_locked(&adev->dbg.trace_fifo, buf, size, &adev->dbg.fifo_lock);
+	__kfifo_fromio(&adev->dbg.trace_fifo, buf, size);
 	wake_up(&adev->dbg.trace_waitq);
 
 	return 0;
diff --git a/sound/soc/intel/avs/utils.c b/sound/soc/intel/avs/utils.c
index 13611dee97877..75ad434d7dfb9 100644
--- a/sound/soc/intel/avs/utils.c
+++ b/sound/soc/intel/avs/utils.c
@@ -301,14 +301,11 @@ void avs_release_firmwares(struct avs_dev *adev)
 	}
 }
 
-unsigned int __kfifo_fromio_locked(struct kfifo *fifo, const void __iomem *src, unsigned int len,
-				   spinlock_t *lock)
+unsigned int __kfifo_fromio(struct kfifo *fifo, const void __iomem *src, unsigned int len)
 {
 	struct __kfifo *__fifo = &fifo->kfifo;
-	unsigned long flags;
 	unsigned int l, off;
 
-	spin_lock_irqsave(lock, flags);
 	len = min(len, kfifo_avail(fifo));
 	off = __fifo->in & __fifo->mask;
 	l = min(len, kfifo_size(fifo) - off);
@@ -318,7 +315,6 @@ unsigned int __kfifo_fromio_locked(struct kfifo *fifo, const void __iomem *src,
 	/* Make sure data copied from SRAM is visible to all CPUs. */
 	smp_mb();
 	__fifo->in += len;
-	spin_unlock_irqrestore(lock, flags);
 
 	return len;
 }
-- 
GitLab


From 9e3c15beb8976771f95ba30b3da8bd35dc7188ac Mon Sep 17 00:00:00 2001
From: Cezary Rojewski <cezary.rojewski@intel.com>
Date: Fri, 2 Dec 2022 16:28:31 +0100
Subject: [PATCH 107/875] ASoC: Intel: avs: Introduce debug-context aware
 helpers

Debug-related fields and log-dumping are useful when debugfs is enabled.
Define them under CONFIG_DEBUG_FS and provide stubs when the config is
disabled so that the code that makes use of these needs not to be
complicated unnecessarily.

Members that are duplicated by this patch will be removed by the follow
up changes.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20221202152841.672536-7-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/avs/Makefile  |  4 ++++
 sound/soc/intel/avs/avs.h     | 29 +++++++++++++++++++++++++++++
 sound/soc/intel/avs/debugfs.c | 28 ++++++++++++++++++++++++++++
 3 files changed, 61 insertions(+)
 create mode 100644 sound/soc/intel/avs/debugfs.c

diff --git a/sound/soc/intel/avs/Makefile b/sound/soc/intel/avs/Makefile
index 919212825f216..a211a0b7b4a83 100644
--- a/sound/soc/intel/avs/Makefile
+++ b/sound/soc/intel/avs/Makefile
@@ -9,6 +9,10 @@ snd-soc-avs-objs += trace.o
 # tell define_trace.h where to find the trace header
 CFLAGS_trace.o := -I$(src)
 
+ifneq ($(CONFIG_DEBUG_FS),)
+snd-soc-avs-objs += debugfs.o
+endif
+
 obj-$(CONFIG_SND_SOC_INTEL_AVS) += snd-soc-avs.o
 
 # Machine support
diff --git a/sound/soc/intel/avs/avs.h b/sound/soc/intel/avs/avs.h
index 957151ecf39ac..3687d03f87d4c 100644
--- a/sound/soc/intel/avs/avs.h
+++ b/sound/soc/intel/avs/avs.h
@@ -9,6 +9,7 @@
 #ifndef __SOUND_SOC_INTEL_AVS_H
 #define __SOUND_SOC_INTEL_AVS_H
 
+#include <linux/debugfs.h>
 #include <linux/device.h>
 #include <linux/firmware.h>
 #include <linux/kfifo.h>
@@ -146,6 +147,14 @@ struct avs_dev {
 	struct mutex path_mutex;
 
 	struct avs_debug dbg;
+	spinlock_t trace_lock;	/* serialize debug window I/O between each LOG_BUFFER_STATUS */
+#ifdef CONFIG_DEBUG_FS
+	struct kfifo trace_fifo;
+	wait_queue_head_t trace_waitq;
+	u32 aging_timer_period;
+	u32 fifo_full_timer_period;
+	u32 logged_resources;	/* context dependent: core or library */
+#endif
 };
 
 /* from hda_bus to avs_dev */
@@ -366,4 +375,24 @@ struct apl_log_buffer_layout {
 #define apl_log_payload_addr(addr) \
 	(addr + sizeof(struct apl_log_buffer_layout))
 
+#ifdef CONFIG_DEBUG_FS
+bool avs_logging_fw(struct avs_dev *adev);
+void avs_dump_fw_log(struct avs_dev *adev, const void __iomem *src, unsigned int len);
+void avs_dump_fw_log_wakeup(struct avs_dev *adev, const void __iomem *src, unsigned int len);
+#else
+static inline bool avs_logging_fw(struct avs_dev *adev)
+{
+	return false;
+}
+
+static inline void avs_dump_fw_log(struct avs_dev *adev, const void __iomem *src, unsigned int len)
+{
+}
+
+static inline void
+avs_dump_fw_log_wakeup(struct avs_dev *adev, const void __iomem *src, unsigned int len)
+{
+}
+#endif
+
 #endif /* __SOUND_SOC_INTEL_AVS_H */
diff --git a/sound/soc/intel/avs/debugfs.c b/sound/soc/intel/avs/debugfs.c
new file mode 100644
index 0000000000000..ac3889e21542a
--- /dev/null
+++ b/sound/soc/intel/avs/debugfs.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
+//
+// Authors: Cezary Rojewski <cezary.rojewski@intel.com>
+//          Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
+//
+
+#include <linux/debugfs.h>
+#include <linux/kfifo.h>
+#include <linux/wait.h>
+#include "avs.h"
+
+bool avs_logging_fw(struct avs_dev *adev)
+{
+	return kfifo_initialized(&adev->trace_fifo);
+}
+
+void avs_dump_fw_log(struct avs_dev *adev, const void __iomem *src, unsigned int len)
+{
+	__kfifo_fromio(&adev->trace_fifo, src, len);
+}
+
+void avs_dump_fw_log_wakeup(struct avs_dev *adev, const void __iomem *src, unsigned int len)
+{
+	avs_dump_fw_log(adev, src, len);
+	wake_up(&adev->trace_waitq);
+}
-- 
GitLab


From b3eefa5d8dbfe5286c3308fa706fc9c45b38fe19 Mon Sep 17 00:00:00 2001
From: Cezary Rojewski <cezary.rojewski@intel.com>
Date: Fri, 2 Dec 2022 16:28:32 +0100
Subject: [PATCH 108/875] ASoC: Intel: avs: Make enable_logs() dependent on
 DEBUG_FS

Without debug filesystem present, this code is redundant.
Operations: log_buffer_status and log_buffer_offset are left as is as
EXCEPTION_CAUGHT and even unexpected LOG_BUFFER_STATUS notifications may
occur without user ever touching debugfs.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20221202152841.672536-8-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/avs/apl.c      |  7 ++++---
 sound/soc/intel/avs/avs.h      |  5 +++++
 sound/soc/intel/avs/messages.c | 36 ++++++++++++++++++----------------
 sound/soc/intel/avs/skl.c      |  7 ++++---
 4 files changed, 32 insertions(+), 23 deletions(-)

diff --git a/sound/soc/intel/avs/apl.c b/sound/soc/intel/avs/apl.c
index 66672ffd95dfd..beef308c94285 100644
--- a/sound/soc/intel/avs/apl.c
+++ b/sound/soc/intel/avs/apl.c
@@ -13,8 +13,9 @@
 #include "path.h"
 #include "topology.h"
 
-static int apl_enable_logs(struct avs_dev *adev, enum avs_log_enable enable, u32 aging_period,
-			   u32 fifo_full_period, unsigned long resource_mask, u32 *priorities)
+static int __maybe_unused
+apl_enable_logs(struct avs_dev *adev, enum avs_log_enable enable, u32 aging_period,
+		u32 fifo_full_period, unsigned long resource_mask, u32 *priorities)
 {
 	struct apl_log_state_info *info;
 	u32 size, num_cores = adev->hw_cfg.dsp_cores;
@@ -239,10 +240,10 @@ const struct avs_dsp_ops apl_dsp_ops = {
 	.load_basefw = avs_hda_load_basefw,
 	.load_lib = avs_hda_load_library,
 	.transfer_mods = avs_hda_transfer_modules,
-	.enable_logs = apl_enable_logs,
 	.log_buffer_offset = skl_log_buffer_offset,
 	.log_buffer_status = apl_log_buffer_status,
 	.coredump = apl_coredump,
 	.d0ix_toggle = apl_d0ix_toggle,
 	.set_d0ix = apl_set_d0ix,
+	AVS_SET_ENABLE_LOGS_OP(apl)
 };
diff --git a/sound/soc/intel/avs/avs.h b/sound/soc/intel/avs/avs.h
index 3687d03f87d4c..f8f11d8b59361 100644
--- a/sound/soc/intel/avs/avs.h
+++ b/sound/soc/intel/avs/avs.h
@@ -376,10 +376,15 @@ struct apl_log_buffer_layout {
 	(addr + sizeof(struct apl_log_buffer_layout))
 
 #ifdef CONFIG_DEBUG_FS
+#define AVS_SET_ENABLE_LOGS_OP(name) \
+	.enable_logs = name##_enable_logs
+
 bool avs_logging_fw(struct avs_dev *adev);
 void avs_dump_fw_log(struct avs_dev *adev, const void __iomem *src, unsigned int len);
 void avs_dump_fw_log_wakeup(struct avs_dev *adev, const void __iomem *src, unsigned int len);
 #else
+#define AVS_SET_ENABLE_LOGS_OP(name)
+
 static inline bool avs_logging_fw(struct avs_dev *adev)
 {
 	return false;
diff --git a/sound/soc/intel/avs/messages.c b/sound/soc/intel/avs/messages.c
index 6b0fecbf07c3c..f734d49e42be7 100644
--- a/sound/soc/intel/avs/messages.c
+++ b/sound/soc/intel/avs/messages.c
@@ -685,6 +685,24 @@ int avs_ipc_get_modules_info(struct avs_dev *adev, struct avs_mods_info **info)
 	return 0;
 }
 
+int avs_ipc_copier_set_sink_format(struct avs_dev *adev, u16 module_id,
+				   u8 instance_id, u32 sink_id,
+				   const struct avs_audio_format *src_fmt,
+				   const struct avs_audio_format *sink_fmt)
+{
+	struct avs_copier_sink_format cpr_fmt;
+
+	cpr_fmt.sink_id = sink_id;
+	/* Firmware expects driver to resend copier's input format. */
+	cpr_fmt.src_fmt = *src_fmt;
+	cpr_fmt.sink_fmt = *sink_fmt;
+
+	return avs_ipc_set_large_config(adev, module_id, instance_id,
+					AVS_COPIER_SET_SINK_FORMAT,
+					(u8 *)&cpr_fmt, sizeof(cpr_fmt));
+}
+
+#ifdef CONFIG_DEBUG_FS
 int avs_ipc_set_enable_logs(struct avs_dev *adev, u8 *log_info, size_t size)
 {
 	return avs_ipc_set_large_config(adev, AVS_BASEFW_MOD_ID, AVS_BASEFW_INST_ID,
@@ -704,20 +722,4 @@ int avs_ipc_set_system_time(struct avs_dev *adev)
 	return avs_ipc_set_large_config(adev, AVS_BASEFW_MOD_ID, AVS_BASEFW_INST_ID,
 					AVS_BASEFW_SYSTEM_TIME, (u8 *)&sys_time, sizeof(sys_time));
 }
-
-int avs_ipc_copier_set_sink_format(struct avs_dev *adev, u16 module_id,
-				   u8 instance_id, u32 sink_id,
-				   const struct avs_audio_format *src_fmt,
-				   const struct avs_audio_format *sink_fmt)
-{
-	struct avs_copier_sink_format cpr_fmt;
-
-	cpr_fmt.sink_id = sink_id;
-	/* Firmware expects driver to resend copier's input format. */
-	cpr_fmt.src_fmt = *src_fmt;
-	cpr_fmt.sink_fmt = *sink_fmt;
-
-	return avs_ipc_set_large_config(adev, module_id, instance_id,
-					AVS_COPIER_SET_SINK_FORMAT,
-					(u8 *)&cpr_fmt, sizeof(cpr_fmt));
-}
+#endif
diff --git a/sound/soc/intel/avs/skl.c b/sound/soc/intel/avs/skl.c
index 936cd44eb73e5..c5edb0b0df145 100644
--- a/sound/soc/intel/avs/skl.c
+++ b/sound/soc/intel/avs/skl.c
@@ -12,8 +12,9 @@
 #include "avs.h"
 #include "messages.h"
 
-static int skl_enable_logs(struct avs_dev *adev, enum avs_log_enable enable, u32 aging_period,
-			   u32 fifo_full_period, unsigned long resource_mask, u32 *priorities)
+static int __maybe_unused
+skl_enable_logs(struct avs_dev *adev, enum avs_log_enable enable, u32 aging_period,
+		u32 fifo_full_period, unsigned long resource_mask, u32 *priorities)
 {
 	struct skl_log_state_info *info;
 	u32 size, num_cores = adev->hw_cfg.dsp_cores;
@@ -111,10 +112,10 @@ const struct avs_dsp_ops skl_dsp_ops = {
 	.load_basefw = avs_cldma_load_basefw,
 	.load_lib = avs_cldma_load_library,
 	.transfer_mods = avs_cldma_transfer_modules,
-	.enable_logs = skl_enable_logs,
 	.log_buffer_offset = skl_log_buffer_offset,
 	.log_buffer_status = skl_log_buffer_status,
 	.coredump = skl_coredump,
 	.d0ix_toggle = skl_d0ix_toggle,
 	.set_d0ix = skl_set_d0ix,
+	AVS_SET_ENABLE_LOGS_OP(skl)
 };
-- 
GitLab


From f7de161fc8d5e1ebac3c361a37b1d748e7086330 Mon Sep 17 00:00:00 2001
From: Cezary Rojewski <cezary.rojewski@intel.com>
Date: Fri, 2 Dec 2022 16:28:33 +0100
Subject: [PATCH 109/875] ASoC: Intel: avs: Drop usage of debug members in
 non-debug code

Switch to debug-context aware wrappers instead of accessing debug
members directly allowing for readable separation of debug and non-debug
related code. Duplicates are removed along the way.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20221202152841.672536-9-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/avs/apl.c     | 11 ++++-------
 sound/soc/intel/avs/avs.h     | 16 ++--------------
 sound/soc/intel/avs/debugfs.c | 18 ++++++++++++++++++
 sound/soc/intel/avs/skl.c     |  5 ++---
 sound/soc/intel/avs/utils.c   | 18 ------------------
 5 files changed, 26 insertions(+), 42 deletions(-)

diff --git a/sound/soc/intel/avs/apl.c b/sound/soc/intel/avs/apl.c
index beef308c94285..02683dce277af 100644
--- a/sound/soc/intel/avs/apl.c
+++ b/sound/soc/intel/avs/apl.c
@@ -59,21 +59,18 @@ static int apl_log_buffer_status(struct avs_dev *adev, union avs_notify_msg *msg
 
 	memcpy_fromio(&layout, addr, sizeof(layout));
 
-	if (!kfifo_initialized(&adev->dbg.trace_fifo))
+	if (!avs_logging_fw(adev))
 		/* consume the logs regardless of consumer presence */
 		goto update_read_ptr;
 
 	buf = apl_log_payload_addr(addr);
 
 	if (layout.read_ptr > layout.write_ptr) {
-		__kfifo_fromio(&adev->dbg.trace_fifo, buf + layout.read_ptr,
-			       apl_log_payload_size(adev) - layout.read_ptr);
+		avs_dump_fw_log(adev, buf + layout.read_ptr,
+				apl_log_payload_size(adev) - layout.read_ptr);
 		layout.read_ptr = 0;
 	}
-	__kfifo_fromio(&adev->dbg.trace_fifo, buf + layout.read_ptr,
-		       layout.write_ptr - layout.read_ptr);
-
-	wake_up(&adev->dbg.trace_waitq);
+	avs_dump_fw_log_wakeup(adev, buf + layout.read_ptr, layout.write_ptr - layout.read_ptr);
 
 update_read_ptr:
 	writel(layout.write_ptr, addr);
diff --git a/sound/soc/intel/avs/avs.h b/sound/soc/intel/avs/avs.h
index f8f11d8b59361..7a9fb27d38456 100644
--- a/sound/soc/intel/avs/avs.h
+++ b/sound/soc/intel/avs/avs.h
@@ -94,15 +94,6 @@ struct avs_fw_entry {
 	struct list_head node;
 };
 
-struct avs_debug {
-	struct kfifo trace_fifo;
-	spinlock_t trace_lock;	/* serialize debug window I/O between each LOG_BUFFER_STATUS */
-	wait_queue_head_t trace_waitq;
-	u32 aging_timer_period;
-	u32 fifo_full_timer_period;
-	u32 logged_resources;	/* context dependent: core or library */
-};
-
 /*
  * struct avs_dev - Intel HD-Audio driver data
  *
@@ -146,7 +137,6 @@ struct avs_dev {
 	spinlock_t path_list_lock;
 	struct mutex path_mutex;
 
-	struct avs_debug dbg;
 	spinlock_t trace_lock;	/* serialize debug window I/O between each LOG_BUFFER_STATUS */
 #ifdef CONFIG_DEBUG_FS
 	struct kfifo trace_fifo;
@@ -339,8 +329,6 @@ void avs_unregister_all_boards(struct avs_dev *adev);
 
 /* Firmware tracing helpers */
 
-unsigned int __kfifo_fromio(struct kfifo *fifo, const void __iomem *src, unsigned int len);
-
 #define avs_log_buffer_size(adev) \
 	((adev)->fw_cfg.trace_log_bytes / (adev)->hw_cfg.dsp_cores)
 
@@ -356,9 +344,9 @@ static inline int avs_log_buffer_status_locked(struct avs_dev *adev, union avs_n
 	unsigned long flags;
 	int ret;
 
-	spin_lock_irqsave(&adev->dbg.trace_lock, flags);
+	spin_lock_irqsave(&adev->trace_lock, flags);
 	ret = avs_dsp_op(adev, log_buffer_status, msg);
-	spin_unlock_irqrestore(&adev->dbg.trace_lock, flags);
+	spin_unlock_irqrestore(&adev->trace_lock, flags);
 
 	return ret;
 }
diff --git a/sound/soc/intel/avs/debugfs.c b/sound/soc/intel/avs/debugfs.c
index ac3889e21542a..78705bcb09fbb 100644
--- a/sound/soc/intel/avs/debugfs.c
+++ b/sound/soc/intel/avs/debugfs.c
@@ -11,6 +11,24 @@
 #include <linux/wait.h>
 #include "avs.h"
 
+static unsigned int __kfifo_fromio(struct kfifo *fifo, const void __iomem *src, unsigned int len)
+{
+	struct __kfifo *__fifo = &fifo->kfifo;
+	unsigned int l, off;
+
+	len = min(len, kfifo_avail(fifo));
+	off = __fifo->in & __fifo->mask;
+	l = min(len, kfifo_size(fifo) - off);
+
+	memcpy_fromio(__fifo->data + off, src, l);
+	memcpy_fromio(__fifo->data, src + l, len - l);
+	/* Make sure data copied from SRAM is visible to all CPUs. */
+	smp_mb();
+	__fifo->in += len;
+
+	return len;
+}
+
 bool avs_logging_fw(struct avs_dev *adev)
 {
 	return kfifo_initialized(&adev->trace_fifo);
diff --git a/sound/soc/intel/avs/skl.c b/sound/soc/intel/avs/skl.c
index c5edb0b0df145..6bb8bbc70442b 100644
--- a/sound/soc/intel/avs/skl.c
+++ b/sound/soc/intel/avs/skl.c
@@ -59,7 +59,7 @@ skl_log_buffer_status(struct avs_dev *adev, union avs_notify_msg *msg)
 	void __iomem *buf;
 	u16 size, write, offset;
 
-	if (!kfifo_initialized(&adev->dbg.trace_fifo))
+	if (!avs_logging_fw(adev))
 		return 0;
 
 	size = avs_log_buffer_size(adev) / 2;
@@ -69,8 +69,7 @@ skl_log_buffer_status(struct avs_dev *adev, union avs_notify_msg *msg)
 
 	/* Address is guaranteed to exist in SRAM2. */
 	buf = avs_log_buffer_addr(adev, msg->log.core) + offset;
-	__kfifo_fromio(&adev->dbg.trace_fifo, buf, size);
-	wake_up(&adev->dbg.trace_waitq);
+	avs_dump_fw_log_wakeup(adev, buf, size);
 
 	return 0;
 }
diff --git a/sound/soc/intel/avs/utils.c b/sound/soc/intel/avs/utils.c
index 75ad434d7dfb9..82416b86662d8 100644
--- a/sound/soc/intel/avs/utils.c
+++ b/sound/soc/intel/avs/utils.c
@@ -300,21 +300,3 @@ void avs_release_firmwares(struct avs_dev *adev)
 		kfree(entry);
 	}
 }
-
-unsigned int __kfifo_fromio(struct kfifo *fifo, const void __iomem *src, unsigned int len)
-{
-	struct __kfifo *__fifo = &fifo->kfifo;
-	unsigned int l, off;
-
-	len = min(len, kfifo_avail(fifo));
-	off = __fifo->in & __fifo->mask;
-	l = min(len, kfifo_size(fifo) - off);
-
-	memcpy_fromio(__fifo->data + off, src, l);
-	memcpy_fromio(__fifo->data, src + l, len - l);
-	/* Make sure data copied from SRAM is visible to all CPUs. */
-	smp_mb();
-	__fifo->in += len;
-
-	return len;
-}
-- 
GitLab


From dab8d000e25c3e91154efca287434a4f78ab65d2 Mon Sep 17 00:00:00 2001
From: Cezary Rojewski <cezary.rojewski@intel.com>
Date: Fri, 2 Dec 2022 16:28:34 +0100
Subject: [PATCH 110/875] ASoC: Intel: avs: Add data probing requests

Data probing is a cAVS firmware functionality that allows for data
extraction and injection directly from or to DMA stream. To support it,
new functions and types are added. These facilitate communication
with the firmware.

Total of eight IPCs:
- probe module initialization and cleanup
- addition and removal of probe points
- addition and removal of injection DMAs
- dumping list of currently connected probe points or enlisted DMAs

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20221202152841.672536-10-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/avs/Makefile   |  2 +-
 sound/soc/intel/avs/messages.c | 78 ++++++++++++++++++++++++++++++++++
 sound/soc/intel/avs/messages.h | 53 +++++++++++++++++++++++
 sound/soc/intel/avs/probes.c   | 46 ++++++++++++++++++++
 4 files changed, 178 insertions(+), 1 deletion(-)
 create mode 100644 sound/soc/intel/avs/probes.c

diff --git a/sound/soc/intel/avs/Makefile b/sound/soc/intel/avs/Makefile
index a211a0b7b4a83..1c6924a1ebca3 100644
--- a/sound/soc/intel/avs/Makefile
+++ b/sound/soc/intel/avs/Makefile
@@ -10,7 +10,7 @@ snd-soc-avs-objs += trace.o
 CFLAGS_trace.o := -I$(src)
 
 ifneq ($(CONFIG_DEBUG_FS),)
-snd-soc-avs-objs += debugfs.o
+snd-soc-avs-objs += probes.o debugfs.o
 endif
 
 obj-$(CONFIG_SND_SOC_INTEL_AVS) += snd-soc-avs.o
diff --git a/sound/soc/intel/avs/messages.c b/sound/soc/intel/avs/messages.c
index f734d49e42be7..e11ae4246416c 100644
--- a/sound/soc/intel/avs/messages.c
+++ b/sound/soc/intel/avs/messages.c
@@ -722,4 +722,82 @@ int avs_ipc_set_system_time(struct avs_dev *adev)
 	return avs_ipc_set_large_config(adev, AVS_BASEFW_MOD_ID, AVS_BASEFW_INST_ID,
 					AVS_BASEFW_SYSTEM_TIME, (u8 *)&sys_time, sizeof(sys_time));
 }
+
+int avs_ipc_probe_get_dma(struct avs_dev *adev, struct avs_probe_dma **dmas, size_t *num_dmas)
+{
+	size_t payload_size;
+	u32 module_id;
+	u8 *payload;
+	int ret;
+
+	module_id = avs_get_module_id(adev, &AVS_PROBE_MOD_UUID);
+
+	ret = avs_ipc_get_large_config(adev, module_id, AVS_PROBE_INST_ID, AVS_PROBE_INJECTION_DMA,
+				       NULL, 0, &payload, &payload_size);
+	if (ret)
+		return ret;
+
+	*dmas = (struct avs_probe_dma *)payload;
+	*num_dmas = payload_size / sizeof(**dmas);
+
+	return 0;
+}
+
+int avs_ipc_probe_attach_dma(struct avs_dev *adev, struct avs_probe_dma *dmas, size_t num_dmas)
+{
+	u32 module_id = avs_get_module_id(adev, &AVS_PROBE_MOD_UUID);
+
+	return avs_ipc_set_large_config(adev, module_id, AVS_PROBE_INST_ID, AVS_PROBE_INJECTION_DMA,
+					(u8 *)dmas, array_size(sizeof(*dmas), num_dmas));
+}
+
+int avs_ipc_probe_detach_dma(struct avs_dev *adev, union avs_connector_node_id *node_ids,
+			     size_t num_node_ids)
+{
+	u32 module_id = avs_get_module_id(adev, &AVS_PROBE_MOD_UUID);
+
+	return avs_ipc_set_large_config(adev, module_id, AVS_PROBE_INST_ID,
+					AVS_PROBE_INJECTION_DMA_DETACH, (u8 *)node_ids,
+					array_size(sizeof(*node_ids), num_node_ids));
+}
+
+int avs_ipc_probe_get_points(struct avs_dev *adev, struct avs_probe_point_desc **descs,
+			     size_t *num_descs)
+{
+	size_t payload_size;
+	u32 module_id;
+	u8 *payload;
+	int ret;
+
+	module_id = avs_get_module_id(adev, &AVS_PROBE_MOD_UUID);
+
+	ret = avs_ipc_get_large_config(adev, module_id, AVS_PROBE_INST_ID, AVS_PROBE_POINTS, NULL,
+				       0, &payload, &payload_size);
+	if (ret)
+		return ret;
+
+	*descs = (struct avs_probe_point_desc *)payload;
+	*num_descs = payload_size / sizeof(**descs);
+
+	return 0;
+}
+
+int avs_ipc_probe_connect_points(struct avs_dev *adev, struct avs_probe_point_desc *descs,
+				 size_t num_descs)
+{
+	u32 module_id = avs_get_module_id(adev, &AVS_PROBE_MOD_UUID);
+
+	return avs_ipc_set_large_config(adev, module_id, AVS_PROBE_INST_ID, AVS_PROBE_POINTS,
+					(u8 *)descs, array_size(sizeof(*descs), num_descs));
+}
+
+int avs_ipc_probe_disconnect_points(struct avs_dev *adev, union avs_probe_point_id *ids,
+				    size_t num_ids)
+{
+	u32 module_id = avs_get_module_id(adev, &AVS_PROBE_MOD_UUID);
+
+	return avs_ipc_set_large_config(adev, module_id, AVS_PROBE_INST_ID,
+					AVS_PROBE_POINTS_DISCONNECT, (u8 *)ids,
+					array_size(sizeof(*ids), num_ids));
+}
 #endif
diff --git a/sound/soc/intel/avs/messages.h b/sound/soc/intel/avs/messages.h
index 02b3b7a74783a..9dd835527e02c 100644
--- a/sound/soc/intel/avs/messages.h
+++ b/sound/soc/intel/avs/messages.h
@@ -802,4 +802,57 @@ int avs_ipc_copier_set_sink_format(struct avs_dev *adev, u16 module_id,
 				   const struct avs_audio_format *src_fmt,
 				   const struct avs_audio_format *sink_fmt);
 
+#define AVS_PROBE_INST_ID	0
+
+enum avs_probe_runtime_param {
+	AVS_PROBE_INJECTION_DMA = 1,
+	AVS_PROBE_INJECTION_DMA_DETACH,
+	AVS_PROBE_POINTS,
+	AVS_PROBE_POINTS_DISCONNECT,
+};
+
+struct avs_probe_dma {
+	union avs_connector_node_id node_id;
+	u32 dma_buffer_size;
+} __packed;
+
+enum avs_probe_type {
+	AVS_PROBE_TYPE_INPUT = 0,
+	AVS_PROBE_TYPE_OUTPUT,
+	AVS_PROBE_TYPE_INTERNAL
+};
+
+union avs_probe_point_id {
+	u32 value;
+	struct {
+		u32 module_id:16;
+		u32 instance_id:8;
+		u32 type:2;
+		u32 index:6;
+	} id;
+} __packed;
+
+enum avs_connection_purpose {
+	AVS_CONNECTION_PURPOSE_EXTRACT = 0,
+	AVS_CONNECTION_PURPOSE_INJECT,
+	AVS_CONNECTION_PURPOSE_INJECT_REEXTRACT,
+};
+
+struct avs_probe_point_desc {
+	union avs_probe_point_id id;
+	u32 purpose;
+	union avs_connector_node_id node_id;
+} __packed;
+
+int avs_ipc_probe_get_dma(struct avs_dev *adev, struct avs_probe_dma **dmas, size_t *num_dmas);
+int avs_ipc_probe_attach_dma(struct avs_dev *adev, struct avs_probe_dma *dmas, size_t num_dmas);
+int avs_ipc_probe_detach_dma(struct avs_dev *adev, union avs_connector_node_id *node_ids,
+			     size_t num_node_ids);
+int avs_ipc_probe_get_points(struct avs_dev *adev, struct avs_probe_point_desc **descs,
+			     size_t *num_descs);
+int avs_ipc_probe_connect_points(struct avs_dev *adev, struct avs_probe_point_desc *descs,
+				 size_t num_descs);
+int avs_ipc_probe_disconnect_points(struct avs_dev *adev, union avs_probe_point_id *ids,
+				    size_t num_ids);
+
 #endif /* __SOUND_SOC_INTEL_AVS_MSGS_H */
diff --git a/sound/soc/intel/avs/probes.c b/sound/soc/intel/avs/probes.c
new file mode 100644
index 0000000000000..339bad6fec223
--- /dev/null
+++ b/sound/soc/intel/avs/probes.c
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
+//
+// Authors: Cezary Rojewski <cezary.rojewski@intel.com>
+//          Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
+//
+
+#include "avs.h"
+#include "messages.h"
+
+__maybe_unused
+static int avs_dsp_init_probe(struct avs_dev *adev, union avs_connector_node_id node_id,
+			      size_t buffer_size)
+
+{
+	struct avs_probe_cfg cfg = {{0}};
+	struct avs_module_entry mentry;
+	u16 dummy;
+
+	avs_get_module_entry(adev, &AVS_PROBE_MOD_UUID, &mentry);
+
+	/*
+	 * Probe module uses no cycles, audio data format and input and output
+	 * frame sizes are unused. It is also not owned by any pipeline.
+	 */
+	cfg.base.ibs = 1;
+	/* BSS module descriptor is always segment of index=2. */
+	cfg.base.is_pages = mentry.segments[2].flags.length;
+	cfg.gtw_cfg.node_id = node_id;
+	cfg.gtw_cfg.dma_buffer_size = buffer_size;
+
+	return avs_dsp_init_module(adev, mentry.module_id, INVALID_PIPELINE_ID, 0, 0, &cfg,
+				   sizeof(cfg), &dummy);
+}
+
+__maybe_unused
+static void avs_dsp_delete_probe(struct avs_dev *adev)
+{
+	struct avs_module_entry mentry;
+
+	avs_get_module_entry(adev, &AVS_PROBE_MOD_UUID, &mentry);
+
+	/* There is only ever one probe module instance. */
+	avs_dsp_delete_module(adev, mentry.module_id, 0, INVALID_PIPELINE_ID, 0);
+}
-- 
GitLab


From 700462f55493c6831ad71b209eaebe310dcf11fd Mon Sep 17 00:00:00 2001
From: Cezary Rojewski <cezary.rojewski@intel.com>
Date: Fri, 2 Dec 2022 16:28:35 +0100
Subject: [PATCH 111/875] ASoC: Intel: avs: Probe compress operations

Add compress operations handlers for data extraction through probes. A
single HDAudio stream is enlisted for said purpose. Operations follow
same protocol as for standard PCM streaming on HOST side.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20221202152841.672536-11-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/Kconfig      |   1 +
 sound/soc/intel/avs/avs.h    |   3 +
 sound/soc/intel/avs/probes.c | 224 ++++++++++++++++++++++++++++++++++-
 3 files changed, 225 insertions(+), 3 deletions(-)

diff --git a/sound/soc/intel/Kconfig b/sound/soc/intel/Kconfig
index ac799de4f7fda..4b9e498e33037 100644
--- a/sound/soc/intel/Kconfig
+++ b/sound/soc/intel/Kconfig
@@ -217,6 +217,7 @@ config SND_SOC_INTEL_AVS
 	select SND_SOC_ACPI if ACPI
 	select SND_SOC_TOPOLOGY
 	select SND_SOC_HDA
+	select SND_SOC_COMPRESS if DEBUG_FS
 	select SND_HDA_EXT_CORE
 	select SND_HDA_DSP_LOADER
 	select SND_INTEL_DSP_CONFIG
diff --git a/sound/soc/intel/avs/avs.h b/sound/soc/intel/avs/avs.h
index 7a9fb27d38456..e5e7c72eb5110 100644
--- a/sound/soc/intel/avs/avs.h
+++ b/sound/soc/intel/avs/avs.h
@@ -144,6 +144,9 @@ struct avs_dev {
 	u32 aging_timer_period;
 	u32 fifo_full_timer_period;
 	u32 logged_resources;	/* context dependent: core or library */
+	/* probes */
+	struct hdac_ext_stream *extractor;
+	unsigned int num_probe_streams;
 #endif
 };
 
diff --git a/sound/soc/intel/avs/probes.c b/sound/soc/intel/avs/probes.c
index 339bad6fec223..e90284ec8500b 100644
--- a/sound/soc/intel/avs/probes.c
+++ b/sound/soc/intel/avs/probes.c
@@ -6,13 +6,15 @@
 //          Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
 //
 
+#include <sound/compress_driver.h>
+#include <sound/hdaudio_ext.h>
+#include <sound/hdaudio.h>
+#include <sound/soc.h>
 #include "avs.h"
 #include "messages.h"
 
-__maybe_unused
 static int avs_dsp_init_probe(struct avs_dev *adev, union avs_connector_node_id node_id,
 			      size_t buffer_size)
-
 {
 	struct avs_probe_cfg cfg = {{0}};
 	struct avs_module_entry mentry;
@@ -34,7 +36,6 @@ static int avs_dsp_init_probe(struct avs_dev *adev, union avs_connector_node_id
 				   sizeof(cfg), &dummy);
 }
 
-__maybe_unused
 static void avs_dsp_delete_probe(struct avs_dev *adev)
 {
 	struct avs_module_entry mentry;
@@ -44,3 +45,220 @@ static void avs_dsp_delete_probe(struct avs_dev *adev)
 	/* There is only ever one probe module instance. */
 	avs_dsp_delete_module(adev, mentry.module_id, 0, INVALID_PIPELINE_ID, 0);
 }
+
+static inline struct hdac_ext_stream *avs_compr_get_host_stream(struct snd_compr_stream *cstream)
+{
+	return cstream->runtime->private_data;
+}
+
+static int avs_probe_compr_open(struct snd_compr_stream *cstream, struct snd_soc_dai *dai)
+{
+	struct avs_dev *adev = to_avs_dev(dai->dev);
+	struct hdac_bus *bus = &adev->base.core;
+	struct hdac_ext_stream *host_stream;
+
+	if (adev->extractor) {
+		dev_err(dai->dev, "Cannot open more than one extractor stream\n");
+		return -EEXIST;
+	}
+
+	host_stream = snd_hdac_ext_cstream_assign(bus, cstream);
+	if (!host_stream) {
+		dev_err(dai->dev, "Failed to assign HDAudio stream for extraction\n");
+		return -EBUSY;
+	}
+
+	adev->extractor = host_stream;
+	hdac_stream(host_stream)->curr_pos = 0;
+	cstream->runtime->private_data = host_stream;
+
+	return 0;
+}
+
+static int avs_probe_compr_free(struct snd_compr_stream *cstream, struct snd_soc_dai *dai)
+{
+	struct hdac_ext_stream *host_stream = avs_compr_get_host_stream(cstream);
+	struct avs_dev *adev = to_avs_dev(dai->dev);
+	struct avs_probe_point_desc *desc;
+	/* Extractor node identifier. */
+	unsigned int vindex = INVALID_NODE_ID.vindex;
+	size_t num_desc;
+	int i, ret;
+
+	/* Disconnect all probe points. */
+	ret = avs_ipc_probe_get_points(adev, &desc, &num_desc);
+	if (ret) {
+		dev_err(dai->dev, "get probe points failed: %d\n", ret);
+		ret = AVS_IPC_RET(ret);
+		goto exit;
+	}
+
+	for (i = 0; i < num_desc; i++)
+		if (desc[i].node_id.vindex == vindex)
+			avs_ipc_probe_disconnect_points(adev, &desc[i].id, 1);
+	kfree(desc);
+
+exit:
+	if (adev->num_probe_streams) {
+		adev->num_probe_streams--;
+		if (!adev->num_probe_streams) {
+			avs_dsp_delete_probe(adev);
+			avs_dsp_enable_d0ix(adev);
+		}
+	}
+
+	snd_hdac_stream_cleanup(hdac_stream(host_stream));
+	hdac_stream(host_stream)->prepared = 0;
+	snd_hdac_ext_stream_release(host_stream, HDAC_EXT_STREAM_TYPE_HOST);
+
+	snd_compr_free_pages(cstream);
+	adev->extractor = NULL;
+
+	return ret;
+}
+
+static int avs_probe_compr_set_params(struct snd_compr_stream *cstream,
+				      struct snd_compr_params *params, struct snd_soc_dai *dai)
+{
+	struct hdac_ext_stream *host_stream = avs_compr_get_host_stream(cstream);
+	struct snd_compr_runtime *rtd = cstream->runtime;
+	struct avs_dev *adev = to_avs_dev(dai->dev);
+	/* compr params do not store bit depth, default to S32_LE. */
+	snd_pcm_format_t format = SNDRV_PCM_FORMAT_S32_LE;
+	unsigned int format_val;
+	int bps, ret;
+
+	hdac_stream(host_stream)->bufsize = 0;
+	hdac_stream(host_stream)->period_bytes = 0;
+	hdac_stream(host_stream)->format_val = 0;
+	cstream->dma_buffer.dev.type = SNDRV_DMA_TYPE_DEV_SG;
+	cstream->dma_buffer.dev.dev = adev->dev;
+
+	ret = snd_compr_malloc_pages(cstream, rtd->buffer_size);
+	if (ret < 0)
+		return ret;
+	bps = snd_pcm_format_physical_width(format);
+	if (bps < 0)
+		return bps;
+	format_val = snd_hdac_calc_stream_format(params->codec.sample_rate, params->codec.ch_out,
+						 format, bps, 0);
+	ret = snd_hdac_stream_set_params(hdac_stream(host_stream), format_val);
+	if (ret < 0)
+		return ret;
+	ret = snd_hdac_stream_setup(hdac_stream(host_stream));
+	if (ret < 0)
+		return ret;
+
+	hdac_stream(host_stream)->prepared = 1;
+
+	if (!adev->num_probe_streams) {
+		union avs_connector_node_id node_id;
+
+		/* D0ix not allowed during probing. */
+		ret = avs_dsp_disable_d0ix(adev);
+		if (ret)
+			return ret;
+
+		node_id.vindex = hdac_stream(host_stream)->stream_tag - 1;
+		node_id.dma_type = AVS_DMA_HDA_HOST_INPUT;
+
+		ret = avs_dsp_init_probe(adev, node_id, rtd->dma_bytes);
+		if (ret < 0) {
+			dev_err(dai->dev, "probe init failed: %d\n", ret);
+			avs_dsp_enable_d0ix(adev);
+			return ret;
+		}
+	}
+
+	adev->num_probe_streams++;
+	return 0;
+}
+
+static int avs_probe_compr_trigger(struct snd_compr_stream *cstream, int cmd,
+				   struct snd_soc_dai *dai)
+{
+	struct hdac_ext_stream *host_stream = avs_compr_get_host_stream(cstream);
+	struct avs_dev *adev = to_avs_dev(dai->dev);
+	struct hdac_bus *bus = &adev->base.core;
+	unsigned long cookie;
+
+	if (!hdac_stream(host_stream)->prepared)
+		return -EPIPE;
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+	case SNDRV_PCM_TRIGGER_RESUME:
+		spin_lock_irqsave(&bus->reg_lock, cookie);
+		snd_hdac_stream_start(hdac_stream(host_stream), true);
+		spin_unlock_irqrestore(&bus->reg_lock, cookie);
+		break;
+
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_STOP:
+		spin_lock_irqsave(&bus->reg_lock, cookie);
+		snd_hdac_stream_stop(hdac_stream(host_stream));
+		spin_unlock_irqrestore(&bus->reg_lock, cookie);
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int avs_probe_compr_pointer(struct snd_compr_stream *cstream,
+				   struct snd_compr_tstamp *tstamp, struct snd_soc_dai *dai)
+{
+	struct hdac_ext_stream *host_stream = avs_compr_get_host_stream(cstream);
+	struct snd_soc_pcm_stream *pstream;
+
+	pstream = &dai->driver->capture;
+	tstamp->copied_total = hdac_stream(host_stream)->curr_pos;
+	tstamp->sampling_rate = snd_pcm_rate_bit_to_rate(pstream->rates);
+
+	return 0;
+}
+
+static int avs_probe_compr_copy(struct snd_soc_component *comp, struct snd_compr_stream *cstream,
+				char __user *buf, size_t count)
+{
+	struct snd_compr_runtime *rtd = cstream->runtime;
+	unsigned int offset, n;
+	void *ptr;
+	int ret;
+
+	if (count > rtd->buffer_size)
+		count = rtd->buffer_size;
+
+	div_u64_rem(rtd->total_bytes_transferred, rtd->buffer_size, &offset);
+	ptr = rtd->dma_area + offset;
+	n = rtd->buffer_size - offset;
+
+	if (count < n) {
+		ret = copy_to_user(buf, ptr, count);
+	} else {
+		ret = copy_to_user(buf, ptr, n);
+		ret += copy_to_user(buf + n, rtd->dma_area, count - n);
+	}
+
+	if (ret)
+		return count - ret;
+	return count;
+}
+
+__maybe_unused
+static const struct snd_soc_cdai_ops avs_probe_dai_ops = {
+	.startup = avs_probe_compr_open,
+	.shutdown = avs_probe_compr_free,
+	.set_params = avs_probe_compr_set_params,
+	.trigger = avs_probe_compr_trigger,
+	.pointer = avs_probe_compr_pointer,
+};
+
+__maybe_unused
+static const struct snd_compress_ops avs_probe_compress_ops = {
+	.copy = avs_probe_compr_copy,
+};
-- 
GitLab


From ed914a2a45a45e7d8f900ae8997ca4573792afcc Mon Sep 17 00:00:00 2001
From: Cezary Rojewski <cezary.rojewski@intel.com>
Date: Fri, 2 Dec 2022 16:28:36 +0100
Subject: [PATCH 112/875] ASoC: Intel: avs: Data probing soc-component

Define stub component for data probing. Stub as most operations from
standard PCM case do not apply here. Specific bits are CPU DAIs and
compress_ops. FE DAIs can link against these new CPU DAI to create new
compress devices.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20221202152841.672536-12-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/avs/avs.h    | 10 +++++++
 sound/soc/intel/avs/pcm.c    |  6 ++--
 sound/soc/intel/avs/probes.c | 53 ++++++++++++++++++++++++++++++++++--
 3 files changed, 64 insertions(+), 5 deletions(-)

diff --git a/sound/soc/intel/avs/avs.h b/sound/soc/intel/avs/avs.h
index e5e7c72eb5110..e19d8d89455d1 100644
--- a/sound/soc/intel/avs/avs.h
+++ b/sound/soc/intel/avs/avs.h
@@ -322,6 +322,9 @@ struct avs_soc_component {
 
 extern const struct snd_soc_dai_ops avs_dai_fe_ops;
 
+int avs_soc_component_register(struct device *dev, const char *name,
+			       const struct snd_soc_component_driver *drv,
+			       struct snd_soc_dai_driver *cpu_dais, int num_cpu_dais);
 int avs_dmic_platform_register(struct avs_dev *adev, const char *name);
 int avs_i2s_platform_register(struct avs_dev *adev, const char *name, unsigned long port_mask,
 			      unsigned long *tdms);
@@ -373,6 +376,8 @@ struct apl_log_buffer_layout {
 bool avs_logging_fw(struct avs_dev *adev);
 void avs_dump_fw_log(struct avs_dev *adev, const void __iomem *src, unsigned int len);
 void avs_dump_fw_log_wakeup(struct avs_dev *adev, const void __iomem *src, unsigned int len);
+
+int avs_probe_platform_register(struct avs_dev *adev, const char *name);
 #else
 #define AVS_SET_ENABLE_LOGS_OP(name)
 
@@ -389,6 +394,11 @@ static inline void
 avs_dump_fw_log_wakeup(struct avs_dev *adev, const void __iomem *src, unsigned int len)
 {
 }
+
+static inline int avs_probe_platform_register(struct avs_dev *adev, const char *name)
+{
+	return 0;
+}
 #endif
 
 #endif /* __SOUND_SOC_INTEL_AVS_H */
diff --git a/sound/soc/intel/avs/pcm.c b/sound/soc/intel/avs/pcm.c
index 70d687fa9923e..f930c5e86a84a 100644
--- a/sound/soc/intel/avs/pcm.c
+++ b/sound/soc/intel/avs/pcm.c
@@ -1126,9 +1126,9 @@ static const struct snd_soc_component_driver avs_component_driver = {
 	.topology_name_prefix	= "intel/avs",
 };
 
-static int avs_soc_component_register(struct device *dev, const char *name,
-				      const struct snd_soc_component_driver *drv,
-				      struct snd_soc_dai_driver *cpu_dais, int num_cpu_dais)
+int avs_soc_component_register(struct device *dev, const char *name,
+			       const struct snd_soc_component_driver *drv,
+			       struct snd_soc_dai_driver *cpu_dais, int num_cpu_dais)
 {
 	struct avs_soc_component *acomp;
 	int ret;
diff --git a/sound/soc/intel/avs/probes.c b/sound/soc/intel/avs/probes.c
index e90284ec8500b..29d63f2a9616c 100644
--- a/sound/soc/intel/avs/probes.c
+++ b/sound/soc/intel/avs/probes.c
@@ -249,7 +249,6 @@ static int avs_probe_compr_copy(struct snd_soc_component *comp, struct snd_compr
 	return count;
 }
 
-__maybe_unused
 static const struct snd_soc_cdai_ops avs_probe_dai_ops = {
 	.startup = avs_probe_compr_open,
 	.shutdown = avs_probe_compr_free,
@@ -258,7 +257,57 @@ static const struct snd_soc_cdai_ops avs_probe_dai_ops = {
 	.pointer = avs_probe_compr_pointer,
 };
 
-__maybe_unused
 static const struct snd_compress_ops avs_probe_compress_ops = {
 	.copy = avs_probe_compr_copy,
 };
+
+static struct snd_soc_dai_driver probe_cpu_dais[] = {
+{
+	.name = "Probe Extraction CPU DAI",
+	.compress_new = snd_soc_new_compress,
+	.cops = &avs_probe_dai_ops,
+	.capture = {
+		.stream_name = "Probe Extraction",
+		.channels_min = 1,
+		.channels_max = 8,
+		.rates = SNDRV_PCM_RATE_48000,
+		.rate_min = 48000,
+		.rate_max = 48000,
+	},
+},
+};
+
+static int avs_probe_component_probe(struct snd_soc_component *component)
+{
+	struct avs_soc_component *acomp = to_avs_soc_component(component);
+	struct avs_dev *adev = to_avs_dev(component->dev);
+
+	mutex_lock(&adev->comp_list_mutex);
+	list_add_tail(&acomp->node, &adev->comp_list);
+	mutex_unlock(&adev->comp_list_mutex);
+	return 0;
+}
+
+static void avs_probe_component_remove(struct snd_soc_component *component)
+{
+	struct avs_soc_component *acomp = to_avs_soc_component(component);
+	struct avs_dev *adev = to_avs_dev(component->dev);
+
+	mutex_lock(&adev->comp_list_mutex);
+	list_del(&acomp->node);
+	mutex_unlock(&adev->comp_list_mutex);
+}
+
+static const struct snd_soc_component_driver avs_probe_component_driver = {
+	.name			= "avs-probe-compr",
+	.probe			= avs_probe_component_probe,
+	.remove			= avs_probe_component_remove,
+	.compress_ops		= &avs_probe_compress_ops,
+	.module_get_upon_open	= 1, /* increment refcount when a stream is opened */
+};
+
+int avs_probe_platform_register(struct avs_dev *adev, const char *name)
+{
+	return avs_soc_component_register(adev->dev, name, &avs_probe_component_driver,
+					  probe_cpu_dais, ARRAY_SIZE(probe_cpu_dais));
+}
-- 
GitLab


From e17527e167ae5bd71fc9cb67da4e73bbb050e6f7 Mon Sep 17 00:00:00 2001
From: Cezary Rojewski <cezary.rojewski@intel.com>
Date: Fri, 2 Dec 2022 16:28:37 +0100
Subject: [PATCH 113/875] ASoC: Intel: avs: Add probe machine board

Stub machine board driver with no custom DAPM routes and single FE DAI
link for userspace to interact with.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20221202152841.672536-13-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/avs/board_selection.c | 33 ++++++++++++++
 sound/soc/intel/avs/boards/Kconfig    |  8 ++++
 sound/soc/intel/avs/boards/Makefile   |  2 +
 sound/soc/intel/avs/boards/probe.c    | 64 +++++++++++++++++++++++++++
 4 files changed, 107 insertions(+)
 create mode 100644 sound/soc/intel/avs/boards/probe.c

diff --git a/sound/soc/intel/avs/board_selection.c b/sound/soc/intel/avs/board_selection.c
index 02cc1ce8f5f58..b2823c2107f77 100644
--- a/sound/soc/intel/avs/board_selection.c
+++ b/sound/soc/intel/avs/board_selection.c
@@ -291,6 +291,33 @@ static void board_pdev_unregister(void *data)
 	platform_device_unregister(data);
 }
 
+static int __maybe_unused avs_register_probe_board(struct avs_dev *adev)
+{
+	struct platform_device *board;
+	struct snd_soc_acpi_mach mach = {{0}};
+	int ret;
+
+	ret = avs_probe_platform_register(adev, "probe-platform");
+	if (ret < 0)
+		return ret;
+
+	mach.mach_params.platform = "probe-platform";
+
+	board = platform_device_register_data(NULL, "avs_probe_mb", PLATFORM_DEVID_NONE,
+					      (const void *)&mach, sizeof(mach));
+	if (IS_ERR(board)) {
+		dev_err(adev->dev, "probe board register failed\n");
+		return PTR_ERR(board);
+	}
+
+	ret = devm_add_action(adev->dev, board_pdev_unregister, board);
+	if (ret < 0) {
+		platform_device_unregister(board);
+		return ret;
+	}
+	return 0;
+}
+
 static int avs_register_dmic_board(struct avs_dev *adev)
 {
 	struct platform_device *codec, *board;
@@ -500,6 +527,12 @@ int avs_register_all_boards(struct avs_dev *adev)
 {
 	int ret;
 
+#ifdef CONFIG_DEBUG_FS
+	ret = avs_register_probe_board(adev);
+	if (ret < 0)
+		dev_warn(adev->dev, "enumerate PROBE endpoints failed: %d\n", ret);
+#endif
+
 	ret = avs_register_dmic_board(adev);
 	if (ret < 0)
 		dev_warn(adev->dev, "enumerate DMIC endpoints failed: %d\n",
diff --git a/sound/soc/intel/avs/boards/Kconfig b/sound/soc/intel/avs/boards/Kconfig
index 9bd40fdd90280..e4c230efe8d79 100644
--- a/sound/soc/intel/avs/boards/Kconfig
+++ b/sound/soc/intel/avs/boards/Kconfig
@@ -77,6 +77,14 @@ config SND_SOC_INTEL_AVS_MACH_NAU8825
 	   Say Y or m if you have such a device. This is a recommended option.
 	   If unsure select "N".
 
+config SND_SOC_INTEL_AVS_MACH_PROBE
+	tristate "Probing (data) board"
+	depends on DEBUG_FS
+	select SND_HWDEP
+	help
+	   This adds support for data probing board which can be used to
+	   gather data from runtime stream over compress operations.
+
 config SND_SOC_INTEL_AVS_MACH_RT274
 	tristate "rt274 in I2S mode"
 	depends on I2C
diff --git a/sound/soc/intel/avs/boards/Makefile b/sound/soc/intel/avs/boards/Makefile
index 4d70b8d09ce55..b81343420370f 100644
--- a/sound/soc/intel/avs/boards/Makefile
+++ b/sound/soc/intel/avs/boards/Makefile
@@ -8,6 +8,7 @@ snd-soc-avs-max98927-objs := max98927.o
 snd-soc-avs-max98357a-objs := max98357a.o
 snd-soc-avs-max98373-objs := max98373.o
 snd-soc-avs-nau8825-objs := nau8825.o
+snd-soc-avs-probe-objs := probe.o
 snd-soc-avs-rt274-objs := rt274.o
 snd-soc-avs-rt286-objs := rt286.o
 snd-soc-avs-rt298-objs := rt298.o
@@ -22,6 +23,7 @@ obj-$(CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98927) += snd-soc-avs-max98927.o
 obj-$(CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98357A) += snd-soc-avs-max98357a.o
 obj-$(CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98373) += snd-soc-avs-max98373.o
 obj-$(CONFIG_SND_SOC_INTEL_AVS_MACH_NAU8825) += snd-soc-avs-nau8825.o
+obj-$(CONFIG_SND_SOC_INTEL_AVS_MACH_PROBE) += snd-soc-avs-probe.o
 obj-$(CONFIG_SND_SOC_INTEL_AVS_MACH_RT274) += snd-soc-avs-rt274.o
 obj-$(CONFIG_SND_SOC_INTEL_AVS_MACH_RT286) += snd-soc-avs-rt286.o
 obj-$(CONFIG_SND_SOC_INTEL_AVS_MACH_RT298) += snd-soc-avs-rt298.o
diff --git a/sound/soc/intel/avs/boards/probe.c b/sound/soc/intel/avs/boards/probe.c
new file mode 100644
index 0000000000000..411acaee74f90
--- /dev/null
+++ b/sound/soc/intel/avs/boards/probe.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
+//
+// Authors: Cezary Rojewski <cezary.rojewski@intel.com>
+//          Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
+//
+
+#include <linux/device.h>
+#include <linux/module.h>
+#include <sound/soc.h>
+#include <sound/soc-acpi.h>
+
+SND_SOC_DAILINK_DEF(dummy, DAILINK_COMP_ARRAY(COMP_DUMMY()));
+SND_SOC_DAILINK_DEF(probe_cp, DAILINK_COMP_ARRAY(COMP_CPU("Probe Extraction CPU DAI")));
+SND_SOC_DAILINK_DEF(platform, DAILINK_COMP_ARRAY(COMP_PLATFORM("probe-platform")));
+
+static struct snd_soc_dai_link probe_mb_dai_links[] = {
+	{
+		.name = "Compress Probe Capture",
+		.nonatomic = 1,
+		SND_SOC_DAILINK_REG(probe_cp, dummy, platform),
+	},
+};
+
+static int avs_probe_mb_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct snd_soc_acpi_mach *mach;
+	struct snd_soc_card *card;
+	int ret;
+
+	mach = dev_get_platdata(dev);
+
+	card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
+	if (!card)
+		return -ENOMEM;
+
+	card->name = "avs_probe_mb";
+	card->dev = dev;
+	card->owner = THIS_MODULE;
+	card->dai_link = probe_mb_dai_links;
+	card->num_links = ARRAY_SIZE(probe_mb_dai_links);
+	card->fully_routed = true;
+
+	ret = snd_soc_fixup_dai_links_platform_name(card, mach->mach_params.platform);
+	if (ret)
+		return ret;
+
+	return devm_snd_soc_register_card(dev, card);
+}
+
+static struct platform_driver avs_probe_mb_driver = {
+	.probe = avs_probe_mb_probe,
+	.driver = {
+		.name = "avs_probe_mb",
+		.pm = &snd_soc_pm_ops,
+	},
+};
+
+module_platform_driver(avs_probe_mb_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:avs_probe_mb");
-- 
GitLab


From 5a565ba23abe478f3d4c3b0c8798bcb5215b82f5 Mon Sep 17 00:00:00 2001
From: Cezary Rojewski <cezary.rojewski@intel.com>
Date: Fri, 2 Dec 2022 16:28:38 +0100
Subject: [PATCH 114/875] ASoC: Intel: avs: Probing and firmware tracing over
 debugfs

Define debugfs subdirectory delegated for IPC communication with DSP.
Input format: uint,uint,(...) which are later translated into DWORDS
sequence and further into instances of struct of interest given the IPC
type.

For Extractor probes, following have been enabled:
- PROBE_POINT_ADD (echo <..> probe_points)
- PROBE_POINT_REMOVE (echo <..> probe_points_remove)
- PROBE_POINT_INFO (cat probe_points)

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20221202152841.672536-14-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/avs/avs.h     |   7 +
 sound/soc/intel/avs/core.c    |   2 +
 sound/soc/intel/avs/debugfs.c | 326 ++++++++++++++++++++++++++++++++++
 3 files changed, 335 insertions(+)

diff --git a/sound/soc/intel/avs/avs.h b/sound/soc/intel/avs/avs.h
index e19d8d89455d1..d7fccdcb9c167 100644
--- a/sound/soc/intel/avs/avs.h
+++ b/sound/soc/intel/avs/avs.h
@@ -144,6 +144,7 @@ struct avs_dev {
 	u32 aging_timer_period;
 	u32 fifo_full_timer_period;
 	u32 logged_resources;	/* context dependent: core or library */
+	struct dentry *debugfs_root;
 	/* probes */
 	struct hdac_ext_stream *extractor;
 	unsigned int num_probe_streams;
@@ -378,6 +379,9 @@ void avs_dump_fw_log(struct avs_dev *adev, const void __iomem *src, unsigned int
 void avs_dump_fw_log_wakeup(struct avs_dev *adev, const void __iomem *src, unsigned int len);
 
 int avs_probe_platform_register(struct avs_dev *adev, const char *name);
+
+void avs_debugfs_init(struct avs_dev *adev);
+void avs_debugfs_exit(struct avs_dev *adev);
 #else
 #define AVS_SET_ENABLE_LOGS_OP(name)
 
@@ -399,6 +403,9 @@ static inline int avs_probe_platform_register(struct avs_dev *adev, const char *
 {
 	return 0;
 }
+
+static inline void avs_debugfs_init(struct avs_dev *adev) { }
+static inline void avs_debugfs_exit(struct avs_dev *adev) { }
 #endif
 
 #endif /* __SOUND_SOC_INTEL_AVS_H */
diff --git a/sound/soc/intel/avs/core.c b/sound/soc/intel/avs/core.c
index f7bc06404dbce..2ca24273c4910 100644
--- a/sound/soc/intel/avs/core.c
+++ b/sound/soc/intel/avs/core.c
@@ -214,6 +214,7 @@ static void avs_hda_probe_work(struct work_struct *work)
 	adev->nhlt = intel_nhlt_init(adev->dev);
 	if (!adev->nhlt)
 		dev_info(bus->dev, "platform has no NHLT\n");
+	avs_debugfs_init(adev);
 
 	avs_register_all_boards(adev);
 
@@ -491,6 +492,7 @@ static void avs_pci_remove(struct pci_dev *pci)
 
 	avs_unregister_all_boards(adev);
 
+	avs_debugfs_exit(adev);
 	if (adev->nhlt)
 		intel_nhlt_free(adev->nhlt);
 
diff --git a/sound/soc/intel/avs/debugfs.c b/sound/soc/intel/avs/debugfs.c
index 78705bcb09fbb..678572ee6b9df 100644
--- a/sound/soc/intel/avs/debugfs.c
+++ b/sound/soc/intel/avs/debugfs.c
@@ -9,7 +9,10 @@
 #include <linux/debugfs.h>
 #include <linux/kfifo.h>
 #include <linux/wait.h>
+#include <linux/sched/signal.h>
+#include <sound/soc.h>
 #include "avs.h"
+#include "messages.h"
 
 static unsigned int __kfifo_fromio(struct kfifo *fifo, const void __iomem *src, unsigned int len)
 {
@@ -44,3 +47,326 @@ void avs_dump_fw_log_wakeup(struct avs_dev *adev, const void __iomem *src, unsig
 	avs_dump_fw_log(adev, src, len);
 	wake_up(&adev->trace_waitq);
 }
+
+static ssize_t probe_points_read(struct file *file, char __user *to, size_t count, loff_t *ppos)
+{
+	struct avs_dev *adev = file->private_data;
+	struct avs_probe_point_desc *desc;
+	size_t num_desc, len = 0;
+	char *buf;
+	int i, ret;
+
+	/* Prevent chaining, send and dump IPC value just once. */
+	if (*ppos)
+		return 0;
+
+	buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
+	if (!buf)
+		return -ENOMEM;
+
+	ret = avs_ipc_probe_get_points(adev, &desc, &num_desc);
+	if (ret) {
+		ret = AVS_IPC_RET(ret);
+		goto exit;
+	}
+
+	for (i = 0; i < num_desc; i++) {
+		ret = snprintf(buf + len, PAGE_SIZE - len,
+			       "Id: %#010x  Purpose: %d  Node id: %#x\n",
+			       desc[i].id.value, desc[i].purpose, desc[i].node_id.val);
+		if (ret < 0)
+			goto free_desc;
+		len += ret;
+	}
+
+	ret = simple_read_from_buffer(to, count, ppos, buf, len);
+free_desc:
+	kfree(desc);
+exit:
+	kfree(buf);
+	return ret;
+}
+
+static ssize_t probe_points_write(struct file *file, const char __user *from, size_t count,
+				  loff_t *ppos)
+{
+	struct avs_dev *adev = file->private_data;
+	struct avs_probe_point_desc *desc;
+	u32 *array, num_elems;
+	size_t bytes;
+	int ret;
+
+	ret = parse_int_array_user(from, count, (int **)&array);
+	if (ret < 0)
+		return ret;
+
+	num_elems = *array;
+	bytes = sizeof(*array) * num_elems;
+	if (bytes % sizeof(*desc)) {
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	desc = (struct avs_probe_point_desc *)&array[1];
+	ret = avs_ipc_probe_connect_points(adev, desc, bytes / sizeof(*desc));
+	if (ret)
+		ret = AVS_IPC_RET(ret);
+	else
+		ret = count;
+exit:
+	kfree(array);
+	return ret;
+}
+
+static const struct file_operations probe_points_fops = {
+	.open = simple_open,
+	.read = probe_points_read,
+	.write = probe_points_write,
+	.llseek = no_llseek,
+};
+
+static ssize_t probe_points_disconnect_write(struct file *file, const char __user *from,
+					     size_t count, loff_t *ppos)
+{
+	struct avs_dev *adev = file->private_data;
+	union avs_probe_point_id *id;
+	u32 *array, num_elems;
+	size_t bytes;
+	int ret;
+
+	ret = parse_int_array_user(from, count, (int **)&array);
+	if (ret < 0)
+		return ret;
+
+	num_elems = *array;
+	bytes = sizeof(*array) * num_elems;
+	if (bytes % sizeof(*id)) {
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	id = (union avs_probe_point_id *)&array[1];
+	ret = avs_ipc_probe_disconnect_points(adev, id, bytes / sizeof(*id));
+	if (ret)
+		ret = AVS_IPC_RET(ret);
+	else
+		ret = count;
+exit:
+	kfree(array);
+	return ret;
+}
+
+static const struct file_operations probe_points_disconnect_fops = {
+	.open = simple_open,
+	.write = probe_points_disconnect_write,
+	.llseek = default_llseek,
+};
+
+static ssize_t strace_read(struct file *file, char __user *to, size_t count, loff_t *ppos)
+{
+	struct avs_dev *adev = file->private_data;
+	struct kfifo *fifo = &adev->trace_fifo;
+	unsigned int copied;
+
+	if (kfifo_is_empty(fifo)) {
+		DEFINE_WAIT(wait);
+
+		prepare_to_wait(&adev->trace_waitq, &wait, TASK_INTERRUPTIBLE);
+		if (!signal_pending(current))
+			schedule();
+		finish_wait(&adev->trace_waitq, &wait);
+	}
+
+	if (kfifo_to_user(fifo, to, count, &copied))
+		return -EFAULT;
+	*ppos += copied;
+	return copied;
+}
+
+static int strace_open(struct inode *inode, struct file *file)
+{
+	struct avs_dev *adev = inode->i_private;
+	int ret;
+
+	if (kfifo_initialized(&adev->trace_fifo))
+		return -EBUSY;
+
+	ret = kfifo_alloc(&adev->trace_fifo, PAGE_SIZE, GFP_KERNEL);
+	if (ret < 0)
+		return ret;
+
+	file->private_data = adev;
+	return 0;
+}
+
+static int strace_release(struct inode *inode, struct file *file)
+{
+	struct avs_dev *adev = file->private_data;
+	unsigned long flags;
+
+	spin_lock_irqsave(&adev->trace_lock, flags);
+	kfifo_free(&adev->trace_fifo);
+	spin_unlock_irqrestore(&adev->trace_lock, flags);
+
+	return 0;
+}
+
+static const struct file_operations strace_fops = {
+	.llseek = default_llseek,
+	.read = strace_read,
+	.open = strace_open,
+	.release = strace_release,
+};
+
+#define DISABLE_TIMERS	UINT_MAX
+
+static int enable_logs(struct avs_dev *adev, u32 resource_mask, u32 *priorities)
+{
+	int ret;
+
+	/* Logging demands D0i0 state from DSP. */
+	if (!adev->logged_resources) {
+		pm_runtime_get_sync(adev->dev);
+
+		ret = avs_dsp_disable_d0ix(adev);
+		if (ret)
+			goto err_d0ix;
+	}
+
+	ret = avs_ipc_set_system_time(adev);
+	if (ret && ret != AVS_IPC_NOT_SUPPORTED) {
+		ret = AVS_IPC_RET(ret);
+		goto err_ipc;
+	}
+
+	ret = avs_dsp_op(adev, enable_logs, AVS_LOG_ENABLE, adev->aging_timer_period,
+			 adev->fifo_full_timer_period, resource_mask, priorities);
+	if (ret)
+		goto err_ipc;
+
+	adev->logged_resources |= resource_mask;
+	return 0;
+
+err_ipc:
+	if (!adev->logged_resources) {
+		avs_dsp_enable_d0ix(adev);
+err_d0ix:
+		pm_runtime_mark_last_busy(adev->dev);
+		pm_runtime_put_autosuspend(adev->dev);
+	}
+
+	return ret;
+}
+
+static int disable_logs(struct avs_dev *adev, u32 resource_mask)
+{
+	int ret;
+
+	/* Check if there's anything to do. */
+	if (!adev->logged_resources)
+		return 0;
+
+	ret = avs_dsp_op(adev, enable_logs, AVS_LOG_DISABLE, DISABLE_TIMERS, DISABLE_TIMERS,
+			 resource_mask, NULL);
+
+	/*
+	 * If IPC fails causing recovery, logged_resources is already zero
+	 * so unsetting bits is still safe.
+	 */
+	adev->logged_resources &= ~resource_mask;
+
+	/* If that's the last resource, allow for D3. */
+	if (!adev->logged_resources) {
+		avs_dsp_enable_d0ix(adev);
+		pm_runtime_mark_last_busy(adev->dev);
+		pm_runtime_put_autosuspend(adev->dev);
+	}
+
+	return ret;
+}
+
+static ssize_t trace_control_read(struct file *file, char __user *to, size_t count, loff_t *ppos)
+{
+	struct avs_dev *adev = file->private_data;
+	char buf[64];
+	int len;
+
+	len = snprintf(buf, sizeof(buf), "0x%08x\n", adev->logged_resources);
+
+	return simple_read_from_buffer(to, count, ppos, buf, len);
+}
+
+static ssize_t trace_control_write(struct file *file, const char __user *from, size_t count,
+				   loff_t *ppos)
+{
+	struct avs_dev *adev = file->private_data;
+	u32 *array, num_elems;
+	u32 resource_mask;
+	int ret;
+
+	ret = parse_int_array_user(from, count, (int **)&array);
+	if (ret < 0)
+		return ret;
+
+	num_elems = *array;
+	resource_mask = array[1];
+
+	/*
+	 * Disable if just resource mask is provided - no log priority flags.
+	 *
+	 * Enable input format:   mask, prio1, .., prioN
+	 * Where 'N' equals number of bits set in the 'mask'.
+	 */
+	if (num_elems == 1) {
+		ret = disable_logs(adev, resource_mask);
+	} else {
+		if (num_elems != (hweight_long(resource_mask) + 1)) {
+			ret = -EINVAL;
+			goto free_array;
+		}
+
+		ret = enable_logs(adev, resource_mask, &array[2]);
+	}
+
+	if (!ret)
+		ret = count;
+free_array:
+	kfree(array);
+	return ret;
+}
+
+static const struct file_operations trace_control_fops = {
+	.llseek = default_llseek,
+	.read = trace_control_read,
+	.write = trace_control_write,
+	.open = simple_open,
+};
+
+void avs_debugfs_init(struct avs_dev *adev)
+{
+	init_waitqueue_head(&adev->trace_waitq);
+	spin_lock_init(&adev->trace_lock);
+
+	adev->debugfs_root = debugfs_create_dir("avs", snd_soc_debugfs_root);
+
+	/* Initialize timer periods with recommended defaults. */
+	adev->aging_timer_period = 10;
+	adev->fifo_full_timer_period = 10;
+
+	debugfs_create_file("strace", 0444, adev->debugfs_root, adev, &strace_fops);
+	debugfs_create_file("trace_control", 0644, adev->debugfs_root, adev, &trace_control_fops);
+
+	debugfs_create_u32("trace_aging_period", 0644, adev->debugfs_root,
+			   &adev->aging_timer_period);
+	debugfs_create_u32("trace_fifo_full_period", 0644, adev->debugfs_root,
+			   &adev->fifo_full_timer_period);
+
+	debugfs_create_file("probe_points", 0644, adev->debugfs_root, adev, &probe_points_fops);
+	debugfs_create_file("probe_points_disconnect", 0200, adev->debugfs_root, adev,
+			    &probe_points_disconnect_fops);
+}
+
+void avs_debugfs_exit(struct avs_dev *adev)
+{
+	debugfs_remove_recursive(adev->debugfs_root);
+}
-- 
GitLab


From 34d27c71707c4ed615105376e0f3907d99b1b271 Mon Sep 17 00:00:00 2001
From: Cezary Rojewski <cezary.rojewski@intel.com>
Date: Fri, 2 Dec 2022 16:28:39 +0100
Subject: [PATCH 115/875] ASoC: Intel: avs: Gather remaining logs on
 strace_release()

When user closes the tracer, some logs may still remain in the tail of
the buffer as firmware sends LOG_BUFFER_STATUS notification only when
certain threshold of data is reached. Add whatever is left to already
gathered logs so no information is lost.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20221202152841.672536-15-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/avs/debugfs.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/sound/soc/intel/avs/debugfs.c b/sound/soc/intel/avs/debugfs.c
index 678572ee6b9df..e7b0b99824aa1 100644
--- a/sound/soc/intel/avs/debugfs.c
+++ b/sound/soc/intel/avs/debugfs.c
@@ -201,11 +201,25 @@ static int strace_open(struct inode *inode, struct file *file)
 
 static int strace_release(struct inode *inode, struct file *file)
 {
+	union avs_notify_msg msg = AVS_NOTIFICATION(LOG_BUFFER_STATUS);
 	struct avs_dev *adev = file->private_data;
-	unsigned long flags;
+	unsigned long resource_mask;
+	unsigned long flags, i;
+	u32 num_cores;
+
+	resource_mask = adev->logged_resources;
+	num_cores = adev->hw_cfg.dsp_cores;
 
 	spin_lock_irqsave(&adev->trace_lock, flags);
+
+	/* Gather any remaining logs. */
+	for_each_set_bit(i, &resource_mask, num_cores) {
+		msg.log.core = i;
+		avs_dsp_op(adev, log_buffer_status, &msg);
+	}
+
 	kfifo_free(&adev->trace_fifo);
+
 	spin_unlock_irqrestore(&adev->trace_lock, flags);
 
 	return 0;
-- 
GitLab


From 870f6e5abba95ac78e750b61cf8f3f15be96796f Mon Sep 17 00:00:00 2001
From: Cezary Rojewski <cezary.rojewski@intel.com>
Date: Fri, 2 Dec 2022 16:28:40 +0100
Subject: [PATCH 116/875] ASoC: Intel: avs: Allow for dumping FW_REGS area

SRAM0 window begins with a block of memory, usually of size PAGE_SIZE,
dedicated to the base firmware registers. When debugging firmware, it is
desirable to be able to dump them at will.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20221202152841.672536-16-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/avs/debugfs.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/sound/soc/intel/avs/debugfs.c b/sound/soc/intel/avs/debugfs.c
index e7b0b99824aa1..e9042d4328c41 100644
--- a/sound/soc/intel/avs/debugfs.c
+++ b/sound/soc/intel/avs/debugfs.c
@@ -48,6 +48,29 @@ void avs_dump_fw_log_wakeup(struct avs_dev *adev, const void __iomem *src, unsig
 	wake_up(&adev->trace_waitq);
 }
 
+static ssize_t fw_regs_read(struct file *file, char __user *to, size_t count, loff_t *ppos)
+{
+	struct avs_dev *adev = file->private_data;
+	char *buf;
+	int ret;
+
+	buf = kzalloc(AVS_FW_REGS_SIZE, GFP_KERNEL);
+	if (!buf)
+		return -ENOMEM;
+
+	memcpy_fromio(buf, avs_sram_addr(adev, AVS_FW_REGS_WINDOW), AVS_FW_REGS_SIZE);
+
+	ret = simple_read_from_buffer(to, count, ppos, buf, AVS_FW_REGS_SIZE);
+	kfree(buf);
+	return ret;
+}
+
+static const struct file_operations fw_regs_fops = {
+	.open = simple_open,
+	.read = fw_regs_read,
+	.llseek = no_llseek,
+};
+
 static ssize_t probe_points_read(struct file *file, char __user *to, size_t count, loff_t *ppos)
 {
 	struct avs_dev *adev = file->private_data;
@@ -369,6 +392,7 @@ void avs_debugfs_init(struct avs_dev *adev)
 
 	debugfs_create_file("strace", 0444, adev->debugfs_root, adev, &strace_fops);
 	debugfs_create_file("trace_control", 0644, adev->debugfs_root, adev, &trace_control_fops);
+	debugfs_create_file("fw_regs", 0444, adev->debugfs_root, adev, &fw_regs_fops);
 
 	debugfs_create_u32("trace_aging_period", 0644, adev->debugfs_root,
 			   &adev->aging_timer_period);
-- 
GitLab


From 85ac9c8c8eed76e8a320a9e017c6d36e2a52745b Mon Sep 17 00:00:00 2001
From: Cezary Rojewski <cezary.rojewski@intel.com>
Date: Fri, 2 Dec 2022 16:28:41 +0100
Subject: [PATCH 117/875] ASoC: Intel: avs: Allow for dumping debug window
 snapshot

Add new read-only debugfs entry which dumps entire content of the SRAM
window 2 i.e.: the debug window.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20221202152841.672536-17-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/avs/debugfs.c   | 26 ++++++++++++++++++++++++++
 sound/soc/intel/avs/registers.h |  3 ++-
 2 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/sound/soc/intel/avs/debugfs.c b/sound/soc/intel/avs/debugfs.c
index e9042d4328c41..bdd388ec01eaf 100644
--- a/sound/soc/intel/avs/debugfs.c
+++ b/sound/soc/intel/avs/debugfs.c
@@ -71,6 +71,31 @@ static const struct file_operations fw_regs_fops = {
 	.llseek = no_llseek,
 };
 
+static ssize_t debug_window_read(struct file *file, char __user *to, size_t count, loff_t *ppos)
+{
+	struct avs_dev *adev = file->private_data;
+	size_t size;
+	char *buf;
+	int ret;
+
+	size = adev->hw_cfg.dsp_cores * AVS_WINDOW_CHUNK_SIZE;
+	buf = kzalloc(size, GFP_KERNEL);
+	if (!buf)
+		return -ENOMEM;
+
+	memcpy_fromio(buf, avs_sram_addr(adev, AVS_DEBUG_WINDOW), size);
+
+	ret = simple_read_from_buffer(to, count, ppos, buf, size);
+	kfree(buf);
+	return ret;
+}
+
+static const struct file_operations debug_window_fops = {
+	.open = simple_open,
+	.read = debug_window_read,
+	.llseek = no_llseek,
+};
+
 static ssize_t probe_points_read(struct file *file, char __user *to, size_t count, loff_t *ppos)
 {
 	struct avs_dev *adev = file->private_data;
@@ -393,6 +418,7 @@ void avs_debugfs_init(struct avs_dev *adev)
 	debugfs_create_file("strace", 0444, adev->debugfs_root, adev, &strace_fops);
 	debugfs_create_file("trace_control", 0644, adev->debugfs_root, adev, &trace_control_fops);
 	debugfs_create_file("fw_regs", 0444, adev->debugfs_root, adev, &fw_regs_fops);
+	debugfs_create_file("debug_window", 0444, adev->debugfs_root, adev, &debug_window_fops);
 
 	debugfs_create_u32("trace_aging_period", 0644, adev->debugfs_root,
 			   &adev->aging_timer_period);
diff --git a/sound/soc/intel/avs/registers.h b/sound/soc/intel/avs/registers.h
index 95be86148cf3a..2b464e466ed52 100644
--- a/sound/soc/intel/avs/registers.h
+++ b/sound/soc/intel/avs/registers.h
@@ -59,7 +59,8 @@
 #define AVS_FW_REG_STATUS(adev)		(AVS_FW_REG_BASE(adev) + 0x0)
 #define AVS_FW_REG_ERROR_CODE(adev)	(AVS_FW_REG_BASE(adev) + 0x4)
 
-#define AVS_FW_REGS_SIZE		PAGE_SIZE
+#define AVS_WINDOW_CHUNK_SIZE		PAGE_SIZE
+#define AVS_FW_REGS_SIZE		AVS_WINDOW_CHUNK_SIZE
 #define AVS_FW_REGS_WINDOW		0
 /* DSP -> HOST communication window */
 #define AVS_UPLINK_WINDOW		AVS_FW_REGS_WINDOW
-- 
GitLab


From 1b41beaa7a58467505ec3023af8aad74f878b888 Mon Sep 17 00:00:00 2001
From: Yang Yingliang <yangyingliang@huawei.com>
Date: Mon, 5 Dec 2022 22:37:21 +0800
Subject: [PATCH 118/875] ASoC: sof_es8336: fix possible use-after-free in
 sof_es8336_remove()

sof_es8336_remove() calls cancel_delayed_work(). However, that
function does not wait until the work function finishes. This
means that the callback function may still be running after
the driver's remove function has finished, which would result
in a use-after-free.

Fix by calling cancel_delayed_work_sync(), which ensures that
the work is properly cancelled, no longer running, and unable
to re-schedule itself.

Fixes: 89cdb224f2ab ("ASoC: sof_es8336: reduce pop noise on speaker")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Acked-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20221205143721.3988988-1-yangyingliang@huawei.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/boards/sof_es8336.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/intel/boards/sof_es8336.c b/sound/soc/intel/boards/sof_es8336.c
index 70713e4b07dc1..773e5d1d87d46 100644
--- a/sound/soc/intel/boards/sof_es8336.c
+++ b/sound/soc/intel/boards/sof_es8336.c
@@ -783,7 +783,7 @@ static int sof_es8336_remove(struct platform_device *pdev)
 	struct snd_soc_card *card = platform_get_drvdata(pdev);
 	struct sof_es8336_private *priv = snd_soc_card_get_drvdata(card);
 
-	cancel_delayed_work(&priv->pcm_pop_work);
+	cancel_delayed_work_sync(&priv->pcm_pop_work);
 	gpiod_put(priv->gpio_speakers);
 	device_remove_software_node(priv->codec_dev);
 	put_device(priv->codec_dev);
-- 
GitLab


From 8e4c2eee1e15c1206c26f6b28b05fe9711a427c6 Mon Sep 17 00:00:00 2001
From: Christian Schoenebeck <linux_oss@crudebyte.com>
Date: Tue, 22 Nov 2022 20:20:22 +0100
Subject: [PATCH 119/875] net/9p: distinguish zero-copy requests

Add boolean `zc` member to struct p9_fcall to distinguish zero-copy
messages (not using the linear `sdata` buffer for message payload) from
regular messages (which do copy message payload to `sdata` before being
further processed).

This new member is appended to end of structure to avoid inserting huge
padding in generated layout.

Link: https://lkml.kernel.org/r/8f2a5c12a446c3b544da64e0b1550e1fb2d6f972.1669144861.git.linux_oss@crudebyte.com
Signed-off-by: Christian Schoenebeck <linux_oss@crudebyte.com>
Tested-by: Stefano Stabellini <sstabellini@kernel.org>
Signed-off-by: Dominique Martinet <asmadeus@codewreck.org>
---
 include/net/9p/9p.h | 2 ++
 net/9p/client.c     | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/include/net/9p/9p.h b/include/net/9p/9p.h
index 13abe013af21c..429adf6be29cd 100644
--- a/include/net/9p/9p.h
+++ b/include/net/9p/9p.h
@@ -531,6 +531,7 @@ struct p9_rstatfs {
  * @offset: used by marshalling routines to track current position in buffer
  * @capacity: used by marshalling routines to track total malloc'd capacity
  * @sdata: payload
+ * @zc: whether zero-copy is used
  *
  * &p9_fcall represents the structure for all 9P RPC
  * transactions.  Requests are packaged into fcalls, and reponses
@@ -549,6 +550,7 @@ struct p9_fcall {
 
 	struct kmem_cache *cache;
 	u8 *sdata;
+	bool zc;
 };
 
 int p9_errstr2errno(char *errstr, int len);
diff --git a/net/9p/client.c b/net/9p/client.c
index b554f8357f967..a2b4a965a5a99 100644
--- a/net/9p/client.c
+++ b/net/9p/client.c
@@ -685,6 +685,9 @@ p9_client_rpc(struct p9_client *c, int8_t type, const char *fmt, ...)
 	if (IS_ERR(req))
 		return req;
 
+	req->tc.zc = false;
+	req->rc.zc = false;
+
 	if (signal_pending(current)) {
 		sigpending = 1;
 		clear_thread_flag(TIF_SIGPENDING);
@@ -783,6 +786,9 @@ static struct p9_req_t *p9_client_zc_rpc(struct p9_client *c, int8_t type,
 	if (IS_ERR(req))
 		return req;
 
+	req->tc.zc = true;
+	req->rc.zc = true;
+
 	if (signal_pending(current)) {
 		sigpending = 1;
 		clear_thread_flag(TIF_SIGPENDING);
-- 
GitLab


From a31b3cffbd8e5d032dcb267bf94ee48d71c1a28b Mon Sep 17 00:00:00 2001
From: Christian Schoenebeck <linux_oss@crudebyte.com>
Date: Tue, 22 Nov 2022 20:20:29 +0100
Subject: [PATCH 120/875] net/9p: fix response size check in p9_check_errors()

Since commit 60ece0833b6c ("net/9p: allocate appropriate reduced message
buffers") it is no longer appropriate to check server's response size
against msize. Check against the previously allocated buffer capacity
instead.

- Omit this size check entirely for zero-copy messages, as those always
  allocate 4k (P9_ZC_HDR_SZ) linear buffers which are not used for actual
  payload and can be much bigger than 4k.

- Replace p9_debug() by pr_err() to make sure this message is always
  printed in case this error is triggered.

- Add 9p message type to error message to ease investigation.

Link: https://lkml.kernel.org/r/e0edec84b1c80119ae937ce854b4f5f6dbe2d08c.1669144861.git.linux_oss@crudebyte.com
Signed-off-by: Christian Schoenebeck <linux_oss@crudebyte.com>
Tested-by: Stefano Stabellini <sstabellini@kernel.org>
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Dominique Martinet <asmadeus@codewreck.org>
---
 net/9p/client.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/net/9p/client.c b/net/9p/client.c
index a2b4a965a5a99..7b2a997662d9c 100644
--- a/net/9p/client.c
+++ b/net/9p/client.c
@@ -519,10 +519,9 @@ static int p9_check_errors(struct p9_client *c, struct p9_req_t *req)
 	int ecode;
 
 	err = p9_parse_header(&req->rc, NULL, &type, NULL, 0);
-	if (req->rc.size >= c->msize) {
-		p9_debug(P9_DEBUG_ERROR,
-			 "requested packet size too big: %d\n",
-			 req->rc.size);
+	if (req->rc.size > req->rc.capacity && !req->rc.zc) {
+		pr_err("requested packet size too big: %d does not fit %zu (type=%d)\n",
+		       req->rc.size, req->rc.capacity, req->rc.id);
 		return -EIO;
 	}
 	/* dump the response from server
-- 
GitLab


From 45558b3abb87eeb2cedb8a59cb2699c120b5102a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 2 Dec 2022 19:35:05 +0100
Subject: [PATCH 121/875] pwm: sifive: Call pwm_sifive_update_clock() while
 mutex is held
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

As was documented in commit 0f02f491b786 ("pwm: sifive: Reduce time the
controller lock is held") a caller of pwm_sifive_update_clock() must
hold the mutex. So fix pwm_sifive_clock_notifier() to grab the lock.

While this necessity was only documented later, the race exists since
the driver was introduced.

Fixes: 9e37a53eb051 ("pwm: sifive: Add a driver for SiFive SoC PWM")
Reported-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Link: https://lore.kernel.org/r/20221018061656.1428111-1-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-sifive.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c
index 2d4fa5e5fdd46..bb72393134016 100644
--- a/drivers/pwm/pwm-sifive.c
+++ b/drivers/pwm/pwm-sifive.c
@@ -204,8 +204,11 @@ static int pwm_sifive_clock_notifier(struct notifier_block *nb,
 	struct pwm_sifive_ddata *ddata =
 		container_of(nb, struct pwm_sifive_ddata, notifier);
 
-	if (event == POST_RATE_CHANGE)
+	if (event == POST_RATE_CHANGE) {
+		mutex_lock(&ddata->lock);
 		pwm_sifive_update_clock(ddata, ndata->new_rate);
+		mutex_unlock(&ddata->lock);
+	}
 
 	return NOTIFY_OK;
 }
-- 
GitLab


From 0b5ef3429d8f78427558ab0dcbfd862098ba2a63 Mon Sep 17 00:00:00 2001
From: xinlei lee <xinlei.lee@mediatek.com>
Date: Fri, 2 Dec 2022 19:35:06 +0100
Subject: [PATCH 122/875] pwm: mtk-disp: Fix the parameters calculated by the
 enabled flag of disp_pwm
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

In the original mtk_disp_pwm_get_state() function wrongly uses bit 0 of
CON0 to judge if the PWM is enabled.
However that is indicated by a bit (at a machine dependent position) in
the DISP_PWM_EN register. Fix this accordingly.

Fixes: 3f2b16734914 ("pwm: mtk-disp: Implement atomic API .get_state()")
Signed-off-by: xinlei lee <xinlei.lee@mediatek.com>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/1666172538-11652-1-git-send-email-xinlei.lee@mediatek.com
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-mtk-disp.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c
index c605013e4114c..3fbb4bae93a4e 100644
--- a/drivers/pwm/pwm-mtk-disp.c
+++ b/drivers/pwm/pwm-mtk-disp.c
@@ -178,7 +178,7 @@ static void mtk_disp_pwm_get_state(struct pwm_chip *chip,
 {
 	struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
 	u64 rate, period, high_width;
-	u32 clk_div, con0, con1;
+	u32 clk_div, pwm_en, con0, con1;
 	int err;
 
 	err = clk_prepare_enable(mdp->clk_main);
@@ -197,7 +197,8 @@ static void mtk_disp_pwm_get_state(struct pwm_chip *chip,
 	rate = clk_get_rate(mdp->clk_main);
 	con0 = readl(mdp->base + mdp->data->con0);
 	con1 = readl(mdp->base + mdp->data->con1);
-	state->enabled = !!(con0 & BIT(0));
+	pwm_en = readl(mdp->base + DISP_PWM_EN);
+	state->enabled = !!(pwm_en & mdp->data->enable_mask);
 	clk_div = FIELD_GET(PWM_CLKDIV_MASK, con0);
 	period = FIELD_GET(PWM_PERIOD_MASK, con1);
 	/*
-- 
GitLab


From 07d8d8d29aa76f3c28020a9c914cc890eb86a48c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 2 Dec 2022 19:35:07 +0100
Subject: [PATCH 123/875] pwm: lpc18xx-sct: Fix a comment to match code
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

lpc18xx_pwm_probe() only ensures clk_rate <= NSEC_PER_SEC, the following
reasoning is right even under this slightly lesser condition.

Fixes: 8933d30c5f46 ("pwm: lpc18xx: Fix period handling")
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Link: https://lore.kernel.org/r/20221108153013.132514-1-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-lpc18xx-sct.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pwm/pwm-lpc18xx-sct.c b/drivers/pwm/pwm-lpc18xx-sct.c
index 763f2e3a146d5..378e1df944dc0 100644
--- a/drivers/pwm/pwm-lpc18xx-sct.c
+++ b/drivers/pwm/pwm-lpc18xx-sct.c
@@ -175,7 +175,7 @@ static void lpc18xx_pwm_config_duty(struct pwm_chip *chip,
 	u32 val;
 
 	/*
-	 * With clk_rate < NSEC_PER_SEC this cannot overflow.
+	 * With clk_rate <= NSEC_PER_SEC this cannot overflow.
 	 * With duty_ns <= period_ns < max_period_ns this also fits into an u32.
 	 */
 	val = mul_u64_u64_div_u64(duty_ns, lpc18xx_pwm->clk_rate, NSEC_PER_SEC);
-- 
GitLab


From aa3c668f2f98856af96e13f44da6ca4f26f0b98c Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Fri, 2 Dec 2022 19:35:08 +0100
Subject: [PATCH 124/875] pwm: mediatek: always use bus clock for PWM on MT7622
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

According to MT7622 Reference Manual for Development Board v1.0 the PWM
unit found in the MT7622 SoC also comes with the PWM_CK_26M_SEL register
at offset 0x210 just like other modern MediaTek ARM64 SoCs.
And also MT7622 sets that register to 0x00000001 on reset which is
described as 'Select 26M fix CLK as BCLK' in the datasheet.
Hence set has_ck_26m_sel to true also for MT7622 which results in the
driver writing 0 to the PWM_CK_26M_SEL register which is described as
'Select bus CLK as BCLK'.

Fixes: 0c0ead76235db0 ("pwm: mediatek: Always use bus clock")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/Y1iF2slvSblf6bYK@makrotopia.org
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-mediatek.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
index 6901a44dc428d..a337b47dc2f7d 100644
--- a/drivers/pwm/pwm-mediatek.c
+++ b/drivers/pwm/pwm-mediatek.c
@@ -296,7 +296,7 @@ static const struct pwm_mediatek_of_data mt6795_pwm_data = {
 static const struct pwm_mediatek_of_data mt7622_pwm_data = {
 	.num_pwms = 6,
 	.pwm45_fixup = false,
-	.has_ck_26m_sel = false,
+	.has_ck_26m_sel = true,
 };
 
 static const struct pwm_mediatek_of_data mt7623_pwm_data = {
-- 
GitLab


From e51b156b18fb6d34a1e409d153040a02adb5c7e0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 2 Dec 2022 19:35:09 +0100
Subject: [PATCH 125/875] pwm: Document variables protected by pwm_lock
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

To simplify validation of the used locking, document for the global pwm
mutex what it actually protects against concurrent access. Also note for
two functions modifying these that pwm_lock is held by the caller.

Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20221117211143.3817381-2-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/core.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
index d333e7422f4a9..ebe06efe9de52 100644
--- a/drivers/pwm/core.c
+++ b/drivers/pwm/core.c
@@ -27,7 +27,10 @@
 
 static DEFINE_MUTEX(pwm_lookup_lock);
 static LIST_HEAD(pwm_lookup_list);
+
+/* protects access to pwm_chips, allocated_pwms, and pwm_tree */
 static DEFINE_MUTEX(pwm_lock);
+
 static LIST_HEAD(pwm_chips);
 static DECLARE_BITMAP(allocated_pwms, MAX_PWMS);
 static RADIX_TREE(pwm_tree, GFP_KERNEL);
@@ -37,6 +40,7 @@ static struct pwm_device *pwm_to_device(unsigned int pwm)
 	return radix_tree_lookup(&pwm_tree, pwm);
 }
 
+/* Called with pwm_lock held */
 static int alloc_pwms(unsigned int count)
 {
 	unsigned int start;
@@ -50,6 +54,7 @@ static int alloc_pwms(unsigned int count)
 	return start;
 }
 
+/* Called with pwm_lock held */
 static void free_pwms(struct pwm_chip *chip)
 {
 	unsigned int i;
-- 
GitLab


From c8135b5174145a65c72c4303f2752cc8cecf8d08 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 2 Dec 2022 19:35:10 +0100
Subject: [PATCH 126/875] pwm: Reduce time the pwm_lock mutex is held in
 pwmchip_add()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This simplifies error handling as the need for goto error handling goes
away and at the end of the function the code can be simplified as this
code isn't used in the error case any more.

Now memory allocation and the call to of_pwmchip_add() are done without
holding the lock. Both don't access the data structures protected by
&pwm_lock.

Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20221117211143.3817381-3-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/core.c | 27 ++++++++++++---------------
 1 file changed, 12 insertions(+), 15 deletions(-)

diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
index ebe06efe9de52..2338119a09d89 100644
--- a/drivers/pwm/core.c
+++ b/drivers/pwm/core.c
@@ -272,20 +272,21 @@ int pwmchip_add(struct pwm_chip *chip)
 	if (!pwm_ops_check(chip))
 		return -EINVAL;
 
+	chip->pwms = kcalloc(chip->npwm, sizeof(*pwm), GFP_KERNEL);
+	if (!chip->pwms)
+		return -ENOMEM;
+
 	mutex_lock(&pwm_lock);
 
 	ret = alloc_pwms(chip->npwm);
-	if (ret < 0)
-		goto out;
+	if (ret < 0) {
+		mutex_unlock(&pwm_lock);
+		kfree(chip->pwms);
+		return ret;
+	}
 
 	chip->base = ret;
 
-	chip->pwms = kcalloc(chip->npwm, sizeof(*pwm), GFP_KERNEL);
-	if (!chip->pwms) {
-		ret = -ENOMEM;
-		goto out;
-	}
-
 	for (i = 0; i < chip->npwm; i++) {
 		pwm = &chip->pwms[i];
 
@@ -301,18 +302,14 @@ int pwmchip_add(struct pwm_chip *chip)
 	INIT_LIST_HEAD(&chip->list);
 	list_add(&chip->list, &pwm_chips);
 
-	ret = 0;
+	mutex_unlock(&pwm_lock);
 
 	if (IS_ENABLED(CONFIG_OF))
 		of_pwmchip_add(chip);
 
-out:
-	mutex_unlock(&pwm_lock);
-
-	if (!ret)
-		pwmchip_sysfs_export(chip);
+	pwmchip_sysfs_export(chip);
 
-	return ret;
+	return 0;
 }
 EXPORT_SYMBOL_GPL(pwmchip_add);
 
-- 
GitLab


From 4034e5944884dca1673e52cc392b07d0d35b6ff0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 2 Dec 2022 19:35:11 +0100
Subject: [PATCH 127/875] pwm: Mark free pwm IDs as used in alloc_pwms()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

alloc_pwms() only identified a free range of IDs and this range was marked
as used only later by pwmchip_add(). Instead let alloc_pwms() already do
the marking (which makes the function actually allocating the range and so
justifies the function name). This way access to the allocated_pwms
bitfield is limited to two functions only.

Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20221117211143.3817381-4-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
index 2338119a09d89..b43b24bd3c9f1 100644
--- a/drivers/pwm/core.c
+++ b/drivers/pwm/core.c
@@ -51,6 +51,8 @@ static int alloc_pwms(unsigned int count)
 	if (start + count > MAX_PWMS)
 		return -ENOSPC;
 
+	bitmap_set(allocated_pwms, start, count);
+
 	return start;
 }
 
@@ -297,8 +299,6 @@ int pwmchip_add(struct pwm_chip *chip)
 		radix_tree_insert(&pwm_tree, pwm->pwm, pwm);
 	}
 
-	bitmap_set(allocated_pwms, chip->base, chip->npwm);
-
 	INIT_LIST_HEAD(&chip->list);
 	list_add(&chip->list, &pwm_chips);
 
-- 
GitLab


From fa1b9aa4492cc4f29178ef38ca0467c48714250e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 2 Dec 2022 19:35:12 +0100
Subject: [PATCH 128/875] pwm: Don't initialize list head before calling
 list_add()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

list_add() just overwrites the members of the element to add (here:
chip->list) without any checks, even in the DEBUG_LIST case. So save the
effort to initialize the list.

Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20221117211143.3817381-5-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/core.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
index b43b24bd3c9f1..61bacd8d9b44c 100644
--- a/drivers/pwm/core.c
+++ b/drivers/pwm/core.c
@@ -299,7 +299,6 @@ int pwmchip_add(struct pwm_chip *chip)
 		radix_tree_insert(&pwm_tree, pwm->pwm, pwm);
 	}
 
-	INIT_LIST_HEAD(&chip->list);
 	list_add(&chip->list, &pwm_chips);
 
 	mutex_unlock(&pwm_lock);
-- 
GitLab


From 55f363e19cb8ca65400eeb11d716519609fbeae6 Mon Sep 17 00:00:00 2001
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Date: Fri, 2 Dec 2022 19:35:13 +0100
Subject: [PATCH 129/875] pwm: core: Remove S_IFREG from debugfs_create_file()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The debugfs_create_file() already has a check and adds S_IFREG
automatically. Remove unneeded flag.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20221117165812.27757-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/core.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
index 61bacd8d9b44c..3a0967209853f 100644
--- a/drivers/pwm/core.c
+++ b/drivers/pwm/core.c
@@ -1180,8 +1180,7 @@ DEFINE_SEQ_ATTRIBUTE(pwm_debugfs);
 
 static int __init pwm_debugfs_init(void)
 {
-	debugfs_create_file("pwm", S_IFREG | 0444, NULL, NULL,
-			    &pwm_debugfs_fops);
+	debugfs_create_file("pwm", 0444, NULL, NULL, &pwm_debugfs_fops);
 
 	return 0;
 }
-- 
GitLab


From c637d87a7d96bd04674515b879b500f66361b74c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 2 Dec 2022 19:35:14 +0100
Subject: [PATCH 130/875] pwm: fsl-ftm: Use regmap_clear_bits and
 regmap_set_bits where applicable
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Found using coccinelle and the following semantic patch:

@@
expression map, reg, bits;
@@

- regmap_update_bits(map, reg, bits, bits)
+ regmap_set_bits(map, reg, bits)

@@
expression map, reg, bits;
@@

- regmap_update_bits(map, reg, bits, 0)
+ regmap_clear_bits(map, reg, bits)

Link: https://lore.kernel.org/r/20221115111347.3705732-2-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-fsl-ftm.c | 18 +++++++-----------
 1 file changed, 7 insertions(+), 11 deletions(-)

diff --git a/drivers/pwm/pwm-fsl-ftm.c b/drivers/pwm/pwm-fsl-ftm.c
index 0247757f9a72d..5caadbd6194e0 100644
--- a/drivers/pwm/pwm-fsl-ftm.c
+++ b/drivers/pwm/pwm-fsl-ftm.c
@@ -65,13 +65,12 @@ static void ftm_clear_write_protection(struct fsl_pwm_chip *fpc)
 
 	regmap_read(fpc->regmap, FTM_FMS, &val);
 	if (val & FTM_FMS_WPEN)
-		regmap_update_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS,
-				   FTM_MODE_WPDIS);
+		regmap_set_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS);
 }
 
 static void ftm_set_write_protection(struct fsl_pwm_chip *fpc)
 {
-	regmap_update_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN, FTM_FMS_WPEN);
+	regmap_set_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN);
 }
 
 static bool fsl_pwm_periodcfg_are_equal(const struct fsl_pwm_periodcfg *a,
@@ -94,8 +93,7 @@ static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
 	ret = clk_prepare_enable(fpc->ipg_clk);
 	if (!ret && fpc->soc->has_enable_bits) {
 		mutex_lock(&fpc->lock);
-		regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
-				   BIT(pwm->hwpwm + 16));
+		regmap_set_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
 		mutex_unlock(&fpc->lock);
 	}
 
@@ -108,8 +106,7 @@ static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
 
 	if (fpc->soc->has_enable_bits) {
 		mutex_lock(&fpc->lock);
-		regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
-				   0);
+		regmap_clear_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
 		mutex_unlock(&fpc->lock);
 	}
 
@@ -317,8 +314,8 @@ static int fsl_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 
 	if (!newstate->enabled) {
 		if (oldstate->enabled) {
-			regmap_update_bits(fpc->regmap, FTM_OUTMASK,
-					   BIT(pwm->hwpwm), BIT(pwm->hwpwm));
+			regmap_set_bits(fpc->regmap, FTM_OUTMASK,
+					BIT(pwm->hwpwm));
 			clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
 			clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
 		}
@@ -342,8 +339,7 @@ static int fsl_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 			goto end_mutex;
 		}
 
-		regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm),
-				   0);
+		regmap_clear_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm));
 	}
 
 end_mutex:
-- 
GitLab


From 50f2151034b65125b6cce6b385ce8b74556e45f6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 2 Dec 2022 19:35:15 +0100
Subject: [PATCH 131/875] pwm: img: Use regmap_clear_bits and regmap_set_bits
 where applicable
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Found using coccinelle and the following semantic patch:

@@
expression map, reg, bits;
@@

- regmap_update_bits(map, reg, bits, bits)
+ regmap_set_bits(map, reg, bits)

@@
expression map, reg, bits;
@@

- regmap_update_bits(map, reg, bits, 0)
+ regmap_clear_bits(map, reg, bits)

Link: https://lore.kernel.org/r/20221115111347.3705732-3-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-img.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/pwm/pwm-img.c b/drivers/pwm/pwm-img.c
index 0fccf061ab958..89362afe3c914 100644
--- a/drivers/pwm/pwm-img.c
+++ b/drivers/pwm/pwm-img.c
@@ -161,9 +161,9 @@ static int img_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 	val |= BIT(pwm->hwpwm);
 	img_pwm_writel(imgchip, PWM_CTRL_CFG, val);
 
-	regmap_update_bits(imgchip->periph_regs, PERIP_PWM_PDM_CONTROL,
-			   PERIP_PWM_PDM_CONTROL_CH_MASK <<
-			   PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm), 0);
+	regmap_clear_bits(imgchip->periph_regs, PERIP_PWM_PDM_CONTROL,
+			  PERIP_PWM_PDM_CONTROL_CH_MASK <<
+			  PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm));
 
 	return 0;
 }
@@ -397,11 +397,10 @@ static int img_pwm_resume(struct device *dev)
 
 	for (i = 0; i < imgchip->chip.npwm; i++)
 		if (imgchip->suspend_ctrl_cfg & BIT(i))
-			regmap_update_bits(imgchip->periph_regs,
-					   PERIP_PWM_PDM_CONTROL,
-					   PERIP_PWM_PDM_CONTROL_CH_MASK <<
-					   PERIP_PWM_PDM_CONTROL_CH_SHIFT(i),
-					   0);
+			regmap_clear_bits(imgchip->periph_regs,
+					  PERIP_PWM_PDM_CONTROL,
+					  PERIP_PWM_PDM_CONTROL_CH_MASK <<
+					  PERIP_PWM_PDM_CONTROL_CH_SHIFT(i));
 
 	if (pm_runtime_status_suspended(dev))
 		img_pwm_runtime_suspend(dev);
-- 
GitLab


From 2c85895bf3d202f6932598b124d0db2be4278999 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 2 Dec 2022 19:35:16 +0100
Subject: [PATCH 132/875] pwm: iqs620a: Use regmap_clear_bits and
 regmap_set_bits where applicable
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Found using coccinelle and the following semantic patch:

@@
expression map, reg, bits;
@@

- regmap_update_bits(map, reg, bits, bits)
+ regmap_set_bits(map, reg, bits)

@@
expression map, reg, bits;
@@

- regmap_update_bits(map, reg, bits, 0)
+ regmap_clear_bits(map, reg, bits)

Link: https://lore.kernel.org/r/20221115111347.3705732-4-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-iqs620a.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-iqs620a.c b/drivers/pwm/pwm-iqs620a.c
index 54bd95a5cab0c..7246176fce06a 100644
--- a/drivers/pwm/pwm-iqs620a.c
+++ b/drivers/pwm/pwm-iqs620a.c
@@ -47,8 +47,8 @@ static int iqs620_pwm_init(struct iqs620_pwm_private *iqs620_pwm,
 	int ret;
 
 	if (!duty_scale)
-		return regmap_update_bits(iqs62x->regmap, IQS620_PWR_SETTINGS,
-					  IQS620_PWR_SETTINGS_PWM_OUT, 0);
+		return regmap_clear_bits(iqs62x->regmap, IQS620_PWR_SETTINGS,
+					 IQS620_PWR_SETTINGS_PWM_OUT);
 
 	ret = regmap_write(iqs62x->regmap, IQS620_PWM_DUTY_CYCLE,
 			   duty_scale - 1);
-- 
GitLab


From 85cad49f5ed269ffa0c80081d6506e39fa78456b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 2 Dec 2022 19:35:17 +0100
Subject: [PATCH 133/875] pwm: stm32-lp: Use regmap_clear_bits and
 regmap_set_bits where applicable
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Found using coccinelle and the following semantic patch:

@@
expression map, reg, bits;
@@

- regmap_update_bits(map, reg, bits, bits)
+ regmap_set_bits(map, reg, bits)

@@
expression map, reg, bits;
@@

- regmap_update_bits(map, reg, bits, 0)
+ regmap_clear_bits(map, reg, bits)

Tested-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Link: https://lore.kernel.org/r/20221115111347.3705732-5-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-stm32-lp.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/pwm/pwm-stm32-lp.c b/drivers/pwm/pwm-stm32-lp.c
index 3115abb3f52ab..212bdc7d51ee9 100644
--- a/drivers/pwm/pwm-stm32-lp.c
+++ b/drivers/pwm/pwm-stm32-lp.c
@@ -140,9 +140,8 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 
 	if (reenable) {
 		/* Start LP timer in continuous mode */
-		ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CR,
-					 STM32_LPTIM_CNTSTRT,
-					 STM32_LPTIM_CNTSTRT);
+		ret = regmap_set_bits(priv->regmap, STM32_LPTIM_CR,
+				      STM32_LPTIM_CNTSTRT);
 		if (ret) {
 			regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
 			goto err;
-- 
GitLab


From 632ae5d7eb348b3ef88552ec0999260b6f9d6ab1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 2 Dec 2022 19:35:18 +0100
Subject: [PATCH 134/875] pwm: stm32: Use regmap_clear_bits and regmap_set_bits
 where applicable
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Found using coccinelle and the following semantic patch:

@@
expression map, reg, bits;
@@

- regmap_update_bits(map, reg, bits, bits)
+ regmap_set_bits(map, reg, bits)

@@
expression map, reg, bits;
@@

- regmap_update_bits(map, reg, bits, 0)
+ regmap_clear_bits(map, reg, bits)

Tested-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Link: https://lore.kernel.org/r/20221115111347.3705732-6-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-stm32.c | 34 ++++++++++++++++------------------
 1 file changed, 16 insertions(+), 18 deletions(-)

diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c
index 794ca5b029681..21e4a34dfff3c 100644
--- a/drivers/pwm/pwm-stm32.c
+++ b/drivers/pwm/pwm-stm32.c
@@ -115,14 +115,14 @@ static int stm32_pwm_raw_capture(struct stm32_pwm *priv, struct pwm_device *pwm,
 	int ret;
 
 	/* Ensure registers have been updated, enable counter and capture */
-	regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
-	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
+	regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
+	regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
 
 	/* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */
 	dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3;
 	ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E;
 	ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3;
-	regmap_update_bits(priv->regmap, TIM_CCER, ccen, ccen);
+	regmap_set_bits(priv->regmap, TIM_CCER, ccen);
 
 	/*
 	 * Timer DMA burst mode. Request 2 registers, 2 bursts, to get both
@@ -160,8 +160,8 @@ static int stm32_pwm_raw_capture(struct stm32_pwm *priv, struct pwm_device *pwm,
 	}
 
 stop:
-	regmap_update_bits(priv->regmap, TIM_CCER, ccen, 0);
-	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
+	regmap_clear_bits(priv->regmap, TIM_CCER, ccen);
+	regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
 
 	return ret;
 }
@@ -359,7 +359,7 @@ static int stm32_pwm_config(struct stm32_pwm *priv, int ch,
 
 	regmap_write(priv->regmap, TIM_PSC, prescaler);
 	regmap_write(priv->regmap, TIM_ARR, prd - 1);
-	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
+	regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
 
 	/* Calculate the duty cycles */
 	dty = prd * duty_ns;
@@ -377,7 +377,7 @@ static int stm32_pwm_config(struct stm32_pwm *priv, int ch,
 	else
 		regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
 
-	regmap_update_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE, TIM_BDTR_MOE);
+	regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE);
 
 	return 0;
 }
@@ -411,13 +411,13 @@ static int stm32_pwm_enable(struct stm32_pwm *priv, int ch)
 	if (priv->have_complementary_output)
 		mask |= TIM_CCER_CC1NE << (ch * 4);
 
-	regmap_update_bits(priv->regmap, TIM_CCER, mask, mask);
+	regmap_set_bits(priv->regmap, TIM_CCER, mask);
 
 	/* Make sure that registers are updated */
-	regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
+	regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
 
 	/* Enable controller */
-	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
+	regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
 
 	return 0;
 }
@@ -431,11 +431,11 @@ static void stm32_pwm_disable(struct stm32_pwm *priv, int ch)
 	if (priv->have_complementary_output)
 		mask |= TIM_CCER_CC1NE << (ch * 4);
 
-	regmap_update_bits(priv->regmap, TIM_CCER, mask, 0);
+	regmap_clear_bits(priv->regmap, TIM_CCER, mask);
 
 	/* When all channels are disabled, we can disable the controller */
 	if (!active_channels(priv))
-		regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
+		regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
 
 	clk_disable(priv->clk);
 }
@@ -568,10 +568,9 @@ static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
 	 * If complementary bit doesn't exist writing 1 will have no
 	 * effect so we can detect it.
 	 */
-	regmap_update_bits(priv->regmap,
-			   TIM_CCER, TIM_CCER_CC1NE, TIM_CCER_CC1NE);
+	regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
 	regmap_read(priv->regmap, TIM_CCER, &ccer);
-	regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE, 0);
+	regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
 
 	priv->have_complementary_output = (ccer != 0);
 }
@@ -585,10 +584,9 @@ static int stm32_pwm_detect_channels(struct stm32_pwm *priv)
 	 * If channels enable bits don't exist writing 1 will have no
 	 * effect so we can detect and count them.
 	 */
-	regmap_update_bits(priv->regmap,
-			   TIM_CCER, TIM_CCER_CCXE, TIM_CCER_CCXE);
+	regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE);
 	regmap_read(priv->regmap, TIM_CCER, &ccer);
-	regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE, 0);
+	regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE);
 
 	if (ccer & TIM_CCER_CC1E)
 		npwm++;
-- 
GitLab


From 241eab76657f72d82a5a77ef7d7958c6e07dd2b0 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Fri, 2 Dec 2022 19:35:19 +0100
Subject: [PATCH 135/875] pwm: mediatek: Add support for MT7986
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add support for PWM on MT7986 which has 2 PWM channels, one of them is
typically used for a temperature controlled fan.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Sam Shih <sam.shih@mediatek.com>
Link: https://lore.kernel.org/r/Y1K5ym1EL8kwzQEt@makrotopia.org
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-mediatek.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
index a337b47dc2f7d..5b5eeaff35da6 100644
--- a/drivers/pwm/pwm-mediatek.c
+++ b/drivers/pwm/pwm-mediatek.c
@@ -329,6 +329,12 @@ static const struct pwm_mediatek_of_data mt8365_pwm_data = {
 	.has_ck_26m_sel = true,
 };
 
+static const struct pwm_mediatek_of_data mt7986_pwm_data = {
+	.num_pwms = 2,
+	.pwm45_fixup = false,
+	.has_ck_26m_sel = true,
+};
+
 static const struct pwm_mediatek_of_data mt8516_pwm_data = {
 	.num_pwms = 5,
 	.pwm45_fixup = false,
@@ -342,6 +348,7 @@ static const struct of_device_id pwm_mediatek_of_match[] = {
 	{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
 	{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
 	{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
+	{ .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
 	{ .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
 	{ .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
 	{ .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
-- 
GitLab


From f956b838934ab06deeee2ce9d5c8dfe64e4beb24 Mon Sep 17 00:00:00 2001
From: Doug Brown <doug@schmorgal.com>
Date: Fri, 2 Dec 2022 19:35:20 +0100
Subject: [PATCH 136/875] pwm: pxa: Remove pxa_pwm_enable/disable
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

These functions are only acting as wrappers for clk_prepare_enable and
clk_disable_unprepare now, so remove them to simplify the driver.

Suggested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Doug Brown <doug@schmorgal.com>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20221113233639.24244-2-doug@schmorgal.com
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-pxa.c | 19 +++----------------
 1 file changed, 3 insertions(+), 16 deletions(-)

diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c
index 0bcaa58c6a91e..0ac052652c627 100644
--- a/drivers/pwm/pwm-pxa.c
+++ b/drivers/pwm/pwm-pxa.c
@@ -101,23 +101,10 @@ static int pxa_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 	return 0;
 }
 
-static int pxa_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
-{
-	struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip);
-
-	return clk_prepare_enable(pc->clk);
-}
-
-static void pxa_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
-{
-	struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip);
-
-	clk_disable_unprepare(pc->clk);
-}
-
 static int pxa_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 			 const struct pwm_state *state)
 {
+	struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip);
 	int err;
 
 	if (state->polarity != PWM_POLARITY_NORMAL)
@@ -125,7 +112,7 @@ static int pxa_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 
 	if (!state->enabled) {
 		if (pwm->state.enabled)
-			pxa_pwm_disable(chip, pwm);
+			clk_disable_unprepare(pc->clk);
 
 		return 0;
 	}
@@ -135,7 +122,7 @@ static int pxa_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 		return err;
 
 	if (!pwm->state.enabled)
-		return pxa_pwm_enable(chip, pwm);
+		return clk_prepare_enable(pc->clk);
 
 	return 0;
 }
-- 
GitLab


From 152f2d1def5e4b974947877126ff292a68a8c521 Mon Sep 17 00:00:00 2001
From: Doug Brown <doug@schmorgal.com>
Date: Fri, 2 Dec 2022 19:35:21 +0100
Subject: [PATCH 137/875] pwm: pxa: Set duty cycle to 0 when disabling PWM
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When disabling PWM, the duty cycle needs to be set to 0. This prevents
the previous duty cycle from showing up momentarily when the clock is
re-enabled next time.

Because the clock has to be running in order to configure the duty
cycle, unconditionally enable it early in pxa_pwm_apply and account for
the correct enable count at the end.

Suggested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Doug Brown <doug@schmorgal.com>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20221113233639.24244-3-doug@schmorgal.com
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-pxa.c | 25 ++++++++++++++++---------
 1 file changed, 16 insertions(+), 9 deletions(-)

diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c
index 0ac052652c627..9ee9b41d62b8b 100644
--- a/drivers/pwm/pwm-pxa.c
+++ b/drivers/pwm/pwm-pxa.c
@@ -105,24 +105,31 @@ static int pxa_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 			 const struct pwm_state *state)
 {
 	struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip);
+	u64 duty_cycle;
 	int err;
 
 	if (state->polarity != PWM_POLARITY_NORMAL)
 		return -EINVAL;
 
-	if (!state->enabled) {
-		if (pwm->state.enabled)
-			clk_disable_unprepare(pc->clk);
+	err = clk_prepare_enable(pc->clk);
+	if (err)
+		return err;
 
-		return 0;
-	}
+	duty_cycle = state->enabled ? state->duty_cycle : 0;
 
-	err = pxa_pwm_config(chip, pwm, state->duty_cycle, state->period);
-	if (err)
+	err = pxa_pwm_config(chip, pwm, duty_cycle, state->period);
+	if (err) {
+		clk_disable_unprepare(pc->clk);
 		return err;
+	}
+
+	if (state->enabled && !pwm->state.enabled)
+		return 0;
+
+	clk_disable_unprepare(pc->clk);
 
-	if (!pwm->state.enabled)
-		return clk_prepare_enable(pc->clk);
+	if (!state->enabled && pwm->state.enabled)
+		clk_disable_unprepare(pc->clk);
 
 	return 0;
 }
-- 
GitLab


From 939d002b7501128640aaeffe175d6331dcce2ca6 Mon Sep 17 00:00:00 2001
From: Doug Brown <doug@schmorgal.com>
Date: Fri, 2 Dec 2022 19:35:22 +0100
Subject: [PATCH 138/875] pwm: pxa: Remove clk enable/disable from
 pxa_pwm_config
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Now that pxa_pwm_apply always enables the clock first, there is no need
for pxa_pwm_config to do any clock enabling/disabling.

Signed-off-by: Doug Brown <doug@schmorgal.com>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20221113233639.24244-4-doug@schmorgal.com
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-pxa.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c
index 9ee9b41d62b8b..cf4d22c91929f 100644
--- a/drivers/pwm/pwm-pxa.c
+++ b/drivers/pwm/pwm-pxa.c
@@ -64,7 +64,6 @@ static int pxa_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 	unsigned long long c;
 	unsigned long period_cycles, prescale, pv, dc;
 	unsigned long offset;
-	int rc;
 
 	offset = pwm->hwpwm ? 0x10 : 0;
 
@@ -86,18 +85,10 @@ static int pxa_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 	else
 		dc = mul_u64_u64_div_u64(pv + 1, duty_ns, period_ns);
 
-	/* NOTE: the clock to PWM has to be enabled first
-	 * before writing to the registers
-	 */
-	rc = clk_prepare_enable(pc->clk);
-	if (rc < 0)
-		return rc;
-
 	writel(prescale, pc->mmio_base + offset + PWMCR);
 	writel(dc, pc->mmio_base + offset + PWMDCR);
 	writel(pv, pc->mmio_base + offset + PWMPCR);
 
-	clk_disable_unprepare(pc->clk);
 	return 0;
 }
 
-- 
GitLab


From 092c2ef4571cbc7e5f466bc241ff054723c41973 Mon Sep 17 00:00:00 2001
From: Doug Brown <doug@schmorgal.com>
Date: Fri, 2 Dec 2022 19:35:23 +0100
Subject: [PATCH 139/875] pwm: pxa: Use abrupt shutdown mode
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Switch to abrupt shutdown mode in order to stop the clock as soon as
possible when PWM is disabled. This minimizes the possibility of the
clock being re-enabled while it is still in the process of turning off,
which will result in the clock ending up erroneously disabled.

Signed-off-by: Doug Brown <doug@schmorgal.com>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20221113233639.24244-5-doug@schmorgal.com
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-pxa.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c
index cf4d22c91929f..00063ead7c0ae 100644
--- a/drivers/pwm/pwm-pxa.c
+++ b/drivers/pwm/pwm-pxa.c
@@ -85,7 +85,7 @@ static int pxa_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 	else
 		dc = mul_u64_u64_div_u64(pv + 1, duty_ns, period_ns);
 
-	writel(prescale, pc->mmio_base + offset + PWMCR);
+	writel(prescale | PWMCR_SD, pc->mmio_base + offset + PWMCR);
 	writel(dc, pc->mmio_base + offset + PWMDCR);
 	writel(pv, pc->mmio_base + offset + PWMPCR);
 
-- 
GitLab


From 8ba2725ffac351a1b80063ac7eb362832fae16a2 Mon Sep 17 00:00:00 2001
From: Doug Brown <doug@schmorgal.com>
Date: Fri, 2 Dec 2022 19:35:24 +0100
Subject: [PATCH 140/875] pwm: pxa: Add reference manual link and limitations
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add a pointer to the location of reference manuals for some of the
supported chips, and add a limitations section explaining the hardware's
PWM disable behavior.

Suggested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Doug Brown <doug@schmorgal.com>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20221113233639.24244-6-doug@schmorgal.com
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-pxa.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c
index 00063ead7c0ae..46ed668bd1411 100644
--- a/drivers/pwm/pwm-pxa.c
+++ b/drivers/pwm/pwm-pxa.c
@@ -6,6 +6,13 @@
  *
  * 2008-02-13	initial version
  *		eric miao <eric.miao@marvell.com>
+ *
+ * Links to reference manuals for some of the supported PWM chips can be found
+ * in Documentation/arm/marvell.rst.
+ *
+ * Limitations:
+ * - When PWM is stopped, the current PWM period stops abruptly at the next
+ *   input clock (PWMCR_SD is set) and the output is driven to inactive.
  */
 
 #include <linux/module.h>
-- 
GitLab


From 958f03074980e8ae1b0c257a732fe467069ec267 Mon Sep 17 00:00:00 2001
From: Doug Brown <doug@schmorgal.com>
Date: Fri, 2 Dec 2022 19:35:25 +0100
Subject: [PATCH 141/875] pwm: pxa: Enable for MMP platform
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The PXA168, which is part of the MMP platform, also uses this driver.

Signed-off-by: Doug Brown <doug@schmorgal.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20221113233639.24244-7-doug@schmorgal.com
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index cb623d0702f6d..dae023d783a22 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -434,7 +434,7 @@ config PWM_PCA9685
 
 config PWM_PXA
 	tristate "PXA PWM support"
-	depends on ARCH_PXA || COMPILE_TEST
+	depends on ARCH_PXA || ARCH_MMP || COMPILE_TEST
 	depends on HAS_IOMEM
 	help
 	  Generic PWM framework driver for PXA.
-- 
GitLab


From 6c452cff79f8bf1c0146fda598d32061cfd25443 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 2 Dec 2022 19:35:26 +0100
Subject: [PATCH 142/875] pwm: Make .get_state() callback return an error code
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.get_state() might fail in some cases. To make it possible that a driver
signals such a failure change the prototype of .get_state() to return an
error code.

This patch was created using coccinelle and the following semantic patch:

@p1@
identifier getstatefunc;
identifier driver;
@@
 struct pwm_ops driver = {
        ...,
        .get_state = getstatefunc
        ,...
 };

@p2@
identifier p1.getstatefunc;
identifier chip, pwm, state;
@@
-void
+int
 getstatefunc(struct pwm_chip *chip, struct pwm_device *pwm, struct pwm_state *state)
 {
   ...
-  return;
+  return 0;
   ...
 }

plus the actual change of the prototype in include/linux/pwm.h (plus some
manual fixing of indentions and empty lines).

So for now all drivers return success unconditionally. They are adapted
in the following patches to make the changes easier reviewable.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com>
Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Acked-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: Pavel Machek <pavel@ucw.cz>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221130152148.2769768-2-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/gpio/gpio-mvebu.c             |  9 ++++++---
 drivers/gpu/drm/bridge/ti-sn65dsi86.c | 14 ++++++++------
 drivers/leds/rgb/leds-qcom-lpg.c      | 14 ++++++++------
 drivers/pwm/pwm-atmel.c               |  6 ++++--
 drivers/pwm/pwm-bcm-iproc.c           |  8 +++++---
 drivers/pwm/pwm-crc.c                 | 10 ++++++----
 drivers/pwm/pwm-cros-ec.c             |  8 +++++---
 drivers/pwm/pwm-dwc.c                 |  6 ++++--
 drivers/pwm/pwm-hibvt.c               |  6 ++++--
 drivers/pwm/pwm-imx-tpm.c             |  8 +++++---
 drivers/pwm/pwm-imx27.c               |  8 +++++---
 drivers/pwm/pwm-intel-lgm.c           |  6 ++++--
 drivers/pwm/pwm-iqs620a.c             |  6 ++++--
 drivers/pwm/pwm-keembay.c             |  6 ++++--
 drivers/pwm/pwm-lpss.c                |  6 ++++--
 drivers/pwm/pwm-meson.c               |  8 +++++---
 drivers/pwm/pwm-mtk-disp.c            | 12 +++++++-----
 drivers/pwm/pwm-pca9685.c             |  8 +++++---
 drivers/pwm/pwm-raspberrypi-poe.c     |  8 +++++---
 drivers/pwm/pwm-rockchip.c            | 12 +++++++-----
 drivers/pwm/pwm-sifive.c              |  6 ++++--
 drivers/pwm/pwm-sl28cpld.c            |  8 +++++---
 drivers/pwm/pwm-sprd.c                |  8 +++++---
 drivers/pwm/pwm-stm32-lp.c            |  8 +++++---
 drivers/pwm/pwm-sun4i.c               | 12 +++++++-----
 drivers/pwm/pwm-sunplus.c             |  6 ++++--
 drivers/pwm/pwm-visconti.c            |  6 ++++--
 drivers/pwm/pwm-xilinx.c              |  8 +++++---
 include/linux/pwm.h                   |  4 ++--
 29 files changed, 146 insertions(+), 89 deletions(-)

diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index 1bb317b8dccea..91a4232ee58c2 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -657,9 +657,10 @@ static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
 	spin_unlock_irqrestore(&mvpwm->lock, flags);
 }
 
-static void mvebu_pwm_get_state(struct pwm_chip *chip,
-				struct pwm_device *pwm,
-				struct pwm_state *state) {
+static int mvebu_pwm_get_state(struct pwm_chip *chip,
+			       struct pwm_device *pwm,
+			       struct pwm_state *state)
+{
 
 	struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
 	struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
@@ -693,6 +694,8 @@ static void mvebu_pwm_get_state(struct pwm_chip *chip,
 		state->enabled = false;
 
 	spin_unlock_irqrestore(&mvpwm->lock, flags);
+
+	return 0;
 }
 
 static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
index 3c3561942eb66..6826d2423ae9a 100644
--- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
@@ -1500,8 +1500,8 @@ out:
 	return ret;
 }
 
-static void ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
-				struct pwm_state *state)
+static int ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+			       struct pwm_state *state)
 {
 	struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
 	unsigned int pwm_en_inv;
@@ -1512,19 +1512,19 @@ static void ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 
 	ret = regmap_read(pdata->regmap, SN_PWM_EN_INV_REG, &pwm_en_inv);
 	if (ret)
-		return;
+		return 0;
 
 	ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_SCALE_REG, &scale);
 	if (ret)
-		return;
+		return 0;
 
 	ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_REG, &backlight);
 	if (ret)
-		return;
+		return 0;
 
 	ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div);
 	if (ret)
-		return;
+		return 0;
 
 	state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv);
 	if (FIELD_GET(SN_PWM_INV_MASK, pwm_en_inv))
@@ -1539,6 +1539,8 @@ static void ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 
 	if (state->duty_cycle > state->period)
 		state->duty_cycle = state->period;
+
+	return 0;
 }
 
 static const struct pwm_ops ti_sn_pwm_ops = {
diff --git a/drivers/leds/rgb/leds-qcom-lpg.c b/drivers/leds/rgb/leds-qcom-lpg.c
index 02f51cc618376..741cc2fd817d6 100644
--- a/drivers/leds/rgb/leds-qcom-lpg.c
+++ b/drivers/leds/rgb/leds-qcom-lpg.c
@@ -968,8 +968,8 @@ out_unlock:
 	return ret;
 }
 
-static void lpg_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
-			      struct pwm_state *state)
+static int lpg_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+			     struct pwm_state *state)
 {
 	struct lpg *lpg = container_of(chip, struct lpg, pwm);
 	struct lpg_channel *chan = &lpg->channels[pwm->hwpwm];
@@ -982,20 +982,20 @@ static void lpg_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 
 	ret = regmap_read(lpg->map, chan->base + LPG_SIZE_CLK_REG, &val);
 	if (ret)
-		return;
+		return 0;
 
 	refclk = lpg_clk_rates[val & PWM_CLK_SELECT_MASK];
 	if (refclk) {
 		ret = regmap_read(lpg->map, chan->base + LPG_PREDIV_CLK_REG, &val);
 		if (ret)
-			return;
+			return 0;
 
 		pre_div = lpg_pre_divs[FIELD_GET(PWM_FREQ_PRE_DIV_MASK, val)];
 		m = FIELD_GET(PWM_FREQ_EXP_MASK, val);
 
 		ret = regmap_bulk_read(lpg->map, chan->base + PWM_VALUE_REG, &pwm_value, sizeof(pwm_value));
 		if (ret)
-			return;
+			return 0;
 
 		state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * LPG_RESOLUTION * pre_div * (1 << m), refclk);
 		state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pwm_value * pre_div * (1 << m), refclk);
@@ -1006,13 +1006,15 @@ static void lpg_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 
 	ret = regmap_read(lpg->map, chan->base + PWM_ENABLE_CONTROL_REG, &val);
 	if (ret)
-		return;
+		return 0;
 
 	state->enabled = FIELD_GET(LPG_ENABLE_CONTROL_OUTPUT, val);
 	state->polarity = PWM_POLARITY_NORMAL;
 
 	if (state->duty_cycle > state->period)
 		state->duty_cycle = state->period;
+
+	return 0;
 }
 
 static const struct pwm_ops lpg_pwm_ops = {
diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c
index 8e00a4286145b..cdbc23649032c 100644
--- a/drivers/pwm/pwm-atmel.c
+++ b/drivers/pwm/pwm-atmel.c
@@ -356,8 +356,8 @@ static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 	return 0;
 }
 
-static void atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
-				struct pwm_state *state)
+static int atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+			       struct pwm_state *state)
 {
 	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 	u32 sr, cmr;
@@ -396,6 +396,8 @@ static void atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 		state->polarity = PWM_POLARITY_INVERSED;
 	else
 		state->polarity = PWM_POLARITY_NORMAL;
+
+	return 0;
 }
 
 static const struct pwm_ops atmel_pwm_ops = {
diff --git a/drivers/pwm/pwm-bcm-iproc.c b/drivers/pwm/pwm-bcm-iproc.c
index 7251037d4dd56..97ec131eb7c1b 100644
--- a/drivers/pwm/pwm-bcm-iproc.c
+++ b/drivers/pwm/pwm-bcm-iproc.c
@@ -68,8 +68,8 @@ static void iproc_pwmc_disable(struct iproc_pwmc *ip, unsigned int channel)
 	ndelay(400);
 }
 
-static void iproc_pwmc_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
-				 struct pwm_state *state)
+static int iproc_pwmc_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+				struct pwm_state *state)
 {
 	struct iproc_pwmc *ip = to_iproc_pwmc(chip);
 	u64 tmp, multi, rate;
@@ -91,7 +91,7 @@ static void iproc_pwmc_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 	if (rate == 0) {
 		state->period = 0;
 		state->duty_cycle = 0;
-		return;
+		return 0;
 	}
 
 	value = readl(ip->base + IPROC_PWM_PRESCALE_OFFSET);
@@ -107,6 +107,8 @@ static void iproc_pwmc_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 	value = readl(ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm));
 	tmp = (value & IPROC_PWM_PERIOD_MAX) * multi;
 	state->duty_cycle = div64_u64(tmp, rate);
+
+	return 0;
 }
 
 static int iproc_pwmc_apply(struct pwm_chip *chip, struct pwm_device *pwm,
diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c
index 7b357d1cf6421..4099850117ba4 100644
--- a/drivers/pwm/pwm-crc.c
+++ b/drivers/pwm/pwm-crc.c
@@ -121,8 +121,8 @@ static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 	return 0;
 }
 
-static void crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
-			      struct pwm_state *state)
+static int crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+			     struct pwm_state *state)
 {
 	struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip);
 	struct device *dev = crc_pwm->chip.dev;
@@ -132,13 +132,13 @@ static void crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 	error = regmap_read(crc_pwm->regmap, PWM0_CLK_DIV, &clk_div_reg);
 	if (error) {
 		dev_err(dev, "Error reading PWM0_CLK_DIV %d\n", error);
-		return;
+		return 0;
 	}
 
 	error = regmap_read(crc_pwm->regmap, PWM0_DUTY_CYCLE, &duty_cycle_reg);
 	if (error) {
 		dev_err(dev, "Error reading PWM0_DUTY_CYCLE %d\n", error);
-		return;
+		return 0;
 	}
 
 	clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1;
@@ -149,6 +149,8 @@ static void crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 		DIV_ROUND_UP_ULL(duty_cycle_reg * state->period, PWM_MAX_LEVEL);
 	state->polarity = PWM_POLARITY_NORMAL;
 	state->enabled = !!(clk_div_reg & PWM_OUTPUT_ENABLE);
+
+	return 0;
 }
 
 static const struct pwm_ops crc_pwm_ops = {
diff --git a/drivers/pwm/pwm-cros-ec.c b/drivers/pwm/pwm-cros-ec.c
index 7f10f56c3eb66..11684edc06207 100644
--- a/drivers/pwm/pwm-cros-ec.c
+++ b/drivers/pwm/pwm-cros-ec.c
@@ -183,8 +183,8 @@ static int cros_ec_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 	return 0;
 }
 
-static void cros_ec_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
-				  struct pwm_state *state)
+static int cros_ec_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+				 struct pwm_state *state)
 {
 	struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip);
 	struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);
@@ -193,7 +193,7 @@ static void cros_ec_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 	ret = cros_ec_pwm_get_duty(ec_pwm, pwm->hwpwm);
 	if (ret < 0) {
 		dev_err(chip->dev, "error getting initial duty: %d\n", ret);
-		return;
+		return 0;
 	}
 
 	state->enabled = (ret > 0);
@@ -212,6 +212,8 @@ static void cros_ec_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 		state->duty_cycle = channel->duty_cycle;
 	else
 		state->duty_cycle = ret;
+
+	return 0;
 }
 
 static struct pwm_device *
diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c
index 7568300bb11e5..bd2308812096d 100644
--- a/drivers/pwm/pwm-dwc.c
+++ b/drivers/pwm/pwm-dwc.c
@@ -163,8 +163,8 @@ static int dwc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 	return 0;
 }
 
-static void dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
-			      struct pwm_state *state)
+static int dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+			     struct pwm_state *state)
 {
 	struct dwc_pwm *dwc = to_dwc_pwm(chip);
 	u64 duty, period;
@@ -188,6 +188,8 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 	state->polarity = PWM_POLARITY_INVERSED;
 
 	pm_runtime_put_sync(chip->dev);
+
+	return 0;
 }
 
 static const struct pwm_ops dwc_pwm_ops = {
diff --git a/drivers/pwm/pwm-hibvt.c b/drivers/pwm/pwm-hibvt.c
index 333f1b18ff4e6..12c05c155cab0 100644
--- a/drivers/pwm/pwm-hibvt.c
+++ b/drivers/pwm/pwm-hibvt.c
@@ -128,8 +128,8 @@ static void hibvt_pwm_set_polarity(struct pwm_chip *chip,
 				PWM_POLARITY_MASK, (0x0 << PWM_POLARITY_SHIFT));
 }
 
-static void hibvt_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
-				struct pwm_state *state)
+static int hibvt_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+			       struct pwm_state *state)
 {
 	struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
 	void __iomem *base;
@@ -146,6 +146,8 @@ static void hibvt_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 
 	value = readl(base + PWM_CTRL_ADDR(pwm->hwpwm));
 	state->enabled = (PWM_ENABLE_MASK & value);
+
+	return 0;
 }
 
 static int hibvt_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
diff --git a/drivers/pwm/pwm-imx-tpm.c b/drivers/pwm/pwm-imx-tpm.c
index e5e7b7c339a8f..ed1aad96fff04 100644
--- a/drivers/pwm/pwm-imx-tpm.c
+++ b/drivers/pwm/pwm-imx-tpm.c
@@ -132,9 +132,9 @@ static int pwm_imx_tpm_round_state(struct pwm_chip *chip,
 	return 0;
 }
 
-static void pwm_imx_tpm_get_state(struct pwm_chip *chip,
-				  struct pwm_device *pwm,
-				  struct pwm_state *state)
+static int pwm_imx_tpm_get_state(struct pwm_chip *chip,
+				 struct pwm_device *pwm,
+				 struct pwm_state *state)
 {
 	struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
 	u32 rate, val, prescale;
@@ -164,6 +164,8 @@ static void pwm_imx_tpm_get_state(struct pwm_chip *chip,
 
 	/* get channel status */
 	state->enabled = FIELD_GET(PWM_IMX_TPM_CnSC_ELS, val) ? true : false;
+
+	return 0;
 }
 
 /* this function is supposed to be called with mutex hold */
diff --git a/drivers/pwm/pwm-imx27.c b/drivers/pwm/pwm-imx27.c
index ea91a2f81a9fc..3a22c2fddc452 100644
--- a/drivers/pwm/pwm-imx27.c
+++ b/drivers/pwm/pwm-imx27.c
@@ -118,8 +118,8 @@ static void pwm_imx27_clk_disable_unprepare(struct pwm_imx27_chip *imx)
 	clk_disable_unprepare(imx->clk_ipg);
 }
 
-static void pwm_imx27_get_state(struct pwm_chip *chip,
-				struct pwm_device *pwm, struct pwm_state *state)
+static int pwm_imx27_get_state(struct pwm_chip *chip,
+			       struct pwm_device *pwm, struct pwm_state *state)
 {
 	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
 	u32 period, prescaler, pwm_clk, val;
@@ -128,7 +128,7 @@ static void pwm_imx27_get_state(struct pwm_chip *chip,
 
 	ret = pwm_imx27_clk_prepare_enable(imx);
 	if (ret < 0)
-		return;
+		return 0;
 
 	val = readl(imx->mmio_base + MX3_PWMCR);
 
@@ -170,6 +170,8 @@ static void pwm_imx27_get_state(struct pwm_chip *chip,
 	state->duty_cycle = DIV_ROUND_UP_ULL(tmp, pwm_clk);
 
 	pwm_imx27_clk_disable_unprepare(imx);
+
+	return 0;
 }
 
 static void pwm_imx27_sw_reset(struct pwm_chip *chip)
diff --git a/drivers/pwm/pwm-intel-lgm.c b/drivers/pwm/pwm-intel-lgm.c
index b66c350740870..0cd7dd548e82f 100644
--- a/drivers/pwm/pwm-intel-lgm.c
+++ b/drivers/pwm/pwm-intel-lgm.c
@@ -86,8 +86,8 @@ static int lgm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 	return lgm_pwm_enable(chip, 1);
 }
 
-static void lgm_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
-			      struct pwm_state *state)
+static int lgm_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+			     struct pwm_state *state)
 {
 	struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
 	u32 duty, val;
@@ -100,6 +100,8 @@ static void lgm_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 	regmap_read(pc->regmap, LGM_PWM_FAN_CON0, &val);
 	duty = FIELD_GET(LGM_PWM_FAN_DC_MSK, val);
 	state->duty_cycle = DIV_ROUND_UP(duty * pc->period, LGM_PWM_MAX_DUTY_CYCLE);
+
+	return 0;
 }
 
 static const struct pwm_ops lgm_pwm_ops = {
diff --git a/drivers/pwm/pwm-iqs620a.c b/drivers/pwm/pwm-iqs620a.c
index 7246176fce06a..4987ca940b648 100644
--- a/drivers/pwm/pwm-iqs620a.c
+++ b/drivers/pwm/pwm-iqs620a.c
@@ -104,8 +104,8 @@ static int iqs620_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 	return ret;
 }
 
-static void iqs620_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
-				 struct pwm_state *state)
+static int iqs620_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+				struct pwm_state *state)
 {
 	struct iqs620_pwm_private *iqs620_pwm;
 
@@ -126,6 +126,8 @@ static void iqs620_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 	mutex_unlock(&iqs620_pwm->lock);
 
 	state->period = IQS620_PWM_PERIOD_NS;
+
+	return 0;
 }
 
 static int iqs620_pwm_notifier(struct notifier_block *notifier,
diff --git a/drivers/pwm/pwm-keembay.c b/drivers/pwm/pwm-keembay.c
index 733811b057219..ac02d8bb4a0b5 100644
--- a/drivers/pwm/pwm-keembay.c
+++ b/drivers/pwm/pwm-keembay.c
@@ -89,8 +89,8 @@ static void keembay_pwm_disable(struct keembay_pwm *priv, int ch)
 				KMB_PWM_LEADIN_OFFSET(ch));
 }
 
-static void keembay_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
-				  struct pwm_state *state)
+static int keembay_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+				 struct pwm_state *state)
 {
 	struct keembay_pwm *priv = to_keembay_pwm_dev(chip);
 	unsigned long long high, low;
@@ -113,6 +113,8 @@ static void keembay_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 	state->duty_cycle = DIV_ROUND_UP_ULL(high, clk_rate);
 	state->period = DIV_ROUND_UP_ULL(high + low, clk_rate);
 	state->polarity = PWM_POLARITY_NORMAL;
+
+	return 0;
 }
 
 static int keembay_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c
index accdef5dd58e7..81ac297b8ba50 100644
--- a/drivers/pwm/pwm-lpss.c
+++ b/drivers/pwm/pwm-lpss.c
@@ -205,8 +205,8 @@ static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 	return ret;
 }
 
-static void pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
-			       struct pwm_state *state)
+static int pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+			      struct pwm_state *state)
 {
 	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
 	unsigned long base_unit_range;
@@ -236,6 +236,8 @@ static void pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 	state->enabled = !!(ctrl & PWM_ENABLE);
 
 	pm_runtime_put(chip->dev);
+
+	return 0;
 }
 
 static const struct pwm_ops pwm_lpss_ops = {
diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
index 57112f438c6dd..16d79ca5d8f53 100644
--- a/drivers/pwm/pwm-meson.c
+++ b/drivers/pwm/pwm-meson.c
@@ -318,8 +318,8 @@ static unsigned int meson_pwm_cnt_to_ns(struct pwm_chip *chip,
 	return cnt * fin_ns * (channel->pre_div + 1);
 }
 
-static void meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
-				struct pwm_state *state)
+static int meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+			       struct pwm_state *state)
 {
 	struct meson_pwm *meson = to_meson_pwm(chip);
 	struct meson_pwm_channel_data *channel_data;
@@ -327,7 +327,7 @@ static void meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 	u32 value, tmp;
 
 	if (!state)
-		return;
+		return 0;
 
 	channel = &meson->channels[pwm->hwpwm];
 	channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
@@ -357,6 +357,8 @@ static void meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 		state->period = 0;
 		state->duty_cycle = 0;
 	}
+
+	return 0;
 }
 
 static const struct pwm_ops meson_pwm_ops = {
diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c
index 3fbb4bae93a4e..ccf0ccdef29df 100644
--- a/drivers/pwm/pwm-mtk-disp.c
+++ b/drivers/pwm/pwm-mtk-disp.c
@@ -172,9 +172,9 @@ static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 	return 0;
 }
 
-static void mtk_disp_pwm_get_state(struct pwm_chip *chip,
-				   struct pwm_device *pwm,
-				   struct pwm_state *state)
+static int mtk_disp_pwm_get_state(struct pwm_chip *chip,
+				  struct pwm_device *pwm,
+				  struct pwm_state *state)
 {
 	struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
 	u64 rate, period, high_width;
@@ -184,14 +184,14 @@ static void mtk_disp_pwm_get_state(struct pwm_chip *chip,
 	err = clk_prepare_enable(mdp->clk_main);
 	if (err < 0) {
 		dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
-		return;
+		return 0;
 	}
 
 	err = clk_prepare_enable(mdp->clk_mm);
 	if (err < 0) {
 		dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
 		clk_disable_unprepare(mdp->clk_main);
-		return;
+		return 0;
 	}
 
 	rate = clk_get_rate(mdp->clk_main);
@@ -212,6 +212,8 @@ static void mtk_disp_pwm_get_state(struct pwm_chip *chip,
 	state->polarity = PWM_POLARITY_NORMAL;
 	clk_disable_unprepare(mdp->clk_mm);
 	clk_disable_unprepare(mdp->clk_main);
+
+	return 0;
 }
 
 static const struct pwm_ops mtk_disp_pwm_ops = {
diff --git a/drivers/pwm/pwm-pca9685.c b/drivers/pwm/pwm-pca9685.c
index f230c10d28bb2..41be244e7dd3d 100644
--- a/drivers/pwm/pwm-pca9685.c
+++ b/drivers/pwm/pwm-pca9685.c
@@ -431,8 +431,8 @@ static int pca9685_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 	return ret;
 }
 
-static void pca9685_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
-				  struct pwm_state *state)
+static int pca9685_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+				 struct pwm_state *state)
 {
 	struct pca9685 *pca = to_pca(chip);
 	unsigned long long duty;
@@ -458,12 +458,14 @@ static void pca9685_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 		 */
 		state->duty_cycle = 0;
 		state->enabled = false;
-		return;
+		return 0;
 	}
 
 	state->enabled = true;
 	duty = pca9685_pwm_get_duty(pca, pwm->hwpwm);
 	state->duty_cycle = DIV_ROUND_DOWN_ULL(duty * state->period, PCA9685_COUNTER_RANGE);
+
+	return 0;
 }
 
 static int pca9685_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
diff --git a/drivers/pwm/pwm-raspberrypi-poe.c b/drivers/pwm/pwm-raspberrypi-poe.c
index 6ff73029f367f..2939b71a7ba7b 100644
--- a/drivers/pwm/pwm-raspberrypi-poe.c
+++ b/drivers/pwm/pwm-raspberrypi-poe.c
@@ -82,9 +82,9 @@ static int raspberrypi_pwm_get_property(struct rpi_firmware *firmware,
 	return 0;
 }
 
-static void raspberrypi_pwm_get_state(struct pwm_chip *chip,
-				      struct pwm_device *pwm,
-				      struct pwm_state *state)
+static int raspberrypi_pwm_get_state(struct pwm_chip *chip,
+				     struct pwm_device *pwm,
+				     struct pwm_state *state)
 {
 	struct raspberrypi_pwm *rpipwm = raspberrypi_pwm_from_chip(chip);
 
@@ -93,6 +93,8 @@ static void raspberrypi_pwm_get_state(struct pwm_chip *chip,
 					 RPI_PWM_MAX_DUTY);
 	state->enabled = !!(rpipwm->duty_cycle);
 	state->polarity = PWM_POLARITY_NORMAL;
+
+	return 0;
 }
 
 static int raspberrypi_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c
index a5af859217c19..3ec7d17569034 100644
--- a/drivers/pwm/pwm-rockchip.c
+++ b/drivers/pwm/pwm-rockchip.c
@@ -57,9 +57,9 @@ static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
 	return container_of(c, struct rockchip_pwm_chip, chip);
 }
 
-static void rockchip_pwm_get_state(struct pwm_chip *chip,
-				   struct pwm_device *pwm,
-				   struct pwm_state *state)
+static int rockchip_pwm_get_state(struct pwm_chip *chip,
+				  struct pwm_device *pwm,
+				  struct pwm_state *state)
 {
 	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
 	u32 enable_conf = pc->data->enable_conf;
@@ -70,11 +70,11 @@ static void rockchip_pwm_get_state(struct pwm_chip *chip,
 
 	ret = clk_enable(pc->pclk);
 	if (ret)
-		return;
+		return 0;
 
 	ret = clk_enable(pc->clk);
 	if (ret)
-		return;
+		return 0;
 
 	clk_rate = clk_get_rate(pc->clk);
 
@@ -96,6 +96,8 @@ static void rockchip_pwm_get_state(struct pwm_chip *chip,
 
 	clk_disable(pc->clk);
 	clk_disable(pc->pclk);
+
+	return 0;
 }
 
 static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c
index bb72393134016..62b6acc6373db 100644
--- a/drivers/pwm/pwm-sifive.c
+++ b/drivers/pwm/pwm-sifive.c
@@ -105,8 +105,8 @@ static void pwm_sifive_update_clock(struct pwm_sifive_ddata *ddata,
 		"New real_period = %u ns\n", ddata->real_period);
 }
 
-static void pwm_sifive_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
-				 struct pwm_state *state)
+static int pwm_sifive_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+				struct pwm_state *state)
 {
 	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
 	u32 duty, val;
@@ -123,6 +123,8 @@ static void pwm_sifive_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 	state->duty_cycle =
 		(u64)duty * ddata->real_period >> PWM_SIFIVE_CMPWIDTH;
 	state->polarity = PWM_POLARITY_INVERSED;
+
+	return 0;
 }
 
 static int pwm_sifive_apply(struct pwm_chip *chip, struct pwm_device *pwm,
diff --git a/drivers/pwm/pwm-sl28cpld.c b/drivers/pwm/pwm-sl28cpld.c
index 589aeaaa6ac86..e64900ad4ba1e 100644
--- a/drivers/pwm/pwm-sl28cpld.c
+++ b/drivers/pwm/pwm-sl28cpld.c
@@ -87,9 +87,9 @@ struct sl28cpld_pwm {
 #define sl28cpld_pwm_from_chip(_chip) \
 	container_of(_chip, struct sl28cpld_pwm, pwm_chip)
 
-static void sl28cpld_pwm_get_state(struct pwm_chip *chip,
-				   struct pwm_device *pwm,
-				   struct pwm_state *state)
+static int sl28cpld_pwm_get_state(struct pwm_chip *chip,
+				  struct pwm_device *pwm,
+				  struct pwm_state *state)
 {
 	struct sl28cpld_pwm *priv = sl28cpld_pwm_from_chip(chip);
 	unsigned int reg;
@@ -115,6 +115,8 @@ static void sl28cpld_pwm_get_state(struct pwm_chip *chip,
 	 * the PWM core.
 	 */
 	state->duty_cycle = min(state->duty_cycle, state->period);
+
+	return 0;
 }
 
 static int sl28cpld_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
diff --git a/drivers/pwm/pwm-sprd.c b/drivers/pwm/pwm-sprd.c
index 7004f55bbf115..bda8bc5af9768 100644
--- a/drivers/pwm/pwm-sprd.c
+++ b/drivers/pwm/pwm-sprd.c
@@ -65,8 +65,8 @@ static void sprd_pwm_write(struct sprd_pwm_chip *spc, u32 hwid,
 	writel_relaxed(val, spc->base + offset);
 }
 
-static void sprd_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
-			       struct pwm_state *state)
+static int sprd_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+			      struct pwm_state *state)
 {
 	struct sprd_pwm_chip *spc =
 		container_of(chip, struct sprd_pwm_chip, chip);
@@ -83,7 +83,7 @@ static void sprd_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 	if (ret) {
 		dev_err(spc->dev, "failed to enable pwm%u clocks\n",
 			pwm->hwpwm);
-		return;
+		return 0;
 	}
 
 	val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE);
@@ -113,6 +113,8 @@ static void sprd_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 	/* Disable PWM clocks if the PWM channel is not in enable state. */
 	if (!state->enabled)
 		clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks);
+
+	return 0;
 }
 
 static int sprd_pwm_config(struct sprd_pwm_chip *spc, struct pwm_device *pwm,
diff --git a/drivers/pwm/pwm-stm32-lp.c b/drivers/pwm/pwm-stm32-lp.c
index 212bdc7d51ee9..514ff58a4471d 100644
--- a/drivers/pwm/pwm-stm32-lp.c
+++ b/drivers/pwm/pwm-stm32-lp.c
@@ -156,9 +156,9 @@ err:
 	return ret;
 }
 
-static void stm32_pwm_lp_get_state(struct pwm_chip *chip,
-				   struct pwm_device *pwm,
-				   struct pwm_state *state)
+static int stm32_pwm_lp_get_state(struct pwm_chip *chip,
+				  struct pwm_device *pwm,
+				  struct pwm_state *state)
 {
 	struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip);
 	unsigned long rate = clk_get_rate(priv->clk);
@@ -184,6 +184,8 @@ static void stm32_pwm_lp_get_state(struct pwm_chip *chip,
 	tmp = prd - val;
 	tmp = (tmp << presc) * NSEC_PER_SEC;
 	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate);
+
+	return 0;
 }
 
 static const struct pwm_ops stm32_pwm_lp_ops = {
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index c8445b0a33392..37d75e252d4e7 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -108,9 +108,9 @@ static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
 	writel(val, chip->base + offset);
 }
 
-static void sun4i_pwm_get_state(struct pwm_chip *chip,
-				struct pwm_device *pwm,
-				struct pwm_state *state)
+static int sun4i_pwm_get_state(struct pwm_chip *chip,
+			       struct pwm_device *pwm,
+			       struct pwm_state *state)
 {
 	struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
 	u64 clk_rate, tmp;
@@ -132,7 +132,7 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
 		state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
 		state->polarity = PWM_POLARITY_NORMAL;
 		state->enabled = true;
-		return;
+		return 0;
 	}
 
 	if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
@@ -142,7 +142,7 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
 		prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
 
 	if (prescaler == 0)
-		return;
+		return 0;
 
 	if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
 		state->polarity = PWM_POLARITY_NORMAL;
@@ -162,6 +162,8 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
 
 	tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
 	state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
+
+	return 0;
 }
 
 static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
diff --git a/drivers/pwm/pwm-sunplus.c b/drivers/pwm/pwm-sunplus.c
index e776fd16512de..d6ebe9f03b354 100644
--- a/drivers/pwm/pwm-sunplus.c
+++ b/drivers/pwm/pwm-sunplus.c
@@ -124,8 +124,8 @@ static int sunplus_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 	return 0;
 }
 
-static void sunplus_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
-				  struct pwm_state *state)
+static int sunplus_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+				 struct pwm_state *state)
 {
 	struct sunplus_pwm *priv = to_sunplus_pwm(chip);
 	u32 mode0, dd_freq, duty;
@@ -155,6 +155,8 @@ static void sunplus_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 	}
 
 	state->polarity = PWM_POLARITY_NORMAL;
+
+	return 0;
 }
 
 static const struct pwm_ops sunplus_pwm_ops = {
diff --git a/drivers/pwm/pwm-visconti.c b/drivers/pwm/pwm-visconti.c
index 927c4cbb1daf0..e3fb79b3e2a7a 100644
--- a/drivers/pwm/pwm-visconti.c
+++ b/drivers/pwm/pwm-visconti.c
@@ -103,8 +103,8 @@ static int visconti_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 	return 0;
 }
 
-static void visconti_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
-				   struct pwm_state *state)
+static int visconti_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+				  struct pwm_state *state)
 {
 	struct visconti_pwm_chip *priv = visconti_pwm_from_chip(chip);
 	u32 period, duty, pwmc0, pwmc0_clk;
@@ -122,6 +122,8 @@ static void visconti_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm
 		state->polarity = PWM_POLARITY_NORMAL;
 
 	state->enabled = true;
+
+	return 0;
 }
 
 static const struct pwm_ops visconti_pwm_ops = {
diff --git a/drivers/pwm/pwm-xilinx.c b/drivers/pwm/pwm-xilinx.c
index 4dab2b86c4276..f7a50fdcd9a52 100644
--- a/drivers/pwm/pwm-xilinx.c
+++ b/drivers/pwm/pwm-xilinx.c
@@ -169,9 +169,9 @@ static int xilinx_pwm_apply(struct pwm_chip *chip, struct pwm_device *unused,
 	return 0;
 }
 
-static void xilinx_pwm_get_state(struct pwm_chip *chip,
-				 struct pwm_device *unused,
-				 struct pwm_state *state)
+static int xilinx_pwm_get_state(struct pwm_chip *chip,
+				struct pwm_device *unused,
+				struct pwm_state *state)
 {
 	struct xilinx_timer_priv *priv = xilinx_pwm_chip_to_priv(chip);
 	u32 tlr0, tlr1, tcsr0, tcsr1;
@@ -191,6 +191,8 @@ static void xilinx_pwm_get_state(struct pwm_chip *chip,
 	 */
 	if (state->period == state->duty_cycle)
 		state->duty_cycle = 0;
+
+	return 0;
 }
 
 static const struct pwm_ops xilinx_pwm_ops = {
diff --git a/include/linux/pwm.h b/include/linux/pwm.h
index d70c6e5a839d6..4de09163c968a 100644
--- a/include/linux/pwm.h
+++ b/include/linux/pwm.h
@@ -276,8 +276,8 @@ struct pwm_ops {
 		       struct pwm_capture *result, unsigned long timeout);
 	int (*apply)(struct pwm_chip *chip, struct pwm_device *pwm,
 		     const struct pwm_state *state);
-	void (*get_state)(struct pwm_chip *chip, struct pwm_device *pwm,
-			  struct pwm_state *state);
+	int (*get_state)(struct pwm_chip *chip, struct pwm_device *pwm,
+			 struct pwm_state *state);
 	struct module *owner;
 };
 
-- 
GitLab


From 3dae106f4ca358bb1d8d8708d3289fa130b1ad5b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 2 Dec 2022 19:35:27 +0100
Subject: [PATCH 143/875] pwm/tracing: Also record trace events for failed API
 calls
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Record and report an error code for the events. This allows to report
about failed calls without ambiguity and so gives a more complete
picture.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221130152148.2769768-3-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/core.c         | 18 ++++++++----------
 include/trace/events/pwm.h | 20 ++++++++++----------
 2 files changed, 18 insertions(+), 20 deletions(-)

diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
index 3a0967209853f..61d15510fdd77 100644
--- a/drivers/pwm/core.c
+++ b/drivers/pwm/core.c
@@ -115,8 +115,8 @@ static int pwm_device_request(struct pwm_device *pwm, const char *label)
 	}
 
 	if (pwm->chip->ops->get_state) {
-		pwm->chip->ops->get_state(pwm->chip, pwm, &pwm->state);
-		trace_pwm_get(pwm, &pwm->state);
+		err = pwm->chip->ops->get_state(pwm->chip, pwm, &pwm->state);
+		trace_pwm_get(pwm, &pwm->state, err);
 
 		if (IS_ENABLED(CONFIG_PWM_DEBUG))
 			pwm->last = pwm->state;
@@ -458,8 +458,8 @@ static void pwm_apply_state_debug(struct pwm_device *pwm,
 	 * checks.
 	 */
 
-	chip->ops->get_state(chip, pwm, &s1);
-	trace_pwm_get(pwm, &s1);
+	err = chip->ops->get_state(chip, pwm, &s1);
+	trace_pwm_get(pwm, &s1, err);
 
 	/*
 	 * The lowlevel driver either ignored .polarity (which is a bug) or as
@@ -515,16 +515,15 @@ static void pwm_apply_state_debug(struct pwm_device *pwm,
 
 	/* reapply the state that the driver reported being configured. */
 	err = chip->ops->apply(chip, pwm, &s1);
+	trace_pwm_apply(pwm, &s1, err);
 	if (err) {
 		*last = s1;
 		dev_err(chip->dev, "failed to reapply current setting\n");
 		return;
 	}
 
-	trace_pwm_apply(pwm, &s1);
-
-	chip->ops->get_state(chip, pwm, last);
-	trace_pwm_get(pwm, last);
+	err = chip->ops->get_state(chip, pwm, last);
+	trace_pwm_get(pwm, last, err);
 
 	/* reapplication of the current state should give an exact match */
 	if (s1.enabled != last->enabled ||
@@ -572,11 +571,10 @@ int pwm_apply_state(struct pwm_device *pwm, const struct pwm_state *state)
 		return 0;
 
 	err = chip->ops->apply(chip, pwm, state);
+	trace_pwm_apply(pwm, state, err);
 	if (err)
 		return err;
 
-	trace_pwm_apply(pwm, state);
-
 	pwm->state = *state;
 
 	/*
diff --git a/include/trace/events/pwm.h b/include/trace/events/pwm.h
index cf243de41cc82..12b35e4ff917a 100644
--- a/include/trace/events/pwm.h
+++ b/include/trace/events/pwm.h
@@ -10,9 +10,9 @@
 
 DECLARE_EVENT_CLASS(pwm,
 
-	TP_PROTO(struct pwm_device *pwm, const struct pwm_state *state),
+	TP_PROTO(struct pwm_device *pwm, const struct pwm_state *state, int err),
 
-	TP_ARGS(pwm, state),
+	TP_ARGS(pwm, state, err),
 
 	TP_STRUCT__entry(
 		__field(struct pwm_device *, pwm)
@@ -20,6 +20,7 @@ DECLARE_EVENT_CLASS(pwm,
 		__field(u64, duty_cycle)
 		__field(enum pwm_polarity, polarity)
 		__field(bool, enabled)
+		__field(int, err)
 	),
 
 	TP_fast_assign(
@@ -28,28 +29,27 @@ DECLARE_EVENT_CLASS(pwm,
 		__entry->duty_cycle = state->duty_cycle;
 		__entry->polarity = state->polarity;
 		__entry->enabled = state->enabled;
+		__entry->err = err;
 	),
 
-	TP_printk("%p: period=%llu duty_cycle=%llu polarity=%d enabled=%d",
+	TP_printk("%p: period=%llu duty_cycle=%llu polarity=%d enabled=%d err=%d",
 		  __entry->pwm, __entry->period, __entry->duty_cycle,
-		  __entry->polarity, __entry->enabled)
+		  __entry->polarity, __entry->enabled, __entry->err)
 
 );
 
 DEFINE_EVENT(pwm, pwm_apply,
 
-	TP_PROTO(struct pwm_device *pwm, const struct pwm_state *state),
-
-	TP_ARGS(pwm, state)
+	TP_PROTO(struct pwm_device *pwm, const struct pwm_state *state, int err),
 
+	TP_ARGS(pwm, state, err)
 );
 
 DEFINE_EVENT(pwm, pwm_get,
 
-	TP_PROTO(struct pwm_device *pwm, const struct pwm_state *state),
-
-	TP_ARGS(pwm, state)
+	TP_PROTO(struct pwm_device *pwm, const struct pwm_state *state, int err),
 
+	TP_ARGS(pwm, state, err)
 );
 
 #endif /* _TRACE_PWM_H */
-- 
GitLab


From f00de180661d8191aa979c2a8a8f4ec2b35a4cfd Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 2 Dec 2022 19:35:28 +0100
Subject: [PATCH 144/875] drm/bridge: ti-sn65dsi86: Propagate errors in
 .get_state() to the caller
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.get_state() can return an error indication. Make use of it to propagate
failing hardware accesses.

Acked-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221130152148.2769768-4-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/gpu/drm/bridge/ti-sn65dsi86.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
index 6826d2423ae9a..9671071490d8a 100644
--- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
@@ -1512,19 +1512,19 @@ static int ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 
 	ret = regmap_read(pdata->regmap, SN_PWM_EN_INV_REG, &pwm_en_inv);
 	if (ret)
-		return 0;
+		return ret;
 
 	ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_SCALE_REG, &scale);
 	if (ret)
-		return 0;
+		return ret;
 
 	ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_REG, &backlight);
 	if (ret)
-		return 0;
+		return ret;
 
 	ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div);
 	if (ret)
-		return 0;
+		return ret;
 
 	state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv);
 	if (FIELD_GET(SN_PWM_INV_MASK, pwm_en_inv))
-- 
GitLab


From fea768cf68c04d68ea2a8091c559667378f3b77c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 2 Dec 2022 19:35:29 +0100
Subject: [PATCH 145/875] leds: qcom-lpg: Propagate errors in .get_state() to
 the caller
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.get_state() can return an error indication. Make use of it to propagate
failing hardware accesses.

Acked-by: Pavel Machek <pavel@ucw.cz>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221130152148.2769768-5-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/leds/rgb/leds-qcom-lpg.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/leds/rgb/leds-qcom-lpg.c b/drivers/leds/rgb/leds-qcom-lpg.c
index 741cc2fd817d6..0dcc046a9a192 100644
--- a/drivers/leds/rgb/leds-qcom-lpg.c
+++ b/drivers/leds/rgb/leds-qcom-lpg.c
@@ -982,20 +982,20 @@ static int lpg_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 
 	ret = regmap_read(lpg->map, chan->base + LPG_SIZE_CLK_REG, &val);
 	if (ret)
-		return 0;
+		return ret;
 
 	refclk = lpg_clk_rates[val & PWM_CLK_SELECT_MASK];
 	if (refclk) {
 		ret = regmap_read(lpg->map, chan->base + LPG_PREDIV_CLK_REG, &val);
 		if (ret)
-			return 0;
+			return ret;
 
 		pre_div = lpg_pre_divs[FIELD_GET(PWM_FREQ_PRE_DIV_MASK, val)];
 		m = FIELD_GET(PWM_FREQ_EXP_MASK, val);
 
 		ret = regmap_bulk_read(lpg->map, chan->base + PWM_VALUE_REG, &pwm_value, sizeof(pwm_value));
 		if (ret)
-			return 0;
+			return ret;
 
 		state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * LPG_RESOLUTION * pre_div * (1 << m), refclk);
 		state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pwm_value * pre_div * (1 << m), refclk);
@@ -1006,7 +1006,7 @@ static int lpg_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 
 	ret = regmap_read(lpg->map, chan->base + PWM_ENABLE_CONTROL_REG, &val);
 	if (ret)
-		return 0;
+		return ret;
 
 	state->enabled = FIELD_GET(LPG_ENABLE_CONTROL_OUTPUT, val);
 	state->polarity = PWM_POLARITY_NORMAL;
-- 
GitLab


From 9c9d5e9957ac443cc544d63688e2442c230430ea Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 2 Dec 2022 19:35:30 +0100
Subject: [PATCH 146/875] pwm: crc: Propagate errors in .get_state() to the
 caller
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.get_state() can return an error indication. Make use of it to propagate
failing hardware accesses.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221130152148.2769768-6-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-crc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c
index 4099850117ba4..4703b4a0b6e4a 100644
--- a/drivers/pwm/pwm-crc.c
+++ b/drivers/pwm/pwm-crc.c
@@ -132,13 +132,13 @@ static int crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 	error = regmap_read(crc_pwm->regmap, PWM0_CLK_DIV, &clk_div_reg);
 	if (error) {
 		dev_err(dev, "Error reading PWM0_CLK_DIV %d\n", error);
-		return 0;
+		return error;
 	}
 
 	error = regmap_read(crc_pwm->regmap, PWM0_DUTY_CYCLE, &duty_cycle_reg);
 	if (error) {
 		dev_err(dev, "Error reading PWM0_DUTY_CYCLE %d\n", error);
-		return 0;
+		return error;
 	}
 
 	clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1;
-- 
GitLab


From ee02c1cb87f957ff0c66337d776486e72967987d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 2 Dec 2022 19:35:31 +0100
Subject: [PATCH 147/875] pwm: cros-ec: Propagate errors in .get_state() to the
 caller
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.get_state() can return an error indication. Make use of it to propagate
failing hardware accesses.

Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221130152148.2769768-7-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-cros-ec.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pwm/pwm-cros-ec.c b/drivers/pwm/pwm-cros-ec.c
index 11684edc06207..86df6702cb835 100644
--- a/drivers/pwm/pwm-cros-ec.c
+++ b/drivers/pwm/pwm-cros-ec.c
@@ -193,7 +193,7 @@ static int cros_ec_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 	ret = cros_ec_pwm_get_duty(ec_pwm, pwm->hwpwm);
 	if (ret < 0) {
 		dev_err(chip->dev, "error getting initial duty: %d\n", ret);
-		return 0;
+		return ret;
 	}
 
 	state->enabled = (ret > 0);
-- 
GitLab


From 51b9f2fb38bd209bbfa49e1eca2e262667f29e48 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 2 Dec 2022 19:35:32 +0100
Subject: [PATCH 148/875] pwm: imx27: Propagate errors in .get_state() to the
 caller
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.get_state() can return an error indication. Make use of it to propagate
failing hardware accesses.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221130152148.2769768-8-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-imx27.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pwm/pwm-imx27.c b/drivers/pwm/pwm-imx27.c
index 3a22c2fddc452..29a3089c534cd 100644
--- a/drivers/pwm/pwm-imx27.c
+++ b/drivers/pwm/pwm-imx27.c
@@ -128,7 +128,7 @@ static int pwm_imx27_get_state(struct pwm_chip *chip,
 
 	ret = pwm_imx27_clk_prepare_enable(imx);
 	if (ret < 0)
-		return 0;
+		return ret;
 
 	val = readl(imx->mmio_base + MX3_PWMCR);
 
-- 
GitLab


From 2f47786ce460206f2ff8ecb7d19352e2307b5511 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 2 Dec 2022 19:35:33 +0100
Subject: [PATCH 149/875] pwm: mtk-disp: Propagate errors in .get_state() to
 the caller
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.get_state() can return an error indication. Make use of it to propagate
failing hardware accesses.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221130152148.2769768-9-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-mtk-disp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c
index ccf0ccdef29df..692a06121b286 100644
--- a/drivers/pwm/pwm-mtk-disp.c
+++ b/drivers/pwm/pwm-mtk-disp.c
@@ -184,14 +184,14 @@ static int mtk_disp_pwm_get_state(struct pwm_chip *chip,
 	err = clk_prepare_enable(mdp->clk_main);
 	if (err < 0) {
 		dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
-		return 0;
+		return err;
 	}
 
 	err = clk_prepare_enable(mdp->clk_mm);
 	if (err < 0) {
 		dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
 		clk_disable_unprepare(mdp->clk_main);
-		return 0;
+		return err;
 	}
 
 	rate = clk_get_rate(mdp->clk_main);
-- 
GitLab


From 790a8bae62f701821305dac37a9f6013cde8488f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 2 Dec 2022 19:35:34 +0100
Subject: [PATCH 150/875] pwm: rockchip: Propagate errors in .get_state() to
 the caller
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.get_state() can return an error indication. Make use of it to propagate
failing hardware accesses.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221130152148.2769768-10-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-rockchip.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c
index 3ec7d17569034..7f084eb340923 100644
--- a/drivers/pwm/pwm-rockchip.c
+++ b/drivers/pwm/pwm-rockchip.c
@@ -70,11 +70,11 @@ static int rockchip_pwm_get_state(struct pwm_chip *chip,
 
 	ret = clk_enable(pc->pclk);
 	if (ret)
-		return 0;
+		return ret;
 
 	ret = clk_enable(pc->clk);
 	if (ret)
-		return 0;
+		return ret;
 
 	clk_rate = clk_get_rate(pc->clk);
 
-- 
GitLab


From 500f879843adf329281e418d302e1ad40baa26c3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 2 Dec 2022 19:35:35 +0100
Subject: [PATCH 151/875] pwm: sprd: Propagate errors in .get_state() to the
 caller
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.get_state() can return an error indication. Make use of it to propagate
failing hardware accesses.

Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221130152148.2769768-11-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-sprd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pwm/pwm-sprd.c b/drivers/pwm/pwm-sprd.c
index bda8bc5af9768..d866ce345f977 100644
--- a/drivers/pwm/pwm-sprd.c
+++ b/drivers/pwm/pwm-sprd.c
@@ -83,7 +83,7 @@ static int sprd_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 	if (ret) {
 		dev_err(spc->dev, "failed to enable pwm%u clocks\n",
 			pwm->hwpwm);
-		return 0;
+		return ret;
 	}
 
 	val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE);
-- 
GitLab


From c73a3107624ddc305483ced13deca9ce8a073783 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 2 Dec 2022 19:35:36 +0100
Subject: [PATCH 152/875] pwm: Handle .get_state() failures
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This suppresses diagnosis for PWM_DEBUG routines and makes sure that
pwm->state isn't modified in pwm_device_request() if .get_state() fails.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221130152148.2769768-12-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/core.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
index 61d15510fdd77..e01147f66e15a 100644
--- a/drivers/pwm/core.c
+++ b/drivers/pwm/core.c
@@ -115,8 +115,13 @@ static int pwm_device_request(struct pwm_device *pwm, const char *label)
 	}
 
 	if (pwm->chip->ops->get_state) {
-		err = pwm->chip->ops->get_state(pwm->chip, pwm, &pwm->state);
-		trace_pwm_get(pwm, &pwm->state, err);
+		struct pwm_state state;
+
+		err = pwm->chip->ops->get_state(pwm->chip, pwm, &state);
+		trace_pwm_get(pwm, &state, err);
+
+		if (!err)
+			pwm->state = state;
 
 		if (IS_ENABLED(CONFIG_PWM_DEBUG))
 			pwm->last = pwm->state;
@@ -460,6 +465,9 @@ static void pwm_apply_state_debug(struct pwm_device *pwm,
 
 	err = chip->ops->get_state(chip, pwm, &s1);
 	trace_pwm_get(pwm, &s1, err);
+	if (err)
+		/* If that failed there isn't much to debug */
+		return;
 
 	/*
 	 * The lowlevel driver either ignored .polarity (which is a bug) or as
@@ -524,6 +532,8 @@ static void pwm_apply_state_debug(struct pwm_device *pwm,
 
 	err = chip->ops->get_state(chip, pwm, last);
 	trace_pwm_get(pwm, last, err);
+	if (err)
+		return;
 
 	/* reapplication of the current state should give an exact match */
 	if (s1.enabled != last->enabled ||
-- 
GitLab


From a08b318a155e77d4c61bbdc28248b347d66f7248 Mon Sep 17 00:00:00 2001
From: Andre Przywara <andre.przywara@arm.com>
Date: Fri, 2 Dec 2022 19:35:37 +0100
Subject: [PATCH 153/875] pwm: sun4i: Propagate errors in .get_state() to the
 caller
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.get_state() can return an error indication now. Make use of it to
propagate an impossible prescaler encoding, should that have sneaked in
somehow.
Also check the return value of clk_get_rate(). That's unlikely to fail,
but we use that in two divide operations down in the code, so let's
avoid a divide-by-zero condition on the way.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20221201152223.3133-1-andre.przywara@arm.com
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-sun4i.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 37d75e252d4e7..b973da73e9ab4 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -118,6 +118,8 @@ static int sun4i_pwm_get_state(struct pwm_chip *chip,
 	unsigned int prescaler;
 
 	clk_rate = clk_get_rate(sun4i_pwm->clk);
+	if (!clk_rate)
+		return -EINVAL;
 
 	val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
 
@@ -142,7 +144,7 @@ static int sun4i_pwm_get_state(struct pwm_chip *chip,
 		prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
 
 	if (prescaler == 0)
-		return 0;
+		return -EINVAL;
 
 	if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
 		state->polarity = PWM_POLARITY_NORMAL;
-- 
GitLab


From 8fa22f4b88e877c0811d2a0e506cf56755add554 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 2 Dec 2022 19:35:38 +0100
Subject: [PATCH 154/875] pwm: pca9685: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Link: https://lore.kernel.org/r/20221118224540.619276-538-uwe@kleine-koenig.org
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
 drivers/pwm/pwm-pca9685.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/pwm/pwm-pca9685.c b/drivers/pwm/pwm-pca9685.c
index 41be244e7dd3d..3ed5a48ca5812 100644
--- a/drivers/pwm/pwm-pca9685.c
+++ b/drivers/pwm/pwm-pca9685.c
@@ -515,8 +515,7 @@ static const struct regmap_config pca9685_regmap_i2c_config = {
 	.cache_type = REGCACHE_NONE,
 };
 
-static int pca9685_pwm_probe(struct i2c_client *client,
-				const struct i2c_device_id *id)
+static int pca9685_pwm_probe(struct i2c_client *client)
 {
 	struct pca9685 *pca;
 	unsigned int reg;
@@ -666,7 +665,7 @@ static struct i2c_driver pca9685_i2c_driver = {
 		.of_match_table = of_match_ptr(pca9685_dt_ids),
 		.pm = &pca9685_pwm_pm,
 	},
-	.probe = pca9685_pwm_probe,
+	.probe_new = pca9685_pwm_probe,
 	.remove = pca9685_pwm_remove,
 	.id_table = pca9685_id,
 };
-- 
GitLab


From e78a11174de9e84e2f685618432754b83bd9f4ec Mon Sep 17 00:00:00 2001
From: XiakaiPan <13212017962@163.com>
Date: Wed, 7 Dec 2022 09:16:02 +0530
Subject: [PATCH 155/875] RISC-V: KVM: Add exit logic to main.c

Several lines of code are inserted to remove KVM module normally
using rmmod command just like others.

Signed-off-by: XiakaiPan <13212017962@163.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Tested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
---
 arch/riscv/kvm/main.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c
index df2d8716851f2..58c5489d3031a 100644
--- a/arch/riscv/kvm/main.c
+++ b/arch/riscv/kvm/main.c
@@ -127,3 +127,9 @@ static int __init riscv_kvm_init(void)
 	return kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
 }
 module_init(riscv_kvm_init);
+
+static void __exit riscv_kvm_exit(void)
+{
+	kvm_exit();
+}
+module_exit(riscv_kvm_exit);
-- 
GitLab


From b3f2575a993497dde19c18db73208325e8efba60 Mon Sep 17 00:00:00 2001
From: Bo Liu <liubo03@inspur.com>
Date: Wed, 7 Dec 2022 09:16:11 +0530
Subject: [PATCH 156/875] RISC-V: KVM: use vma_lookup() instead of
 find_vma_intersection()

vma_lookup() finds the vma of a specific address with a cleaner
interface and is more readable.

Signed-off-by: Bo Liu <liubo03@inspur.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
---
 arch/riscv/kvm/mmu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c
index 3620ecac2fa14..5942d10c97361 100644
--- a/arch/riscv/kvm/mmu.c
+++ b/arch/riscv/kvm/mmu.c
@@ -632,7 +632,7 @@ int kvm_riscv_gstage_map(struct kvm_vcpu *vcpu,
 
 	mmap_read_lock(current->mm);
 
-	vma = find_vma_intersection(current->mm, hva, hva + 1);
+	vma = vma_lookup(current->mm, hva);
 	if (unlikely(!vma)) {
 		kvm_err("Failed to find VMA for hva 0x%lx\n", hva);
 		mmap_read_unlock(current->mm);
-- 
GitLab


From af934432e4a169f7252a114a6c5c7289366bd0ab Mon Sep 17 00:00:00 2001
From: Anup Patel <apatel@ventanamicro.com>
Date: Wed, 7 Dec 2022 09:16:21 +0530
Subject: [PATCH 157/875] RISC-V: KVM: Exit run-loop immediately if
 xfer_to_guest fails

If xfer_to_guest_mode_handle_work() fails in the run-loop then exit
the run-loop immediately instead of doing it after some more work.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
---
 arch/riscv/kvm/vcpu.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 71ebbc4821f0e..17d5b3f8c2eec 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -984,8 +984,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
 	while (ret > 0) {
 		/* Check conditions before entering the guest */
 		ret = xfer_to_guest_mode_handle_work(vcpu);
-		if (!ret)
-			ret = 1;
+		if (ret)
+			continue;
+		ret = 1;
 
 		kvm_riscv_gstage_vmid_update(vcpu);
 
-- 
GitLab


From 3e2d4756e2e5dd854b36aa947d7b6168f21dc4a1 Mon Sep 17 00:00:00 2001
From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Date: Wed, 7 Dec 2022 09:16:39 +0530
Subject: [PATCH 158/875] RISC-V: KVM: Simplify
 kvm_arch_prepare_memory_region()

In kvm_arch_prepare_memory_region(), if no error occurs, a spin_lock()/
spin_unlock() call can be avoided.

Switch to kvm_riscv_gstage_iounmap() that is the same as the current code,
but with a better semantic.
It also embeds the locking logic. So it is avoided if ret == 0.

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Anup Patel <anup@brainfault.org>
---
 arch/riscv/kvm/mmu.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c
index 5942d10c97361..34b57e0be2ef0 100644
--- a/arch/riscv/kvm/mmu.c
+++ b/arch/riscv/kvm/mmu.c
@@ -537,10 +537,8 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm,
 	if (change == KVM_MR_FLAGS_ONLY)
 		goto out;
 
-	spin_lock(&kvm->mmu_lock);
 	if (ret)
-		gstage_unmap_range(kvm, base_gpa, size, false);
-	spin_unlock(&kvm->mmu_lock);
+		kvm_riscv_gstage_iounmap(kvm, base_gpa, size);
 
 out:
 	mmap_read_unlock(current->mm);
-- 
GitLab


From e482d9e33d5b0f222cbef7341dcd52cead6b9edc Mon Sep 17 00:00:00 2001
From: Anup Patel <apatel@ventanamicro.com>
Date: Wed, 7 Dec 2022 09:16:51 +0530
Subject: [PATCH 159/875] RISC-V: KVM: Fix reg_val check in
 kvm_riscv_vcpu_set_reg_config()

The reg_val check in kvm_riscv_vcpu_set_reg_config() should only
be done for isa config register.

Fixes: 9bfd900beeec ("RISC-V: KVM: Improve ISA extension by using a bitmap")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
---
 arch/riscv/kvm/vcpu.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 17d5b3f8c2eec..982a3f5e7130c 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -296,12 +296,15 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
 	if (copy_from_user(&reg_val, uaddr, KVM_REG_SIZE(reg->id)))
 		return -EFAULT;
 
-	/* This ONE REG interface is only defined for single letter extensions */
-	if (fls(reg_val) >= RISCV_ISA_EXT_BASE)
-		return -EINVAL;
-
 	switch (reg_num) {
 	case KVM_REG_RISCV_CONFIG_REG(isa):
+		/*
+		 * This ONE REG interface is only defined for
+		 * single letter extensions.
+		 */
+		if (fls(reg_val) >= RISCV_ISA_EXT_BASE)
+			return -EINVAL;
+
 		if (!vcpu->arch.ran_atleast_once) {
 			/* Ignore the enable/disable request for certain extensions */
 			for (i = 0; i < RISCV_ISA_EXT_BASE; i++) {
-- 
GitLab


From fabd6179d08229cdb0f8ccfc4d9ec3ff379d9f28 Mon Sep 17 00:00:00 2001
From: Anup Patel <apatel@ventanamicro.com>
Date: Wed, 7 Dec 2022 09:17:05 +0530
Subject: [PATCH 160/875] RISC-V: KVM: Remove redundant includes of
 asm/kvm_vcpu_timer.h

The asm/kvm_vcpu_timer.h is redundantly included in vcpu_sbi_base.c
so let us remove it.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
---
 arch/riscv/kvm/vcpu_sbi_base.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
index 48f431091cdbc..22b9126e2872f 100644
--- a/arch/riscv/kvm/vcpu_sbi_base.c
+++ b/arch/riscv/kvm/vcpu_sbi_base.c
@@ -12,7 +12,6 @@
 #include <linux/version.h>
 #include <asm/csr.h>
 #include <asm/sbi.h>
-#include <asm/kvm_vcpu_timer.h>
 #include <asm/kvm_vcpu_sbi.h>
 
 static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
-- 
GitLab


From 1343c61a7032cf85680b666a340d9c4c683b2ec8 Mon Sep 17 00:00:00 2001
From: Anup Patel <apatel@ventanamicro.com>
Date: Wed, 7 Dec 2022 09:17:12 +0530
Subject: [PATCH 161/875] RISC-V: KVM: Remove redundant includes of asm/csr.h

We should include asm/csr.h only where required so let us remove
redundant includes of this header.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
---
 arch/riscv/include/asm/kvm_host.h | 1 -
 arch/riscv/kvm/vcpu_sbi_base.c    | 1 -
 arch/riscv/kvm/vcpu_sbi_hsm.c     | 1 -
 arch/riscv/kvm/vcpu_sbi_replace.c | 1 -
 arch/riscv/kvm/vcpu_sbi_v01.c     | 1 -
 5 files changed, 5 deletions(-)

diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
index dbbf43d526234..6502f90999651 100644
--- a/arch/riscv/include/asm/kvm_host.h
+++ b/arch/riscv/include/asm/kvm_host.h
@@ -13,7 +13,6 @@
 #include <linux/kvm.h>
 #include <linux/kvm_types.h>
 #include <linux/spinlock.h>
-#include <asm/csr.h>
 #include <asm/hwcap.h>
 #include <asm/kvm_vcpu_fp.h>
 #include <asm/kvm_vcpu_insn.h>
diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
index 22b9126e2872f..0c806f61c629d 100644
--- a/arch/riscv/kvm/vcpu_sbi_base.c
+++ b/arch/riscv/kvm/vcpu_sbi_base.c
@@ -10,7 +10,6 @@
 #include <linux/err.h>
 #include <linux/kvm_host.h>
 #include <linux/version.h>
-#include <asm/csr.h>
 #include <asm/sbi.h>
 #include <asm/kvm_vcpu_sbi.h>
 
diff --git a/arch/riscv/kvm/vcpu_sbi_hsm.c b/arch/riscv/kvm/vcpu_sbi_hsm.c
index 239dec0a628a2..2e915cafd5519 100644
--- a/arch/riscv/kvm/vcpu_sbi_hsm.c
+++ b/arch/riscv/kvm/vcpu_sbi_hsm.c
@@ -9,7 +9,6 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/kvm_host.h>
-#include <asm/csr.h>
 #include <asm/sbi.h>
 #include <asm/kvm_vcpu_sbi.h>
 
diff --git a/arch/riscv/kvm/vcpu_sbi_replace.c b/arch/riscv/kvm/vcpu_sbi_replace.c
index 4c034d8a606a1..03a0198389f07 100644
--- a/arch/riscv/kvm/vcpu_sbi_replace.c
+++ b/arch/riscv/kvm/vcpu_sbi_replace.c
@@ -9,7 +9,6 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/kvm_host.h>
-#include <asm/csr.h>
 #include <asm/sbi.h>
 #include <asm/kvm_vcpu_timer.h>
 #include <asm/kvm_vcpu_sbi.h>
diff --git a/arch/riscv/kvm/vcpu_sbi_v01.c b/arch/riscv/kvm/vcpu_sbi_v01.c
index 8a91a14e7139a..489f225ee66d1 100644
--- a/arch/riscv/kvm/vcpu_sbi_v01.c
+++ b/arch/riscv/kvm/vcpu_sbi_v01.c
@@ -9,7 +9,6 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/kvm_host.h>
-#include <asm/csr.h>
 #include <asm/sbi.h>
 #include <asm/kvm_vcpu_timer.h>
 #include <asm/kvm_vcpu_sbi.h>
-- 
GitLab


From e81af89baebf86938cda1a7c2bee51c676c04e21 Mon Sep 17 00:00:00 2001
From: Anup Patel <apatel@ventanamicro.com>
Date: Wed, 7 Dec 2022 09:17:19 +0530
Subject: [PATCH 162/875] RISC-V: KVM: Use switch-case in
 kvm_riscv_vcpu_set/get_reg()

We should use switch-case in kvm_riscv_vcpu_set/get_reg() functions
because the else-if ladder is quite big now.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
---
 arch/riscv/kvm/vcpu.c | 36 ++++++++++++++++++++++--------------
 1 file changed, 22 insertions(+), 14 deletions(-)

diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 982a3f5e7130c..68c86f632d370 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -544,22 +544,26 @@ static int kvm_riscv_vcpu_set_reg_isa_ext(struct kvm_vcpu *vcpu,
 static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
 				  const struct kvm_one_reg *reg)
 {
-	if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG)
+	switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
+	case KVM_REG_RISCV_CONFIG:
 		return kvm_riscv_vcpu_set_reg_config(vcpu, reg);
-	else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE)
+	case KVM_REG_RISCV_CORE:
 		return kvm_riscv_vcpu_set_reg_core(vcpu, reg);
-	else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)
+	case KVM_REG_RISCV_CSR:
 		return kvm_riscv_vcpu_set_reg_csr(vcpu, reg);
-	else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
+	case KVM_REG_RISCV_TIMER:
 		return kvm_riscv_vcpu_set_reg_timer(vcpu, reg);
-	else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
+	case KVM_REG_RISCV_FP_F:
 		return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
 						 KVM_REG_RISCV_FP_F);
-	else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
+	case KVM_REG_RISCV_FP_D:
 		return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
 						 KVM_REG_RISCV_FP_D);
-	else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT)
+	case KVM_REG_RISCV_ISA_EXT:
 		return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg);
+	default:
+		break;
+	}
 
 	return -EINVAL;
 }
@@ -567,22 +571,26 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
 static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu,
 				  const struct kvm_one_reg *reg)
 {
-	if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG)
+	switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
+	case KVM_REG_RISCV_CONFIG:
 		return kvm_riscv_vcpu_get_reg_config(vcpu, reg);
-	else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE)
+	case KVM_REG_RISCV_CORE:
 		return kvm_riscv_vcpu_get_reg_core(vcpu, reg);
-	else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)
+	case KVM_REG_RISCV_CSR:
 		return kvm_riscv_vcpu_get_reg_csr(vcpu, reg);
-	else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
+	case KVM_REG_RISCV_TIMER:
 		return kvm_riscv_vcpu_get_reg_timer(vcpu, reg);
-	else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
+	case KVM_REG_RISCV_FP_F:
 		return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
 						 KVM_REG_RISCV_FP_F);
-	else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
+	case KVM_REG_RISCV_FP_D:
 		return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
 						 KVM_REG_RISCV_FP_D);
-	else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT)
+	case KVM_REG_RISCV_ISA_EXT:
 		return kvm_riscv_vcpu_get_reg_isa_ext(vcpu, reg);
+	default:
+		break;
+	}
 
 	return -EINVAL;
 }
-- 
GitLab


From 23fe562e45c5959590a24d05c61c963f10ccb934 Mon Sep 17 00:00:00 2001
From: Anup Patel <apatel@ventanamicro.com>
Date: Wed, 7 Dec 2022 09:17:27 +0530
Subject: [PATCH 163/875] RISC-V: KVM: Move sbi related struct and functions to
 kvm_vcpu_sbi.h

Just like asm/kvm_vcpu_timer.h, we should have all sbi related struct
and functions in asm/kvm_vcpu_sbi.h.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
---
 arch/riscv/include/asm/kvm_host.h     | 10 ++--------
 arch/riscv/include/asm/kvm_vcpu_sbi.h |  6 ++++++
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
index 6502f90999651..91c74b09a9709 100644
--- a/arch/riscv/include/asm/kvm_host.h
+++ b/arch/riscv/include/asm/kvm_host.h
@@ -16,6 +16,7 @@
 #include <asm/hwcap.h>
 #include <asm/kvm_vcpu_fp.h>
 #include <asm/kvm_vcpu_insn.h>
+#include <asm/kvm_vcpu_sbi.h>
 #include <asm/kvm_vcpu_timer.h>
 
 #define KVM_MAX_VCPUS			1024
@@ -94,10 +95,6 @@ struct kvm_arch {
 	struct kvm_guest_timer timer;
 };
 
-struct kvm_sbi_context {
-	int return_handled;
-};
-
 struct kvm_cpu_trap {
 	unsigned long sepc;
 	unsigned long scause;
@@ -216,7 +213,7 @@ struct kvm_vcpu_arch {
 	struct kvm_csr_decode csr_decode;
 
 	/* SBI context */
-	struct kvm_sbi_context sbi_context;
+	struct kvm_vcpu_sbi_context sbi_context;
 
 	/* Cache pages needed to program page tables with spinlock held */
 	struct kvm_mmu_memory_cache mmu_page_cache;
@@ -326,7 +323,4 @@ bool kvm_riscv_vcpu_has_interrupts(struct kvm_vcpu *vcpu, unsigned long mask);
 void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu);
 void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu);
 
-int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
-int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run);
-
 #endif /* __RISCV_KVM_HOST_H__ */
diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm/kvm_vcpu_sbi.h
index d4e3e600beefb..f79478a85d2df 100644
--- a/arch/riscv/include/asm/kvm_vcpu_sbi.h
+++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h
@@ -14,6 +14,10 @@
 #define KVM_SBI_VERSION_MAJOR 1
 #define KVM_SBI_VERSION_MINOR 0
 
+struct kvm_vcpu_sbi_context {
+	int return_handled;
+};
+
 struct kvm_vcpu_sbi_extension {
 	unsigned long extid_start;
 	unsigned long extid_end;
@@ -31,7 +35,9 @@ void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run);
 void kvm_riscv_vcpu_sbi_system_reset(struct kvm_vcpu *vcpu,
 				     struct kvm_run *run,
 				     u32 type, u64 flags);
+int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
 const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(unsigned long extid);
+int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run);
 
 #ifdef CONFIG_RISCV_SBI_V01
 extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01;
-- 
GitLab


From a1a44e227ce69459ca43aa9dadaa1b58619b18ee Mon Sep 17 00:00:00 2001
From: Anup Patel <apatel@ventanamicro.com>
Date: Wed, 7 Dec 2022 09:17:38 +0530
Subject: [PATCH 164/875] RISC-V: Export sbi_get_mvendorid() and friends

The sbi_get_mvendorid(), sbi_get_marchid(), and sbi_get_mimpid()
can be used by KVM module so let us export these functions.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
---
 arch/riscv/kernel/sbi.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 775d3322b422f..5c87db8fdff2d 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -627,16 +627,19 @@ long sbi_get_mvendorid(void)
 {
 	return __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID);
 }
+EXPORT_SYMBOL_GPL(sbi_get_mvendorid);
 
 long sbi_get_marchid(void)
 {
 	return __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID);
 }
+EXPORT_SYMBOL_GPL(sbi_get_marchid);
 
 long sbi_get_mimpid(void)
 {
 	return __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID);
 }
+EXPORT_SYMBOL_GPL(sbi_get_mimpid);
 
 static void sbi_send_cpumask_ipi(const struct cpumask *target)
 {
-- 
GitLab


From 52ec4b695dbe0552bb994c4149e9122610a76668 Mon Sep 17 00:00:00 2001
From: Anup Patel <apatel@ventanamicro.com>
Date: Wed, 7 Dec 2022 09:17:43 +0530
Subject: [PATCH 165/875] RISC-V: KVM: Save mvendorid, marchid, and mimpid when
 creating VCPU

We should save VCPU mvendorid, marchid, and mimpid at the time
of creating VCPU so that we don't have to do host SBI call every
time Guest/VM ask for these details.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
---
 arch/riscv/include/asm/kvm_host.h |  5 +++++
 arch/riscv/kvm/vcpu.c             |  6 ++++++
 arch/riscv/kvm/vcpu_sbi_base.c    | 11 +++++------
 3 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
index 91c74b09a9709..93f43a3e78865 100644
--- a/arch/riscv/include/asm/kvm_host.h
+++ b/arch/riscv/include/asm/kvm_host.h
@@ -165,6 +165,11 @@ struct kvm_vcpu_arch {
 	/* ISA feature bits (similar to MISA) */
 	DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
 
+	/* Vendor, Arch, and Implementation details */
+	unsigned long mvendorid;
+	unsigned long marchid;
+	unsigned long mimpid;
+
 	/* SSCRATCH, STVEC, and SCOUNTEREN of Host */
 	unsigned long host_sscratch;
 	unsigned long host_stvec;
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 68c86f632d370..312a8a9268677 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -21,6 +21,7 @@
 #include <asm/csr.h>
 #include <asm/cacheflush.h>
 #include <asm/hwcap.h>
+#include <asm/sbi.h>
 
 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
 	KVM_GENERIC_VCPU_STATS(),
@@ -171,6 +172,11 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
 			set_bit(host_isa, vcpu->arch.isa);
 	}
 
+	/* Setup vendor, arch, and implementation details */
+	vcpu->arch.mvendorid = sbi_get_mvendorid();
+	vcpu->arch.marchid = sbi_get_marchid();
+	vcpu->arch.mimpid = sbi_get_mimpid();
+
 	/* Setup VCPU hfence queue */
 	spin_lock_init(&vcpu->arch.hfence_lock);
 
diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
index 0c806f61c629d..5d65c634d3012 100644
--- a/arch/riscv/kvm/vcpu_sbi_base.c
+++ b/arch/riscv/kvm/vcpu_sbi_base.c
@@ -19,7 +19,6 @@ static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
 {
 	int ret = 0;
 	struct kvm_cpu_context *cp = &vcpu->arch.guest_context;
-	struct sbiret ecall_ret;
 
 	switch (cp->a6) {
 	case SBI_EXT_BASE_GET_SPEC_VERSION:
@@ -48,13 +47,13 @@ static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
 			*out_val = kvm_vcpu_sbi_find_ext(cp->a0) ? 1 : 0;
 		break;
 	case SBI_EXT_BASE_GET_MVENDORID:
+		*out_val = vcpu->arch.mvendorid;
+		break;
 	case SBI_EXT_BASE_GET_MARCHID:
+		*out_val = vcpu->arch.marchid;
+		break;
 	case SBI_EXT_BASE_GET_MIMPID:
-		ecall_ret = sbi_ecall(SBI_EXT_BASE, cp->a6, 0, 0, 0, 0, 0, 0);
-		if (!ecall_ret.error)
-			*out_val = ecall_ret.value;
-		/*TODO: We are unnecessarily converting the error twice */
-		ret = sbi_err_map_linux_errno(ecall_ret.error);
+		*out_val = vcpu->arch.mimpid;
 		break;
 	default:
 		ret = -EOPNOTSUPP;
-- 
GitLab


From 6ebbdecff6ae00557a52539287b681641f4f0d33 Mon Sep 17 00:00:00 2001
From: Anup Patel <apatel@ventanamicro.com>
Date: Wed, 7 Dec 2022 09:17:49 +0530
Subject: [PATCH 166/875] RISC-V: KVM: Add ONE_REG interface for mvendorid,
 marchid, and mimpid

We add ONE_REG interface for VCPU mvendorid, marchid, and mimpid
so that KVM user-space can change this details to support migration
across heterogeneous hosts.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
---
 arch/riscv/include/uapi/asm/kvm.h |  3 +++
 arch/riscv/kvm/vcpu.c             | 27 +++++++++++++++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 8985ff234c01c..92af6f3f057cf 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -49,6 +49,9 @@ struct kvm_sregs {
 struct kvm_riscv_config {
 	unsigned long isa;
 	unsigned long zicbom_block_size;
+	unsigned long mvendorid;
+	unsigned long marchid;
+	unsigned long mimpid;
 };
 
 /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 312a8a9268677..7c08567097f0a 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -276,6 +276,15 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
 			return -EINVAL;
 		reg_val = riscv_cbom_block_size;
 		break;
+	case KVM_REG_RISCV_CONFIG_REG(mvendorid):
+		reg_val = vcpu->arch.mvendorid;
+		break;
+	case KVM_REG_RISCV_CONFIG_REG(marchid):
+		reg_val = vcpu->arch.marchid;
+		break;
+	case KVM_REG_RISCV_CONFIG_REG(mimpid):
+		reg_val = vcpu->arch.mimpid;
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -338,6 +347,24 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
 		break;
 	case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
 		return -EOPNOTSUPP;
+	case KVM_REG_RISCV_CONFIG_REG(mvendorid):
+		if (!vcpu->arch.ran_atleast_once)
+			vcpu->arch.mvendorid = reg_val;
+		else
+			return -EBUSY;
+		break;
+	case KVM_REG_RISCV_CONFIG_REG(marchid):
+		if (!vcpu->arch.ran_atleast_once)
+			vcpu->arch.marchid = reg_val;
+		else
+			return -EBUSY;
+		break;
+	case KVM_REG_RISCV_CONFIG_REG(mimpid):
+		if (!vcpu->arch.ran_atleast_once)
+			vcpu->arch.mimpid = reg_val;
+		else
+			return -EBUSY;
+		break;
 	default:
 		return -EINVAL;
 	}
-- 
GitLab


From 7bd156cbbd0add4b869a7d997d057b76c329f4e5 Mon Sep 17 00:00:00 2001
From: Jeff Johnson <quic_jjohnson@quicinc.com>
Date: Wed, 14 Sep 2022 16:47:03 -0700
Subject: [PATCH 167/875] remoteproc: sysmon: Make QMI message rules const

Commit ff6d365898d4 ("soc: qcom: qmi: use const for struct
qmi_elem_info") allows QMI message encoding/decoding rules to be
const, so do that for sysmon.

Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com>
Reviewed-by: Alex Elder <elder@linaro.org>
Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220914234705.28405-3-quic_jjohnson@quicinc.com
---
 drivers/remoteproc/qcom_sysmon.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/remoteproc/qcom_sysmon.c b/drivers/remoteproc/qcom_sysmon.c
index 57dde2a69b9dd..3992bb61d2ec1 100644
--- a/drivers/remoteproc/qcom_sysmon.c
+++ b/drivers/remoteproc/qcom_sysmon.c
@@ -190,7 +190,7 @@ struct ssctl_shutdown_resp {
 	struct qmi_response_type_v01 resp;
 };
 
-static struct qmi_elem_info ssctl_shutdown_resp_ei[] = {
+static const struct qmi_elem_info ssctl_shutdown_resp_ei[] = {
 	{
 		.data_type	= QMI_STRUCT,
 		.elem_len	= 1,
@@ -211,7 +211,7 @@ struct ssctl_subsys_event_req {
 	u32 evt_driven;
 };
 
-static struct qmi_elem_info ssctl_subsys_event_req_ei[] = {
+static const struct qmi_elem_info ssctl_subsys_event_req_ei[] = {
 	{
 		.data_type	= QMI_DATA_LEN,
 		.elem_len	= 1,
@@ -269,7 +269,7 @@ struct ssctl_subsys_event_resp {
 	struct qmi_response_type_v01 resp;
 };
 
-static struct qmi_elem_info ssctl_subsys_event_resp_ei[] = {
+static const struct qmi_elem_info ssctl_subsys_event_resp_ei[] = {
 	{
 		.data_type	= QMI_STRUCT,
 		.elem_len	= 1,
@@ -283,7 +283,7 @@ static struct qmi_elem_info ssctl_subsys_event_resp_ei[] = {
 	{}
 };
 
-static struct qmi_elem_info ssctl_shutdown_ind_ei[] = {
+static const struct qmi_elem_info ssctl_shutdown_ind_ei[] = {
 	{}
 };
 
-- 
GitLab


From e01ce676aaef3b13d02343d7e70f9637d93a3367 Mon Sep 17 00:00:00 2001
From: Gaosheng Cui <cuigaosheng1@huawei.com>
Date: Tue, 29 Nov 2022 18:56:50 +0800
Subject: [PATCH 168/875] remoteproc: sysmon: fix memory leak in
 qcom_add_sysmon_subdev()

The kfree() should be called when of_irq_get_byname() fails or
devm_request_threaded_irq() fails in qcom_add_sysmon_subdev(),
otherwise there will be a memory leak, so add kfree() to fix it.

Fixes: 027045a6e2b7 ("remoteproc: qcom: Add shutdown-ack irq")
Signed-off-by: Gaosheng Cui <cuigaosheng1@huawei.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221129105650.1539187-1-cuigaosheng1@huawei.com
---
 drivers/remoteproc/qcom_sysmon.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/remoteproc/qcom_sysmon.c b/drivers/remoteproc/qcom_sysmon.c
index 3992bb61d2ec1..85393d5eb0058 100644
--- a/drivers/remoteproc/qcom_sysmon.c
+++ b/drivers/remoteproc/qcom_sysmon.c
@@ -652,7 +652,9 @@ struct qcom_sysmon *qcom_add_sysmon_subdev(struct rproc *rproc,
 		if (sysmon->shutdown_irq != -ENODATA) {
 			dev_err(sysmon->dev,
 				"failed to retrieve shutdown-ack IRQ\n");
-			return ERR_PTR(sysmon->shutdown_irq);
+			ret = sysmon->shutdown_irq;
+			kfree(sysmon);
+			return ERR_PTR(ret);
 		}
 	} else {
 		ret = devm_request_threaded_irq(sysmon->dev,
@@ -663,6 +665,7 @@ struct qcom_sysmon *qcom_add_sysmon_subdev(struct rproc *rproc,
 		if (ret) {
 			dev_err(sysmon->dev,
 				"failed to acquire shutdown-ack IRQ\n");
+			kfree(sysmon);
 			return ERR_PTR(ret);
 		}
 	}
-- 
GitLab


From f360e2b275efbb745ba0af8b47d9ef44221be586 Mon Sep 17 00:00:00 2001
From: Shang XiaoJing <shangxiaojing@huawei.com>
Date: Fri, 25 Nov 2022 10:16:41 +0800
Subject: [PATCH 169/875] remoteproc: qcom: q6v5: Fix potential null-ptr-deref
 in q6v5_wcss_init_mmio()

q6v5_wcss_init_mmio() will call platform_get_resource_byname() that may
fail and return NULL. devm_ioremap() will use res->start as input, which
may causes null-ptr-deref. Check the ret value of
platform_get_resource_byname() to avoid the null-ptr-deref.

Fixes: 0af65b9b915e ("remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404")
Signed-off-by: Shang XiaoJing <shangxiaojing@huawei.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221125021641.29392-1-shangxiaojing@huawei.com
---
 drivers/remoteproc/qcom_q6v5_wcss.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c
index bb0947f7770ea..de232337e082c 100644
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -827,6 +827,9 @@ static int q6v5_wcss_init_mmio(struct q6v5_wcss *wcss,
 	int ret;
 
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
+	if (!res)
+		return -EINVAL;
+
 	wcss->reg_base = devm_ioremap(&pdev->dev, res->start,
 				      resource_size(res));
 	if (!wcss->reg_base)
-- 
GitLab


From 9a70551996e699fda262e8d54bbd41739d7aad6d Mon Sep 17 00:00:00 2001
From: Luca Weiss <luca.weiss@fairphone.com>
Date: Fri, 18 Nov 2022 10:08:15 +0100
Subject: [PATCH 170/875] remoteproc: qcom_q6v5_pas: disable wakeup on probe
 fail or remove

Leaving wakeup enabled during probe fail (-EPROBE_DEFER) or remove makes
the subsequent probe fail.

[    3.749454] remoteproc remoteproc0: releasing 3000000.remoteproc
[    3.752949] qcom_q6v5_pas: probe of 3000000.remoteproc failed with error -17
[    3.878935] remoteproc remoteproc0: releasing 4080000.remoteproc
[    3.887602] qcom_q6v5_pas: probe of 4080000.remoteproc failed with error -17
[    4.319552] remoteproc remoteproc0: releasing 8300000.remoteproc
[    4.332716] qcom_q6v5_pas: probe of 8300000.remoteproc failed with error -17

Fix this by disabling wakeup in both cases so the driver can properly
probe on the next try.

Fixes: a781e5aa5911 ("remoteproc: core: Prevent system suspend during remoteproc recovery")
Fixes: dc86c129b4fb ("remoteproc: qcom: pas: Mark devices as wakeup capable")
Reviewed-by: Mukesh Ojha <quic_mojha@quicinc.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221118090816.100012-1-luca.weiss@fairphone.com
---
 drivers/remoteproc/qcom_q6v5_pas.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
index 6afd0941e5524..67f5152e23985 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -556,6 +556,7 @@ static int adsp_probe(struct platform_device *pdev)
 detach_proxy_pds:
 	adsp_pds_detach(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
 free_rproc:
+	device_init_wakeup(adsp->dev, false);
 	rproc_free(rproc);
 
 	return ret;
@@ -572,6 +573,7 @@ static int adsp_remove(struct platform_device *pdev)
 	qcom_remove_sysmon_subdev(adsp->sysmon);
 	qcom_remove_smd_subdev(adsp->rproc, &adsp->smd_subdev);
 	qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
+	device_init_wakeup(adsp->dev, false);
 	rproc_free(adsp->rproc);
 
 	return 0;
-- 
GitLab


From 34d01df00b84127be04c914fc9f8e8be1fcdf851 Mon Sep 17 00:00:00 2001
From: Luca Weiss <luca.weiss@fairphone.com>
Date: Fri, 18 Nov 2022 10:08:16 +0100
Subject: [PATCH 171/875] remoteproc: qcom_q6v5_pas: detach power domains on
 remove

We need to detach from the power domains also on remove, not just on
probe fail so a subsequent probe works as expected.

Otherwise the following error appears on re-probe:

[   29.452005] sysfs: cannot create duplicate filename '/devices/genpd:0:3000000.remoteproc'
[   29.477121] CPU: 1 PID: 483 Comm: sh Tainted: G        W          6.1.0-rc4-00075-g71a113770bda #78
[   29.510319] Hardware name: Fairphone 4 (DT)
[   29.538335] Call trace:
[   29.564470]  dump_backtrace.part.0+0xe0/0xf0
[   29.592602]  show_stack+0x18/0x30
[   29.619616]  dump_stack_lvl+0x64/0x80
[   29.646834]  dump_stack+0x18/0x34
[   29.673541]  sysfs_warn_dup+0x60/0x7c
[   29.700592]  sysfs_create_dir_ns+0xec/0x110
[   29.728057]  kobject_add_internal+0xb8/0x374
[   29.755530]  kobject_add+0x9c/0x104
[   29.782072]  device_add+0xbc/0x8a0
[   29.808445]  device_register+0x20/0x30
[   29.835175]  genpd_dev_pm_attach_by_id+0xa4/0x190
[   29.862851]  genpd_dev_pm_attach_by_name+0x3c/0xb0
[   29.890472]  dev_pm_domain_attach_by_name+0x20/0x30
[   29.918212]  adsp_probe+0x278/0x580
[   29.944384]  platform_probe+0x68/0xc0
[   29.970603]  really_probe+0xbc/0x2dc
[   29.996662]  __driver_probe_device+0x78/0xe0
[   30.023491]  device_driver_attach+0x48/0xac
[   30.050215]  bind_store+0xb8/0x114
[   30.075957]  drv_attr_store+0x24/0x3c
[   30.101874]  sysfs_kf_write+0x44/0x54
[   30.127751]  kernfs_fop_write_iter+0x120/0x1f0
[   30.154448]  vfs_write+0x1ac/0x380
[   30.179937]  ksys_write+0x70/0x104
[   30.205274]  __arm64_sys_write+0x1c/0x2c
[   30.231060]  invoke_syscall+0x48/0x114
[   30.256594]  el0_svc_common.constprop.0+0x44/0xec
[   30.283183]  do_el0_svc+0x2c/0xd0
[   30.308320]  el0_svc+0x2c/0x84
[   30.333059]  el0t_64_sync_handler+0xf4/0x120
[   30.359001]  el0t_64_sync+0x18c/0x190
[   30.384385] kobject_add_internal failed for genpd:0:3000000.remoteproc with -EEXIST, don't try to register things with the same name in the same directory.
[   30.406029] remoteproc remoteproc0: releasing 3000000.remoteproc
[   30.416064] qcom_q6v5_pas: probe of 3000000.remoteproc failed with error -17

Fixes: 17ee2fb4e856 ("remoteproc: qcom: pas: Vote for active/proxy power domains")
Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>
Reviewed-by: Mukesh Ojha <quic_mojha@quicinc.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221118090816.100012-2-luca.weiss@fairphone.com
---
 drivers/remoteproc/qcom_q6v5_pas.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
index 67f5152e23985..a14ff1142e761 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -573,6 +573,7 @@ static int adsp_remove(struct platform_device *pdev)
 	qcom_remove_sysmon_subdev(adsp->sysmon);
 	qcom_remove_smd_subdev(adsp->rproc, &adsp->smd_subdev);
 	qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
+	adsp_pds_detach(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
 	device_init_wakeup(adsp->dev, false);
 	rproc_free(adsp->rproc);
 
-- 
GitLab


From 38e7d9c19276832ebb0277f415b9214bf7baeb37 Mon Sep 17 00:00:00 2001
From: Yuan Can <yuancan@huawei.com>
Date: Sat, 3 Dec 2022 07:06:39 +0000
Subject: [PATCH 172/875] remoteproc: qcom_q6v5_pas: Fix missing of_node_put()
 in adsp_alloc_memory_region()

The pointer node is returned by of_parse_phandle() with refcount
incremented. We should use of_node_put() on it when done.

Fixes: b9e718e950c3 ("remoteproc: Introduce Qualcomm ADSP PIL")
Signed-off-by: Yuan Can <yuancan@huawei.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221203070639.15128-1-yuancan@huawei.com
---
 drivers/remoteproc/qcom_q6v5_pas.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
index a14ff1142e761..dc6f07ca83410 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -449,6 +449,7 @@ static int adsp_alloc_memory_region(struct qcom_adsp *adsp)
 	}
 
 	ret = of_address_to_resource(node, 0, &r);
+	of_node_put(node);
 	if (ret)
 		return ret;
 
-- 
GitLab


From 7ff5d60f18bba5cbaf17b2926aa9da44d5beca01 Mon Sep 17 00:00:00 2001
From: Shang XiaoJing <shangxiaojing@huawei.com>
Date: Sun, 4 Dec 2022 16:27:57 +0800
Subject: [PATCH 173/875] remoteproc: qcom: q6v5: Fix missing
 clk_disable_unprepare() in q6v5_wcss_qcs404_power_on()

q6v5_wcss_qcs404_power_on() have no fail path for readl_poll_timeout().
Add fail path for readl_poll_timeout().

Fixes: 0af65b9b915e ("remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404")
Signed-off-by: Shang XiaoJing <shangxiaojing@huawei.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221204082757.18850-1-shangxiaojing@huawei.com
---
 drivers/remoteproc/qcom_q6v5_wcss.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c
index de232337e082c..ba24d745b2d65 100644
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -351,7 +351,7 @@ static int q6v5_wcss_qcs404_power_on(struct q6v5_wcss *wcss)
 	if (ret) {
 		dev_err(wcss->dev,
 			"xo cbcr enabling timed out (rc:%d)\n", ret);
-		return ret;
+		goto disable_xo_cbcr_clk;
 	}
 
 	writel(0, wcss->reg_base + Q6SS_CGC_OVERRIDE);
@@ -417,6 +417,7 @@ disable_sleep_cbcr_clk:
 	val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR);
 	val &= ~Q6SS_CLK_ENABLE;
 	writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR);
+disable_xo_cbcr_clk:
 	val = readl(wcss->reg_base + Q6SS_XO_CBCR);
 	val &= ~Q6SS_CLK_ENABLE;
 	writel(val, wcss->reg_base + Q6SS_XO_CBCR);
-- 
GitLab


From 31b573946ea55e1ea0e08ae8e83bcf879b30f83a Mon Sep 17 00:00:00 2001
From: Jiao Zhou <jiaozhou@google.com>
Date: Tue, 6 Dec 2022 13:53:11 -0500
Subject: [PATCH 174/875] ALSA: hda/hdmi: Add HP Device 0x8711 to force connect
 list

HDMI audio is not working on the HP EliteDesk 800 G6 because the pin is
unconnected. This issue can be resolved by using the 'hdajackretask'
tool to override the unconnected pin to force it to connect.

Signed-off-by: Jiao Zhou <jiaozhou@google.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20221206185311.3669950-1-jiaozhou@google.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/pci/hda/patch_hdmi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
index 21edf7a619f07..7a40ddfd695a1 100644
--- a/sound/pci/hda/patch_hdmi.c
+++ b/sound/pci/hda/patch_hdmi.c
@@ -1975,6 +1975,7 @@ static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
 static const struct snd_pci_quirk force_connect_list[] = {
 	SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1),
 	SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1),
+	SND_PCI_QUIRK(0x103c, 0x8711, "HP", 1),
 	SND_PCI_QUIRK(0x1462, 0xec94, "MS-7C94", 1),
 	SND_PCI_QUIRK(0x8086, 0x2081, "Intel NUC 10", 1),
 	{}
-- 
GitLab


From 696b66ac26ef953aed5783ef26a252ec8f207013 Mon Sep 17 00:00:00 2001
From: wangdicheng <wangdicheng@kylinos.cn>
Date: Wed, 7 Dec 2022 16:20:36 +0800
Subject: [PATCH 175/875] ALSA: usb-audio: add the quirk for KT0206 device

Add relevant information to the quirks-table.h file.
The test passes and the sound source file plays normally.

Signed-off-by: wangdicheng <wangdicheng@kylinos.cn>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/SG2PR02MB587849631CB96809CF90DBED8A1A9@SG2PR02MB5878.apcprd02.prod.outlook.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/usb/quirks-table.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/sound/usb/quirks-table.h b/sound/usb/quirks-table.h
index 874fcf245747f..271884e350035 100644
--- a/sound/usb/quirks-table.h
+++ b/sound/usb/quirks-table.h
@@ -76,6 +76,8 @@
 { USB_DEVICE_VENDOR_SPEC(0x041e, 0x3f0a) },
 /* E-Mu 0204 USB */
 { USB_DEVICE_VENDOR_SPEC(0x041e, 0x3f19) },
+/* Ktmicro Usb_audio device */
+{ USB_DEVICE_VENDOR_SPEC(0x31b2, 0x0011) },
 
 /*
  * Creative Technology, Ltd Live! Cam Sync HD [VF0770]
-- 
GitLab


From b9420da8847874976d25489186f57ec3215ff77c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:27 +0100
Subject: [PATCH 176/875] mfd: 88pm800: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-414-uwe@kleine-koenig.org
---
 drivers/mfd/88pm800.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/88pm800.c b/drivers/mfd/88pm800.c
index a30e47b743270..5236c065da88e 100644
--- a/drivers/mfd/88pm800.c
+++ b/drivers/mfd/88pm800.c
@@ -528,8 +528,7 @@ out:
 	return ret;
 }
 
-static int pm800_probe(struct i2c_client *client,
-				 const struct i2c_device_id *id)
+static int pm800_probe(struct i2c_client *client)
 {
 	int ret = 0;
 	struct pm80x_chip *chip;
@@ -599,7 +598,7 @@ static struct i2c_driver pm800_driver = {
 		.name = "88PM800",
 		.pm = &pm80x_pm_ops,
 		},
-	.probe = pm800_probe,
+	.probe_new = pm800_probe,
 	.remove = pm800_remove,
 	.id_table = pm80x_id_table,
 };
-- 
GitLab


From 61d1be25a226b64d341aa3eb1e852f4815af18b8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:28 +0100
Subject: [PATCH 177/875] mfd: 88pm805: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-415-uwe@kleine-koenig.org
---
 drivers/mfd/88pm805.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/88pm805.c b/drivers/mfd/88pm805.c
index 10d3637840c8c..c274f1840761a 100644
--- a/drivers/mfd/88pm805.c
+++ b/drivers/mfd/88pm805.c
@@ -209,8 +209,7 @@ out_irq_init:
 	return ret;
 }
 
-static int pm805_probe(struct i2c_client *client,
-				 const struct i2c_device_id *id)
+static int pm805_probe(struct i2c_client *client)
 {
 	int ret = 0;
 	struct pm80x_chip *chip;
@@ -254,7 +253,7 @@ static struct i2c_driver pm805_driver = {
 		.name = "88PM805",
 		.pm = &pm80x_pm_ops,
 		},
-	.probe = pm805_probe,
+	.probe_new = pm805_probe,
 	.remove = pm805_remove,
 	.id_table = pm80x_id_table,
 };
-- 
GitLab


From fb53f6668273da9bd604348763a857ac83ed1406 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:29 +0100
Subject: [PATCH 178/875] mfd: aat2870-core: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-416-uwe@kleine-koenig.org
---
 drivers/mfd/aat2870-core.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/aat2870-core.c b/drivers/mfd/aat2870-core.c
index a17cf759739d0..f096dc80b7543 100644
--- a/drivers/mfd/aat2870-core.c
+++ b/drivers/mfd/aat2870-core.c
@@ -332,8 +332,7 @@ static inline void aat2870_init_debugfs(struct aat2870_data *aat2870)
 }
 #endif /* CONFIG_DEBUG_FS */
 
-static int aat2870_i2c_probe(struct i2c_client *client,
-			     const struct i2c_device_id *id)
+static int aat2870_i2c_probe(struct i2c_client *client)
 {
 	struct aat2870_platform_data *pdata = dev_get_platdata(&client->dev);
 	struct aat2870_data *aat2870;
@@ -454,7 +453,7 @@ static struct i2c_driver aat2870_i2c_driver = {
 		.pm			= &aat2870_pm_ops,
 		.suppress_bind_attrs	= true,
 	},
-	.probe		= aat2870_i2c_probe,
+	.probe_new	= aat2870_i2c_probe,
 	.id_table	= aat2870_i2c_id_table,
 };
 
-- 
GitLab


From 75a4504e49b0085229e056ffe99c8542055d2657 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:30 +0100
Subject: [PATCH 179/875] mfd: act8945a: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-417-uwe@kleine-koenig.org
---
 drivers/mfd/act8945a.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/act8945a.c b/drivers/mfd/act8945a.c
index d3520430997c3..bcf0fda15f0c3 100644
--- a/drivers/mfd/act8945a.c
+++ b/drivers/mfd/act8945a.c
@@ -28,8 +28,7 @@ static const struct regmap_config act8945a_regmap_config = {
 	.val_bits = 8,
 };
 
-static int act8945a_i2c_probe(struct i2c_client *i2c,
-			      const struct i2c_device_id *id)
+static int act8945a_i2c_probe(struct i2c_client *i2c)
 {
 	int ret;
 	struct regmap *regmap;
@@ -71,7 +70,7 @@ static struct i2c_driver act8945a_i2c_driver = {
 		   .name = "act8945a",
 		   .of_match_table = of_match_ptr(act8945a_of_match),
 	},
-	.probe = act8945a_i2c_probe,
+	.probe_new = act8945a_i2c_probe,
 	.id_table = act8945a_i2c_id,
 };
 
-- 
GitLab


From 48c2c36686125ff4a7ac6c6448dff31880ddd0df Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:31 +0100
Subject: [PATCH 180/875] mfd: adp5520: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-418-uwe@kleine-koenig.org
---
 drivers/mfd/adp5520.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/adp5520.c b/drivers/mfd/adp5520.c
index 8db15f5a7179f..bdcedb034913e 100644
--- a/drivers/mfd/adp5520.c
+++ b/drivers/mfd/adp5520.c
@@ -204,9 +204,9 @@ static int adp5520_remove_subdevs(struct adp5520_chip *chip)
 	return device_for_each_child(chip->dev, NULL, __remove_subdev);
 }
 
-static int adp5520_probe(struct i2c_client *client,
-					const struct i2c_device_id *id)
+static int adp5520_probe(struct i2c_client *client)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(client);
 	struct adp5520_platform_data *pdata = dev_get_platdata(&client->dev);
 	struct platform_device *pdev;
 	struct adp5520_chip *chip;
@@ -342,7 +342,7 @@ static struct i2c_driver adp5520_driver = {
 		.pm			= &adp5520_pm,
 		.suppress_bind_attrs	= true,
 	},
-	.probe		= adp5520_probe,
+	.probe_new	= adp5520_probe,
 	.id_table	= adp5520_id,
 };
 builtin_i2c_driver(adp5520_driver);
-- 
GitLab


From 6cb7ac1c0402e61d84652b0fb79a471aca0fb7b2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:32 +0100
Subject: [PATCH 181/875] mfd: arizona-i2c: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-419-uwe@kleine-koenig.org
---
 drivers/mfd/arizona-i2c.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/arizona-i2c.c b/drivers/mfd/arizona-i2c.c
index bfc7cf56ff2c7..20dd1b1e4ec15 100644
--- a/drivers/mfd/arizona-i2c.c
+++ b/drivers/mfd/arizona-i2c.c
@@ -20,9 +20,9 @@
 
 #include "arizona.h"
 
-static int arizona_i2c_probe(struct i2c_client *i2c,
-			     const struct i2c_device_id *id)
+static int arizona_i2c_probe(struct i2c_client *i2c)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
 	const void *match_data;
 	struct arizona *arizona;
 	const struct regmap_config *regmap_config = NULL;
@@ -120,7 +120,7 @@ static struct i2c_driver arizona_i2c_driver = {
 		.pm	= &arizona_pm_ops,
 		.of_match_table	= of_match_ptr(arizona_i2c_of_match),
 	},
-	.probe		= arizona_i2c_probe,
+	.probe_new	= arizona_i2c_probe,
 	.remove		= arizona_i2c_remove,
 	.id_table	= arizona_i2c_id,
 };
-- 
GitLab


From 4a36fb26728dd4dced21a2806bb58618433e6415 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:33 +0100
Subject: [PATCH 182/875] mfd: as3711: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-420-uwe@kleine-koenig.org
---
 drivers/mfd/as3711.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/as3711.c b/drivers/mfd/as3711.c
index 3adaec6c37dfd..3facfdd28e81f 100644
--- a/drivers/mfd/as3711.c
+++ b/drivers/mfd/as3711.c
@@ -116,8 +116,7 @@ static const struct of_device_id as3711_of_match[] = {
 };
 #endif
 
-static int as3711_i2c_probe(struct i2c_client *client,
-			    const struct i2c_device_id *id)
+static int as3711_i2c_probe(struct i2c_client *client)
 {
 	struct as3711 *as3711;
 	struct as3711_platform_data *pdata;
@@ -202,7 +201,7 @@ static struct i2c_driver as3711_i2c_driver = {
 		   .name = "as3711",
 		   .of_match_table = of_match_ptr(as3711_of_match),
 	},
-	.probe = as3711_i2c_probe,
+	.probe_new = as3711_i2c_probe,
 	.id_table = as3711_i2c_id,
 };
 
-- 
GitLab


From 9b6e839353819841c0689997b0fb3a90cf44c59e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:34 +0100
Subject: [PATCH 183/875] mfd: as3722: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-421-uwe@kleine-koenig.org
---
 drivers/mfd/as3722.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/as3722.c b/drivers/mfd/as3722.c
index 38665efae4f00..b6dda0eb86456 100644
--- a/drivers/mfd/as3722.c
+++ b/drivers/mfd/as3722.c
@@ -333,8 +333,7 @@ static int as3722_i2c_of_probe(struct i2c_client *i2c,
 	return 0;
 }
 
-static int as3722_i2c_probe(struct i2c_client *i2c,
-			const struct i2c_device_id *id)
+static int as3722_i2c_probe(struct i2c_client *i2c)
 {
 	struct as3722 *as3722;
 	unsigned long irq_flags;
@@ -446,7 +445,7 @@ static struct i2c_driver as3722_i2c_driver = {
 		.of_match_table = as3722_of_match,
 		.pm = &as3722_pm_ops,
 	},
-	.probe = as3722_i2c_probe,
+	.probe_new = as3722_i2c_probe,
 	.id_table = as3722_i2c_id,
 };
 
-- 
GitLab


From 10206ff20678debb540a09ccacd86afd4956515d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:35 +0100
Subject: [PATCH 184/875] mfd: atc260x-i2c: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-422-uwe@kleine-koenig.org
---
 drivers/mfd/atc260x-i2c.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/atc260x-i2c.c b/drivers/mfd/atc260x-i2c.c
index 5855efd09efc4..19e248ed79665 100644
--- a/drivers/mfd/atc260x-i2c.c
+++ b/drivers/mfd/atc260x-i2c.c
@@ -12,8 +12,7 @@
 #include <linux/of.h>
 #include <linux/regmap.h>
 
-static int atc260x_i2c_probe(struct i2c_client *client,
-			     const struct i2c_device_id *id)
+static int atc260x_i2c_probe(struct i2c_client *client)
 {
 	struct atc260x *atc260x;
 	struct regmap_config regmap_cfg;
@@ -54,7 +53,7 @@ static struct i2c_driver atc260x_i2c_driver = {
 		.name = "atc260x",
 		.of_match_table	= of_match_ptr(atc260x_i2c_of_match),
 	},
-	.probe = atc260x_i2c_probe,
+	.probe_new = atc260x_i2c_probe,
 };
 module_i2c_driver(atc260x_i2c_driver);
 
-- 
GitLab


From 2f2455db6f5f1db82ffffd6d8bdb3beac8a0fe63 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:36 +0100
Subject: [PATCH 185/875] mfd: axp20x-i2c: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-423-uwe@kleine-koenig.org
---
 drivers/mfd/axp20x-i2c.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/axp20x-i2c.c b/drivers/mfd/axp20x-i2c.c
index 8fd6727dc30a1..f49fbd3079589 100644
--- a/drivers/mfd/axp20x-i2c.c
+++ b/drivers/mfd/axp20x-i2c.c
@@ -22,8 +22,7 @@
 #include <linux/regmap.h>
 #include <linux/slab.h>
 
-static int axp20x_i2c_probe(struct i2c_client *i2c,
-			    const struct i2c_device_id *id)
+static int axp20x_i2c_probe(struct i2c_client *i2c)
 {
 	struct axp20x_dev *axp20x;
 	int ret;
@@ -100,7 +99,7 @@ static struct i2c_driver axp20x_i2c_driver = {
 		.of_match_table	= of_match_ptr(axp20x_i2c_of_match),
 		.acpi_match_table = ACPI_PTR(axp20x_i2c_acpi_match),
 	},
-	.probe		= axp20x_i2c_probe,
+	.probe_new	= axp20x_i2c_probe,
 	.remove		= axp20x_i2c_remove,
 	.id_table	= axp20x_i2c_id,
 };
-- 
GitLab


From ace24876abf16f086bf19349d99baf0a8ef2e986 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:37 +0100
Subject: [PATCH 186/875] mfd: bcm590xx: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-424-uwe@kleine-koenig.org
---
 drivers/mfd/bcm590xx.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/bcm590xx.c b/drivers/mfd/bcm590xx.c
index 6ca337cde84c8..251d515478d55 100644
--- a/drivers/mfd/bcm590xx.c
+++ b/drivers/mfd/bcm590xx.c
@@ -38,8 +38,7 @@ static const struct regmap_config bcm590xx_regmap_config_sec = {
 	.cache_type	= REGCACHE_RBTREE,
 };
 
-static int bcm590xx_i2c_probe(struct i2c_client *i2c_pri,
-			      const struct i2c_device_id *id)
+static int bcm590xx_i2c_probe(struct i2c_client *i2c_pri)
 {
 	struct bcm590xx *bcm590xx;
 	int ret;
@@ -109,7 +108,7 @@ static struct i2c_driver bcm590xx_i2c_driver = {
 		   .name = "bcm590xx",
 		   .of_match_table = bcm590xx_of_match,
 	},
-	.probe = bcm590xx_i2c_probe,
+	.probe_new = bcm590xx_i2c_probe,
 	.id_table = bcm590xx_i2c_id,
 };
 module_i2c_driver(bcm590xx_i2c_driver);
-- 
GitLab


From 4c023a6ec3a8911f2935da55ca0512d94bb289ab Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:38 +0100
Subject: [PATCH 187/875] mfd: bd9571mwv: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-425-uwe@kleine-koenig.org
---
 drivers/mfd/bd9571mwv.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/bd9571mwv.c b/drivers/mfd/bd9571mwv.c
index e15b1acfb0630..60dc858c8117a 100644
--- a/drivers/mfd/bd9571mwv.c
+++ b/drivers/mfd/bd9571mwv.c
@@ -204,8 +204,7 @@ static int bd957x_identify(struct device *dev, struct regmap *regmap)
 	return 0;
 }
 
-static int bd9571mwv_probe(struct i2c_client *client,
-			   const struct i2c_device_id *ids)
+static int bd9571mwv_probe(struct i2c_client *client)
 {
 	const struct regmap_config *regmap_config;
 	const struct regmap_irq_chip *irq_chip;
@@ -279,7 +278,7 @@ static struct i2c_driver bd9571mwv_driver = {
 		.name	= "bd9571mwv",
 		.of_match_table = bd9571mwv_of_match_table,
 	},
-	.probe		= bd9571mwv_probe,
+	.probe_new	= bd9571mwv_probe,
 	.id_table       = bd9571mwv_id_table,
 };
 module_i2c_driver(bd9571mwv_driver);
-- 
GitLab


From 6887bb934cf3864e2ae0894fe58d299e03609752 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:39 +0100
Subject: [PATCH 188/875] mfd: da903x: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-426-uwe@kleine-koenig.org
---
 drivers/mfd/da903x.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/da903x.c b/drivers/mfd/da903x.c
index 3f8f6ad3a98c4..44a25d642ce94 100644
--- a/drivers/mfd/da903x.c
+++ b/drivers/mfd/da903x.c
@@ -488,9 +488,9 @@ failed:
 	return ret;
 }
 
-static int da903x_probe(struct i2c_client *client,
-				  const struct i2c_device_id *id)
+static int da903x_probe(struct i2c_client *client)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(client);
 	struct da903x_platform_data *pdata = dev_get_platdata(&client->dev);
 	struct da903x_chip *chip;
 	unsigned int tmp;
@@ -543,7 +543,7 @@ static struct i2c_driver da903x_driver = {
 	.driver	= {
 		.name	= "da903x",
 	},
-	.probe		= da903x_probe,
+	.probe_new	= da903x_probe,
 	.remove		= da903x_remove,
 	.id_table	= da903x_id_table,
 };
-- 
GitLab


From 1ebf79726a9a911247a0b8566c5be84d44a18fa0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:40 +0100
Subject: [PATCH 189/875] mfd: da9052-i2c: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-427-uwe@kleine-koenig.org
---
 drivers/mfd/da9052-i2c.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/da9052-i2c.c b/drivers/mfd/da9052-i2c.c
index 5a74696c8704f..ecb8077cdaaf9 100644
--- a/drivers/mfd/da9052-i2c.c
+++ b/drivers/mfd/da9052-i2c.c
@@ -126,9 +126,9 @@ static const struct of_device_id dialog_dt_ids[] = {
 };
 #endif
 
-static int da9052_i2c_probe(struct i2c_client *client,
-				       const struct i2c_device_id *id)
+static int da9052_i2c_probe(struct i2c_client *client)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(client);
 	struct da9052 *da9052;
 	int ret;
 
@@ -176,7 +176,7 @@ static void da9052_i2c_remove(struct i2c_client *client)
 }
 
 static struct i2c_driver da9052_i2c_driver = {
-	.probe = da9052_i2c_probe,
+	.probe_new = da9052_i2c_probe,
 	.remove = da9052_i2c_remove,
 	.id_table = da9052_i2c_id,
 	.driver = {
-- 
GitLab


From d429772913a9804e7440c13a135cc22957fee4f5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:41 +0100
Subject: [PATCH 190/875] mfd: da9055-i2c: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-428-uwe@kleine-koenig.org
---
 drivers/mfd/da9055-i2c.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/da9055-i2c.c b/drivers/mfd/da9055-i2c.c
index 276c7d1c509e0..702abff506a1a 100644
--- a/drivers/mfd/da9055-i2c.c
+++ b/drivers/mfd/da9055-i2c.c
@@ -15,8 +15,7 @@
 
 #include <linux/mfd/da9055/core.h>
 
-static int da9055_i2c_probe(struct i2c_client *i2c,
-				      const struct i2c_device_id *id)
+static int da9055_i2c_probe(struct i2c_client *i2c)
 {
 	struct da9055 *da9055;
 	int ret;
@@ -67,7 +66,7 @@ static const struct of_device_id da9055_of_match[] = {
 };
 
 static struct i2c_driver da9055_i2c_driver = {
-	.probe = da9055_i2c_probe,
+	.probe_new = da9055_i2c_probe,
 	.remove = da9055_i2c_remove,
 	.id_table = da9055_i2c_id,
 	.driver = {
-- 
GitLab


From 7df5c3d803f7aea56dce550a1151236d13d82d79 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:42 +0100
Subject: [PATCH 191/875] mfd: da9062-core: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-429-uwe@kleine-koenig.org
---
 drivers/mfd/da9062-core.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/da9062-core.c b/drivers/mfd/da9062-core.c
index a26e473507c71..40cde51e57198 100644
--- a/drivers/mfd/da9062-core.c
+++ b/drivers/mfd/da9062-core.c
@@ -621,9 +621,9 @@ static const struct of_device_id da9062_dt_ids[] = {
 };
 MODULE_DEVICE_TABLE(of, da9062_dt_ids);
 
-static int da9062_i2c_probe(struct i2c_client *i2c,
-	const struct i2c_device_id *id)
+static int da9062_i2c_probe(struct i2c_client *i2c)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
 	struct da9062 *chip;
 	unsigned int irq_base;
 	const struct mfd_cell *cell;
@@ -744,7 +744,7 @@ static struct i2c_driver da9062_i2c_driver = {
 		.name = "da9062",
 		.of_match_table = da9062_dt_ids,
 	},
-	.probe    = da9062_i2c_probe,
+	.probe_new = da9062_i2c_probe,
 	.remove   = da9062_i2c_remove,
 	.id_table = da9062_i2c_id,
 };
-- 
GitLab


From b309636b660639e8d1c758c042ca49726bef5aa7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:43 +0100
Subject: [PATCH 192/875] mfd: da9063-i2c: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-430-uwe@kleine-koenig.org
---
 drivers/mfd/da9063-i2c.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/da9063-i2c.c b/drivers/mfd/da9063-i2c.c
index 343ed6e96d87e..03f8f95a1d62c 100644
--- a/drivers/mfd/da9063-i2c.c
+++ b/drivers/mfd/da9063-i2c.c
@@ -351,9 +351,9 @@ static const struct of_device_id da9063_dt_ids[] = {
 	{ }
 };
 MODULE_DEVICE_TABLE(of, da9063_dt_ids);
-static int da9063_i2c_probe(struct i2c_client *i2c,
-			    const struct i2c_device_id *id)
+static int da9063_i2c_probe(struct i2c_client *i2c)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
 	struct da9063 *da9063;
 	int ret;
 
@@ -469,7 +469,7 @@ static struct i2c_driver da9063_i2c_driver = {
 		.name = "da9063",
 		.of_match_table = da9063_dt_ids,
 	},
-	.probe    = da9063_i2c_probe,
+	.probe_new = da9063_i2c_probe,
 	.id_table = da9063_i2c_id,
 };
 
-- 
GitLab


From 3dc6eb9fa1c69b5218be571832f76ee7472c355e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:44 +0100
Subject: [PATCH 193/875] mfd: da9150-core: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-431-uwe@kleine-koenig.org
---
 drivers/mfd/da9150-core.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/da9150-core.c b/drivers/mfd/da9150-core.c
index 6ae56e46d24e6..d2c954103b2f5 100644
--- a/drivers/mfd/da9150-core.c
+++ b/drivers/mfd/da9150-core.c
@@ -392,8 +392,7 @@ static struct mfd_cell da9150_devs[] = {
 	},
 };
 
-static int da9150_probe(struct i2c_client *client,
-			const struct i2c_device_id *id)
+static int da9150_probe(struct i2c_client *client)
 {
 	struct da9150 *da9150;
 	struct da9150_pdata *pdata = dev_get_platdata(&client->dev);
@@ -511,7 +510,7 @@ static struct i2c_driver da9150_driver = {
 		.name	= "da9150",
 		.of_match_table = da9150_of_match,
 	},
-	.probe		= da9150_probe,
+	.probe_new	= da9150_probe,
 	.remove		= da9150_remove,
 	.shutdown	= da9150_shutdown,
 	.id_table	= da9150_i2c_id,
-- 
GitLab


From c88e02da2970804992462983fdde30289123bb3e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:45 +0100
Subject: [PATCH 194/875] mfd: khadas-mcu: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-432-uwe@kleine-koenig.org
---
 drivers/mfd/khadas-mcu.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/khadas-mcu.c b/drivers/mfd/khadas-mcu.c
index f3d418810693c..7338cc16f3271 100644
--- a/drivers/mfd/khadas-mcu.c
+++ b/drivers/mfd/khadas-mcu.c
@@ -84,8 +84,7 @@ static struct mfd_cell khadas_mcu_cells[] = {
 	{ .name = "khadas-mcu-user-mem", },
 };
 
-static int khadas_mcu_probe(struct i2c_client *client,
-		       const struct i2c_device_id *id)
+static int khadas_mcu_probe(struct i2c_client *client)
 {
 	struct device *dev = &client->dev;
 	struct khadas_mcu *ddata;
@@ -135,7 +134,7 @@ static struct i2c_driver khadas_mcu_driver = {
 		.name = "khadas-mcu-core",
 		.of_match_table = of_match_ptr(khadas_mcu_of_match),
 	},
-	.probe = khadas_mcu_probe,
+	.probe_new = khadas_mcu_probe,
 };
 module_i2c_driver(khadas_mcu_driver);
 
-- 
GitLab


From daf811fc4873af4a1facbe919526880b72c42a54 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:46 +0100
Subject: [PATCH 195/875] mfd: lm3533-core: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-433-uwe@kleine-koenig.org
---
 drivers/mfd/lm3533-core.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/lm3533-core.c b/drivers/mfd/lm3533-core.c
index be32ffc5af384..74a5533294160 100644
--- a/drivers/mfd/lm3533-core.c
+++ b/drivers/mfd/lm3533-core.c
@@ -584,8 +584,7 @@ static const struct regmap_config regmap_config = {
 	.precious_reg	= lm3533_precious_register,
 };
 
-static int lm3533_i2c_probe(struct i2c_client *i2c,
-					const struct i2c_device_id *id)
+static int lm3533_i2c_probe(struct i2c_client *i2c)
 {
 	struct lm3533 *lm3533;
 
@@ -627,7 +626,7 @@ static struct i2c_driver lm3533_i2c_driver = {
 		   .name = "lm3533",
 	},
 	.id_table	= lm3533_i2c_ids,
-	.probe		= lm3533_i2c_probe,
+	.probe_new	= lm3533_i2c_probe,
 	.remove		= lm3533_i2c_remove,
 };
 
-- 
GitLab


From f7b497cb3e14b7d61caf47e8ba7cdc0eb8fde0a4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:47 +0100
Subject: [PATCH 196/875] mfd: lp3943: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-434-uwe@kleine-koenig.org
---
 drivers/mfd/lp3943.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mfd/lp3943.c b/drivers/mfd/lp3943.c
index 13cb89be3d661..f9f39b53d0300 100644
--- a/drivers/mfd/lp3943.c
+++ b/drivers/mfd/lp3943.c
@@ -102,7 +102,7 @@ static const struct regmap_config lp3943_regmap_config = {
 	.max_register = LP3943_MAX_REGISTERS,
 };
 
-static int lp3943_probe(struct i2c_client *cl, const struct i2c_device_id *id)
+static int lp3943_probe(struct i2c_client *cl)
 {
 	struct lp3943 *lp3943;
 	struct device *dev = &cl->dev;
@@ -140,7 +140,7 @@ MODULE_DEVICE_TABLE(of, lp3943_of_match);
 #endif
 
 static struct i2c_driver lp3943_driver = {
-	.probe = lp3943_probe,
+	.probe_new = lp3943_probe,
 	.driver = {
 		.name = "lp3943",
 		.of_match_table = of_match_ptr(lp3943_of_match),
-- 
GitLab


From 4acb5992aa3dcf22ed16923d92e0053a73e1a9f4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:48 +0100
Subject: [PATCH 197/875] mfd: lp873x: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-435-uwe@kleine-koenig.org
---
 drivers/mfd/lp873x.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/lp873x.c b/drivers/mfd/lp873x.c
index b6166dec492d4..c81c5c9ad7489 100644
--- a/drivers/mfd/lp873x.c
+++ b/drivers/mfd/lp873x.c
@@ -24,8 +24,7 @@ static const struct mfd_cell lp873x_cells[] = {
 	{ .name = "lp873x-gpio", },
 };
 
-static int lp873x_probe(struct i2c_client *client,
-			const struct i2c_device_id *ids)
+static int lp873x_probe(struct i2c_client *client)
 {
 	struct lp873x *lp873;
 	int ret;
@@ -79,7 +78,7 @@ static struct i2c_driver lp873x_driver = {
 		.name	= "lp873x",
 		.of_match_table = of_lp873x_match_table,
 	},
-	.probe		= lp873x_probe,
+	.probe_new	= lp873x_probe,
 	.id_table	= lp873x_id_table,
 };
 module_i2c_driver(lp873x_driver);
-- 
GitLab


From 7ec69cc2aa0c6210f4617ec67ce438e3e429cf9c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:49 +0100
Subject: [PATCH 198/875] mfd: lp87565: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-436-uwe@kleine-koenig.org
---
 drivers/mfd/lp87565.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/lp87565.c b/drivers/mfd/lp87565.c
index a52ab76febb34..568f0f01ea0d2 100644
--- a/drivers/mfd/lp87565.c
+++ b/drivers/mfd/lp87565.c
@@ -43,8 +43,7 @@ static const struct of_device_id of_lp87565_match_table[] = {
 };
 MODULE_DEVICE_TABLE(of, of_lp87565_match_table);
 
-static int lp87565_probe(struct i2c_client *client,
-			 const struct i2c_device_id *ids)
+static int lp87565_probe(struct i2c_client *client)
 {
 	struct lp87565 *lp87565;
 	const struct of_device_id *of_id;
@@ -120,7 +119,7 @@ static struct i2c_driver lp87565_driver = {
 		.name	= "lp87565",
 		.of_match_table = of_lp87565_match_table,
 	},
-	.probe = lp87565_probe,
+	.probe_new = lp87565_probe,
 	.shutdown = lp87565_shutdown,
 	.id_table = lp87565_id_table,
 };
-- 
GitLab


From 2034ef7458083eb92ce3f563cca883772118d8e2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:50 +0100
Subject: [PATCH 199/875] mfd: lp8788: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-437-uwe@kleine-koenig.org
---
 drivers/mfd/lp8788.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mfd/lp8788.c b/drivers/mfd/lp8788.c
index 724a5712b36ba..fe809b64147e6 100644
--- a/drivers/mfd/lp8788.c
+++ b/drivers/mfd/lp8788.c
@@ -166,7 +166,7 @@ static const struct regmap_config lp8788_regmap_config = {
 	.max_register = MAX_LP8788_REGISTERS,
 };
 
-static int lp8788_probe(struct i2c_client *cl, const struct i2c_device_id *id)
+static int lp8788_probe(struct i2c_client *cl)
 {
 	struct lp8788 *lp;
 	struct lp8788_platform_data *pdata = dev_get_platdata(&cl->dev);
@@ -225,7 +225,7 @@ static struct i2c_driver lp8788_driver = {
 	.driver = {
 		.name = "lp8788",
 	},
-	.probe = lp8788_probe,
+	.probe_new = lp8788_probe,
 	.remove = lp8788_remove,
 	.id_table = lp8788_ids,
 };
-- 
GitLab


From 806b9167d4175787651b497892213fe7974e9ee0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:51 +0100
Subject: [PATCH 200/875] mfd: madera-i2c: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-438-uwe@kleine-koenig.org
---
 drivers/mfd/madera-i2c.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/madera-i2c.c b/drivers/mfd/madera-i2c.c
index 915d2f95bad31..47e65d88feb0e 100644
--- a/drivers/mfd/madera-i2c.c
+++ b/drivers/mfd/madera-i2c.c
@@ -17,9 +17,9 @@
 
 #include "madera.h"
 
-static int madera_i2c_probe(struct i2c_client *i2c,
-			    const struct i2c_device_id *id)
+static int madera_i2c_probe(struct i2c_client *i2c)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
 	struct madera *madera;
 	const struct regmap_config *regmap_16bit_config = NULL;
 	const struct regmap_config *regmap_32bit_config = NULL;
@@ -139,7 +139,7 @@ static struct i2c_driver madera_i2c_driver = {
 		.pm	= &madera_pm_ops,
 		.of_match_table	= of_match_ptr(madera_of_match),
 	},
-	.probe		= madera_i2c_probe,
+	.probe_new	= madera_i2c_probe,
 	.remove		= madera_i2c_remove,
 	.id_table	= madera_i2c_id,
 };
-- 
GitLab


From 8df214715d056e88ae428f0312c49ecf46d93331 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:52 +0100
Subject: [PATCH 201/875] mfd: max14577: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-439-uwe@kleine-koenig.org
---
 drivers/mfd/max14577.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/max14577.c b/drivers/mfd/max14577.c
index d44ad6f337425..11211039ed901 100644
--- a/drivers/mfd/max14577.c
+++ b/drivers/mfd/max14577.c
@@ -358,9 +358,9 @@ static void max77836_remove(struct max14577 *max14577)
 	i2c_unregister_device(max14577->i2c_pmic);
 }
 
-static int max14577_i2c_probe(struct i2c_client *i2c,
-			      const struct i2c_device_id *id)
+static int max14577_i2c_probe(struct i2c_client *i2c)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
 	struct max14577 *max14577;
 	struct max14577_platform_data *pdata = dev_get_platdata(&i2c->dev);
 	struct device_node *np = i2c->dev.of_node;
@@ -523,7 +523,7 @@ static struct i2c_driver max14577_i2c_driver = {
 		.pm = &max14577_pm,
 		.of_match_table = max14577_dt_match,
 	},
-	.probe = max14577_i2c_probe,
+	.probe_new = max14577_i2c_probe,
 	.remove = max14577_i2c_remove,
 	.id_table = max14577_i2c_id,
 };
-- 
GitLab


From 773fb98fec5f7ae42254836391dd149e49427d9a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:53 +0100
Subject: [PATCH 202/875] mfd: max77620: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-440-uwe@kleine-koenig.org
---
 drivers/mfd/max77620.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/max77620.c b/drivers/mfd/max77620.c
index a6661e07035ba..0b1e9340210b5 100644
--- a/drivers/mfd/max77620.c
+++ b/drivers/mfd/max77620.c
@@ -494,9 +494,9 @@ static void max77620_pm_power_off(void)
 			   MAX77620_ONOFFCNFG1_SFT_RST);
 }
 
-static int max77620_probe(struct i2c_client *client,
-			  const struct i2c_device_id *id)
+static int max77620_probe(struct i2c_client *client)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(client);
 	const struct regmap_config *rmap_config;
 	struct max77620_chip *chip;
 	const struct mfd_cell *mfd_cells;
@@ -701,7 +701,7 @@ static struct i2c_driver max77620_driver = {
 		.name = "max77620",
 		.pm = &max77620_pm_ops,
 	},
-	.probe = max77620_probe,
+	.probe_new = max77620_probe,
 	.id_table = max77620_id,
 };
 builtin_i2c_driver(max77620_driver);
-- 
GitLab


From 317018e57b4eae64a304877f3aad32163ed58ea3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:54 +0100
Subject: [PATCH 203/875] mfd: max77693: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-441-uwe@kleine-koenig.org
---
 drivers/mfd/max77693.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/max77693.c b/drivers/mfd/max77693.c
index 7088cb6f91745..aa32e89b6c8e5 100644
--- a/drivers/mfd/max77693.c
+++ b/drivers/mfd/max77693.c
@@ -149,9 +149,9 @@ static const struct regmap_config max77693_regmap_haptic_config = {
 	.max_register = MAX77693_HAPTIC_REG_END,
 };
 
-static int max77693_i2c_probe(struct i2c_client *i2c,
-			      const struct i2c_device_id *id)
+static int max77693_i2c_probe(struct i2c_client *i2c)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
 	struct max77693_dev *max77693;
 	unsigned int reg_data;
 	int ret = 0;
@@ -360,7 +360,7 @@ static struct i2c_driver max77693_i2c_driver = {
 		   .pm = &max77693_pm,
 		   .of_match_table = of_match_ptr(max77693_dt_match),
 	},
-	.probe = max77693_i2c_probe,
+	.probe_new = max77693_i2c_probe,
 	.remove = max77693_i2c_remove,
 	.id_table = max77693_i2c_id,
 };
-- 
GitLab


From 13c6de605f1ec5617ca085a9044a244bb8f4b9b7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:55 +0100
Subject: [PATCH 204/875] mfd: max77843: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-442-uwe@kleine-koenig.org
---
 drivers/mfd/max77843.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/max77843.c b/drivers/mfd/max77843.c
index 209ee24d9ce1c..c6fd93efd5c4e 100644
--- a/drivers/mfd/max77843.c
+++ b/drivers/mfd/max77843.c
@@ -93,9 +93,9 @@ err_chg_i2c:
 	return ret;
 }
 
-static int max77843_probe(struct i2c_client *i2c,
-			  const struct i2c_device_id *id)
+static int max77843_probe(struct i2c_client *i2c)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
 	struct max77693_dev *max77843;
 	unsigned int reg_data;
 	int ret;
@@ -208,7 +208,7 @@ static struct i2c_driver max77843_i2c_driver = {
 		.of_match_table = max77843_dt_match,
 		.suppress_bind_attrs = true,
 	},
-	.probe = max77843_probe,
+	.probe_new = max77843_probe,
 	.id_table = max77843_id,
 };
 
-- 
GitLab


From bab90bb26256c31633897867d124164d22ce5de9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:56 +0100
Subject: [PATCH 205/875] mfd: max8907: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-443-uwe@kleine-koenig.org
---
 drivers/mfd/max8907.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/max8907.c b/drivers/mfd/max8907.c
index c340080971cef..a69b865c6eacf 100644
--- a/drivers/mfd/max8907.c
+++ b/drivers/mfd/max8907.c
@@ -181,8 +181,7 @@ static void max8907_power_off(void)
 			MAX8907_MASK_POWER_OFF, MAX8907_MASK_POWER_OFF);
 }
 
-static int max8907_i2c_probe(struct i2c_client *i2c,
-				       const struct i2c_device_id *id)
+static int max8907_i2c_probe(struct i2c_client *i2c)
 {
 	struct max8907 *max8907;
 	int ret;
@@ -314,7 +313,7 @@ static struct i2c_driver max8907_i2c_driver = {
 		.name = "max8907",
 		.of_match_table = of_match_ptr(max8907_of_match),
 	},
-	.probe = max8907_i2c_probe,
+	.probe_new = max8907_i2c_probe,
 	.remove = max8907_i2c_remove,
 	.id_table = max8907_i2c_id,
 };
-- 
GitLab


From 18d9f1217e42d50372ef40be07a37e7748f940f0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:57 +0100
Subject: [PATCH 206/875] mfd: max8925-i2c: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-444-uwe@kleine-koenig.org
---
 drivers/mfd/max8925-i2c.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/max8925-i2c.c b/drivers/mfd/max8925-i2c.c
index 04101da42bd31..7c3ec167f9417 100644
--- a/drivers/mfd/max8925-i2c.c
+++ b/drivers/mfd/max8925-i2c.c
@@ -144,8 +144,7 @@ static int max8925_dt_init(struct device_node *np, struct device *dev,
 	return 0;
 }
 
-static int max8925_probe(struct i2c_client *client,
-				   const struct i2c_device_id *id)
+static int max8925_probe(struct i2c_client *client)
 {
 	struct max8925_platform_data *pdata = dev_get_platdata(&client->dev);
 	struct max8925_chip *chip;
@@ -242,7 +241,7 @@ static struct i2c_driver max8925_driver = {
 		.pm     = &max8925_pm_ops,
 		.of_match_table = max8925_dt_ids,
 	},
-	.probe		= max8925_probe,
+	.probe_new	= max8925_probe,
 	.remove		= max8925_remove,
 	.id_table	= max8925_id_table,
 };
-- 
GitLab


From c9f105ec976a7f038d99e2745508cdceec44353c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:58 +0100
Subject: [PATCH 207/875] mfd: max8997: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-445-uwe@kleine-koenig.org
---
 drivers/mfd/max8997.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/max8997.c b/drivers/mfd/max8997.c
index 2141de78115d9..79d551b86150f 100644
--- a/drivers/mfd/max8997.c
+++ b/drivers/mfd/max8997.c
@@ -152,9 +152,9 @@ static inline unsigned long max8997_i2c_get_driver_data(struct i2c_client *i2c,
 	return id->driver_data;
 }
 
-static int max8997_i2c_probe(struct i2c_client *i2c,
-			    const struct i2c_device_id *id)
+static int max8997_i2c_probe(struct i2c_client *i2c)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
 	struct max8997_dev *max8997;
 	struct max8997_platform_data *pdata = dev_get_platdata(&i2c->dev);
 	int ret = 0;
@@ -478,7 +478,7 @@ static struct i2c_driver max8997_i2c_driver = {
 		   .suppress_bind_attrs = true,
 		   .of_match_table = of_match_ptr(max8997_pmic_dt_match),
 	},
-	.probe = max8997_i2c_probe,
+	.probe_new = max8997_i2c_probe,
 	.id_table = max8997_i2c_id,
 };
 
-- 
GitLab


From 833eaaf700ae94a15ced1a67392564eca03e5fcf Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:42:59 +0100
Subject: [PATCH 208/875] mfd: max8998: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-446-uwe@kleine-koenig.org
---
 drivers/mfd/max8998.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/max8998.c b/drivers/mfd/max8998.c
index 0eb15e611b671..122f7b931f5a2 100644
--- a/drivers/mfd/max8998.c
+++ b/drivers/mfd/max8998.c
@@ -162,9 +162,9 @@ static inline unsigned long max8998_i2c_get_driver_data(struct i2c_client *i2c,
 	return id->driver_data;
 }
 
-static int max8998_i2c_probe(struct i2c_client *i2c,
-			    const struct i2c_device_id *id)
+static int max8998_i2c_probe(struct i2c_client *i2c)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
 	struct max8998_platform_data *pdata = dev_get_platdata(&i2c->dev);
 	struct max8998_dev *max8998;
 	int ret = 0;
@@ -348,7 +348,7 @@ static struct i2c_driver max8998_i2c_driver = {
 		   .suppress_bind_attrs = true,
 		   .of_match_table = of_match_ptr(max8998_dt_match),
 	},
-	.probe = max8998_i2c_probe,
+	.probe_new = max8998_i2c_probe,
 	.id_table = max8998_i2c_id,
 };
 
-- 
GitLab


From 1060552913f13b58db02078bdfef657c1badfc6e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:00 +0100
Subject: [PATCH 209/875] mfd: mc13xxx-i2c: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-447-uwe@kleine-koenig.org
---
 drivers/mfd/mc13xxx-i2c.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/mc13xxx-i2c.c b/drivers/mfd/mc13xxx-i2c.c
index eb94f3004cf33..9593e2be23ed5 100644
--- a/drivers/mfd/mc13xxx-i2c.c
+++ b/drivers/mfd/mc13xxx-i2c.c
@@ -52,9 +52,9 @@ static const struct regmap_config mc13xxx_regmap_i2c_config = {
 	.cache_type = REGCACHE_NONE,
 };
 
-static int mc13xxx_i2c_probe(struct i2c_client *client,
-		const struct i2c_device_id *id)
+static int mc13xxx_i2c_probe(struct i2c_client *client)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(client);
 	struct mc13xxx *mc13xxx;
 	int ret;
 
@@ -96,7 +96,7 @@ static struct i2c_driver mc13xxx_i2c_driver = {
 		.name = "mc13xxx",
 		.of_match_table = mc13xxx_dt_ids,
 	},
-	.probe = mc13xxx_i2c_probe,
+	.probe_new = mc13xxx_i2c_probe,
 	.remove = mc13xxx_i2c_remove,
 };
 
-- 
GitLab


From 19301f114ba83b248f37f27131c9511b767d737b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:01 +0100
Subject: [PATCH 210/875] mfd: menelaus: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-448-uwe@kleine-koenig.org
---
 drivers/mfd/menelaus.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/menelaus.c b/drivers/mfd/menelaus.c
index eb08f69001f91..c2866a11c1d22 100644
--- a/drivers/mfd/menelaus.c
+++ b/drivers/mfd/menelaus.c
@@ -1142,8 +1142,7 @@ static inline void menelaus_rtc_init(struct menelaus_chip *m)
 
 static struct i2c_driver menelaus_i2c_driver;
 
-static int menelaus_probe(struct i2c_client *client,
-			  const struct i2c_device_id *id)
+static int menelaus_probe(struct i2c_client *client)
 {
 	struct menelaus_chip	*menelaus;
 	int			rev = 0;
@@ -1241,7 +1240,7 @@ static struct i2c_driver menelaus_i2c_driver = {
 	.driver = {
 		.name		= DRIVER_NAME,
 	},
-	.probe		= menelaus_probe,
+	.probe_new	= menelaus_probe,
 	.remove		= menelaus_remove,
 	.id_table	= menelaus_id,
 };
-- 
GitLab


From a5a689fa14558e1e7d7a57303539ed8c2bc37c3f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:02 +0100
Subject: [PATCH 211/875] mfd: menf21bmc: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-449-uwe@kleine-koenig.org
---
 drivers/mfd/menf21bmc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mfd/menf21bmc.c b/drivers/mfd/menf21bmc.c
index 8f72b1cccbe54..9092fac46e359 100644
--- a/drivers/mfd/menf21bmc.c
+++ b/drivers/mfd/menf21bmc.c
@@ -49,7 +49,7 @@ static int menf21bmc_wdt_exit_prod_mode(struct i2c_client *client)
 }
 
 static int
-menf21bmc_probe(struct i2c_client *client, const struct i2c_device_id *ids)
+menf21bmc_probe(struct i2c_client *client)
 {
 	int rev_major, rev_minor, rev_main;
 	int ret;
@@ -111,7 +111,7 @@ MODULE_DEVICE_TABLE(i2c, menf21bmc_id_table);
 static struct i2c_driver menf21bmc_driver = {
 	.driver.name	= "menf21bmc",
 	.id_table	= menf21bmc_id_table,
-	.probe		= menf21bmc_probe,
+	.probe_new	= menf21bmc_probe,
 };
 
 module_i2c_driver(menf21bmc_driver);
-- 
GitLab


From a5d6cbcfc7aec61df571972b5e7b93ec117de01c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:03 +0100
Subject: [PATCH 212/875] mfd: palmas: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-450-uwe@kleine-koenig.org
---
 drivers/mfd/palmas.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/palmas.c b/drivers/mfd/palmas.c
index 8b7429bd2e3eb..d26d82c85ba8e 100644
--- a/drivers/mfd/palmas.c
+++ b/drivers/mfd/palmas.c
@@ -502,8 +502,7 @@ static const struct of_device_id of_palmas_match_tbl[] = {
 };
 MODULE_DEVICE_TABLE(of, of_palmas_match_tbl);
 
-static int palmas_i2c_probe(struct i2c_client *i2c,
-			    const struct i2c_device_id *id)
+static int palmas_i2c_probe(struct i2c_client *i2c)
 {
 	struct palmas *palmas;
 	struct palmas_platform_data *pdata;
@@ -732,7 +731,7 @@ static struct i2c_driver palmas_i2c_driver = {
 		   .name = "palmas",
 		   .of_match_table = of_palmas_match_tbl,
 	},
-	.probe = palmas_i2c_probe,
+	.probe_new = palmas_i2c_probe,
 	.remove = palmas_i2c_remove,
 	.id_table = palmas_i2c_id,
 };
-- 
GitLab


From 659ea732119d556de500ace6de69a29c021c2ff1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:04 +0100
Subject: [PATCH 213/875] mfd: pcf50633-core: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-451-uwe@kleine-koenig.org
---
 drivers/mfd/pcf50633-core.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/pcf50633-core.c b/drivers/mfd/pcf50633-core.c
index 4ccc2c3e7681d..da39a7940560b 100644
--- a/drivers/mfd/pcf50633-core.c
+++ b/drivers/mfd/pcf50633-core.c
@@ -183,8 +183,7 @@ static const struct regmap_config pcf50633_regmap_config = {
 	.val_bits = 8,
 };
 
-static int pcf50633_probe(struct i2c_client *client,
-				const struct i2c_device_id *ids)
+static int pcf50633_probe(struct i2c_client *client)
 {
 	struct pcf50633 *pcf;
 	struct platform_device *pdev;
@@ -303,7 +302,7 @@ static struct i2c_driver pcf50633_driver = {
 		.pm	= &pcf50633_pm,
 	},
 	.id_table = pcf50633_id_table,
-	.probe = pcf50633_probe,
+	.probe_new = pcf50633_probe,
 	.remove = pcf50633_remove,
 };
 
-- 
GitLab


From 913c4a3e1988f042e9f817288092c0a0bc4214bd Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:05 +0100
Subject: [PATCH 214/875] mfd: rc5t583: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-452-uwe@kleine-koenig.org
---
 drivers/mfd/rc5t583.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/rc5t583.c b/drivers/mfd/rc5t583.c
index d0dc48f990967..df83cc3993151 100644
--- a/drivers/mfd/rc5t583.c
+++ b/drivers/mfd/rc5t583.c
@@ -233,8 +233,7 @@ static const struct regmap_config rc5t583_regmap_config = {
 	.cache_type = REGCACHE_RBTREE,
 };
 
-static int rc5t583_i2c_probe(struct i2c_client *i2c,
-			      const struct i2c_device_id *id)
+static int rc5t583_i2c_probe(struct i2c_client *i2c)
 {
 	struct rc5t583 *rc5t583;
 	struct rc5t583_platform_data *pdata = dev_get_platdata(&i2c->dev);
@@ -289,7 +288,7 @@ static struct i2c_driver rc5t583_i2c_driver = {
 	.driver = {
 		   .name = "rc5t583",
 		   },
-	.probe = rc5t583_i2c_probe,
+	.probe_new = rc5t583_i2c_probe,
 	.id_table = rc5t583_i2c_id,
 };
 
-- 
GitLab


From faa424fc01455557702d2d29602625a88996ce1d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:06 +0100
Subject: [PATCH 215/875] mfd: retu-mfd: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-453-uwe@kleine-koenig.org
---
 drivers/mfd/retu-mfd.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mfd/retu-mfd.c b/drivers/mfd/retu-mfd.c
index 3b5acf7ca39cb..d71483859e2ef 100644
--- a/drivers/mfd/retu-mfd.c
+++ b/drivers/mfd/retu-mfd.c
@@ -227,7 +227,7 @@ static const struct regmap_config retu_config = {
 	.val_bits = 16,
 };
 
-static int retu_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+static int retu_probe(struct i2c_client *i2c)
 {
 	struct retu_data const *rdat;
 	struct retu_dev *rdev;
@@ -318,7 +318,7 @@ static struct i2c_driver retu_driver = {
 		.name = "retu-mfd",
 		.of_match_table = retu_of_match,
 	},
-	.probe		= retu_probe,
+	.probe_new	= retu_probe,
 	.remove		= retu_remove,
 	.id_table	= retu_id,
 };
-- 
GitLab


From 8416360935b9b632a517503eac6e320cbd5f310a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:07 +0100
Subject: [PATCH 216/875] mfd: rk808: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-454-uwe@kleine-koenig.org
---
 drivers/mfd/rk808.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/rk808.c b/drivers/mfd/rk808.c
index e00da7c7e3b11..b390bba542e66 100644
--- a/drivers/mfd/rk808.c
+++ b/drivers/mfd/rk808.c
@@ -640,8 +640,7 @@ static const struct of_device_id rk808_of_match[] = {
 };
 MODULE_DEVICE_TABLE(of, rk808_of_match);
 
-static int rk808_probe(struct i2c_client *client,
-		       const struct i2c_device_id *id)
+static int rk808_probe(struct i2c_client *client)
 {
 	struct device_node *np = client->dev.of_node;
 	struct rk808 *rk808;
@@ -861,7 +860,7 @@ static struct i2c_driver rk808_i2c_driver = {
 		.of_match_table = rk808_of_match,
 		.pm = &rk8xx_pm_ops,
 	},
-	.probe    = rk808_probe,
+	.probe_new = rk808_probe,
 	.remove   = rk808_remove,
 	.shutdown = rk8xx_shutdown,
 };
-- 
GitLab


From 6816c54bdd95e8c35103b88bef3c75e699ff587b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:08 +0100
Subject: [PATCH 217/875] mfd: rohm-bd718x7: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Matti Vaittinen <mazziesaccount@gmail.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-455-uwe@kleine-koenig.org
---
 drivers/mfd/rohm-bd718x7.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/rohm-bd718x7.c b/drivers/mfd/rohm-bd718x7.c
index bfd81f78beaee..3c766cb15a24f 100644
--- a/drivers/mfd/rohm-bd718x7.c
+++ b/drivers/mfd/rohm-bd718x7.c
@@ -127,8 +127,7 @@ static int bd718xx_init_press_duration(struct regmap *regmap,
 	return 0;
 }
 
-static int bd718xx_i2c_probe(struct i2c_client *i2c,
-			    const struct i2c_device_id *id)
+static int bd718xx_i2c_probe(struct i2c_client *i2c)
 {
 	struct regmap *regmap;
 	struct regmap_irq_chip_data *irq_data;
@@ -215,7 +214,7 @@ static struct i2c_driver bd718xx_i2c_driver = {
 		.name = "rohm-bd718x7",
 		.of_match_table = bd718xx_of_match,
 	},
-	.probe = bd718xx_i2c_probe,
+	.probe_new = bd718xx_i2c_probe,
 };
 
 static int __init bd718xx_i2c_init(void)
-- 
GitLab


From 601e6d48ee3519648679177a0647dd3b3cbaefbb Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:09 +0100
Subject: [PATCH 218/875] mfd: rsmu_i2c: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-456-uwe@kleine-koenig.org
---
 drivers/mfd/rsmu_i2c.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/rsmu_i2c.c b/drivers/mfd/rsmu_i2c.c
index f716ab8039a06..15d25b0814346 100644
--- a/drivers/mfd/rsmu_i2c.c
+++ b/drivers/mfd/rsmu_i2c.c
@@ -106,9 +106,9 @@ static const struct regmap_config rsmu_sl_regmap_config = {
 	.can_multi_write = true,
 };
 
-static int rsmu_i2c_probe(struct i2c_client *client,
-			  const struct i2c_device_id *id)
+static int rsmu_i2c_probe(struct i2c_client *client)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(client);
 	const struct regmap_config *cfg;
 	struct rsmu_ddata *rsmu;
 	int ret;
@@ -180,7 +180,7 @@ static struct i2c_driver rsmu_i2c_driver = {
 		.name = "rsmu-i2c",
 		.of_match_table = of_match_ptr(rsmu_i2c_of_match),
 	},
-	.probe = rsmu_i2c_probe,
+	.probe_new = rsmu_i2c_probe,
 	.remove	= rsmu_i2c_remove,
 	.id_table = rsmu_i2c_id,
 };
-- 
GitLab


From e46b578cabb0365e8a91fba766d39d20153b82ce Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:10 +0100
Subject: [PATCH 219/875] mfd: rt5033: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-457-uwe@kleine-koenig.org
---
 drivers/mfd/rt5033.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/rt5033.c b/drivers/mfd/rt5033.c
index f1236a9acf304..8bcf1c01348ce 100644
--- a/drivers/mfd/rt5033.c
+++ b/drivers/mfd/rt5033.c
@@ -56,8 +56,7 @@ static const struct regmap_config rt5033_regmap_config = {
 	.max_register	= RT5033_REG_END,
 };
 
-static int rt5033_i2c_probe(struct i2c_client *i2c,
-				const struct i2c_device_id *id)
+static int rt5033_i2c_probe(struct i2c_client *i2c)
 {
 	struct rt5033_dev *rt5033;
 	unsigned int dev_id;
@@ -124,7 +123,7 @@ static struct i2c_driver rt5033_driver = {
 		.name = "rt5033",
 		.of_match_table = rt5033_dt_match,
 	},
-	.probe = rt5033_i2c_probe,
+	.probe_new = rt5033_i2c_probe,
 	.id_table = rt5033_i2c_id,
 };
 module_i2c_driver(rt5033_driver);
-- 
GitLab


From a403e589705fa4b93732581450c5c05833105ae3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:11 +0100
Subject: [PATCH 220/875] mfd: sec-core: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-458-uwe@kleine-koenig.org
---
 drivers/mfd/sec-core.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/sec-core.c b/drivers/mfd/sec-core.c
index 1fb29c45f5cf4..6bf117b7193ad 100644
--- a/drivers/mfd/sec-core.c
+++ b/drivers/mfd/sec-core.c
@@ -305,8 +305,7 @@ sec_pmic_i2c_parse_dt_pdata(struct device *dev)
 	return pd;
 }
 
-static int sec_pmic_probe(struct i2c_client *i2c,
-			    const struct i2c_device_id *id)
+static int sec_pmic_probe(struct i2c_client *i2c)
 {
 	const struct regmap_config *regmap;
 	struct sec_platform_data *pdata;
@@ -498,7 +497,7 @@ static struct i2c_driver sec_pmic_driver = {
 		   .pm = &sec_pmic_pm_ops,
 		   .of_match_table = sec_dt_match,
 	},
-	.probe = sec_pmic_probe,
+	.probe_new = sec_pmic_probe,
 	.shutdown = sec_pmic_shutdown,
 };
 module_i2c_driver(sec_pmic_driver);
-- 
GitLab


From ca08a4f30be612a2fa725f84c2f9b2dd8f54efee Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:12 +0100
Subject: [PATCH 221/875] mfd: si476x-i2c: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-459-uwe@kleine-koenig.org
---
 drivers/mfd/si476x-i2c.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/si476x-i2c.c b/drivers/mfd/si476x-i2c.c
index 8166949b725cc..22131cf85e3f9 100644
--- a/drivers/mfd/si476x-i2c.c
+++ b/drivers/mfd/si476x-i2c.c
@@ -683,9 +683,9 @@ bool si476x_core_is_powered_up(struct si476x_core *core)
 }
 EXPORT_SYMBOL_GPL(si476x_core_is_powered_up);
 
-static int si476x_core_probe(struct i2c_client *client,
-			     const struct i2c_device_id *id)
+static int si476x_core_probe(struct i2c_client *client)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(client);
 	int rval;
 	struct si476x_core          *core;
 	struct si476x_platform_data *pdata;
@@ -866,7 +866,7 @@ static struct i2c_driver si476x_core_driver = {
 	.driver		= {
 		.name	= "si476x-core",
 	},
-	.probe		= si476x_core_probe,
+	.probe_new	= si476x_core_probe,
 	.remove         = si476x_core_remove,
 	.id_table       = si476x_id,
 };
-- 
GitLab


From 81943ca2a616e1c35003f15bcac22c2a322610ae Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:13 +0100
Subject: [PATCH 222/875] mfd: sky81452: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-460-uwe@kleine-koenig.org
---
 drivers/mfd/sky81452.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/sky81452.c b/drivers/mfd/sky81452.c
index 3ad35bf0c0155..2515ecae1d3fe 100644
--- a/drivers/mfd/sky81452.c
+++ b/drivers/mfd/sky81452.c
@@ -21,8 +21,7 @@ static const struct regmap_config sky81452_config = {
 	.val_bits = 8,
 };
 
-static int sky81452_probe(struct i2c_client *client,
-				const struct i2c_device_id *id)
+static int sky81452_probe(struct i2c_client *client)
 {
 	struct device *dev = &client->dev;
 	const struct sky81452_platform_data *pdata = dev_get_platdata(dev);
@@ -78,7 +77,7 @@ static struct i2c_driver sky81452_driver = {
 		.name = "sky81452",
 		.of_match_table = of_match_ptr(sky81452_of_match),
 	},
-	.probe = sky81452_probe,
+	.probe_new = sky81452_probe,
 	.id_table = sky81452_ids,
 };
 
-- 
GitLab


From 05b62f4ca66d8c20da59ddc3fdc72bd973acb1b6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:14 +0100
Subject: [PATCH 223/875] mfd: stmfx: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-461-uwe@kleine-koenig.org
---
 drivers/mfd/stmfx.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/stmfx.c b/drivers/mfd/stmfx.c
index 5dd7d96884596..025b8761e50fb 100644
--- a/drivers/mfd/stmfx.c
+++ b/drivers/mfd/stmfx.c
@@ -410,8 +410,7 @@ static void stmfx_chip_exit(struct i2c_client *client)
 	}
 }
 
-static int stmfx_probe(struct i2c_client *client,
-		       const struct i2c_device_id *id)
+static int stmfx_probe(struct i2c_client *client)
 {
 	struct device *dev = &client->dev;
 	struct stmfx *stmfx;
@@ -556,7 +555,7 @@ static struct i2c_driver stmfx_driver = {
 		.of_match_table = stmfx_of_match,
 		.pm = &stmfx_dev_pm_ops,
 	},
-	.probe = stmfx_probe,
+	.probe_new = stmfx_probe,
 	.remove = stmfx_remove,
 };
 module_i2c_driver(stmfx_driver);
-- 
GitLab


From 50b1d5bab4424169d8cc16853a5aa1140fe2bb78 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:15 +0100
Subject: [PATCH 224/875] mfd: stmpe-i2c: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-462-uwe@kleine-koenig.org
---
 drivers/mfd/stmpe-i2c.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/mfd/stmpe-i2c.c b/drivers/mfd/stmpe-i2c.c
index 4d55494a97c4b..624e3d421b9fc 100644
--- a/drivers/mfd/stmpe-i2c.c
+++ b/drivers/mfd/stmpe-i2c.c
@@ -67,8 +67,9 @@ static const struct of_device_id stmpe_of_match[] = {
 MODULE_DEVICE_TABLE(of, stmpe_of_match);
 
 static int
-stmpe_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+stmpe_i2c_probe(struct i2c_client *i2c)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
 	enum stmpe_partnum partnum;
 	const struct of_device_id *of_id;
 
@@ -119,7 +120,7 @@ static struct i2c_driver stmpe_i2c_driver = {
 #endif
 		.of_match_table = stmpe_of_match,
 	},
-	.probe		= stmpe_i2c_probe,
+	.probe_new	= stmpe_i2c_probe,
 	.remove		= stmpe_i2c_remove,
 	.id_table	= stmpe_i2c_id,
 };
-- 
GitLab


From 39cabdc8fbc2b12b1a3cfd29af553ffe1ce06d1d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:16 +0100
Subject: [PATCH 225/875] mfd: stpmic1: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-463-uwe@kleine-koenig.org
---
 drivers/mfd/stpmic1.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/stpmic1.c b/drivers/mfd/stpmic1.c
index eb3da558c3fbd..f5a51171b1b34 100644
--- a/drivers/mfd/stpmic1.c
+++ b/drivers/mfd/stpmic1.c
@@ -116,8 +116,7 @@ static const struct regmap_irq_chip stpmic1_regmap_irq_chip = {
 	.num_irqs = ARRAY_SIZE(stpmic1_irqs),
 };
 
-static int stpmic1_probe(struct i2c_client *i2c,
-			 const struct i2c_device_id *id)
+static int stpmic1_probe(struct i2c_client *i2c)
 {
 	struct stpmic1 *ddata;
 	struct device *dev = &i2c->dev;
@@ -203,7 +202,7 @@ static struct i2c_driver stpmic1_driver = {
 		.of_match_table = of_match_ptr(stpmic1_of_match),
 		.pm = &stpmic1_pm,
 	},
-	.probe = stpmic1_probe,
+	.probe_new = stpmic1_probe,
 };
 
 module_i2c_driver(stpmic1_driver);
-- 
GitLab


From 40ee15f763906ce1d8a47261a3343507f5c7bc9a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:17 +0100
Subject: [PATCH 226/875] mfd: stw481x: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-464-uwe@kleine-koenig.org
---
 drivers/mfd/stw481x.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/stw481x.c b/drivers/mfd/stw481x.c
index 7478f03ccbae2..2a8fc9d1c8063 100644
--- a/drivers/mfd/stw481x.c
+++ b/drivers/mfd/stw481x.c
@@ -173,8 +173,7 @@ static const struct regmap_config stw481x_regmap_config = {
 	.val_bits = 8,
 };
 
-static int stw481x_probe(struct i2c_client *client,
-			 const struct i2c_device_id *id)
+static int stw481x_probe(struct i2c_client *client)
 {
 	struct stw481x			*stw481x;
 	int ret;
@@ -240,7 +239,7 @@ static struct i2c_driver stw481x_driver = {
 		.name	= "stw481x",
 		.of_match_table = stw481x_match,
 	},
-	.probe		= stw481x_probe,
+	.probe_new	= stw481x_probe,
 	.id_table	= stw481x_id,
 };
 
-- 
GitLab


From d28fa288ea506812ef73980b8c3dc9c39ec8c18b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:18 +0100
Subject: [PATCH 227/875] mfd: tc3589x: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-465-uwe@kleine-koenig.org
---
 drivers/mfd/tc3589x.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/tc3589x.c b/drivers/mfd/tc3589x.c
index d5d0ec117acb2..b0f4fff5872dd 100644
--- a/drivers/mfd/tc3589x.c
+++ b/drivers/mfd/tc3589x.c
@@ -352,9 +352,9 @@ tc3589x_of_probe(struct device *dev, enum tc3589x_version *version)
 	return pdata;
 }
 
-static int tc3589x_probe(struct i2c_client *i2c,
-				   const struct i2c_device_id *id)
+static int tc3589x_probe(struct i2c_client *i2c)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
 	struct device_node *np = i2c->dev.of_node;
 	struct tc3589x_platform_data *pdata = dev_get_platdata(&i2c->dev);
 	struct tc3589x *tc3589x;
@@ -486,7 +486,7 @@ static struct i2c_driver tc3589x_driver = {
 		.pm	= &tc3589x_dev_pm_ops,
 		.of_match_table = of_match_ptr(tc3589x_match),
 	},
-	.probe		= tc3589x_probe,
+	.probe_new	= tc3589x_probe,
 	.remove		= tc3589x_remove,
 	.id_table	= tc3589x_id,
 };
-- 
GitLab


From e6a6b1d6bb06e8fda4d9f5a6a9c61291eb504a86 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:19 +0100
Subject: [PATCH 228/875] mfd: ti-lmu: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-466-uwe@kleine-koenig.org
---
 drivers/mfd/ti-lmu.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/mfd/ti-lmu.c b/drivers/mfd/ti-lmu.c
index fd6e8c417baa3..9921320be2557 100644
--- a/drivers/mfd/ti-lmu.c
+++ b/drivers/mfd/ti-lmu.c
@@ -133,8 +133,9 @@ TI_LMU_DATA(lm3633, LM3633_MAX_REG);
 TI_LMU_DATA(lm3695, LM3695_MAX_REG);
 TI_LMU_DATA(lm36274, LM36274_MAX_REG);
 
-static int ti_lmu_probe(struct i2c_client *cl, const struct i2c_device_id *id)
+static int ti_lmu_probe(struct i2c_client *cl)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(cl);
 	struct device *dev = &cl->dev;
 	const struct ti_lmu_data *data;
 	struct regmap_config regmap_cfg;
@@ -216,7 +217,7 @@ static const struct i2c_device_id ti_lmu_ids[] = {
 MODULE_DEVICE_TABLE(i2c, ti_lmu_ids);
 
 static struct i2c_driver ti_lmu_driver = {
-	.probe = ti_lmu_probe,
+	.probe_new = ti_lmu_probe,
 	.driver = {
 		.name = "ti-lmu",
 		.of_match_table = ti_lmu_of_match,
-- 
GitLab


From bb5b1c649a638411805545072f2a284f0ea0dd13 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:20 +0100
Subject: [PATCH 229/875] mfd: tps6105x: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-467-uwe@kleine-koenig.org
---
 drivers/mfd/tps6105x.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/tps6105x.c b/drivers/mfd/tps6105x.c
index b360568ea6750..a66cb911998d7 100644
--- a/drivers/mfd/tps6105x.c
+++ b/drivers/mfd/tps6105x.c
@@ -117,8 +117,7 @@ static struct tps6105x_platform_data *tps6105x_parse_dt(struct device *dev)
 	return pdata;
 }
 
-static int tps6105x_probe(struct i2c_client *client,
-			const struct i2c_device_id *id)
+static int tps6105x_probe(struct i2c_client *client)
 {
 	struct tps6105x			*tps6105x;
 	struct tps6105x_platform_data	*pdata;
@@ -210,7 +209,7 @@ static struct i2c_driver tps6105x_driver = {
 		.name	= "tps6105x",
 		.of_match_table = tps6105x_of_match,
 	},
-	.probe		= tps6105x_probe,
+	.probe_new	= tps6105x_probe,
 	.remove		= tps6105x_remove,
 	.id_table	= tps6105x_id,
 };
-- 
GitLab


From 71b954d8ac2b0c8c0c6bfe7be9d09e8bfba4a711 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:21 +0100
Subject: [PATCH 230/875] mfd: tps65010: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-468-uwe@kleine-koenig.org
---
 drivers/mfd/tps65010.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/tps65010.c b/drivers/mfd/tps65010.c
index c2afa2e69f42f..fb733288cca3b 100644
--- a/drivers/mfd/tps65010.c
+++ b/drivers/mfd/tps65010.c
@@ -519,9 +519,9 @@ static void tps65010_remove(struct i2c_client *client)
 	the_tps = NULL;
 }
 
-static int tps65010_probe(struct i2c_client *client,
-			  const struct i2c_device_id *id)
+static int tps65010_probe(struct i2c_client *client)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(client);
 	struct tps65010		*tps;
 	int			status;
 	struct tps65010_board	*board = dev_get_platdata(&client->dev);
@@ -668,7 +668,7 @@ static struct i2c_driver tps65010_driver = {
 	.driver = {
 		.name	= "tps65010",
 	},
-	.probe	= tps65010_probe,
+	.probe_new = tps65010_probe,
 	.remove	= tps65010_remove,
 	.id_table = tps65010_id,
 };
-- 
GitLab


From 0e1a8964f270226218e8055ecd2fac4d96788c7b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:22 +0100
Subject: [PATCH 231/875] mfd: tps6507x: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-469-uwe@kleine-koenig.org
---
 drivers/mfd/tps6507x.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/tps6507x.c b/drivers/mfd/tps6507x.c
index 1f308c4e36941..500b594de3165 100644
--- a/drivers/mfd/tps6507x.c
+++ b/drivers/mfd/tps6507x.c
@@ -84,8 +84,7 @@ static int tps6507x_i2c_write_device(struct tps6507x_dev *tps6507x, char reg,
 	return 0;
 }
 
-static int tps6507x_i2c_probe(struct i2c_client *i2c,
-			    const struct i2c_device_id *id)
+static int tps6507x_i2c_probe(struct i2c_client *i2c)
 {
 	struct tps6507x_dev *tps6507x;
 
@@ -123,7 +122,7 @@ static struct i2c_driver tps6507x_i2c_driver = {
 		   .name = "tps6507x",
 		   .of_match_table = of_match_ptr(tps6507x_of_match),
 	},
-	.probe = tps6507x_i2c_probe,
+	.probe_new = tps6507x_i2c_probe,
 	.id_table = tps6507x_i2c_id,
 };
 
-- 
GitLab


From 1f662faa5e8ef07a4cd68fe3ebe2b4dac419c503 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:23 +0100
Subject: [PATCH 232/875] mfd: tps65086: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-470-uwe@kleine-koenig.org
---
 drivers/mfd/tps65086.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/tps65086.c b/drivers/mfd/tps65086.c
index 81a7360a87bbc..9494c1d71b866 100644
--- a/drivers/mfd/tps65086.c
+++ b/drivers/mfd/tps65086.c
@@ -61,8 +61,7 @@ static const struct of_device_id tps65086_of_match_table[] = {
 };
 MODULE_DEVICE_TABLE(of, tps65086_of_match_table);
 
-static int tps65086_probe(struct i2c_client *client,
-			  const struct i2c_device_id *ids)
+static int tps65086_probe(struct i2c_client *client)
 {
 	struct tps65086 *tps;
 	unsigned int version;
@@ -130,7 +129,7 @@ static struct i2c_driver tps65086_driver = {
 		.name	= "tps65086",
 		.of_match_table = tps65086_of_match_table,
 	},
-	.probe		= tps65086_probe,
+	.probe_new	= tps65086_probe,
 	.remove		= tps65086_remove,
 	.id_table       = tps65086_id_table,
 };
-- 
GitLab


From b63250984c88faf0df7c75b16587dbb20611c8d0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:24 +0100
Subject: [PATCH 233/875] mfd: tps65090: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-471-uwe@kleine-koenig.org
---
 drivers/mfd/tps65090.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/tps65090.c b/drivers/mfd/tps65090.c
index bd6235308c6b9..e1f2491a2578d 100644
--- a/drivers/mfd/tps65090.c
+++ b/drivers/mfd/tps65090.c
@@ -164,8 +164,7 @@ static const struct of_device_id tps65090_of_match[] = {
 };
 #endif
 
-static int tps65090_i2c_probe(struct i2c_client *client,
-			      const struct i2c_device_id *id)
+static int tps65090_i2c_probe(struct i2c_client *client)
 {
 	struct tps65090_platform_data *pdata = dev_get_platdata(&client->dev);
 	int irq_base = 0;
@@ -238,7 +237,7 @@ static struct i2c_driver tps65090_driver = {
 		.suppress_bind_attrs = true,
 		.of_match_table = of_match_ptr(tps65090_of_match),
 	},
-	.probe		= tps65090_i2c_probe,
+	.probe_new	= tps65090_i2c_probe,
 	.id_table	= tps65090_id_table,
 };
 
-- 
GitLab


From 3d984091e15a11e7f1520ea6c30e82d39e91c2f6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:25 +0100
Subject: [PATCH 234/875] mfd: tps65218: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-472-uwe@kleine-koenig.org
---
 drivers/mfd/tps65218.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/tps65218.c b/drivers/mfd/tps65218.c
index 49bb8fd168f87..ea69dcef91ecc 100644
--- a/drivers/mfd/tps65218.c
+++ b/drivers/mfd/tps65218.c
@@ -280,8 +280,7 @@ static int tps65218_voltage_set_uvlo(struct tps65218 *tps)
 	return 0;
 }
 
-static int tps65218_probe(struct i2c_client *client,
-				const struct i2c_device_id *ids)
+static int tps65218_probe(struct i2c_client *client)
 {
 	struct tps65218 *tps;
 	int ret;
@@ -348,7 +347,7 @@ static struct i2c_driver tps65218_driver = {
 		.name	= "tps65218",
 		.of_match_table = of_tps65218_match_table,
 	},
-	.probe		= tps65218_probe,
+	.probe_new	= tps65218_probe,
 	.id_table       = tps65218_id_table,
 };
 
-- 
GitLab


From ba801bd52f883bd934238ad7b47c35048f42ddc1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:26 +0100
Subject: [PATCH 235/875] mfd: tps6586x: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-473-uwe@kleine-koenig.org
---
 drivers/mfd/tps6586x.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/tps6586x.c b/drivers/mfd/tps6586x.c
index fb340da64bbc4..92703e975ffae 100644
--- a/drivers/mfd/tps6586x.c
+++ b/drivers/mfd/tps6586x.c
@@ -499,8 +499,7 @@ static void tps6586x_print_version(struct i2c_client *client, int version)
 	dev_info(&client->dev, "Found %s, VERSIONCRC is %02x\n", name, version);
 }
 
-static int tps6586x_i2c_probe(struct i2c_client *client,
-					const struct i2c_device_id *id)
+static int tps6586x_i2c_probe(struct i2c_client *client)
 {
 	struct tps6586x_platform_data *pdata = dev_get_platdata(&client->dev);
 	struct tps6586x *tps6586x;
@@ -624,7 +623,7 @@ static struct i2c_driver tps6586x_driver = {
 		.of_match_table = of_match_ptr(tps6586x_of_match),
 		.pm	= &tps6586x_pm_ops,
 	},
-	.probe		= tps6586x_i2c_probe,
+	.probe_new	= tps6586x_i2c_probe,
 	.remove		= tps6586x_i2c_remove,
 	.id_table	= tps6586x_id_table,
 };
-- 
GitLab


From 74e52d31cf1d26485c1df3f7caca53b6cc6410d3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:27 +0100
Subject: [PATCH 236/875] mfd: tps65910: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-474-uwe@kleine-koenig.org
---
 drivers/mfd/tps65910.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/tps65910.c b/drivers/mfd/tps65910.c
index 67e2707af4bce..821c0277a2edc 100644
--- a/drivers/mfd/tps65910.c
+++ b/drivers/mfd/tps65910.c
@@ -441,9 +441,9 @@ static void tps65910_power_off(void)
 			   DEVCTRL_DEV_OFF_MASK);
 }
 
-static int tps65910_i2c_probe(struct i2c_client *i2c,
-			      const struct i2c_device_id *id)
+static int tps65910_i2c_probe(struct i2c_client *i2c)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
 	struct tps65910 *tps65910;
 	struct tps65910_board *pmic_plat_data;
 	struct tps65910_board *of_pmic_plat_data = NULL;
@@ -535,7 +535,7 @@ static struct i2c_driver tps65910_i2c_driver = {
 		   .name = "tps65910",
 		   .of_match_table = of_match_ptr(tps65910_of_match),
 	},
-	.probe = tps65910_i2c_probe,
+	.probe_new = tps65910_i2c_probe,
 	.id_table = tps65910_i2c_id,
 };
 
-- 
GitLab


From 328fc6f86f509f8b98147d5397caa1851e63ca49 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:28 +0100
Subject: [PATCH 237/875] mfd: tps65912-i2c: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-475-uwe@kleine-koenig.org
---
 drivers/mfd/tps65912-i2c.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/tps65912-i2c.c b/drivers/mfd/tps65912-i2c.c
index 7e2b19efe8679..1bf945966bf7a 100644
--- a/drivers/mfd/tps65912-i2c.c
+++ b/drivers/mfd/tps65912-i2c.c
@@ -21,8 +21,7 @@ static const struct of_device_id tps65912_i2c_of_match_table[] = {
 };
 MODULE_DEVICE_TABLE(of, tps65912_i2c_of_match_table);
 
-static int tps65912_i2c_probe(struct i2c_client *client,
-			      const struct i2c_device_id *ids)
+static int tps65912_i2c_probe(struct i2c_client *client)
 {
 	struct tps65912 *tps;
 
@@ -61,7 +60,7 @@ static struct i2c_driver tps65912_i2c_driver = {
 		.name	= "tps65912",
 		.of_match_table = tps65912_i2c_of_match_table,
 	},
-	.probe		= tps65912_i2c_probe,
+	.probe_new	= tps65912_i2c_probe,
 	.remove		= tps65912_i2c_remove,
 	.id_table       = tps65912_i2c_id_table,
 };
-- 
GitLab


From c291d0e347261c329fe7280e4bacfb23294db5b0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:29 +0100
Subject: [PATCH 238/875] mfd: twl-core: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-476-uwe@kleine-koenig.org
---
 drivers/mfd/twl-core.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index f6b4b9d94bbd3..62be2326c9b20 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -754,8 +754,9 @@ static struct of_dev_auxdata twl_auxdata_lookup[] = {
 
 /* NOTE: This driver only handles a single twl4030/tps659x0 chip */
 static int
-twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
+twl_probe(struct i2c_client *client)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(client);
 	struct device_node		*node = client->dev.of_node;
 	struct platform_device		*pdev;
 	const struct regmap_config	*twl_regmap_config;
@@ -955,7 +956,7 @@ static struct i2c_driver twl_driver = {
 	.driver.name	= DRIVER_NAME,
 	.driver.pm	= &twl_dev_pm_ops,
 	.id_table	= twl_ids,
-	.probe		= twl_probe,
+	.probe_new	= twl_probe,
 	.remove		= twl_remove,
 };
 builtin_i2c_driver(twl_driver);
-- 
GitLab


From d85213be3397e16d15a29420a32f75450a096355 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:30 +0100
Subject: [PATCH 239/875] mfd: twl6040: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-477-uwe@kleine-koenig.org
---
 drivers/mfd/twl6040.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/twl6040.c b/drivers/mfd/twl6040.c
index f429b8f00db61..dd9543f6213f4 100644
--- a/drivers/mfd/twl6040.c
+++ b/drivers/mfd/twl6040.c
@@ -633,8 +633,7 @@ static struct regmap_irq_chip twl6040_irq_chip = {
 	.mask_base = TWL6040_REG_INTMR,
 };
 
-static int twl6040_probe(struct i2c_client *client,
-			 const struct i2c_device_id *id)
+static int twl6040_probe(struct i2c_client *client)
 {
 	struct device_node *node = client->dev.of_node;
 	struct twl6040 *twl6040;
@@ -833,7 +832,7 @@ static struct i2c_driver twl6040_driver = {
 	.driver = {
 		.name = "twl6040",
 	},
-	.probe		= twl6040_probe,
+	.probe_new	= twl6040_probe,
 	.remove		= twl6040_remove,
 	.id_table	= twl6040_i2c_id,
 };
-- 
GitLab


From 490e11b7c33c094e5263e03df59deffd71eac5cf Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:31 +0100
Subject: [PATCH 240/875] mfd: wl1273-core: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-478-uwe@kleine-koenig.org
---
 drivers/mfd/wl1273-core.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/wl1273-core.c b/drivers/mfd/wl1273-core.c
index 1ab5e15a65ebc..a5d6128fc67d4 100644
--- a/drivers/mfd/wl1273-core.c
+++ b/drivers/mfd/wl1273-core.c
@@ -156,8 +156,7 @@ static int wl1273_fm_set_volume(struct wl1273_core *core, unsigned int volume)
 	return 0;
 }
 
-static int wl1273_core_probe(struct i2c_client *client,
-				       const struct i2c_device_id *id)
+static int wl1273_core_probe(struct i2c_client *client)
 {
 	struct wl1273_fm_platform_data *pdata = dev_get_platdata(&client->dev);
 	struct wl1273_core *core;
@@ -233,7 +232,7 @@ static struct i2c_driver wl1273_core_driver = {
 	.driver = {
 		.name = WL1273_FM_DRIVER_NAME,
 	},
-	.probe = wl1273_core_probe,
+	.probe_new = wl1273_core_probe,
 	.id_table = wl1273_driver_id_table,
 };
 
-- 
GitLab


From 5fb66be1bf4984ab0c49e3296efd66fdb65cace9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:32 +0100
Subject: [PATCH 241/875] mfd: wm831x-i2c: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-479-uwe@kleine-koenig.org
---
 drivers/mfd/wm831x-i2c.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/wm831x-i2c.c b/drivers/mfd/wm831x-i2c.c
index daa1ad0365954..9dbe96e2d46a0 100644
--- a/drivers/mfd/wm831x-i2c.c
+++ b/drivers/mfd/wm831x-i2c.c
@@ -21,9 +21,9 @@
 #include <linux/mfd/wm831x/core.h>
 #include <linux/mfd/wm831x/pdata.h>
 
-static int wm831x_i2c_probe(struct i2c_client *i2c,
-			    const struct i2c_device_id *id)
+static int wm831x_i2c_probe(struct i2c_client *i2c)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
 	struct wm831x_pdata *pdata = dev_get_platdata(&i2c->dev);
 	const struct of_device_id *of_id;
 	struct wm831x *wm831x;
@@ -102,7 +102,7 @@ static struct i2c_driver wm831x_i2c_driver = {
 		.of_match_table = of_match_ptr(wm831x_of_match),
 		.suppress_bind_attrs = true,
 	},
-	.probe = wm831x_i2c_probe,
+	.probe_new = wm831x_i2c_probe,
 	.id_table = wm831x_i2c_id,
 };
 
-- 
GitLab


From 8b20feff0985599c20e7824807fcfb3a40589dd8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:33 +0100
Subject: [PATCH 242/875] mfd: wm8350-i2c: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-480-uwe@kleine-koenig.org
---
 drivers/mfd/wm8350-i2c.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/wm8350-i2c.c b/drivers/mfd/wm8350-i2c.c
index 48fd46800c281..1fa1dfbc9e315 100644
--- a/drivers/mfd/wm8350-i2c.c
+++ b/drivers/mfd/wm8350-i2c.c
@@ -16,8 +16,7 @@
 #include <linux/regmap.h>
 #include <linux/slab.h>
 
-static int wm8350_i2c_probe(struct i2c_client *i2c,
-			    const struct i2c_device_id *id)
+static int wm8350_i2c_probe(struct i2c_client *i2c)
 {
 	struct wm8350 *wm8350;
 	struct wm8350_platform_data *pdata = dev_get_platdata(&i2c->dev);
@@ -53,7 +52,7 @@ static struct i2c_driver wm8350_i2c_driver = {
 		   .name = "wm8350",
 		   .suppress_bind_attrs = true,
 	},
-	.probe = wm8350_i2c_probe,
+	.probe_new = wm8350_i2c_probe,
 	.id_table = wm8350_i2c_id,
 };
 
-- 
GitLab


From 521fcf401f97f76948c64fb0bd039fdf3795486f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:34 +0100
Subject: [PATCH 243/875] mfd: wm8400-core: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-481-uwe@kleine-koenig.org
---
 drivers/mfd/wm8400-core.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/wm8400-core.c b/drivers/mfd/wm8400-core.c
index 0fe32a05421be..5e1599ac9abc3 100644
--- a/drivers/mfd/wm8400-core.c
+++ b/drivers/mfd/wm8400-core.c
@@ -118,8 +118,7 @@ void wm8400_reset_codec_reg_cache(struct wm8400 *wm8400)
 EXPORT_SYMBOL_GPL(wm8400_reset_codec_reg_cache);
 
 #if IS_ENABLED(CONFIG_I2C)
-static int wm8400_i2c_probe(struct i2c_client *i2c,
-			    const struct i2c_device_id *id)
+static int wm8400_i2c_probe(struct i2c_client *i2c)
 {
 	struct wm8400 *wm8400;
 
@@ -146,7 +145,7 @@ static struct i2c_driver wm8400_i2c_driver = {
 	.driver = {
 		.name = "WM8400",
 	},
-	.probe    = wm8400_i2c_probe,
+	.probe_new = wm8400_i2c_probe,
 	.id_table = wm8400_i2c_id,
 };
 #endif
-- 
GitLab


From 54f872baf6b17a74492f4d601be3c36626907178 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:43:35 +0100
Subject: [PATCH 244/875] mfd: wm8994-core: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-482-uwe@kleine-koenig.org
---
 drivers/mfd/wm8994-core.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/wm8994-core.c b/drivers/mfd/wm8994-core.c
index 7e88f5b0abe6a..53994abe75968 100644
--- a/drivers/mfd/wm8994-core.c
+++ b/drivers/mfd/wm8994-core.c
@@ -623,9 +623,9 @@ static const struct of_device_id wm8994_of_match[] = {
 };
 MODULE_DEVICE_TABLE(of, wm8994_of_match);
 
-static int wm8994_i2c_probe(struct i2c_client *i2c,
-				      const struct i2c_device_id *id)
+static int wm8994_i2c_probe(struct i2c_client *i2c)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
 	const struct of_device_id *of_id;
 	struct wm8994 *wm8994;
 	int ret;
@@ -683,7 +683,7 @@ static struct i2c_driver wm8994_i2c_driver = {
 		.pm = &wm8994_pm_ops,
 		.of_match_table = wm8994_of_match,
 	},
-	.probe = wm8994_i2c_probe,
+	.probe_new = wm8994_i2c_probe,
 	.remove = wm8994_i2c_remove,
 	.id_table = wm8994_i2c_id,
 };
-- 
GitLab


From 2e992b22ccd1a620165a077355163798c3951d4b Mon Sep 17 00:00:00 2001
From: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Date: Sun, 25 Sep 2022 22:44:17 -0700
Subject: [PATCH 245/875] mfd: mc13xxx: Stop including of_gpio.h

Neither SPI nor I2C variant uses any APIs from of_gpio.h so let's stop
including it.

Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20220926054421.1546436-1-dmitry.torokhov@gmail.com
---
 drivers/mfd/mc13xxx-i2c.c | 1 -
 drivers/mfd/mc13xxx-spi.c | 1 -
 2 files changed, 2 deletions(-)

diff --git a/drivers/mfd/mc13xxx-i2c.c b/drivers/mfd/mc13xxx-i2c.c
index 9593e2be23ed5..633b973a5ba77 100644
--- a/drivers/mfd/mc13xxx-i2c.c
+++ b/drivers/mfd/mc13xxx-i2c.c
@@ -11,7 +11,6 @@
 #include <linux/mfd/mc13xxx.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
-#include <linux/of_gpio.h>
 #include <linux/i2c.h>
 #include <linux/err.h>
 
diff --git a/drivers/mfd/mc13xxx-spi.c b/drivers/mfd/mc13xxx-spi.c
index f803527e58194..2809fbeb317c5 100644
--- a/drivers/mfd/mc13xxx-spi.c
+++ b/drivers/mfd/mc13xxx-spi.c
@@ -15,7 +15,6 @@
 #include <linux/mfd/mc13xxx.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
-#include <linux/of_gpio.h>
 #include <linux/err.h>
 #include <linux/spi/spi.h>
 
-- 
GitLab


From de5567ca320aee5c99dd7bbebefffb05cc9df9f4 Mon Sep 17 00:00:00 2001
From: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Date: Sun, 25 Sep 2022 22:44:18 -0700
Subject: [PATCH 246/875] mfd: madera: Include correct gpio API

The driver is using gpiod API and therefore should include
linux/gpio/consumer.h, not linux/gpio.h. Also, the driver does not use
any of the APIs from of_gpio.h, so we should not be including it.

Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20220926054421.1546436-2-dmitry.torokhov@gmail.com
---
 drivers/mfd/madera-core.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/mfd/madera-core.c b/drivers/mfd/madera-core.c
index a2abc0094def7..bdbd5bfc97145 100644
--- a/drivers/mfd/madera-core.c
+++ b/drivers/mfd/madera-core.c
@@ -8,13 +8,12 @@
 #include <linux/device.h>
 #include <linux/delay.h>
 #include <linux/err.h>
-#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
 #include <linux/mfd/core.h>
 #include <linux/module.h>
 #include <linux/mutex.h>
 #include <linux/notifier.h>
 #include <linux/of.h>
-#include <linux/of_gpio.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
 #include <linux/regmap.h>
-- 
GitLab


From 7ca91a33775c4a33cb451f508f84a7820179c73b Mon Sep 17 00:00:00 2001
From: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Date: Sun, 25 Sep 2022 22:44:19 -0700
Subject: [PATCH 247/875] mfd: palmas: Stop including of_gpio.h

It does not appear that any of palmas sub-drivers are using OF-based
gpio APIs, so let's stop including this header.

Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20220926054421.1546436-3-dmitry.torokhov@gmail.com
---
 include/linux/mfd/palmas.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h
index 1e61c7e9f50df..117d027084395 100644
--- a/include/linux/mfd/palmas.h
+++ b/include/linux/mfd/palmas.h
@@ -16,7 +16,6 @@
 #include <linux/regmap.h>
 #include <linux/regulator/driver.h>
 #include <linux/extcon-provider.h>
-#include <linux/of_gpio.h>
 #include <linux/usb/phy_companion.h>
 
 #define PALMAS_NUM_CLIENTS		3
-- 
GitLab


From 3c92699a167a543b2bc7d603e4a09aa78a99f809 Mon Sep 17 00:00:00 2001
From: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Date: Sun, 25 Sep 2022 22:44:20 -0700
Subject: [PATCH 248/875] mfd: twl6040: Switch to using gpiod API

This patch switches the dirver from legacy gpio API to a newer gpiod
API so that we can eventually drop the former.

Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20220926054421.1546436-4-dmitry.torokhov@gmail.com
---
 drivers/mfd/twl6040.c       | 29 +++++++++++++----------------
 include/linux/mfd/twl6040.h |  5 +++--
 2 files changed, 16 insertions(+), 18 deletions(-)

diff --git a/drivers/mfd/twl6040.c b/drivers/mfd/twl6040.c
index dd9543f6213f4..fc97fa5a2d0c3 100644
--- a/drivers/mfd/twl6040.c
+++ b/drivers/mfd/twl6040.c
@@ -17,9 +17,8 @@
 #include <linux/platform_device.h>
 #include <linux/of.h>
 #include <linux/of_irq.h>
-#include <linux/of_gpio.h>
 #include <linux/of_platform.h>
-#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
 #include <linux/delay.h>
 #include <linux/i2c.h>
 #include <linux/regmap.h>
@@ -251,7 +250,7 @@ static int twl6040_power_up_automatic(struct twl6040 *twl6040)
 {
 	int time_left;
 
-	gpio_set_value(twl6040->audpwron, 1);
+	gpiod_set_value_cansleep(twl6040->audpwron, 1);
 
 	time_left = wait_for_completion_timeout(&twl6040->ready,
 						msecs_to_jiffies(144));
@@ -262,7 +261,7 @@ static int twl6040_power_up_automatic(struct twl6040 *twl6040)
 		intid = twl6040_reg_read(twl6040, TWL6040_REG_INTID);
 		if (!(intid & TWL6040_READYINT)) {
 			dev_err(twl6040->dev, "automatic power-up failed\n");
-			gpio_set_value(twl6040->audpwron, 0);
+			gpiod_set_value_cansleep(twl6040->audpwron, 0);
 			return -ETIMEDOUT;
 		}
 	}
@@ -290,7 +289,7 @@ int twl6040_power(struct twl6040 *twl6040, int on)
 		/* Allow writes to the chip */
 		regcache_cache_only(twl6040->regmap, false);
 
-		if (gpio_is_valid(twl6040->audpwron)) {
+		if (twl6040->audpwron) {
 			/* use automatic power-up sequence */
 			ret = twl6040_power_up_automatic(twl6040);
 			if (ret) {
@@ -337,9 +336,9 @@ int twl6040_power(struct twl6040 *twl6040, int on)
 		if (--twl6040->power_count)
 			goto out;
 
-		if (gpio_is_valid(twl6040->audpwron)) {
+		if (twl6040->audpwron) {
 			/* use AUDPWRON line */
-			gpio_set_value(twl6040->audpwron, 0);
+			gpiod_set_value_cansleep(twl6040->audpwron, 0);
 
 			/* power-down sequence latency */
 			usleep_range(500, 700);
@@ -711,18 +710,16 @@ static int twl6040_probe(struct i2c_client *client)
 	}
 
 	/* ERRATA: Automatic power-up is not possible in ES1.0 */
-	if (twl6040_get_revid(twl6040) > TWL6040_REV_ES1_0)
-		twl6040->audpwron = of_get_named_gpio(node,
-						      "ti,audpwron-gpio", 0);
-	else
-		twl6040->audpwron = -EINVAL;
-
-	if (gpio_is_valid(twl6040->audpwron)) {
-		ret = devm_gpio_request_one(&client->dev, twl6040->audpwron,
-					    GPIOF_OUT_INIT_LOW, "audpwron");
+	if (twl6040_get_revid(twl6040) > TWL6040_REV_ES1_0) {
+		twl6040->audpwron = devm_gpiod_get_optional(&client->dev,
+							    "ti,audpwron",
+							    GPIOD_OUT_LOW);
+		ret = PTR_ERR_OR_ZERO(twl6040->audpwron);
 		if (ret)
 			goto gpio_err;
 
+		gpiod_set_consumer_name(twl6040->audpwron, "audpwron");
+
 		/* Clear any pending interrupt */
 		twl6040_reg_read(twl6040, TWL6040_REG_INTID);
 	}
diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h
index 1fc7450bd8ab1..cb1e7a9ce3177 100644
--- a/include/linux/mfd/twl6040.h
+++ b/include/linux/mfd/twl6040.h
@@ -196,13 +196,14 @@ struct twl6040_gpo_data {
 };
 
 struct twl6040_platform_data {
-	int audpwron_gpio;	/* audio power-on gpio */
+	struct gpio_desc *audpwron_gpio;	/* audio power-on gpio */
 
 	struct twl6040_codec_data *codec;
 	struct twl6040_vibra_data *vibra;
 	struct twl6040_gpo_data *gpo;
 };
 
+struct gpio_desc;
 struct regmap;
 struct regmap_irq_chips_data;
 
@@ -218,7 +219,7 @@ struct twl6040 {
 	struct mfd_cell cells[TWL6040_CELLS];
 	struct completion ready;
 
-	int audpwron;
+	struct gpio_desc *audpwron;
 	int power_count;
 	int rev;
 
-- 
GitLab


From 1f7caaa1743edbc40f3cd7e2bc0dff89698fd91d Mon Sep 17 00:00:00 2001
From: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Date: Sun, 25 Sep 2022 22:44:21 -0700
Subject: [PATCH 249/875] mfd: twl6040: Drop twl6040_platform_data and
 associated definitions

As of df04b6242a58 ("mfd: twl6040: Remove support for legacy (pdata)
mode") the driver no longer references the platform data, so we can drop
its definition, as well as definitions of related structures.

Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20220926054421.1546436-5-dmitry.torokhov@gmail.com
---
 include/linux/mfd/twl6040.h | 29 -----------------------------
 1 file changed, 29 deletions(-)

diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h
index cb1e7a9ce3177..286a724e379a7 100644
--- a/include/linux/mfd/twl6040.h
+++ b/include/linux/mfd/twl6040.h
@@ -174,35 +174,6 @@
 
 #define TWL6040_GPO_MAX	3
 
-/* TODO: All platform data struct can be removed */
-struct twl6040_codec_data {
-	u16 hs_left_step;
-	u16 hs_right_step;
-	u16 hf_left_step;
-	u16 hf_right_step;
-};
-
-struct twl6040_vibra_data {
-	unsigned int vibldrv_res;	/* left driver resistance */
-	unsigned int vibrdrv_res;	/* right driver resistance */
-	unsigned int viblmotor_res;	/* left motor resistance */
-	unsigned int vibrmotor_res;	/* right motor resistance */
-	int vddvibl_uV;			/* VDDVIBL volt, set 0 for fixed reg */
-	int vddvibr_uV;			/* VDDVIBR volt, set 0 for fixed reg */
-};
-
-struct twl6040_gpo_data {
-	int gpio_base;
-};
-
-struct twl6040_platform_data {
-	struct gpio_desc *audpwron_gpio;	/* audio power-on gpio */
-
-	struct twl6040_codec_data *codec;
-	struct twl6040_vibra_data *vibra;
-	struct twl6040_gpo_data *gpo;
-};
-
 struct gpio_desc;
 struct regmap;
 struct regmap_irq_chips_data;
-- 
GitLab


From 763ab98687404d924b6612f7c9c8430333d31229 Mon Sep 17 00:00:00 2001
From: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Date: Wed, 28 Sep 2022 01:05:17 +0100
Subject: [PATCH 250/875] dt-bindings: mfd: qcom,spmi-pmic: Drop PWM reg
 dependency

The PWM node is not a separate device and is expected to be part of parent
SPMI PMIC node, thus it obtains the address space from the parent. One IO
address in "reg" is also not correct description because LPG block maps to
several regions.

Fixes: 3f5117be9584 ("dt-bindings: mfd: convert to yaml Qualcomm SPMI PMIC")
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20220928000517.228382-2-bryan.odonoghue@linaro.org
---
 Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
index 6a3e3ede1ede7..777f2da52f1ed 100644
--- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
+++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
@@ -98,6 +98,10 @@ properties:
     type: object
     $ref: /schemas/regulator/qcom,spmi-regulator.yaml#
 
+  pwm:
+    type: object
+    $ref: /schemas/leds/leds-qcom-lpg.yaml#
+
 patternProperties:
   "^adc@[0-9a-f]+$":
     type: object
@@ -123,10 +127,6 @@ patternProperties:
     type: object
     $ref: /schemas/power/reset/qcom,pon.yaml#
 
-  "pwm@[0-9a-f]+$":
-    type: object
-    $ref: /schemas/leds/leds-qcom-lpg.yaml#
-
   "^rtc@[0-9a-f]+$":
     type: object
     $ref: /schemas/rtc/qcom-pm8xxx-rtc.yaml#
-- 
GitLab


From f19fd81ba1ea34a4ddb771cc3b64059f6e666b12 Mon Sep 17 00:00:00 2001
From: Quan Nguyen <quan@os.amperecomputing.com>
Date: Thu, 29 Sep 2022 16:43:20 +0700
Subject: [PATCH 251/875] mfd: Add Ampere's Altra SMpro MFD driver

Adds Multi-function devices driver for SMpro co-processor found on the
Mt.Jade hardware reference platform with Ampere's Altra processor family.

Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20220929094321.770125-9-quan@os.amperecomputing.com
---
 drivers/mfd/Kconfig      |  12 ++++
 drivers/mfd/Makefile     |   1 +
 drivers/mfd/smpro-core.c | 138 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 151 insertions(+)
 create mode 100644 drivers/mfd/smpro-core.c

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 8b93856de432a..9e77f47629994 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -77,6 +77,18 @@ config MFD_AS3711
 	help
 	  Support for the AS3711 PMIC from AMS
 
+config MFD_SMPRO
+	tristate "Ampere Computing SMpro core driver"
+	depends on I2C
+	select MFD_CORE
+	select REGMAP_I2C
+	help
+	  Say yes here to enable SMpro driver support for Ampere's Altra
+	  processor family.
+
+	  Ampere's Altra SMpro exposes an I2C regmap interface that can
+	  be accessed by child devices.
+
 config MFD_AS3722
 	tristate "ams AS3722 Power Management IC"
 	select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 7ed3ef4a698cf..9387c3ddab4e5 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -271,6 +271,7 @@ obj-$(CONFIG_MFD_QCOM_PM8008)	+= qcom-pm8008.o
 
 obj-$(CONFIG_SGI_MFD_IOC3)	+= ioc3.o
 obj-$(CONFIG_MFD_SIMPLE_MFD_I2C)	+= simple-mfd-i2c.o
+obj-$(CONFIG_MFD_SMPRO)		+= smpro-core.o
 obj-$(CONFIG_MFD_INTEL_M10_BMC)   += intel-m10-bmc.o
 
 obj-$(CONFIG_MFD_ATC260X)	+= atc260x-core.o
diff --git a/drivers/mfd/smpro-core.c b/drivers/mfd/smpro-core.c
new file mode 100644
index 0000000000000..d7729cf703782
--- /dev/null
+++ b/drivers/mfd/smpro-core.c
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Ampere Altra Family SMPro core driver
+ * Copyright (c) 2022, Ampere Computing LLC
+ */
+
+#include <linux/i2c.h>
+#include <linux/kernel.h>
+#include <linux/mfd/core.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/regmap.h>
+
+/* Identification Registers */
+#define MANUFACTURER_ID_REG     0x02
+#define AMPERE_MANUFACTURER_ID  0xCD3A
+
+#define CORE_CE_ERR_DATA        0x82
+#define CORE_UE_ERR_DATA        0x85
+#define MEM_CE_ERR_DATA         0x92
+#define MEM_UE_ERR_DATA         0x95
+#define PCIE_CE_ERR_DATA        0xC2
+#define PCIE_UE_ERR_DATA        0xC5
+#define OTHER_CE_ERR_DATA       0xD2
+#define OTHER_UE_ERR_DATA       0xDA
+
+static int smpro_core_write(void *context, const void *data, size_t count)
+{
+	struct device *dev = context;
+	struct i2c_client *i2c = to_i2c_client(dev);
+	int ret;
+
+	ret = i2c_master_send(i2c, data, count);
+	if (unlikely(ret != count))
+		return (ret < 0) ? ret : -EIO;
+
+	return 0;
+}
+
+static int smpro_core_read(void *context, const void *reg, size_t reg_size,
+			   void *val, size_t val_size)
+{
+	struct device *dev = context;
+	struct i2c_client *i2c = to_i2c_client(dev);
+	struct i2c_msg xfer[2];
+	unsigned char buf[2];
+	int ret;
+
+	xfer[0].addr = i2c->addr;
+	xfer[0].flags = 0;
+
+	buf[0] = *(u8 *)reg;
+	buf[1] = val_size;
+	xfer[0].len = 2;
+	xfer[0].buf = buf;
+
+	xfer[1].addr = i2c->addr;
+	xfer[1].flags = I2C_M_RD;
+	xfer[1].len = val_size;
+	xfer[1].buf = val;
+
+	ret = i2c_transfer(i2c->adapter, xfer, 2);
+	if (unlikely(ret != 2))
+		return (ret < 0) ? ret : -EIO;
+
+	return 0;
+}
+
+static const struct regmap_bus smpro_regmap_bus = {
+	.read = smpro_core_read,
+	.write = smpro_core_write,
+	.val_format_endian_default = REGMAP_ENDIAN_BIG,
+};
+
+static bool smpro_core_readable_noinc_reg(struct device *dev, unsigned int reg)
+{
+	return  (reg == CORE_CE_ERR_DATA || reg == CORE_UE_ERR_DATA ||
+		 reg == MEM_CE_ERR_DATA || reg == MEM_UE_ERR_DATA ||
+		 reg == PCIE_CE_ERR_DATA || reg == PCIE_UE_ERR_DATA ||
+		 reg == OTHER_CE_ERR_DATA || reg == OTHER_UE_ERR_DATA);
+}
+
+static const struct regmap_config smpro_regmap_config = {
+	.reg_bits = 8,
+	.val_bits = 16,
+	.readable_noinc_reg = smpro_core_readable_noinc_reg,
+};
+
+static const struct mfd_cell smpro_devs[] = {
+	MFD_CELL_NAME("smpro-hwmon"),
+	MFD_CELL_NAME("smpro-errmon"),
+	MFD_CELL_NAME("smpro-misc"),
+};
+
+static int smpro_core_probe(struct i2c_client *i2c)
+{
+	const struct regmap_config *config;
+	struct regmap *regmap;
+	unsigned int val;
+	int ret;
+
+	config = device_get_match_data(&i2c->dev);
+	if (!config)
+		return -EINVAL;
+
+	regmap = devm_regmap_init(&i2c->dev, &smpro_regmap_bus, &i2c->dev, config);
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
+
+	ret = regmap_read(regmap, MANUFACTURER_ID_REG, &val);
+	if (ret)
+		return ret;
+
+	if (val != AMPERE_MANUFACTURER_ID)
+		return -ENODEV;
+
+	return devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO,
+				    smpro_devs, ARRAY_SIZE(smpro_devs), NULL, 0, NULL);
+}
+
+static const struct of_device_id smpro_core_of_match[] = {
+	{ .compatible = "ampere,smpro", .data = &smpro_regmap_config },
+	{}
+};
+MODULE_DEVICE_TABLE(of, smpro_core_of_match);
+
+static struct i2c_driver smpro_core_driver = {
+	.probe_new = smpro_core_probe,
+	.driver = {
+		.name = "smpro-core",
+		.of_match_table = smpro_core_of_match,
+	},
+};
+module_i2c_driver(smpro_core_driver);
+
+MODULE_AUTHOR("Quan Nguyen <quan@os.amperecomputing.com>");
+MODULE_DESCRIPTION("SMPRO CORE - I2C driver");
+MODULE_LICENSE("GPL");
-- 
GitLab


From 03317a86df980f255b80a9f7122ffa16b3451f3b Mon Sep 17 00:00:00 2001
From: Johan Hovold <johan+linaro@kernel.org>
Date: Fri, 7 Oct 2022 14:11:10 +0200
Subject: [PATCH 252/875] dt-bindings: mfd: qcom,tcsr: Add sc8280xp binding

Add a binding for the SC8280XP TCSR.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221007121110.5432-1-johan+linaro@kernel.org
---
 Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
index b12809b5cc22e..cb0ae38a777fe 100644
--- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
+++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
@@ -21,6 +21,7 @@ properties:
           - qcom,qcs404-tcsr
           - qcom,sc7180-tcsr
           - qcom,sc7280-tcsr
+          - qcom,sc8280xp-tcsr
           - qcom,sdm630-tcsr
           - qcom,sdm845-tcsr
           - qcom,sm8150-tcsr
-- 
GitLab


From 4bef4d519b01cf15818b81a3fbf62d9f51612ad3 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Thu, 8 Sep 2022 10:09:38 +0200
Subject: [PATCH 253/875] dt-bindings: mfd: qcom,spmi-pmic: Use generic node
 name "gpio"

GPIO controller nodes are named by convention just "gpio", not "gpios".

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20220908080938.29199-3-krzysztof.kozlowski@linaro.org
---
 Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
index 777f2da52f1ed..c8362efd43454 100644
--- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
+++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
@@ -119,7 +119,7 @@ patternProperties:
     type: object
     $ref: /schemas/extcon/qcom,pm8941-misc.yaml#
 
-  "gpio(s)?@[0-9a-f]+$":
+  "gpio@[0-9a-f]+$":
     type: object
     $ref: /schemas/pinctrl/qcom,pmic-gpio.yaml#
 
@@ -199,7 +199,7 @@ examples:
             #address-cells = <1>;
             #size-cells = <0>;
 
-            pmi8998_gpio: gpios@c000 {
+            pmi8998_gpio: gpio@c000 {
                 compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio";
                 reg = <0xc000>;
                 gpio-controller;
@@ -284,7 +284,7 @@ examples:
             };
         };
 
-        pm6150_gpio: gpios@c000 {
+        pm6150_gpio: gpio@c000 {
             compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio";
             reg = <0xc000>;
             gpio-controller;
-- 
GitLab


From 5f4f94e9f26cca6514474b307b59348b8485e711 Mon Sep 17 00:00:00 2001
From: ChiYuan Huang <cy_huang@richtek.com>
Date: Thu, 29 Sep 2022 10:00:17 +0800
Subject: [PATCH 254/875] mfd: mt6360: Add bounds checking in Regmap read/write
 call-backs

Fix the potential risk of OOB read if bank index is over the maximum.

Refer to the discussion list for the experiment result on mt6370.
https://lore.kernel.org/all/20220914013345.GA5802@cyhuang-hp-elitebook-840-g3.rt/
If not to check the bound, there is the same issue on mt6360.

Cc: stable@vger.kernel.org
Fixes: 3b0850440a06c (mfd: mt6360: Merge different sub-devices I2C read/write)
Signed-off-by: ChiYuan Huang <cy_huang@richtek.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/1664416817-31590-1-git-send-email-u0084500@gmail.com
---
 drivers/mfd/mt6360-core.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/mfd/mt6360-core.c b/drivers/mfd/mt6360-core.c
index 6eaa6775b8885..d3b32eb798377 100644
--- a/drivers/mfd/mt6360-core.c
+++ b/drivers/mfd/mt6360-core.c
@@ -402,7 +402,7 @@ static int mt6360_regmap_read(void *context, const void *reg, size_t reg_size,
 	struct mt6360_ddata *ddata = context;
 	u8 bank = *(u8 *)reg;
 	u8 reg_addr = *(u8 *)(reg + 1);
-	struct i2c_client *i2c = ddata->i2c[bank];
+	struct i2c_client *i2c;
 	bool crc_needed = false;
 	u8 *buf;
 	int buf_len = MT6360_ALLOC_READ_SIZE(val_size);
@@ -410,6 +410,11 @@ static int mt6360_regmap_read(void *context, const void *reg, size_t reg_size,
 	u8 crc;
 	int ret;
 
+	if (bank >= MT6360_SLAVE_MAX)
+		return -EINVAL;
+
+	i2c = ddata->i2c[bank];
+
 	if (bank == MT6360_SLAVE_PMIC || bank == MT6360_SLAVE_LDO) {
 		crc_needed = true;
 		ret = mt6360_xlate_pmicldo_addr(&reg_addr, val_size);
@@ -453,13 +458,18 @@ static int mt6360_regmap_write(void *context, const void *val, size_t val_size)
 	struct mt6360_ddata *ddata = context;
 	u8 bank = *(u8 *)val;
 	u8 reg_addr = *(u8 *)(val + 1);
-	struct i2c_client *i2c = ddata->i2c[bank];
+	struct i2c_client *i2c;
 	bool crc_needed = false;
 	u8 *buf;
 	int buf_len = MT6360_ALLOC_WRITE_SIZE(val_size);
 	int write_size = val_size - MT6360_REGMAP_REG_BYTE_SIZE;
 	int ret;
 
+	if (bank >= MT6360_SLAVE_MAX)
+		return -EINVAL;
+
+	i2c = ddata->i2c[bank];
+
 	if (bank == MT6360_SLAVE_PMIC || bank == MT6360_SLAVE_LDO) {
 		crc_needed = true;
 		ret = mt6360_xlate_pmicldo_addr(&reg_addr, val_size - MT6360_REGMAP_REG_BYTE_SIZE);
-- 
GitLab


From 118ee241c423636c03527eada8f672301514751e Mon Sep 17 00:00:00 2001
From: Fabien Parent <fparent@baylibre.com>
Date: Thu, 20 Oct 2022 18:20:45 +0200
Subject: [PATCH 255/875] dt-bindings: mfd: mt6397: Add binding for MT6357

Add binding documentation for the MT6357 PMIC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221005-mt6357-support-v3-1-7e0bd7c315b2@baylibre.com
---
 Documentation/devicetree/bindings/mfd/mt6397.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt
index 0088442efca1a..518986c44880f 100644
--- a/Documentation/devicetree/bindings/mfd/mt6397.txt
+++ b/Documentation/devicetree/bindings/mfd/mt6397.txt
@@ -21,6 +21,7 @@ Required properties:
 compatible:
 	"mediatek,mt6323" for PMIC MT6323
 	"mediatek,mt6331" for PMIC MT6331 and MT6332
+	"mediatek,mt6357" for PMIC MT6357
 	"mediatek,mt6358" for PMIC MT6358 and MT6366
 	"mediatek,mt6359" for PMIC MT6359
 	"mediatek,mt6397" for PMIC MT6397
-- 
GitLab


From fc45720334ebc9f97335a9ce67896811354f0a1c Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Wed, 19 Oct 2022 17:29:32 +0200
Subject: [PATCH 256/875] mfd: Remove dm355evm_msp driver

The DaVinci DM355EVM platform is gone after the removal of all
unused board files, so the MTD device along with its sub-devices
can be removed as well.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221019152947.3857217-7-arnd@kernel.org
---
 drivers/input/misc/Kconfig         |  11 -
 drivers/input/misc/Makefile        |   1 -
 drivers/input/misc/dm355evm_keys.c | 238 ---------------
 drivers/mfd/Kconfig                |   8 -
 drivers/mfd/Makefile               |   1 -
 drivers/mfd/dm355evm_msp.c         | 454 -----------------------------
 drivers/rtc/Kconfig                |   6 -
 drivers/rtc/Makefile               |   1 -
 drivers/rtc/rtc-dm355evm.c         | 151 ----------
 include/linux/mfd/dm355evm_msp.h   |  79 -----
 10 files changed, 950 deletions(-)
 delete mode 100644 drivers/input/misc/dm355evm_keys.c
 delete mode 100644 drivers/mfd/dm355evm_msp.c
 delete mode 100644 drivers/rtc/rtc-dm355evm.c
 delete mode 100644 include/linux/mfd/dm355evm_msp.h

diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index 9f088900f863b..540633b164d44 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -662,17 +662,6 @@ config INPUT_DA9063_ONKEY
 	  To compile this driver as a module, choose M here: the module
 	  will be called da9063_onkey.
 
-config INPUT_DM355EVM
-	tristate "TI DaVinci DM355 EVM Keypad and IR Remote"
-	depends on MFD_DM355EVM_MSP
-	select INPUT_SPARSEKMAP
-	help
-	  Supports the pushbuttons and IR remote used with
-	  the DM355 EVM board.
-
-	  To compile this driver as a module, choose M here: the
-	  module will be called dm355evm_keys.
-
 config INPUT_WM831X_ON
 	tristate "WM831X ON pin"
 	depends on MFD_WM831X
diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
index 6abefc41037b5..156f9c21f53b7 100644
--- a/drivers/input/misc/Makefile
+++ b/drivers/input/misc/Makefile
@@ -31,7 +31,6 @@ obj-$(CONFIG_INPUT_DA7280_HAPTICS)	+= da7280.o
 obj-$(CONFIG_INPUT_DA9052_ONKEY)	+= da9052_onkey.o
 obj-$(CONFIG_INPUT_DA9055_ONKEY)	+= da9055_onkey.o
 obj-$(CONFIG_INPUT_DA9063_ONKEY)	+= da9063_onkey.o
-obj-$(CONFIG_INPUT_DM355EVM)		+= dm355evm_keys.o
 obj-$(CONFIG_INPUT_E3X0_BUTTON)		+= e3x0-button.o
 obj-$(CONFIG_INPUT_DRV260X_HAPTICS)	+= drv260x.o
 obj-$(CONFIG_INPUT_DRV2665_HAPTICS)	+= drv2665.o
diff --git a/drivers/input/misc/dm355evm_keys.c b/drivers/input/misc/dm355evm_keys.c
deleted file mode 100644
index 397ca7c787cc1..0000000000000
--- a/drivers/input/misc/dm355evm_keys.c
+++ /dev/null
@@ -1,238 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * dm355evm_keys.c - support buttons and IR remote on DM355 EVM board
- *
- * Copyright (c) 2008 by David Brownell
- */
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/input.h>
-#include <linux/input/sparse-keymap.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-
-#include <linux/mfd/dm355evm_msp.h>
-#include <linux/module.h>
-
-
-/*
- * The MSP430 firmware on the DM355 EVM monitors on-board pushbuttons
- * and an IR receptor used for the remote control.  When any key is
- * pressed, or its autorepeat kicks in, an event is sent.  This driver
- * read those events from the small (32 event) queue and reports them.
- *
- * Note that physically there can only be one of these devices.
- *
- * This driver was tested with firmware revision A4.
- */
-struct dm355evm_keys {
-	struct input_dev	*input;
-	struct device		*dev;
-};
-
-/* These initial keycodes can be remapped */
-static const struct key_entry dm355evm_keys[] = {
-	/*
-	 * Pushbuttons on the EVM board ... note that the labels for these
-	 * are SW10/SW11/etc on the PC board.  The left/right orientation
-	 * comes only from the firmware's documentation, and presumes the
-	 * power connector is immediately in front of you and the IR sensor
-	 * is to the right.  (That is, rotate the board counter-clockwise
-	 * by 90 degrees from the SW10/etc and "DM355 EVM" labels.)
-	 */
-	{ KE_KEY, 0x00d8, { KEY_OK } },		/* SW12 */
-	{ KE_KEY, 0x00b8, { KEY_UP } },		/* SW13 */
-	{ KE_KEY, 0x00e8, { KEY_DOWN } },	/* SW11 */
-	{ KE_KEY, 0x0078, { KEY_LEFT } },	/* SW14 */
-	{ KE_KEY, 0x00f0, { KEY_RIGHT } },	/* SW10 */
-
-	/*
-	 * IR buttons ... codes assigned to match the universal remote
-	 * provided with the EVM (Philips PM4S) using DVD code 0020.
-	 *
-	 * These event codes match firmware documentation, but other
-	 * remote controls could easily send more RC5-encoded events.
-	 * The PM4S manual was used in several cases to help select
-	 * a keycode reflecting the intended usage.
-	 *
-	 * RC5 codes are 14 bits, with two start bits (0x3 prefix)
-	 * and a toggle bit (masked out below).
-	 */
-	{ KE_KEY, 0x300c, { KEY_POWER } },	/* NOTE: docs omit this */
-	{ KE_KEY, 0x3000, { KEY_NUMERIC_0 } },
-	{ KE_KEY, 0x3001, { KEY_NUMERIC_1 } },
-	{ KE_KEY, 0x3002, { KEY_NUMERIC_2 } },
-	{ KE_KEY, 0x3003, { KEY_NUMERIC_3 } },
-	{ KE_KEY, 0x3004, { KEY_NUMERIC_4 } },
-	{ KE_KEY, 0x3005, { KEY_NUMERIC_5 } },
-	{ KE_KEY, 0x3006, { KEY_NUMERIC_6 } },
-	{ KE_KEY, 0x3007, { KEY_NUMERIC_7 } },
-	{ KE_KEY, 0x3008, { KEY_NUMERIC_8 } },
-	{ KE_KEY, 0x3009, { KEY_NUMERIC_9 } },
-	{ KE_KEY, 0x3022, { KEY_ENTER } },
-	{ KE_KEY, 0x30ec, { KEY_MODE } },	/* "tv/vcr/..." */
-	{ KE_KEY, 0x300f, { KEY_SELECT } },	/* "info" */
-	{ KE_KEY, 0x3020, { KEY_CHANNELUP } },	/* "up" */
-	{ KE_KEY, 0x302e, { KEY_MENU } },	/* "in/out" */
-	{ KE_KEY, 0x3011, { KEY_VOLUMEDOWN } },	/* "left" */
-	{ KE_KEY, 0x300d, { KEY_MUTE } },	/* "ok" */
-	{ KE_KEY, 0x3010, { KEY_VOLUMEUP } },	/* "right" */
-	{ KE_KEY, 0x301e, { KEY_SUBTITLE } },	/* "cc" */
-	{ KE_KEY, 0x3021, { KEY_CHANNELDOWN } },/* "down" */
-	{ KE_KEY, 0x3022, { KEY_PREVIOUS } },
-	{ KE_KEY, 0x3026, { KEY_SLEEP } },
-	{ KE_KEY, 0x3172, { KEY_REWIND } },	/* NOTE: docs wrongly say 0x30ca */
-	{ KE_KEY, 0x3175, { KEY_PLAY } },
-	{ KE_KEY, 0x3174, { KEY_FASTFORWARD } },
-	{ KE_KEY, 0x3177, { KEY_RECORD } },
-	{ KE_KEY, 0x3176, { KEY_STOP } },
-	{ KE_KEY, 0x3169, { KEY_PAUSE } },
-};
-
-/*
- * Because we communicate with the MSP430 using I2C, and all I2C calls
- * in Linux sleep, we use a threaded IRQ handler.  The IRQ itself is
- * active low, but we go through the GPIO controller so we can trigger
- * on falling edges and not worry about enabling/disabling the IRQ in
- * the keypress handling path.
- */
-static irqreturn_t dm355evm_keys_irq(int irq, void *_keys)
-{
-	static u16 last_event;
-	struct dm355evm_keys *keys = _keys;
-	const struct key_entry *ke;
-	unsigned int keycode;
-	int status;
-	u16 event;
-
-	/* For simplicity we ignore INPUT_COUNT and just read
-	 * events until we get the "queue empty" indicator.
-	 * Reading INPUT_LOW decrements the count.
-	 */
-	for (;;) {
-		status = dm355evm_msp_read(DM355EVM_MSP_INPUT_HIGH);
-		if (status < 0) {
-			dev_dbg(keys->dev, "input high err %d\n",
-					status);
-			break;
-		}
-		event = status << 8;
-
-		status = dm355evm_msp_read(DM355EVM_MSP_INPUT_LOW);
-		if (status < 0) {
-			dev_dbg(keys->dev, "input low err %d\n",
-					status);
-			break;
-		}
-		event |= status;
-		if (event == 0xdead)
-			break;
-
-		/* Press and release a button:  two events, same code.
-		 * Press and hold (autorepeat), then release: N events
-		 * (N > 2), same code.  For RC5 buttons the toggle bits
-		 * distinguish (for example) "1-autorepeat" from "1 1";
-		 * but PCB buttons don't support that bit.
-		 *
-		 * So we must synthesize release events.  We do that by
-		 * mapping events to a press/release event pair; then
-		 * to avoid adding extra events, skip the second event
-		 * of each pair.
-		 */
-		if (event == last_event) {
-			last_event = 0;
-			continue;
-		}
-		last_event = event;
-
-		/* ignore the RC5 toggle bit */
-		event &= ~0x0800;
-
-		/* find the key, or report it as unknown */
-		ke = sparse_keymap_entry_from_scancode(keys->input, event);
-		keycode = ke ? ke->keycode : KEY_UNKNOWN;
-		dev_dbg(keys->dev,
-			"input event 0x%04x--> keycode %d\n",
-			event, keycode);
-
-		/* report press + release */
-		input_report_key(keys->input, keycode, 1);
-		input_sync(keys->input);
-		input_report_key(keys->input, keycode, 0);
-		input_sync(keys->input);
-	}
-
-	return IRQ_HANDLED;
-}
-
-/*----------------------------------------------------------------------*/
-
-static int dm355evm_keys_probe(struct platform_device *pdev)
-{
-	struct dm355evm_keys	*keys;
-	struct input_dev	*input;
-	int			irq;
-	int			error;
-
-	keys = devm_kzalloc(&pdev->dev, sizeof (*keys), GFP_KERNEL);
-	if (!keys)
-		return -ENOMEM;
-
-	input = devm_input_allocate_device(&pdev->dev);
-	if (!input)
-		return -ENOMEM;
-
-	keys->dev = &pdev->dev;
-	keys->input = input;
-
-	input->name = "DM355 EVM Controls";
-	input->phys = "dm355evm/input0";
-
-	input->id.bustype = BUS_I2C;
-	input->id.product = 0x0355;
-	input->id.version = dm355evm_msp_read(DM355EVM_MSP_FIRMREV);
-
-	error = sparse_keymap_setup(input, dm355evm_keys, NULL);
-	if (error)
-		return error;
-
-	/* REVISIT:  flush the event queue? */
-
-	/* set up "threaded IRQ handler" */
-	irq = platform_get_irq(pdev, 0);
-	if (irq < 0)
-		return irq;
-
-	error = devm_request_threaded_irq(&pdev->dev, irq,
-					  NULL, dm355evm_keys_irq,
-					  IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
-					  dev_name(&pdev->dev), keys);
-	if (error)
-		return error;
-
-	/* register */
-	error = input_register_device(input);
-	if (error)
-		return error;
-
-	return 0;
-}
-
-/* REVISIT:  add suspend/resume when DaVinci supports it.  The IRQ should
- * be able to wake up the system.  When device_may_wakeup(&pdev->dev), call
- * enable_irq_wake() on suspend, and disable_irq_wake() on resume.
- */
-
-/*
- * I2C is used to talk to the MSP430, but this platform device is
- * exposed by an MFD driver that manages I2C communications.
- */
-static struct platform_driver dm355evm_keys_driver = {
-	.probe		= dm355evm_keys_probe,
-	.driver		= {
-		.name	= "dm355evm_keys",
-	},
-};
-module_platform_driver(dm355evm_keys_driver);
-
-MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 9e77f47629994..20613a5648c1f 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1460,14 +1460,6 @@ config MFD_TI_AM335X_TSCADC
 	  To compile this driver as a module, choose M here: the
 	  module will be called ti_am335x_tscadc.
 
-config MFD_DM355EVM_MSP
-	bool "TI DaVinci DM355 EVM microcontroller"
-	depends on I2C=y && MACH_DAVINCI_DM355_EVM
-	help
-	  This driver supports the MSP430 microcontroller used on these
-	  boards.  MSP430 firmware manages resets and power sequencing,
-	  inputs from buttons and the IR remote, LEDs, an RTC, and more.
-
 config MFD_LP3943
 	tristate "TI/National Semiconductor LP3943 MFD Driver"
 	depends on I2C
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 9387c3ddab4e5..6bfe2012e071c 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -25,7 +25,6 @@ obj-$(CONFIG_MFD_TI_LP873X)	+= lp873x.o
 obj-$(CONFIG_MFD_TI_LP87565)	+= lp87565.o
 
 obj-$(CONFIG_MFD_DAVINCI_VOICECODEC)	+= davinci_voicecodec.o
-obj-$(CONFIG_MFD_DM355EVM_MSP)	+= dm355evm_msp.o
 obj-$(CONFIG_MFD_TI_AM335X_TSCADC)	+= ti_am335x_tscadc.o
 
 obj-$(CONFIG_MFD_STA2X11)	+= sta2x11-mfd.o
diff --git a/drivers/mfd/dm355evm_msp.c b/drivers/mfd/dm355evm_msp.c
deleted file mode 100644
index 759c596906801..0000000000000
--- a/drivers/mfd/dm355evm_msp.c
+++ /dev/null
@@ -1,454 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * dm355evm_msp.c - driver for MSP430 firmware on DM355EVM board
- *
- * Copyright (C) 2008 David Brownell
- */
-
-#include <linux/init.h>
-#include <linux/mutex.h>
-#include <linux/platform_device.h>
-#include <linux/clk.h>
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/leds.h>
-#include <linux/i2c.h>
-#include <linux/mfd/dm355evm_msp.h>
-
-
-/*
- * The DM355 is a DaVinci chip with video support but no C64+ DSP.  Its
- * EVM board has an MSP430 programmed with firmware for various board
- * support functions.  This driver exposes some of them directly, and
- * supports other drivers (e.g. RTC, input) for more complex access.
- *
- * Because this firmware is entirely board-specific, this file embeds
- * knowledge that would be passed as platform_data in a generic driver.
- *
- * This driver was tested with firmware revision A4.
- */
-
-#if IS_ENABLED(CONFIG_INPUT_DM355EVM)
-#define msp_has_keyboard()	true
-#else
-#define msp_has_keyboard()	false
-#endif
-
-#if IS_ENABLED(CONFIG_LEDS_GPIO)
-#define msp_has_leds()		true
-#else
-#define msp_has_leds()		false
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_DM355EVM)
-#define msp_has_rtc()		true
-#else
-#define msp_has_rtc()		false
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_TVP514X)
-#define msp_has_tvp()		true
-#else
-#define msp_has_tvp()		false
-#endif
-
-
-/*----------------------------------------------------------------------*/
-
-/* REVISIT for paranoia's sake, retry reads/writes on error */
-
-static struct i2c_client *msp430;
-
-/**
- * dm355evm_msp_write - Writes a register in dm355evm_msp
- * @value: the value to be written
- * @reg: register address
- *
- * Returns result of operation - 0 is success, else negative errno
- */
-int dm355evm_msp_write(u8 value, u8 reg)
-{
-	return i2c_smbus_write_byte_data(msp430, reg, value);
-}
-EXPORT_SYMBOL(dm355evm_msp_write);
-
-/**
- * dm355evm_msp_read - Reads a register from dm355evm_msp
- * @reg: register address
- *
- * Returns result of operation - value, or negative errno
- */
-int dm355evm_msp_read(u8 reg)
-{
-	return i2c_smbus_read_byte_data(msp430, reg);
-}
-EXPORT_SYMBOL(dm355evm_msp_read);
-
-/*----------------------------------------------------------------------*/
-
-/*
- * Many of the msp430 pins are just used as fixed-direction GPIOs.
- * We could export a few more of them this way, if we wanted.
- */
-#define MSP_GPIO(bit, reg)	((DM355EVM_MSP_ ## reg) << 3 | (bit))
-
-static const u8 msp_gpios[] = {
-	/* eight leds */
-	MSP_GPIO(0, LED), MSP_GPIO(1, LED),
-	MSP_GPIO(2, LED), MSP_GPIO(3, LED),
-	MSP_GPIO(4, LED), MSP_GPIO(5, LED),
-	MSP_GPIO(6, LED), MSP_GPIO(7, LED),
-	/* SW6 and the NTSC/nPAL jumper */
-	MSP_GPIO(0, SWITCH1), MSP_GPIO(1, SWITCH1),
-	MSP_GPIO(2, SWITCH1), MSP_GPIO(3, SWITCH1),
-	MSP_GPIO(4, SWITCH1),
-	/* switches on MMC/SD sockets */
-	/*
-	 * Note: EVMDM355_ECP_VA4.pdf suggests that Bit 2 and 4 should be
-	 * checked for card detection. However on the EVM bit 1 and 3 gives
-	 * this status, for 0 and 1 instance respectively. The pdf also
-	 * suggests that Bit 1 and 3 should be checked for write protection.
-	 * However on the EVM bit 2 and 4 gives this status,for 0 and 1
-	 * instance respectively.
-	 */
-	MSP_GPIO(2, SDMMC), MSP_GPIO(1, SDMMC),	/* mmc0 WP, nCD */
-	MSP_GPIO(4, SDMMC), MSP_GPIO(3, SDMMC),	/* mmc1 WP, nCD */
-};
-
-static struct gpio_led evm_leds[] = {
-	{ .name = "dm355evm::ds14",
-	  .default_trigger = "heartbeat", },
-	{ .name = "dm355evm::ds15",
-	  .default_trigger = "mmc0", },
-	{ .name = "dm355evm::ds16",
-	  /* could also be a CE-ATA drive */
-	  .default_trigger = "mmc1", },
-	{ .name = "dm355evm::ds17",
-	  .default_trigger = "nand-disk", },
-	{ .name = "dm355evm::ds18", },
-	{ .name = "dm355evm::ds19", },
-	{ .name = "dm355evm::ds20", },
-	{ .name = "dm355evm::ds21", },
-};
-
-static struct gpio_led_platform_data evm_led_data = {
-	.num_leds	= ARRAY_SIZE(evm_leds),
-	.leds		= evm_leds,
-};
-
-static struct gpiod_lookup_table evm_leds_gpio_table = {
-	.dev_id = "leds-gpio",
-	.table = {
-		/*
-		 * These GPIOs are on the dm355evm_msp
-		 * GPIO chip at index 0..7
-		 */
-		GPIO_LOOKUP_IDX("dm355evm_msp", 0, NULL,
-				0, GPIO_ACTIVE_LOW),
-		GPIO_LOOKUP_IDX("dm355evm_msp", 1, NULL,
-				1, GPIO_ACTIVE_LOW),
-		GPIO_LOOKUP_IDX("dm355evm_msp", 2, NULL,
-				2, GPIO_ACTIVE_LOW),
-		GPIO_LOOKUP_IDX("dm355evm_msp", 3, NULL,
-				3, GPIO_ACTIVE_LOW),
-		GPIO_LOOKUP_IDX("dm355evm_msp", 4, NULL,
-				4, GPIO_ACTIVE_LOW),
-		GPIO_LOOKUP_IDX("dm355evm_msp", 5, NULL,
-				5, GPIO_ACTIVE_LOW),
-		GPIO_LOOKUP_IDX("dm355evm_msp", 6, NULL,
-				6, GPIO_ACTIVE_LOW),
-		GPIO_LOOKUP_IDX("dm355evm_msp", 7, NULL,
-				7, GPIO_ACTIVE_LOW),
-		{ },
-	},
-};
-
-#define MSP_GPIO_REG(offset)	(msp_gpios[(offset)] >> 3)
-#define MSP_GPIO_MASK(offset)	BIT(msp_gpios[(offset)] & 0x07)
-
-static int msp_gpio_in(struct gpio_chip *chip, unsigned offset)
-{
-	switch (MSP_GPIO_REG(offset)) {
-	case DM355EVM_MSP_SWITCH1:
-	case DM355EVM_MSP_SWITCH2:
-	case DM355EVM_MSP_SDMMC:
-		return 0;
-	default:
-		return -EINVAL;
-	}
-}
-
-static u8 msp_led_cache;
-
-static int msp_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
-	int reg, status;
-
-	reg = MSP_GPIO_REG(offset);
-	status = dm355evm_msp_read(reg);
-	if (status < 0)
-		return status;
-	if (reg == DM355EVM_MSP_LED)
-		msp_led_cache = status;
-	return !!(status & MSP_GPIO_MASK(offset));
-}
-
-static int msp_gpio_out(struct gpio_chip *chip, unsigned offset, int value)
-{
-	int mask, bits;
-
-	/* NOTE:  there are some other signals that could be
-	 * packaged as output GPIOs, but they aren't as useful
-	 * as the LEDs ... so for now we don't.
-	 */
-	if (MSP_GPIO_REG(offset) != DM355EVM_MSP_LED)
-		return -EINVAL;
-
-	mask = MSP_GPIO_MASK(offset);
-	bits = msp_led_cache;
-
-	bits &= ~mask;
-	if (value)
-		bits |= mask;
-	msp_led_cache = bits;
-
-	return dm355evm_msp_write(bits, DM355EVM_MSP_LED);
-}
-
-static void msp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
-	msp_gpio_out(chip, offset, value);
-}
-
-static struct gpio_chip dm355evm_msp_gpio = {
-	.label			= "dm355evm_msp",
-	.owner			= THIS_MODULE,
-	.direction_input	= msp_gpio_in,
-	.get			= msp_gpio_get,
-	.direction_output	= msp_gpio_out,
-	.set			= msp_gpio_set,
-	.base			= -EINVAL,		/* dynamic assignment */
-	.ngpio			= ARRAY_SIZE(msp_gpios),
-	.can_sleep		= true,
-};
-
-/*----------------------------------------------------------------------*/
-
-static struct device *add_child(struct i2c_client *client, const char *name,
-		void *pdata, unsigned pdata_len,
-		bool can_wakeup, int irq)
-{
-	struct platform_device	*pdev;
-	int			status;
-
-	pdev = platform_device_alloc(name, -1);
-	if (!pdev)
-		return ERR_PTR(-ENOMEM);
-
-	device_init_wakeup(&pdev->dev, can_wakeup);
-	pdev->dev.parent = &client->dev;
-
-	if (pdata) {
-		status = platform_device_add_data(pdev, pdata, pdata_len);
-		if (status < 0) {
-			dev_dbg(&pdev->dev, "can't add platform_data\n");
-			goto put_device;
-		}
-	}
-
-	if (irq) {
-		struct resource r = {
-			.start = irq,
-			.flags = IORESOURCE_IRQ,
-		};
-
-		status = platform_device_add_resources(pdev, &r, 1);
-		if (status < 0) {
-			dev_dbg(&pdev->dev, "can't add irq\n");
-			goto put_device;
-		}
-	}
-
-	status = platform_device_add(pdev);
-	if (status)
-		goto put_device;
-
-	return &pdev->dev;
-
-put_device:
-	platform_device_put(pdev);
-	dev_err(&client->dev, "failed to add device %s\n", name);
-	return ERR_PTR(status);
-}
-
-static int add_children(struct i2c_client *client)
-{
-	static const struct {
-		int offset;
-		char *label;
-	} config_inputs[] = {
-		/* 8 == right after the LEDs */
-		{ 8 + 0, "sw6_1", },
-		{ 8 + 1, "sw6_2", },
-		{ 8 + 2, "sw6_3", },
-		{ 8 + 3, "sw6_4", },
-		{ 8 + 4, "NTSC/nPAL", },
-	};
-
-	struct device	*child;
-	int		status;
-	int		i;
-
-	/* GPIO-ish stuff */
-	dm355evm_msp_gpio.parent = &client->dev;
-	status = gpiochip_add_data(&dm355evm_msp_gpio, NULL);
-	if (status < 0)
-		return status;
-
-	/* LED output */
-	if (msp_has_leds()) {
-		gpiod_add_lookup_table(&evm_leds_gpio_table);
-		/* NOTE:  these are the only fully programmable LEDs
-		 * on the board, since GPIO-61/ds22 (and many signals
-		 * going to DC7) must be used for AEMIF address lines
-		 * unless the top 1 GB of NAND is unused...
-		 */
-		child = add_child(client, "leds-gpio",
-				&evm_led_data, sizeof(evm_led_data),
-				false, 0);
-		if (IS_ERR(child))
-			return PTR_ERR(child);
-	}
-
-	/* configuration inputs */
-	for (i = 0; i < ARRAY_SIZE(config_inputs); i++) {
-		int gpio = dm355evm_msp_gpio.base + config_inputs[i].offset;
-
-		gpio_request_one(gpio, GPIOF_IN, config_inputs[i].label);
-
-		/* make it easy for userspace to see these */
-		gpio_export(gpio, false);
-	}
-
-	/* MMC/SD inputs -- right after the last config input */
-	if (dev_get_platdata(&client->dev)) {
-		void (*mmcsd_setup)(unsigned) = dev_get_platdata(&client->dev);
-
-		mmcsd_setup(dm355evm_msp_gpio.base + 8 + 5);
-	}
-
-	/* RTC is a 32 bit counter, no alarm */
-	if (msp_has_rtc()) {
-		child = add_child(client, "rtc-dm355evm",
-				NULL, 0, false, 0);
-		if (IS_ERR(child))
-			return PTR_ERR(child);
-	}
-
-	/* input from buttons and IR remote (uses the IRQ) */
-	if (msp_has_keyboard()) {
-		child = add_child(client, "dm355evm_keys",
-				NULL, 0, true, client->irq);
-		if (IS_ERR(child))
-			return PTR_ERR(child);
-	}
-
-	return 0;
-}
-
-/*----------------------------------------------------------------------*/
-
-static void dm355evm_command(unsigned command)
-{
-	int status;
-
-	status = dm355evm_msp_write(command, DM355EVM_MSP_COMMAND);
-	if (status < 0)
-		dev_err(&msp430->dev, "command %d failure %d\n",
-				command, status);
-}
-
-static void dm355evm_power_off(void)
-{
-	dm355evm_command(MSP_COMMAND_POWEROFF);
-}
-
-static void dm355evm_msp_remove(struct i2c_client *client)
-{
-	pm_power_off = NULL;
-	msp430 = NULL;
-}
-
-static int
-dm355evm_msp_probe(struct i2c_client *client, const struct i2c_device_id *id)
-{
-	int		status;
-	const char	*video = msp_has_tvp() ? "TVP5146" : "imager";
-
-	if (msp430)
-		return -EBUSY;
-	msp430 = client;
-
-	/* display revision status; doubles as sanity check */
-	status = dm355evm_msp_read(DM355EVM_MSP_FIRMREV);
-	if (status < 0)
-		goto fail;
-	dev_info(&client->dev, "firmware v.%02X, %s as video-in\n",
-			status, video);
-
-	/* mux video input:  either tvp5146 or some external imager */
-	status = dm355evm_msp_write(msp_has_tvp() ? 0 : MSP_VIDEO_IMAGER,
-			DM355EVM_MSP_VIDEO_IN);
-	if (status < 0)
-		dev_warn(&client->dev, "error %d muxing %s as video-in\n",
-			status, video);
-
-	/* init LED cache, and turn off the LEDs */
-	msp_led_cache = 0xff;
-	dm355evm_msp_write(msp_led_cache, DM355EVM_MSP_LED);
-
-	/* export capabilities we support */
-	status = add_children(client);
-	if (status < 0)
-		goto fail;
-
-	/* PM hookup */
-	pm_power_off = dm355evm_power_off;
-
-	return 0;
-
-fail:
-	/* FIXME remove children ... */
-	dm355evm_msp_remove(client);
-	return status;
-}
-
-static const struct i2c_device_id dm355evm_msp_ids[] = {
-	{ "dm355evm_msp", 0 },
-	{ /* end of list */ },
-};
-MODULE_DEVICE_TABLE(i2c, dm355evm_msp_ids);
-
-static struct i2c_driver dm355evm_msp_driver = {
-	.driver.name	= "dm355evm_msp",
-	.id_table	= dm355evm_msp_ids,
-	.probe		= dm355evm_msp_probe,
-	.remove		= dm355evm_msp_remove,
-};
-
-static int __init dm355evm_msp_init(void)
-{
-	return i2c_add_driver(&dm355evm_msp_driver);
-}
-subsys_initcall(dm355evm_msp_init);
-
-static void __exit dm355evm_msp_exit(void)
-{
-	i2c_del_driver(&dm355evm_msp_driver);
-}
-module_exit(dm355evm_msp_exit);
-
-MODULE_DESCRIPTION("Interface to MSP430 firmware on DM355EVM");
-MODULE_LICENSE("GPL");
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index bb63edb507da4..35298c6517301 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -540,12 +540,6 @@ config RTC_DRV_BQ32K
 	  This driver can also be built as a module. If so, the module
 	  will be called rtc-bq32k.
 
-config RTC_DRV_DM355EVM
-	tristate "TI DaVinci DM355 EVM RTC"
-	depends on MFD_DM355EVM_MSP
-	help
-	  Supports the RTC firmware in the MSP430 on the DM355 EVM.
-
 config RTC_DRV_TWL92330
 	bool "TI TWL92330/Menelaus"
 	depends on MENELAUS
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index aab22bc634321..c2d474985919a 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -46,7 +46,6 @@ obj-$(CONFIG_RTC_DRV_DA9055)	+= rtc-da9055.o
 obj-$(CONFIG_RTC_DRV_DA9063)	+= rtc-da9063.o
 obj-$(CONFIG_RTC_DRV_DAVINCI)	+= rtc-davinci.o
 obj-$(CONFIG_RTC_DRV_DIGICOLOR)	+= rtc-digicolor.o
-obj-$(CONFIG_RTC_DRV_DM355EVM)	+= rtc-dm355evm.o
 obj-$(CONFIG_RTC_DRV_DS1216)	+= rtc-ds1216.o
 obj-$(CONFIG_RTC_DRV_DS1286)	+= rtc-ds1286.o
 obj-$(CONFIG_RTC_DRV_DS1302)	+= rtc-ds1302.o
diff --git a/drivers/rtc/rtc-dm355evm.c b/drivers/rtc/rtc-dm355evm.c
deleted file mode 100644
index 94fb16ac3e0fa..0000000000000
--- a/drivers/rtc/rtc-dm355evm.c
+++ /dev/null
@@ -1,151 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * rtc-dm355evm.c - access battery-backed counter in MSP430 firmware
- *
- * Copyright (c) 2008 by David Brownell
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/rtc.h>
-#include <linux/platform_device.h>
-
-#include <linux/mfd/dm355evm_msp.h>
-#include <linux/module.h>
-
-
-/*
- * The MSP430 firmware on the DM355 EVM uses a watch crystal to feed
- * a 1 Hz counter.  When a backup battery is supplied, that makes a
- * reasonable RTC for applications where alarms and non-NTP drift
- * compensation aren't important.
- *
- * The only real glitch is the inability to read or write all four
- * counter bytes atomically:  the count may increment in the middle
- * of an operation, causing trouble when the LSB rolls over.
- *
- * This driver was tested with firmware revision A4.
- */
-union evm_time {
-	u8	bytes[4];
-	u32	value;
-};
-
-static int dm355evm_rtc_read_time(struct device *dev, struct rtc_time *tm)
-{
-	union evm_time	time;
-	int		status;
-	int		tries = 0;
-
-	do {
-		/*
-		 * Read LSB(0) to MSB(3) bytes.  Defend against the counter
-		 * rolling over by re-reading until the value is stable,
-		 * and assuming the four reads take at most a few seconds.
-		 */
-		status = dm355evm_msp_read(DM355EVM_MSP_RTC_0);
-		if (status < 0)
-			return status;
-		if (tries && time.bytes[0] == status)
-			break;
-		time.bytes[0] = status;
-
-		status = dm355evm_msp_read(DM355EVM_MSP_RTC_1);
-		if (status < 0)
-			return status;
-		if (tries && time.bytes[1] == status)
-			break;
-		time.bytes[1] = status;
-
-		status = dm355evm_msp_read(DM355EVM_MSP_RTC_2);
-		if (status < 0)
-			return status;
-		if (tries && time.bytes[2] == status)
-			break;
-		time.bytes[2] = status;
-
-		status = dm355evm_msp_read(DM355EVM_MSP_RTC_3);
-		if (status < 0)
-			return status;
-		if (tries && time.bytes[3] == status)
-			break;
-		time.bytes[3] = status;
-
-	} while (++tries < 5);
-
-	dev_dbg(dev, "read timestamp %08x\n", time.value);
-
-	rtc_time64_to_tm(le32_to_cpu(time.value), tm);
-	return 0;
-}
-
-static int dm355evm_rtc_set_time(struct device *dev, struct rtc_time *tm)
-{
-	union evm_time	time;
-	unsigned long	value;
-	int		status;
-
-	value = rtc_tm_to_time64(tm);
-	time.value = cpu_to_le32(value);
-
-	dev_dbg(dev, "write timestamp %08x\n", time.value);
-
-	/*
-	 * REVISIT handle non-atomic writes ... maybe just retry until
-	 * byte[1] sticks (no rollover)?
-	 */
-	status = dm355evm_msp_write(time.bytes[0], DM355EVM_MSP_RTC_0);
-	if (status < 0)
-		return status;
-
-	status = dm355evm_msp_write(time.bytes[1], DM355EVM_MSP_RTC_1);
-	if (status < 0)
-		return status;
-
-	status = dm355evm_msp_write(time.bytes[2], DM355EVM_MSP_RTC_2);
-	if (status < 0)
-		return status;
-
-	status = dm355evm_msp_write(time.bytes[3], DM355EVM_MSP_RTC_3);
-	if (status < 0)
-		return status;
-
-	return 0;
-}
-
-static const struct rtc_class_ops dm355evm_rtc_ops = {
-	.read_time	= dm355evm_rtc_read_time,
-	.set_time	= dm355evm_rtc_set_time,
-};
-
-/*----------------------------------------------------------------------*/
-
-static int dm355evm_rtc_probe(struct platform_device *pdev)
-{
-	struct rtc_device *rtc;
-
-	rtc = devm_rtc_allocate_device(&pdev->dev);
-	if (IS_ERR(rtc))
-		return PTR_ERR(rtc);
-
-	platform_set_drvdata(pdev, rtc);
-
-	rtc->ops = &dm355evm_rtc_ops;
-	rtc->range_max = U32_MAX;
-
-	return devm_rtc_register_device(rtc);
-}
-
-/*
- * I2C is used to talk to the MSP430, but this platform device is
- * exposed by an MFD driver that manages I2C communications.
- */
-static struct platform_driver rtc_dm355evm_driver = {
-	.probe		= dm355evm_rtc_probe,
-	.driver		= {
-		.name	= "rtc-dm355evm",
-	},
-};
-
-module_platform_driver(rtc_dm355evm_driver);
-
-MODULE_LICENSE("GPL");
diff --git a/include/linux/mfd/dm355evm_msp.h b/include/linux/mfd/dm355evm_msp.h
deleted file mode 100644
index 372470350faba..0000000000000
--- a/include/linux/mfd/dm355evm_msp.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * dm355evm_msp.h - support MSP430 microcontroller on DM355EVM board
- */
-#ifndef __LINUX_I2C_DM355EVM_MSP
-#define __LINUX_I2C_DM355EVM_MSP
-
-/*
- * Written against Spectrum's writeup for the A4 firmware revision,
- * and tweaked to match source and rev D2 schematics by removing CPLD
- * and NOR flash hooks (which were last appropriate in rev B boards).
- *
- * Note that the firmware supports a flavor of write posting ... to be
- * sure a write completes, issue another read or write.
- */
-
-/* utilities to access "registers" emulated by msp430 firmware */
-extern int dm355evm_msp_write(u8 value, u8 reg);
-extern int dm355evm_msp_read(u8 reg);
-
-
-/* command/control registers */
-#define DM355EVM_MSP_COMMAND		0x00
-#	define MSP_COMMAND_NULL		0
-#	define MSP_COMMAND_RESET_COLD	1
-#	define MSP_COMMAND_RESET_WARM	2
-#	define MSP_COMMAND_RESET_WARM_I	3
-#	define MSP_COMMAND_POWEROFF	4
-#	define MSP_COMMAND_IR_REINIT	5
-#define DM355EVM_MSP_STATUS		0x01
-#	define MSP_STATUS_BAD_OFFSET	BIT(0)
-#	define MSP_STATUS_BAD_COMMAND	BIT(1)
-#	define MSP_STATUS_POWER_ERROR	BIT(2)
-#	define MSP_STATUS_RXBUF_OVERRUN	BIT(3)
-#define DM355EVM_MSP_RESET		0x02	/* 0 bits == in reset */
-#	define MSP_RESET_DC5		BIT(0)
-#	define MSP_RESET_TVP5154	BIT(2)
-#	define MSP_RESET_IMAGER		BIT(3)
-#	define MSP_RESET_ETHERNET	BIT(4)
-#	define MSP_RESET_SYS		BIT(5)
-#	define MSP_RESET_AIC33		BIT(7)
-
-/* GPIO registers ... bit patterns mostly match the source MSP ports */
-#define DM355EVM_MSP_LED		0x03	/* active low (MSP P4) */
-#define DM355EVM_MSP_SWITCH1		0x04	/* (MSP P5, masked) */
-#	define MSP_SWITCH1_SW6_1	BIT(0)
-#	define MSP_SWITCH1_SW6_2	BIT(1)
-#	define MSP_SWITCH1_SW6_3	BIT(2)
-#	define MSP_SWITCH1_SW6_4	BIT(3)
-#	define MSP_SWITCH1_J1		BIT(4)	/* NTSC/PAL */
-#	define MSP_SWITCH1_MSP_INT	BIT(5)	/* active low */
-#define DM355EVM_MSP_SWITCH2		0x05	/* (MSP P6, masked) */
-#	define MSP_SWITCH2_SW10		BIT(3)
-#	define MSP_SWITCH2_SW11		BIT(4)
-#	define MSP_SWITCH2_SW12		BIT(5)
-#	define MSP_SWITCH2_SW13		BIT(6)
-#	define MSP_SWITCH2_SW14		BIT(7)
-#define DM355EVM_MSP_SDMMC		0x06	/* (MSP P2, masked) */
-#	define MSP_SDMMC_0_WP		BIT(1)
-#	define MSP_SDMMC_0_CD		BIT(2)	/* active low */
-#	define MSP_SDMMC_1_WP		BIT(3)
-#	define MSP_SDMMC_1_CD		BIT(4)	/* active low */
-#define DM355EVM_MSP_FIRMREV		0x07	/* not a GPIO (out of order) */
-#define DM355EVM_MSP_VIDEO_IN		0x08	/* (MSP P3, masked) */
-#	define MSP_VIDEO_IMAGER		BIT(7)	/* low == tvp5146 */
-
-/* power supply registers are currently omitted */
-
-/* RTC registers */
-#define DM355EVM_MSP_RTC_0		0x12	/* LSB */
-#define DM355EVM_MSP_RTC_1		0x13
-#define DM355EVM_MSP_RTC_2		0x14
-#define DM355EVM_MSP_RTC_3		0x15	/* MSB */
-
-/* input event queue registers; code == ((HIGH << 8) | LOW) */
-#define DM355EVM_MSP_INPUT_COUNT	0x16	/* decrement by reading LOW */
-#define DM355EVM_MSP_INPUT_HIGH		0x17
-#define DM355EVM_MSP_INPUT_LOW		0x18
-
-#endif /* __LINUX_I2C_DM355EVM_MSP */
-- 
GitLab


From 67470bb7b30b87bebcfb798aedc77dc6519cc0a7 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Wed, 19 Oct 2022 17:29:36 +0200
Subject: [PATCH 257/875] mfd: Remove davinci voicecodec driver

The ASoC davinci voicecodec support is no longer used after
the removal of the dm3xx SoC platform, so the MFD driver is never
selected.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221019152947.3857217-11-arnd@kernel.org
---
 drivers/mfd/Kconfig              |   5 --
 drivers/mfd/Makefile             |   2 -
 drivers/mfd/davinci_voicecodec.c | 136 -------------------------------
 3 files changed, 143 deletions(-)
 delete mode 100644 drivers/mfd/davinci_voicecodec.c

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 20613a5648c1f..3bacbe1d06007 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1444,11 +1444,6 @@ config MFD_SYSCON
 	  Select this option to enable accessing system control registers
 	  via regmap.
 
-config MFD_DAVINCI_VOICECODEC
-	tristate
-	select MFD_CORE
-	select REGMAP_MMIO
-
 config MFD_TI_AM335X_TSCADC
 	tristate "TI ADC / Touch Screen chip support"
 	select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 6bfe2012e071c..86c51dc4ad6aa 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -23,8 +23,6 @@ obj-$(CONFIG_HTC_I2CPLD)	+= htc-i2cpld.o
 
 obj-$(CONFIG_MFD_TI_LP873X)	+= lp873x.o
 obj-$(CONFIG_MFD_TI_LP87565)	+= lp87565.o
-
-obj-$(CONFIG_MFD_DAVINCI_VOICECODEC)	+= davinci_voicecodec.o
 obj-$(CONFIG_MFD_TI_AM335X_TSCADC)	+= ti_am335x_tscadc.o
 
 obj-$(CONFIG_MFD_STA2X11)	+= sta2x11-mfd.o
diff --git a/drivers/mfd/davinci_voicecodec.c b/drivers/mfd/davinci_voicecodec.c
deleted file mode 100644
index 965820481f1e1..0000000000000
--- a/drivers/mfd/davinci_voicecodec.c
+++ /dev/null
@@ -1,136 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * DaVinci Voice Codec Core Interface for TI platforms
- *
- * Copyright (C) 2010 Texas Instruments, Inc
- *
- * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/regmap.h>
-
-#include <sound/pcm.h>
-
-#include <linux/mfd/davinci_voicecodec.h>
-
-static const struct regmap_config davinci_vc_regmap = {
-	.reg_bits = 32,
-	.val_bits = 32,
-};
-
-static int __init davinci_vc_probe(struct platform_device *pdev)
-{
-	struct davinci_vc *davinci_vc;
-	struct resource *res;
-	struct mfd_cell *cell = NULL;
-	dma_addr_t fifo_base;
-	int ret;
-
-	davinci_vc = devm_kzalloc(&pdev->dev,
-				  sizeof(struct davinci_vc), GFP_KERNEL);
-	if (!davinci_vc)
-		return -ENOMEM;
-
-	davinci_vc->clk = devm_clk_get(&pdev->dev, NULL);
-	if (IS_ERR(davinci_vc->clk)) {
-		dev_dbg(&pdev->dev,
-			    "could not get the clock for voice codec\n");
-		return -ENODEV;
-	}
-	clk_enable(davinci_vc->clk);
-
-	davinci_vc->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
-	if (IS_ERR(davinci_vc->base)) {
-		ret = PTR_ERR(davinci_vc->base);
-		goto fail;
-	}
-	fifo_base = (dma_addr_t)res->start;
-
-	davinci_vc->regmap = devm_regmap_init_mmio(&pdev->dev,
-						   davinci_vc->base,
-						   &davinci_vc_regmap);
-	if (IS_ERR(davinci_vc->regmap)) {
-		ret = PTR_ERR(davinci_vc->regmap);
-		goto fail;
-	}
-
-	res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
-	if (!res) {
-		dev_err(&pdev->dev, "no DMA resource\n");
-		ret = -ENXIO;
-		goto fail;
-	}
-
-	davinci_vc->davinci_vcif.dma_tx_channel = res->start;
-	davinci_vc->davinci_vcif.dma_tx_addr = fifo_base + DAVINCI_VC_WFIFO;
-
-	res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
-	if (!res) {
-		dev_err(&pdev->dev, "no DMA resource\n");
-		ret = -ENXIO;
-		goto fail;
-	}
-
-	davinci_vc->davinci_vcif.dma_rx_channel = res->start;
-	davinci_vc->davinci_vcif.dma_rx_addr = fifo_base + DAVINCI_VC_RFIFO;
-
-	davinci_vc->dev = &pdev->dev;
-	davinci_vc->pdev = pdev;
-
-	/* Voice codec interface client */
-	cell = &davinci_vc->cells[DAVINCI_VC_VCIF_CELL];
-	cell->name = "davinci-vcif";
-	cell->platform_data = davinci_vc;
-	cell->pdata_size = sizeof(*davinci_vc);
-
-	/* Voice codec CQ93VC client */
-	cell = &davinci_vc->cells[DAVINCI_VC_CQ93VC_CELL];
-	cell->name = "cq93vc-codec";
-	cell->platform_data = davinci_vc;
-	cell->pdata_size = sizeof(*davinci_vc);
-
-	ret = mfd_add_devices(&pdev->dev, pdev->id, davinci_vc->cells,
-			      DAVINCI_VC_CELLS, NULL, 0, NULL);
-	if (ret != 0) {
-		dev_err(&pdev->dev, "fail to register client devices\n");
-		goto fail;
-	}
-
-	return 0;
-
-fail:
-	clk_disable(davinci_vc->clk);
-
-	return ret;
-}
-
-static int davinci_vc_remove(struct platform_device *pdev)
-{
-	struct davinci_vc *davinci_vc = platform_get_drvdata(pdev);
-
-	mfd_remove_devices(&pdev->dev);
-
-	clk_disable(davinci_vc->clk);
-
-	return 0;
-}
-
-static struct platform_driver davinci_vc_driver = {
-	.driver	= {
-		.name = "davinci_voicecodec",
-	},
-	.remove	= davinci_vc_remove,
-};
-
-module_platform_driver_probe(davinci_vc_driver, davinci_vc_probe);
-
-MODULE_AUTHOR("Miguel Aguilar");
-MODULE_DESCRIPTION("Texas Instruments DaVinci Voice Codec Core Interface");
-MODULE_LICENSE("GPL");
-- 
GitLab


From 707857d997ae39743eba939a5b3aaafbab04fa78 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Wed, 19 Oct 2022 17:03:39 +0200
Subject: [PATCH 258/875] mfd: Remove htc-i2cpld driver

The HTC Herald machine was removed, so this driver is no
longer used anywhere.

Cc: Cory Maccarrone <darkstar6262@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221019150410.3851944-17-arnd@kernel.org
---
 drivers/mfd/Kconfig      |   9 -
 drivers/mfd/Makefile     |   1 -
 drivers/mfd/htc-i2cpld.c | 627 ---------------------------------------
 include/linux/htcpld.h   |  23 --
 4 files changed, 660 deletions(-)
 delete mode 100644 drivers/mfd/htc-i2cpld.c
 delete mode 100644 include/linux/htcpld.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 3bacbe1d06007..f4a3415f72979 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -559,15 +559,6 @@ config HTC_PASIC3
 	  HTC Magician devices, respectively. Actual functionality is
 	  handled by the leds-pasic3 and ds1wm drivers.
 
-config HTC_I2CPLD
-	bool "HTC I2C PLD chip support"
-	depends on I2C=y && GPIOLIB
-	help
-	  If you say yes here you get support for the supposed CPLD
-	  found on omap850 HTC devices like the HTC Wizard and HTC Herald.
-	  This device provides input and output GPIOs through an I2C
-	  interface to one or more sub-chips.
-
 config MFD_INTEL_QUARK_I2C_GPIO
 	tristate "Intel Quark MFD I2C GPIO"
 	depends on PCI
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 86c51dc4ad6aa..4dd479212b3ab 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -19,7 +19,6 @@ obj-$(CONFIG_MFD_EXYNOS_LPASS)	+= exynos-lpass.o
 obj-$(CONFIG_MFD_GATEWORKS_GSC)	+= gateworks-gsc.o
 
 obj-$(CONFIG_HTC_PASIC3)	+= htc-pasic3.o
-obj-$(CONFIG_HTC_I2CPLD)	+= htc-i2cpld.o
 
 obj-$(CONFIG_MFD_TI_LP873X)	+= lp873x.o
 obj-$(CONFIG_MFD_TI_LP87565)	+= lp87565.o
diff --git a/drivers/mfd/htc-i2cpld.c b/drivers/mfd/htc-i2cpld.c
deleted file mode 100644
index b45b1346ab544..0000000000000
--- a/drivers/mfd/htc-i2cpld.c
+++ /dev/null
@@ -1,627 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- *  htc-i2cpld.c
- *  Chip driver for an unknown CPLD chip found on omap850 HTC devices like
- *  the HTC Wizard and HTC Herald.
- *  The cpld is located on the i2c bus and acts as an input/output GPIO
- *  extender.
- *
- *  Copyright (C) 2009 Cory Maccarrone <darkstar6262@gmail.com>
- *
- *  Based on work done in the linwizard project
- *  Copyright (C) 2008-2009 Angelo Arrifano <miknix@gmail.com>
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/spinlock.h>
-#include <linux/htcpld.h>
-#include <linux/gpio/driver.h>
-#include <linux/gpio/machine.h>
-#include <linux/gpio/consumer.h>
-#include <linux/slab.h>
-
-struct htcpld_chip {
-	spinlock_t              lock;
-
-	/* chip info */
-	u8                      reset;
-	u8                      addr;
-	struct device           *dev;
-	struct i2c_client	*client;
-
-	/* Output details */
-	u8                      cache_out;
-	struct gpio_chip        chip_out;
-
-	/* Input details */
-	u8                      cache_in;
-	struct gpio_chip        chip_in;
-
-	u16                     irqs_enabled;
-	uint                    irq_start;
-	int                     nirqs;
-
-	unsigned int		flow_type;
-	/*
-	 * Work structure to allow for setting values outside of any
-	 * possible interrupt context
-	 */
-	struct work_struct set_val_work;
-};
-
-struct htcpld_data {
-	/* irq info */
-	u16                irqs_enabled;
-	uint               irq_start;
-	int                nirqs;
-	uint               chained_irq;
-	struct gpio_desc   *int_reset_gpio_hi;
-	struct gpio_desc   *int_reset_gpio_lo;
-
-	/* htcpld info */
-	struct htcpld_chip *chip;
-	unsigned int       nchips;
-};
-
-/* There does not appear to be a way to proactively mask interrupts
- * on the htcpld chip itself.  So, we simply ignore interrupts that
- * aren't desired. */
-static void htcpld_mask(struct irq_data *data)
-{
-	struct htcpld_chip *chip = irq_data_get_irq_chip_data(data);
-	chip->irqs_enabled &= ~(1 << (data->irq - chip->irq_start));
-	pr_debug("HTCPLD mask %d %04x\n", data->irq, chip->irqs_enabled);
-}
-static void htcpld_unmask(struct irq_data *data)
-{
-	struct htcpld_chip *chip = irq_data_get_irq_chip_data(data);
-	chip->irqs_enabled |= 1 << (data->irq - chip->irq_start);
-	pr_debug("HTCPLD unmask %d %04x\n", data->irq, chip->irqs_enabled);
-}
-
-static int htcpld_set_type(struct irq_data *data, unsigned int flags)
-{
-	struct htcpld_chip *chip = irq_data_get_irq_chip_data(data);
-
-	if (flags & ~IRQ_TYPE_SENSE_MASK)
-		return -EINVAL;
-
-	/* We only allow edge triggering */
-	if (flags & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))
-		return -EINVAL;
-
-	chip->flow_type = flags;
-	return 0;
-}
-
-static struct irq_chip htcpld_muxed_chip = {
-	.name         = "htcpld",
-	.irq_mask     = htcpld_mask,
-	.irq_unmask   = htcpld_unmask,
-	.irq_set_type = htcpld_set_type,
-};
-
-/* To properly dispatch IRQ events, we need to read from the
- * chip.  This is an I2C action that could possibly sleep
- * (which is bad in interrupt context) -- so we use a threaded
- * interrupt handler to get around that.
- */
-static irqreturn_t htcpld_handler(int irq, void *dev)
-{
-	struct htcpld_data *htcpld = dev;
-	unsigned int i;
-	unsigned long flags;
-	int irqpin;
-
-	if (!htcpld) {
-		pr_debug("htcpld is null in ISR\n");
-		return IRQ_HANDLED;
-	}
-
-	/*
-	 * For each chip, do a read of the chip and trigger any interrupts
-	 * desired.  The interrupts will be triggered from LSB to MSB (i.e.
-	 * bit 0 first, then bit 1, etc.)
-	 *
-	 * For chips that have no interrupt range specified, just skip 'em.
-	 */
-	for (i = 0; i < htcpld->nchips; i++) {
-		struct htcpld_chip *chip = &htcpld->chip[i];
-		struct i2c_client *client;
-		int val;
-		unsigned long uval, old_val;
-
-		if (!chip) {
-			pr_debug("chip %d is null in ISR\n", i);
-			continue;
-		}
-
-		if (chip->nirqs == 0)
-			continue;
-
-		client = chip->client;
-		if (!client) {
-			pr_debug("client %d is null in ISR\n", i);
-			continue;
-		}
-
-		/* Scan the chip */
-		val = i2c_smbus_read_byte_data(client, chip->cache_out);
-		if (val < 0) {
-			/* Throw a warning and skip this chip */
-			dev_warn(chip->dev, "Unable to read from chip: %d\n",
-				 val);
-			continue;
-		}
-
-		uval = (unsigned long)val;
-
-		spin_lock_irqsave(&chip->lock, flags);
-
-		/* Save away the old value so we can compare it */
-		old_val = chip->cache_in;
-
-		/* Write the new value */
-		chip->cache_in = uval;
-
-		spin_unlock_irqrestore(&chip->lock, flags);
-
-		/*
-		 * For each bit in the data (starting at bit 0), trigger
-		 * associated interrupts.
-		 */
-		for (irqpin = 0; irqpin < chip->nirqs; irqpin++) {
-			unsigned oldb, newb, type = chip->flow_type;
-
-			irq = chip->irq_start + irqpin;
-
-			/* Run the IRQ handler, but only if the bit value
-			 * changed, and the proper flags are set */
-			oldb = (old_val >> irqpin) & 1;
-			newb = (uval >> irqpin) & 1;
-
-			if ((!oldb && newb && (type & IRQ_TYPE_EDGE_RISING)) ||
-			    (oldb && !newb && (type & IRQ_TYPE_EDGE_FALLING))) {
-				pr_debug("fire IRQ %d\n", irqpin);
-				generic_handle_irq(irq);
-			}
-		}
-	}
-
-	/*
-	 * In order to continue receiving interrupts, the int_reset_gpio must
-	 * be asserted.
-	 */
-	if (htcpld->int_reset_gpio_hi)
-		gpiod_set_value(htcpld->int_reset_gpio_hi, 1);
-	if (htcpld->int_reset_gpio_lo)
-		gpiod_set_value(htcpld->int_reset_gpio_lo, 0);
-
-	return IRQ_HANDLED;
-}
-
-/*
- * The GPIO set routines can be called from interrupt context, especially if,
- * for example they're attached to the led-gpio framework and a trigger is
- * enabled.  As such, we declared work above in the htcpld_chip structure,
- * and that work is scheduled in the set routine.  The kernel can then run
- * the I2C functions, which will sleep, in process context.
- */
-static void htcpld_chip_set(struct gpio_chip *chip, unsigned offset, int val)
-{
-	struct i2c_client *client;
-	struct htcpld_chip *chip_data = gpiochip_get_data(chip);
-	unsigned long flags;
-
-	client = chip_data->client;
-	if (!client)
-		return;
-
-	spin_lock_irqsave(&chip_data->lock, flags);
-	if (val)
-		chip_data->cache_out |= (1 << offset);
-	else
-		chip_data->cache_out &= ~(1 << offset);
-	spin_unlock_irqrestore(&chip_data->lock, flags);
-
-	schedule_work(&(chip_data->set_val_work));
-}
-
-static void htcpld_chip_set_ni(struct work_struct *work)
-{
-	struct htcpld_chip *chip_data;
-	struct i2c_client *client;
-
-	chip_data = container_of(work, struct htcpld_chip, set_val_work);
-	client = chip_data->client;
-	i2c_smbus_read_byte_data(client, chip_data->cache_out);
-}
-
-static int htcpld_chip_get(struct gpio_chip *chip, unsigned offset)
-{
-	struct htcpld_chip *chip_data = gpiochip_get_data(chip);
-	u8 cache;
-
-	if (!strncmp(chip->label, "htcpld-out", 10)) {
-		cache = chip_data->cache_out;
-	} else if (!strncmp(chip->label, "htcpld-in", 9)) {
-		cache = chip_data->cache_in;
-	} else
-		return -EINVAL;
-
-	return (cache >> offset) & 1;
-}
-
-static int htcpld_direction_output(struct gpio_chip *chip,
-					unsigned offset, int value)
-{
-	htcpld_chip_set(chip, offset, value);
-	return 0;
-}
-
-static int htcpld_direction_input(struct gpio_chip *chip,
-					unsigned offset)
-{
-	/*
-	 * No-op: this function can only be called on the input chip.
-	 * We do however make sure the offset is within range.
-	 */
-	return (offset < chip->ngpio) ? 0 : -EINVAL;
-}
-
-static int htcpld_chip_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-	struct htcpld_chip *chip_data = gpiochip_get_data(chip);
-
-	if (offset < chip_data->nirqs)
-		return chip_data->irq_start + offset;
-	else
-		return -EINVAL;
-}
-
-static void htcpld_chip_reset(struct i2c_client *client)
-{
-	struct htcpld_chip *chip_data = i2c_get_clientdata(client);
-	if (!chip_data)
-		return;
-
-	i2c_smbus_read_byte_data(
-		client, (chip_data->cache_out = chip_data->reset));
-}
-
-static int htcpld_setup_chip_irq(
-		struct platform_device *pdev,
-		int chip_index)
-{
-	struct htcpld_data *htcpld;
-	struct htcpld_chip *chip;
-	unsigned int irq, irq_end;
-
-	/* Get the platform and driver data */
-	htcpld = platform_get_drvdata(pdev);
-	chip = &htcpld->chip[chip_index];
-
-	/* Setup irq handlers */
-	irq_end = chip->irq_start + chip->nirqs;
-	for (irq = chip->irq_start; irq < irq_end; irq++) {
-		irq_set_chip_and_handler(irq, &htcpld_muxed_chip,
-					 handle_simple_irq);
-		irq_set_chip_data(irq, chip);
-		irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
-	}
-
-	return 0;
-}
-
-static int htcpld_register_chip_i2c(
-		struct platform_device *pdev,
-		int chip_index)
-{
-	struct htcpld_data *htcpld;
-	struct device *dev = &pdev->dev;
-	struct htcpld_core_platform_data *pdata;
-	struct htcpld_chip *chip;
-	struct htcpld_chip_platform_data *plat_chip_data;
-	struct i2c_adapter *adapter;
-	struct i2c_client *client;
-	struct i2c_board_info info;
-
-	/* Get the platform and driver data */
-	pdata = dev_get_platdata(dev);
-	htcpld = platform_get_drvdata(pdev);
-	chip = &htcpld->chip[chip_index];
-	plat_chip_data = &pdata->chip[chip_index];
-
-	adapter = i2c_get_adapter(pdata->i2c_adapter_id);
-	if (!adapter) {
-		/* Eek, no such I2C adapter!  Bail out. */
-		dev_warn(dev, "Chip at i2c address 0x%x: Invalid i2c adapter %d\n",
-			 plat_chip_data->addr, pdata->i2c_adapter_id);
-		return -ENODEV;
-	}
-
-	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_READ_BYTE_DATA)) {
-		dev_warn(dev, "i2c adapter %d non-functional\n",
-			 pdata->i2c_adapter_id);
-		i2c_put_adapter(adapter);
-		return -EINVAL;
-	}
-
-	memset(&info, 0, sizeof(struct i2c_board_info));
-	info.addr = plat_chip_data->addr;
-	strscpy(info.type, "htcpld-chip", I2C_NAME_SIZE);
-	info.platform_data = chip;
-
-	/* Add the I2C device.  This calls the probe() function. */
-	client = i2c_new_client_device(adapter, &info);
-	if (IS_ERR(client)) {
-		/* I2C device registration failed, contineu with the next */
-		dev_warn(dev, "Unable to add I2C device for 0x%x\n",
-			 plat_chip_data->addr);
-		i2c_put_adapter(adapter);
-		return PTR_ERR(client);
-	}
-
-	i2c_set_clientdata(client, chip);
-	snprintf(client->name, I2C_NAME_SIZE, "Chip_0x%x", client->addr);
-	chip->client = client;
-
-	/* Reset the chip */
-	htcpld_chip_reset(client);
-	chip->cache_in = i2c_smbus_read_byte_data(client, chip->cache_out);
-
-	return 0;
-}
-
-static void htcpld_unregister_chip_i2c(
-		struct platform_device *pdev,
-		int chip_index)
-{
-	struct htcpld_data *htcpld;
-	struct htcpld_chip *chip;
-
-	/* Get the platform and driver data */
-	htcpld = platform_get_drvdata(pdev);
-	chip = &htcpld->chip[chip_index];
-
-	i2c_unregister_device(chip->client);
-}
-
-static int htcpld_register_chip_gpio(
-		struct platform_device *pdev,
-		int chip_index)
-{
-	struct htcpld_data *htcpld;
-	struct device *dev = &pdev->dev;
-	struct htcpld_core_platform_data *pdata;
-	struct htcpld_chip *chip;
-	struct htcpld_chip_platform_data *plat_chip_data;
-	struct gpio_chip *gpio_chip;
-	int ret = 0;
-
-	/* Get the platform and driver data */
-	pdata = dev_get_platdata(dev);
-	htcpld = platform_get_drvdata(pdev);
-	chip = &htcpld->chip[chip_index];
-	plat_chip_data = &pdata->chip[chip_index];
-
-	/* Setup the GPIO chips */
-	gpio_chip = &(chip->chip_out);
-	gpio_chip->label           = "htcpld-out";
-	gpio_chip->parent             = dev;
-	gpio_chip->owner           = THIS_MODULE;
-	gpio_chip->get             = htcpld_chip_get;
-	gpio_chip->set             = htcpld_chip_set;
-	gpio_chip->direction_input = NULL;
-	gpio_chip->direction_output = htcpld_direction_output;
-	gpio_chip->base            = plat_chip_data->gpio_out_base;
-	gpio_chip->ngpio           = plat_chip_data->num_gpios;
-
-	gpio_chip = &(chip->chip_in);
-	gpio_chip->label           = "htcpld-in";
-	gpio_chip->parent             = dev;
-	gpio_chip->owner           = THIS_MODULE;
-	gpio_chip->get             = htcpld_chip_get;
-	gpio_chip->set             = NULL;
-	gpio_chip->direction_input = htcpld_direction_input;
-	gpio_chip->direction_output = NULL;
-	gpio_chip->to_irq          = htcpld_chip_to_irq;
-	gpio_chip->base            = plat_chip_data->gpio_in_base;
-	gpio_chip->ngpio           = plat_chip_data->num_gpios;
-
-	/* Add the GPIO chips */
-	ret = gpiochip_add_data(&(chip->chip_out), chip);
-	if (ret) {
-		dev_warn(dev, "Unable to register output GPIOs for 0x%x: %d\n",
-			 plat_chip_data->addr, ret);
-		return ret;
-	}
-
-	ret = gpiochip_add_data(&(chip->chip_in), chip);
-	if (ret) {
-		dev_warn(dev, "Unable to register input GPIOs for 0x%x: %d\n",
-			 plat_chip_data->addr, ret);
-		gpiochip_remove(&(chip->chip_out));
-		return ret;
-	}
-
-	return 0;
-}
-
-static int htcpld_setup_chips(struct platform_device *pdev)
-{
-	struct htcpld_data *htcpld;
-	struct device *dev = &pdev->dev;
-	struct htcpld_core_platform_data *pdata;
-	int i;
-
-	/* Get the platform and driver data */
-	pdata = dev_get_platdata(dev);
-	htcpld = platform_get_drvdata(pdev);
-
-	/* Setup each chip's output GPIOs */
-	htcpld->nchips = pdata->num_chip;
-	htcpld->chip = devm_kcalloc(dev,
-				    htcpld->nchips,
-				    sizeof(struct htcpld_chip),
-				    GFP_KERNEL);
-	if (!htcpld->chip)
-		return -ENOMEM;
-
-	/* Add the chips as best we can */
-	for (i = 0; i < htcpld->nchips; i++) {
-		int ret;
-
-		/* Setup the HTCPLD chips */
-		htcpld->chip[i].reset = pdata->chip[i].reset;
-		htcpld->chip[i].cache_out = pdata->chip[i].reset;
-		htcpld->chip[i].cache_in = 0;
-		htcpld->chip[i].dev = dev;
-		htcpld->chip[i].irq_start = pdata->chip[i].irq_base;
-		htcpld->chip[i].nirqs = pdata->chip[i].num_irqs;
-
-		INIT_WORK(&(htcpld->chip[i].set_val_work), &htcpld_chip_set_ni);
-		spin_lock_init(&(htcpld->chip[i].lock));
-
-		/* Setup the interrupts for the chip */
-		if (htcpld->chained_irq) {
-			ret = htcpld_setup_chip_irq(pdev, i);
-			if (ret)
-				continue;
-		}
-
-		/* Register the chip with I2C */
-		ret = htcpld_register_chip_i2c(pdev, i);
-		if (ret)
-			continue;
-
-
-		/* Register the chips with the GPIO subsystem */
-		ret = htcpld_register_chip_gpio(pdev, i);
-		if (ret) {
-			/* Unregister the chip from i2c and continue */
-			htcpld_unregister_chip_i2c(pdev, i);
-			continue;
-		}
-
-		dev_info(dev, "Registered chip at 0x%x\n", pdata->chip[i].addr);
-	}
-
-	return 0;
-}
-
-static int htcpld_core_probe(struct platform_device *pdev)
-{
-	struct htcpld_data *htcpld;
-	struct device *dev = &pdev->dev;
-	struct htcpld_core_platform_data *pdata;
-	struct resource *res;
-	int ret = 0;
-
-	if (!dev)
-		return -ENODEV;
-
-	pdata = dev_get_platdata(dev);
-	if (!pdata) {
-		dev_warn(dev, "Platform data not found for htcpld core!\n");
-		return -ENXIO;
-	}
-
-	htcpld = devm_kzalloc(dev, sizeof(struct htcpld_data), GFP_KERNEL);
-	if (!htcpld)
-		return -ENOMEM;
-
-	/* Find chained irq */
-	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-	if (res) {
-		int flags;
-		htcpld->chained_irq = res->start;
-
-		/* Setup the chained interrupt handler */
-		flags = IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
-			IRQF_ONESHOT;
-		ret = request_threaded_irq(htcpld->chained_irq,
-					   NULL, htcpld_handler,
-					   flags, pdev->name, htcpld);
-		if (ret) {
-			dev_warn(dev, "Unable to setup chained irq handler: %d\n", ret);
-			return ret;
-		} else
-			device_init_wakeup(dev, 0);
-	}
-
-	/* Set the driver data */
-	platform_set_drvdata(pdev, htcpld);
-
-	/* Setup the htcpld chips */
-	ret = htcpld_setup_chips(pdev);
-	if (ret)
-		return ret;
-
-	/* Request the GPIO(s) for the int reset and set them up */
-	htcpld->int_reset_gpio_hi = gpiochip_request_own_desc(&htcpld->chip[2].chip_out,
-							      7, "htcpld-core", GPIO_ACTIVE_HIGH,
-							      GPIOD_OUT_HIGH);
-	if (IS_ERR(htcpld->int_reset_gpio_hi)) {
-		/*
-		 * If it failed, that sucks, but we can probably
-		 * continue on without it.
-		 */
-		htcpld->int_reset_gpio_hi = NULL;
-		dev_warn(dev, "Unable to request int_reset_gpio_hi -- interrupts may not work\n");
-	}
-
-	htcpld->int_reset_gpio_lo = gpiochip_request_own_desc(&htcpld->chip[2].chip_out,
-							      0, "htcpld-core", GPIO_ACTIVE_HIGH,
-							      GPIOD_OUT_LOW);
-	if (IS_ERR(htcpld->int_reset_gpio_lo)) {
-		/*
-		 * If it failed, that sucks, but we can probably
-		 * continue on without it.
-		 */
-		htcpld->int_reset_gpio_lo = NULL;
-		dev_warn(dev, "Unable to request int_reset_gpio_lo -- interrupts may not work\n");
-	}
-
-	dev_info(dev, "Initialized successfully\n");
-	return 0;
-}
-
-/* The I2C Driver -- used internally */
-static const struct i2c_device_id htcpld_chip_id[] = {
-	{ "htcpld-chip", 0 },
-	{ }
-};
-
-static struct i2c_driver htcpld_chip_driver = {
-	.driver = {
-		.name	= "htcpld-chip",
-	},
-	.id_table = htcpld_chip_id,
-};
-
-/* The Core Driver */
-static struct platform_driver htcpld_core_driver = {
-	.driver = {
-		.name = "i2c-htcpld",
-	},
-};
-
-static int __init htcpld_core_init(void)
-{
-	int ret;
-
-	/* Register the I2C Chip driver */
-	ret = i2c_add_driver(&htcpld_chip_driver);
-	if (ret)
-		return ret;
-
-	/* Probe for our chips */
-	return platform_driver_probe(&htcpld_core_driver, htcpld_core_probe);
-}
-device_initcall(htcpld_core_init);
diff --git a/include/linux/htcpld.h b/include/linux/htcpld.h
deleted file mode 100644
index 5f8ac9b1d724c..0000000000000
--- a/include/linux/htcpld.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __LINUX_HTCPLD_H
-#define __LINUX_HTCPLD_H
-
-struct htcpld_chip_platform_data {
-	unsigned int addr;
-	unsigned int reset;
-	unsigned int num_gpios;
-	unsigned int gpio_out_base;
-	unsigned int gpio_in_base;
-	unsigned int irq_base;
-	unsigned int num_irqs;
-};
-
-struct htcpld_core_platform_data {
-	unsigned int                      i2c_adapter_id;
-
-	struct htcpld_chip_platform_data  *chip;
-	unsigned int                      num_chip;
-};
-
-#endif /* __LINUX_HTCPLD_H */
-
-- 
GitLab


From 5ed6cf8c0d55497f010c80fcf4c011e6febf9673 Mon Sep 17 00:00:00 2001
From: Matt Ranostay <mranostay@ti.com>
Date: Tue, 25 Oct 2022 01:00:14 -0700
Subject: [PATCH 259/875] dt-bindings: mfd: ti,am3359-tscadc: Add missing
 power-domains property

Add optional power-domains property to avoid the following dt-schema
failures:

tscadc@40200000: 'power-domains' does not match any of the regexes: 'pinctrl-[0-9]+'

Signed-off-by: Matt Ranostay <mranostay@ti.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221025080014.403457-1-mranostay@ti.com
---
 Documentation/devicetree/bindings/mfd/ti,am3359-tscadc.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/mfd/ti,am3359-tscadc.yaml b/Documentation/devicetree/bindings/mfd/ti,am3359-tscadc.yaml
index 34bf6a01436fa..23a63265be3c8 100644
--- a/Documentation/devicetree/bindings/mfd/ti,am3359-tscadc.yaml
+++ b/Documentation/devicetree/bindings/mfd/ti,am3359-tscadc.yaml
@@ -52,6 +52,9 @@ properties:
     type: object
     description: Magnetic reader
 
+  power-domains:
+    maxItems: 1
+
 required:
   - compatible
   - reg
-- 
GitLab


From d4b15e447c352ae74b18261bdaf0023fa9a7d1bd Mon Sep 17 00:00:00 2001
From: Guillaume La Roque <glaroque@baylibre.com>
Date: Wed, 26 Oct 2022 16:09:11 +0200
Subject: [PATCH 260/875] mfd: palmas: Add support of module build for Ti
 palmas chip

Modified Kconfig to enable module build support

Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Nicolas Frayer <nfrayer@baylibre.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221026140911.204776-1-nfrayer@baylibre.com
---
 drivers/mfd/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index f4a3415f72979..6e920442366c0 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1489,7 +1489,7 @@ config MFD_OMAP_USB_HOST
 	  OMAP USB Host drivers.
 
 config MFD_PALMAS
-	bool "TI Palmas series chips"
+	tristate "TI Palmas series chips"
 	select MFD_CORE
 	select REGMAP_I2C
 	select REGMAP_IRQ
-- 
GitLab


From 9f8fa5e9b2fc90855fe4df770c4cf0fa653e5672 Mon Sep 17 00:00:00 2001
From: Matt Ranostay <mranostay@ti.com>
Date: Sun, 23 Oct 2022 20:54:04 -0700
Subject: [PATCH 261/875] dt-bindings: mfd: ti,j721e-system-controller: Add
 compatible strings for other platforms

There are multiple J7 based platforms, and the j721e-system-controller
shouldn't be define in non-j721e devices device trees.

This is mainly for clarity; but also useful in case there are future
erratas that need to be fixed for a specific platform.

Signed-off-by: Matt Ranostay <mranostay@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221024035405.366208-2-mranostay@ti.com
---
 .../devicetree/bindings/mfd/ti,j721e-system-controller.yaml     | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
index 873ee0c0973f1..76ef4352e13ca 100644
--- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
+++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
@@ -26,7 +26,9 @@ properties:
   compatible:
     items:
       - enum:
+          - ti,j7200-system-controller
           - ti,j721e-system-controller
+          - ti,j721s2-system-controller
       - const: syscon
       - const: simple-mfd
 
-- 
GitLab


From 6af338b0011727da68c32ba79f8dfab8524fc4ae Mon Sep 17 00:00:00 2001
From: Neil Armstrong <neil.armstrong@linaro.org>
Date: Fri, 21 Oct 2022 11:06:41 +0200
Subject: [PATCH 262/875] dt-bindings: mfd: qcom-pm8xxx: Document qcom,pm8921
 as fallback of qcom,pm8018

The PM8018 is used as compatible with PM8921 on the MDM9615, document this situation,
and an example section to validate this change.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20220928-mdm9615-dt-schema-fixes-v4-5-dac2dfaac703@linaro.org
---
 .../devicetree/bindings/mfd/qcom-pm8xxx.yaml  | 33 ++++++++++++++++---
 1 file changed, 28 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.yaml b/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.yaml
index 61bd0b3ce02f8..84b87f01e0295 100644
--- a/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.yaml
+++ b/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.yaml
@@ -15,11 +15,15 @@ description: |
 
 properties:
   compatible:
-    enum:
-      - qcom,pm8018
-      - qcom,pm8058
-      - qcom,pm8821
-      - qcom,pm8921
+    oneOf:
+      - enum:
+          - qcom,pm8058
+          - qcom,pm8821
+          - qcom,pm8921
+      - items:
+          - enum:
+              - qcom,pm8018
+          - const: qcom,pm8921
 
   reg:
     maxItems: 1
@@ -52,4 +56,23 @@ required:
   - interrupt-controller
 
 additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    ssbi {
+      #address-cells = <1>;
+      #size-cells = <0>;
+      pmic@0 {
+        compatible = "qcom,pm8921";
+        reg = <0>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+
+        interrupt-parent = <&tlmm>;
+        interrupts = <32 IRQ_TYPE_EDGE_RISING>;
+      };
+    };
 ...
-- 
GitLab


From 727b67e34969ab7ad254a379664bbb492ae0bc5a Mon Sep 17 00:00:00 2001
From: Neil Armstrong <neil.armstrong@linaro.org>
Date: Fri, 21 Oct 2022 11:06:44 +0200
Subject: [PATCH 263/875] mfd: qcom-pm8xxx: Drop unused PM8018 compatible

The PM8018 compatible is always used with PM8921 fallback, so PM8018
compatible can be safely removed from device ID table

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20220928-mdm9615-dt-schema-fixes-v4-8-dac2dfaac703@linaro.org
---
 drivers/mfd/qcom-pm8xxx.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/mfd/qcom-pm8xxx.c b/drivers/mfd/qcom-pm8xxx.c
index 2f2734ba5273e..601106580e2e5 100644
--- a/drivers/mfd/qcom-pm8xxx.c
+++ b/drivers/mfd/qcom-pm8xxx.c
@@ -497,7 +497,6 @@ static const struct pm_irq_data pm8821_data = {
 };
 
 static const struct of_device_id pm8xxx_id_table[] = {
-	{ .compatible = "qcom,pm8018", .data = &pm8xxx_data},
 	{ .compatible = "qcom,pm8058", .data = &pm8xxx_data},
 	{ .compatible = "qcom,pm8821", .data = &pm8821_data},
 	{ .compatible = "qcom,pm8921", .data = &pm8xxx_data},
-- 
GitLab


From e112f2de151badd38a9c8a098a1f92f2369349cb Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
Date: Fri, 28 Oct 2022 13:53:53 +0200
Subject: [PATCH 264/875] dt-bindings: timer: Add Broadcom's BCMBCA timers
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

BCA is a big set / family of Broadcom devices sharing multiple hardware
blocks. One of them is timer that actually exists in two versions. It's
a part of TWD MFD block.

Add binding for it so SoCs can be properly described. Linux (and
probably any other OS) doesn't really seem to need a driver for it. it
may be needed for bootloaders (e.g. U-Boot) though. Especially for SoCs
with CPUs other than Cortex-A9 (which contains arch timers).

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221028115353.13881-1-zajec5@gmail.com
---
 .../devicetree/bindings/mfd/brcm,twd.yaml     |  8 ++++
 .../bindings/timer/brcm,bcmbca-timer.yaml     | 40 +++++++++++++++++++
 2 files changed, 48 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/brcm,bcmbca-timer.yaml

diff --git a/Documentation/devicetree/bindings/mfd/brcm,twd.yaml b/Documentation/devicetree/bindings/mfd/brcm,twd.yaml
index 634526f790b87..e5136a37b0a38 100644
--- a/Documentation/devicetree/bindings/mfd/brcm,twd.yaml
+++ b/Documentation/devicetree/bindings/mfd/brcm,twd.yaml
@@ -36,6 +36,9 @@ properties:
     const: 1
 
 patternProperties:
+  '^timer@[a-f0-9]+$':
+    $ref: /schemas/timer/brcm,bcmbca-timer.yaml
+
   '^watchdog@[a-f0-9]+$':
     $ref: /schemas/watchdog/brcm,bcm7038-wdt.yaml
 
@@ -54,6 +57,11 @@ examples:
         #address-cells = <1>;
         #size-cells = <1>;
 
+        timer@0 {
+            compatible = "brcm,bcm63138-timer";
+            reg = <0x0 0x28>;
+        };
+
         watchdog@28 {
             compatible = "brcm,bcm7038-wdt";
             reg = <0x28 0x8>;
diff --git a/Documentation/devicetree/bindings/timer/brcm,bcmbca-timer.yaml b/Documentation/devicetree/bindings/timer/brcm,bcmbca-timer.yaml
new file mode 100644
index 0000000000000..6707d97608577
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/brcm,bcmbca-timer.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/brcm,bcmbca-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom Broadband SoC timer
+
+maintainers:
+  - Rafał Miłecki <rafal@milecki.pl>
+
+properties:
+  compatible:
+    oneOf:
+      - const: brcm,bcm6345-timer
+        description: >
+          An old block with 3 timers.
+
+          It can be found in BCM6345, BCM6838 and BCM63268.
+      - const: brcm,bcm63138-timer
+        description: >
+          Updated block with 4 timers and control regs at the beginning.
+
+          It can be found in newer SoCs, e.g. BCM63138, BCM63148, BCM63381,
+          BCM68360, BCM6848, BCM6858, BCM4908.
+
+  reg:
+    maxItems: 1
+
+additionalProperties: false
+
+required:
+  - reg
+
+examples:
+  - |
+    timer@fffe0200 {
+      compatible = "brcm,bcm6345-timer";
+      reg = <0xfffe0200 0x1c>;
+    };
-- 
GitLab


From 9f0345e335b2eccf56faf45fb9706b40052acbdf Mon Sep 17 00:00:00 2001
From: Quan Nguyen <quan@os.amperecomputing.com>
Date: Mon, 31 Oct 2022 09:44:40 +0700
Subject: [PATCH 265/875] dt-bindings: mfd: Add bindings for Ampere Altra SMPro
 MFD driver

Adds device tree bindings for SMPro MFD driver found on the Mt.Jade
hardware reference platform with Ampere's Altra Processor family.

The SMpro co-processor on Ampere Altra processor family is to monitor
and report various data included hwmon-related info, RAS errors, and
other miscellaneous information.

Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221031024442.2490881-2-quan@os.amperecomputing.com
---
 .../devicetree/bindings/mfd/ampere,smpro.yaml | 42 +++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/ampere,smpro.yaml

diff --git a/Documentation/devicetree/bindings/mfd/ampere,smpro.yaml b/Documentation/devicetree/bindings/mfd/ampere,smpro.yaml
new file mode 100644
index 0000000000000..c442c3cdffed0
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/ampere,smpro.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/ampere,smpro.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ampere Altra SMPro firmware driver
+
+maintainers:
+  - Quan Nguyen <quan@os.amperecomputing.com>
+
+description: |
+  Ampere Altra SMPro firmware may contain different blocks like hardware
+  monitoring, error monitoring and other miscellaneous features.
+
+properties:
+  compatible:
+    enum:
+      - ampere,smpro
+
+  reg:
+    description:
+      I2C device address.
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        smpro@4f {
+            compatible = "ampere,smpro";
+            reg = <0x4f>;
+        };
+    };
-- 
GitLab


From 4c7ee9a38dcc347887511deb773624550f7629ca Mon Sep 17 00:00:00 2001
From: Colin Foster <colin.foster@in-advantage.com>
Date: Mon, 24 Oct 2022 22:03:49 -0700
Subject: [PATCH 266/875] dt-bindings: mfd: ocelot: Remove spi-max-frequency
 from required properties

The property spi-max-frequency was initially documented as a required
property. It is not actually required, and will break bindings validation
if other control mediums (e.g. PCIe) are used.

Remove this property from the required arguments.

Signed-off-by: Colin Foster <colin.foster@in-advantage.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221025050355.3979380-2-colin.foster@in-advantage.com
---
 Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml | 1 -
 1 file changed, 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml b/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
index 8bf45a5673a47..c6da91211a18f 100644
--- a/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
+++ b/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
@@ -61,7 +61,6 @@ required:
   - reg
   - '#address-cells'
   - '#size-cells'
-  - spi-max-frequency
 
 additionalProperties: false
 
-- 
GitLab


From b092874ace67d5e33a9dc3aba7cb2e666dda8fd3 Mon Sep 17 00:00:00 2001
From: Colin Foster <colin.foster@in-advantage.com>
Date: Mon, 24 Oct 2022 22:03:50 -0700
Subject: [PATCH 267/875] dt-bindings: mfd: ocelot: Remove unnecessary driver
 wording

Initially there was unnecessary verbage around "this driver" in the
documentation. It was unnecessary. Remove self references about it being a
"driver" documentation and replace it with a more detailed description
about external interfaces that are supported.

Signed-off-by: Colin Foster <colin.foster@in-advantage.com>
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221025050355.3979380-3-colin.foster@in-advantage.com
---
 Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml b/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
index c6da91211a18f..1d1fee1a16c1a 100644
--- a/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
+++ b/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
@@ -12,7 +12,8 @@ maintainers:
 description: |
   The Ocelot ethernet switch family contains chips that have an internal CPU
   (VSC7513, VSC7514) and chips that don't (VSC7511, VSC7512). All switches have
-  the option to be controlled externally, which is the purpose of this driver.
+  the option to be controlled externally via external interfaces like SPI or
+  PCIe.
 
   The switch family is a multi-port networking switch that supports many
   interfaces. Additionally, the device can perform pin control, MDIO buses, and
-- 
GitLab


From 3633daacea2e54bf991d2f6b871efe9f83a0cac8 Mon Sep 17 00:00:00 2001
From: Neil Armstrong <neil.armstrong@linaro.org>
Date: Mon, 31 Oct 2022 17:05:07 +0100
Subject: [PATCH 268/875] mfd: rk808: Permit having multiple PMIC instances

This set each cells id to PLATFORM_DEVID_NONE to allow multiple
instances of each cell in case multiple PMICs handled by the rk808
driver are probed.

This fixes probing a RK818 and a RK817 on the Odroid Go Ultra
devices.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221025-rk808-multi-v2-0-d292d51ada81@linaro.org
---
 drivers/mfd/rk808.c | 26 ++++++++++++++++----------
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/drivers/mfd/rk808.c b/drivers/mfd/rk808.c
index b390bba542e66..f44fc3f080a8e 100644
--- a/drivers/mfd/rk808.c
+++ b/drivers/mfd/rk808.c
@@ -137,58 +137,64 @@ static const struct resource rk817_charger_resources[] = {
 };
 
 static const struct mfd_cell rk805s[] = {
-	{ .name = "rk808-clkout", },
-	{ .name = "rk808-regulator", },
-	{ .name = "rk805-pinctrl", },
+	{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
+	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
+	{ .name = "rk805-pinctrl", .id = PLATFORM_DEVID_NONE, },
 	{
 		.name = "rk808-rtc",
 		.num_resources = ARRAY_SIZE(rtc_resources),
 		.resources = &rtc_resources[0],
+		.id = PLATFORM_DEVID_NONE,
 	},
 	{	.name = "rk805-pwrkey",
 		.num_resources = ARRAY_SIZE(rk805_key_resources),
 		.resources = &rk805_key_resources[0],
+		.id = PLATFORM_DEVID_NONE,
 	},
 };
 
 static const struct mfd_cell rk808s[] = {
-	{ .name = "rk808-clkout", },
-	{ .name = "rk808-regulator", },
+	{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
+	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
 	{
 		.name = "rk808-rtc",
 		.num_resources = ARRAY_SIZE(rtc_resources),
 		.resources = rtc_resources,
+		.id = PLATFORM_DEVID_NONE,
 	},
 };
 
 static const struct mfd_cell rk817s[] = {
-	{ .name = "rk808-clkout",},
-	{ .name = "rk808-regulator",},
+	{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
+	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
 	{
 		.name = "rk805-pwrkey",
 		.num_resources = ARRAY_SIZE(rk817_pwrkey_resources),
 		.resources = &rk817_pwrkey_resources[0],
+		.id = PLATFORM_DEVID_NONE,
 	},
 	{
 		.name = "rk808-rtc",
 		.num_resources = ARRAY_SIZE(rk817_rtc_resources),
 		.resources = &rk817_rtc_resources[0],
+		.id = PLATFORM_DEVID_NONE,
 	},
-	{ .name = "rk817-codec",},
+	{ .name = "rk817-codec", .id = PLATFORM_DEVID_NONE, },
 	{
 		.name = "rk817-charger",
 		.num_resources = ARRAY_SIZE(rk817_charger_resources),
 		.resources = &rk817_charger_resources[0],
+		.id = PLATFORM_DEVID_NONE,
 	},
 };
 
 static const struct mfd_cell rk818s[] = {
-	{ .name = "rk808-clkout", },
-	{ .name = "rk808-regulator", },
+	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
 	{
 		.name = "rk808-rtc",
 		.num_resources = ARRAY_SIZE(rtc_resources),
 		.resources = rtc_resources,
+		.id = PLATFORM_DEVID_NONE,
 	},
 };
 
-- 
GitLab


From 411ffc82f93cf69f70712467ac85fdf2dc3be04a Mon Sep 17 00:00:00 2001
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Date: Fri, 4 Nov 2022 18:21:19 +0100
Subject: [PATCH 269/875] dt-bindings: mfd: qcom,tcsr: Add compatible for
 MSM8976

Document the qcom,msm8976-tcsr compatible.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221104172122.252761-7-angelogioacchino.delregno@collabora.com
---
 Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
index cb0ae38a777fe..adcae6c007d90 100644
--- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
+++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
@@ -17,6 +17,7 @@ properties:
   compatible:
     items:
       - enum:
+          - qcom,msm8976-tcsr
           - qcom,msm8998-tcsr
           - qcom,qcs404-tcsr
           - qcom,sc7180-tcsr
-- 
GitLab


From b5a8668dab74ee37886aec5a1748f681a2d6cc6c Mon Sep 17 00:00:00 2001
From: Randy Dunlap <rdunlap@infradead.org>
Date: Mon, 31 Oct 2022 22:54:33 -0700
Subject: [PATCH 270/875] mfd: intel_soc_pmic: Allow COMPILE_TEST or
 I2C_DESIGNWARE_PLATFORM

Linus expressed a desire to have intel_soc_pmic_crc.o (INTEL_SOC_PMIC,
for Crystal Cove) be built on an "allmodconfig" build, when
I2C_DESIGNWARE_PLATFORM=m, to enhance build test coverage.

The PMIC driver won't work in this case since it requires
I2C_DESIGNWARE_PLATFORM=y to operate properly, but adding
"|| COMPILE_TEST" does improve the build test coverage.

Link: https://lore.kernel.org/all/CAHk-=wg=hh8xkPjiySnjAyR66AG64eyZ1Y9gHw+MCs8uuSZReA@mail.gmail.com/

Suggested-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221101055433.16891-1-rdunlap@infradead.org
---
 drivers/mfd/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 6e920442366c0..6653d03e0fe31 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -594,7 +594,7 @@ config INTEL_SOC_PMIC
 	bool "Support for Crystal Cove PMIC"
 	depends on HAS_IOMEM && I2C=y && GPIOLIB && COMMON_CLK
 	depends on (X86 && ACPI) || COMPILE_TEST
-	depends on I2C_DESIGNWARE_PLATFORM=y
+	depends on I2C_DESIGNWARE_PLATFORM=y || COMPILE_TEST
 	select MFD_CORE
 	select REGMAP_I2C
 	select REGMAP_IRQ
-- 
GitLab


From 0a5219f34fea85a0e583de2aa4528548acaa85f4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>
Date: Tue, 1 Nov 2022 17:50:45 +0100
Subject: [PATCH 271/875] mfd: mc13xxx-spi: Fix typo ("transfert")
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

That spelling is only correct in French :-)

Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221101165045.1017822-1-j.neuschaefer@gmx.net
---
 drivers/mfd/mc13xxx-spi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mfd/mc13xxx-spi.c b/drivers/mfd/mc13xxx-spi.c
index 2809fbeb317c5..f70d79aa5a833 100644
--- a/drivers/mfd/mc13xxx-spi.c
+++ b/drivers/mfd/mc13xxx-spi.c
@@ -114,7 +114,7 @@ static int mc13xxx_spi_write(void *context, const void *data, size_t count)
  * result, the SS will negate before all of the data has been
  * transferred to/from the peripheral."
  * We workaround this by accessing the SPI controller with a
- * single transfert.
+ * single transfer.
  */
 
 static struct regmap_bus regmap_mc13xxx_bus = {
-- 
GitLab


From ef1709238aa50094d918e4f1dd5231dac5db13c3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>
Date: Sat, 5 Nov 2022 19:59:07 +0100
Subject: [PATCH 272/875] dt-bindings: mfd: syscon: Add nuvoton,wpcm450-shm
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The Shared Memory interface (SHM) is a piece of hardware in Nuvoton BMCs
that allows a host processor (connected via LPC) to access flash and RAM
that belong to the BMC. The SHM includes a register block accessible from
the BMC side.

Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221105185911.1547847-5-j.neuschaefer@gmx.net
---
 Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index 4e4baf53796de..1b01bd0104316 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -53,6 +53,7 @@ properties:
               - microchip,lan966x-cpu-syscon
               - microchip,sparx5-cpu-syscon
               - mstar,msc313-pmsleep
+              - nuvoton,wpcm450-shm
               - rockchip,px30-qos
               - rockchip,rk3036-qos
               - rockchip,rk3066-qos
-- 
GitLab


From 3f37d4f695cff180033254b9ed5adc8ab927cba9 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sat, 5 Nov 2022 16:29:09 -0500
Subject: [PATCH 273/875] mfd: axp20x: Do not sleep in the power off handler

Since commit 856c288b0039 ("ARM: Use do_kernel_power_off()"), the
function axp20x_power_off() now runs inside a RCU read-side critical
section, so it is not allowed to call msleep(). Use mdelay() instead.

Fixes: 856c288b0039 ("ARM: Use do_kernel_power_off()")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221105212909.6526-1-samuel@sholland.org
---
 drivers/mfd/axp20x.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 88a212a8168cf..880c41fa7021b 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -842,7 +842,7 @@ static void axp20x_power_off(void)
 		     AXP20X_OFF);
 
 	/* Give capacitors etc. time to drain to avoid kernel panic msg. */
-	msleep(500);
+	mdelay(500);
 }
 
 int axp20x_match_device(struct axp20x_dev *axp20x)
-- 
GitLab


From 19755a0acb8831a02ba7833f908c55febaaa2607 Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:25 +0100
Subject: [PATCH 274/875] mfd: 88pm80x: Remove #ifdef guards for PM related
 functions

Use the new EXPORT_GPL_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr() macros
to handle the .suspend/.resume callbacks.

These macros allow the suspend and resume functions to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/88pm800.c | 2 +-
 drivers/mfd/88pm805.c | 2 +-
 drivers/mfd/88pm80x.c | 5 +----
 3 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/mfd/88pm800.c b/drivers/mfd/88pm800.c
index 5236c065da88e..4d139cc31c25f 100644
--- a/drivers/mfd/88pm800.c
+++ b/drivers/mfd/88pm800.c
@@ -596,7 +596,7 @@ static void pm800_remove(struct i2c_client *client)
 static struct i2c_driver pm800_driver = {
 	.driver = {
 		.name = "88PM800",
-		.pm = &pm80x_pm_ops,
+		.pm = pm_sleep_ptr(&pm80x_pm_ops),
 		},
 	.probe_new = pm800_probe,
 	.remove = pm800_remove,
diff --git a/drivers/mfd/88pm805.c b/drivers/mfd/88pm805.c
index c274f1840761a..352f13cb14811 100644
--- a/drivers/mfd/88pm805.c
+++ b/drivers/mfd/88pm805.c
@@ -251,7 +251,7 @@ static void pm805_remove(struct i2c_client *client)
 static struct i2c_driver pm805_driver = {
 	.driver = {
 		.name = "88PM805",
-		.pm = &pm80x_pm_ops,
+		.pm = pm_sleep_ptr(&pm80x_pm_ops),
 		},
 	.probe_new = pm805_probe,
 	.remove = pm805_remove,
diff --git a/drivers/mfd/88pm80x.c b/drivers/mfd/88pm80x.c
index be036e7e787b4..ac4f08565f290 100644
--- a/drivers/mfd/88pm80x.c
+++ b/drivers/mfd/88pm80x.c
@@ -129,7 +129,6 @@ int pm80x_deinit(void)
 }
 EXPORT_SYMBOL_GPL(pm80x_deinit);
 
-#ifdef CONFIG_PM_SLEEP
 static int pm80x_suspend(struct device *dev)
 {
 	struct i2c_client *client = to_i2c_client(dev);
@@ -153,10 +152,8 @@ static int pm80x_resume(struct device *dev)
 
 	return 0;
 }
-#endif
 
-SIMPLE_DEV_PM_OPS(pm80x_pm_ops, pm80x_suspend, pm80x_resume);
-EXPORT_SYMBOL_GPL(pm80x_pm_ops);
+EXPORT_GPL_SIMPLE_DEV_PM_OPS(pm80x_pm_ops, pm80x_suspend, pm80x_resume);
 
 MODULE_DESCRIPTION("I2C Driver for Marvell 88PM80x");
 MODULE_AUTHOR("Qiao Zhou <zhouqiao@marvell.com>");
-- 
GitLab


From dce97f81fea6fa6230e6b7f0e2d0f17a74158dc9 Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:26 +0100
Subject: [PATCH 275/875] mfd: aat2870: Remove #ifdef guards for PM related
 functions

Use the new DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr() macros
to handle the .suspend/.resume callbacks.

These macros allow the suspend and resume functions to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/aat2870-core.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/mfd/aat2870-core.c b/drivers/mfd/aat2870-core.c
index f096dc80b7543..f253da5b246be 100644
--- a/drivers/mfd/aat2870-core.c
+++ b/drivers/mfd/aat2870-core.c
@@ -408,7 +408,6 @@ out_disable:
 	return ret;
 }
 
-#ifdef CONFIG_PM_SLEEP
 static int aat2870_i2c_suspend(struct device *dev)
 {
 	struct i2c_client *client = to_i2c_client(dev);
@@ -437,10 +436,9 @@ static int aat2870_i2c_resume(struct device *dev)
 
 	return 0;
 }
-#endif /* CONFIG_PM_SLEEP */
 
-static SIMPLE_DEV_PM_OPS(aat2870_pm_ops, aat2870_i2c_suspend,
-			 aat2870_i2c_resume);
+static DEFINE_SIMPLE_DEV_PM_OPS(aat2870_pm_ops, aat2870_i2c_suspend,
+				aat2870_i2c_resume);
 
 static const struct i2c_device_id aat2870_i2c_id_table[] = {
 	{ "aat2870", 0 },
@@ -450,7 +448,7 @@ static const struct i2c_device_id aat2870_i2c_id_table[] = {
 static struct i2c_driver aat2870_i2c_driver = {
 	.driver = {
 		.name			= "aat2870",
-		.pm			= &aat2870_pm_ops,
+		.pm			= pm_sleep_ptr(&aat2870_pm_ops),
 		.suppress_bind_attrs	= true,
 	},
 	.probe_new	= aat2870_i2c_probe,
-- 
GitLab


From 5745a90a930c81b55dfcb67b5e904b3cb1df0c7a Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:27 +0100
Subject: [PATCH 276/875] mfd: adp5520: Remove #ifdef guards for PM related
 functions

Use the new DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr() macros
to handle the .suspend/.resume callbacks.

These macros allow the suspend and resume functions to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/adp5520.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/mfd/adp5520.c b/drivers/mfd/adp5520.c
index bdcedb034913e..cb168efdbafe8 100644
--- a/drivers/mfd/adp5520.c
+++ b/drivers/mfd/adp5520.c
@@ -305,7 +305,6 @@ out_free_irq:
 	return ret;
 }
 
-#ifdef CONFIG_PM_SLEEP
 static int adp5520_suspend(struct device *dev)
 {
 	struct i2c_client *client = to_i2c_client(dev);
@@ -326,9 +325,8 @@ static int adp5520_resume(struct device *dev)
 	adp5520_write(chip->dev, ADP5520_MODE_STATUS, chip->mode);
 	return 0;
 }
-#endif
 
-static SIMPLE_DEV_PM_OPS(adp5520_pm, adp5520_suspend, adp5520_resume);
+static DEFINE_SIMPLE_DEV_PM_OPS(adp5520_pm, adp5520_suspend, adp5520_resume);
 
 static const struct i2c_device_id adp5520_id[] = {
 	{ "pmic-adp5520", ID_ADP5520 },
@@ -339,7 +337,7 @@ static const struct i2c_device_id adp5520_id[] = {
 static struct i2c_driver adp5520_driver = {
 	.driver = {
 		.name			= "adp5520",
-		.pm			= &adp5520_pm,
+		.pm			= pm_sleep_ptr(&adp5520_pm),
 		.suppress_bind_attrs	= true,
 	},
 	.probe_new	= adp5520_probe,
-- 
GitLab


From 52c9d7193ba4342239a47a5524884f7a0a667e4d Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:28 +0100
Subject: [PATCH 277/875] mfd: max8925-i2c: Remove #ifdef guards for PM related
 functions

Use the new DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr() macros
to handle the .suspend/.resume callbacks.

These macros allow the suspend and resume functions to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/max8925-i2c.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/mfd/max8925-i2c.c b/drivers/mfd/max8925-i2c.c
index 7c3ec167f9417..4057fd15c29e7 100644
--- a/drivers/mfd/max8925-i2c.c
+++ b/drivers/mfd/max8925-i2c.c
@@ -206,7 +206,6 @@ static void max8925_remove(struct i2c_client *client)
 	i2c_unregister_device(chip->rtc);
 }
 
-#ifdef CONFIG_PM_SLEEP
 static int max8925_suspend(struct device *dev)
 {
 	struct i2c_client *client = to_i2c_client(dev);
@@ -226,9 +225,9 @@ static int max8925_resume(struct device *dev)
 		disable_irq_wake(chip->core_irq);
 	return 0;
 }
-#endif
 
-static SIMPLE_DEV_PM_OPS(max8925_pm_ops, max8925_suspend, max8925_resume);
+static DEFINE_SIMPLE_DEV_PM_OPS(max8925_pm_ops,
+				max8925_suspend, max8925_resume);
 
 static const struct of_device_id max8925_dt_ids[] = {
 	{ .compatible = "maxim,max8925", },
@@ -238,7 +237,7 @@ static const struct of_device_id max8925_dt_ids[] = {
 static struct i2c_driver max8925_driver = {
 	.driver	= {
 		.name	= "max8925",
-		.pm     = &max8925_pm_ops,
+		.pm     = pm_sleep_ptr(&max8925_pm_ops),
 		.of_match_table = max8925_dt_ids,
 	},
 	.probe_new	= max8925_probe,
-- 
GitLab


From e1243e0d72185c257ac2cdde1bbba130e24acf9a Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:29 +0100
Subject: [PATCH 278/875] mfd: mt6397-irq: Remove #ifdef guards for PM related
 functions

Use the new pm_sleep_ptr() macro to handle the .irq_set_wake() callback.

This macro allows the mt6397_irq_set_wake() function to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/mt6397-irq.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/mfd/mt6397-irq.c b/drivers/mfd/mt6397-irq.c
index eff53fed8fe73..72f923e47752d 100644
--- a/drivers/mfd/mt6397-irq.c
+++ b/drivers/mfd/mt6397-irq.c
@@ -54,7 +54,6 @@ static void mt6397_irq_enable(struct irq_data *data)
 	mt6397->irq_masks_cur[reg] |= BIT(shift);
 }
 
-#ifdef CONFIG_PM_SLEEP
 static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
 {
 	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
@@ -68,9 +67,6 @@ static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
 
 	return 0;
 }
-#else
-#define mt6397_irq_set_wake NULL
-#endif
 
 static struct irq_chip mt6397_irq_chip = {
 	.name = "mt6397-irq",
@@ -78,7 +74,7 @@ static struct irq_chip mt6397_irq_chip = {
 	.irq_bus_sync_unlock = mt6397_irq_sync_unlock,
 	.irq_enable = mt6397_irq_enable,
 	.irq_disable = mt6397_irq_disable,
-	.irq_set_wake = mt6397_irq_set_wake,
+	.irq_set_wake = pm_sleep_ptr(mt6397_irq_set_wake),
 };
 
 static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
-- 
GitLab


From 245cb473e5388fcbc01c7284b6a4e1446cdbf054 Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:30 +0100
Subject: [PATCH 279/875] mfd: pcf50633: Remove #ifdef guards for PM related
 functions

Use the new EXPORT_GPL_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr() macros
to handle the .suspend/.resume callbacks.

These macros allow the suspend and resume functions to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/pcf50633-core.c       | 22 +---------------------
 drivers/mfd/pcf50633-irq.c        | 13 ++++++++-----
 include/linux/mfd/pcf50633/core.h |  6 ++----
 3 files changed, 11 insertions(+), 30 deletions(-)

diff --git a/drivers/mfd/pcf50633-core.c b/drivers/mfd/pcf50633-core.c
index da39a7940560b..0e4fc99e9f492 100644
--- a/drivers/mfd/pcf50633-core.c
+++ b/drivers/mfd/pcf50633-core.c
@@ -158,26 +158,6 @@ pcf50633_client_dev_register(struct pcf50633 *pcf, const char *name,
 	}
 }
 
-#ifdef CONFIG_PM_SLEEP
-static int pcf50633_suspend(struct device *dev)
-{
-	struct i2c_client *client = to_i2c_client(dev);
-	struct pcf50633 *pcf = i2c_get_clientdata(client);
-
-	return pcf50633_irq_suspend(pcf);
-}
-
-static int pcf50633_resume(struct device *dev)
-{
-	struct i2c_client *client = to_i2c_client(dev);
-	struct pcf50633 *pcf = i2c_get_clientdata(client);
-
-	return pcf50633_irq_resume(pcf);
-}
-#endif
-
-static SIMPLE_DEV_PM_OPS(pcf50633_pm, pcf50633_suspend, pcf50633_resume);
-
 static const struct regmap_config pcf50633_regmap_config = {
 	.reg_bits = 8,
 	.val_bits = 8,
@@ -299,7 +279,7 @@ MODULE_DEVICE_TABLE(i2c, pcf50633_id_table);
 static struct i2c_driver pcf50633_driver = {
 	.driver = {
 		.name	= "pcf50633",
-		.pm	= &pcf50633_pm,
+		.pm	= pm_sleep_ptr(&pcf50633_pm),
 	},
 	.id_table = pcf50633_id_table,
 	.probe_new = pcf50633_probe,
diff --git a/drivers/mfd/pcf50633-irq.c b/drivers/mfd/pcf50633-irq.c
index 2096afb0ce9bb..e85af7f1cb0b1 100644
--- a/drivers/mfd/pcf50633-irq.c
+++ b/drivers/mfd/pcf50633-irq.c
@@ -7,6 +7,7 @@
  * All rights reserved.
  */
 
+#include <linux/i2c.h>
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
 #include <linux/mutex.h>
@@ -218,10 +219,10 @@ out:
 	return IRQ_HANDLED;
 }
 
-#ifdef CONFIG_PM
-
-int pcf50633_irq_suspend(struct pcf50633 *pcf)
+static int pcf50633_suspend(struct device *dev)
 {
+	struct i2c_client *client = to_i2c_client(dev);
+	struct pcf50633 *pcf = i2c_get_clientdata(client);
 	int ret;
 	int i;
 	u8 res[5];
@@ -257,8 +258,10 @@ out:
 	return ret;
 }
 
-int pcf50633_irq_resume(struct pcf50633 *pcf)
+static int pcf50633_resume(struct device *dev)
 {
+	struct i2c_client *client = to_i2c_client(dev);
+	struct pcf50633 *pcf = i2c_get_clientdata(client);
 	int ret;
 
 	/* Write the saved mask registers */
@@ -273,7 +276,7 @@ int pcf50633_irq_resume(struct pcf50633 *pcf)
 	return ret;
 }
 
-#endif
+EXPORT_GPL_SIMPLE_DEV_PM_OPS(pcf50633_pm, pcf50633_suspend, pcf50633_resume);
 
 int pcf50633_irq_init(struct pcf50633 *pcf, int irq)
 {
diff --git a/include/linux/mfd/pcf50633/core.h b/include/linux/mfd/pcf50633/core.h
index 3f752dc62a6c4..539f27f8bd89b 100644
--- a/include/linux/mfd/pcf50633/core.h
+++ b/include/linux/mfd/pcf50633/core.h
@@ -13,6 +13,7 @@
 #include <linux/workqueue.h>
 #include <linux/regulator/driver.h>
 #include <linux/regulator/machine.h>
+#include <linux/pm.h>
 #include <linux/power_supply.h>
 #include <linux/mfd/pcf50633/backlight.h>
 
@@ -226,9 +227,6 @@ static inline struct pcf50633 *dev_to_pcf50633(struct device *dev)
 
 int pcf50633_irq_init(struct pcf50633 *pcf, int irq);
 void pcf50633_irq_free(struct pcf50633 *pcf);
-#ifdef CONFIG_PM
-int pcf50633_irq_suspend(struct pcf50633 *pcf);
-int pcf50633_irq_resume(struct pcf50633 *pcf);
-#endif
+extern const struct dev_pm_ops pcf50633_pm;
 
 #endif
-- 
GitLab


From 2662b90fd58b8833894948be07c2f44bfa782ed8 Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:31 +0100
Subject: [PATCH 280/875] mfd: rc5t583-irq: Remove #ifdef guards for PM related
 functions

Use the new pm_sleep_ptr() macro to handle the .irq_set_wake() callback.

This macro allows the mt6397_irq_set_wake() function to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/rc5t583-irq.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/mfd/rc5t583-irq.c b/drivers/mfd/rc5t583-irq.c
index b374a3d346888..621ea61fa7c62 100644
--- a/drivers/mfd/rc5t583-irq.c
+++ b/drivers/mfd/rc5t583-irq.c
@@ -228,15 +228,12 @@ static void rc5t583_irq_sync_unlock(struct irq_data *irq_data)
 
 	mutex_unlock(&rc5t583->irq_lock);
 }
-#ifdef CONFIG_PM_SLEEP
+
 static int rc5t583_irq_set_wake(struct irq_data *irq_data, unsigned int on)
 {
 	struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
 	return irq_set_irq_wake(rc5t583->chip_irq, on);
 }
-#else
-#define rc5t583_irq_set_wake NULL
-#endif
 
 static irqreturn_t rc5t583_irq(int irq, void *data)
 {
@@ -317,7 +314,7 @@ static struct irq_chip rc5t583_irq_chip = {
 	.irq_bus_lock = rc5t583_irq_lock,
 	.irq_bus_sync_unlock = rc5t583_irq_sync_unlock,
 	.irq_set_type = rc5t583_irq_set_type,
-	.irq_set_wake = rc5t583_irq_set_wake,
+	.irq_set_wake = pm_sleep_ptr(rc5t583_irq_set_wake),
 };
 
 int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base)
-- 
GitLab


From e4b9a17c99d0b45cb4104fd32d170536701214e8 Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:32 +0100
Subject: [PATCH 281/875] mfd: stpmic1: Remove #ifdef guards for PM related
 functions

Use the new DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr() macros
to handle the .suspend/.resume callbacks.

These macros allow the suspend and resume functions to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/stpmic1.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/mfd/stpmic1.c b/drivers/mfd/stpmic1.c
index f5a51171b1b34..54a4d59d1937b 100644
--- a/drivers/mfd/stpmic1.c
+++ b/drivers/mfd/stpmic1.c
@@ -161,7 +161,6 @@ static int stpmic1_probe(struct i2c_client *i2c)
 	return devm_of_platform_populate(dev);
 }
 
-#ifdef CONFIG_PM_SLEEP
 static int stpmic1_suspend(struct device *dev)
 {
 	struct i2c_client *i2c = to_i2c_client(dev);
@@ -186,9 +185,8 @@ static int stpmic1_resume(struct device *dev)
 
 	return 0;
 }
-#endif
 
-static SIMPLE_DEV_PM_OPS(stpmic1_pm, stpmic1_suspend, stpmic1_resume);
+static DEFINE_SIMPLE_DEV_PM_OPS(stpmic1_pm, stpmic1_suspend, stpmic1_resume);
 
 static const struct of_device_id stpmic1_of_match[] = {
 	{ .compatible = "st,stpmic1", },
@@ -200,7 +198,7 @@ static struct i2c_driver stpmic1_driver = {
 	.driver = {
 		.name = "stpmic1",
 		.of_match_table = of_match_ptr(stpmic1_of_match),
-		.pm = &stpmic1_pm,
+		.pm = pm_sleep_ptr(&stpmic1_pm),
 	},
 	.probe_new = stpmic1_probe,
 };
-- 
GitLab


From 03bf96cf8ecbd543a25c3c71b09ea67ffffeb36b Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:33 +0100
Subject: [PATCH 282/875] mfd: ucb1x00: Remove #ifdef guards for PM related
 functions

Use the new DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr() macros
to handle the .suspend/.resume callbacks.

These macros allow the suspend and resume functions to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/ucb1x00-core.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/mfd/ucb1x00-core.c b/drivers/mfd/ucb1x00-core.c
index b690796d24d4b..fc4d4c844a81e 100644
--- a/drivers/mfd/ucb1x00-core.c
+++ b/drivers/mfd/ucb1x00-core.c
@@ -660,7 +660,6 @@ void ucb1x00_unregister_driver(struct ucb1x00_driver *drv)
 	mutex_unlock(&ucb1x00_mutex);
 }
 
-#ifdef CONFIG_PM_SLEEP
 static int ucb1x00_suspend(struct device *dev)
 {
 	struct ucb1x00_plat_data *pdata = dev_get_platdata(dev);
@@ -728,15 +727,15 @@ static int ucb1x00_resume(struct device *dev)
 	mutex_unlock(&ucb1x00_mutex);
 	return 0;
 }
-#endif
 
-static SIMPLE_DEV_PM_OPS(ucb1x00_pm_ops, ucb1x00_suspend, ucb1x00_resume);
+static DEFINE_SIMPLE_DEV_PM_OPS(ucb1x00_pm_ops,
+				ucb1x00_suspend, ucb1x00_resume);
 
 static struct mcp_driver ucb1x00_driver = {
 	.drv		= {
 		.name	= "ucb1x00",
 		.owner	= THIS_MODULE,
-		.pm	= &ucb1x00_pm_ops,
+		.pm	= pm_sleep_ptr(&ucb1x00_pm_ops),
 	},
 	.probe		= ucb1x00_probe,
 	.remove		= ucb1x00_remove,
-- 
GitLab


From fdefee3073bc60b57f664e1463d7e4c07910e3bd Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:34 +0100
Subject: [PATCH 283/875] mfd: 88pm860x: Remove #ifdef guards for PM related
 functions

Use the new DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr() macros
to handle the .suspend/.resume callbacks.

These macros allow the suspend and resume functions to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/88pm860x-core.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/mfd/88pm860x-core.c b/drivers/mfd/88pm860x-core.c
index 5dc86dd66202f..6ba7169cb953a 100644
--- a/drivers/mfd/88pm860x-core.c
+++ b/drivers/mfd/88pm860x-core.c
@@ -1212,7 +1212,6 @@ static void pm860x_remove(struct i2c_client *client)
 	}
 }
 
-#ifdef CONFIG_PM_SLEEP
 static int pm860x_suspend(struct device *dev)
 {
 	struct i2c_client *client = to_i2c_client(dev);
@@ -1232,9 +1231,8 @@ static int pm860x_resume(struct device *dev)
 		disable_irq_wake(chip->core_irq);
 	return 0;
 }
-#endif
 
-static SIMPLE_DEV_PM_OPS(pm860x_pm_ops, pm860x_suspend, pm860x_resume);
+static DEFINE_SIMPLE_DEV_PM_OPS(pm860x_pm_ops, pm860x_suspend, pm860x_resume);
 
 static const struct i2c_device_id pm860x_id_table[] = {
 	{ "88PM860x", 0 },
@@ -1251,7 +1249,7 @@ MODULE_DEVICE_TABLE(of, pm860x_dt_ids);
 static struct i2c_driver pm860x_driver = {
 	.driver	= {
 		.name	= "88PM860x",
-		.pm     = &pm860x_pm_ops,
+		.pm     = pm_sleep_ptr(&pm860x_pm_ops),
 		.of_match_table	= pm860x_dt_ids,
 	},
 	.probe_new	= pm860x_probe,
-- 
GitLab


From ff84723e5291c51ac23429d267ab9107e14ee486 Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:35 +0100
Subject: [PATCH 284/875] mfd: mcp-sa11x0: Remove #ifdef guards for PM related
 functions

Use the new pm_sleep_ptr() macro to handle the .suspend/.resume
callbacks.

This macro allow the suspend and resume functions to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/mcp-sa11x0.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/mfd/mcp-sa11x0.c b/drivers/mfd/mcp-sa11x0.c
index 4629dff187cd5..1c9831b78cf9c 100644
--- a/drivers/mfd/mcp-sa11x0.c
+++ b/drivers/mfd/mcp-sa11x0.c
@@ -255,7 +255,6 @@ static int mcp_sa11x0_remove(struct platform_device *dev)
 	return 0;
 }
 
-#ifdef CONFIG_PM_SLEEP
 static int mcp_sa11x0_suspend(struct device *dev)
 {
 	struct mcp_sa11x0 *m = priv(dev_get_drvdata(dev));
@@ -277,17 +276,14 @@ static int mcp_sa11x0_resume(struct device *dev)
 
 	return 0;
 }
-#endif
 
 static const struct dev_pm_ops mcp_sa11x0_pm_ops = {
-#ifdef CONFIG_PM_SLEEP
 	.suspend = mcp_sa11x0_suspend,
 	.freeze = mcp_sa11x0_suspend,
 	.poweroff = mcp_sa11x0_suspend,
 	.resume_noirq = mcp_sa11x0_resume,
 	.thaw_noirq = mcp_sa11x0_resume,
 	.restore_noirq = mcp_sa11x0_resume,
-#endif
 };
 
 static struct platform_driver mcp_sa11x0_driver = {
@@ -295,7 +291,7 @@ static struct platform_driver mcp_sa11x0_driver = {
 	.remove		= mcp_sa11x0_remove,
 	.driver		= {
 		.name	= DRIVER_NAME,
-		.pm	= &mcp_sa11x0_pm_ops,
+		.pm	= pm_sleep_ptr(&mcp_sa11x0_pm_ops),
 	},
 };
 
-- 
GitLab


From 270a7c3eba574364c43a6ec8583ec995122c255b Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:36 +0100
Subject: [PATCH 285/875] mfd: sec: Remove #ifdef guards for PM related
 functions

Use the new DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr() macros
to handle the .suspend/.resume callbacks.

These macros allow the suspend and resume functions to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/sec-core.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/mfd/sec-core.c b/drivers/mfd/sec-core.c
index 6bf117b7193ad..b03edda56009f 100644
--- a/drivers/mfd/sec-core.c
+++ b/drivers/mfd/sec-core.c
@@ -454,7 +454,6 @@ static void sec_pmic_shutdown(struct i2c_client *i2c)
 	regmap_update_bits(sec_pmic->regmap_pmic, reg, mask, 0);
 }
 
-#ifdef CONFIG_PM_SLEEP
 static int sec_pmic_suspend(struct device *dev)
 {
 	struct i2c_client *i2c = to_i2c_client(dev);
@@ -487,14 +486,14 @@ static int sec_pmic_resume(struct device *dev)
 
 	return 0;
 }
-#endif /* CONFIG_PM_SLEEP */
 
-static SIMPLE_DEV_PM_OPS(sec_pmic_pm_ops, sec_pmic_suspend, sec_pmic_resume);
+static DEFINE_SIMPLE_DEV_PM_OPS(sec_pmic_pm_ops,
+				sec_pmic_suspend, sec_pmic_resume);
 
 static struct i2c_driver sec_pmic_driver = {
 	.driver = {
 		   .name = "sec_pmic",
-		   .pm = &sec_pmic_pm_ops,
+		   .pm = pm_sleep_ptr(&sec_pmic_pm_ops),
 		   .of_match_table = sec_dt_match,
 	},
 	.probe_new = sec_pmic_probe,
-- 
GitLab


From 3833239b5ba22256389c2fd83ca70b6a9028435b Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:37 +0100
Subject: [PATCH 286/875] mfd: sm501: Remove #ifdef guards for PM related
 functions

Use the new pm_sleep_ptr() macro to handle the .suspend/.resume
callbacks.

This macro allow the suspend and resume functions to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/sm501.c | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c
index 3ac4508a6742a..28027982cf693 100644
--- a/drivers/mfd/sm501.c
+++ b/drivers/mfd/sm501.c
@@ -1432,8 +1432,6 @@ static int sm501_plat_probe(struct platform_device *dev)
 
 }
 
-#ifdef CONFIG_PM
-
 /* power management support */
 
 static void sm501_set_power(struct sm501_devdata *sm, int on)
@@ -1509,10 +1507,6 @@ static int sm501_plat_resume(struct platform_device *pdev)
 
 	return 0;
 }
-#else
-#define sm501_plat_suspend NULL
-#define sm501_plat_resume NULL
-#endif
 
 /* Initialisation data for PCI devices */
 
@@ -1714,8 +1708,8 @@ static struct platform_driver sm501_plat_driver = {
 	},
 	.probe		= sm501_plat_probe,
 	.remove		= sm501_plat_remove,
-	.suspend	= sm501_plat_suspend,
-	.resume		= sm501_plat_resume,
+	.suspend	= pm_sleep_ptr(sm501_plat_suspend),
+	.resume		= pm_sleep_ptr(sm501_plat_resume),
 };
 
 static int __init sm501_base_init(void)
-- 
GitLab


From 2d81212cb0c811db0e74b959fd48b2ba19b77e0f Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:38 +0100
Subject: [PATCH 287/875] mfd: tc6387xb: Remove #ifdef guards for PM related
 functions

Use the new pm_sleep_ptr() macro to handle the .suspend/.resume
callbacks.

This macro allow the suspend and resume functions to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/tc6387xb.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/mfd/tc6387xb.c b/drivers/mfd/tc6387xb.c
index e846e4d26b6eb..5392da6ba7b0c 100644
--- a/drivers/mfd/tc6387xb.c
+++ b/drivers/mfd/tc6387xb.c
@@ -40,7 +40,6 @@ static const struct resource tc6387xb_mmc_resources[] = {
 
 /*--------------------------------------------------------------------------*/
 
-#ifdef CONFIG_PM
 static int tc6387xb_suspend(struct platform_device *dev, pm_message_t state)
 {
 	struct tc6387xb *tc6387xb = platform_get_drvdata(dev);
@@ -67,10 +66,6 @@ static int tc6387xb_resume(struct platform_device *dev)
 
 	return 0;
 }
-#else
-#define tc6387xb_suspend  NULL
-#define tc6387xb_resume   NULL
-#endif
 
 /*--------------------------------------------------------------------------*/
 
@@ -220,8 +215,8 @@ static struct platform_driver tc6387xb_platform_driver = {
 	},
 	.probe		= tc6387xb_probe,
 	.remove		= tc6387xb_remove,
-	.suspend        = tc6387xb_suspend,
-	.resume         = tc6387xb_resume,
+	.suspend        = pm_sleep_ptr(tc6387xb_suspend),
+	.resume         = pm_sleep_ptr(tc6387xb_resume),
 };
 
 module_platform_driver(tc6387xb_platform_driver);
-- 
GitLab


From d115e88c297546192354f65be6c0343a68910afb Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:39 +0100
Subject: [PATCH 288/875] mfd: tps6586x: Remove #ifdef guards for PM related
 functions

Use the new pm_sleep_ptr() macro to handle the .irq_set_wake() callback.

This macro allows the mt6397_irq_set_wake() function to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/tps6586x.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/mfd/tps6586x.c b/drivers/mfd/tps6586x.c
index 92703e975ffae..2d947f3f606a6 100644
--- a/drivers/mfd/tps6586x.c
+++ b/drivers/mfd/tps6586x.c
@@ -269,15 +269,11 @@ static void tps6586x_irq_sync_unlock(struct irq_data *data)
 	mutex_unlock(&tps6586x->irq_lock);
 }
 
-#ifdef CONFIG_PM_SLEEP
 static int tps6586x_irq_set_wake(struct irq_data *irq_data, unsigned int on)
 {
 	struct tps6586x *tps6586x = irq_data_get_irq_chip_data(irq_data);
 	return irq_set_irq_wake(tps6586x->irq, on);
 }
-#else
-#define tps6586x_irq_set_wake NULL
-#endif
 
 static struct irq_chip tps6586x_irq_chip = {
 	.name = "tps6586x",
@@ -285,7 +281,7 @@ static struct irq_chip tps6586x_irq_chip = {
 	.irq_bus_sync_unlock = tps6586x_irq_sync_unlock,
 	.irq_disable = tps6586x_irq_disable,
 	.irq_enable = tps6586x_irq_enable,
-	.irq_set_wake = tps6586x_irq_set_wake,
+	.irq_set_wake = pm_sleep_ptr(tps6586x_irq_set_wake),
 };
 
 static int tps6586x_irq_map(struct irq_domain *h, unsigned int virq,
-- 
GitLab


From 9dd3baecebc3d7b722486a73219afe4eaaa16257 Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:40 +0100
Subject: [PATCH 289/875] mfd: wm8994: Remove #ifdef guards for PM related
 functions

Use the new RUNTIME_PM_OPS() and pm_ptr() macros to handle the
.runtime_suspend/.runtime_resume callbacks.

These macros allow the suspend and resume functions to be automatically
dropped by the compiler when CONFIG_PM is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Note that this driver should probably use the new
DEFINE_RUNTIME_DEV_PM_OPS() macro instead, which will provide
.suspend/.resume callbacks, pointing to pm_runtime_force_suspend() and
pm_runtime_force_resume() respectively; unless those callbacks really
aren't needed.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/wm8994-core.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/mfd/wm8994-core.c b/drivers/mfd/wm8994-core.c
index 53994abe75968..a89221bffde5a 100644
--- a/drivers/mfd/wm8994-core.c
+++ b/drivers/mfd/wm8994-core.c
@@ -110,7 +110,6 @@ static const char *wm8958_main_supplies[] = {
 	"SPKVDD2",
 };
 
-#ifdef CONFIG_PM
 static int wm8994_suspend(struct device *dev)
 {
 	struct wm8994 *wm8994 = dev_get_drvdata(dev);
@@ -213,7 +212,6 @@ err_enable:
 
 	return ret;
 }
-#endif
 
 #ifdef CONFIG_REGULATOR
 static int wm8994_ldo_in_use(struct wm8994_pdata *pdata, int ldo)
@@ -674,13 +672,13 @@ static const struct i2c_device_id wm8994_i2c_id[] = {
 MODULE_DEVICE_TABLE(i2c, wm8994_i2c_id);
 
 static const struct dev_pm_ops wm8994_pm_ops = {
-	SET_RUNTIME_PM_OPS(wm8994_suspend, wm8994_resume, NULL)
+	RUNTIME_PM_OPS(wm8994_suspend, wm8994_resume, NULL)
 };
 
 static struct i2c_driver wm8994_i2c_driver = {
 	.driver = {
 		.name = "wm8994",
-		.pm = &wm8994_pm_ops,
+		.pm = pm_ptr(&wm8994_pm_ops),
 		.of_match_table = wm8994_of_match,
 	},
 	.probe_new = wm8994_i2c_probe,
-- 
GitLab


From 9b990dc9f09fcdde272abc54ae0c158596149944 Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:41 +0100
Subject: [PATCH 290/875] mfd: max77620: Remove #ifdef guards for PM related
 functions

Use the new DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr() macros
to handle the .suspend/.resume callbacks.

These macros allow the suspend and resume functions to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/max77620.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/mfd/max77620.c b/drivers/mfd/max77620.c
index 0b1e9340210b5..cbd2297126f04 100644
--- a/drivers/mfd/max77620.c
+++ b/drivers/mfd/max77620.c
@@ -576,7 +576,6 @@ static int max77620_probe(struct i2c_client *client)
 	return 0;
 }
 
-#ifdef CONFIG_PM_SLEEP
 static int max77620_set_fps_period(struct max77620_chip *chip,
 				   int fps_id, int time_period)
 {
@@ -683,7 +682,6 @@ out:
 
 	return 0;
 }
-#endif
 
 static const struct i2c_device_id max77620_id[] = {
 	{"max77620", MAX77620},
@@ -692,14 +690,13 @@ static const struct i2c_device_id max77620_id[] = {
 	{},
 };
 
-static const struct dev_pm_ops max77620_pm_ops = {
-	SET_SYSTEM_SLEEP_PM_OPS(max77620_i2c_suspend, max77620_i2c_resume)
-};
+static DEFINE_SIMPLE_DEV_PM_OPS(max77620_pm_ops,
+				max77620_i2c_suspend, max77620_i2c_resume);
 
 static struct i2c_driver max77620_driver = {
 	.driver = {
 		.name = "max77620",
-		.pm = &max77620_pm_ops,
+		.pm = pm_sleep_ptr(&max77620_pm_ops),
 	},
 	.probe_new = max77620_probe,
 	.id_table = max77620_id,
-- 
GitLab


From daf7ea817fda9e5094082a1dd99227001f7ef861 Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:42 +0100
Subject: [PATCH 291/875] mfd: t7l66xb: Remove #ifdef guards for PM related
 functions

Use the new pm_sleep_ptr() macro to handle the .suspend/.resume
callbacks.

This macro allow the suspend and resume functions to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/t7l66xb.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/mfd/t7l66xb.c b/drivers/mfd/t7l66xb.c
index 663ffd4b85706..1d9d1d38d0689 100644
--- a/drivers/mfd/t7l66xb.c
+++ b/drivers/mfd/t7l66xb.c
@@ -257,7 +257,6 @@ static void t7l66xb_detach_irq(struct platform_device *dev)
 
 /*--------------------------------------------------------------------------*/
 
-#ifdef CONFIG_PM
 static int t7l66xb_suspend(struct platform_device *dev, pm_message_t state)
 {
 	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
@@ -288,10 +287,6 @@ static int t7l66xb_resume(struct platform_device *dev)
 
 	return 0;
 }
-#else
-#define t7l66xb_suspend NULL
-#define t7l66xb_resume	NULL
-#endif
 
 /*--------------------------------------------------------------------------*/
 
@@ -416,8 +411,8 @@ static struct platform_driver t7l66xb_platform_driver = {
 	.driver = {
 		.name	= "t7l66xb",
 	},
-	.suspend	= t7l66xb_suspend,
-	.resume		= t7l66xb_resume,
+	.suspend	= pm_sleep_ptr(t7l66xb_suspend),
+	.resume		= pm_sleep_ptr(t7l66xb_resume),
 	.probe		= t7l66xb_probe,
 	.remove		= t7l66xb_remove,
 };
-- 
GitLab


From 50d3ac7d3ce472801c4c0b3f8705b943657a6552 Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:43 +0100
Subject: [PATCH 292/875] mfd: arizona: Remove #ifdef guards for PM related
 functions

Only export the arizona_pm_ops if CONFIG_PM is set, but leave the
suspend/resume functions (and related code) outside #ifdef guards.

If CONFIG_PM is not set, the arizona_pm_ops will be defined as
"static __maybe_unused", and the structure plus all the callbacks will
be automatically dropped by the compiler.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/arizona-core.c | 19 +++++++------------
 drivers/mfd/arizona-i2c.c  |  2 +-
 drivers/mfd/arizona-spi.c  |  2 +-
 3 files changed, 9 insertions(+), 14 deletions(-)

diff --git a/drivers/mfd/arizona-core.c b/drivers/mfd/arizona-core.c
index cbf1dd90b70d5..bd7ee3260d53f 100644
--- a/drivers/mfd/arizona-core.c
+++ b/drivers/mfd/arizona-core.c
@@ -480,7 +480,6 @@ static int wm5102_clear_write_sequencer(struct arizona *arizona)
 	return 0;
 }
 
-#ifdef CONFIG_PM
 static int arizona_isolate_dcvdd(struct arizona *arizona)
 {
 	int ret;
@@ -742,9 +741,7 @@ static int arizona_runtime_suspend(struct device *dev)
 
 	return 0;
 }
-#endif
 
-#ifdef CONFIG_PM_SLEEP
 static int arizona_suspend(struct device *dev)
 {
 	struct arizona *arizona = dev_get_drvdata(dev);
@@ -784,17 +781,15 @@ static int arizona_resume(struct device *dev)
 
 	return 0;
 }
-#endif
 
-const struct dev_pm_ops arizona_pm_ops = {
-	SET_RUNTIME_PM_OPS(arizona_runtime_suspend,
-			   arizona_runtime_resume,
-			   NULL)
-	SET_SYSTEM_SLEEP_PM_OPS(arizona_suspend, arizona_resume)
-	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(arizona_suspend_noirq,
-				      arizona_resume_noirq)
+EXPORT_GPL_DEV_PM_OPS(arizona_pm_ops) = {
+	RUNTIME_PM_OPS(arizona_runtime_suspend,
+		       arizona_runtime_resume,
+		       NULL)
+	SYSTEM_SLEEP_PM_OPS(arizona_suspend, arizona_resume)
+	NOIRQ_SYSTEM_SLEEP_PM_OPS(arizona_suspend_noirq,
+				  arizona_resume_noirq)
 };
-EXPORT_SYMBOL_GPL(arizona_pm_ops);
 
 #ifdef CONFIG_OF
 static int arizona_of_get_core_pdata(struct arizona *arizona)
diff --git a/drivers/mfd/arizona-i2c.c b/drivers/mfd/arizona-i2c.c
index 20dd1b1e4ec15..b2301586adbc5 100644
--- a/drivers/mfd/arizona-i2c.c
+++ b/drivers/mfd/arizona-i2c.c
@@ -117,7 +117,7 @@ static const struct of_device_id arizona_i2c_of_match[] = {
 static struct i2c_driver arizona_i2c_driver = {
 	.driver = {
 		.name	= "arizona",
-		.pm	= &arizona_pm_ops,
+		.pm	= pm_ptr(&arizona_pm_ops),
 		.of_match_table	= of_match_ptr(arizona_i2c_of_match),
 	},
 	.probe_new	= arizona_i2c_probe,
diff --git a/drivers/mfd/arizona-spi.c b/drivers/mfd/arizona-spi.c
index 941b0267d09d4..da05b966d48c6 100644
--- a/drivers/mfd/arizona-spi.c
+++ b/drivers/mfd/arizona-spi.c
@@ -282,7 +282,7 @@ static const struct of_device_id arizona_spi_of_match[] = {
 static struct spi_driver arizona_spi_driver = {
 	.driver = {
 		.name	= "arizona",
-		.pm	= &arizona_pm_ops,
+		.pm	= pm_ptr(&arizona_pm_ops),
 		.of_match_table	= of_match_ptr(arizona_spi_of_match),
 		.acpi_match_table = ACPI_PTR(arizona_acpi_match),
 	},
-- 
GitLab


From 8a8d0485f579120f464193efd8a1ebc96b32fc8b Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:44 +0100
Subject: [PATCH 293/875] mfd: max14577: Remove #ifdef guards for PM related
 functions

Use the new DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr() macros
to handle the .suspend/.resume callbacks.

These macros allow the suspend and resume functions to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/max14577.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/mfd/max14577.c b/drivers/mfd/max14577.c
index 11211039ed901..c598226373385 100644
--- a/drivers/mfd/max14577.c
+++ b/drivers/mfd/max14577.c
@@ -480,7 +480,6 @@ static const struct i2c_device_id max14577_i2c_id[] = {
 };
 MODULE_DEVICE_TABLE(i2c, max14577_i2c_id);
 
-#ifdef CONFIG_PM_SLEEP
 static int max14577_suspend(struct device *dev)
 {
 	struct i2c_client *i2c = to_i2c_client(dev);
@@ -513,14 +512,13 @@ static int max14577_resume(struct device *dev)
 
 	return 0;
 }
-#endif /* CONFIG_PM_SLEEP */
 
-static SIMPLE_DEV_PM_OPS(max14577_pm, max14577_suspend, max14577_resume);
+static DEFINE_SIMPLE_DEV_PM_OPS(max14577_pm, max14577_suspend, max14577_resume);
 
 static struct i2c_driver max14577_i2c_driver = {
 	.driver = {
 		.name = "max14577",
-		.pm = &max14577_pm,
+		.pm = pm_sleep_ptr(&max14577_pm),
 		.of_match_table = max14577_dt_match,
 	},
 	.probe_new = max14577_i2c_probe,
-- 
GitLab


From ef72ed420ea16fa21680a262bc40a5592994a46e Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:45 +0100
Subject: [PATCH 294/875] mfd: max77686: Remove #ifdef guards for PM related
 functions

Use the new DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr() macros
to handle the .suspend/.resume callbacks.

These macros allow the suspend and resume functions to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/max77686.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/mfd/max77686.c b/drivers/mfd/max77686.c
index 2ac64277fb846..f8e863f3fc958 100644
--- a/drivers/mfd/max77686.c
+++ b/drivers/mfd/max77686.c
@@ -226,7 +226,6 @@ static int max77686_i2c_probe(struct i2c_client *i2c)
 	return 0;
 }
 
-#ifdef CONFIG_PM_SLEEP
 static int max77686_suspend(struct device *dev)
 {
 	struct i2c_client *i2c = to_i2c_client(dev);
@@ -261,14 +260,13 @@ static int max77686_resume(struct device *dev)
 
 	return 0;
 }
-#endif /* CONFIG_PM_SLEEP */
 
-static SIMPLE_DEV_PM_OPS(max77686_pm, max77686_suspend, max77686_resume);
+static DEFINE_SIMPLE_DEV_PM_OPS(max77686_pm, max77686_suspend, max77686_resume);
 
 static struct i2c_driver max77686_i2c_driver = {
 	.driver = {
 		   .name = "max77686",
-		   .pm = &max77686_pm,
+		   .pm = pm_sleep_ptr(&max77686_pm),
 		   .of_match_table = max77686_pmic_dt_match,
 	},
 	.probe_new = max77686_i2c_probe,
-- 
GitLab


From 4060c6e50a77a70bf7b7ff3a3aaaa8b1828ec7b6 Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:46 +0100
Subject: [PATCH 295/875] mfd: motorola-cpcap: Remove #ifdef guards for PM
 related functions

Use the new DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr() macros
to handle the .suspend/.resume callbacks.

These macros allow the suspend and resume functions to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/motorola-cpcap.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/mfd/motorola-cpcap.c b/drivers/mfd/motorola-cpcap.c
index 265464b5d7cc5..ae8930eff72d5 100644
--- a/drivers/mfd/motorola-cpcap.c
+++ b/drivers/mfd/motorola-cpcap.c
@@ -221,7 +221,6 @@ static const struct regmap_config cpcap_regmap_config = {
 	.val_format_endian = REGMAP_ENDIAN_LITTLE,
 };
 
-#ifdef CONFIG_PM_SLEEP
 static int cpcap_suspend(struct device *dev)
 {
 	struct spi_device *spi = to_spi_device(dev);
@@ -239,9 +238,8 @@ static int cpcap_resume(struct device *dev)
 
 	return 0;
 }
-#endif
 
-static SIMPLE_DEV_PM_OPS(cpcap_pm, cpcap_suspend, cpcap_resume);
+static DEFINE_SIMPLE_DEV_PM_OPS(cpcap_pm, cpcap_suspend, cpcap_resume);
 
 static const struct mfd_cell cpcap_mfd_devices[] = {
 	{
@@ -346,7 +344,7 @@ static struct spi_driver cpcap_driver = {
 	.driver = {
 		.name = "cpcap-core",
 		.of_match_table = cpcap_of_match,
-		.pm = &cpcap_pm,
+		.pm = pm_sleep_ptr(&cpcap_pm),
 	},
 	.probe = cpcap_probe,
 	.id_table = cpcap_spi_ids,
-- 
GitLab


From 69bbab91835acb4d1f64b2f488b379116c1c49b5 Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:47 +0100
Subject: [PATCH 296/875] mfd: sprd-sc27xx: Remove #ifdef guards for PM related
 functions

Use the new DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr() macros
to handle the .suspend/.resume callbacks.

These macros allow the suspend and resume functions to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/sprd-sc27xx-spi.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/mfd/sprd-sc27xx-spi.c b/drivers/mfd/sprd-sc27xx-spi.c
index d05a47c5187f9..ea68d73e5d1ce 100644
--- a/drivers/mfd/sprd-sc27xx-spi.c
+++ b/drivers/mfd/sprd-sc27xx-spi.c
@@ -215,7 +215,6 @@ static int sprd_pmic_probe(struct spi_device *spi)
 	return 0;
 }
 
-#ifdef CONFIG_PM_SLEEP
 static int sprd_pmic_suspend(struct device *dev)
 {
 	struct sprd_pmic *ddata = dev_get_drvdata(dev);
@@ -235,9 +234,9 @@ static int sprd_pmic_resume(struct device *dev)
 
 	return 0;
 }
-#endif
 
-static SIMPLE_DEV_PM_OPS(sprd_pmic_pm_ops, sprd_pmic_suspend, sprd_pmic_resume);
+static DEFINE_SIMPLE_DEV_PM_OPS(sprd_pmic_pm_ops,
+				sprd_pmic_suspend, sprd_pmic_resume);
 
 static const struct of_device_id sprd_pmic_match[] = {
 	{ .compatible = "sprd,sc2730", .data = &sc2730_data },
@@ -257,7 +256,7 @@ static struct spi_driver sprd_pmic_driver = {
 	.driver = {
 		.name = "sc27xx-pmic",
 		.of_match_table = sprd_pmic_match,
-		.pm = &sprd_pmic_pm_ops,
+		.pm = pm_sleep_ptr(&sprd_pmic_pm_ops),
 	},
 	.probe = sprd_pmic_probe,
 	.id_table = sprd_pmic_spi_ids,
-- 
GitLab


From 4d8a6ae23af64a37803c0d15922819d27b4b8b08 Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:48 +0100
Subject: [PATCH 297/875] mfd: stmfx: Remove #ifdef guards for PM related
 functions

Use the new DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr() macros
to handle the .suspend/.resume callbacks.

These macros allow the suspend and resume functions to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/stmfx.c       | 6 ++----
 include/linux/mfd/stmfx.h | 2 --
 2 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/mfd/stmfx.c b/drivers/mfd/stmfx.c
index 025b8761e50fb..e281971ba54ed 100644
--- a/drivers/mfd/stmfx.c
+++ b/drivers/mfd/stmfx.c
@@ -473,7 +473,6 @@ static void stmfx_remove(struct i2c_client *client)
 	stmfx_chip_exit(client);
 }
 
-#ifdef CONFIG_PM_SLEEP
 static int stmfx_suspend(struct device *dev)
 {
 	struct stmfx *stmfx = dev_get_drvdata(dev);
@@ -539,9 +538,8 @@ static int stmfx_resume(struct device *dev)
 
 	return 0;
 }
-#endif
 
-static SIMPLE_DEV_PM_OPS(stmfx_dev_pm_ops, stmfx_suspend, stmfx_resume);
+static DEFINE_SIMPLE_DEV_PM_OPS(stmfx_dev_pm_ops, stmfx_suspend, stmfx_resume);
 
 static const struct of_device_id stmfx_of_match[] = {
 	{ .compatible = "st,stmfx-0300", },
@@ -553,7 +551,7 @@ static struct i2c_driver stmfx_driver = {
 	.driver = {
 		.name = "stmfx-core",
 		.of_match_table = stmfx_of_match,
-		.pm = &stmfx_dev_pm_ops,
+		.pm = pm_sleep_ptr(&stmfx_dev_pm_ops),
 	},
 	.probe_new = stmfx_probe,
 	.remove = stmfx_remove,
diff --git a/include/linux/mfd/stmfx.h b/include/linux/mfd/stmfx.h
index 744dce63946e0..967a2e486800d 100644
--- a/include/linux/mfd/stmfx.h
+++ b/include/linux/mfd/stmfx.h
@@ -113,10 +113,8 @@ struct stmfx {
 	struct irq_domain *irq_domain;
 	struct mutex lock; /* IRQ bus lock */
 	u8 irq_src;
-#ifdef CONFIG_PM
 	u8 bkp_sysctrl;
 	u8 bkp_irqoutpin;
-#endif
 };
 
 int stmfx_function_enable(struct stmfx *stmfx, u32 func);
-- 
GitLab


From f7f292fe819b6c754836923e126ec27c29be2d07 Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:49 +0100
Subject: [PATCH 298/875] mfd: stmpe: Remove #ifdef guards for PM related
 functions

Use the new EXPORT_GPL_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr() macros
to handle the .suspend/.resume callbacks.

These macros allow the suspend and resume functions to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/stmpe-i2c.c | 4 +---
 drivers/mfd/stmpe-spi.c | 4 +---
 drivers/mfd/stmpe.c     | 8 ++------
 3 files changed, 4 insertions(+), 12 deletions(-)

diff --git a/drivers/mfd/stmpe-i2c.c b/drivers/mfd/stmpe-i2c.c
index 624e3d421b9fc..d4944fc1feb18 100644
--- a/drivers/mfd/stmpe-i2c.c
+++ b/drivers/mfd/stmpe-i2c.c
@@ -115,9 +115,7 @@ MODULE_DEVICE_TABLE(i2c, stmpe_i2c_id);
 static struct i2c_driver stmpe_i2c_driver = {
 	.driver = {
 		.name = "stmpe-i2c",
-#ifdef CONFIG_PM
-		.pm = &stmpe_dev_pm_ops,
-#endif
+		.pm = pm_sleep_ptr(&stmpe_dev_pm_ops),
 		.of_match_table = stmpe_of_match,
 	},
 	.probe_new	= stmpe_i2c_probe,
diff --git a/drivers/mfd/stmpe-spi.c b/drivers/mfd/stmpe-spi.c
index ad8055a0e2869..e9cbf33502b3d 100644
--- a/drivers/mfd/stmpe-spi.c
+++ b/drivers/mfd/stmpe-spi.c
@@ -135,9 +135,7 @@ static struct spi_driver stmpe_spi_driver = {
 	.driver = {
 		.name	= "stmpe-spi",
 		.of_match_table = of_match_ptr(stmpe_spi_of_match),
-#ifdef CONFIG_PM
-		.pm	= &stmpe_dev_pm_ops,
-#endif
+		.pm	= pm_sleep_ptr(&stmpe_dev_pm_ops),
 	},
 	.probe		= stmpe_spi_probe,
 	.remove		= stmpe_spi_remove,
diff --git a/drivers/mfd/stmpe.c b/drivers/mfd/stmpe.c
index 0c4f74197d3e0..c304d20bb988a 100644
--- a/drivers/mfd/stmpe.c
+++ b/drivers/mfd/stmpe.c
@@ -1495,7 +1495,6 @@ void stmpe_remove(struct stmpe *stmpe)
 	mfd_remove_devices(stmpe->dev);
 }
 
-#ifdef CONFIG_PM
 static int stmpe_suspend(struct device *dev)
 {
 	struct stmpe *stmpe = dev_get_drvdata(dev);
@@ -1516,8 +1515,5 @@ static int stmpe_resume(struct device *dev)
 	return 0;
 }
 
-const struct dev_pm_ops stmpe_dev_pm_ops = {
-	.suspend	= stmpe_suspend,
-	.resume		= stmpe_resume,
-};
-#endif
+EXPORT_GPL_SIMPLE_DEV_PM_OPS(stmpe_dev_pm_ops,
+			     stmpe_suspend, stmpe_resume);
-- 
GitLab


From 02313a90095fb919d9e5e166458f73a5f7bf915c Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:50 +0100
Subject: [PATCH 299/875] mfd: tc3589x: Remove #ifdef guards for PM related
 functions

Use the new DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr() macros
to handle the .suspend/.resume callbacks.

These macros allow the suspend and resume functions to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/tc3589x.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/mfd/tc3589x.c b/drivers/mfd/tc3589x.c
index b0f4fff5872dd..1f6e0d682cd9f 100644
--- a/drivers/mfd/tc3589x.c
+++ b/drivers/mfd/tc3589x.c
@@ -436,7 +436,6 @@ static void tc3589x_remove(struct i2c_client *client)
 	mfd_remove_devices(tc3589x->dev);
 }
 
-#ifdef CONFIG_PM_SLEEP
 static int tc3589x_suspend(struct device *dev)
 {
 	struct tc3589x *tc3589x = dev_get_drvdata(dev);
@@ -464,9 +463,9 @@ static int tc3589x_resume(struct device *dev)
 
 	return ret;
 }
-#endif
 
-static SIMPLE_DEV_PM_OPS(tc3589x_dev_pm_ops, tc3589x_suspend, tc3589x_resume);
+static DEFINE_SIMPLE_DEV_PM_OPS(tc3589x_dev_pm_ops,
+				tc3589x_suspend, tc3589x_resume);
 
 static const struct i2c_device_id tc3589x_id[] = {
 	{ "tc35890", TC3589X_TC35890 },
@@ -483,7 +482,7 @@ MODULE_DEVICE_TABLE(i2c, tc3589x_id);
 static struct i2c_driver tc3589x_driver = {
 	.driver = {
 		.name	= "tc3589x",
-		.pm	= &tc3589x_dev_pm_ops,
+		.pm	= pm_sleep_ptr(&tc3589x_dev_pm_ops),
 		.of_match_table = of_match_ptr(tc3589x_match),
 	},
 	.probe_new	= tc3589x_probe,
-- 
GitLab


From 6fed0c1e6efad3494dad90fb7c5e167b7b5317b1 Mon Sep 17 00:00:00 2001
From: Paul Cercueil <paul@crapouillou.net>
Date: Sun, 23 Oct 2022 10:48:51 +0100
Subject: [PATCH 300/875] mfd: tc6393xb: Remove #ifdef guards for PM related
 functions

Use the new pm_sleep_ptr() macro to handle the .suspend/.resume
callbacks.

This macro allow the suspend and resume functions to be automatically
dropped by the compiler when CONFIG_SUSPEND is disabled, without having
to use #ifdef guards.

This has the advantage of always compiling these functions in,
independently of any Kconfig option. Thanks to that, bugs and other
regressions are subsequently easier to catch.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/mfd/tc6393xb.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/mfd/tc6393xb.c b/drivers/mfd/tc6393xb.c
index aa903a31dd433..997bb8b5881de 100644
--- a/drivers/mfd/tc6393xb.c
+++ b/drivers/mfd/tc6393xb.c
@@ -813,7 +813,6 @@ static int tc6393xb_remove(struct platform_device *dev)
 	return 0;
 }
 
-#ifdef CONFIG_PM
 static int tc6393xb_suspend(struct platform_device *dev, pm_message_t state)
 {
 	struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev);
@@ -876,16 +875,12 @@ static int tc6393xb_resume(struct platform_device *dev)
 
 	return 0;
 }
-#else
-#define tc6393xb_suspend NULL
-#define tc6393xb_resume NULL
-#endif
 
 static struct platform_driver tc6393xb_driver = {
 	.probe = tc6393xb_probe,
 	.remove = tc6393xb_remove,
-	.suspend = tc6393xb_suspend,
-	.resume = tc6393xb_resume,
+	.suspend = pm_sleep_ptr(tc6393xb_suspend),
+	.resume = pm_sleep_ptr(tc6393xb_resume),
 
 	.driver = {
 		.name = "tc6393xb",
-- 
GitLab


From 2d51f03536c6fc19ed8489f65fabefeae1546a09 Mon Sep 17 00:00:00 2001
From: Thomas Gleixner <tglx@linutronix.de>
Date: Sun, 13 Nov 2022 21:33:56 +0100
Subject: [PATCH 301/875] mfd: timberdale: Remove linux/msi.h include

Nothing in this file needs anything from linux/msi.h

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221113202428.312137892@linutronix.de
---
 drivers/mfd/timberdale.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/mfd/timberdale.c b/drivers/mfd/timberdale.c
index 9393ee60a656c..07e5aa10a146f 100644
--- a/drivers/mfd/timberdale.c
+++ b/drivers/mfd/timberdale.c
@@ -11,7 +11,6 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/pci.h>
-#include <linux/msi.h>
 #include <linux/mfd/core.h>
 #include <linux/slab.h>
 
-- 
GitLab


From ba215dd650c50fee321bb47af94fb689cb3cf776 Mon Sep 17 00:00:00 2001
From: Luca Weiss <luca@z3ntu.xyz>
Date: Mon, 31 Oct 2022 18:39:31 +0100
Subject: [PATCH 302/875] dt-bindings: mfd: qcom,spmi-pmic: Support more types

* 'adc@' is either spmi-iadc or spmi-vadc
* 'charger@' is either pm8941-charger or pm8941-coincell
* 'usb-vbus-regulator@' is usb-vbus-regulator
* 'vibrator@' is now in yaml format, so add it

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221031173933.936147-1-luca@z3ntu.xyz
---
 .../devicetree/bindings/mfd/qcom,spmi-pmic.yaml  | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
index c8362efd43454..8d9fbc2789182 100644
--- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
+++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
@@ -105,7 +105,9 @@ properties:
 patternProperties:
   "^adc@[0-9a-f]+$":
     type: object
-    $ref: /schemas/iio/adc/qcom,spmi-vadc.yaml#
+    oneOf:
+      - $ref: /schemas/iio/adc/qcom,spmi-iadc.yaml#
+      - $ref: /schemas/iio/adc/qcom,spmi-vadc.yaml#
 
   "^adc-tm@[0-9a-f]+$":
     type: object
@@ -115,6 +117,12 @@ patternProperties:
     type: object
     additionalProperties: true # FIXME qcom,pm8916-wcd-analog-codec binding not converted yet
 
+  "^charger@[0-9a-f]+$":
+    type: object
+    oneOf:
+      - $ref: /schemas/power/supply/qcom,pm8941-charger.yaml#
+      - $ref: /schemas/power/supply/qcom,pm8941-coincell.yaml#
+
   "extcon@[0-9a-f]+$":
     type: object
     $ref: /schemas/extcon/qcom,pm8941-misc.yaml#
@@ -135,9 +143,13 @@ patternProperties:
     type: object
     $ref: /schemas/thermal/qcom,spmi-temp-alarm.yaml#
 
+  "^usb-vbus-regulator@[0-9a-f]+$":
+    type: object
+    $ref: /schemas/regulator/qcom,usb-vbus-regulator.yaml#
+
   "^vibrator@[0-9a-f]+$":
     type: object
-    additionalProperties: true # FIXME qcom,pm8916-vib binding not converted yet
+    $ref: /schemas/input/qcom,pm8xxx-vib.yaml#
 
   "^mpps@[0-9a-f]+$":
     type: object
-- 
GitLab


From 0867c49146c2145ecfb07d6d03071cdbeae9b6e1 Mon Sep 17 00:00:00 2001
From: Luca Weiss <luca@z3ntu.xyz>
Date: Mon, 31 Oct 2022 18:57:14 +0100
Subject: [PATCH 303/875] dt-bindings: mfd: qcom,spmi-pmic: Rename extcon node
 name

extcon is a Linux-specific name and shouldn't be a part of the dts. Make
it be called usb-detect@ instead.

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221031175717.942237-1-luca@z3ntu.xyz
---
 Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
index 8d9fbc2789182..a5e69836dcef9 100644
--- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
+++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
@@ -123,10 +123,6 @@ patternProperties:
       - $ref: /schemas/power/supply/qcom,pm8941-charger.yaml#
       - $ref: /schemas/power/supply/qcom,pm8941-coincell.yaml#
 
-  "extcon@[0-9a-f]+$":
-    type: object
-    $ref: /schemas/extcon/qcom,pm8941-misc.yaml#
-
   "gpio@[0-9a-f]+$":
     type: object
     $ref: /schemas/pinctrl/qcom,pmic-gpio.yaml#
@@ -143,6 +139,10 @@ patternProperties:
     type: object
     $ref: /schemas/thermal/qcom,spmi-temp-alarm.yaml#
 
+  "^usb-detect@[0-9a-f]+$":
+    type: object
+    $ref: /schemas/extcon/qcom,pm8941-misc.yaml#
+
   "^usb-vbus-regulator@[0-9a-f]+$":
     type: object
     $ref: /schemas/regulator/qcom,usb-vbus-regulator.yaml#
-- 
GitLab


From 0eeb2ddcb41502b6a4330646a9b3f0f80e4827b4 Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Date: Sat, 12 Nov 2022 15:18:18 +0000
Subject: [PATCH 304/875] mfd: 88pm800: Replace irqchip mask_invert with
 unmask_base

Remove use of the deprecated mask_invert flag. Inverted mask
registers (where a '1' bit enables an IRQ) can be described more
directly as an unmask register.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221112151835.39059-2-aidanmacdonald.0x0@gmail.com
---
 drivers/mfd/88pm800.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/mfd/88pm800.c b/drivers/mfd/88pm800.c
index 4d139cc31c25f..4d9b61b927544 100644
--- a/drivers/mfd/88pm800.c
+++ b/drivers/mfd/88pm800.c
@@ -398,9 +398,8 @@ static struct regmap_irq_chip pm800_irq_chip = {
 
 	.num_regs = 4,
 	.status_base = PM800_INT_STATUS1,
-	.mask_base = PM800_INT_ENA_1,
+	.unmask_base = PM800_INT_ENA_1,
 	.ack_base = PM800_INT_STATUS1,
-	.mask_invert = 1,
 };
 
 static int pm800_pages_init(struct pm80x_chip *chip)
-- 
GitLab


From 3db3b9a5cbcc9e96a489bca9f2f07e0193ba8e93 Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Date: Sat, 12 Nov 2022 15:18:19 +0000
Subject: [PATCH 305/875] mfd: atc260x: Replace irqchip mask_invert with
 unmask_base

Remove use of the deprecated mask_invert flag. Inverted mask
registers (where a '1' bit enables an IRQ) can be described more
directly as an unmask register.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221112151835.39059-3-aidanmacdonald.0x0@gmail.com
---
 drivers/mfd/atc260x-core.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/mfd/atc260x-core.c b/drivers/mfd/atc260x-core.c
index 7148ff5b05b17..7c5de3ae776e5 100644
--- a/drivers/mfd/atc260x-core.c
+++ b/drivers/mfd/atc260x-core.c
@@ -100,8 +100,7 @@ static const struct regmap_irq_chip atc2603c_regmap_irq_chip = {
 	.num_irqs = ARRAY_SIZE(atc2603c_regmap_irqs),
 	.num_regs = 1,
 	.status_base = ATC2603C_INTS_PD,
-	.mask_base = ATC2603C_INTS_MSK,
-	.mask_invert = true,
+	.unmask_base = ATC2603C_INTS_MSK,
 };
 
 static const struct regmap_irq_chip atc2609a_regmap_irq_chip = {
@@ -110,8 +109,7 @@ static const struct regmap_irq_chip atc2609a_regmap_irq_chip = {
 	.num_irqs = ARRAY_SIZE(atc2609a_regmap_irqs),
 	.num_regs = 1,
 	.status_base = ATC2609A_INTS_PD,
-	.mask_base = ATC2609A_INTS_MSK,
-	.mask_invert = true,
+	.unmask_base = ATC2609A_INTS_MSK,
 };
 
 static const struct resource atc2603c_onkey_resources[] = {
-- 
GitLab


From acc247b2870cb5bccf6dadd5c2686a1d8d1275e0 Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Date: Sat, 12 Nov 2022 15:18:20 +0000
Subject: [PATCH 306/875] mfd: axp20x: Replace irqchip mask_invert with
 unmask_base

Remove use of the deprecated mask_invert flag. Inverted mask
registers (where a '1' bit enables an IRQ) can be described more
directly as an unmask register.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221112151835.39059-4-aidanmacdonald.0x0@gmail.com
---
 drivers/mfd/axp20x.c | 21 +++++++--------------
 1 file changed, 7 insertions(+), 14 deletions(-)

diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 880c41fa7021b..47fd700f284f1 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -506,8 +506,7 @@ static const struct regmap_irq_chip axp152_regmap_irq_chip = {
 	.name			= "axp152_irq_chip",
 	.status_base		= AXP152_IRQ1_STATE,
 	.ack_base		= AXP152_IRQ1_STATE,
-	.mask_base		= AXP152_IRQ1_EN,
-	.mask_invert		= true,
+	.unmask_base		= AXP152_IRQ1_EN,
 	.init_ack_masked	= true,
 	.irqs			= axp152_regmap_irqs,
 	.num_irqs		= ARRAY_SIZE(axp152_regmap_irqs),
@@ -518,8 +517,7 @@ static const struct regmap_irq_chip axp20x_regmap_irq_chip = {
 	.name			= "axp20x_irq_chip",
 	.status_base		= AXP20X_IRQ1_STATE,
 	.ack_base		= AXP20X_IRQ1_STATE,
-	.mask_base		= AXP20X_IRQ1_EN,
-	.mask_invert		= true,
+	.unmask_base		= AXP20X_IRQ1_EN,
 	.init_ack_masked	= true,
 	.irqs			= axp20x_regmap_irqs,
 	.num_irqs		= ARRAY_SIZE(axp20x_regmap_irqs),
@@ -531,8 +529,7 @@ static const struct regmap_irq_chip axp22x_regmap_irq_chip = {
 	.name			= "axp22x_irq_chip",
 	.status_base		= AXP20X_IRQ1_STATE,
 	.ack_base		= AXP20X_IRQ1_STATE,
-	.mask_base		= AXP20X_IRQ1_EN,
-	.mask_invert		= true,
+	.unmask_base		= AXP20X_IRQ1_EN,
 	.init_ack_masked	= true,
 	.irqs			= axp22x_regmap_irqs,
 	.num_irqs		= ARRAY_SIZE(axp22x_regmap_irqs),
@@ -543,8 +540,7 @@ static const struct regmap_irq_chip axp288_regmap_irq_chip = {
 	.name			= "axp288_irq_chip",
 	.status_base		= AXP20X_IRQ1_STATE,
 	.ack_base		= AXP20X_IRQ1_STATE,
-	.mask_base		= AXP20X_IRQ1_EN,
-	.mask_invert		= true,
+	.unmask_base		= AXP20X_IRQ1_EN,
 	.init_ack_masked	= true,
 	.irqs			= axp288_regmap_irqs,
 	.num_irqs		= ARRAY_SIZE(axp288_regmap_irqs),
@@ -556,8 +552,7 @@ static const struct regmap_irq_chip axp803_regmap_irq_chip = {
 	.name			= "axp803",
 	.status_base		= AXP20X_IRQ1_STATE,
 	.ack_base		= AXP20X_IRQ1_STATE,
-	.mask_base		= AXP20X_IRQ1_EN,
-	.mask_invert		= true,
+	.unmask_base		= AXP20X_IRQ1_EN,
 	.init_ack_masked	= true,
 	.irqs			= axp803_regmap_irqs,
 	.num_irqs		= ARRAY_SIZE(axp803_regmap_irqs),
@@ -568,8 +563,7 @@ static const struct regmap_irq_chip axp806_regmap_irq_chip = {
 	.name			= "axp806",
 	.status_base		= AXP20X_IRQ1_STATE,
 	.ack_base		= AXP20X_IRQ1_STATE,
-	.mask_base		= AXP20X_IRQ1_EN,
-	.mask_invert		= true,
+	.unmask_base		= AXP20X_IRQ1_EN,
 	.init_ack_masked	= true,
 	.irqs			= axp806_regmap_irqs,
 	.num_irqs		= ARRAY_SIZE(axp806_regmap_irqs),
@@ -580,8 +574,7 @@ static const struct regmap_irq_chip axp809_regmap_irq_chip = {
 	.name			= "axp809",
 	.status_base		= AXP20X_IRQ1_STATE,
 	.ack_base		= AXP20X_IRQ1_STATE,
-	.mask_base		= AXP20X_IRQ1_EN,
-	.mask_invert		= true,
+	.unmask_base		= AXP20X_IRQ1_EN,
 	.init_ack_masked	= true,
 	.irqs			= axp809_regmap_irqs,
 	.num_irqs		= ARRAY_SIZE(axp809_regmap_irqs),
-- 
GitLab


From 3576fc04594989426c61c8b46dfcc986b6f76a22 Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Date: Sat, 12 Nov 2022 15:18:21 +0000
Subject: [PATCH 307/875] mfd: gateworks-gsc: Replace irqchip mask_invert with
 unmask_base

Remove use of the deprecated mask_invert flag. Inverted mask
registers (where a '1' bit enables an IRQ) can be described more
directly as an unmask register.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221112151835.39059-5-aidanmacdonald.0x0@gmail.com
---
 drivers/mfd/gateworks-gsc.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/mfd/gateworks-gsc.c b/drivers/mfd/gateworks-gsc.c
index 9d7d870c44a8c..c954ed265de81 100644
--- a/drivers/mfd/gateworks-gsc.c
+++ b/drivers/mfd/gateworks-gsc.c
@@ -189,8 +189,7 @@ static const struct regmap_irq_chip gsc_irq_chip = {
 	.num_irqs = ARRAY_SIZE(gsc_irqs),
 	.num_regs = 1,
 	.status_base = GSC_IRQ_STATUS,
-	.mask_base = GSC_IRQ_ENABLE,
-	.mask_invert = true,
+	.unmask_base = GSC_IRQ_ENABLE,
 	.ack_base = GSC_IRQ_STATUS,
 	.ack_invert = true,
 };
-- 
GitLab


From 911b8b42242256f53ca210a45580e2c35323e6b9 Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Date: Sat, 12 Nov 2022 15:18:22 +0000
Subject: [PATCH 308/875] mfd: max14577: Replace irqchip mask_invert with
 unmask_base

Remove use of the deprecated mask_invert flag. Inverted mask
registers (where a '1' bit enables an IRQ) can be described more
directly as an unmask register.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221112151835.39059-6-aidanmacdonald.0x0@gmail.com
---
 drivers/mfd/max14577.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/mfd/max14577.c b/drivers/mfd/max14577.c
index c598226373385..0e3731e9e9b59 100644
--- a/drivers/mfd/max14577.c
+++ b/drivers/mfd/max14577.c
@@ -209,8 +209,7 @@ static const struct regmap_irq max14577_irqs[] = {
 static const struct regmap_irq_chip max14577_irq_chip = {
 	.name			= "max14577",
 	.status_base		= MAX14577_REG_INT1,
-	.mask_base		= MAX14577_REG_INTMASK1,
-	.mask_invert		= true,
+	.unmask_base		= MAX14577_REG_INTMASK1,
 	.num_regs		= 3,
 	.irqs			= max14577_irqs,
 	.num_irqs		= ARRAY_SIZE(max14577_irqs),
@@ -239,8 +238,7 @@ static const struct regmap_irq max77836_muic_irqs[] = {
 static const struct regmap_irq_chip max77836_muic_irq_chip = {
 	.name			= "max77836-muic",
 	.status_base		= MAX14577_REG_INT1,
-	.mask_base		= MAX14577_REG_INTMASK1,
-	.mask_invert		= true,
+	.unmask_base		= MAX14577_REG_INTMASK1,
 	.num_regs		= 3,
 	.irqs			= max77836_muic_irqs,
 	.num_irqs		= ARRAY_SIZE(max77836_muic_irqs),
@@ -255,7 +253,6 @@ static const struct regmap_irq_chip max77836_pmic_irq_chip = {
 	.name			= "max77836-pmic",
 	.status_base		= MAX77836_PMIC_REG_TOPSYS_INT,
 	.mask_base		= MAX77836_PMIC_REG_TOPSYS_INT_MASK,
-	.mask_invert		= false,
 	.num_regs		= 1,
 	.irqs			= max77836_pmic_irqs,
 	.num_irqs		= ARRAY_SIZE(max77836_pmic_irqs),
-- 
GitLab


From b171b0b46b2b6441f04c9a800251ebf82ad67f09 Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Date: Sat, 12 Nov 2022 15:18:23 +0000
Subject: [PATCH 309/875] mfd: max77650: Remove useless type_invert flag

The type_invert flag does nothing when type_in_mask is set, and
it's part of deprecated functionality in regmap-irq. Remove it.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221112151835.39059-7-aidanmacdonald.0x0@gmail.com
---
 drivers/mfd/max77650.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/mfd/max77650.c b/drivers/mfd/max77650.c
index 777485a33bc0f..3c07fcdd9d076 100644
--- a/drivers/mfd/max77650.c
+++ b/drivers/mfd/max77650.c
@@ -138,7 +138,6 @@ static const struct regmap_irq_chip max77650_irq_chip = {
 	.status_base		= MAX77650_REG_INT_GLBL,
 	.mask_base		= MAX77650_REG_INTM_GLBL,
 	.type_in_mask		= true,
-	.type_invert		= true,
 	.init_ack_masked	= true,
 	.clear_on_unmask	= true,
 };
-- 
GitLab


From a5ae0a0ccdbc18228de8281dcb185dd647fbedbe Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Date: Sat, 12 Nov 2022 15:18:24 +0000
Subject: [PATCH 310/875] mfd: max77693: Replace irqchip mask_invert with
 unmask_base

Remove use of the deprecated mask_invert flag. Inverted mask
registers (where a '1' bit enables an IRQ) can be described more
directly as an unmask register.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221112151835.39059-8-aidanmacdonald.0x0@gmail.com
---
 drivers/mfd/max77693.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/mfd/max77693.c b/drivers/mfd/max77693.c
index aa32e89b6c8e5..3995e8769f491 100644
--- a/drivers/mfd/max77693.c
+++ b/drivers/mfd/max77693.c
@@ -66,7 +66,6 @@ static const struct regmap_irq_chip max77693_led_irq_chip = {
 	.name			= "max77693-led",
 	.status_base		= MAX77693_LED_REG_FLASH_INT,
 	.mask_base		= MAX77693_LED_REG_FLASH_INT_MASK,
-	.mask_invert		= false,
 	.num_regs		= 1,
 	.irqs			= max77693_led_irqs,
 	.num_irqs		= ARRAY_SIZE(max77693_led_irqs),
@@ -82,7 +81,6 @@ static const struct regmap_irq_chip max77693_topsys_irq_chip = {
 	.name			= "max77693-topsys",
 	.status_base		= MAX77693_PMIC_REG_TOPSYS_INT,
 	.mask_base		= MAX77693_PMIC_REG_TOPSYS_INT_MASK,
-	.mask_invert		= false,
 	.num_regs		= 1,
 	.irqs			= max77693_topsys_irqs,
 	.num_irqs		= ARRAY_SIZE(max77693_topsys_irqs),
@@ -100,7 +98,6 @@ static const struct regmap_irq_chip max77693_charger_irq_chip = {
 	.name			= "max77693-charger",
 	.status_base		= MAX77693_CHG_REG_CHG_INT,
 	.mask_base		= MAX77693_CHG_REG_CHG_INT_MASK,
-	.mask_invert		= false,
 	.num_regs		= 1,
 	.irqs			= max77693_charger_irqs,
 	.num_irqs		= ARRAY_SIZE(max77693_charger_irqs),
@@ -136,8 +133,7 @@ static const struct regmap_irq max77693_muic_irqs[] = {
 static const struct regmap_irq_chip max77693_muic_irq_chip = {
 	.name			= "max77693-muic",
 	.status_base		= MAX77693_MUIC_REG_INT1,
-	.mask_base		= MAX77693_MUIC_REG_INTMASK1,
-	.mask_invert		= true,
+	.unmask_base		= MAX77693_MUIC_REG_INTMASK1,
 	.num_regs		= 3,
 	.irqs			= max77693_muic_irqs,
 	.num_irqs		= ARRAY_SIZE(max77693_muic_irqs),
-- 
GitLab


From ea5718ff3970ba9ff12ae32cbd1ca6c2aa2a895b Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Date: Sat, 12 Nov 2022 15:18:25 +0000
Subject: [PATCH 311/875] mfd: max77843: Drop useless mask_invert flag on
 irqchip

Setting mask_invert to false is pointless because that's the
default. The flag is also deprecated, so drop it.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221112151835.39059-9-aidanmacdonald.0x0@gmail.com
---
 drivers/mfd/max77843.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/mfd/max77843.c b/drivers/mfd/max77843.c
index c6fd93efd5c4e..8ff0723808c8e 100644
--- a/drivers/mfd/max77843.c
+++ b/drivers/mfd/max77843.c
@@ -59,7 +59,6 @@ static const struct regmap_irq_chip max77843_irq_chip = {
 	.name		= "max77843",
 	.status_base	= MAX77843_SYS_REG_SYSINTSRC,
 	.mask_base	= MAX77843_SYS_REG_SYSINTMASK,
-	.mask_invert	= false,
 	.num_regs	= 1,
 	.irqs		= max77843_irqs,
 	.num_irqs	= ARRAY_SIZE(max77843_irqs),
-- 
GitLab


From 80ff2d30c0d1a2c7e51e750a8381342a038890fe Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Date: Sat, 12 Nov 2022 15:18:26 +0000
Subject: [PATCH 312/875] mfd: rn5t618: Replace irqchip mask_invert with
 unmask_base

Remove use of the deprecated mask_invert flag. Inverted mask
registers (where a '1' bit enables an IRQ) can be described more
directly as an unmask register.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221112151835.39059-10-aidanmacdonald.0x0@gmail.com
---
 drivers/mfd/rn5t618.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/mfd/rn5t618.c b/drivers/mfd/rn5t618.c
index eb8005b4e58d3..2f59230749cd9 100644
--- a/drivers/mfd/rn5t618.c
+++ b/drivers/mfd/rn5t618.c
@@ -80,8 +80,7 @@ static const struct regmap_irq_chip rc5t619_irq_chip = {
 	.num_irqs = ARRAY_SIZE(rc5t619_irqs),
 	.num_regs = 1,
 	.status_base = RN5T618_INTMON,
-	.mask_base = RN5T618_INTEN,
-	.mask_invert = true,
+	.unmask_base = RN5T618_INTEN,
 };
 
 static struct i2c_client *rn5t618_pm_power_off;
-- 
GitLab


From cdbecc4c44e9a139651cec531f77a98c0b62d5c6 Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Date: Sat, 12 Nov 2022 15:18:27 +0000
Subject: [PATCH 313/875] mfd: rohm-bd71828: Replace irqchip mask_invert with
 unmask_base

Remove use of the deprecated mask_invert flag. Inverted mask
registers (where a '1' bit enables an IRQ) can be described more
directly as an unmask register.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Reviewed-by: Matti Vaittinen <mazziesaccount@gmail.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221112151835.39059-11-aidanmacdonald.0x0@gmail.com
---
 drivers/mfd/rohm-bd71828.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/mfd/rohm-bd71828.c b/drivers/mfd/rohm-bd71828.c
index 714d9fcbf07b9..3c5c6c3936509 100644
--- a/drivers/mfd/rohm-bd71828.c
+++ b/drivers/mfd/rohm-bd71828.c
@@ -413,9 +413,8 @@ static struct regmap_irq_chip bd71828_irq_chip = {
 	.irqs = &bd71828_irqs[0],
 	.num_irqs = ARRAY_SIZE(bd71828_irqs),
 	.status_base = BD71828_REG_INT_BUCK,
-	.mask_base = BD71828_REG_INT_MASK_BUCK,
+	.unmask_base = BD71828_REG_INT_MASK_BUCK,
 	.ack_base = BD71828_REG_INT_BUCK,
-	.mask_invert = true,
 	.init_ack_masked = true,
 	.num_regs = 12,
 	.num_main_regs = 1,
@@ -430,9 +429,8 @@ static struct regmap_irq_chip bd71815_irq_chip = {
 	.irqs = &bd71815_irqs[0],
 	.num_irqs = ARRAY_SIZE(bd71815_irqs),
 	.status_base = BD71815_REG_INT_STAT_01,
-	.mask_base = BD71815_REG_INT_EN_01,
+	.unmask_base = BD71815_REG_INT_EN_01,
 	.ack_base = BD71815_REG_INT_STAT_01,
-	.mask_invert = true,
 	.init_ack_masked = true,
 	.num_regs = 12,
 	.num_main_regs = 1,
-- 
GitLab


From 3210c7faff513809250567024402934401d91155 Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Date: Sat, 12 Nov 2022 15:18:28 +0000
Subject: [PATCH 314/875] mfd: rohm-bd718x7: Drop useless mask_invert flag on
 irqchip

Setting mask_invert to false is pointless because that's the
default. The flag is also deprecated, so drop it.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Reviewed-by: Matti Vaittinen <mazziesaccount@gmail.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221112151835.39059-12-aidanmacdonald.0x0@gmail.com
---
 drivers/mfd/rohm-bd718x7.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/mfd/rohm-bd718x7.c b/drivers/mfd/rohm-bd718x7.c
index 3c766cb15a24f..b55674d7b7dc2 100644
--- a/drivers/mfd/rohm-bd718x7.c
+++ b/drivers/mfd/rohm-bd718x7.c
@@ -70,7 +70,6 @@ static struct regmap_irq_chip bd718xx_irq_chip = {
 	.mask_base = BD718XX_REG_MIRQ,
 	.ack_base = BD718XX_REG_IRQ,
 	.init_ack_masked = true,
-	.mask_invert = false,
 };
 
 static const struct regmap_range pmic_status_range = {
-- 
GitLab


From 4627ecec79dfa85b02856e89fab152b4a749c091 Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Date: Sat, 12 Nov 2022 15:18:29 +0000
Subject: [PATCH 315/875] mfd: rt5033: Replace irqchip mask_invert with
 unmask_base

Remove use of the deprecated mask_invert flag. Inverted mask
registers (where a '1' bit enables an IRQ) can be described more
directly as an unmask register.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221112151835.39059-13-aidanmacdonald.0x0@gmail.com
---
 drivers/mfd/rt5033.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/mfd/rt5033.c b/drivers/mfd/rt5033.c
index 8bcf1c01348ce..a5e520fe50a14 100644
--- a/drivers/mfd/rt5033.c
+++ b/drivers/mfd/rt5033.c
@@ -29,8 +29,7 @@ static const struct regmap_irq rt5033_irqs[] = {
 static const struct regmap_irq_chip rt5033_irq_chip = {
 	.name		= "rt5033",
 	.status_base	= RT5033_REG_PMIC_IRQ_STAT,
-	.mask_base	= RT5033_REG_PMIC_IRQ_CTRL,
-	.mask_invert	= true,
+	.unmask_base	= RT5033_REG_PMIC_IRQ_CTRL,
 	.num_regs	= 1,
 	.irqs		= rt5033_irqs,
 	.num_irqs	= ARRAY_SIZE(rt5033_irqs),
-- 
GitLab


From cdd13e7260b288fed9ef612f766ba02431947033 Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Date: Sat, 12 Nov 2022 15:18:30 +0000
Subject: [PATCH 316/875] mfd: rt5120: Replace irqchip mask_invert with
 unmask_base

Remove use of the deprecated mask_invert flag. Inverted mask
registers (where a '1' bit enables an IRQ) can be described more
directly as an unmask register.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221112151835.39059-14-aidanmacdonald.0x0@gmail.com
---
 drivers/mfd/rt5120.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/mfd/rt5120.c b/drivers/mfd/rt5120.c
index 8046e383bc92b..829b7a0a0781c 100644
--- a/drivers/mfd/rt5120.c
+++ b/drivers/mfd/rt5120.c
@@ -59,9 +59,8 @@ static const struct regmap_irq rt5120_irqs[] = {
 static const struct regmap_irq_chip rt5120_irq_chip = {
 	.name = "rt5120-pmic",
 	.status_base = RT5120_REG_INTSTAT,
-	.mask_base = RT5120_REG_INTENABLE,
+	.unmask_base = RT5120_REG_INTENABLE,
 	.ack_base = RT5120_REG_INTSTAT,
-	.mask_invert = true,
 	.use_ack = true,
 	.num_regs = 1,
 	.irqs = rt5120_irqs,
-- 
GitLab


From 963cd957694b28e227709608467595d58fcf1605 Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Date: Sat, 12 Nov 2022 15:18:31 +0000
Subject: [PATCH 317/875] mfd: sprd-sc27xx-spi: Replace irqchip mask_invert
 with unmask_base

Remove use of the deprecated mask_invert flag. Inverted mask
registers (where a '1' bit enables an IRQ) can be described more
directly as an unmask register.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221112151835.39059-15-aidanmacdonald.0x0@gmail.com
---
 drivers/mfd/sprd-sc27xx-spi.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/mfd/sprd-sc27xx-spi.c b/drivers/mfd/sprd-sc27xx-spi.c
index ea68d73e5d1ce..d21f32cc784da 100644
--- a/drivers/mfd/sprd-sc27xx-spi.c
+++ b/drivers/mfd/sprd-sc27xx-spi.c
@@ -181,11 +181,10 @@ static int sprd_pmic_probe(struct spi_device *spi)
 	ddata->irq_chip.name = dev_name(&spi->dev);
 	ddata->irq_chip.status_base =
 		pdata->irq_base + SPRD_PMIC_INT_MASK_STATUS;
-	ddata->irq_chip.mask_base = pdata->irq_base + SPRD_PMIC_INT_EN;
+	ddata->irq_chip.unmask_base = pdata->irq_base + SPRD_PMIC_INT_EN;
 	ddata->irq_chip.ack_base = 0;
 	ddata->irq_chip.num_regs = 1;
 	ddata->irq_chip.num_irqs = pdata->num_irqs;
-	ddata->irq_chip.mask_invert = true;
 
 	ddata->irqs = devm_kcalloc(&spi->dev,
 				   pdata->num_irqs, sizeof(struct regmap_irq),
-- 
GitLab


From c79e387389d5add7cb967d2f7622c3bf5550927b Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Date: Sat, 12 Nov 2022 15:18:32 +0000
Subject: [PATCH 318/875] mfd: stpmic1: Fix swapped mask/unmask in irq chip

The usual behavior of mask registers is writing a '1' bit to
disable (mask) an interrupt; similarly, writing a '1' bit to
an unmask register enables (unmasks) an interrupt.

Due to a longstanding issue in regmap-irq, mask and unmask
registers were inverted when both kinds of registers were
present on the same chip, ie. regmap-irq actually wrote '1's
to the mask register to enable an IRQ and '1's to the unmask
register to disable an IRQ.

This was fixed by commit e8ffb12e7f06 ("regmap-irq: Fix
inverted handling of unmask registers") but the fix is opt-in
via mask_unmask_non_inverted = true because it requires manual
changes for each affected driver. The new behavior will become
the default once all drivers have been updated.

The STPMIC1 has a normal mask register with separate set and
clear registers. The driver intends to use the set & clear
registers with regmap-irq and has compensated for regmap-irq's
inverted behavior, and should currently be working properly.
Thus, swap mask_base and unmask_base, and opt in to the new
non-inverted behavior.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221112151835.39059-16-aidanmacdonald.0x0@gmail.com
---
 drivers/mfd/stpmic1.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/mfd/stpmic1.c b/drivers/mfd/stpmic1.c
index 54a4d59d1937b..8db1530d9bacb 100644
--- a/drivers/mfd/stpmic1.c
+++ b/drivers/mfd/stpmic1.c
@@ -108,8 +108,9 @@ static const struct regmap_irq stpmic1_irqs[] = {
 static const struct regmap_irq_chip stpmic1_regmap_irq_chip = {
 	.name = "pmic_irq",
 	.status_base = INT_PENDING_R1,
-	.mask_base = INT_CLEAR_MASK_R1,
-	.unmask_base = INT_SET_MASK_R1,
+	.mask_base = INT_SET_MASK_R1,
+	.unmask_base = INT_CLEAR_MASK_R1,
+	.mask_unmask_non_inverted = true,
 	.ack_base = INT_CLEAR_R1,
 	.num_regs = STPMIC1_PMIC_NUM_IRQ_REGS,
 	.irqs = stpmic1_irqs,
-- 
GitLab


From 8d9ad03265a4f24bcf904dacdd05a451d6e51cd9 Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Date: Sat, 12 Nov 2022 15:18:33 +0000
Subject: [PATCH 319/875] mfd: sun4i-gpadc: Replace irqchip mask_invert with
 unmask_base

Remove use of the deprecated mask_invert flag. Inverted mask
registers (where a '1' bit enables an IRQ) can be described more
directly as an unmask register.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221112151835.39059-17-aidanmacdonald.0x0@gmail.com
---
 drivers/mfd/sun4i-gpadc.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/mfd/sun4i-gpadc.c b/drivers/mfd/sun4i-gpadc.c
index cfe14d9bf6dcd..edc180d83a4b0 100644
--- a/drivers/mfd/sun4i-gpadc.c
+++ b/drivers/mfd/sun4i-gpadc.c
@@ -34,9 +34,8 @@ static const struct regmap_irq_chip sun4i_gpadc_regmap_irq_chip = {
 	.name = "sun4i_gpadc_irq_chip",
 	.status_base = SUN4I_GPADC_INT_FIFOS,
 	.ack_base = SUN4I_GPADC_INT_FIFOS,
-	.mask_base = SUN4I_GPADC_INT_FIFOC,
+	.unmask_base = SUN4I_GPADC_INT_FIFOC,
 	.init_ack_masked = true,
-	.mask_invert = true,
 	.irqs = sun4i_gpadc_regmap_irq,
 	.num_irqs = ARRAY_SIZE(sun4i_gpadc_regmap_irq),
 	.num_regs = 1,
-- 
GitLab


From 50ff095ba366cca51084a4a5eebd600b432e31f0 Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Date: Sat, 12 Nov 2022 15:18:34 +0000
Subject: [PATCH 320/875] mfd: tps65090: Replace irqchip mask_invert with
 unmask_base

Remove use of the deprecated mask_invert flag. Inverted mask
registers (where a '1' bit enables an IRQ) can be described more
directly as an unmask register.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221112151835.39059-18-aidanmacdonald.0x0@gmail.com
---
 drivers/mfd/tps65090.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/mfd/tps65090.c b/drivers/mfd/tps65090.c
index e1f2491a2578d..af718a9c58b33 100644
--- a/drivers/mfd/tps65090.c
+++ b/drivers/mfd/tps65090.c
@@ -127,8 +127,7 @@ static struct regmap_irq_chip tps65090_irq_chip = {
 	.num_irqs = ARRAY_SIZE(tps65090_irqs),
 	.num_regs = NUM_INT_REG,
 	.status_base = TPS65090_REG_INTR_STS,
-	.mask_base = TPS65090_REG_INTR_MASK,
-	.mask_invert = true,
+	.unmask_base = TPS65090_REG_INTR_MASK,
 };
 
 static bool is_volatile_reg(struct device *dev, unsigned int reg)
-- 
GitLab


From 0cd1860e445f668038621aabf6c67616e6d3bb8b Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Date: Sat, 12 Nov 2022 15:18:35 +0000
Subject: [PATCH 321/875] mfd: wcd934x: Convert irq chip to config regs

Type registers are deprecated and will eventually be removed from
regmap-irq. The same functionality can be replicated with config
registers.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221112151835.39059-19-aidanmacdonald.0x0@gmail.com
---
 drivers/mfd/wcd934x.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/wcd934x.c b/drivers/mfd/wcd934x.c
index 68e2fa2fda99c..07e884087f2c7 100644
--- a/drivers/mfd/wcd934x.c
+++ b/drivers/mfd/wcd934x.c
@@ -55,17 +55,22 @@ static const struct regmap_irq wcd934x_irqs[] = {
 	WCD934X_REGMAP_IRQ_REG(WCD934X_IRQ_SOUNDWIRE, 2, BIT(4)),
 };
 
+static const unsigned int wcd934x_config_regs[] = {
+	WCD934X_INTR_LEVEL0,
+};
+
 static const struct regmap_irq_chip wcd934x_regmap_irq_chip = {
 	.name = "wcd934x_irq",
 	.status_base = WCD934X_INTR_PIN1_STATUS0,
 	.mask_base = WCD934X_INTR_PIN1_MASK0,
 	.ack_base = WCD934X_INTR_PIN1_CLEAR0,
-	.type_base = WCD934X_INTR_LEVEL0,
-	.num_type_reg = 4,
-	.type_in_mask = false,
 	.num_regs = 4,
 	.irqs = wcd934x_irqs,
 	.num_irqs = ARRAY_SIZE(wcd934x_irqs),
+	.config_base = wcd934x_config_regs,
+	.num_config_bases = ARRAY_SIZE(wcd934x_config_regs),
+	.num_config_regs = 4,
+	.set_type_config = regmap_irq_set_type_config_simple,
 };
 
 static bool wcd934x_is_volatile_register(struct device *dev, unsigned int reg)
-- 
GitLab


From 85842c46fd47fa6bd78681c154223bed27d5fd19 Mon Sep 17 00:00:00 2001
From: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Date: Wed, 16 Nov 2022 10:19:21 +0200
Subject: [PATCH 322/875] mfd: bd957x: Fix Kconfig dependency on REGMAP_IRQ

The BD957x driver uses REGMAP_IRQ but does not 'select' to depend on
it. This can cause build failures.  Select REGMAP_IRQ for BD957X.

Fixes: 0e9692607f94 ("mfd: bd9576: Add IRQ support")
Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/Y3SdCWkRr1L64SWK@dc75zzyyyyyyyyyyyyydt-3.rev.dnainternet.fi
---
 drivers/mfd/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 6653d03e0fe31..d6f1b0d3d8293 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -2017,6 +2017,7 @@ config MFD_ROHM_BD957XMUF
 	depends on I2C=y
 	depends on OF
 	select REGMAP_I2C
+	select REGMAP_IRQ
 	select MFD_CORE
 	help
 	  Select this option to get support for the ROHM BD9576MUF and
-- 
GitLab


From 74c17a0a49a6ad3b32cb130f25196d1f8d5d560e Mon Sep 17 00:00:00 2001
From: Jerome Neanne <jneanne@baylibre.com>
Date: Fri, 4 Nov 2022 16:23:09 +0100
Subject: [PATCH 323/875] mfd: tps65219: Add driver for TI TPS65219 PMIC

The TPS65219 is a power management IC PMIC designed to supply a wide
range of SoCs in both portable and stationary applications. Any SoC can
control TPS65219 over a standard I2C interface.

It contains the following components:
- Regulators.
- Over Temperature warning and Shut down.
- GPIOs
- Multi Function Pins (MFP)
- power-button

This patch adds support for tps65219 PMIC. At this time only
the functionalities listed below are made available:

- Regulators probe and functionalities
- warm and cold reset support
- SW shutdown support
- Regulator warnings via IRQs
- Power-button via IRQ

Signed-off-by: Jerome Neanne <jneanne@baylibre.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221104152311.1098603-5-jneanne@baylibre.com
---
 MAINTAINERS                  |   1 +
 drivers/mfd/Kconfig          |  14 ++
 drivers/mfd/Makefile         |   1 +
 drivers/mfd/tps65219.c       | 299 ++++++++++++++++++++++++++++++
 include/linux/mfd/tps65219.h | 345 +++++++++++++++++++++++++++++++++++
 5 files changed, 660 insertions(+)
 create mode 100644 drivers/mfd/tps65219.c
 create mode 100644 include/linux/mfd/tps65219.h

diff --git a/MAINTAINERS b/MAINTAINERS
index cf0f185023724..43b7cccbbaa44 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15110,6 +15110,7 @@ F:	drivers/mfd/menelaus.c
 F:	drivers/mfd/palmas.c
 F:	drivers/mfd/tps65217.c
 F:	drivers/mfd/tps65218.c
+F:	drivers/mfd/tps65219.c
 F:	drivers/mfd/tps65910.c
 F:	drivers/mfd/twl-core.[ch]
 F:	drivers/mfd/twl4030*.c
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index d6f1b0d3d8293..2d563277105ca 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1625,6 +1625,20 @@ config MFD_TPS65218
 	  This driver can also be built as a module.  If so, the module
 	  will be called tps65218.
 
+config MFD_TPS65219
+	tristate "TI TPS65219 Power Management IC"
+	depends on I2C && OF
+	select MFD_CORE
+	select REGMAP_I2C
+	select REGMAP_IRQ
+	help
+	  If you say yes here you get support for the TPS65219 series of Power
+	  Management ICs. These include voltage regulators, GPIOs and
+	  push/power button that is often used in portable devices.
+
+	  This driver can also be built as a module. If so, the module
+	  will be called tps65219.
+
 config MFD_TPS6586X
 	bool "TI TPS6586x Power Management chips"
 	depends on I2C=y
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 4dd479212b3ab..457471478a937 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -97,6 +97,7 @@ obj-$(CONFIG_TPS6507X)		+= tps6507x.o
 obj-$(CONFIG_MFD_TPS65086)	+= tps65086.o
 obj-$(CONFIG_MFD_TPS65217)	+= tps65217.o
 obj-$(CONFIG_MFD_TPS65218)	+= tps65218.o
+obj-$(CONFIG_MFD_TPS65219)	+= tps65219.o
 obj-$(CONFIG_MFD_TPS65910)	+= tps65910.o
 obj-$(CONFIG_MFD_TPS65912)	+= tps65912-core.o
 obj-$(CONFIG_MFD_TPS65912_I2C)	+= tps65912-i2c.o
diff --git a/drivers/mfd/tps65219.c b/drivers/mfd/tps65219.c
new file mode 100644
index 0000000000000..0e402fda206bd
--- /dev/null
+++ b/drivers/mfd/tps65219.c
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Driver for TPS65219 Integrated Power Management Integrated Chips (PMIC)
+//
+// Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/
+
+#include <linux/i2c.h>
+#include <linux/reboot.h>
+#include <linux/regmap.h>
+
+#include <linux/mfd/core.h>
+#include <linux/mfd/tps65219.h>
+
+static int tps65219_warm_reset(struct tps65219 *tps)
+{
+	return regmap_update_bits(tps->regmap, TPS65219_REG_MFP_CTRL,
+				  TPS65219_MFP_WARM_RESET_I2C_CTRL_MASK,
+				  TPS65219_MFP_WARM_RESET_I2C_CTRL_MASK);
+}
+
+static int tps65219_cold_reset(struct tps65219 *tps)
+{
+	return regmap_update_bits(tps->regmap, TPS65219_REG_MFP_CTRL,
+				  TPS65219_MFP_COLD_RESET_I2C_CTRL_MASK,
+				  TPS65219_MFP_COLD_RESET_I2C_CTRL_MASK);
+}
+
+static int tps65219_restart(struct notifier_block *this,
+			    unsigned long reboot_mode, void *cmd)
+{
+	struct tps65219 *tps;
+
+	tps = container_of(this, struct tps65219, nb);
+
+	if (reboot_mode == REBOOT_WARM)
+		tps65219_warm_reset(tps);
+	else
+		tps65219_cold_reset(tps);
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block pmic_rst_restart_nb = {
+	.notifier_call = tps65219_restart,
+	.priority = 200,
+};
+
+static const struct resource tps65219_pwrbutton_resources[] = {
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_PB_FALLING_EDGE_DETECT, "falling"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_PB_RISING_EDGE_DETECT, "rising"),
+};
+
+static const struct resource tps65219_regulator_resources[] = {
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO3_SCG, "LDO3_SCG"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO3_OC, "LDO3_OC"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO3_UV, "LDO3_UV"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO4_SCG, "LDO4_SCG"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO4_OC, "LDO4_OC"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO4_UV, "LDO4_UV"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_SCG, "LDO1_SCG"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_OC, "LDO1_OC"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_UV, "LDO1_UV"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_SCG, "LDO2_SCG"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_OC, "LDO2_OC"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_UV, "LDO2_UV"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_SCG, "BUCK3_SCG"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_OC, "BUCK3_OC"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_NEG_OC, "BUCK3_NEG_OC"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_UV, "BUCK3_UV"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_SCG, "BUCK1_SCG"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_OC, "BUCK1_OC"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_NEG_OC, "BUCK1_NEG_OC"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_UV, "BUCK1_UV"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_SCG, "BUCK2_SCG"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_OC, "BUCK2_OC"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_NEG_OC, "BUCK2_NEG_OC"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_UV, "BUCK2_UV"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_RV, "BUCK1_RV"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_RV, "BUCK2_RV"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_RV, "BUCK3_RV"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_RV, "LDO1_RV"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_RV, "LDO2_RV"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO3_RV, "LDO3_RV"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO4_RV, "LDO4_RV"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_RV_SD, "BUCK1_RV_SD"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_RV_SD, "BUCK2_RV_SD"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_RV_SD, "BUCK3_RV_SD"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_RV_SD, "LDO1_RV_SD"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_RV_SD, "LDO2_RV_SD"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO3_RV_SD, "LDO3_RV_SD"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO4_RV_SD, "LDO4_RV_SD"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_TIMEOUT, "TIMEOUT"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_3_WARM, "SENSOR_3_WARM"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_2_WARM, "SENSOR_2_WARM"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_1_WARM, "SENSOR_1_WARM"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_WARM, "SENSOR_0_WARM"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_3_HOT, "SENSOR_3_HOT"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_2_HOT, "SENSOR_2_HOT"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_1_HOT, "SENSOR_1_HOT"),
+	DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_HOT, "SENSOR_0_HOT"),
+};
+
+static const struct mfd_cell tps65219_cells[] = {
+	{
+		.name = "tps65219-regulator",
+		.resources = tps65219_regulator_resources,
+		.num_resources = ARRAY_SIZE(tps65219_regulator_resources),
+	},
+	{ .name = "tps65219-gpios", },
+};
+
+static const struct mfd_cell tps65219_pwrbutton_cell = {
+	.name = "tps65219-pwrbutton",
+	.resources = tps65219_pwrbutton_resources,
+	.num_resources = ARRAY_SIZE(tps65219_pwrbutton_resources),
+};
+
+static const struct regmap_config tps65219_regmap_config = {
+	.reg_bits = 8,
+	.val_bits = 8,
+	.max_register = TPS65219_REG_FACTORY_CONFIG_2,
+};
+
+/*
+ * Mapping of main IRQ register bits to sub-IRQ register offsets so that we can
+ * access corect sub-IRQ registers based on bits that are set in main IRQ
+ * register.
+ */
+/* Timeout Residual Voltage Shutdown */
+static unsigned int bit0_offsets[] = { TPS65219_REG_INT_TO_RV_POS };
+static unsigned int bit1_offsets[] = { TPS65219_REG_INT_RV_POS };	/* Residual Voltage */
+static unsigned int bit2_offsets[] = { TPS65219_REG_INT_SYS_POS };	/* System */
+static unsigned int bit3_offsets[] = { TPS65219_REG_INT_BUCK_1_2_POS };	/* Buck 1-2 */
+static unsigned int bit4_offsets[] = { TPS65219_REG_INT_BUCK_3_POS };	/* Buck 3 */
+static unsigned int bit5_offsets[] = { TPS65219_REG_INT_LDO_1_2_POS };	/* LDO 1-2 */
+static unsigned int bit6_offsets[] = { TPS65219_REG_INT_LDO_3_4_POS };	/* LDO 3-4 */
+static unsigned int bit7_offsets[] = { TPS65219_REG_INT_PB_POS };	/* Power Button */
+
+static struct regmap_irq_sub_irq_map tps65219_sub_irq_offsets[] = {
+	REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets),
+	REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets),
+	REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets),
+	REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets),
+	REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets),
+	REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets),
+	REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets),
+	REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets),
+};
+
+#define TPS65219_REGMAP_IRQ_REG(int_name, register_position) \
+	REGMAP_IRQ_REG(int_name, register_position, int_name##_MASK)
+
+static struct regmap_irq tps65219_irqs[] = {
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO3_SCG, TPS65219_REG_INT_LDO_3_4_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO3_OC, TPS65219_REG_INT_LDO_3_4_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO3_UV, TPS65219_REG_INT_LDO_3_4_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO4_SCG, TPS65219_REG_INT_LDO_3_4_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO4_OC, TPS65219_REG_INT_LDO_3_4_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO4_UV, TPS65219_REG_INT_LDO_3_4_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_SCG, TPS65219_REG_INT_LDO_1_2_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_OC, TPS65219_REG_INT_LDO_1_2_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_UV, TPS65219_REG_INT_LDO_1_2_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO2_SCG, TPS65219_REG_INT_LDO_1_2_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO2_OC, TPS65219_REG_INT_LDO_1_2_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO2_UV, TPS65219_REG_INT_LDO_1_2_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_SCG, TPS65219_REG_INT_BUCK_3_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_OC, TPS65219_REG_INT_BUCK_3_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_NEG_OC, TPS65219_REG_INT_BUCK_3_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_UV, TPS65219_REG_INT_BUCK_3_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_SCG, TPS65219_REG_INT_BUCK_1_2_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_OC, TPS65219_REG_INT_BUCK_1_2_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_NEG_OC, TPS65219_REG_INT_BUCK_1_2_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_UV, TPS65219_REG_INT_BUCK_1_2_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_SCG, TPS65219_REG_INT_BUCK_1_2_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_OC, TPS65219_REG_INT_BUCK_1_2_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_NEG_OC, TPS65219_REG_INT_BUCK_1_2_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_UV, TPS65219_REG_INT_BUCK_1_2_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_3_WARM, TPS65219_REG_INT_SYS_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_2_WARM, TPS65219_REG_INT_SYS_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_1_WARM, TPS65219_REG_INT_SYS_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_0_WARM, TPS65219_REG_INT_SYS_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_3_HOT, TPS65219_REG_INT_SYS_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_2_HOT, TPS65219_REG_INT_SYS_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_1_HOT, TPS65219_REG_INT_SYS_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_0_HOT, TPS65219_REG_INT_SYS_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_RV, TPS65219_REG_INT_RV_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_RV, TPS65219_REG_INT_RV_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_RV, TPS65219_REG_INT_RV_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_RV, TPS65219_REG_INT_RV_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO2_RV, TPS65219_REG_INT_RV_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO3_RV, TPS65219_REG_INT_RV_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO4_RV, TPS65219_REG_INT_RV_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_RV_SD, TPS65219_REG_INT_TO_RV_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_RV_SD, TPS65219_REG_INT_TO_RV_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_RV_SD, TPS65219_REG_INT_TO_RV_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_RV_SD, TPS65219_REG_INT_TO_RV_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO2_RV_SD, TPS65219_REG_INT_TO_RV_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO3_RV_SD, TPS65219_REG_INT_TO_RV_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO4_RV_SD, TPS65219_REG_INT_TO_RV_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_TIMEOUT, TPS65219_REG_INT_TO_RV_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_PB_FALLING_EDGE_DETECT, TPS65219_REG_INT_PB_POS),
+	TPS65219_REGMAP_IRQ_REG(TPS65219_INT_PB_RISING_EDGE_DETECT, TPS65219_REG_INT_PB_POS),
+};
+
+static struct regmap_irq_chip tps65219_irq_chip = {
+	.name = "tps65219_irq",
+	.main_status = TPS65219_REG_INT_SOURCE,
+	.num_main_regs = 1,
+	.num_main_status_bits = 8,
+	.irqs = tps65219_irqs,
+	.num_irqs = ARRAY_SIZE(tps65219_irqs),
+	.status_base = TPS65219_REG_INT_LDO_3_4,
+	.ack_base = TPS65219_REG_INT_LDO_3_4,
+	.clear_ack = 1,
+	.num_regs = 8,
+	.sub_reg_offsets = tps65219_sub_irq_offsets,
+};
+
+static int tps65219_probe(struct i2c_client *client)
+{
+	struct tps65219 *tps;
+	unsigned int chipid;
+	bool pwr_button;
+	int ret;
+
+	tps = devm_kzalloc(&client->dev, sizeof(*tps), GFP_KERNEL);
+	if (!tps)
+		return -ENOMEM;
+
+	i2c_set_clientdata(client, tps);
+
+	tps->dev = &client->dev;
+
+	tps->regmap = devm_regmap_init_i2c(client, &tps65219_regmap_config);
+	if (IS_ERR(tps->regmap)) {
+		ret = PTR_ERR(tps->regmap);
+		dev_err(tps->dev, "Failed to allocate register map: %d\n", ret);
+		return ret;
+	}
+
+	ret = devm_regmap_add_irq_chip(&client->dev, tps->regmap, client->irq,
+				       IRQF_ONESHOT, 0, &tps65219_irq_chip,
+				       &tps->irq_data);
+	if (ret)
+		return ret;
+
+	ret = regmap_read(tps->regmap, TPS65219_REG_TI_DEV_ID, &chipid);
+	if (ret) {
+		dev_err(tps->dev, "Failed to read device ID: %d\n", ret);
+		return ret;
+	}
+
+	ret = devm_mfd_add_devices(tps->dev, PLATFORM_DEVID_AUTO,
+				   tps65219_cells, ARRAY_SIZE(tps65219_cells),
+				   NULL, 0, regmap_irq_get_domain(tps->irq_data));
+	if (ret) {
+		dev_err(tps->dev, "Failed to add child devices: %d\n", ret);
+		return ret;
+	}
+
+	pwr_button = of_property_read_bool(tps->dev->of_node, "ti,power-button");
+	if (pwr_button) {
+		ret = devm_mfd_add_devices(tps->dev, PLATFORM_DEVID_AUTO,
+					   &tps65219_pwrbutton_cell, 1, NULL, 0,
+					   regmap_irq_get_domain(tps->irq_data));
+		if (ret) {
+			dev_err(tps->dev, "Failed to add power-button: %d\n", ret);
+			return ret;
+		}
+	}
+
+	tps->nb = pmic_rst_restart_nb;
+	ret = register_restart_handler(&tps->nb);
+	if (ret) {
+		dev_err(tps->dev, "cannot register restart handler, %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct of_device_id of_tps65219_match_table[] = {
+	{ .compatible = "ti,tps65219", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, of_tps65219_match_table);
+
+static struct i2c_driver tps65219_driver = {
+	.driver		= {
+		.name	= "tps65219",
+		.of_match_table = of_tps65219_match_table,
+	},
+	.probe_new	= tps65219_probe,
+};
+module_i2c_driver(tps65219_driver);
+
+MODULE_AUTHOR("Jerome Neanne <jneanne@baylibre.com>");
+MODULE_DESCRIPTION("TPS65219 power management IC driver");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/mfd/tps65219.h b/include/linux/mfd/tps65219.h
new file mode 100644
index 0000000000000..e6826e34e2a64
--- /dev/null
+++ b/include/linux/mfd/tps65219.h
@@ -0,0 +1,345 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Functions to access TPS65219 Power Management IC.
+ *
+ * Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/
+ */
+
+#ifndef MFD_TPS65219_H
+#define MFD_TPS65219_H
+
+#include <linux/bitops.h>
+#include <linux/notifier.h>
+#include <linux/regulator/driver.h>
+
+struct regmap;
+struct regmap_irq_chip_data;
+
+#define TPS65219_1V35					1350000
+#define TPS65219_1V8					1800000
+
+/* TPS chip id list */
+#define TPS65219					0xF0
+
+/* I2C ID for TPS65219 part */
+#define TPS65219_I2C_ID					0x24
+
+/* All register addresses */
+#define TPS65219_REG_TI_DEV_ID				0x00
+#define TPS65219_REG_NVM_ID				0x01
+#define TPS65219_REG_ENABLE_CTRL			0x02
+#define TPS65219_REG_BUCKS_CONFIG			0x03
+#define TPS65219_REG_LDO4_VOUT				0x04
+#define TPS65219_REG_LDO3_VOUT				0x05
+#define TPS65219_REG_LDO2_VOUT				0x06
+#define TPS65219_REG_LDO1_VOUT				0x07
+#define TPS65219_REG_BUCK3_VOUT				0x8
+#define TPS65219_REG_BUCK2_VOUT				0x9
+#define TPS65219_REG_BUCK1_VOUT				0xA
+#define TPS65219_REG_LDO4_SEQUENCE_SLOT			0xB
+#define TPS65219_REG_LDO3_SEQUENCE_SLOT			0xC
+#define TPS65219_REG_LDO2_SEQUENCE_SLOT			0xD
+#define TPS65219_REG_LDO1_SEQUENCE_SLOT			0xE
+#define TPS65219_REG_BUCK3_SEQUENCE_SLOT		0xF
+#define TPS65219_REG_BUCK2_SEQUENCE_SLOT		0x10
+#define TPS65219_REG_BUCK1_SEQUENCE_SLOT		0x11
+#define TPS65219_REG_nRST_SEQUENCE_SLOT			0x12
+#define TPS65219_REG_GPIO_SEQUENCE_SLOT			0x13
+#define TPS65219_REG_GPO2_SEQUENCE_SLOT			0x14
+#define TPS65219_REG_GPO1_SEQUENCE_SLOT			0x15
+#define TPS65219_REG_POWER_UP_SLOT_DURATION_1		0x16
+#define TPS65219_REG_POWER_UP_SLOT_DURATION_2		0x17
+#define TPS65219_REG_POWER_UP_SLOT_DURATION_3		0x18
+#define TPS65219_REG_POWER_UP_SLOT_DURATION_4		0x19
+#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_1		0x1A
+#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_2		0x1B
+#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_3		0x1C
+#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_4		0x1D
+#define TPS65219_REG_GENERAL_CONFIG			0x1E
+#define TPS65219_REG_MFP_1_CONFIG			0x1F
+#define TPS65219_REG_MFP_2_CONFIG			0x20
+#define TPS65219_REG_STBY_1_CONFIG			0x21
+#define TPS65219_REG_STBY_2_CONFIG			0x22
+#define TPS65219_REG_OC_DEGL_CONFIG			0x23
+/* 'sub irq' MASK registers */
+#define TPS65219_REG_INT_MASK_UV			0x24
+#define TPS65219_REG_MASK_CONFIG			0x25
+
+#define TPS65219_REG_I2C_ADDRESS_REG			0x26
+#define TPS65219_REG_USER_GENERAL_NVM_STORAGE		0x27
+#define TPS65219_REG_MANUFACTURING_VER			0x28
+#define TPS65219_REG_MFP_CTRL				0x29
+#define TPS65219_REG_DISCHARGE_CONFIG			0x2A
+/* main irq registers */
+#define TPS65219_REG_INT_SOURCE				0x2B
+/* 'sub irq' registers */
+#define TPS65219_REG_INT_LDO_3_4			0x2C
+#define TPS65219_REG_INT_LDO_1_2			0x2D
+#define TPS65219_REG_INT_BUCK_3				0x2E
+#define TPS65219_REG_INT_BUCK_1_2			0x2F
+#define TPS65219_REG_INT_SYSTEM				0x30
+#define TPS65219_REG_INT_RV				0x31
+#define TPS65219_REG_INT_TIMEOUT_RV_SD			0x32
+#define TPS65219_REG_INT_PB				0x33
+
+#define TPS65219_REG_INT_LDO_3_4_POS			0
+#define TPS65219_REG_INT_LDO_1_2_POS			1
+#define TPS65219_REG_INT_BUCK_3_POS			2
+#define TPS65219_REG_INT_BUCK_1_2_POS			3
+#define TPS65219_REG_INT_SYS_POS			4
+#define TPS65219_REG_INT_RV_POS				5
+#define TPS65219_REG_INT_TO_RV_POS			6
+#define TPS65219_REG_INT_PB_POS				7
+
+#define TPS65219_REG_USER_NVM_CMD			0x34
+#define TPS65219_REG_POWER_UP_STATUS			0x35
+#define TPS65219_REG_SPARE_2				0x36
+#define TPS65219_REG_SPARE_3				0x37
+#define TPS65219_REG_FACTORY_CONFIG_2			0x41
+
+/* Register field definitions */
+#define TPS65219_DEVID_REV_MASK				GENMASK(7, 0)
+#define TPS65219_BUCKS_LDOS_VOUT_VSET_MASK		GENMASK(5, 0)
+#define TPS65219_BUCKS_UV_THR_SEL_MASK			BIT(6)
+#define TPS65219_BUCKS_BW_SEL_MASK			BIT(7)
+#define LDO_BYP_SHIFT					6
+#define TPS65219_LDOS_BYP_CONFIG_MASK			BIT(LDO_BYP_SHIFT)
+#define TPS65219_LDOS_LSW_CONFIG_MASK			BIT(7)
+/* Regulators enable control */
+#define TPS65219_ENABLE_BUCK1_EN_MASK			BIT(0)
+#define TPS65219_ENABLE_BUCK2_EN_MASK			BIT(1)
+#define TPS65219_ENABLE_BUCK3_EN_MASK			BIT(2)
+#define TPS65219_ENABLE_LDO1_EN_MASK			BIT(3)
+#define TPS65219_ENABLE_LDO2_EN_MASK			BIT(4)
+#define TPS65219_ENABLE_LDO3_EN_MASK			BIT(5)
+#define TPS65219_ENABLE_LDO4_EN_MASK			BIT(6)
+/* power ON-OFF sequence slot */
+#define TPS65219_BUCKS_LDOS_SEQUENCE_OFF_SLOT_MASK	GENMASK(3, 0)
+#define TPS65219_BUCKS_LDOS_SEQUENCE_ON_SLOT_MASK	GENMASK(7, 4)
+/* TODO: Not needed, same mapping as TPS65219_ENABLE_REGNAME_EN, factorize */
+#define TPS65219_STBY1_BUCK1_STBY_EN_MASK		BIT(0)
+#define TPS65219_STBY1_BUCK2_STBY_EN_MASK		BIT(1)
+#define TPS65219_STBY1_BUCK3_STBY_EN_MASK		BIT(2)
+#define TPS65219_STBY1_LDO1_STBY_EN_MASK		BIT(3)
+#define TPS65219_STBY1_LDO2_STBY_EN_MASK		BIT(4)
+#define TPS65219_STBY1_LDO3_STBY_EN_MASK		BIT(5)
+#define TPS65219_STBY1_LDO4_STBY_EN_MASK		BIT(6)
+/* STBY_2 config */
+#define TPS65219_STBY2_GPO1_STBY_EN_MASK		BIT(0)
+#define TPS65219_STBY2_GPO2_STBY_EN_MASK		BIT(1)
+#define TPS65219_STBY2_GPIO_STBY_EN_MASK		BIT(2)
+/* MFP Control */
+#define TPS65219_MFP_I2C_OFF_REQ_MASK			BIT(0)
+#define TPS65219_MFP_STBY_I2C_CTRL_MASK			BIT(1)
+#define TPS65219_MFP_COLD_RESET_I2C_CTRL_MASK		BIT(2)
+#define TPS65219_MFP_WARM_RESET_I2C_CTRL_MASK		BIT(3)
+#define TPS65219_MFP_GPIO_STATUS_MASK			BIT(4)
+/* MFP_1 Config */
+#define TPS65219_MFP_1_VSEL_DDR_SEL_MASK		BIT(0)
+#define TPS65219_MFP_1_VSEL_SD_POL_MASK			BIT(1)
+#define TPS65219_MFP_1_VSEL_RAIL_MASK			BIT(2)
+/* MFP_2 Config */
+#define TPS65219_MFP_2_MODE_STBY_MASK			GENMASK(1, 0)
+#define TPS65219_MFP_2_MODE_RESET_MASK			BIT(2)
+#define TPS65219_MFP_2_EN_PB_VSENSE_DEGL_MASK		BIT(3)
+#define TPS65219_MFP_2_EN_PB_VSENSE_MASK		GENMASK(5, 4)
+#define TPS65219_MFP_2_WARM_COLD_RESET_MASK		BIT(6)
+#define TPS65219_MFP_2_PU_ON_FSD_MASK			BIT(7)
+#define TPS65219_MFP_2_EN				0
+#define TPS65219_MFP_2_PB				BIT(4)
+#define TPS65219_MFP_2_VSENSE				BIT(5)
+/* MASK_UV Config */
+#define TPS65219_REG_MASK_UV_LDO1_UV_MASK		BIT(0)
+#define TPS65219_REG_MASK_UV_LDO2_UV_MASK		BIT(1)
+#define TPS65219_REG_MASK_UV_LDO3_UV_MASK		BIT(2)
+#define TPS65219_REG_MASK_UV_LDO4_UV_MASK		BIT(3)
+#define TPS65219_REG_MASK_UV_BUCK1_UV_MASK		BIT(4)
+#define TPS65219_REG_MASK_UV_BUCK2_UV_MASK		BIT(5)
+#define TPS65219_REG_MASK_UV_BUCK3_UV_MASK		BIT(6)
+#define TPS65219_REG_MASK_UV_RETRY_MASK			BIT(7)
+/* MASK Config */
+// SENSOR_N_WARM_MASK already defined in Thermal
+#define TPS65219_REG_MASK_INT_FOR_RV_MASK		BIT(4)
+#define TPS65219_REG_MASK_EFFECT_MASK			GENMASK(2, 1)
+#define TPS65219_REG_MASK_INT_FOR_PB_MASK		BIT(7)
+/* UnderVoltage - Short to GND - OverCurrent*/
+/* LDO3-4 */
+#define TPS65219_INT_LDO3_SCG_MASK			BIT(0)
+#define TPS65219_INT_LDO3_OC_MASK			BIT(1)
+#define TPS65219_INT_LDO3_UV_MASK			BIT(2)
+#define TPS65219_INT_LDO4_SCG_MASK			BIT(3)
+#define TPS65219_INT_LDO4_OC_MASK			BIT(4)
+#define TPS65219_INT_LDO4_UV_MASK			BIT(5)
+/* LDO1-2 */
+#define TPS65219_INT_LDO1_SCG_MASK			BIT(0)
+#define TPS65219_INT_LDO1_OC_MASK			BIT(1)
+#define TPS65219_INT_LDO1_UV_MASK			BIT(2)
+#define TPS65219_INT_LDO2_SCG_MASK			BIT(3)
+#define TPS65219_INT_LDO2_OC_MASK			BIT(4)
+#define TPS65219_INT_LDO2_UV_MASK			BIT(5)
+/* BUCK3 */
+#define TPS65219_INT_BUCK3_SCG_MASK			BIT(0)
+#define TPS65219_INT_BUCK3_OC_MASK			BIT(1)
+#define TPS65219_INT_BUCK3_NEG_OC_MASK			BIT(2)
+#define TPS65219_INT_BUCK3_UV_MASK			BIT(3)
+/* BUCK1-2 */
+#define TPS65219_INT_BUCK1_SCG_MASK			BIT(0)
+#define TPS65219_INT_BUCK1_OC_MASK			BIT(1)
+#define TPS65219_INT_BUCK1_NEG_OC_MASK			BIT(2)
+#define TPS65219_INT_BUCK1_UV_MASK			BIT(3)
+#define TPS65219_INT_BUCK2_SCG_MASK			BIT(4)
+#define TPS65219_INT_BUCK2_OC_MASK			BIT(5)
+#define TPS65219_INT_BUCK2_NEG_OC_MASK			BIT(6)
+#define TPS65219_INT_BUCK2_UV_MASK			BIT(7)
+/* Thermal Sensor  */
+#define TPS65219_INT_SENSOR_3_WARM_MASK			BIT(0)
+#define TPS65219_INT_SENSOR_2_WARM_MASK			BIT(1)
+#define TPS65219_INT_SENSOR_1_WARM_MASK			BIT(2)
+#define TPS65219_INT_SENSOR_0_WARM_MASK			BIT(3)
+#define TPS65219_INT_SENSOR_3_HOT_MASK			BIT(4)
+#define TPS65219_INT_SENSOR_2_HOT_MASK			BIT(5)
+#define TPS65219_INT_SENSOR_1_HOT_MASK			BIT(6)
+#define TPS65219_INT_SENSOR_0_HOT_MASK			BIT(7)
+/* Residual Voltage */
+#define TPS65219_INT_BUCK1_RV_MASK			BIT(0)
+#define TPS65219_INT_BUCK2_RV_MASK			BIT(1)
+#define TPS65219_INT_BUCK3_RV_MASK			BIT(2)
+#define TPS65219_INT_LDO1_RV_MASK			BIT(3)
+#define TPS65219_INT_LDO2_RV_MASK			BIT(4)
+#define TPS65219_INT_LDO3_RV_MASK			BIT(5)
+#define TPS65219_INT_LDO4_RV_MASK			BIT(6)
+/* Residual Voltage ShutDown */
+#define TPS65219_INT_BUCK1_RV_SD_MASK			BIT(0)
+#define TPS65219_INT_BUCK2_RV_SD_MASK			BIT(1)
+#define TPS65219_INT_BUCK3_RV_SD_MASK			BIT(2)
+#define TPS65219_INT_LDO1_RV_SD_MASK			BIT(3)
+#define TPS65219_INT_LDO2_RV_SD_MASK			BIT(4)
+#define TPS65219_INT_LDO3_RV_SD_MASK			BIT(5)
+#define TPS65219_INT_LDO4_RV_SD_MASK			BIT(6)
+#define TPS65219_INT_TIMEOUT_MASK			BIT(7)
+/* Power Button */
+#define TPS65219_INT_PB_FALLING_EDGE_DETECT_MASK	BIT(0)
+#define TPS65219_INT_PB_RISING_EDGE_DETECT_MASK		BIT(1)
+#define TPS65219_INT_PB_REAL_TIME_STATUS_MASK		BIT(2)
+
+#define TPS65219_PB_POS					7
+#define TPS65219_TO_RV_POS				6
+#define TPS65219_RV_POS					5
+#define TPS65219_SYS_POS				4
+#define TPS65219_BUCK_1_2_POS				3
+#define TPS65219_BUCK_3_POS				2
+#define TPS65219_LDO_1_2_POS				1
+#define TPS65219_LDO_3_4_POS				0
+
+/* IRQs */
+enum {
+	/* LDO3-4 register IRQs */
+	TPS65219_INT_LDO3_SCG,
+	TPS65219_INT_LDO3_OC,
+	TPS65219_INT_LDO3_UV,
+	TPS65219_INT_LDO4_SCG,
+	TPS65219_INT_LDO4_OC,
+	TPS65219_INT_LDO4_UV,
+	/* LDO1-2 */
+	TPS65219_INT_LDO1_SCG,
+	TPS65219_INT_LDO1_OC,
+	TPS65219_INT_LDO1_UV,
+	TPS65219_INT_LDO2_SCG,
+	TPS65219_INT_LDO2_OC,
+	TPS65219_INT_LDO2_UV,
+	/* BUCK3 */
+	TPS65219_INT_BUCK3_SCG,
+	TPS65219_INT_BUCK3_OC,
+	TPS65219_INT_BUCK3_NEG_OC,
+	TPS65219_INT_BUCK3_UV,
+	/* BUCK1-2 */
+	TPS65219_INT_BUCK1_SCG,
+	TPS65219_INT_BUCK1_OC,
+	TPS65219_INT_BUCK1_NEG_OC,
+	TPS65219_INT_BUCK1_UV,
+	TPS65219_INT_BUCK2_SCG,
+	TPS65219_INT_BUCK2_OC,
+	TPS65219_INT_BUCK2_NEG_OC,
+	TPS65219_INT_BUCK2_UV,
+	/* Thermal Sensor  */
+	TPS65219_INT_SENSOR_3_WARM,
+	TPS65219_INT_SENSOR_2_WARM,
+	TPS65219_INT_SENSOR_1_WARM,
+	TPS65219_INT_SENSOR_0_WARM,
+	TPS65219_INT_SENSOR_3_HOT,
+	TPS65219_INT_SENSOR_2_HOT,
+	TPS65219_INT_SENSOR_1_HOT,
+	TPS65219_INT_SENSOR_0_HOT,
+	/* Residual Voltage */
+	TPS65219_INT_BUCK1_RV,
+	TPS65219_INT_BUCK2_RV,
+	TPS65219_INT_BUCK3_RV,
+	TPS65219_INT_LDO1_RV,
+	TPS65219_INT_LDO2_RV,
+	TPS65219_INT_LDO3_RV,
+	TPS65219_INT_LDO4_RV,
+	/* Residual Voltage ShutDown */
+	TPS65219_INT_BUCK1_RV_SD,
+	TPS65219_INT_BUCK2_RV_SD,
+	TPS65219_INT_BUCK3_RV_SD,
+	TPS65219_INT_LDO1_RV_SD,
+	TPS65219_INT_LDO2_RV_SD,
+	TPS65219_INT_LDO3_RV_SD,
+	TPS65219_INT_LDO4_RV_SD,
+	TPS65219_INT_TIMEOUT,
+	/* Power Button */
+	TPS65219_INT_PB_FALLING_EDGE_DETECT,
+	TPS65219_INT_PB_RISING_EDGE_DETECT,
+};
+
+enum tps65219_regulator_id {
+	/* DCDC's */
+	TPS65219_BUCK_1,
+	TPS65219_BUCK_2,
+	TPS65219_BUCK_3,
+	/* LDOs */
+	TPS65219_LDO_1,
+	TPS65219_LDO_2,
+	TPS65219_LDO_3,
+	TPS65219_LDO_4,
+};
+
+/* Number of step-down converters available */
+#define TPS65219_NUM_DCDC		3
+/* Number of LDO voltage regulators available */
+#define TPS65219_NUM_LDO		4
+/* Number of total regulators available */
+#define TPS65219_NUM_REGULATOR		(TPS65219_NUM_DCDC + TPS65219_NUM_LDO)
+
+/* Define the TPS65219 IRQ numbers */
+enum tps65219_irqs {
+	/* INT source registers */
+	TPS65219_TO_RV_SD_SET_IRQ,
+	TPS65219_RV_SET_IRQ,
+	TPS65219_SYS_SET_IRQ,
+	TPS65219_BUCK_1_2_SET_IRQ,
+	TPS65219_BUCK_3_SET_IRQ,
+	TPS65219_LDO_1_2_SET_IRQ,
+	TPS65219_LDO_3_4_SET_IRQ,
+	TPS65219_PB_SET_IRQ,
+};
+
+/**
+ * struct tps65219 - tps65219 sub-driver chip access routines
+ *
+ * Device data may be used to access the TPS65219 chip
+ *
+ * @dev: MFD device
+ * @regmap: Regmap for accessing the device registers
+ * @irq_data: Regmap irq data used for the irq chip
+ * @nb: notifier block for the restart handler
+ */
+struct tps65219 {
+	struct device *dev;
+	struct regmap *regmap;
+
+	struct regmap_irq_chip_data *irq_data;
+	struct notifier_block nb;
+};
+
+#endif /* MFD_TPS65219_H */
-- 
GitLab


From c8cf6e2328ce42ba016f6c321ba663d07e6f70ff Mon Sep 17 00:00:00 2001
From: Markus Schneider-Pargmann <msp@baylibre.com>
Date: Fri, 4 Nov 2022 16:23:10 +0100
Subject: [PATCH 324/875] Input: Add tps65219 interrupt driven powerbutton

TPS65219 has different interrupts compared to other TPS6521* chips.
TPS65219 defines two interrupts for the powerbutton one for push and one
for release.

This driver is very simple in that it maps the push interrupt to a key
input and the release interrupt to a key release.

Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Signed-off-by: Jerome Neanne <jneanne@baylibre.com>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221104152311.1098603-6-jneanne@baylibre.com
---
 drivers/input/misc/Kconfig              |  10 ++
 drivers/input/misc/Makefile             |   1 +
 drivers/input/misc/tps65219-pwrbutton.c | 148 ++++++++++++++++++++++++
 3 files changed, 159 insertions(+)
 create mode 100644 drivers/input/misc/tps65219-pwrbutton.c

diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index 540633b164d44..006335142491a 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -468,6 +468,16 @@ config INPUT_TPS65218_PWRBUTTON
 	  To compile this driver as a module, choose M here. The module will
 	  be called tps65218-pwrbutton.
 
+config INPUT_TPS65219_PWRBUTTON
+	tristate "TPS65219 Power button driver"
+	depends on MFD_TPS65219
+	help
+	  Say Y here if you want to enable power button reporting for
+	  TPS65219 Power Management IC devices.
+
+	  To compile this driver as a module, choose M here. The module will
+	  be called tps65219-pwrbutton.
+
 config INPUT_AXP20X_PEK
 	tristate "X-Powers AXP20X power button driver"
 	depends on MFD_AXP20X
diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
index 156f9c21f53b7..61949263300d5 100644
--- a/drivers/input/misc/Makefile
+++ b/drivers/input/misc/Makefile
@@ -79,6 +79,7 @@ obj-$(CONFIG_INPUT_SOC_BUTTON_ARRAY)	+= soc_button_array.o
 obj-$(CONFIG_INPUT_SPARCSPKR)		+= sparcspkr.o
 obj-$(CONFIG_INPUT_STPMIC1_ONKEY)  	+= stpmic1_onkey.o
 obj-$(CONFIG_INPUT_TPS65218_PWRBUTTON)	+= tps65218-pwrbutton.o
+obj-$(CONFIG_INPUT_TPS65219_PWRBUTTON)	+= tps65219-pwrbutton.o
 obj-$(CONFIG_INPUT_TWL4030_PWRBUTTON)	+= twl4030-pwrbutton.o
 obj-$(CONFIG_INPUT_TWL4030_VIBRA)	+= twl4030-vibra.o
 obj-$(CONFIG_INPUT_TWL6040_VIBRA)	+= twl6040-vibra.o
diff --git a/drivers/input/misc/tps65219-pwrbutton.c b/drivers/input/misc/tps65219-pwrbutton.c
new file mode 100644
index 0000000000000..245134bdb59e6
--- /dev/null
+++ b/drivers/input/misc/tps65219-pwrbutton.c
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Driver for TPS65219 Push Button
+//
+// Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/
+
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/mfd/tps65219.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+struct tps65219_pwrbutton {
+	struct device *dev;
+	struct input_dev *idev;
+	char phys[32];
+};
+
+static irqreturn_t tps65219_pb_push_irq(int irq, void *_pwr)
+{
+	struct tps65219_pwrbutton *pwr = _pwr;
+
+	input_report_key(pwr->idev, KEY_POWER, 1);
+	pm_wakeup_event(pwr->dev, 0);
+	input_sync(pwr->idev);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t tps65219_pb_release_irq(int irq, void *_pwr)
+{
+	struct tps65219_pwrbutton *pwr = _pwr;
+
+	input_report_key(pwr->idev, KEY_POWER, 0);
+	input_sync(pwr->idev);
+
+	return IRQ_HANDLED;
+}
+
+static int tps65219_pb_probe(struct platform_device *pdev)
+{
+	struct tps65219 *tps = dev_get_drvdata(pdev->dev.parent);
+	struct device *dev = &pdev->dev;
+	struct tps65219_pwrbutton *pwr;
+	struct input_dev *idev;
+	int error;
+	int push_irq;
+	int release_irq;
+
+	pwr = devm_kzalloc(dev, sizeof(*pwr), GFP_KERNEL);
+	if (!pwr)
+		return -ENOMEM;
+
+	idev = devm_input_allocate_device(dev);
+	if (!idev)
+		return -ENOMEM;
+
+	idev->name = pdev->name;
+	snprintf(pwr->phys, sizeof(pwr->phys), "%s/input0",
+		 pdev->name);
+	idev->phys = pwr->phys;
+	idev->id.bustype = BUS_I2C;
+
+	input_set_capability(idev, EV_KEY, KEY_POWER);
+
+	pwr->dev = dev;
+	pwr->idev = idev;
+	device_init_wakeup(dev, true);
+
+	push_irq = platform_get_irq(pdev, 0);
+	if (push_irq < 0)
+		return -EINVAL;
+
+	release_irq = platform_get_irq(pdev, 1);
+	if (release_irq < 0)
+		return -EINVAL;
+
+	error = devm_request_threaded_irq(dev, push_irq, NULL,
+					  tps65219_pb_push_irq,
+					  IRQF_ONESHOT,
+					  dev->init_name, pwr);
+	if (error) {
+		dev_err(dev, "failed to request push IRQ #%d: %d\n", push_irq,
+			error);
+		return error;
+	}
+
+	error = devm_request_threaded_irq(dev, release_irq, NULL,
+					  tps65219_pb_release_irq,
+					  IRQF_ONESHOT,
+					  dev->init_name, pwr);
+	if (error) {
+		dev_err(dev, "failed to request release IRQ #%d: %d\n",
+			release_irq, error);
+		return error;
+	}
+
+	error = input_register_device(idev);
+	if (error) {
+		dev_err(dev, "Can't register power button: %d\n", error);
+		return error;
+	}
+
+	/* Enable interrupts for the pushbutton */
+	regmap_clear_bits(tps->regmap, TPS65219_REG_MASK_CONFIG,
+			  TPS65219_REG_MASK_INT_FOR_PB_MASK);
+
+	/* Set PB/EN/VSENSE pin to be a pushbutton */
+	regmap_update_bits(tps->regmap, TPS65219_REG_MFP_2_CONFIG,
+			   TPS65219_MFP_2_EN_PB_VSENSE_MASK, TPS65219_MFP_2_PB);
+
+	return 0;
+}
+
+static int tps65219_pb_remove(struct platform_device *pdev)
+{
+	struct tps65219 *tps = dev_get_drvdata(pdev->dev.parent);
+
+	/* Disable interrupt for the pushbutton */
+	return regmap_update_bits(tps->regmap, TPS65219_REG_MASK_CONFIG,
+				  TPS65219_REG_MASK_INT_FOR_PB_MASK,
+				  TPS65219_REG_MASK_INT_FOR_PB_MASK);
+}
+
+static const struct platform_device_id tps65219_pwrbtn_id_table[] = {
+	{ "tps65219-pwrbutton", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(platform, tps65219_pwrbtn_id_table);
+
+static struct platform_driver tps65219_pb_driver = {
+	.probe = tps65219_pb_probe,
+	.remove = tps65219_pb_remove,
+	.driver = {
+		.name = "tps65219_pwrbutton",
+	},
+	.id_table = tps65219_pwrbtn_id_table,
+};
+module_platform_driver(tps65219_pb_driver);
+
+MODULE_DESCRIPTION("TPS65219 Power Button");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Markus Schneider-Pargmann <msp@baylibre.com");
-- 
GitLab


From d0871b5a22b46fc81887e35e4559710cd53fcfae Mon Sep 17 00:00:00 2001
From: ye xingchen <ye.xingchen@zte.com.cn>
Date: Thu, 17 Nov 2022 19:52:24 +0800
Subject: [PATCH 325/875] mfd: palmas: Use device_get_match_data() to simplify
 the code

Directly get the match data with device_get_match_data().

Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/202211171952240424511@zte.com.cn
---
 drivers/mfd/palmas.c | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/drivers/mfd/palmas.c b/drivers/mfd/palmas.c
index d26d82c85ba8e..b8383c6cba3ff 100644
--- a/drivers/mfd/palmas.c
+++ b/drivers/mfd/palmas.c
@@ -511,7 +511,6 @@ static int palmas_i2c_probe(struct i2c_client *i2c)
 	int ret = 0, i;
 	unsigned int reg, addr;
 	int slave;
-	const struct of_device_id *match;
 
 	pdata = dev_get_platdata(&i2c->dev);
 
@@ -535,12 +534,7 @@ static int palmas_i2c_probe(struct i2c_client *i2c)
 	palmas->dev = &i2c->dev;
 	palmas->irq = i2c->irq;
 
-	match = of_match_device(of_palmas_match_tbl, &i2c->dev);
-
-	if (!match)
-		return -ENODATA;
-
-	driver_data = (struct palmas_driver_data *)match->data;
+	driver_data = (struct palmas_driver_data *) device_get_match_data(&i2c->dev);
 	palmas->features = *driver_data->features;
 
 	for (i = 0; i < PALMAS_NUM_CLIENTS; i++) {
-- 
GitLab


From 1ca8a011ddca3e44340d9db611b019054dfc37d6 Mon Sep 17 00:00:00 2001
From: Matti Vaittinen <mazziesaccount@gmail.com>
Date: Thu, 1 Dec 2022 08:57:52 +0200
Subject: [PATCH 326/875] dt-bindings: Fix maintainer email for a few ROHM ICs

The email backend used by ROHM keeps labeling patches as spam. This can
result to missing the patches.

Switch my mail address from a company mail to a personal one.

Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/7986d30480df6179a3989fba4cd13817738635c5.1669877740.git.mazziesaccount@gmail.com
---
 Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml   | 2 +-
 Documentation/devicetree/bindings/mfd/rohm,bd71815-pmic.yaml    | 2 +-
 Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml    | 2 +-
 Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.yaml    | 2 +-
 Documentation/devicetree/bindings/mfd/rohm,bd71847-pmic.yaml    | 2 +-
 Documentation/devicetree/bindings/mfd/rohm,bd9576-pmic.yaml     | 2 +-
 .../devicetree/bindings/power/supply/rohm,bd99954.yaml          | 2 +-
 .../devicetree/bindings/regulator/rohm,bd71815-regulator.yaml   | 2 +-
 .../devicetree/bindings/regulator/rohm,bd71828-regulator.yaml   | 2 +-
 .../devicetree/bindings/regulator/rohm,bd71837-regulator.yaml   | 2 +-
 .../devicetree/bindings/regulator/rohm,bd71847-regulator.yaml   | 2 +-
 .../devicetree/bindings/regulator/rohm,bd9576-regulator.yaml    | 2 +-
 12 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml b/Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml
index 86a37c92b8348..d48c404c848ea 100644
--- a/Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml
+++ b/Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: ROHM BD71828 Power Management Integrated Circuit LED driver
 
 maintainers:
-  - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
+  - Matti Vaittinen <mazziesaccount@gmail.com>
 
 description: |
   This module is part of the ROHM BD71828 MFD device. For more details
diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd71815-pmic.yaml b/Documentation/devicetree/bindings/mfd/rohm,bd71815-pmic.yaml
index fbface720678c..7cda8adc178e1 100644
--- a/Documentation/devicetree/bindings/mfd/rohm,bd71815-pmic.yaml
+++ b/Documentation/devicetree/bindings/mfd/rohm,bd71815-pmic.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: ROHM BD71815 Power Management Integrated Circuit bindings
 
 maintainers:
-  - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
+  - Matti Vaittinen <mazziesaccount@gmail.com>
 
 description: |
   BD71815AGW is a single-chip power management ICs for battery-powered
diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml b/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml
index 8380166d176cd..c13730aa34d94 100644
--- a/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml
+++ b/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: ROHM BD71828 Power Management Integrated Circuit bindings
 
 maintainers:
-  - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
+  - Matti Vaittinen <mazziesaccount@gmail.com>
 
 description: |
   BD71828GW is a single-chip power management IC for battery-powered portable
diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.yaml b/Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.yaml
index 3bfdd33702ad1..3ab8dcf0e8f1c 100644
--- a/Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.yaml
+++ b/Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: ROHM BD71837 Power Management Integrated Circuit bindings
 
 maintainers:
-  - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
+  - Matti Vaittinen <mazziesaccount@gmail.com>
 
 description: |
   BD71837MWV is programmable Power Management ICs for powering single-core,
diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd71847-pmic.yaml b/Documentation/devicetree/bindings/mfd/rohm,bd71847-pmic.yaml
index 5d531051a1537..8ed4390bb43fc 100644
--- a/Documentation/devicetree/bindings/mfd/rohm,bd71847-pmic.yaml
+++ b/Documentation/devicetree/bindings/mfd/rohm,bd71847-pmic.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: ROHM BD71847 and BD71850 Power Management Integrated Circuit bindings
 
 maintainers:
-  - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
+  - Matti Vaittinen <mazziesaccount@gmail.com>
 
 description: |
   BD71847AMWV and BD71850MWV are programmable Power Management ICs for powering
diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd9576-pmic.yaml b/Documentation/devicetree/bindings/mfd/rohm,bd9576-pmic.yaml
index 6483860da9554..e1ebea9ad5da2 100644
--- a/Documentation/devicetree/bindings/mfd/rohm,bd9576-pmic.yaml
+++ b/Documentation/devicetree/bindings/mfd/rohm,bd9576-pmic.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: ROHM BD9576MUF and BD9573MUF Power Management Integrated Circuit bindings
 
 maintainers:
-  - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
+  - Matti Vaittinen <mazziesaccount@gmail.com>
 
 description: |
   BD9576MUF and BD9573MUF are power management ICs primarily intended for
diff --git a/Documentation/devicetree/bindings/power/supply/rohm,bd99954.yaml b/Documentation/devicetree/bindings/power/supply/rohm,bd99954.yaml
index 24b06957b4ca5..6a0756e33eb8d 100644
--- a/Documentation/devicetree/bindings/power/supply/rohm,bd99954.yaml
+++ b/Documentation/devicetree/bindings/power/supply/rohm,bd99954.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: ROHM BD99954 Battery charger
 
 maintainers:
-  - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
+  - Matti Vaittinen <mazziesaccount@gmail.com>
   - Markus Laine <markus.laine@fi.rohmeurope.com>
   - Mikko Mutanen <mikko.mutanen@fi.rohmeurope.com>
 
diff --git a/Documentation/devicetree/bindings/regulator/rohm,bd71815-regulator.yaml b/Documentation/devicetree/bindings/regulator/rohm,bd71815-regulator.yaml
index d61e8675f0672..027fab3dc181b 100644
--- a/Documentation/devicetree/bindings/regulator/rohm,bd71815-regulator.yaml
+++ b/Documentation/devicetree/bindings/regulator/rohm,bd71815-regulator.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: ROHM BD71815 Power Management Integrated Circuit regulators
 
 maintainers:
-  - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
+  - Matti Vaittinen <mazziesaccount@gmail.com>
 
 description: |
   This module is part of the ROHM BD718215 MFD device. For more details
diff --git a/Documentation/devicetree/bindings/regulator/rohm,bd71828-regulator.yaml b/Documentation/devicetree/bindings/regulator/rohm,bd71828-regulator.yaml
index 5ce587fff9615..3cbe3b76ccee6 100644
--- a/Documentation/devicetree/bindings/regulator/rohm,bd71828-regulator.yaml
+++ b/Documentation/devicetree/bindings/regulator/rohm,bd71828-regulator.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: ROHM BD71828 Power Management Integrated Circuit regulators
 
 maintainers:
-  - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
+  - Matti Vaittinen <mazziesaccount@gmail.com>
 
 description: |
   This module is part of the ROHM BD71828 MFD device. For more details
diff --git a/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.yaml b/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.yaml
index 1941b36cf1efa..ab842817d847f 100644
--- a/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.yaml
+++ b/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: ROHM BD71837 Power Management Integrated Circuit regulators
 
 maintainers:
-  - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
+  - Matti Vaittinen <mazziesaccount@gmail.com>
 
 description: |
   List of regulators provided by this controller. BD71837 regulators node
diff --git a/Documentation/devicetree/bindings/regulator/rohm,bd71847-regulator.yaml b/Documentation/devicetree/bindings/regulator/rohm,bd71847-regulator.yaml
index a1b8063738536..65fc3d15f693f 100644
--- a/Documentation/devicetree/bindings/regulator/rohm,bd71847-regulator.yaml
+++ b/Documentation/devicetree/bindings/regulator/rohm,bd71847-regulator.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: ROHM BD71847 and BD71850 Power Management Integrated Circuit regulators
 
 maintainers:
-  - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
+  - Matti Vaittinen <mazziesaccount@gmail.com>
 
 description: |
   List of regulators provided by this controller. BD71847 regulators node
diff --git a/Documentation/devicetree/bindings/regulator/rohm,bd9576-regulator.yaml b/Documentation/devicetree/bindings/regulator/rohm,bd9576-regulator.yaml
index 7cb74cc8c5d96..1e41168a49800 100644
--- a/Documentation/devicetree/bindings/regulator/rohm,bd9576-regulator.yaml
+++ b/Documentation/devicetree/bindings/regulator/rohm,bd9576-regulator.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: ROHM BD9576 and BD9573 Power Management Integrated Circuit regulators
 
 maintainers:
-  - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
+  - Matti Vaittinen <mazziesaccount@gmail.com>
 
 description: |
   This module is part of the ROHM BD9576 MFD device. For more details
-- 
GitLab


From f57c2eaaede3ada5db8c47b3ecdf24c58786f5f2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:45:19 +0100
Subject: [PATCH 327/875] backlight: adp8860: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
Acked-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-586-uwe@kleine-koenig.org
---
 drivers/video/backlight/adp8860_bl.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/video/backlight/adp8860_bl.c b/drivers/video/backlight/adp8860_bl.c
index b0fe02273e875..a479aab90f784 100644
--- a/drivers/video/backlight/adp8860_bl.c
+++ b/drivers/video/backlight/adp8860_bl.c
@@ -648,9 +648,9 @@ static const struct attribute_group adp8860_bl_attr_group = {
 	.attrs = adp8860_bl_attributes,
 };
 
-static int adp8860_probe(struct i2c_client *client,
-					const struct i2c_device_id *id)
+static int adp8860_probe(struct i2c_client *client)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(client);
 	struct backlight_device *bl;
 	struct adp8860_bl *data;
 	struct adp8860_backlight_platform_data *pdata =
@@ -803,7 +803,7 @@ static struct i2c_driver adp8860_driver = {
 		.name	= KBUILD_MODNAME,
 		.pm	= &adp8860_i2c_pm_ops,
 	},
-	.probe    = adp8860_probe,
+	.probe_new = adp8860_probe,
 	.remove   = adp8860_remove,
 	.id_table = adp8860_id,
 };
-- 
GitLab


From e78b28b8abab618284ef5de1f3aa4dc2b5151fe6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:45:20 +0100
Subject: [PATCH 328/875] backlight: adp8870: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-587-uwe@kleine-koenig.org
---
 drivers/video/backlight/adp8870_bl.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/video/backlight/adp8870_bl.c b/drivers/video/backlight/adp8870_bl.c
index 5becace3fd0f5..d6b0007db6491 100644
--- a/drivers/video/backlight/adp8870_bl.c
+++ b/drivers/video/backlight/adp8870_bl.c
@@ -836,9 +836,9 @@ static const struct attribute_group adp8870_bl_attr_group = {
 	.attrs = adp8870_bl_attributes,
 };
 
-static int adp8870_probe(struct i2c_client *client,
-					const struct i2c_device_id *id)
+static int adp8870_probe(struct i2c_client *client)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(client);
 	struct backlight_properties props;
 	struct backlight_device *bl;
 	struct adp8870_bl *data;
@@ -973,7 +973,7 @@ static struct i2c_driver adp8870_driver = {
 		.name	= KBUILD_MODNAME,
 		.pm	= &adp8870_i2c_pm_ops,
 	},
-	.probe    = adp8870_probe,
+	.probe_new = adp8870_probe,
 	.remove   = adp8870_remove,
 	.id_table = adp8870_id,
 };
-- 
GitLab


From 64ec2769813f07201c78db274af0b4d4bf84800c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:45:21 +0100
Subject: [PATCH 329/875] backlight: arcxcnn: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-588-uwe@kleine-koenig.org
---
 drivers/video/backlight/arcxcnn_bl.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/video/backlight/arcxcnn_bl.c b/drivers/video/backlight/arcxcnn_bl.c
index 060c0eef6a52d..555b036643fbc 100644
--- a/drivers/video/backlight/arcxcnn_bl.c
+++ b/drivers/video/backlight/arcxcnn_bl.c
@@ -241,7 +241,7 @@ static void arcxcnn_parse_dt(struct arcxcnn *lp)
 	}
 }
 
-static int arcxcnn_probe(struct i2c_client *cl, const struct i2c_device_id *id)
+static int arcxcnn_probe(struct i2c_client *cl)
 {
 	struct arcxcnn *lp;
 	int ret;
@@ -395,7 +395,7 @@ static struct i2c_driver arcxcnn_driver = {
 		.name = "arcxcnn_bl",
 		.of_match_table = of_match_ptr(arcxcnn_dt_ids),
 	},
-	.probe = arcxcnn_probe,
+	.probe_new = arcxcnn_probe,
 	.remove = arcxcnn_remove,
 	.id_table = arcxcnn_ids,
 };
-- 
GitLab


From 58d2b900c7b1fcc85fb6d285c86976dda9c70cc2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:45:22 +0100
Subject: [PATCH 330/875] backlight: bd6107: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-589-uwe@kleine-koenig.org
---
 drivers/video/backlight/bd6107.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/video/backlight/bd6107.c b/drivers/video/backlight/bd6107.c
index a506872d43963..f4db6c064635b 100644
--- a/drivers/video/backlight/bd6107.c
+++ b/drivers/video/backlight/bd6107.c
@@ -113,8 +113,7 @@ static const struct backlight_ops bd6107_backlight_ops = {
 	.check_fb	= bd6107_backlight_check_fb,
 };
 
-static int bd6107_probe(struct i2c_client *client,
-			  const struct i2c_device_id *id)
+static int bd6107_probe(struct i2c_client *client)
 {
 	struct bd6107_platform_data *pdata = dev_get_platdata(&client->dev);
 	struct backlight_device *backlight;
@@ -193,7 +192,7 @@ static struct i2c_driver bd6107_driver = {
 	.driver = {
 		.name = "bd6107",
 	},
-	.probe = bd6107_probe,
+	.probe_new = bd6107_probe,
 	.remove = bd6107_remove,
 	.id_table = bd6107_ids,
 };
-- 
GitLab


From b2d4f93f891d2d7281f0e907675f6b84836022a4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:45:23 +0100
Subject: [PATCH 331/875] backlight: lm3630a: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-590-uwe@kleine-koenig.org
---
 drivers/video/backlight/lm3630a_bl.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/video/backlight/lm3630a_bl.c b/drivers/video/backlight/lm3630a_bl.c
index 475f35635bf67..d8c42acecb5dd 100644
--- a/drivers/video/backlight/lm3630a_bl.c
+++ b/drivers/video/backlight/lm3630a_bl.c
@@ -491,8 +491,7 @@ static int lm3630a_parse_node(struct lm3630a_chip *pchip,
 	return ret;
 }
 
-static int lm3630a_probe(struct i2c_client *client,
-			 const struct i2c_device_id *id)
+static int lm3630a_probe(struct i2c_client *client)
 {
 	struct lm3630a_platform_data *pdata = dev_get_platdata(&client->dev);
 	struct lm3630a_chip *pchip;
@@ -617,7 +616,7 @@ static struct i2c_driver lm3630a_i2c_driver = {
 		   .name = LM3630A_NAME,
 		   .of_match_table = lm3630a_match_table,
 		   },
-	.probe = lm3630a_probe,
+	.probe_new = lm3630a_probe,
 	.remove = lm3630a_remove,
 	.id_table = lm3630a_id,
 };
-- 
GitLab


From 3065efe8af914407b206543c83c4b4c642b0ea62 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:45:24 +0100
Subject: [PATCH 332/875] backlight: lm3639: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-591-uwe@kleine-koenig.org
---
 drivers/video/backlight/lm3639_bl.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/video/backlight/lm3639_bl.c b/drivers/video/backlight/lm3639_bl.c
index 6580911671a3e..a836628ce06e8 100644
--- a/drivers/video/backlight/lm3639_bl.c
+++ b/drivers/video/backlight/lm3639_bl.c
@@ -296,8 +296,7 @@ static const struct regmap_config lm3639_regmap = {
 	.max_register = REG_MAX,
 };
 
-static int lm3639_probe(struct i2c_client *client,
-				  const struct i2c_device_id *id)
+static int lm3639_probe(struct i2c_client *client)
 {
 	int ret;
 	struct lm3639_chip_data *pchip;
@@ -412,7 +411,7 @@ static struct i2c_driver lm3639_i2c_driver = {
 	.driver = {
 		   .name = LM3639_NAME,
 		   },
-	.probe = lm3639_probe,
+	.probe_new = lm3639_probe,
 	.remove = lm3639_remove,
 	.id_table = lm3639_id,
 };
-- 
GitLab


From 60aa101b2f59538a1922107bdfd4428761ccf898 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:45:25 +0100
Subject: [PATCH 333/875] backlight: lp855x: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

.probe_new() doesn't get the i2c_device_id * parameter, so determine
that explicitly in the probe function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-592-uwe@kleine-koenig.org
---
 drivers/video/backlight/lp855x_bl.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/video/backlight/lp855x_bl.c b/drivers/video/backlight/lp855x_bl.c
index bd0bdeae23a4f..81012bf29bafc 100644
--- a/drivers/video/backlight/lp855x_bl.c
+++ b/drivers/video/backlight/lp855x_bl.c
@@ -394,8 +394,9 @@ static int lp855x_parse_acpi(struct lp855x *lp)
 	return 0;
 }
 
-static int lp855x_probe(struct i2c_client *cl, const struct i2c_device_id *id)
+static int lp855x_probe(struct i2c_client *cl)
 {
+	const struct i2c_device_id *id = i2c_client_get_device_id(cl);
 	const struct acpi_device_id *acpi_id = NULL;
 	struct device *dev = &cl->dev;
 	struct lp855x *lp;
@@ -586,7 +587,7 @@ static struct i2c_driver lp855x_driver = {
 		   .of_match_table = of_match_ptr(lp855x_dt_ids),
 		   .acpi_match_table = ACPI_PTR(lp855x_acpi_match),
 		   },
-	.probe = lp855x_probe,
+	.probe_new = lp855x_probe,
 	.remove = lp855x_remove,
 	.id_table = lp855x_ids,
 };
-- 
GitLab


From 5867af29c84507a1101115fc3dd6b28060ef2c03 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:45:26 +0100
Subject: [PATCH 334/875] backlight: lv5207lp: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-593-uwe@kleine-koenig.org
---
 drivers/video/backlight/lv5207lp.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/video/backlight/lv5207lp.c b/drivers/video/backlight/lv5207lp.c
index 767b800d79faf..00673c8b66ac5 100644
--- a/drivers/video/backlight/lv5207lp.c
+++ b/drivers/video/backlight/lv5207lp.c
@@ -76,8 +76,7 @@ static const struct backlight_ops lv5207lp_backlight_ops = {
 	.check_fb	= lv5207lp_backlight_check_fb,
 };
 
-static int lv5207lp_probe(struct i2c_client *client,
-			  const struct i2c_device_id *id)
+static int lv5207lp_probe(struct i2c_client *client)
 {
 	struct lv5207lp_platform_data *pdata = dev_get_platdata(&client->dev);
 	struct backlight_device *backlight;
@@ -142,7 +141,7 @@ static struct i2c_driver lv5207lp_driver = {
 	.driver = {
 		.name = "lv5207lp",
 	},
-	.probe = lv5207lp_probe,
+	.probe_new = lv5207lp_probe,
 	.remove = lv5207lp_remove,
 	.id_table = lv5207lp_ids,
 };
-- 
GitLab


From 0de796b6047d1ccc29d03fcd0a93dca52691ec21 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Fri, 18 Nov 2022 23:45:27 +0100
Subject: [PATCH 335/875] backlight: tosa: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so it
can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221118224540.619276-594-uwe@kleine-koenig.org
---
 drivers/video/backlight/tosa_bl.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/video/backlight/tosa_bl.c b/drivers/video/backlight/tosa_bl.c
index f55b3d616a871..77b71f6c19b58 100644
--- a/drivers/video/backlight/tosa_bl.c
+++ b/drivers/video/backlight/tosa_bl.c
@@ -75,8 +75,7 @@ static const struct backlight_ops bl_ops = {
 	.update_status		= tosa_bl_update_status,
 };
 
-static int tosa_bl_probe(struct i2c_client *client,
-		const struct i2c_device_id *id)
+static int tosa_bl_probe(struct i2c_client *client)
 {
 	struct backlight_properties props;
 	struct tosa_bl_data *data;
@@ -160,7 +159,7 @@ static struct i2c_driver tosa_bl_driver = {
 		.name		= "tosa-bl",
 		.pm		= &tosa_bl_pm_ops,
 	},
-	.probe		= tosa_bl_probe,
+	.probe_new	= tosa_bl_probe,
 	.remove		= tosa_bl_remove,
 	.id_table	= tosa_bl_id,
 };
-- 
GitLab


From 4bf5bf54476dffe60e6b6d8d539f67309ff599e2 Mon Sep 17 00:00:00 2001
From: Edward Pacman <edward@edward-p.xyz>
Date: Wed, 7 Dec 2022 21:32:18 +0800
Subject: [PATCH 336/875] ALSA: hda/realtek: Add quirk for Lenovo
 TianYi510Pro-14IOB

Lenovo TianYi510Pro-14IOB (17aa:3742)
require quirk for enabling headset-mic

Signed-off-by: Edward Pacman <edward@edward-p.xyz>
Cc: <stable@vger.kernel.org>
Link: https://bugzilla.kernel.org/show_bug.cgi?id=216756
Link: https://lore.kernel.org/r/20221207133218.18989-1-edward@edward-p.xyz
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/pci/hda/patch_realtek.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index 5f51f8fc7fdcd..e443d88f627f0 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -10999,6 +10999,17 @@ static void alc897_fixup_lenovo_headset_mic(struct hda_codec *codec,
 	}
 }
 
+static void alc897_fixup_lenovo_headset_mode(struct hda_codec *codec,
+				     const struct hda_fixup *fix, int action)
+{
+	struct alc_spec *spec = codec->spec;
+
+	if (action == HDA_FIXUP_ACT_PRE_PROBE) {
+		spec->parse_flags |= HDA_PINCFG_HEADSET_MIC;
+		spec->gen.hp_automute_hook = alc897_hp_automute_hook;
+	}
+}
+
 static const struct coef_fw alc668_coefs[] = {
 	WRITE_COEF(0x01, 0xbebe), WRITE_COEF(0x02, 0xaaaa), WRITE_COEF(0x03,    0x0),
 	WRITE_COEF(0x04, 0x0180), WRITE_COEF(0x06,    0x0), WRITE_COEF(0x07, 0x0f80),
@@ -11082,6 +11093,8 @@ enum {
 	ALC897_FIXUP_LENOVO_HEADSET_MIC,
 	ALC897_FIXUP_HEADSET_MIC_PIN,
 	ALC897_FIXUP_HP_HSMIC_VERB,
+	ALC897_FIXUP_LENOVO_HEADSET_MODE,
+	ALC897_FIXUP_HEADSET_MIC_PIN2,
 };
 
 static const struct hda_fixup alc662_fixups[] = {
@@ -11508,6 +11521,19 @@ static const struct hda_fixup alc662_fixups[] = {
 			{ }
 		},
 	},
+	[ALC897_FIXUP_LENOVO_HEADSET_MODE] = {
+		.type = HDA_FIXUP_FUNC,
+		.v.func = alc897_fixup_lenovo_headset_mode,
+	},
+	[ALC897_FIXUP_HEADSET_MIC_PIN2] = {
+		.type = HDA_FIXUP_PINS,
+		.v.pins = (const struct hda_pintbl[]) {
+			{ 0x1a, 0x01a11140 }, /* use as headset mic, without its own jack detect */
+			{ }
+		},
+		.chained = true,
+		.chain_id = ALC897_FIXUP_LENOVO_HEADSET_MODE
+	},
 };
 
 static const struct snd_pci_quirk alc662_fixup_tbl[] = {
@@ -11560,6 +11586,7 @@ static const struct snd_pci_quirk alc662_fixup_tbl[] = {
 	SND_PCI_QUIRK(0x17aa, 0x32cb, "Lenovo ThinkCentre M70", ALC897_FIXUP_HEADSET_MIC_PIN),
 	SND_PCI_QUIRK(0x17aa, 0x32cf, "Lenovo ThinkCentre M950", ALC897_FIXUP_HEADSET_MIC_PIN),
 	SND_PCI_QUIRK(0x17aa, 0x32f7, "Lenovo ThinkCentre M90", ALC897_FIXUP_HEADSET_MIC_PIN),
+	SND_PCI_QUIRK(0x17aa, 0x3742, "Lenovo TianYi510Pro-14IOB", ALC897_FIXUP_HEADSET_MIC_PIN2),
 	SND_PCI_QUIRK(0x17aa, 0x38af, "Lenovo Ideapad Y550P", ALC662_FIXUP_IDEAPAD),
 	SND_PCI_QUIRK(0x17aa, 0x3a0d, "Lenovo Ideapad Y550", ALC662_FIXUP_IDEAPAD),
 	SND_PCI_QUIRK(0x1849, 0x5892, "ASRock B150M", ALC892_FIXUP_ASROCK_MOBO),
-- 
GitLab


From 72d9a541d7f186f0ec97c71ba7e477dd9bf4155f Mon Sep 17 00:00:00 2001
From: Cezary Rojewski <cezary.rojewski@intel.com>
Date: Mon, 5 Dec 2022 09:53:25 +0100
Subject: [PATCH 337/875] ASoC: Intel: Skylake: Update pipe_config_idx before
 filling BE params

Without updating the index before BE copier config is filled with
hardware parameters, outdated parameters are used instead.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Tested-by: Lukasz Majczak <lma@semihlaf.com>
Link: https://lore.kernel.org/r/20221205085330.857665-2-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/skylake/skl-topology.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/sound/soc/intel/skylake/skl-topology.c b/sound/soc/intel/skylake/skl-topology.c
index e06eac592da12..fc3d719d93e1e 100644
--- a/sound/soc/intel/skylake/skl-topology.c
+++ b/sound/soc/intel/skylake/skl-topology.c
@@ -1837,16 +1837,24 @@ static int skl_tplg_be_fill_pipe_params(struct snd_soc_dai *dai,
 {
 	struct nhlt_specific_cfg *cfg;
 	struct skl_pipe *pipe = mconfig->pipe;
+	struct skl_pipe_params save = *pipe->p_params;
 	struct skl_pipe_fmt *pipe_fmt;
 	struct skl_dev *skl = get_skl_ctx(dai->dev);
 	int link_type = skl_tplg_be_link_type(mconfig->dev_type);
 	u8 dev_type = skl_tplg_be_dev_type(mconfig->dev_type);
+	int ret;
 
 	skl_tplg_fill_dma_id(mconfig, params);
 
 	if (link_type == NHLT_LINK_HDA)
 		return 0;
 
+	*pipe->p_params = *params;
+	ret = skl_tplg_get_pipe_config(skl, mconfig);
+	if (ret)
+		goto err;
+
+	dev_dbg(skl->dev, "%s using pipe config: %d\n", __func__, pipe->pipe_config_idx);
 	if (pipe->direction == SNDRV_PCM_STREAM_PLAYBACK)
 		pipe_fmt = &pipe->configs[pipe->pipe_config_idx].out_fmt;
 	else
@@ -1865,10 +1873,15 @@ static int skl_tplg_be_fill_pipe_params(struct snd_soc_dai *dai,
 		dev_err(dai->dev, "Blob NULL for id:%d type:%d dirn:%d ch:%d, freq:%d, fmt:%d\n",
 			mconfig->vbus_id, link_type, params->stream,
 			params->ch, params->s_freq, params->s_fmt);
-		return -EINVAL;
+		ret = -EINVAL;
+		goto err;
 	}
 
 	return 0;
+
+err:
+	*pipe->p_params = save;
+	return ret;
 }
 
 static int skl_tplg_be_set_src_pipe_params(struct snd_soc_dai *dai,
-- 
GitLab


From b0d16e54e7559f2055123ea7b1d9ff1bb808ebad Mon Sep 17 00:00:00 2001
From: Cezary Rojewski <cezary.rojewski@intel.com>
Date: Mon, 5 Dec 2022 09:53:26 +0100
Subject: [PATCH 338/875] ASoC: Intel: Skylake: Remove skl_tplg_is_multi_fmt()

Rather than forcing userspace to select proper format with enumerable
kcontrols, select it ourselves based on provided hw_params.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Tested-by: Lukasz Majczak <lma@semihlaf.com>
Link: https://lore.kernel.org/r/20221205085330.857665-3-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/skylake/skl-topology.c | 40 --------------------------
 1 file changed, 40 deletions(-)

diff --git a/sound/soc/intel/skylake/skl-topology.c b/sound/soc/intel/skylake/skl-topology.c
index fc3d719d93e1e..f144acae1b440 100644
--- a/sound/soc/intel/skylake/skl-topology.c
+++ b/sound/soc/intel/skylake/skl-topology.c
@@ -582,38 +582,6 @@ static int skl_tplg_unload_pipe_modules(struct skl_dev *skl,
 	return ret;
 }
 
-static bool skl_tplg_is_multi_fmt(struct skl_dev *skl, struct skl_pipe *pipe)
-{
-	struct skl_pipe_fmt *cur_fmt;
-	struct skl_pipe_fmt *next_fmt;
-	int i;
-
-	if (pipe->nr_cfgs <= 1)
-		return false;
-
-	if (pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
-		return true;
-
-	for (i = 0; i < pipe->nr_cfgs - 1; i++) {
-		if (pipe->direction == SNDRV_PCM_STREAM_PLAYBACK) {
-			cur_fmt = &pipe->configs[i].out_fmt;
-			next_fmt = &pipe->configs[i + 1].out_fmt;
-		} else {
-			cur_fmt = &pipe->configs[i].in_fmt;
-			next_fmt = &pipe->configs[i + 1].in_fmt;
-		}
-
-		if (!CHECK_HW_PARAMS(cur_fmt->channels, cur_fmt->freq,
-				     cur_fmt->bps,
-				     next_fmt->channels,
-				     next_fmt->freq,
-				     next_fmt->bps))
-			return true;
-	}
-
-	return false;
-}
-
 /*
  * Here, we select pipe format based on the pipe type and pipe
  * direction to determine the current config index for the pipeline.
@@ -636,14 +604,6 @@ skl_tplg_get_pipe_config(struct skl_dev *skl, struct skl_module_cfg *mconfig)
 		return 0;
 	}
 
-	if (skl_tplg_is_multi_fmt(skl, pipe)) {
-		pipe->cur_config_idx = pipe->pipe_config_idx;
-		pipe->memory_pages = pconfig->mem_pages;
-		dev_dbg(skl->dev, "found pipe config idx:%d\n",
-			pipe->cur_config_idx);
-		return 0;
-	}
-
 	if (pipe->conn_type == SKL_PIPE_CONN_TYPE_NONE || pipe->nr_cfgs == 1) {
 		dev_dbg(skl->dev, "No conn_type or just 1 pathcfg, taking 0th for %d\n",
 			pipe->ppl_id);
-- 
GitLab


From 75ab3c00769009e32e5cf51c8b503de4f73114e4 Mon Sep 17 00:00:00 2001
From: Cezary Rojewski <cezary.rojewski@intel.com>
Date: Mon, 5 Dec 2022 09:53:27 +0100
Subject: [PATCH 339/875] ASoC: Intel: Skylake: Drop pipe_config_idx

Field ->pipe_config_idx duplicates the job of ->cur_config_idx so
remove it.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Tested-by: Lukasz Majczak <lma@semihlaf.com>
Link: https://lore.kernel.org/r/20221205085330.857665-4-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/skylake/skl-topology.c | 10 +++++-----
 sound/soc/intel/skylake/skl-topology.h |  1 -
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/sound/soc/intel/skylake/skl-topology.c b/sound/soc/intel/skylake/skl-topology.c
index f144acae1b440..567a3b661ce4c 100644
--- a/sound/soc/intel/skylake/skl-topology.c
+++ b/sound/soc/intel/skylake/skl-topology.c
@@ -1351,9 +1351,9 @@ static int skl_tplg_multi_config_set_get(struct snd_kcontrol *kcontrol,
 		return -EIO;
 
 	if (is_set)
-		pipe->pipe_config_idx = ucontrol->value.enumerated.item[0];
+		pipe->cur_config_idx = ucontrol->value.enumerated.item[0];
 	else
-		ucontrol->value.enumerated.item[0]  =  pipe->pipe_config_idx;
+		ucontrol->value.enumerated.item[0] = pipe->cur_config_idx;
 
 	return 0;
 }
@@ -1814,11 +1814,11 @@ static int skl_tplg_be_fill_pipe_params(struct snd_soc_dai *dai,
 	if (ret)
 		goto err;
 
-	dev_dbg(skl->dev, "%s using pipe config: %d\n", __func__, pipe->pipe_config_idx);
+	dev_dbg(skl->dev, "%s using pipe config: %d\n", __func__, pipe->cur_config_idx);
 	if (pipe->direction == SNDRV_PCM_STREAM_PLAYBACK)
-		pipe_fmt = &pipe->configs[pipe->pipe_config_idx].out_fmt;
+		pipe_fmt = &pipe->configs[pipe->cur_config_idx].out_fmt;
 	else
-		pipe_fmt = &pipe->configs[pipe->pipe_config_idx].in_fmt;
+		pipe_fmt = &pipe->configs[pipe->cur_config_idx].in_fmt;
 
 	/* update the blob based on virtual bus_id*/
 	cfg = intel_nhlt_get_endpoint_blob(dai->dev, skl->nhlt,
diff --git a/sound/soc/intel/skylake/skl-topology.h b/sound/soc/intel/skylake/skl-topology.h
index 017ac0ef324dd..6db0fd7bad49c 100644
--- a/sound/soc/intel/skylake/skl-topology.h
+++ b/sound/soc/intel/skylake/skl-topology.h
@@ -324,7 +324,6 @@ struct skl_pipe {
 	struct skl_path_config configs[SKL_MAX_PATH_CONFIGS];
 	struct list_head w_list;
 	bool passthru;
-	u32 pipe_config_idx;
 };
 
 enum skl_module_state {
-- 
GitLab


From 4ac587f3578c5ca490e4df55af6403f5474eb2f0 Mon Sep 17 00:00:00 2001
From: Cezary Rojewski <cezary.rojewski@intel.com>
Date: Mon, 5 Dec 2022 09:53:28 +0100
Subject: [PATCH 340/875] ASoC: Intel: Skylake: Introduce single place for
 pipe-config selection

Provide a single location for pipe config selection where all fields
that have to be updated whenever ->pipe_config_idx changes can be
updated accordingly.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Tested-by: Lukasz Majczak <lma@semihlaf.com>
Link: https://lore.kernel.org/r/20221205085330.857665-5-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/skylake/skl-topology.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/sound/soc/intel/skylake/skl-topology.c b/sound/soc/intel/skylake/skl-topology.c
index 567a3b661ce4c..b20643b834012 100644
--- a/sound/soc/intel/skylake/skl-topology.c
+++ b/sound/soc/intel/skylake/skl-topology.c
@@ -582,6 +582,12 @@ static int skl_tplg_unload_pipe_modules(struct skl_dev *skl,
 	return ret;
 }
 
+static void skl_tplg_set_pipe_config_idx(struct skl_pipe *pipe, int idx)
+{
+	pipe->cur_config_idx = idx;
+	pipe->memory_pages = pipe->configs[idx].mem_pages;
+}
+
 /*
  * Here, we select pipe format based on the pipe type and pipe
  * direction to determine the current config index for the pipeline.
@@ -600,16 +606,14 @@ skl_tplg_get_pipe_config(struct skl_dev *skl, struct skl_module_cfg *mconfig)
 	int i;
 
 	if (pipe->nr_cfgs == 0) {
-		pipe->cur_config_idx = 0;
+		skl_tplg_set_pipe_config_idx(pipe, 0);
 		return 0;
 	}
 
 	if (pipe->conn_type == SKL_PIPE_CONN_TYPE_NONE || pipe->nr_cfgs == 1) {
 		dev_dbg(skl->dev, "No conn_type or just 1 pathcfg, taking 0th for %d\n",
 			pipe->ppl_id);
-		pipe->cur_config_idx = 0;
-		pipe->memory_pages = pconfig->mem_pages;
-
+		skl_tplg_set_pipe_config_idx(pipe, 0);
 		return 0;
 	}
 
@@ -628,10 +632,8 @@ skl_tplg_get_pipe_config(struct skl_dev *skl, struct skl_module_cfg *mconfig)
 
 		if (CHECK_HW_PARAMS(params->ch, params->s_freq, params->s_fmt,
 				    fmt->channels, fmt->freq, fmt->bps)) {
-			pipe->cur_config_idx = i;
-			pipe->memory_pages = pconfig->mem_pages;
+			skl_tplg_set_pipe_config_idx(pipe, i);
 			dev_dbg(skl->dev, "Using pipe config: %d\n", i);
-
 			return 0;
 		}
 	}
@@ -1351,7 +1353,7 @@ static int skl_tplg_multi_config_set_get(struct snd_kcontrol *kcontrol,
 		return -EIO;
 
 	if (is_set)
-		pipe->cur_config_idx = ucontrol->value.enumerated.item[0];
+		skl_tplg_set_pipe_config_idx(pipe, ucontrol->value.enumerated.item[0]);
 	else
 		ucontrol->value.enumerated.item[0] = pipe->cur_config_idx;
 
-- 
GitLab


From 171107237246d66bce04f3769d33648f896b4ce3 Mon Sep 17 00:00:00 2001
From: Cezary Rojewski <cezary.rojewski@intel.com>
Date: Mon, 5 Dec 2022 09:53:29 +0100
Subject: [PATCH 341/875] ASoC: Intel: Skylake: Fix driver hang during shutdown

AudioDSP cores and HDAudio links need to be turned off on shutdown to
ensure no communication or data transfer occurs during the procedure.

Fixes: c5a76a246989 ("ASoC: Intel: Skylake: Add shutdown callback")
Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Tested-by: Lukasz Majczak <lma@semihlaf.com>
Link: https://lore.kernel.org/r/20221205085330.857665-6-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/skylake/skl.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/sound/soc/intel/skylake/skl.c b/sound/soc/intel/skylake/skl.c
index 9bd9f98668988..998bd0232cf1d 100644
--- a/sound/soc/intel/skylake/skl.c
+++ b/sound/soc/intel/skylake/skl.c
@@ -1107,7 +1107,10 @@ static void skl_shutdown(struct pci_dev *pci)
 	if (!skl->init_done)
 		return;
 
-	snd_hdac_stop_streams_and_chip(bus);
+	snd_hdac_stop_streams(bus);
+	snd_hdac_ext_bus_link_power_down_all(bus);
+	skl_dsp_sleep(skl->dsp);
+
 	list_for_each_entry(s, &bus->stream_list, list) {
 		stream = stream_to_hdac_ext_stream(s);
 		snd_hdac_ext_stream_decouple(bus, stream, false);
-- 
GitLab


From 451d85c46cf719a09a052510d4d4cd920103163a Mon Sep 17 00:00:00 2001
From: Cezary Rojewski <cezary.rojewski@intel.com>
Date: Mon, 5 Dec 2022 09:53:30 +0100
Subject: [PATCH 342/875] ASoC: Intel: Skylake: Use SG allocation for SKL-based
 firmware load

Resign from ->alloc_dma_buf() and use snd_dma_alloc_pages() directly.
For data i.e.: base firmware binary transfer, make use of SG allocation
to better adapt to memory-limited environment. For BDL descriptor, given
its small size this is not required.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Tested-by: Lukasz Majczak <lma@semihlaf.com>
Link: https://lore.kernel.org/r/20221205085330.857665-7-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/skylake/skl-sst-cldma.c | 27 +++++++++++++++----------
 1 file changed, 16 insertions(+), 11 deletions(-)

diff --git a/sound/soc/intel/skylake/skl-sst-cldma.c b/sound/soc/intel/skylake/skl-sst-cldma.c
index b91f7a652a2b1..b0204ea00f07f 100644
--- a/sound/soc/intel/skylake/skl-sst-cldma.c
+++ b/sound/soc/intel/skylake/skl-sst-cldma.c
@@ -11,6 +11,7 @@
 #include <linux/io.h>
 #include <linux/mm.h>
 #include <linux/delay.h>
+#include <sound/hda_register.h>
 #include "../common/sst-dsp.h"
 #include "../common/sst-dsp-priv.h"
 
@@ -79,21 +80,25 @@ static void skl_cldma_setup_bdle(struct sst_dsp *ctx,
 		__le32 **bdlp, int size, int with_ioc)
 {
 	__le32 *bdl = *bdlp;
+	int remaining = ctx->cl_dev.bufsize;
+	int offset = 0;
 
 	ctx->cl_dev.frags = 0;
-	while (size > 0) {
-		phys_addr_t addr = virt_to_phys(dmab_data->area +
-				(ctx->cl_dev.frags * ctx->cl_dev.bufsize));
+	while (remaining > 0) {
+		phys_addr_t addr;
+		int chunk;
 
+		addr = snd_sgbuf_get_addr(dmab_data, offset);
 		bdl[0] = cpu_to_le32(lower_32_bits(addr));
 		bdl[1] = cpu_to_le32(upper_32_bits(addr));
+		chunk = snd_sgbuf_get_chunk_size(dmab_data, offset, size);
+		bdl[2] = cpu_to_le32(chunk);
 
-		bdl[2] = cpu_to_le32(ctx->cl_dev.bufsize);
-
-		size -= ctx->cl_dev.bufsize;
-		bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
+		remaining -= chunk;
+		bdl[3] = (remaining > 0) ? 0 : cpu_to_le32(0x01);
 
 		bdl += 4;
+		offset += chunk;
 		ctx->cl_dev.frags++;
 	}
 }
@@ -338,15 +343,15 @@ int skl_cldma_prepare(struct sst_dsp *ctx)
 	ctx->cl_dev.ops.cl_stop_dma = skl_cldma_stop;
 
 	/* Allocate buffer*/
-	ret = ctx->dsp_ops.alloc_dma_buf(ctx->dev,
-			&ctx->cl_dev.dmab_data, ctx->cl_dev.bufsize);
+	ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, ctx->dev, ctx->cl_dev.bufsize,
+				  &ctx->cl_dev.dmab_data);
 	if (ret < 0) {
 		dev_err(ctx->dev, "Alloc buffer for base fw failed: %x\n", ret);
 		return ret;
 	}
+
 	/* Setup Code loader BDL */
-	ret = ctx->dsp_ops.alloc_dma_buf(ctx->dev,
-			&ctx->cl_dev.dmab_bdl, PAGE_SIZE);
+	ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, ctx->dev, BDL_SIZE, &ctx->cl_dev.dmab_bdl);
 	if (ret < 0) {
 		dev_err(ctx->dev, "Alloc buffer for blde failed: %x\n", ret);
 		ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
-- 
GitLab


From c0660fce5e0672b9fcffaae02184d58c8ed2aec1 Mon Sep 17 00:00:00 2001
From: Brent Lu <brent.lu@intel.com>
Date: Tue, 6 Dec 2022 15:25:05 -0600
Subject: [PATCH 343/875] ASoC: Intel: sof_rt5682: add jsl_rt5682 board config

This configuration supports JSL boards which implement ALC5682I-VD/VS
on SSP0 port.

Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: Brent Lu <brent.lu@intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20221206212507.359993-2-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/boards/sof_rt5682.c               | 6 ++++++
 sound/soc/intel/common/soc-acpi-intel-jsl-match.c | 5 +++++
 2 files changed, 11 insertions(+)

diff --git a/sound/soc/intel/boards/sof_rt5682.c b/sound/soc/intel/boards/sof_rt5682.c
index 4a2f91249b10c..2eabc4b0fafa4 100644
--- a/sound/soc/intel/boards/sof_rt5682.c
+++ b/sound/soc/intel/boards/sof_rt5682.c
@@ -1104,6 +1104,12 @@ static const struct platform_device_id board_ids[] = {
 					SOF_RT5682_SSP_AMP(1) |
 					SOF_RT5682_NUM_HDMIDEV(4)),
 	},
+	{
+		.name = "jsl_rt5682",
+		.driver_data = (kernel_ulong_t)(SOF_RT5682_MCLK_EN |
+					SOF_RT5682_MCLK_24MHZ |
+					SOF_RT5682_SSP_CODEC(0)),
+	},
 	{ }
 };
 MODULE_DEVICE_TABLE(platform, board_ids);
diff --git a/sound/soc/intel/common/soc-acpi-intel-jsl-match.c b/sound/soc/intel/common/soc-acpi-intel-jsl-match.c
index b95c4b2cda947..f5c7e1bbded06 100644
--- a/sound/soc/intel/common/soc-acpi-intel-jsl-match.c
+++ b/sound/soc/intel/common/soc-acpi-intel-jsl-match.c
@@ -78,6 +78,11 @@ struct snd_soc_acpi_mach snd_soc_acpi_intel_jsl_machines[] = {
 		.quirk_data = &mx98360a_spk,
 		.sof_tplg_filename = "sof-jsl-rt5682-mx98360a.tplg",
 	},
+	{
+		.comp_ids = &rt5682_rt5682s_hp,
+		.drv_name = "jsl_rt5682",
+		.sof_tplg_filename = "sof-jsl-rt5682.tplg",
+	},
 	{
 		.id = "10134242",
 		.drv_name = "jsl_cs4242_mx98360a",
-- 
GitLab


From 5c10da436ebd93f9bfa244ea933773d14b566499 Mon Sep 17 00:00:00 2001
From: Gongjun Song <gongjun.song@intel.com>
Date: Tue, 6 Dec 2022 15:25:06 -0600
Subject: [PATCH 344/875] ASoC: Intel: sof_sdw: use common helpers for all
 Realtek amps

sof_sdw_rt1308.c/sof_sdw_rt1316.c/sof_sdw_rt1318.c handle amp
in basically the same way, optimized and merged into one file.

Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Signed-off-by: Gongjun Song <gongjun.song@intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20221206212507.359993-3-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/boards/Makefile               |   3 +-
 sound/soc/intel/boards/sof_sdw.c              |  10 +-
 sound/soc/intel/boards/sof_sdw_common.h       |  20 +-
 sound/soc/intel/boards/sof_sdw_rt1316.c       | 239 ------------------
 sound/soc/intel/boards/sof_sdw_rt1318.c       | 120 ---------
 .../{sof_sdw_rt1308.c => sof_sdw_rt_amp.c}    | 139 +++++++---
 6 files changed, 120 insertions(+), 411 deletions(-)
 delete mode 100644 sound/soc/intel/boards/sof_sdw_rt1316.c
 delete mode 100644 sound/soc/intel/boards/sof_sdw_rt1318.c
 rename sound/soc/intel/boards/{sof_sdw_rt1308.c => sof_sdw_rt_amp.c} (59%)

diff --git a/sound/soc/intel/boards/Makefile b/sound/soc/intel/boards/Makefile
index 7e1a4ff77ac32..d1fd7a2b32dbc 100644
--- a/sound/soc/intel/boards/Makefile
+++ b/sound/soc/intel/boards/Makefile
@@ -37,8 +37,7 @@ snd-soc-sof_da7219_max98373-objs := sof_da7219_max98373.o
 snd-soc-ehl-rt5660-objs := ehl_rt5660.o
 snd-soc-sof-ssp-amp-objs := sof_ssp_amp.o
 snd-soc-sof-sdw-objs += sof_sdw.o				\
-			sof_sdw_max98373.o sof_sdw_rt1308.o	\
-			sof_sdw_rt1316.o sof_sdw_rt1318.o	\
+			sof_sdw_max98373.o sof_sdw_rt_amp.o	\
 			sof_sdw_rt5682.o sof_sdw_rt700.o	\
 			sof_sdw_rt711.o sof_sdw_rt711_sdca.o 	\
 			sof_sdw_rt715.o	sof_sdw_rt715_sdca.o 	\
diff --git a/sound/soc/intel/boards/sof_sdw.c b/sound/soc/intel/boards/sof_sdw.c
index b58c7b35599d2..d2ed807abde95 100644
--- a/sound/soc/intel/boards/sof_sdw.c
+++ b/sound/soc/intel/boards/sof_sdw.c
@@ -550,23 +550,23 @@ static struct sof_sdw_codec_info codec_info_list[] = {
 		.direction = {true, false},
 		.dai_name = "rt1308-aif",
 		.ops = &sof_sdw_rt1308_i2s_ops,
-		.init = sof_sdw_rt1308_init,
-		.exit = sof_sdw_rt1308_exit,
+		.init = sof_sdw_rt_amp_init,
+		.exit = sof_sdw_rt_amp_exit,
 		.codec_type = SOF_SDW_CODEC_TYPE_AMP,
 	},
 	{
 		.part_id = 0x1316,
 		.direction = {true, true},
 		.dai_name = "rt1316-aif",
-		.init = sof_sdw_rt1316_init,
-		.exit = sof_sdw_rt1316_exit,
+		.init = sof_sdw_rt_amp_init,
+		.exit = sof_sdw_rt_amp_exit,
 		.codec_type = SOF_SDW_CODEC_TYPE_AMP,
 	},
 	{
 		.part_id = 0x1318,
 		.direction = {true, true},
 		.dai_name = "rt1318-aif",
-		.init = sof_sdw_rt1318_init,
+		.init = sof_sdw_rt_amp_init,
 		.codec_type = SOF_SDW_CODEC_TYPE_AMP,
 	},
 	{
diff --git a/sound/soc/intel/boards/sof_sdw_common.h b/sound/soc/intel/boards/sof_sdw_common.h
index 54a50f7da4da7..350010b0e5f4f 100644
--- a/sound/soc/intel/boards/sof_sdw_common.h
+++ b/sound/soc/intel/boards/sof_sdw_common.h
@@ -125,30 +125,18 @@ int sof_sdw_rt700_init(struct snd_soc_card *card,
 		       struct sof_sdw_codec_info *info,
 		       bool playback);
 
-/* RT1308 support */
+/* RT1308 I2S support */
 extern struct snd_soc_ops sof_sdw_rt1308_i2s_ops;
 
-int sof_sdw_rt1308_init(struct snd_soc_card *card,
+/* generic amp support */
+int sof_sdw_rt_amp_init(struct snd_soc_card *card,
 			const struct snd_soc_acpi_link_adr *link,
 			struct snd_soc_dai_link *dai_links,
 			struct sof_sdw_codec_info *info,
 			bool playback);
-int sof_sdw_rt1308_exit(struct snd_soc_card *card, struct snd_soc_dai_link *dai_link);
+int sof_sdw_rt_amp_exit(struct snd_soc_card *card, struct snd_soc_dai_link *dai_link);
 
 /* RT1316 support */
-int sof_sdw_rt1316_init(struct snd_soc_card *card,
-			const struct snd_soc_acpi_link_adr *link,
-			struct snd_soc_dai_link *dai_links,
-			struct sof_sdw_codec_info *info,
-			bool playback);
-int sof_sdw_rt1316_exit(struct snd_soc_card *card, struct snd_soc_dai_link *dai_link);
-
-/* RT1318 support */
-int sof_sdw_rt1318_init(struct snd_soc_card *card,
-			const struct snd_soc_acpi_link_adr *link,
-			struct snd_soc_dai_link *dai_links,
-			struct sof_sdw_codec_info *info,
-			bool playback);
 
 /* RT715 support */
 int sof_sdw_rt715_init(struct snd_soc_card *card,
diff --git a/sound/soc/intel/boards/sof_sdw_rt1316.c b/sound/soc/intel/boards/sof_sdw_rt1316.c
deleted file mode 100644
index f6bbea0d38105..0000000000000
--- a/sound/soc/intel/boards/sof_sdw_rt1316.c
+++ /dev/null
@@ -1,239 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-// Copyright (c) 2020 Intel Corporation
-
-/*
- *  sof_sdw_rt1316 - Helpers to handle RT1316 from generic machine driver
- */
-
-#include <linux/device.h>
-#include <linux/errno.h>
-#include <sound/control.h>
-#include <sound/soc.h>
-#include <sound/soc-acpi.h>
-#include <sound/soc-dapm.h>
-#include <linux/soundwire/sdw.h>
-#include <linux/soundwire/sdw_type.h>
-#include <linux/dmi.h>
-#include "sof_sdw_common.h"
-#include "sof_sdw_amp_coeff_tables.h"
-
-struct rt1316_platform_data {
-	const unsigned char *bq_params;
-	const unsigned int bq_params_cnt;
-};
-
-static const struct rt1316_platform_data dell_0b00_platform_data = {
-	.bq_params = dell_0b00_bq_params,
-	.bq_params_cnt = ARRAY_SIZE(dell_0b00_bq_params),
-};
-
-static const struct dmi_system_id dmi_platform_data[] = {
-	/* AlderLake devices */
-	{
-		.matches = {
-			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
-			DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0B00")
-		},
-		.driver_data = (void *)&dell_0b00_platform_data,
-	},
-	{
-		.matches = {
-			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
-			DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0B01")
-		},
-		.driver_data = (void *)&dell_0b00_platform_data,
-	},
-	{
-		.matches = {
-			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
-			DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0AFF")
-		},
-		.driver_data = (void *)&dell_0b00_platform_data,
-	},
-	{
-		.matches = {
-			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
-			DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0AFE")
-		},
-		.driver_data = (void *)&dell_0b00_platform_data,
-	},
-};
-
-static int rt1316_add_device_props(struct device *sdw_dev)
-{
-	struct property_entry props[3] = {};
-	struct fwnode_handle *fwnode;
-	const struct dmi_system_id *dmi_data;
-	const struct rt1316_platform_data *pdata;
-	unsigned char params[RT1316_MAX_BQ_REG];
-	int ret;
-
-	dmi_data = dmi_first_match(dmi_platform_data);
-	if (!dmi_data)
-		return 0;
-
-	pdata = dmi_data->driver_data;
-	memcpy(&params, pdata->bq_params, sizeof(unsigned char) * pdata->bq_params_cnt);
-
-	props[0] = PROPERTY_ENTRY_U8_ARRAY("realtek,bq-params", params);
-	props[1] = PROPERTY_ENTRY_U32("realtek,bq-params-cnt", pdata->bq_params_cnt);
-
-	fwnode = fwnode_create_software_node(props, NULL);
-	if (IS_ERR(fwnode))
-		return PTR_ERR(fwnode);
-
-	ret = device_add_software_node(sdw_dev, to_software_node(fwnode));
-
-	fwnode_handle_put(fwnode);
-
-	return ret;
-}
-
-static const struct snd_soc_dapm_widget rt1316_widgets[] = {
-	SND_SOC_DAPM_SPK("Speaker", NULL),
-};
-
-/*
- * dapm routes for rt1316 will be registered dynamically according
- * to the number of rt1316 used. The first two entries will be registered
- * for one codec case, and the last two entries are also registered
- * if two 1316s are used.
- */
-static const struct snd_soc_dapm_route rt1316_map[] = {
-	{ "Speaker", NULL, "rt1316-1 SPOL" },
-	{ "Speaker", NULL, "rt1316-1 SPOR" },
-	{ "Speaker", NULL, "rt1316-2 SPOL" },
-	{ "Speaker", NULL, "rt1316-2 SPOR" },
-};
-
-static const struct snd_kcontrol_new rt1316_controls[] = {
-	SOC_DAPM_PIN_SWITCH("Speaker"),
-};
-
-static int first_spk_init(struct snd_soc_pcm_runtime *rtd)
-{
-	struct snd_soc_card *card = rtd->card;
-	int ret;
-
-	card->components = devm_kasprintf(card->dev, GFP_KERNEL,
-					  "%s spk:rt1316",
-					  card->components);
-	if (!card->components)
-		return -ENOMEM;
-
-	ret = snd_soc_add_card_controls(card, rt1316_controls,
-					ARRAY_SIZE(rt1316_controls));
-	if (ret) {
-		dev_err(card->dev, "rt1316 controls addition failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = snd_soc_dapm_new_controls(&card->dapm, rt1316_widgets,
-					ARRAY_SIZE(rt1316_widgets));
-	if (ret) {
-		dev_err(card->dev, "rt1316 widgets addition failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = snd_soc_dapm_add_routes(&card->dapm, rt1316_map, 2);
-	if (ret)
-		dev_err(rtd->dev, "failed to add first SPK map: %d\n", ret);
-
-	return ret;
-}
-
-static int second_spk_init(struct snd_soc_pcm_runtime *rtd)
-{
-	struct snd_soc_card *card = rtd->card;
-	int ret;
-
-	ret = snd_soc_dapm_add_routes(&card->dapm, rt1316_map + 2, 2);
-	if (ret)
-		dev_err(rtd->dev, "failed to add second SPK map: %d\n", ret);
-
-	return ret;
-}
-
-static int all_spk_init(struct snd_soc_pcm_runtime *rtd)
-{
-	int ret;
-
-	ret = first_spk_init(rtd);
-	if (ret)
-		return ret;
-
-	return second_spk_init(rtd);
-}
-
-int sof_sdw_rt1316_exit(struct snd_soc_card *card, struct snd_soc_dai_link *dai_link)
-{
-	struct mc_private *ctx = snd_soc_card_get_drvdata(card);
-
-	if (ctx->amp_dev1) {
-		device_remove_software_node(ctx->amp_dev1);
-		put_device(ctx->amp_dev1);
-	}
-
-	if (ctx->amp_dev2) {
-		device_remove_software_node(ctx->amp_dev2);
-		put_device(ctx->amp_dev2);
-	}
-
-	return 0;
-}
-
-int sof_sdw_rt1316_init(struct snd_soc_card *card,
-			const struct snd_soc_acpi_link_adr *link,
-			struct snd_soc_dai_link *dai_links,
-			struct sof_sdw_codec_info *info,
-			bool playback)
-{
-	struct mc_private *ctx = snd_soc_card_get_drvdata(card);
-	struct device *sdw_dev1, *sdw_dev2;
-	int ret;
-
-	/* Count amp number and do init on playback link only. */
-	if (!playback)
-		return 0;
-
-	info->amp_num++;
-	if (info->amp_num == 1)
-		dai_links->init = first_spk_init;
-
-	if (info->amp_num == 2) {
-		sdw_dev1 = bus_find_device_by_name(&sdw_bus_type, NULL, dai_links->codecs[0].name);
-		if (!sdw_dev1)
-			return -EPROBE_DEFER;
-
-		ret = rt1316_add_device_props(sdw_dev1);
-		if (ret < 0) {
-			put_device(sdw_dev1);
-			return ret;
-		}
-		ctx->amp_dev1 = sdw_dev1;
-
-		sdw_dev2 = bus_find_device_by_name(&sdw_bus_type, NULL, dai_links->codecs[1].name);
-		if (!sdw_dev2)
-			return -EPROBE_DEFER;
-
-		ret = rt1316_add_device_props(sdw_dev2);
-		if (ret < 0) {
-			put_device(sdw_dev2);
-			return ret;
-		}
-		ctx->amp_dev2 = sdw_dev2;
-
-		/*
-		 * if two 1316s are in one dai link, the init function
-		 * in this dai link will be first set for the first speaker,
-		 * and it should be reset to initialize all speakers when
-		 * the second speaker is found.
-		 */
-		if (dai_links->init)
-			dai_links->init = all_spk_init;
-		else
-			dai_links->init = second_spk_init;
-	}
-
-	return 0;
-}
diff --git a/sound/soc/intel/boards/sof_sdw_rt1318.c b/sound/soc/intel/boards/sof_sdw_rt1318.c
deleted file mode 100644
index dbee4bf5c8149..0000000000000
--- a/sound/soc/intel/boards/sof_sdw_rt1318.c
+++ /dev/null
@@ -1,120 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-// Copyright (c) 2022 Intel Corporation
-
-/*
- *  sof_sdw_rt1318 - Helpers to handle RT1318 from generic machine driver
- */
-
-#include <linux/device.h>
-#include <linux/errno.h>
-#include <sound/control.h>
-#include <sound/soc.h>
-#include <sound/soc-acpi.h>
-#include <sound/soc-dapm.h>
-#include "sof_sdw_common.h"
-
-static const struct snd_soc_dapm_widget rt1318_widgets[] = {
-	SND_SOC_DAPM_SPK("Speaker", NULL),
-};
-
-/*
- * dapm routes for rt1318 will be registered dynamically according
- * to the number of rt1318 used. The first two entries will be registered
- * for one codec case, and the last two entries are also registered
- * if two 1318s are used.
- */
-static const struct snd_soc_dapm_route rt1318_map[] = {
-	{ "Speaker", NULL, "rt1318-1 SPOL" },
-	{ "Speaker", NULL, "rt1318-1 SPOR" },
-	{ "Speaker", NULL, "rt1318-2 SPOL" },
-	{ "Speaker", NULL, "rt1318-2 SPOR" },
-};
-
-static const struct snd_kcontrol_new rt1318_controls[] = {
-	SOC_DAPM_PIN_SWITCH("Speaker"),
-};
-
-static int first_spk_init(struct snd_soc_pcm_runtime *rtd)
-{
-	struct snd_soc_card *card = rtd->card;
-	int ret;
-
-	card->components = devm_kasprintf(card->dev, GFP_KERNEL,
-					  "%s spk:rt1318",
-					  card->components);
-	if (!card->components)
-		return -ENOMEM;
-
-	ret = snd_soc_add_card_controls(card, rt1318_controls,
-					ARRAY_SIZE(rt1318_controls));
-	if (ret) {
-		dev_err(card->dev, "rt1318 controls addition failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = snd_soc_dapm_new_controls(&card->dapm, rt1318_widgets,
-					ARRAY_SIZE(rt1318_widgets));
-	if (ret) {
-		dev_err(card->dev, "rt1318 widgets addition failed: %d\n", ret);
-		return ret;
-	}
-
-	ret = snd_soc_dapm_add_routes(&card->dapm, rt1318_map, 2);
-	if (ret)
-		dev_err(rtd->dev, "failed to add first SPK map: %d\n", ret);
-
-	return ret;
-}
-
-static int second_spk_init(struct snd_soc_pcm_runtime *rtd)
-{
-	struct snd_soc_card *card = rtd->card;
-	int ret;
-
-	ret = snd_soc_dapm_add_routes(&card->dapm, rt1318_map + 2, 2);
-	if (ret)
-		dev_err(rtd->dev, "failed to add second SPK map: %d\n", ret);
-
-	return ret;
-}
-
-static int all_spk_init(struct snd_soc_pcm_runtime *rtd)
-{
-	int ret;
-
-	ret = first_spk_init(rtd);
-	if (ret)
-		return ret;
-
-	return second_spk_init(rtd);
-}
-
-int sof_sdw_rt1318_init(struct snd_soc_card *card,
-			const struct snd_soc_acpi_link_adr *link,
-			struct snd_soc_dai_link *dai_links,
-			struct sof_sdw_codec_info *info,
-			bool playback)
-{
-	/* Count amp number and do init on playback link only. */
-	if (!playback)
-		return 0;
-
-	info->amp_num++;
-	if (info->amp_num == 1)
-		dai_links->init = first_spk_init;
-
-	if (info->amp_num == 2) {
-		/*
-		 * if two 1318s are in one dai link, the init function
-		 * in this dai link will be first set for the first speaker,
-		 * and it should be reset to initialize all speakers when
-		 * the second speaker is found.
-		 */
-		if (dai_links->init)
-			dai_links->init = all_spk_init;
-		else
-			dai_links->init = second_spk_init;
-	}
-
-	return 0;
-}
diff --git a/sound/soc/intel/boards/sof_sdw_rt1308.c b/sound/soc/intel/boards/sof_sdw_rt_amp.c
similarity index 59%
rename from sound/soc/intel/boards/sof_sdw_rt1308.c
rename to sound/soc/intel/boards/sof_sdw_rt_amp.c
index a19b055b9c6f8..26bf9e0dd3d24 100644
--- a/sound/soc/intel/boards/sof_sdw_rt1308.c
+++ b/sound/soc/intel/boards/sof_sdw_rt_amp.c
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// Copyright (c) 2020 Intel Corporation
+// Copyright (c) 2022 Intel Corporation
 
 /*
- *  sof_sdw_rt1308 - Helpers to handle RT1308 from generic machine driver
+ *  sof_sdw_rt_amp - Helpers to handle RT1308/RT1316/RT1318 from generic machine driver
  */
 
 #include <linux/device.h>
@@ -18,16 +18,26 @@
 #include "sof_sdw_amp_coeff_tables.h"
 #include "../../codecs/rt1308.h"
 
-struct rt1308_platform_data {
+#define CODEC_NAME_SIZE	7
+
+/* choose a larger value to resolve compatibility issues */
+#define RT_AMP_MAX_BQ_REG RT1316_MAX_BQ_REG
+
+struct rt_amp_platform_data {
 	const unsigned char *bq_params;
 	const unsigned int bq_params_cnt;
 };
 
-static const struct rt1308_platform_data dell_0a5d_platform_data = {
+static const struct rt_amp_platform_data dell_0a5d_platform_data = {
 	.bq_params = dell_0a5d_bq_params,
 	.bq_params_cnt = ARRAY_SIZE(dell_0a5d_bq_params),
 };
 
+static const struct rt_amp_platform_data dell_0b00_platform_data = {
+	.bq_params = dell_0b00_bq_params,
+	.bq_params_cnt = ARRAY_SIZE(dell_0b00_bq_params),
+};
+
 static const struct dmi_system_id dmi_platform_data[] = {
 	/* CometLake devices */
 	{
@@ -59,15 +69,45 @@ static const struct dmi_system_id dmi_platform_data[] = {
 		},
 		.driver_data = (void *)&dell_0a5d_platform_data,
 	},
+	/* AlderLake devices */
+	{
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
+			DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0B00")
+		},
+		.driver_data = (void *)&dell_0b00_platform_data,
+	},
+	{
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
+			DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0B01")
+		},
+		.driver_data = (void *)&dell_0b00_platform_data,
+	},
+	{
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
+			DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0AFF")
+		},
+		.driver_data = (void *)&dell_0b00_platform_data,
+	},
+	{
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
+			DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "0AFE")
+		},
+		.driver_data = (void *)&dell_0b00_platform_data,
+	},
+	{},
 };
 
-static int rt1308_add_device_props(struct device *sdw_dev)
+static int rt_amp_add_device_props(struct device *sdw_dev)
 {
 	struct property_entry props[3] = {};
 	struct fwnode_handle *fwnode;
 	const struct dmi_system_id *dmi_data;
-	const struct rt1308_platform_data *pdata;
-	unsigned char params[RT1308_MAX_BQ_REG];
+	const struct rt_amp_platform_data *pdata;
+	unsigned char params[RT_AMP_MAX_BQ_REG];
 	int ret;
 
 	dmi_data = dmi_first_match(dmi_platform_data);
@@ -91,15 +131,19 @@ static int rt1308_add_device_props(struct device *sdw_dev)
 	return ret;
 }
 
-static const struct snd_soc_dapm_widget rt1308_widgets[] = {
+static const struct snd_kcontrol_new rt_amp_controls[] = {
+	SOC_DAPM_PIN_SWITCH("Speaker"),
+};
+
+static const struct snd_soc_dapm_widget rt_amp_widgets[] = {
 	SND_SOC_DAPM_SPK("Speaker", NULL),
 };
 
 /*
- * dapm routes for rt1308 will be registered dynamically according
- * to the number of rt1308 used. The first two entries will be registered
- * for one codec case, and the last two entries are also registered
- * if two 1308s are used.
+ * dapm routes for rt1308/rt1316/rt1318 will be registered dynamically
+ * according to the number of rt1308/rt1316/rt1318 used. The first two
+ * entries will be registered for one codec case, and the last two entries
+ * are also registered if two 1308s/1316s/1318s are used.
  */
 static const struct snd_soc_dapm_route rt1308_map[] = {
 	{ "Speaker", NULL, "rt1308-1 SPOL" },
@@ -108,36 +152,69 @@ static const struct snd_soc_dapm_route rt1308_map[] = {
 	{ "Speaker", NULL, "rt1308-2 SPOR" },
 };
 
-static const struct snd_kcontrol_new rt1308_controls[] = {
-	SOC_DAPM_PIN_SWITCH("Speaker"),
+static const struct snd_soc_dapm_route rt1316_map[] = {
+	{ "Speaker", NULL, "rt1316-1 SPOL" },
+	{ "Speaker", NULL, "rt1316-1 SPOR" },
+	{ "Speaker", NULL, "rt1316-2 SPOL" },
+	{ "Speaker", NULL, "rt1316-2 SPOR" },
 };
 
+static const struct snd_soc_dapm_route rt1318_map[] = {
+	{ "Speaker", NULL, "rt1318-1 SPOL" },
+	{ "Speaker", NULL, "rt1318-1 SPOR" },
+	{ "Speaker", NULL, "rt1318-2 SPOL" },
+	{ "Speaker", NULL, "rt1318-2 SPOR" },
+};
+
+static const struct snd_soc_dapm_route *get_codec_name_and_route(struct snd_soc_pcm_runtime *rtd,
+								 char *codec_name)
+{
+	const char *dai_name;
+
+	dai_name = rtd->dai_link->codecs->dai_name;
+
+	/* get the codec name */
+	snprintf(codec_name, CODEC_NAME_SIZE, "%s", dai_name);
+
+	/* choose the right codec's map  */
+	if (strcmp(codec_name, "rt1308") == 0)
+		return rt1308_map;
+	else if (strcmp(codec_name, "rt1316") == 0)
+		return rt1316_map;
+	else
+		return rt1318_map;
+}
+
 static int first_spk_init(struct snd_soc_pcm_runtime *rtd)
 {
 	struct snd_soc_card *card = rtd->card;
+	const struct snd_soc_dapm_route *rt_amp_map;
+	char codec_name[CODEC_NAME_SIZE];
 	int ret;
 
+	rt_amp_map = get_codec_name_and_route(rtd, codec_name);
+
 	card->components = devm_kasprintf(card->dev, GFP_KERNEL,
-					  "%s spk:rt1308",
-					  card->components);
+					  "%s spk:%s",
+					  card->components, codec_name);
 	if (!card->components)
 		return -ENOMEM;
 
-	ret = snd_soc_add_card_controls(card, rt1308_controls,
-					ARRAY_SIZE(rt1308_controls));
+	ret = snd_soc_add_card_controls(card, rt_amp_controls,
+					ARRAY_SIZE(rt_amp_controls));
 	if (ret) {
-		dev_err(card->dev, "rt1308 controls addition failed: %d\n", ret);
+		dev_err(card->dev, "%s controls addition failed: %d\n", codec_name, ret);
 		return ret;
 	}
 
-	ret = snd_soc_dapm_new_controls(&card->dapm, rt1308_widgets,
-					ARRAY_SIZE(rt1308_widgets));
+	ret = snd_soc_dapm_new_controls(&card->dapm, rt_amp_widgets,
+					ARRAY_SIZE(rt_amp_widgets));
 	if (ret) {
-		dev_err(card->dev, "rt1308 widgets addition failed: %d\n", ret);
+		dev_err(card->dev, "%s widgets addition failed: %d\n", codec_name, ret);
 		return ret;
 	}
 
-	ret = snd_soc_dapm_add_routes(&card->dapm, rt1308_map, 2);
+	ret = snd_soc_dapm_add_routes(&card->dapm, rt_amp_map, 2);
 	if (ret)
 		dev_err(rtd->dev, "failed to add first SPK map: %d\n", ret);
 
@@ -147,9 +224,13 @@ static int first_spk_init(struct snd_soc_pcm_runtime *rtd)
 static int second_spk_init(struct snd_soc_pcm_runtime *rtd)
 {
 	struct snd_soc_card *card = rtd->card;
+	const struct snd_soc_dapm_route *rt_amp_map;
+	char codec_name[CODEC_NAME_SIZE];
 	int ret;
 
-	ret = snd_soc_dapm_add_routes(&card->dapm, rt1308_map + 2, 2);
+	rt_amp_map = get_codec_name_and_route(rtd, codec_name);
+
+	ret = snd_soc_dapm_add_routes(&card->dapm, rt_amp_map + 2, 2);
 	if (ret)
 		dev_err(rtd->dev, "failed to add second SPK map: %d\n", ret);
 
@@ -204,7 +285,7 @@ struct snd_soc_ops sof_sdw_rt1308_i2s_ops = {
 	.hw_params = rt1308_i2s_hw_params,
 };
 
-int sof_sdw_rt1308_exit(struct snd_soc_card *card, struct snd_soc_dai_link *dai_link)
+int sof_sdw_rt_amp_exit(struct snd_soc_card *card, struct snd_soc_dai_link *dai_link)
 {
 	struct mc_private *ctx = snd_soc_card_get_drvdata(card);
 
@@ -221,7 +302,7 @@ int sof_sdw_rt1308_exit(struct snd_soc_card *card, struct snd_soc_dai_link *dai_
 	return 0;
 }
 
-int sof_sdw_rt1308_init(struct snd_soc_card *card,
+int sof_sdw_rt_amp_init(struct snd_soc_card *card,
 			const struct snd_soc_acpi_link_adr *link,
 			struct snd_soc_dai_link *dai_links,
 			struct sof_sdw_codec_info *info,
@@ -244,7 +325,7 @@ int sof_sdw_rt1308_init(struct snd_soc_card *card,
 		if (!sdw_dev1)
 			return -EPROBE_DEFER;
 
-		ret = rt1308_add_device_props(sdw_dev1);
+		ret = rt_amp_add_device_props(sdw_dev1);
 		if (ret < 0) {
 			put_device(sdw_dev1);
 			return ret;
@@ -255,7 +336,7 @@ int sof_sdw_rt1308_init(struct snd_soc_card *card,
 		if (!sdw_dev2)
 			return -EPROBE_DEFER;
 
-		ret = rt1308_add_device_props(sdw_dev2);
+		ret = rt_amp_add_device_props(sdw_dev2);
 		if (ret < 0) {
 			put_device(sdw_dev2);
 			return ret;
@@ -263,7 +344,7 @@ int sof_sdw_rt1308_init(struct snd_soc_card *card,
 		ctx->amp_dev2 = sdw_dev2;
 
 		/*
-		 * if two 1308s are in one dai link, the init function
+		 * if two amps are in one dai link, the init function
 		 * in this dai link will be first set for the first speaker,
 		 * and it should be reset to initialize all speakers when
 		 * the second speaker is found.
-- 
GitLab


From 47d2b66fec133cb27da3a551334686e465d19469 Mon Sep 17 00:00:00 2001
From: Bard Liao <yung-chuan.liao@linux.intel.com>
Date: Tue, 6 Dec 2022 15:25:07 -0600
Subject: [PATCH 345/875] ASoC: Intel: sof_realtek_common: set ret = 0 as
 initial value

'ret' will not be initialized if dai_fmt is not DSP_A or DSP_B.

Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20221206212507.359993-4-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/boards/sof_realtek_common.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/sound/soc/intel/boards/sof_realtek_common.c b/sound/soc/intel/boards/sof_realtek_common.c
index ff2851fc8930a..6c12ca92f3713 100644
--- a/sound/soc/intel/boards/sof_realtek_common.c
+++ b/sound/soc/intel/boards/sof_realtek_common.c
@@ -267,7 +267,8 @@ static int rt1015_hw_params(struct snd_pcm_substream *substream,
 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
 	struct snd_soc_dai_link *dai_link = rtd->dai_link;
 	struct snd_soc_dai *codec_dai;
-	int i, clk_freq, ret;
+	int i, clk_freq;
+	int ret = 0;
 
 	clk_freq = sof_dai_get_bclk(rtd);
 
-- 
GitLab


From 3327d721114c109ba0575f86f8fda3b525404054 Mon Sep 17 00:00:00 2001
From: Wang Yufen <wangyufen@huawei.com>
Date: Mon, 5 Dec 2022 18:04:24 +0800
Subject: [PATCH 346/875] ASoC: mediatek: mt8173-rt5650-rt5514: fix refcount
 leak in mt8173_rt5650_rt5514_dev_probe()

The node returned by of_parse_phandle() with refcount incremented,
of_node_put() needs be called when finish using it. So add it in the
error path in mt8173_rt5650_rt5514_dev_probe().

Fixes: 0d1d7a664288 ("ASoC: mediatek: Refine mt8173 driver and change config option")
Signed-off-by: Wang Yufen <wangyufen@huawei.com>
Link: https://lore.kernel.org/r/1670234664-24246-1-git-send-email-wangyufen@huawei.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/mediatek/mt8173/mt8173-rt5650-rt5514.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/sound/soc/mediatek/mt8173/mt8173-rt5650-rt5514.c b/sound/soc/mediatek/mt8173/mt8173-rt5650-rt5514.c
index 12f40c81b101e..f803f121659de 100644
--- a/sound/soc/mediatek/mt8173/mt8173-rt5650-rt5514.c
+++ b/sound/soc/mediatek/mt8173/mt8173-rt5650-rt5514.c
@@ -200,14 +200,16 @@ static int mt8173_rt5650_rt5514_dev_probe(struct platform_device *pdev)
 	if (!mt8173_rt5650_rt5514_dais[DAI_LINK_CODEC_I2S].codecs[0].of_node) {
 		dev_err(&pdev->dev,
 			"Property 'audio-codec' missing or invalid\n");
-		return -EINVAL;
+		ret = -EINVAL;
+		goto out;
 	}
 	mt8173_rt5650_rt5514_dais[DAI_LINK_CODEC_I2S].codecs[1].of_node =
 		of_parse_phandle(pdev->dev.of_node, "mediatek,audio-codec", 1);
 	if (!mt8173_rt5650_rt5514_dais[DAI_LINK_CODEC_I2S].codecs[1].of_node) {
 		dev_err(&pdev->dev,
 			"Property 'audio-codec' missing or invalid\n");
-		return -EINVAL;
+		ret = -EINVAL;
+		goto out;
 	}
 	mt8173_rt5650_rt5514_codec_conf[0].dlc.of_node =
 		mt8173_rt5650_rt5514_dais[DAI_LINK_CODEC_I2S].codecs[1].of_node;
@@ -216,6 +218,7 @@ static int mt8173_rt5650_rt5514_dev_probe(struct platform_device *pdev)
 
 	ret = devm_snd_soc_register_card(&pdev->dev, card);
 
+out:
 	of_node_put(platform_node);
 	return ret;
 }
-- 
GitLab


From 8ab2d12c726f0fde0692fa5d81d8019b3dcd62d0 Mon Sep 17 00:00:00 2001
From: Wang Yufen <wangyufen@huawei.com>
Date: Mon, 5 Dec 2022 16:15:27 +0800
Subject: [PATCH 347/875] ASoC: audio-graph-card: fix refcount leak of cpu_ep
 in __graph_for_each_link()

The of_get_next_child() returns a node with refcount incremented, and
decrements the refcount of prev. So in the error path of the while loop,
of_node_put() needs be called for cpu_ep.

Fixes: fce9b90c1ab7 ("ASoC: audio-graph-card: cleanup DAI link loop method - step2")
Signed-off-by: Wang Yufen <wangyufen@huawei.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/1670228127-13835-1-git-send-email-wangyufen@huawei.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/generic/audio-graph-card.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/sound/soc/generic/audio-graph-card.c b/sound/soc/generic/audio-graph-card.c
index fe7cf972d44ce..5daa824a4ffcf 100644
--- a/sound/soc/generic/audio-graph-card.c
+++ b/sound/soc/generic/audio-graph-card.c
@@ -485,8 +485,10 @@ static int __graph_for_each_link(struct asoc_simple_priv *priv,
 			of_node_put(codec_ep);
 			of_node_put(codec_port);
 
-			if (ret < 0)
+			if (ret < 0) {
+				of_node_put(cpu_ep);
 				return ret;
+			}
 
 			codec_port_old = codec_port;
 		}
-- 
GitLab


From ef0a098efb36660326c133af9b5a04a96a00e3ca Mon Sep 17 00:00:00 2001
From: Wang Jingjin <wangjingjin1@huawei.com>
Date: Mon, 5 Dec 2022 11:28:02 +0800
Subject: [PATCH 348/875] ASoC: rockchip: pdm: Add missing
 clk_disable_unprepare() in rockchip_pdm_runtime_resume()

The clk_disable_unprepare() should be called in the error handling of
rockchip_pdm_runtime_resume().

Fixes: fc05a5b22253 ("ASoC: rockchip: add support for pdm controller")
Signed-off-by: Wang Jingjin <wangjingjin1@huawei.com>
Link: https://lore.kernel.org/r/20221205032802.2422983-1-wangjingjin1@huawei.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/rockchip/rockchip_pdm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/sound/soc/rockchip/rockchip_pdm.c b/sound/soc/rockchip/rockchip_pdm.c
index a7549f8272359..5b1e47bdc376b 100644
--- a/sound/soc/rockchip/rockchip_pdm.c
+++ b/sound/soc/rockchip/rockchip_pdm.c
@@ -431,6 +431,7 @@ static int rockchip_pdm_runtime_resume(struct device *dev)
 
 	ret = clk_prepare_enable(pdm->hclk);
 	if (ret) {
+		clk_disable_unprepare(pdm->clk);
 		dev_err(pdm->dev, "hclock enable failed %d\n", ret);
 		return ret;
 	}
-- 
GitLab


From a39bc7cf8e284653fb6fd9d897f269f4ac80cf52 Mon Sep 17 00:00:00 2001
From: ye xingchen <ye.xingchen@zte.com.cn>
Date: Mon, 5 Dec 2022 19:43:47 +0800
Subject: [PATCH 349/875] ASoC: imx-audmux: use sysfs_emit() to instead of
 scnprintf()

Follow the advice of the Documentation/filesystems/sysfs.rst and show()
should only use sysfs_emit() or sysfs_emit_at() when formatting the
value to be returned to user space.

Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
Link: https://lore.kernel.org/r/202212051943476482106@zte.com.cn
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/fsl/imx-audmux.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/sound/soc/fsl/imx-audmux.c b/sound/soc/fsl/imx-audmux.c
index 50b71e5d45897..582f1e2431eee 100644
--- a/sound/soc/fsl/imx-audmux.c
+++ b/sound/soc/fsl/imx-audmux.c
@@ -75,8 +75,7 @@ static ssize_t audmux_read_file(struct file *file, char __user *user_buf,
 	if (!buf)
 		return -ENOMEM;
 
-	ret = scnprintf(buf, PAGE_SIZE, "PDCR: %08x\nPTCR: %08x\n",
-		       pdcr, ptcr);
+	ret = sysfs_emit(buf, "PDCR: %08x\nPTCR: %08x\n", pdcr, ptcr);
 
 	if (ptcr & IMX_AUDMUX_V2_PTCR_TFSDIR)
 		ret += scnprintf(buf + ret, PAGE_SIZE - ret,
-- 
GitLab


From 38eef3be38ab895959c442702864212cc3beb96c Mon Sep 17 00:00:00 2001
From: Wang Yufen <wangyufen@huawei.com>
Date: Mon, 5 Dec 2022 17:56:28 +0800
Subject: [PATCH 350/875] ASoC: mediatek: mt8183: fix refcount leak in
 mt8183_mt6358_ts3a227_max98357_dev_probe()

The node returned by of_parse_phandle() with refcount incremented,
of_node_put() needs be called when finish using it. So add it in the
error path in mt8183_mt6358_ts3a227_max98357_dev_probe().

Fixes: 11c0269017b2 ("ASoC: Mediatek: MT8183: Add machine driver with TS3A227")
Signed-off-by: Wang Yufen <wangyufen@huawei.com>
Link: https://lore.kernel.org/r/1670234188-23596-1-git-send-email-wangyufen@huawei.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 .../mt8183/mt8183-mt6358-ts3a227-max98357.c        | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/sound/soc/mediatek/mt8183/mt8183-mt6358-ts3a227-max98357.c b/sound/soc/mediatek/mt8183/mt8183-mt6358-ts3a227-max98357.c
index 8fb473543cf9f..ce9aedde7e1ef 100644
--- a/sound/soc/mediatek/mt8183/mt8183-mt6358-ts3a227-max98357.c
+++ b/sound/soc/mediatek/mt8183/mt8183-mt6358-ts3a227-max98357.c
@@ -677,8 +677,10 @@ mt8183_mt6358_ts3a227_max98357_dev_probe(struct platform_device *pdev)
 	}
 
 	card = (struct snd_soc_card *)of_device_get_match_data(&pdev->dev);
-	if (!card)
+	if (!card) {
+		of_node_put(platform_node);
 		return -EINVAL;
+	}
 	card->dev = &pdev->dev;
 
 	ec_codec = of_parse_phandle(pdev->dev.of_node, "mediatek,ec-codec", 0);
@@ -767,8 +769,10 @@ mt8183_mt6358_ts3a227_max98357_dev_probe(struct platform_device *pdev)
 	}
 
 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
-	if (!priv)
-		return -ENOMEM;
+	if (!priv) {
+		ret = -ENOMEM;
+		goto out;
+	}
 
 	snd_soc_card_set_drvdata(card, priv);
 
@@ -776,7 +780,8 @@ mt8183_mt6358_ts3a227_max98357_dev_probe(struct platform_device *pdev)
 	if (IS_ERR(priv->pinctrl)) {
 		dev_err(&pdev->dev, "%s devm_pinctrl_get failed\n",
 			__func__);
-		return PTR_ERR(priv->pinctrl);
+		ret = PTR_ERR(priv->pinctrl);
+		goto out;
 	}
 
 	for (i = 0; i < PIN_STATE_MAX; i++) {
@@ -809,6 +814,7 @@ mt8183_mt6358_ts3a227_max98357_dev_probe(struct platform_device *pdev)
 
 	ret = devm_snd_soc_register_card(&pdev->dev, card);
 
+out:
 	of_node_put(platform_node);
 	of_node_put(ec_codec);
 	of_node_put(hdmi_codec);
-- 
GitLab


From 81ed7d9de18768fe0cb3d74a7a163a8c082e1346 Mon Sep 17 00:00:00 2001
From: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
Date: Mon, 5 Dec 2022 15:35:07 +0800
Subject: [PATCH 351/875] ASoC: codecs: wcd-clsh: Remove the unused function

The function wcd_clsh_set_buck_mode() is defined in the wcd-clsh-v2.c
file, but not called elsewhere, so remove this unused function.

sound/soc/codecs/wcd-clsh-v2.c:133:20: warning: unused function 'wcd_clsh_enable_status'.

Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=3348
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
Link: https://lore.kernel.org/r/20221205073507.36071-1-jiapeng.chong@linux.alibaba.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/codecs/wcd-clsh-v2.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/sound/soc/codecs/wcd-clsh-v2.c b/sound/soc/codecs/wcd-clsh-v2.c
index 4c7ebc7fb4001..a75db27e52055 100644
--- a/sound/soc/codecs/wcd-clsh-v2.c
+++ b/sound/soc/codecs/wcd-clsh-v2.c
@@ -130,12 +130,6 @@ static inline void wcd_enable_clsh_block(struct wcd_clsh_ctrl *ctrl,
 		ctrl->clsh_users = 0;
 }
 
-static inline bool wcd_clsh_enable_status(struct snd_soc_component *comp)
-{
-	return snd_soc_component_read(comp, WCD9XXX_A_CDC_CLSH_CRC) &
-					WCD9XXX_A_CDC_CLSH_CRC_CLK_EN_MASK;
-}
-
 static inline void wcd_clsh_set_buck_mode(struct snd_soc_component *comp,
 					  int mode)
 {
-- 
GitLab


From 11c7f9e3131ad14b27a957496088fa488b153a48 Mon Sep 17 00:00:00 2001
From: Maria Yu <quic_aiquny@quicinc.com>
Date: Tue, 6 Dec 2022 09:59:57 +0800
Subject: [PATCH 352/875] remoteproc: core: Do pm_relax when in RPROC_OFFLINE
 state

Make sure that pm_relax() happens even when the remoteproc
is stopped before the crash handler work is scheduled.

Signed-off-by: Maria Yu <quic_aiquny@quicinc.com>
Cc: stable <stable@vger.kernel.org>
Fixes: a781e5aa5911 ("remoteproc: core: Prevent system suspend during remoteproc recovery")
Link: https://lore.kernel.org/r/20221206015957.2616-2-quic_aiquny@quicinc.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/remoteproc/remoteproc_core.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
index 11c165ddf1fca..1cd4815a6dd19 100644
--- a/drivers/remoteproc/remoteproc_core.c
+++ b/drivers/remoteproc/remoteproc_core.c
@@ -1868,12 +1868,18 @@ static void rproc_crash_handler_work(struct work_struct *work)
 
 	mutex_lock(&rproc->lock);
 
-	if (rproc->state == RPROC_CRASHED || rproc->state == RPROC_OFFLINE) {
+	if (rproc->state == RPROC_CRASHED) {
 		/* handle only the first crash detected */
 		mutex_unlock(&rproc->lock);
 		return;
 	}
 
+	if (rproc->state == RPROC_OFFLINE) {
+		/* Don't recover if the remote processor was stopped */
+		mutex_unlock(&rproc->lock);
+		goto out;
+	}
+
 	rproc->state = RPROC_CRASHED;
 	dev_err(dev, "handling crash #%u in %s\n", ++rproc->crash_cnt,
 		rproc->name);
@@ -1883,6 +1889,7 @@ static void rproc_crash_handler_work(struct work_struct *work)
 	if (!rproc->recovery_disabled)
 		rproc_trigger_recovery(rproc);
 
+out:
 	pm_relax(rproc->dev.parent);
 }
 
-- 
GitLab


From 1da681e52853f0abfbfff8c69833d31e538ff9c0 Mon Sep 17 00:00:00 2001
From: Chancel Liu <chancel.liu@nxp.com>
Date: Mon, 28 Nov 2022 14:09:50 +0800
Subject: [PATCH 353/875] ASoC: soc-pcm.c: Clear DAIs parameters after
 stream_active is updated

DAIs parameters should be cleared if there's no active stream. Before,
we implemented it in soc_pcm_hw_free() by detecting stream_active. If
the running stream is the last active stream, we're going to clear
parameters.

However it will cause DAIs parameters never be cleared if there're
more than one stream. For example, we have stream1 and stream2 about
to stop. stream2 executes soc_pcm_hw_free() before stream1 executes
soc_pcm_close(). At the moment, stream2 should clear DAIs parameters.
Since stream_active is not yet updated by stream1 in soc_pcm_close(),
stream2 will not clear DAIs parameters. In result both stream1 and
stream2 don't clear the parameters.

This patch moves DAIs parameters cleanup after stream_active is
updated.

Signed-off-by: Chancel Liu <chancel.liu@nxp.com>
Link: https://lore.kernel.org/r/20221128060950.3540845-1-chancel.liu@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/soc-pcm.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c
index a7810c78ffa18..579a44d81d9a3 100644
--- a/sound/soc/soc-pcm.c
+++ b/sound/soc/soc-pcm.c
@@ -709,8 +709,17 @@ static int soc_pcm_clean(struct snd_soc_pcm_runtime *rtd,
 
 	snd_soc_dpcm_mutex_assert_held(rtd);
 
-	if (!rollback)
+	if (!rollback) {
 		snd_soc_runtime_deactivate(rtd, substream->stream);
+		/* clear the corresponding DAIs parameters when going to be inactive */
+		for_each_rtd_dais(rtd, i, dai) {
+			if (snd_soc_dai_active(dai) == 0)
+				soc_pcm_set_dai_params(dai, NULL);
+
+			if (snd_soc_dai_stream_active(dai, substream->stream) == 0)
+				snd_soc_dai_digital_mute(dai, 1, substream->stream);
+		}
+	}
 
 	for_each_rtd_dais(rtd, i, dai)
 		snd_soc_dai_shutdown(dai, substream, rollback);
@@ -940,15 +949,6 @@ static int soc_pcm_hw_clean(struct snd_soc_pcm_runtime *rtd,
 
 	snd_soc_dpcm_mutex_assert_held(rtd);
 
-	/* clear the corresponding DAIs parameters when going to be inactive */
-	for_each_rtd_dais(rtd, i, dai) {
-		if (snd_soc_dai_active(dai) == 1)
-			soc_pcm_set_dai_params(dai, NULL);
-
-		if (snd_soc_dai_stream_active(dai, substream->stream) == 1)
-			snd_soc_dai_digital_mute(dai, 1, substream->stream);
-	}
-
 	/* run the stream event */
 	snd_soc_dapm_stream_stop(rtd, substream->stream);
 
-- 
GitLab


From e85b1f5a9769ac30f4d2f6fb1cdcd9570c38e0c1 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Thu, 8 Dec 2022 04:53:54 +0100
Subject: [PATCH 354/875] ASoC: dt-bindings: fsl-sai: Reinstate i.MX93 SAI
 compatible string

The ASoC: dt-bindings: fsl-sai: Fix mx6ul and mx7d compatible strings
dropped i.MX93 SAI compatible string, reinstate it.

Fixes: 81b6c043e7ba ("ASoC: dt-bindings: fsl-sai: Fix mx6ul and mx7d compatible strings")
Signed-off-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20221208035354.255438-1-marex@denx.de
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 Documentation/devicetree/bindings/sound/fsl,sai.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/sound/fsl,sai.yaml b/Documentation/devicetree/bindings/sound/fsl,sai.yaml
index 5b28d2d513277..7e56337d8edc1 100644
--- a/Documentation/devicetree/bindings/sound/fsl,sai.yaml
+++ b/Documentation/devicetree/bindings/sound/fsl,sai.yaml
@@ -38,6 +38,7 @@ properties:
               - fsl,imx8mq-sai
               - fsl,imx8qm-sai
               - fsl,imx8ulp-sai
+              - fsl,imx93-sai
               - fsl,vf610-sai
 
   reg:
-- 
GitLab


From 65f15e43d9c2e1c263617c9c21501f3b7d09728d Mon Sep 17 00:00:00 2001
From: Minghao Chi <chi.minghao@zte.com.cn>
Date: Thu, 17 Nov 2022 14:07:24 +0800
Subject: [PATCH 355/875] mfd: fsl-imx25-tsadc: Use
 devm_platform_get_and_ioremap_resource()

Convert platform_get_resource(), devm_ioremap_resource() to a single
call to devm_platform_get_and_ioremap_resource(), as this is exactly
what this function does.

Signed-off-by: Minghao Chi <chi.minghao@zte.com.cn>
Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/202211171407248212856@zte.com.cn
---
 drivers/mfd/fsl-imx25-tsadc.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/mfd/fsl-imx25-tsadc.c b/drivers/mfd/fsl-imx25-tsadc.c
index 823595bcc9b7c..089c2ce615b6d 100644
--- a/drivers/mfd/fsl-imx25-tsadc.c
+++ b/drivers/mfd/fsl-imx25-tsadc.c
@@ -137,7 +137,6 @@ static int mx25_tsadc_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct mx25_tsadc *tsadc;
-	struct resource *res;
 	int ret;
 	void __iomem *iomem;
 
@@ -145,8 +144,7 @@ static int mx25_tsadc_probe(struct platform_device *pdev)
 	if (!tsadc)
 		return -ENOMEM;
 
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	iomem = devm_ioremap_resource(dev, res);
+	iomem = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
 	if (IS_ERR(iomem))
 		return PTR_ERR(iomem);
 
-- 
GitLab


From 959ecba7f5b7a821fc3bf742223f58c489db4bee Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Mon, 21 Nov 2022 11:24:54 +0100
Subject: [PATCH 356/875] mfd: rohm-bd9576: Convert to i2c's .probe_new()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The probe function doesn't make use of the i2c_device_id * parameter so
it can be trivially converted.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Matti Vaittinen <mazziesaccount@gmail.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221121102454.15664-1-u.kleine-koenig@pengutronix.de
---
 drivers/mfd/rohm-bd9576.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/rohm-bd9576.c b/drivers/mfd/rohm-bd9576.c
index f37cd4f27aebf..c854ab5bcd808 100644
--- a/drivers/mfd/rohm-bd9576.c
+++ b/drivers/mfd/rohm-bd9576.c
@@ -88,8 +88,7 @@ static struct regmap_irq_chip bd9576_irq_chip = {
 	.irq_reg_stride = 1,
 };
 
-static int bd957x_i2c_probe(struct i2c_client *i2c,
-			     const struct i2c_device_id *id)
+static int bd957x_i2c_probe(struct i2c_client *i2c)
 {
 	int ret;
 	struct regmap *regmap;
@@ -180,7 +179,7 @@ static struct i2c_driver bd957x_drv = {
 		.name = "rohm-bd957x",
 		.of_match_table = bd957x_of_match,
 	},
-	.probe = &bd957x_i2c_probe,
+	.probe_new = &bd957x_i2c_probe,
 };
 module_i2c_driver(bd957x_drv);
 
-- 
GitLab


From f359c3e5794ce1897e95d95f5c3f804018077b52 Mon Sep 17 00:00:00 2001
From: Minghao Chi <chi.minghao@zte.com.cn>
Date: Tue, 22 Nov 2022 09:45:58 +0800
Subject: [PATCH 357/875] mfd: stm32-lptimer: Use
 devm_platform_get_and_ioremap_resource()

Convert platform_get_resource(), devm_ioremap_resource() to a single
call to devm_platform_get_and_ioremap_resource(), as this is exactly
what this function does.

Signed-off-by: Minghao Chi <chi.minghao@zte.com.cn>
Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/202211220945587336502@zte.com.cn
---
 drivers/mfd/stm32-lptimer.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/mfd/stm32-lptimer.c b/drivers/mfd/stm32-lptimer.c
index 746e51a17cc8e..fa322f4412c87 100644
--- a/drivers/mfd/stm32-lptimer.c
+++ b/drivers/mfd/stm32-lptimer.c
@@ -52,7 +52,6 @@ static int stm32_lptimer_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct stm32_lptimer *ddata;
-	struct resource *res;
 	void __iomem *mmio;
 	int ret;
 
@@ -60,8 +59,7 @@ static int stm32_lptimer_probe(struct platform_device *pdev)
 	if (!ddata)
 		return -ENOMEM;
 
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	mmio = devm_ioremap_resource(dev, res);
+	mmio = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
 	if (IS_ERR(mmio))
 		return PTR_ERR(mmio);
 
-- 
GitLab


From 36579aca877a62f67ecd77eb3edefc4c86292406 Mon Sep 17 00:00:00 2001
From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Date: Sun, 20 Nov 2022 18:19:01 +0100
Subject: [PATCH 358/875] mfd: qcom_rpm: Fix an error handling path in
 qcom_rpm_probe()

If an error occurs after the clk_prepare_enable() call, a corresponding
clk_disable_unprepare() should be called.

Simplify code and switch to devm_clk_get_enabled() to fix it.

Fixes: 3526403353c2 ("mfd: qcom_rpm: Handle message RAM clock")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/e39752476d02605b2be46cab7115f71255ce13a8.1668949256.git.christophe.jaillet@wanadoo.fr
---
 drivers/mfd/qcom_rpm.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/mfd/qcom_rpm.c b/drivers/mfd/qcom_rpm.c
index 71bc34b74bc9c..ea5eb94427c4d 100644
--- a/drivers/mfd/qcom_rpm.c
+++ b/drivers/mfd/qcom_rpm.c
@@ -547,7 +547,7 @@ static int qcom_rpm_probe(struct platform_device *pdev)
 	init_completion(&rpm->ack);
 
 	/* Enable message RAM clock */
-	rpm->ramclk = devm_clk_get(&pdev->dev, "ram");
+	rpm->ramclk = devm_clk_get_enabled(&pdev->dev, "ram");
 	if (IS_ERR(rpm->ramclk)) {
 		ret = PTR_ERR(rpm->ramclk);
 		if (ret == -EPROBE_DEFER)
@@ -558,7 +558,6 @@ static int qcom_rpm_probe(struct platform_device *pdev)
 		 */
 		rpm->ramclk = NULL;
 	}
-	clk_prepare_enable(rpm->ramclk); /* Accepts NULL */
 
 	irq_ack = platform_get_irq_byname(pdev, "ack");
 	if (irq_ack < 0)
@@ -681,7 +680,6 @@ static int qcom_rpm_remove(struct platform_device *pdev)
 	struct qcom_rpm *rpm = dev_get_drvdata(&pdev->dev);
 
 	of_platform_depopulate(&pdev->dev);
-	clk_disable_unprepare(rpm->ramclk);
 
 	return 0;
 }
-- 
GitLab


From e48dee96046246980d476714b3f6684d45f29c13 Mon Sep 17 00:00:00 2001
From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Date: Sun, 20 Nov 2022 14:01:43 +0100
Subject: [PATCH 359/875] mfd: qcom_rpm: Use devm_of_platform_populate() to
 simplify code

Use devm_of_platform_populate() instead of hand-writing it.
This simplifies the code.

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/fd997dc92b9cee219e9c55e22959a94f4bbf570b.1668949256.git.christophe.jaillet@wanadoo.fr
---
 drivers/mfd/qcom_rpm.c | 12 +-----------
 1 file changed, 1 insertion(+), 11 deletions(-)

diff --git a/drivers/mfd/qcom_rpm.c b/drivers/mfd/qcom_rpm.c
index ea5eb94427c4d..8fea0e511550a 100644
--- a/drivers/mfd/qcom_rpm.c
+++ b/drivers/mfd/qcom_rpm.c
@@ -672,21 +672,11 @@ static int qcom_rpm_probe(struct platform_device *pdev)
 	if (ret)
 		dev_warn(&pdev->dev, "failed to mark wakeup irq as wakeup\n");
 
-	return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
-}
-
-static int qcom_rpm_remove(struct platform_device *pdev)
-{
-	struct qcom_rpm *rpm = dev_get_drvdata(&pdev->dev);
-
-	of_platform_depopulate(&pdev->dev);
-
-	return 0;
+	return devm_of_platform_populate(&pdev->dev);
 }
 
 static struct platform_driver qcom_rpm_driver = {
 	.probe = qcom_rpm_probe,
-	.remove = qcom_rpm_remove,
 	.driver  = {
 		.name  = "qcom_rpm",
 		.of_match_table = qcom_rpm_of_match,
-- 
GitLab


From 7ef5c57758c4bbf8d5476c3fefcb585e150d116a Mon Sep 17 00:00:00 2001
From: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Date: Tue, 22 Nov 2022 10:58:31 +0100
Subject: [PATCH 360/875] dt-bindings: mfd: da9062: Move IRQ to optional
 properties

Move IRQ to optional properties, because the MFD DA9061/62
is usable without IRQ. This makes the chip usable for designs
that don't have the IRQ pin connected.

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221122095833.3957-2-cniedermaier@dh-electronics.com
---
 Documentation/devicetree/bindings/mfd/da9062.txt | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/da9062.txt b/Documentation/devicetree/bindings/mfd/da9062.txt
index bab0d0e66cb3c..fe580206e18d6 100644
--- a/Documentation/devicetree/bindings/mfd/da9062.txt
+++ b/Documentation/devicetree/bindings/mfd/da9062.txt
@@ -33,11 +33,6 @@ Required properties:
     "dlg,da9061" for DA9061
 - reg : Specifies the I2C slave address (this defaults to 0x58 but it can be
   modified to match the chip's OTP settings).
-- interrupts : IRQ line information.
-- interrupt-controller
-
-See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
-further information on IRQ bindings.
 
 Optional properties:
 
@@ -48,6 +43,12 @@ Optional properties:
 See Documentation/devicetree/bindings/gpio/gpio.txt for further information on
 GPIO bindings.
 
+- interrupts : IRQ line information.
+- interrupt-controller
+
+See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
+further information on IRQ bindings.
+
 Sub-nodes:
 
 - regulators : This node defines the settings for the LDOs and BUCKs.
-- 
GitLab


From 96836a35ffb3bcdf412d5753363daf5ee3e68548 Mon Sep 17 00:00:00 2001
From: Jean Delvare <jdelvare@suse.de>
Date: Tue, 22 Nov 2022 15:41:34 +0100
Subject: [PATCH 361/875] mfd: Drop obsolete dependencies on COMPILE_TEST
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Since commit 0166dc11be91 ("of: make CONFIG_OF user selectable"), it
is possible to test-build any driver which depends on OF on any
architecture by explicitly selecting OF. Therefore depending on
COMPILE_TEST as an alternative is no longer needed.

It is actually better to always build such drivers with OF enabled,
so that the test builds are closer to how each driver will actually be
built on its intended target. Building them without OF may not test
much as the compiler will optimize out potentially large parts of the
code. In the worst case, this could even pop false positive warnings.
Dropping COMPILE_TEST here improves the quality of our testing and
avoids wasting time on non-existent issues.

As a minor optimization, this also lets us drop of_match_ptr(), as we
now know what it will resolve to, we might as well save cpp some work.

Signed-off-by: Jean Delvare <jdelvare@suse.de>
Cc: Lee Jones <lee@kernel.org>
Cc: Bartosz Golaszewski <brgl@bgdev.pl>
Cc: Chanwoo Choi <cw00.choi@samsung.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Cc: Luca Ceresoli <luca.ceresoli@bootlin.com>
Cc: "Jonathan Neuschäfer" <j.neuschaefer@gmx.net>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221122154134.58a7a18b@endymion.delvare
---
 drivers/mfd/Kconfig          | 16 ++++++++--------
 drivers/mfd/motorola-cpcap.c |  2 +-
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 2d563277105ca..30db49f318668 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -797,7 +797,7 @@ config MFD_MAX14577
 config MFD_MAX77620
 	bool "Maxim Semiconductor MAX77620 and MAX20024 PMIC Support"
 	depends on I2C=y
-	depends on OF || COMPILE_TEST
+	depends on OF
 	select MFD_CORE
 	select REGMAP_I2C
 	select REGMAP_IRQ
@@ -812,7 +812,7 @@ config MFD_MAX77620
 config MFD_MAX77650
 	tristate "Maxim MAX77650/77651 PMIC Support"
 	depends on I2C
-	depends on OF || COMPILE_TEST
+	depends on OF
 	select MFD_CORE
 	select REGMAP_I2C
 	select REGMAP_IRQ
@@ -827,7 +827,7 @@ config MFD_MAX77650
 config MFD_MAX77686
 	tristate "Maxim Semiconductor MAX77686/802 PMIC Support"
 	depends on I2C
-	depends on OF || COMPILE_TEST
+	depends on OF
 	select MFD_CORE
 	select REGMAP_I2C
 	select REGMAP_IRQ
@@ -856,7 +856,7 @@ config MFD_MAX77693
 config MFD_MAX77714
 	tristate "Maxim Semiconductor MAX77714 PMIC Support"
 	depends on I2C
-	depends on OF || COMPILE_TEST
+	depends on OF
 	select MFD_CORE
 	select REGMAP_I2C
 	help
@@ -1013,7 +1013,7 @@ config EZX_PCAP
 config MFD_CPCAP
 	tristate "Support for Motorola CPCAP"
 	depends on SPI
-	depends on OF || COMPILE_TEST
+	depends on OF
 	select MFD_CORE
 	select REGMAP_SPI
 	select REGMAP_IRQ
@@ -1038,7 +1038,7 @@ config MFD_VIPERBOARD
 
 config MFD_NTXEC
 	tristate "Netronix embedded controller (EC)"
-	depends on OF || COMPILE_TEST
+	depends on OF
 	depends on I2C
 	select REGMAP_I2C
 	select MFD_CORE
@@ -1234,7 +1234,7 @@ config MFD_RN5T618
 config MFD_SEC_CORE
 	tristate "Samsung Electronics PMIC Series Support"
 	depends on I2C=y
-	depends on OF || COMPILE_TEST
+	depends on OF
 	select MFD_CORE
 	select REGMAP_I2C
 	select REGMAP_IRQ
@@ -2082,7 +2082,7 @@ config MFD_STPMIC1
 config MFD_STMFX
 	tristate "Support for STMicroelectronics Multi-Function eXpander (STMFX)"
 	depends on I2C
-	depends on OF || COMPILE_TEST
+	depends on OF
 	select MFD_CORE
 	select REGMAP_I2C
 	help
diff --git a/drivers/mfd/motorola-cpcap.c b/drivers/mfd/motorola-cpcap.c
index ae8930eff72d5..a19691ba8d8b0 100644
--- a/drivers/mfd/motorola-cpcap.c
+++ b/drivers/mfd/motorola-cpcap.c
@@ -294,7 +294,7 @@ static int cpcap_probe(struct spi_device *spi)
 	struct cpcap_ddata *cpcap;
 	int ret;
 
-	match = of_match_device(of_match_ptr(cpcap_of_match), &spi->dev);
+	match = of_match_device(cpcap_of_match, &spi->dev);
 	if (!match)
 		return -ENODEV;
 
-- 
GitLab


From cb83cb0dfa821b9c91cc9b2e3473f0ea42e11461 Mon Sep 17 00:00:00 2001
From: Matti Vaittinen <mazziesaccount@gmail.com>
Date: Wed, 23 Nov 2022 11:19:49 +0200
Subject: [PATCH 362/875] mfd: rohm: Use dev_err_probe()

The dev_err_probe() has (at least) following benefits over dev_err()
when printing an error print for a failed function call at a device
driver probe:
	- Omit error level print if error is 'EPRBE_DEFER'
	- Standardized print format for returned error
	- return the error value allowing shortening calls like:

	if (ret) {
		dev_err(...);
		return ret;
	}

	to

	if (ret)
		return dev_err_probe(...);

Convert the ROHM BD71828, ROHM BD718x7 and ROHM BD9576 core drivers to
use the dev_err_probe() when returned error is not hard-coded constant.

Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/Y33lte0PKd2u6dyR@fedora
---
 drivers/mfd/rohm-bd71828.c | 23 ++++++++++-------------
 drivers/mfd/rohm-bd718x7.c | 21 ++++++++-------------
 drivers/mfd/rohm-bd9576.c  | 17 ++++++++---------
 3 files changed, 26 insertions(+), 35 deletions(-)

diff --git a/drivers/mfd/rohm-bd71828.c b/drivers/mfd/rohm-bd71828.c
index 3c5c6c3936509..7eb920633ee96 100644
--- a/drivers/mfd/rohm-bd71828.c
+++ b/drivers/mfd/rohm-bd71828.c
@@ -513,27 +513,24 @@ static int bd71828_i2c_probe(struct i2c_client *i2c)
 	}
 
 	regmap = devm_regmap_init_i2c(i2c, regmap_config);
-	if (IS_ERR(regmap)) {
-		dev_err(&i2c->dev, "Failed to initialize Regmap\n");
-		return PTR_ERR(regmap);
-	}
+	if (IS_ERR(regmap))
+		return dev_err_probe(&i2c->dev, PTR_ERR(regmap),
+				     "Failed to initialize Regmap\n");
 
 	ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, i2c->irq,
 				       IRQF_ONESHOT, 0, irqchip, &irq_data);
-	if (ret) {
-		dev_err(&i2c->dev, "Failed to add IRQ chip\n");
-		return ret;
-	}
+	if (ret)
+		return dev_err_probe(&i2c->dev, ret,
+				     "Failed to add IRQ chip\n");
 
 	dev_dbg(&i2c->dev, "Registered %d IRQs for chip\n",
 		irqchip->num_irqs);
 
 	if (button_irq) {
 		ret = regmap_irq_get_virq(irq_data, button_irq);
-		if (ret < 0) {
-			dev_err(&i2c->dev, "Failed to get the power-key IRQ\n");
-			return ret;
-		}
+		if (ret < 0)
+			return dev_err_probe(&i2c->dev, ret,
+					     "Failed to get the power-key IRQ\n");
 
 		button.irq = ret;
 	}
@@ -545,7 +542,7 @@ static int bd71828_i2c_probe(struct i2c_client *i2c)
 	ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, mfd, cells,
 				   NULL, 0, regmap_irq_get_domain(irq_data));
 	if (ret)
-		dev_err(&i2c->dev, "Failed to create subdevices\n");
+		dev_err_probe(&i2c->dev, ret, "Failed to create subdevices\n");
 
 	return ret;
 }
diff --git a/drivers/mfd/rohm-bd718x7.c b/drivers/mfd/rohm-bd718x7.c
index b55674d7b7dc2..378eb1a692e41 100644
--- a/drivers/mfd/rohm-bd718x7.c
+++ b/drivers/mfd/rohm-bd718x7.c
@@ -156,18 +156,15 @@ static int bd718xx_i2c_probe(struct i2c_client *i2c)
 	}
 
 	regmap = devm_regmap_init_i2c(i2c, &bd718xx_regmap_config);
-	if (IS_ERR(regmap)) {
-		dev_err(&i2c->dev, "regmap initialization failed\n");
-		return PTR_ERR(regmap);
-	}
+	if (IS_ERR(regmap))
+		return dev_err_probe(&i2c->dev, PTR_ERR(regmap),
+				     "regmap initialization failed\n");
 
 	ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, i2c->irq,
 				       IRQF_ONESHOT, 0, &bd718xx_irq_chip,
 				       &irq_data);
-	if (ret) {
-		dev_err(&i2c->dev, "Failed to add irq_chip\n");
-		return ret;
-	}
+	if (ret)
+		return dev_err_probe(&i2c->dev, ret, "Failed to add irq_chip\n");
 
 	ret = bd718xx_init_press_duration(regmap, &i2c->dev);
 	if (ret)
@@ -175,10 +172,8 @@ static int bd718xx_i2c_probe(struct i2c_client *i2c)
 
 	ret = regmap_irq_get_virq(irq_data, BD718XX_INT_PWRBTN_S);
 
-	if (ret < 0) {
-		dev_err(&i2c->dev, "Failed to get the IRQ\n");
-		return ret;
-	}
+	if (ret < 0)
+		return dev_err_probe(&i2c->dev, ret, "Failed to get the IRQ\n");
 
 	button.irq = ret;
 
@@ -186,7 +181,7 @@ static int bd718xx_i2c_probe(struct i2c_client *i2c)
 				   mfd, cells, NULL, 0,
 				   regmap_irq_get_domain(irq_data));
 	if (ret)
-		dev_err(&i2c->dev, "Failed to create subdevices\n");
+		dev_err_probe(&i2c->dev, ret, "Failed to create subdevices\n");
 
 	return ret;
 }
diff --git a/drivers/mfd/rohm-bd9576.c b/drivers/mfd/rohm-bd9576.c
index c854ab5bcd808..6491e385d980c 100644
--- a/drivers/mfd/rohm-bd9576.c
+++ b/drivers/mfd/rohm-bd9576.c
@@ -121,10 +121,9 @@ static int bd957x_i2c_probe(struct i2c_client *i2c)
 	}
 
 	regmap = devm_regmap_init_i2c(i2c, &bd957x_regmap);
-	if (IS_ERR(regmap)) {
-		dev_err(&i2c->dev, "Failed to initialize Regmap\n");
-		return PTR_ERR(regmap);
-	}
+	if (IS_ERR(regmap))
+		return dev_err_probe(&i2c->dev, PTR_ERR(regmap),
+				     "Failed to initialize Regmap\n");
 
 	/*
 	 * BD9576 behaves badly. It kepts IRQ line asserted for the whole
@@ -145,10 +144,10 @@ static int bd957x_i2c_probe(struct i2c_client *i2c)
 		ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, i2c->irq,
 					       IRQF_ONESHOT, 0,
 					       &bd9576_irq_chip, &irq_data);
-		if (ret) {
-			dev_err(&i2c->dev, "Failed to add IRQ chip\n");
-			return ret;
-		}
+		if (ret)
+			return dev_err_probe(&i2c->dev, ret,
+					     "Failed to add IRQ chip\n");
+
 		domain = regmap_irq_get_domain(irq_data);
 	} else {
 		ret = regmap_update_bits(regmap, BD957X_REG_INT_MAIN_MASK,
@@ -162,7 +161,7 @@ static int bd957x_i2c_probe(struct i2c_client *i2c)
 	ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, cells,
 				   num_cells, NULL, 0, domain);
 	if (ret)
-		dev_err(&i2c->dev, "Failed to create subdevices\n");
+		dev_err_probe(&i2c->dev, ret, "Failed to create subdevices\n");
 
 	return ret;
 }
-- 
GitLab


From 14f8c55d48e02157519fbcb3a5de557abd8a06e2 Mon Sep 17 00:00:00 2001
From: Yang Yingliang <yangyingliang@huawei.com>
Date: Fri, 25 Nov 2022 15:36:26 +0800
Subject: [PATCH 363/875] mfd: pm8008: Fix return value check in pm8008_probe()

In case of error, the function devm_regmap_init_i2c() returns
ERR_PTR() and never returns NULL. The NULL test in the return
value check should be replaced with IS_ERR().

Fixes: 6b149f3310a4 ("mfd: pm8008: Add driver for QCOM PM8008 PMIC")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Guru Das Srinagesh <gurus@codeaurora.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221125073626.1868229-1-yangyingliang@huawei.com
---
 drivers/mfd/qcom-pm8008.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mfd/qcom-pm8008.c b/drivers/mfd/qcom-pm8008.c
index 4b8ff947762f2..9f3c4a01b4c1c 100644
--- a/drivers/mfd/qcom-pm8008.c
+++ b/drivers/mfd/qcom-pm8008.c
@@ -215,8 +215,8 @@ static int pm8008_probe(struct i2c_client *client)
 
 	dev = &client->dev;
 	regmap = devm_regmap_init_i2c(client, &qcom_mfd_regmap_cfg);
-	if (!regmap)
-		return -ENODEV;
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
 
 	i2c_set_clientdata(client, regmap);
 
-- 
GitLab


From 37fecbb80721c4e72ba3e43d4f07ba9ec15b68fd Mon Sep 17 00:00:00 2001
From: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Date: Wed, 30 Nov 2022 11:14:26 +0100
Subject: [PATCH 364/875] dt-bindings: mfd: da9062: Correct file name for
 watchdog

Replace the watchdog file name with the name currently in use.

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20221130101426.5318-1-cniedermaier@dh-electronics.com
---
 Documentation/devicetree/bindings/mfd/da9062.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mfd/da9062.txt b/Documentation/devicetree/bindings/mfd/da9062.txt
index fe580206e18d6..e4eedd3bd2332 100644
--- a/Documentation/devicetree/bindings/mfd/da9062.txt
+++ b/Documentation/devicetree/bindings/mfd/da9062.txt
@@ -86,7 +86,7 @@ Sub-nodes:
 
 - onkey : See ../input/da9062-onkey.txt
 
-- watchdog: See ../watchdog/da9062-watchdog.txt
+- watchdog: See ../watchdog/da9062-wdt.txt
 
 - thermal : See ../thermal/da9062-thermal.txt
 
-- 
GitLab


From 084ca216931ab9313e6fb862c2ec9ec5e0702cd5 Mon Sep 17 00:00:00 2001
From: Cezary Rojewski <cezary.rojewski@intel.com>
Date: Thu, 8 Dec 2022 15:26:35 +0100
Subject: [PATCH 365/875] ALSA: hda: Error out if invalid stream is being setup

Scenario when snd_hdac_stream_setup_periods() receives an instance of
struct hdac_stream with neither ->substream nor ->cstream initialized is
invalid.

Simultaneously addresses "uninitialized symbol 'dmab'" error reported by
Smatch.

Fixes: 3e9582267e3a ("ALSA: hda: Interrupt servicing and BDL setup for compress streams")
Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20221208142635.1514944-1-cezary.rojewski@intel.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/hda/hdac_stream.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/sound/hda/hdac_stream.c b/sound/hda/hdac_stream.c
index 8f625402505f8..547adbc22590e 100644
--- a/sound/hda/hdac_stream.c
+++ b/sound/hda/hdac_stream.c
@@ -500,6 +500,9 @@ int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
 		dmab = snd_pcm_get_dma_buf(substream);
 	} else if (cstream) {
 		dmab = snd_pcm_get_dma_buf(cstream);
+	} else {
+		WARN(1, "No substream or cstream assigned\n");
+		return -EINVAL;
 	}
 
 	/* reset BDL address */
-- 
GitLab


From ada261b690ecd5c2f55f0c51bdf11d852a4561a6 Mon Sep 17 00:00:00 2001
From: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Date: Fri, 9 Dec 2022 12:18:20 +0200
Subject: [PATCH 366/875] ALSA: hda/hdmi: fix i915 silent stream programming
 flow

The i915 display codec may not successfully transition to
normal audio streaming mode, if the stream id is programmed
while codec is actively transmitting data. This can happen
when silent stream is enabled in KAE mode.

Fix the issue by implementing a i915 specific programming
flow, where the silent streaming is temporarily stopped,
a small delay is applied to ensure display codec becomes
idle, and then proceed with reprogramming the stream ID.

Fixes: 15175a4f2bbb ("ALSA: hda/hdmi: add keep-alive support for ADL-P and DG2")
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/7353
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Tested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://lore.kernel.org/r/20221209101822.3893675-2-kai.vehmanen@linux.intel.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/pci/hda/patch_hdmi.c | 28 ++++++++++++++++++++++++++--
 1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
index 7a40ddfd695a1..48bb23745ed39 100644
--- a/sound/pci/hda/patch_hdmi.c
+++ b/sound/pci/hda/patch_hdmi.c
@@ -2879,9 +2879,33 @@ static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
 				 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
 				 int format)
 {
+	struct hdmi_spec *spec = codec->spec;
+	int pin_idx = pin_id_to_pin_index(codec, pin_nid, dev_id);
+	struct hdmi_spec_per_pin *per_pin;
+	int res;
+
+	if (pin_idx < 0)
+		per_pin = NULL;
+	else
+		per_pin = get_pin(spec, pin_idx);
+
 	haswell_verify_D0(codec, cvt_nid, pin_nid);
-	return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
-				 stream_tag, format);
+
+	if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) {
+		silent_stream_set_kae(codec, per_pin, false);
+		/* wait for pending transfers in codec to clear */
+		usleep_range(100, 200);
+	}
+
+	res = hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
+				stream_tag, format);
+
+	if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) {
+		usleep_range(100, 200);
+		silent_stream_set_kae(codec, per_pin, true);
+	}
+
+	return res;
 }
 
 /* pin_cvt_fixup ops override for HSW+ and VLV+ */
-- 
GitLab


From b17e7ea041d8b565063632501ca4597afd105102 Mon Sep 17 00:00:00 2001
From: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Date: Fri, 9 Dec 2022 12:18:21 +0200
Subject: [PATCH 367/875] ALSA: hda/hdmi: set default audio parameters for KAE
 silent-stream

If the stream-id is zero, the keep-alive (KAE) will only ensure clock is
generated, but no audio samples are sent over display link. This happens
before first real audio stream is played out to a newly connected
receiver.

Reuse the code in silent_stream_enable() to set up stream parameters
to sane defaults values, also when using the newer keep-alive flow.

Fixes: 15175a4f2bbb ("ALSA: hda/hdmi: add keep-alive support for ADL-P and DG2")
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Tested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://lore.kernel.org/r/20221209101822.3893675-3-kai.vehmanen@linux.intel.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/pci/hda/patch_hdmi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
index 48bb23745ed39..f8e6ff7f88209 100644
--- a/sound/pci/hda/patch_hdmi.c
+++ b/sound/pci/hda/patch_hdmi.c
@@ -1738,6 +1738,7 @@ static void silent_stream_enable(struct hda_codec *codec,
 
 	switch (spec->silent_stream_type) {
 	case SILENT_STREAM_KAE:
+		silent_stream_enable_i915(codec, per_pin);
 		silent_stream_set_kae(codec, per_pin, true);
 		break;
 	case SILENT_STREAM_I915:
-- 
GitLab


From ee0b089d660021792e4ab4dda191b097ce1e964f Mon Sep 17 00:00:00 2001
From: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Date: Fri, 9 Dec 2022 12:18:22 +0200
Subject: [PATCH 368/875] ALSA: hda/hdmi: fix stream-id config keep-alive for
 rt suspend

When the new style KAE keep-alive implementation is used on compatible
Intel hardware, the clocks are maintained when codec is in D3. The
generic code in hda_cleanup_all_streams() can however interfere with
generation of audio samples in this mode, by setting the stream and
channel ids to zero.

To get full benefit of the keepalive, set the new
no_stream_clean_at_suspend quirk bit on affected Intel hardware. When
this bit is set, stream cleanup is skipped in hda_call_codec_suspend().

Special handling is needed for the case when system goes to suspend. The
stream id programming can be lost in this case. This will also cause
codec->cvt_setups to be out of sync. Handle this by implementing custom
suspend/resume handlers. If keep-alive is active for any converter, set
the quirk flags no_stream_clean_at_suspend and forced_resume. Upon
resume, keepalive programming is restored if needed.

Fixes: 15175a4f2bbb ("ALSA: hda/hdmi: add keep-alive support for ADL-P and DG2")
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20221209101822.3893675-4-kai.vehmanen@linux.intel.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 include/sound/hda_codec.h  |  1 +
 sound/pci/hda/hda_codec.c  |  3 +-
 sound/pci/hda/patch_hdmi.c | 90 +++++++++++++++++++++++++++++++++++++-
 3 files changed, 92 insertions(+), 2 deletions(-)

diff --git a/include/sound/hda_codec.h b/include/sound/hda_codec.h
index 25ec8c181688d..eba23daf2c290 100644
--- a/include/sound/hda_codec.h
+++ b/include/sound/hda_codec.h
@@ -258,6 +258,7 @@ struct hda_codec {
 	unsigned int link_down_at_suspend:1; /* link down at runtime suspend */
 	unsigned int relaxed_resume:1;	/* don't resume forcibly for jack */
 	unsigned int forced_resume:1; /* forced resume for jack */
+	unsigned int no_stream_clean_at_suspend:1; /* do not clean streams at suspend */
 
 #ifdef CONFIG_PM
 	unsigned long power_on_acct;
diff --git a/sound/pci/hda/hda_codec.c b/sound/pci/hda/hda_codec.c
index b4d1e658c5560..edd653ece70d7 100644
--- a/sound/pci/hda/hda_codec.c
+++ b/sound/pci/hda/hda_codec.c
@@ -2886,7 +2886,8 @@ static unsigned int hda_call_codec_suspend(struct hda_codec *codec)
 	snd_hdac_enter_pm(&codec->core);
 	if (codec->patch_ops.suspend)
 		codec->patch_ops.suspend(codec);
-	hda_cleanup_all_streams(codec);
+	if (!codec->no_stream_clean_at_suspend)
+		hda_cleanup_all_streams(codec);
 	state = hda_set_power_state(codec, AC_PWRST_D3);
 	update_power_acct(codec, true);
 	snd_hdac_leave_pm(&codec->core);
diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
index f8e6ff7f88209..8015e44712678 100644
--- a/sound/pci/hda/patch_hdmi.c
+++ b/sound/pci/hda/patch_hdmi.c
@@ -2926,6 +2926,88 @@ static void i915_pin_cvt_fixup(struct hda_codec *codec,
 	}
 }
 
+#ifdef CONFIG_PM
+static int i915_adlp_hdmi_suspend(struct hda_codec *codec)
+{
+	struct hdmi_spec *spec = codec->spec;
+	bool silent_streams = false;
+	int pin_idx, res;
+
+	res = generic_hdmi_suspend(codec);
+
+	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
+		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
+
+		if (per_pin->silent_stream) {
+			silent_streams = true;
+			break;
+		}
+	}
+
+	if (silent_streams && spec->silent_stream_type == SILENT_STREAM_KAE) {
+		/*
+		 * stream-id should remain programmed when codec goes
+		 * to runtime suspend
+		 */
+		codec->no_stream_clean_at_suspend = 1;
+
+		/*
+		 * the system might go to S3, in which case keep-alive
+		 * must be reprogrammed upon resume
+		 */
+		codec->forced_resume = 1;
+
+		codec_dbg(codec, "HDMI: KAE active at suspend\n");
+	} else {
+		codec->no_stream_clean_at_suspend = 0;
+		codec->forced_resume = 0;
+	}
+
+	return res;
+}
+
+static int i915_adlp_hdmi_resume(struct hda_codec *codec)
+{
+	struct hdmi_spec *spec = codec->spec;
+	int pin_idx, res;
+
+	res = generic_hdmi_resume(codec);
+
+	/* KAE not programmed at suspend, nothing to do here */
+	if (!codec->no_stream_clean_at_suspend)
+		return res;
+
+	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
+		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
+
+		/*
+		 * If system was in suspend with monitor connected,
+		 * the codec setting may have been lost. Re-enable
+		 * keep-alive.
+		 */
+		if (per_pin->silent_stream) {
+			unsigned int param;
+
+			param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0,
+						   AC_VERB_GET_CONV, 0);
+			if (!param) {
+				codec_dbg(codec, "HDMI: KAE: restore stream id\n");
+				silent_stream_enable_i915(codec, per_pin);
+			}
+
+			param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0,
+						   AC_VERB_GET_DIGI_CONVERT_1, 0);
+			if (!(param & (AC_DIG3_KAE << 16))) {
+				codec_dbg(codec, "HDMI: KAE: restore DIG3_KAE\n");
+				silent_stream_set_kae(codec, per_pin, true);
+			}
+		}
+	}
+
+	return res;
+}
+#endif
+
 /* precondition and allocation for Intel codecs */
 static int alloc_intel_hdmi(struct hda_codec *codec)
 {
@@ -3056,8 +3138,14 @@ static int patch_i915_adlp_hdmi(struct hda_codec *codec)
 	if (!res) {
 		spec = codec->spec;
 
-		if (spec->silent_stream_type)
+		if (spec->silent_stream_type) {
 			spec->silent_stream_type = SILENT_STREAM_KAE;
+
+#ifdef CONFIG_PM
+			codec->patch_ops.resume = i915_adlp_hdmi_resume;
+			codec->patch_ops.suspend = i915_adlp_hdmi_suspend;
+#endif
+		}
 	}
 
 	return res;
-- 
GitLab


From 2c1da39008fee00596ed33baeacaffa0dc62df25 Mon Sep 17 00:00:00 2001
From: Matt Roper <matthew.d.roper@intel.com>
Date: Mon, 28 Nov 2022 15:30:10 -0800
Subject: [PATCH 369/875] drm/i915/gt: Correct kerneldoc for
 intel_gt_mcr_wait_for_reg()

The kerneldoc function name was not updated when this function was
converted to a non-fw form.

Fixes: 41f425adbce9 ("drm/i915/gt: Manage uncore->lock while waiting on MCR register")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221128233014.4000136-2-matthew.d.roper@intel.com
(cherry picked from commit 03b713d029bd17a1ed426590609af79843db95e2)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index d9a8ff9e5e578..ea86c1ab5dc56 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -702,7 +702,7 @@ void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss,
 }
 
 /**
- * intel_gt_mcr_wait_for_reg_fw - wait until MCR register matches expected state
+ * intel_gt_mcr_wait_for_reg - wait until MCR register matches expected state
  * @gt: GT structure
  * @reg: the register to read
  * @mask: mask to apply to register value
-- 
GitLab


From 449a0ef584d42ed24b7432c899863eaabe2583b5 Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Wed, 7 Dec 2022 15:29:09 +0400
Subject: [PATCH 370/875] drm/i915: Fix documentation for
 intel_uncore_forcewake_put__locked

intel_uncore_forcewake_put__locked() is used to release a reference.

Fixes: a6111f7b6604 ("drm/i915: Reduce locking in execlist command submission")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221207112909.2655251-1-linmq006@gmail.com
(cherry picked from commit 955f4d7176eb154db587ae162ec2b392dc8d5f27)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 8006a6c614660..614013745fcaf 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -824,9 +824,9 @@ void intel_uncore_forcewake_flush(struct intel_uncore *uncore,
 }
 
 /**
- * intel_uncore_forcewake_put__locked - grab forcewake domain references
+ * intel_uncore_forcewake_put__locked - release forcewake domain references
  * @uncore: the intel_uncore structure
- * @fw_domains: forcewake domains to get reference on
+ * @fw_domains: forcewake domains to put references
  *
  * See intel_uncore_forcewake_put(). This variant places the onus
  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
-- 
GitLab


From d4d4c6fbae3837623708594a7499f40673fb0692 Mon Sep 17 00:00:00 2001
From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Date: Wed, 23 Nov 2022 15:53:42 -0800
Subject: [PATCH 371/875] drm/i915/perf: Do not parse context image for HSW

An earlier commit introduced a mechanism to parse the context image to
find the OA context control offset. This resulted in an NPD on haswell
when gem_context was passed into i915_perf_open_ioctl params. Haswell
does not support logical ring contexts, so ensure that the context image
is parsed only for platforms with logical ring contexts and also
validate lrc_reg_state.

v2: Fix build failure
v3: Fix checkpatch error

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7432
Fixes: a5c3a3cbf029 ("drm/i915/perf: Determine gen12 oa ctx offset at runtime")
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221123235342.713068-1-umesh.nerlige.ramappa@intel.com
(cherry picked from commit 95c713d722017b26e301303713d638e0b95b1f68)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_perf.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 00e09bb18b13b..125b6ca25a756 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1383,6 +1383,9 @@ static u32 oa_context_image_offset(struct intel_context *ce, u32 reg)
 	u32 offset, len = (ce->engine->context_size - PAGE_SIZE) / 4;
 	u32 *state = ce->lrc_reg_state;
 
+	if (drm_WARN_ON(&ce->engine->i915->drm, !state))
+		return U32_MAX;
+
 	for (offset = 0; offset < len; ) {
 		if (IS_MI_LRI_CMD(state[offset])) {
 			/*
@@ -1447,7 +1450,8 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
 	if (IS_ERR(ce))
 		return PTR_ERR(ce);
 
-	if (engine_supports_mi_query(stream->engine)) {
+	if (engine_supports_mi_query(stream->engine) &&
+	    HAS_LOGICAL_RING_CONTEXTS(stream->perf->i915)) {
 		/*
 		 * We are enabling perf query here. If we don't find the context
 		 * offset here, just return an error.
-- 
GitLab


From 2165359b7ed4e0b93fc23f49ede38d76e91fffe1 Mon Sep 17 00:00:00 2001
From: Colin Ian King <colin.i.king@gmail.com>
Date: Thu, 8 Dec 2022 12:18:54 +0000
Subject: [PATCH 372/875] drm/amd/display: Fix spelling mistake:
 "dram_clk_chanage" -> "dram_clk_change"

There is a spelling mistake in the struct field dram_clk_chanage. Fix it.

Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c       | 8 ++++----
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c   | 4 ++--
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c       | 8 ++++----
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c       | 8 ++++----
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c       | 8 ++++----
 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h          | 2 +-
 7 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
index 0f746bb4e500f..d51f1ce028748 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
@@ -55,7 +55,7 @@ void hubbub1_wm_read_state(struct hubbub *hubbub,
 		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
 		s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
 	}
-	s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
+	s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
 
 	s = &wm->sets[1];
 	s->wm_set = 1;
@@ -65,7 +65,7 @@ void hubbub1_wm_read_state(struct hubbub *hubbub,
 		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
 		s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);
 	}
-	s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);
+	s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);
 
 	s = &wm->sets[2];
 	s->wm_set = 2;
@@ -75,7 +75,7 @@ void hubbub1_wm_read_state(struct hubbub *hubbub,
 		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);
 		s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);
 	}
-	s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);
+	s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);
 
 	s = &wm->sets[3];
 	s->wm_set = 3;
@@ -85,7 +85,7 @@ void hubbub1_wm_read_state(struct hubbub *hubbub,
 		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);
 		s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);
 	}
-	s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
+	s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
 }
 
 void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index c8ec11839b4d1..fe2023f18b7d0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -159,7 +159,7 @@ static void dcn10_log_hubbub_state(struct dc *dc,
 		DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
 		DTN_INFO_MICRO_SEC(s->sr_enter);
 		DTN_INFO_MICRO_SEC(s->sr_exit);
-		DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
+		DTN_INFO_MICRO_SEC(s->dram_clk_change);
 		DTN_INFO("\n");
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
index e8b6065fffad4..a0f8e31d2adc9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
@@ -83,7 +83,7 @@ static unsigned int dcn10_get_hubbub_state(struct dc *dc, char *pBuf, unsigned i
 	memset(&wm, 0, sizeof(struct dcn_hubbub_wm));
 	dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);
 
-	chars_printed = snprintf_count(pBuf, remaining_buffer, "wm_set_index,data_urgent,pte_meta_urgent,sr_enter,sr_exit,dram_clk_chanage\n");
+	chars_printed = snprintf_count(pBuf, remaining_buffer, "wm_set_index,data_urgent,pte_meta_urgent,sr_enter,sr_exit,dram_clk_change\n");
 	remaining_buffer -= chars_printed;
 	pBuf += chars_printed;
 
@@ -98,7 +98,7 @@ static unsigned int dcn10_get_hubbub_state(struct dc *dc, char *pBuf, unsigned i
 			(s->pte_meta_urgent * frac) / ref_clk_mhz / frac, (s->pte_meta_urgent * frac) / ref_clk_mhz % frac,
 			(s->sr_enter * frac) / ref_clk_mhz / frac, (s->sr_enter * frac) / ref_clk_mhz % frac,
 			(s->sr_exit * frac) / ref_clk_mhz / frac, (s->sr_exit * frac) / ref_clk_mhz % frac,
-			(s->dram_clk_chanage * frac) / ref_clk_mhz / frac, (s->dram_clk_chanage * frac) / ref_clk_mhz % frac);
+			(s->dram_clk_change * frac) / ref_clk_mhz / frac, (s->dram_clk_change * frac) / ref_clk_mhz % frac);
 		remaining_buffer -= chars_printed;
 		pBuf += chars_printed;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
index aacb1fb5c73eb..24bd932199366 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
@@ -500,7 +500,7 @@ void hubbub2_wm_read_state(struct hubbub *hubbub,
 		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
 		s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
 	}
-	s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
+	s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
 
 	s = &wm->sets[1];
 	s->wm_set = 1;
@@ -511,7 +511,7 @@ void hubbub2_wm_read_state(struct hubbub *hubbub,
 		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
 		s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);
 	}
-	s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);
+	s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);
 
 	s = &wm->sets[2];
 	s->wm_set = 2;
@@ -522,7 +522,7 @@ void hubbub2_wm_read_state(struct hubbub *hubbub,
 		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);
 		s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);
 	}
-	s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);
+	s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);
 
 	s = &wm->sets[3];
 	s->wm_set = 3;
@@ -533,7 +533,7 @@ void hubbub2_wm_read_state(struct hubbub *hubbub,
 		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);
 		s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);
 	}
-	s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
+	s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
 }
 
 void hubbub2_get_dchub_ref_freq(struct hubbub *hubbub,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
index c5e200d09038f..aeb0e0d9b70a4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
@@ -635,7 +635,7 @@ void hubbub21_wm_read_state(struct hubbub *hubbub,
 			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, &s->sr_exit);
 
 	REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A,
-			 DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, &s->dram_clk_chanage);
+			 DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, &s->dram_clk_change);
 
 	s = &wm->sets[1];
 	s->wm_set = 1;
@@ -649,7 +649,7 @@ void hubbub21_wm_read_state(struct hubbub *hubbub,
 			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, &s->sr_exit);
 
 	REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B,
-			DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, &s->dram_clk_chanage);
+			DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, &s->dram_clk_change);
 
 	s = &wm->sets[2];
 	s->wm_set = 2;
@@ -663,7 +663,7 @@ void hubbub21_wm_read_state(struct hubbub *hubbub,
 			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, &s->sr_exit);
 
 	REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C,
-			DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, &s->dram_clk_chanage);
+			DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, &s->dram_clk_change);
 
 	s = &wm->sets[3];
 	s->wm_set = 3;
@@ -677,7 +677,7 @@ void hubbub21_wm_read_state(struct hubbub *hubbub,
 			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, &s->sr_exit);
 
 	REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D,
-			DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, &s->dram_clk_chanage);
+			DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, &s->dram_clk_change);
 }
 
 static void hubbub21_apply_DEDCN21_147_wa(struct hubbub *hubbub)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
index 5947c2cb0f301..9501403a48a95 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
@@ -865,7 +865,7 @@ static void hubbub32_wm_read_state(struct hubbub *hubbub,
 			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, &s->sr_exit);
 
 	REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A,
-			 DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, &s->dram_clk_chanage);
+			 DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, &s->dram_clk_change);
 
 	REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A,
 			 DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, &s->usr_retrain);
@@ -885,7 +885,7 @@ static void hubbub32_wm_read_state(struct hubbub *hubbub,
 			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, &s->sr_exit);
 
 	REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B,
-			DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, &s->dram_clk_chanage);
+			DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, &s->dram_clk_change);
 
 	REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B,
 			 DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, &s->usr_retrain);
@@ -905,7 +905,7 @@ static void hubbub32_wm_read_state(struct hubbub *hubbub,
 			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, &s->sr_exit);
 
 	REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C,
-			DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, &s->dram_clk_chanage);
+			DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, &s->dram_clk_change);
 
 	REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C,
 			 DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, &s->usr_retrain);
@@ -925,7 +925,7 @@ static void hubbub32_wm_read_state(struct hubbub *hubbub,
 			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, &s->sr_exit);
 
 	REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D,
-			DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, &s->dram_clk_chanage);
+			DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, &s->dram_clk_change);
 
 	REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D,
 			 DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, &s->usr_retrain);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
index f2e1fcb668fb9..5b0265c0df61c 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
@@ -46,7 +46,7 @@ struct dcn_hubbub_wm_set {
 	uint32_t pte_meta_urgent;
 	uint32_t sr_enter;
 	uint32_t sr_exit;
-	uint32_t dram_clk_chanage;
+	uint32_t dram_clk_change;
 	uint32_t usr_retrain;
 	uint32_t fclk_pstate_change;
 };
-- 
GitLab


From 81d0bcf9900932633d270d5bc4a54ff599c6ebdb Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Wed, 7 Dec 2022 11:08:53 -0500
Subject: [PATCH 373/875] drm/amdgpu: make display pinning more flexible (v2)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Only apply the static threshold for Stoney and Carrizo.
This hardware has certain requirements that don't allow
mixing of GTT and VRAM.  Newer asics do not have these
requirements so we should be able to be more flexible
with where buffers end up.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2270
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2291
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2255
Acked-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 919bbea2e3ac2..2df55cc7e07f6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1506,7 +1506,8 @@ u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
 uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev,
 					    uint32_t domain)
 {
-	if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) {
+	if ((domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) &&
+	    ((adev->asic_type == CHIP_CARRIZO) || (adev->asic_type == CHIP_STONEY))) {
 		domain = AMDGPU_GEM_DOMAIN_VRAM;
 		if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
 			domain = AMDGPU_GEM_DOMAIN_GTT;
-- 
GitLab


From 1d4624cd72b912b2680c08d0be48338a1629a858 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Mon, 21 Nov 2022 15:52:19 -0500
Subject: [PATCH 374/875] drm/amdgpu: handle polaris10/11 overlap asics (v2)

Some special polaris 10 chips overlap with the polaris11
DID range.  Handle this properly in the driver.

v2: use local flags for other function calls.

Acked-by: Luben Tuikov <luben.tuikov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 7383272c6a3a6..b4f2d61ea0d53 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -2039,6 +2039,15 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
 			 "See modparam exp_hw_support\n");
 		return -ENODEV;
 	}
+	/* differentiate between P10 and P11 asics with the same DID */
+	if (pdev->device == 0x67FF &&
+	    (pdev->revision == 0xE3 ||
+	     pdev->revision == 0xE7 ||
+	     pdev->revision == 0xF3 ||
+	     pdev->revision == 0xF7)) {
+		flags &= ~AMD_ASIC_MASK;
+		flags |= CHIP_POLARIS10;
+	}
 
 	/* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
 	 * however, SME requires an indirect IOMMU mapping because the encryption
@@ -2108,12 +2117,12 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
 
 	pci_set_drvdata(pdev, ddev);
 
-	ret = amdgpu_driver_load_kms(adev, ent->driver_data);
+	ret = amdgpu_driver_load_kms(adev, flags);
 	if (ret)
 		goto err_pci;
 
 retry_init:
-	ret = drm_dev_register(ddev, ent->driver_data);
+	ret = drm_dev_register(ddev, flags);
 	if (ret == -EAGAIN && ++retry <= 3) {
 		DRM_INFO("retry init %d\n", retry);
 		/* Don't request EX mode too frequently which is attacking */
-- 
GitLab


From 2aa2a5ead0ee0a358bf80a2984a641d1bf2adc2a Mon Sep 17 00:00:00 2001
From: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Date: Fri, 9 Dec 2022 13:45:28 +0200
Subject: [PATCH 375/875] ASoC: SOF: Intel: pci-tgl: unblock S5 entry if DMA
 stop has failed"
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

If system shutdown has not been completed cleanly, it is possible the
DMA stream shutdown has not been done, or was not clean.

If this is the case, Intel TGL/ADL HDA platforms may fail to shutdown
cleanly due to pending HDA DMA transactions. To avoid this, detect this
scenario in the shutdown callback, and perform an additional controller
reset. This has been tested to unblock S5 entry if this condition is
hit.

Co-developed-by: Archana Patni <archana.patni@intel.com>
Signed-off-by: Archana Patni <archana.patni@intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20221209114529.3909192-2-kai.vehmanen@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/sof/intel/hda-dsp.c | 72 +++++++++++++++++++++++++++++++++++
 sound/soc/sof/intel/hda.h     |  1 +
 sound/soc/sof/intel/tgl.c     |  2 +-
 3 files changed, 74 insertions(+), 1 deletion(-)

diff --git a/sound/soc/sof/intel/hda-dsp.c b/sound/soc/sof/intel/hda-dsp.c
index 5fa29df54b42e..b4eacae8564c8 100644
--- a/sound/soc/sof/intel/hda-dsp.c
+++ b/sound/soc/sof/intel/hda-dsp.c
@@ -878,6 +878,78 @@ int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
 	return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
 }
 
+static unsigned int hda_dsp_check_for_dma_streams(struct snd_sof_dev *sdev)
+{
+	struct hdac_bus *bus = sof_to_bus(sdev);
+	struct hdac_stream *s;
+	unsigned int active_streams = 0;
+	int sd_offset;
+	u32 val;
+
+	list_for_each_entry(s, &bus->stream_list, list) {
+		sd_offset = SOF_STREAM_SD_OFFSET(s);
+		val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
+				       sd_offset);
+		if (val & SOF_HDA_SD_CTL_DMA_START)
+			active_streams |= BIT(s->index);
+	}
+
+	return active_streams;
+}
+
+static int hda_dsp_s5_quirk(struct snd_sof_dev *sdev)
+{
+	int ret;
+
+	/*
+	 * Do not assume a certain timing between the prior
+	 * suspend flow, and running of this quirk function.
+	 * This is needed if the controller was just put
+	 * to reset before calling this function.
+	 */
+	usleep_range(500, 1000);
+
+	/*
+	 * Take controller out of reset to flush DMA
+	 * transactions.
+	 */
+	ret = hda_dsp_ctrl_link_reset(sdev, false);
+	if (ret < 0)
+		return ret;
+
+	usleep_range(500, 1000);
+
+	/* Restore state for shutdown, back to reset */
+	ret = hda_dsp_ctrl_link_reset(sdev, true);
+	if (ret < 0)
+		return ret;
+
+	return ret;
+}
+
+int hda_dsp_shutdown_dma_flush(struct snd_sof_dev *sdev)
+{
+	unsigned int active_streams;
+	int ret, ret2;
+
+	/* check if DMA cleanup has been successful */
+	active_streams = hda_dsp_check_for_dma_streams(sdev);
+
+	sdev->system_suspend_target = SOF_SUSPEND_S3;
+	ret = snd_sof_suspend(sdev->dev);
+
+	if (active_streams) {
+		dev_warn(sdev->dev,
+			 "There were active DSP streams (%#x) at shutdown, trying to recover\n",
+			 active_streams);
+		ret2 = hda_dsp_s5_quirk(sdev);
+		if (ret2 < 0)
+			dev_err(sdev->dev, "shutdown recovery failed (%d)\n", ret2);
+	}
+
+	return ret;
+}
+
 int hda_dsp_shutdown(struct snd_sof_dev *sdev)
 {
 	sdev->system_suspend_target = SOF_SUSPEND_S3;
diff --git a/sound/soc/sof/intel/hda.h b/sound/soc/sof/intel/hda.h
index 022ce80968ddd..caccaf8fba9c0 100644
--- a/sound/soc/sof/intel/hda.h
+++ b/sound/soc/sof/intel/hda.h
@@ -592,6 +592,7 @@ int hda_dsp_resume(struct snd_sof_dev *sdev);
 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev);
 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev);
 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev);
+int hda_dsp_shutdown_dma_flush(struct snd_sof_dev *sdev);
 int hda_dsp_shutdown(struct snd_sof_dev *sdev);
 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev);
 void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
diff --git a/sound/soc/sof/intel/tgl.c b/sound/soc/sof/intel/tgl.c
index 30f2f49ee149f..58ac3a46e6a75 100644
--- a/sound/soc/sof/intel/tgl.c
+++ b/sound/soc/sof/intel/tgl.c
@@ -60,7 +60,7 @@ int sof_tgl_ops_init(struct snd_sof_dev *sdev)
 	memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
 
 	/* probe/remove/shutdown */
-	sof_tgl_ops.shutdown	= hda_dsp_shutdown;
+	sof_tgl_ops.shutdown	= hda_dsp_shutdown_dma_flush;
 
 	if (sdev->pdata->ipc_type == SOF_IPC) {
 		/* doorbell */
-- 
GitLab


From 44fda61d2bcfb74a942df93959e083a4e8eff75f Mon Sep 17 00:00:00 2001
From: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Date: Fri, 9 Dec 2022 13:45:29 +0200
Subject: [PATCH 376/875] ASoC: SOF: Revert: "core: unregister clients and
 machine drivers in .shutdown"
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The unregister machine drivers call is not safe to do when
kexec is used. Kexec-lite gets blocked with following backtrace:

[   84.943749] Freezing user space processes ... (elapsed 0.111 seconds) done.
[  246.784446] INFO: task kexec-lite:5123 blocked for more than 122 seconds.
[  246.819035] Call Trace:
[  246.821782]  <TASK>
[  246.824186]  __schedule+0x5f9/0x1263
[  246.828231]  schedule+0x87/0xc5
[  246.831779]  snd_card_disconnect_sync+0xb5/0x127
...
[  246.889249]  snd_sof_device_shutdown+0xb4/0x150
[  246.899317]  pci_device_shutdown+0x37/0x61
[  246.903990]  device_shutdown+0x14c/0x1d6
[  246.908391]  kernel_kexec+0x45/0xb9

This reverts commit 83bfc7e793b555291785136c3ae86abcdc046887.

Reported-by: Ricardo Ribalda <ribalda@chromium.org>
Cc: Ricardo Ribalda <ribalda@chromium.org>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20221209114529.3909192-3-kai.vehmanen@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/sof/core.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/sound/soc/sof/core.c b/sound/soc/sof/core.c
index 3e6141d03770f..625977a29d8a8 100644
--- a/sound/soc/sof/core.c
+++ b/sound/soc/sof/core.c
@@ -475,19 +475,10 @@ EXPORT_SYMBOL(snd_sof_device_remove);
 int snd_sof_device_shutdown(struct device *dev)
 {
 	struct snd_sof_dev *sdev = dev_get_drvdata(dev);
-	struct snd_sof_pdata *pdata = sdev->pdata;
 
 	if (IS_ENABLED(CONFIG_SND_SOC_SOF_PROBE_WORK_QUEUE))
 		cancel_work_sync(&sdev->probe_work);
 
-	/*
-	 * make sure clients and machine driver(s) are unregistered to force
-	 * all userspace devices to be closed prior to the DSP shutdown sequence
-	 */
-	sof_unregister_clients(sdev);
-
-	snd_sof_machine_unregister(sdev, pdata);
-
 	if (sdev->fw_state == SOF_FW_BOOT_COMPLETE)
 		return snd_sof_shutdown(sdev);
 
-- 
GitLab


From 83f1b7f39af73b01edf098fe3141404670703281 Mon Sep 17 00:00:00 2001
From: YC Hung <yc.hung@mediatek.com>
Date: Fri, 9 Dec 2022 11:10:53 +0800
Subject: [PATCH 377/875] ASoC: mediatek: mt8195: add sof be ops to check audio
 active

In MT8195 SOF design, both DSP and audio driver would access audio
registers. Before DSP accesses audio registers, audio power and clock
should be enabled. DSP will hang up if DSP access audio register but
audio power and clock are disabled. Therefore, we add audio pm runtime
active checking before accessing audio registers in SOF BE's callback
hw_params function to avoid this situation.

Signed-off-by: YC Hung <yc.hung@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Curtis Malainey <cujomalainey@chromium.org>
Link: https://lore.kernel.org/r/20221209031053.8444-1-yc.hung@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/mediatek/mt8195/mt8195-mt6359.c | 30 +++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/sound/soc/mediatek/mt8195/mt8195-mt6359.c b/sound/soc/mediatek/mt8195/mt8195-mt6359.c
index 61be66f47723c..4682748d82bed 100644
--- a/sound/soc/mediatek/mt8195/mt8195-mt6359.c
+++ b/sound/soc/mediatek/mt8195/mt8195-mt6359.c
@@ -633,6 +633,32 @@ static const struct snd_soc_ops mt8195_rt1011_etdm_ops = {
 	.hw_params = mt8195_rt1011_etdm_hw_params,
 };
 
+static int mt8195_sof_be_hw_params(struct snd_pcm_substream *substream,
+				   struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+	struct snd_soc_component *cmpnt_afe = NULL;
+	struct snd_soc_pcm_runtime *runtime;
+
+	/* find afe component */
+	for_each_card_rtds(rtd->card, runtime) {
+		cmpnt_afe = snd_soc_rtdcom_lookup(runtime, AFE_PCM_NAME);
+		if (cmpnt_afe)
+			break;
+	}
+
+	if (cmpnt_afe && !pm_runtime_active(cmpnt_afe->dev)) {
+		dev_err(rtd->dev, "afe pm runtime is not active!!\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static const struct snd_soc_ops mt8195_sof_be_ops = {
+	.hw_params = mt8195_sof_be_hw_params,
+};
+
 static int mt8195_rt1011_init(struct snd_soc_pcm_runtime *rtd)
 {
 	struct snd_soc_card *card = rtd->card;
@@ -1272,24 +1298,28 @@ static struct snd_soc_dai_link mt8195_mt6359_dai_links[] = {
 		.name = "AFE_SOF_DL2",
 		.no_pcm = 1,
 		.dpcm_playback = 1,
+		.ops = &mt8195_sof_be_ops,
 		SND_SOC_DAILINK_REG(AFE_SOF_DL2),
 	},
 	[DAI_LINK_SOF_DL3_BE] = {
 		.name = "AFE_SOF_DL3",
 		.no_pcm = 1,
 		.dpcm_playback = 1,
+		.ops = &mt8195_sof_be_ops,
 		SND_SOC_DAILINK_REG(AFE_SOF_DL3),
 	},
 	[DAI_LINK_SOF_UL4_BE] = {
 		.name = "AFE_SOF_UL4",
 		.no_pcm = 1,
 		.dpcm_capture = 1,
+		.ops = &mt8195_sof_be_ops,
 		SND_SOC_DAILINK_REG(AFE_SOF_UL4),
 	},
 	[DAI_LINK_SOF_UL5_BE] = {
 		.name = "AFE_SOF_UL5",
 		.no_pcm = 1,
 		.dpcm_capture = 1,
+		.ops = &mt8195_sof_be_ops,
 		SND_SOC_DAILINK_REG(AFE_SOF_UL5),
 	},
 };
-- 
GitLab


From 9529dc167ffcdfd201b9f0eda71015f174095f7e Mon Sep 17 00:00:00 2001
From: Marek Szyprowski <m.szyprowski@samsung.com>
Date: Fri, 9 Dec 2022 10:16:57 +0100
Subject: [PATCH 378/875] ASoC: wm8994: Fix potential deadlock

Fix this by dropping wm8994->accdet_lock while calling
cancel_delayed_work_sync(&wm8994->mic_work) in wm1811_jackdet_irq().

Fixes: c0cc3f166525 ("ASoC: wm8994: Allow a delay between jack insertion and microphone detect")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20221209091657.1183-1-m.szyprowski@samsung.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/codecs/wm8994.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
index d3cfd3788f2ab..8fe9a75d12357 100644
--- a/sound/soc/codecs/wm8994.c
+++ b/sound/soc/codecs/wm8994.c
@@ -3853,7 +3853,12 @@ static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
 	} else {
 		dev_dbg(component->dev, "Jack not detected\n");
 
+		/* Release wm8994->accdet_lock to avoid deadlock:
+		 * cancel_delayed_work_sync() takes wm8994->mic_work internal
+		 * lock and wm1811_mic_work takes wm8994->accdet_lock */
+		mutex_unlock(&wm8994->accdet_lock);
 		cancel_delayed_work_sync(&wm8994->mic_work);
+		mutex_lock(&wm8994->accdet_lock);
 
 		snd_soc_component_update_bits(component, WM8958_MICBIAS2,
 				    WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
-- 
GitLab


From 6d94d0090527b1763872275a7ccd44df7219b31e Mon Sep 17 00:00:00 2001
From: Wang Jingjin <wangjingjin1@huawei.com>
Date: Thu, 8 Dec 2022 14:39:00 +0800
Subject: [PATCH 379/875] ASoC: rockchip: spdif: Add missing
 clk_disable_unprepare() in rk_spdif_runtime_resume()

rk_spdif_runtime_resume() may have called clk_prepare_enable() before return
from failed branches, add missing clk_disable_unprepare() in this case.

Fixes: f874b80e1571 ("ASoC: rockchip: Add rockchip SPDIF transceiver driver")
Signed-off-by: Wang Jingjin <wangjingjin1@huawei.com>
Link: https://lore.kernel.org/r/20221208063900.4180790-1-wangjingjin1@huawei.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/rockchip/rockchip_spdif.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/sound/soc/rockchip/rockchip_spdif.c b/sound/soc/rockchip/rockchip_spdif.c
index 8bef572d3cbc1..5b4f004575879 100644
--- a/sound/soc/rockchip/rockchip_spdif.c
+++ b/sound/soc/rockchip/rockchip_spdif.c
@@ -88,6 +88,7 @@ static int __maybe_unused rk_spdif_runtime_resume(struct device *dev)
 
 	ret = clk_prepare_enable(spdif->hclk);
 	if (ret) {
+		clk_disable_unprepare(spdif->mclk);
 		dev_err(spdif->dev, "hclk clock enable failed %d\n", ret);
 		return ret;
 	}
-- 
GitLab


From 0612d748003ce7bcd0d67a8d270900fcdadb1009 Mon Sep 17 00:00:00 2001
From: Gongjun Song <gongjun.song@intel.com>
Date: Mon, 12 Dec 2022 16:55:27 +0800
Subject: [PATCH 380/875] ASoC: Intel: soc-acpi: update codec addr on 0C11/0C4F
 product

The unique ID is determined by the ADR pin level of rt1318.
ODM changed design, update codec addr to match new design.

Fixes: 0050e3d3d43d ("ASoC: Intel: soc-acpi: add SKU 0C11 SoundWire configuration")
Signed-off-by: Gongjun Song <gongjun.song@intel.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20221212085527.1886168-1-yung-chuan.liao@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/common/soc-acpi-intel-rpl-match.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/intel/common/soc-acpi-intel-rpl-match.c b/sound/soc/intel/common/soc-acpi-intel-rpl-match.c
index 3c5229f41bb03..31b43116e3d88 100644
--- a/sound/soc/intel/common/soc-acpi-intel-rpl-match.c
+++ b/sound/soc/intel/common/soc-acpi-intel-rpl-match.c
@@ -112,7 +112,7 @@ static const struct snd_soc_acpi_adr_device rt1316_1_group2_adr[] = {
 
 static const struct snd_soc_acpi_adr_device rt1318_1_group1_adr[] = {
 	{
-		.adr = 0x000131025D131801ull,
+		.adr = 0x000132025D131801ull,
 		.num_endpoints = 1,
 		.endpoints = &spk_l_endpoint,
 		.name_prefix = "rt1318-1"
-- 
GitLab


From 1c0908d8e441631f5b8ba433523cf39339ee2ba0 Mon Sep 17 00:00:00 2001
From: Mel Gorman <mgorman@techsingularity.net>
Date: Fri, 2 Dec 2022 10:02:23 +0000
Subject: [PATCH 381/875] rtmutex: Add acquire semantics for rtmutex lock
 acquisition slow path

Jan Kara reported the following bug triggering on 6.0.5-rt14 running dbench
on XFS on arm64.

 kernel BUG at fs/inode.c:625!
 Internal error: Oops - BUG: 0 [#1] PREEMPT_RT SMP
 CPU: 11 PID: 6611 Comm: dbench Tainted: G            E   6.0.0-rt14-rt+ #1
 pc : clear_inode+0xa0/0xc0
 lr : clear_inode+0x38/0xc0
 Call trace:
  clear_inode+0xa0/0xc0
  evict+0x160/0x180
  iput+0x154/0x240
  do_unlinkat+0x184/0x300
  __arm64_sys_unlinkat+0x48/0xc0
  el0_svc_common.constprop.4+0xe4/0x2c0
  do_el0_svc+0xac/0x100
  el0_svc+0x78/0x200
  el0t_64_sync_handler+0x9c/0xc0
  el0t_64_sync+0x19c/0x1a0

It also affects 6.1-rc7-rt5 and affects a preempt-rt fork of 5.14 so this
is likely a bug that existed forever and only became visible when ARM
support was added to preempt-rt. The same problem does not occur on x86-64
and he also reported that converting sb->s_inode_wblist_lock to
raw_spinlock_t makes the problem disappear indicating that the RT spinlock
variant is the problem.

Which in turn means that RT mutexes on ARM64 and any other weakly ordered
architecture are affected by this independent of RT.

Will Deacon observed:

  "I'd be more inclined to be suspicious of the slowpath tbh, as we need to
   make sure that we have acquire semantics on all paths where the lock can
   be taken. Looking at the rtmutex code, this really isn't obvious to me
   -- for example, try_to_take_rt_mutex() appears to be able to return via
   the 'takeit' label without acquire semantics and it looks like we might
   be relying on the caller's subsequent _unlock_ of the wait_lock for
   ordering, but that will give us release semantics which aren't correct."

Sebastian Andrzej Siewior prototyped a fix that does work based on that
comment but it was a little bit overkill and added some fences that should
not be necessary.

The lock owner is updated with an IRQ-safe raw spinlock held, but the
spin_unlock does not provide acquire semantics which are needed when
acquiring a mutex.

Adds the necessary acquire semantics for lock owner updates in the slow path
acquisition and the waiter bit logic.

It successfully completed 10 iterations of the dbench workload while the
vanilla kernel fails on the first iteration.

[ bigeasy@linutronix.de: Initial prototype fix ]

Fixes: 700318d1d7b38 ("locking/rtmutex: Use acquire/release semantics")
Fixes: 23f78d4a03c5 ("[PATCH] pi-futex: rt mutex core")
Reported-by: Jan Kara <jack@suse.cz>
Signed-off-by: Mel Gorman <mgorman@techsingularity.net>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20221202100223.6mevpbl7i6x5udfd@techsingularity.net
---
 kernel/locking/rtmutex.c     | 55 ++++++++++++++++++++++++++++++------
 kernel/locking/rtmutex_api.c |  6 ++--
 2 files changed, 49 insertions(+), 12 deletions(-)

diff --git a/kernel/locking/rtmutex.c b/kernel/locking/rtmutex.c
index 7779ee8abc2a0..010cf4e6d0b8f 100644
--- a/kernel/locking/rtmutex.c
+++ b/kernel/locking/rtmutex.c
@@ -89,15 +89,31 @@ static inline int __ww_mutex_check_kill(struct rt_mutex *lock,
  * set this bit before looking at the lock.
  */
 
-static __always_inline void
-rt_mutex_set_owner(struct rt_mutex_base *lock, struct task_struct *owner)
+static __always_inline struct task_struct *
+rt_mutex_owner_encode(struct rt_mutex_base *lock, struct task_struct *owner)
 {
 	unsigned long val = (unsigned long)owner;
 
 	if (rt_mutex_has_waiters(lock))
 		val |= RT_MUTEX_HAS_WAITERS;
 
-	WRITE_ONCE(lock->owner, (struct task_struct *)val);
+	return (struct task_struct *)val;
+}
+
+static __always_inline void
+rt_mutex_set_owner(struct rt_mutex_base *lock, struct task_struct *owner)
+{
+	/*
+	 * lock->wait_lock is held but explicit acquire semantics are needed
+	 * for a new lock owner so WRITE_ONCE is insufficient.
+	 */
+	xchg_acquire(&lock->owner, rt_mutex_owner_encode(lock, owner));
+}
+
+static __always_inline void rt_mutex_clear_owner(struct rt_mutex_base *lock)
+{
+	/* lock->wait_lock is held so the unlock provides release semantics. */
+	WRITE_ONCE(lock->owner, rt_mutex_owner_encode(lock, NULL));
 }
 
 static __always_inline void clear_rt_mutex_waiters(struct rt_mutex_base *lock)
@@ -106,7 +122,8 @@ static __always_inline void clear_rt_mutex_waiters(struct rt_mutex_base *lock)
 			((unsigned long)lock->owner & ~RT_MUTEX_HAS_WAITERS);
 }
 
-static __always_inline void fixup_rt_mutex_waiters(struct rt_mutex_base *lock)
+static __always_inline void
+fixup_rt_mutex_waiters(struct rt_mutex_base *lock, bool acquire_lock)
 {
 	unsigned long owner, *p = (unsigned long *) &lock->owner;
 
@@ -172,8 +189,21 @@ static __always_inline void fixup_rt_mutex_waiters(struct rt_mutex_base *lock)
 	 * still set.
 	 */
 	owner = READ_ONCE(*p);
-	if (owner & RT_MUTEX_HAS_WAITERS)
-		WRITE_ONCE(*p, owner & ~RT_MUTEX_HAS_WAITERS);
+	if (owner & RT_MUTEX_HAS_WAITERS) {
+		/*
+		 * See rt_mutex_set_owner() and rt_mutex_clear_owner() on
+		 * why xchg_acquire() is used for updating owner for
+		 * locking and WRITE_ONCE() for unlocking.
+		 *
+		 * WRITE_ONCE() would work for the acquire case too, but
+		 * in case that the lock acquisition failed it might
+		 * force other lockers into the slow path unnecessarily.
+		 */
+		if (acquire_lock)
+			xchg_acquire(p, owner & ~RT_MUTEX_HAS_WAITERS);
+		else
+			WRITE_ONCE(*p, owner & ~RT_MUTEX_HAS_WAITERS);
+	}
 }
 
 /*
@@ -208,6 +238,13 @@ static __always_inline void mark_rt_mutex_waiters(struct rt_mutex_base *lock)
 		owner = *p;
 	} while (cmpxchg_relaxed(p, owner,
 				 owner | RT_MUTEX_HAS_WAITERS) != owner);
+
+	/*
+	 * The cmpxchg loop above is relaxed to avoid back-to-back ACQUIRE
+	 * operations in the event of contention. Ensure the successful
+	 * cmpxchg is visible.
+	 */
+	smp_mb__after_atomic();
 }
 
 /*
@@ -1243,7 +1280,7 @@ static int __sched __rt_mutex_slowtrylock(struct rt_mutex_base *lock)
 	 * try_to_take_rt_mutex() sets the lock waiters bit
 	 * unconditionally. Clean this up.
 	 */
-	fixup_rt_mutex_waiters(lock);
+	fixup_rt_mutex_waiters(lock, true);
 
 	return ret;
 }
@@ -1604,7 +1641,7 @@ static int __sched __rt_mutex_slowlock(struct rt_mutex_base *lock,
 	 * try_to_take_rt_mutex() sets the waiter bit
 	 * unconditionally. We might have to fix that up.
 	 */
-	fixup_rt_mutex_waiters(lock);
+	fixup_rt_mutex_waiters(lock, true);
 
 	trace_contention_end(lock, ret);
 
@@ -1719,7 +1756,7 @@ static void __sched rtlock_slowlock_locked(struct rt_mutex_base *lock)
 	 * try_to_take_rt_mutex() sets the waiter bit unconditionally.
 	 * We might have to fix that up:
 	 */
-	fixup_rt_mutex_waiters(lock);
+	fixup_rt_mutex_waiters(lock, true);
 	debug_rt_mutex_free_waiter(&waiter);
 
 	trace_contention_end(lock, 0);
diff --git a/kernel/locking/rtmutex_api.c b/kernel/locking/rtmutex_api.c
index 900220941caac..cb9fdff76a8a3 100644
--- a/kernel/locking/rtmutex_api.c
+++ b/kernel/locking/rtmutex_api.c
@@ -267,7 +267,7 @@ void __sched rt_mutex_init_proxy_locked(struct rt_mutex_base *lock,
 void __sched rt_mutex_proxy_unlock(struct rt_mutex_base *lock)
 {
 	debug_rt_mutex_proxy_unlock(lock);
-	rt_mutex_set_owner(lock, NULL);
+	rt_mutex_clear_owner(lock);
 }
 
 /**
@@ -382,7 +382,7 @@ int __sched rt_mutex_wait_proxy_lock(struct rt_mutex_base *lock,
 	 * try_to_take_rt_mutex() sets the waiter bit unconditionally. We might
 	 * have to fix that up.
 	 */
-	fixup_rt_mutex_waiters(lock);
+	fixup_rt_mutex_waiters(lock, true);
 	raw_spin_unlock_irq(&lock->wait_lock);
 
 	return ret;
@@ -438,7 +438,7 @@ bool __sched rt_mutex_cleanup_proxy_lock(struct rt_mutex_base *lock,
 	 * try_to_take_rt_mutex() sets the waiter bit unconditionally. We might
 	 * have to fix that up.
 	 */
-	fixup_rt_mutex_waiters(lock);
+	fixup_rt_mutex_waiters(lock, false);
 
 	raw_spin_unlock_irq(&lock->wait_lock);
 
-- 
GitLab


From 1a4f69ef15ec29b213e2b086b2502644e8ef76ee Mon Sep 17 00:00:00 2001
From: Dominique Martinet <asmadeus@codewreck.org>
Date: Mon, 5 Dec 2022 21:39:01 +0900
Subject: [PATCH 382/875] 9p/client: fix data race on req->status

KCSAN reported a race between writing req->status in p9_client_cb and
accessing it in p9_client_rpc's wait_event.

Accesses to req itself is protected by the data barrier (writing req
fields, write barrier, writing status // reading status, read barrier,
reading other req fields), but status accesses themselves apparently
also must be annotated properly with WRITE_ONCE/READ_ONCE when we
access it without locks.

Follows:
 - error paths writing status in various threads all can notify
p9_client_rpc, so these all also need WRITE_ONCE
 - there's a similar read loop in trans_virtio for zc case that also
needs READ_ONCE
 - other reads in trans_fd should be protected by the trans_fd lock and
lists state machine, as corresponding writers all are within trans_fd
and should be under the same lock. If KCSAN complains on them we likely
will have something else to fix as well, so it's better to leave them
unmarked and look again if required.

Link: https://lkml.kernel.org/r/20221205124756.426350-1-asmadeus@codewreck.org
Reported-by: Naresh Kamboju <naresh.kamboju@linaro.org>
Suggested-by: Marco Elver <elver@google.com>
Acked-by: Marco Elver <elver@google.com>
Reviewed-by: Christian Schoenebeck <linux_oss@crudebyte.com>
Signed-off-by: Dominique Martinet <asmadeus@codewreck.org>
---
 net/9p/client.c       | 15 ++++++++-------
 net/9p/trans_fd.c     | 12 ++++++------
 net/9p/trans_rdma.c   |  4 ++--
 net/9p/trans_virtio.c |  9 +++++----
 net/9p/trans_xen.c    |  4 ++--
 5 files changed, 23 insertions(+), 21 deletions(-)

diff --git a/net/9p/client.c b/net/9p/client.c
index 7b2a997662d9c..fef6516a0639f 100644
--- a/net/9p/client.c
+++ b/net/9p/client.c
@@ -443,7 +443,7 @@ void p9_client_cb(struct p9_client *c, struct p9_req_t *req, int status)
 	 * the status change is visible to another thread
 	 */
 	smp_wmb();
-	req->status = status;
+	WRITE_ONCE(req->status, status);
 
 	wake_up(&req->wq);
 	p9_debug(P9_DEBUG_MUX, "wakeup: %d\n", req->tc.tag);
@@ -604,7 +604,7 @@ static int p9_client_flush(struct p9_client *c, struct p9_req_t *oldreq)
 	/* if we haven't received a response for oldreq,
 	 * remove it from the list
 	 */
-	if (oldreq->status == REQ_STATUS_SENT) {
+	if (READ_ONCE(oldreq->status) == REQ_STATUS_SENT) {
 		if (c->trans_mod->cancelled)
 			c->trans_mod->cancelled(c, oldreq);
 	}
@@ -704,7 +704,8 @@ p9_client_rpc(struct p9_client *c, int8_t type, const char *fmt, ...)
 	}
 again:
 	/* Wait for the response */
-	err = wait_event_killable(req->wq, req->status >= REQ_STATUS_RCVD);
+	err = wait_event_killable(req->wq,
+				  READ_ONCE(req->status) >= REQ_STATUS_RCVD);
 
 	/* Make sure our req is coherent with regard to updates in other
 	 * threads - echoes to wmb() in the callback
@@ -718,7 +719,7 @@ again:
 		goto again;
 	}
 
-	if (req->status == REQ_STATUS_ERROR) {
+	if (READ_ONCE(req->status) == REQ_STATUS_ERROR) {
 		p9_debug(P9_DEBUG_ERROR, "req_status error %d\n", req->t_err);
 		err = req->t_err;
 	}
@@ -731,7 +732,7 @@ again:
 			p9_client_flush(c, req);
 
 		/* if we received the response anyway, don't signal error */
-		if (req->status == REQ_STATUS_RCVD)
+		if (READ_ONCE(req->status) == REQ_STATUS_RCVD)
 			err = 0;
 	}
 recalc_sigpending:
@@ -803,7 +804,7 @@ static struct p9_req_t *p9_client_zc_rpc(struct p9_client *c, int8_t type,
 		if (err != -ERESTARTSYS)
 			goto recalc_sigpending;
 	}
-	if (req->status == REQ_STATUS_ERROR) {
+	if (READ_ONCE(req->status) == REQ_STATUS_ERROR) {
 		p9_debug(P9_DEBUG_ERROR, "req_status error %d\n", req->t_err);
 		err = req->t_err;
 	}
@@ -816,7 +817,7 @@ static struct p9_req_t *p9_client_zc_rpc(struct p9_client *c, int8_t type,
 			p9_client_flush(c, req);
 
 		/* if we received the response anyway, don't signal error */
-		if (req->status == REQ_STATUS_RCVD)
+		if (READ_ONCE(req->status) == REQ_STATUS_RCVD)
 			err = 0;
 	}
 recalc_sigpending:
diff --git a/net/9p/trans_fd.c b/net/9p/trans_fd.c
index 06ec9f7d3318c..f8899745571cf 100644
--- a/net/9p/trans_fd.c
+++ b/net/9p/trans_fd.c
@@ -201,11 +201,11 @@ static void p9_conn_cancel(struct p9_conn *m, int err)
 
 	list_for_each_entry_safe(req, rtmp, &m->req_list, req_list) {
 		list_move(&req->req_list, &cancel_list);
-		req->status = REQ_STATUS_ERROR;
+		WRITE_ONCE(req->status, REQ_STATUS_ERROR);
 	}
 	list_for_each_entry_safe(req, rtmp, &m->unsent_req_list, req_list) {
 		list_move(&req->req_list, &cancel_list);
-		req->status = REQ_STATUS_ERROR;
+		WRITE_ONCE(req->status, REQ_STATUS_ERROR);
 	}
 
 	spin_unlock(&m->req_lock);
@@ -466,7 +466,7 @@ static void p9_write_work(struct work_struct *work)
 
 		req = list_entry(m->unsent_req_list.next, struct p9_req_t,
 			       req_list);
-		req->status = REQ_STATUS_SENT;
+		WRITE_ONCE(req->status, REQ_STATUS_SENT);
 		p9_debug(P9_DEBUG_TRANS, "move req %p\n", req);
 		list_move_tail(&req->req_list, &m->req_list);
 
@@ -675,7 +675,7 @@ static int p9_fd_request(struct p9_client *client, struct p9_req_t *req)
 		return m->err;
 
 	spin_lock(&m->req_lock);
-	req->status = REQ_STATUS_UNSENT;
+	WRITE_ONCE(req->status, REQ_STATUS_UNSENT);
 	list_add_tail(&req->req_list, &m->unsent_req_list);
 	spin_unlock(&m->req_lock);
 
@@ -702,7 +702,7 @@ static int p9_fd_cancel(struct p9_client *client, struct p9_req_t *req)
 
 	if (req->status == REQ_STATUS_UNSENT) {
 		list_del(&req->req_list);
-		req->status = REQ_STATUS_FLSHD;
+		WRITE_ONCE(req->status, REQ_STATUS_FLSHD);
 		p9_req_put(client, req);
 		ret = 0;
 	}
@@ -731,7 +731,7 @@ static int p9_fd_cancelled(struct p9_client *client, struct p9_req_t *req)
 	 * remove it from the list.
 	 */
 	list_del(&req->req_list);
-	req->status = REQ_STATUS_FLSHD;
+	WRITE_ONCE(req->status, REQ_STATUS_FLSHD);
 	spin_unlock(&m->req_lock);
 
 	p9_req_put(client, req);
diff --git a/net/9p/trans_rdma.c b/net/9p/trans_rdma.c
index 33a9ac6f2d552..83f9100d46bff 100644
--- a/net/9p/trans_rdma.c
+++ b/net/9p/trans_rdma.c
@@ -506,7 +506,7 @@ dont_need_post_recv:
 	 * because doing if after could erase the REQ_STATUS_RCVD
 	 * status in case of a very fast reply.
 	 */
-	req->status = REQ_STATUS_SENT;
+	WRITE_ONCE(req->status, REQ_STATUS_SENT);
 	err = ib_post_send(rdma->qp, &wr, NULL);
 	if (err)
 		goto send_error;
@@ -516,7 +516,7 @@ dont_need_post_recv:
 
  /* Handle errors that happened during or while preparing the send: */
  send_error:
-	req->status = REQ_STATUS_ERROR;
+	WRITE_ONCE(req->status, REQ_STATUS_ERROR);
 	kfree(c);
 	p9_debug(P9_DEBUG_ERROR, "Error %d in rdma_request()\n", err);
 
diff --git a/net/9p/trans_virtio.c b/net/9p/trans_virtio.c
index 19bccfa0d593e..3c27ffb781e3e 100644
--- a/net/9p/trans_virtio.c
+++ b/net/9p/trans_virtio.c
@@ -262,7 +262,7 @@ p9_virtio_request(struct p9_client *client, struct p9_req_t *req)
 
 	p9_debug(P9_DEBUG_TRANS, "9p debug: virtio request\n");
 
-	req->status = REQ_STATUS_SENT;
+	WRITE_ONCE(req->status, REQ_STATUS_SENT);
 req_retry:
 	spin_lock_irqsave(&chan->lock, flags);
 
@@ -468,7 +468,7 @@ p9_virtio_zc_request(struct p9_client *client, struct p9_req_t *req,
 			inlen = n;
 		}
 	}
-	req->status = REQ_STATUS_SENT;
+	WRITE_ONCE(req->status, REQ_STATUS_SENT);
 req_retry_pinned:
 	spin_lock_irqsave(&chan->lock, flags);
 
@@ -531,9 +531,10 @@ req_retry_pinned:
 	spin_unlock_irqrestore(&chan->lock, flags);
 	kicked = 1;
 	p9_debug(P9_DEBUG_TRANS, "virtio request kicked\n");
-	err = wait_event_killable(req->wq, req->status >= REQ_STATUS_RCVD);
+	err = wait_event_killable(req->wq,
+			          READ_ONCE(req->status) >= REQ_STATUS_RCVD);
 	// RERROR needs reply (== error string) in static data
-	if (req->status == REQ_STATUS_RCVD &&
+	if (READ_ONCE(req->status) == REQ_STATUS_RCVD &&
 	    unlikely(req->rc.sdata[4] == P9_RERROR))
 		handle_rerror(req, in_hdr_len, offs, in_pages);
 
diff --git a/net/9p/trans_xen.c b/net/9p/trans_xen.c
index de2d2ca8819a1..9630b12755579 100644
--- a/net/9p/trans_xen.c
+++ b/net/9p/trans_xen.c
@@ -157,7 +157,7 @@ again:
 			      &masked_prod, masked_cons,
 			      XEN_9PFS_RING_SIZE(ring));
 
-	p9_req->status = REQ_STATUS_SENT;
+	WRITE_ONCE(p9_req->status, REQ_STATUS_SENT);
 	virt_wmb();			/* write ring before updating pointer */
 	prod += size;
 	ring->intf->out_prod = prod;
@@ -212,7 +212,7 @@ static void p9_xen_response(struct work_struct *work)
 			dev_warn(&priv->dev->dev,
 				 "requested packet size too big: %d for tag %d with capacity %zd\n",
 				 h.size, h.tag, req->rc.capacity);
-			req->status = REQ_STATUS_ERROR;
+			WRITE_ONCE(req->status, REQ_STATUS_ERROR);
 			goto recv_error;
 		}
 
-- 
GitLab


From a1dec9d70b6ad97087b60b81d2492134a84208c6 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Tue, 13 Dec 2022 13:32:46 +0100
Subject: [PATCH 383/875] ASoC: Intel: bytcr_rt5640: Add quirk for the
 Advantech MICA-071 tablet

The Advantech MICA-071 tablet deviates from the defaults for
a non CR Bay Trail based tablet in several ways:

1. It uses an analog MIC on IN3 rather then using DMIC1
2. It only has 1 speaker
3. It needs the OVCD current threshold to be set to 1500uA instead of
   the default 2000uA to reliable differentiate between headphones vs
   headsets

Add a quirk with these settings for this tablet.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20221213123246.11226-1-hdegoede@redhat.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/boards/bytcr_rt5640.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/sound/soc/intel/boards/bytcr_rt5640.c b/sound/soc/intel/boards/bytcr_rt5640.c
index 6db07b2417cad..44e6a0f1e2d90 100644
--- a/sound/soc/intel/boards/bytcr_rt5640.c
+++ b/sound/soc/intel/boards/bytcr_rt5640.c
@@ -570,6 +570,21 @@ static const struct dmi_system_id byt_rt5640_quirk_table[] = {
 					BYT_RT5640_SSP0_AIF1 |
 					BYT_RT5640_MCLK_EN),
 	},
+	{
+		/* Advantech MICA-071 */
+		.matches = {
+			DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Advantech"),
+			DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "MICA-071"),
+		},
+		/* OVCD Th = 1500uA to reliable detect head-phones vs -set */
+		.driver_data = (void *)(BYT_RT5640_IN3_MAP |
+					BYT_RT5640_JD_SRC_JD2_IN4N |
+					BYT_RT5640_OVCD_TH_1500UA |
+					BYT_RT5640_OVCD_SF_0P75 |
+					BYT_RT5640_MONO_SPEAKER |
+					BYT_RT5640_DIFF_MIC |
+					BYT_RT5640_MCLK_EN),
+	},
 	{
 		.matches = {
 			DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ARCHOS"),
-- 
GitLab


From 6c900dcc3f7331a67ed29739d74524e428d137fb Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Tue, 13 Dec 2022 13:33:19 +0100
Subject: [PATCH 384/875] ASoC: rt5670: Remove unbalanced pm_runtime_put()

For some reason rt5670_i2c_probe() does a pm_runtime_put() at the end
of a successful probe. But it has never done a pm_runtime_get() leading
to the following error being logged into dmesg:

 rt5670 i2c-10EC5640:00: Runtime PM usage count underflow!

Fix this by removing the unnecessary pm_runtime_put().

Fixes: 64e89e5f5548 ("ASoC: rt5670: Add runtime PM support")
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20221213123319.11285-1-hdegoede@redhat.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/codecs/rt5670.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/sound/soc/codecs/rt5670.c b/sound/soc/codecs/rt5670.c
index ebac6caeb40ad..a230f441559a6 100644
--- a/sound/soc/codecs/rt5670.c
+++ b/sound/soc/codecs/rt5670.c
@@ -3311,8 +3311,6 @@ static int rt5670_i2c_probe(struct i2c_client *i2c)
 	if (ret < 0)
 		goto err;
 
-	pm_runtime_put(&i2c->dev);
-
 	return 0;
 err:
 	pm_runtime_disable(&i2c->dev);
-- 
GitLab


From 7bd220f2ba9014b78f0304178103393554b8c4fe Mon Sep 17 00:00:00 2001
From: YC Hung <yc.hung@mediatek.com>
Date: Tue, 13 Dec 2022 19:56:17 +0800
Subject: [PATCH 385/875] ASoC: SOF: mediatek: initialize panic_info to zero

Coverity spotted that panic_info is not initialized to zero in
mtk_adsp_dump. Using uninitialized value panic_info.linenum when
calling snd_sof_get_status. Fix this coverity by initializing
panic_info struct as zero.

Signed-off-by: YC Hung <yc.hung@mediatek.com>
Reviewed-by: Curtis Malainey <cujomalainey@chromium.org>
Link: https://lore.kernel.org/r/20221213115617.25086-1-yc.hung@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/sof/mediatek/mtk-adsp-common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/sof/mediatek/mtk-adsp-common.c b/sound/soc/sof/mediatek/mtk-adsp-common.c
index 1e0769c668a7b..de8dbe27cd0de 100644
--- a/sound/soc/sof/mediatek/mtk-adsp-common.c
+++ b/sound/soc/sof/mediatek/mtk-adsp-common.c
@@ -60,7 +60,7 @@ void mtk_adsp_dump(struct snd_sof_dev *sdev, u32 flags)
 {
 	char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR;
 	struct sof_ipc_dsp_oops_xtensa xoops;
-	struct sof_ipc_panic_info panic_info;
+	struct sof_ipc_panic_info panic_info = {};
 	u32 stack[MTK_ADSP_STACK_DUMP_SIZE];
 	u32 status;
 
-- 
GitLab


From b2e9e6a9cb87ce4a82fb106ae16c94639835fd47 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Thu, 8 Dec 2022 00:52:19 +0200
Subject: [PATCH 386/875] drm/i915: Fix VLV/CHV HDMI/DP audio enable
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Despite what I claimed in commit c3c5dc1d9224
("drm/i915/audio: Do the vblank waits") the vblank
interrupts are in fact not enabled yet when we do the
audio enable sequence on VLV/CHV (all other platforms are
fine).

Reorder the enable sequence on VLV/CHV to match that of the
other platforms so that the audio enable happens after the
pipe has been enabled.

Fixes: c3c5dc1d9224 ("drm/i915/audio: Do the vblank waits")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221207225219.29060-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
(cherry picked from commit a467a243554a64b418c14d7531a3b18c03d53bff)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/display/g4x_dp.c   |  4 ++--
 drivers/gpu/drm/i915/display/g4x_hdmi.c | 25 +++++++++++++++++++------
 2 files changed, 21 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 3593938dcd87c..24ef36ec2d3d3 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -673,8 +673,6 @@ static void intel_enable_dp(struct intel_atomic_state *state,
 	intel_dp_pcon_dsc_configure(intel_dp, pipe_config);
 	intel_dp_start_link_train(intel_dp, pipe_config);
 	intel_dp_stop_link_train(intel_dp, pipe_config);
-
-	intel_audio_codec_enable(encoder, pipe_config, conn_state);
 }
 
 static void g4x_enable_dp(struct intel_atomic_state *state,
@@ -683,6 +681,7 @@ static void g4x_enable_dp(struct intel_atomic_state *state,
 			  const struct drm_connector_state *conn_state)
 {
 	intel_enable_dp(state, encoder, pipe_config, conn_state);
+	intel_audio_codec_enable(encoder, pipe_config, conn_state);
 	intel_edp_backlight_on(pipe_config, conn_state);
 }
 
@@ -691,6 +690,7 @@ static void vlv_enable_dp(struct intel_atomic_state *state,
 			  const struct intel_crtc_state *pipe_config,
 			  const struct drm_connector_state *conn_state)
 {
+	intel_audio_codec_enable(encoder, pipe_config, conn_state);
 	intel_edp_backlight_on(pipe_config, conn_state);
 }
 
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 121caeaa409b6..c3580d96765c6 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -157,10 +157,8 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
 			     &pipe_config->infoframes.hdmi);
 }
 
-static void g4x_enable_hdmi(struct intel_atomic_state *state,
-			    struct intel_encoder *encoder,
-			    const struct intel_crtc_state *pipe_config,
-			    const struct drm_connector_state *conn_state)
+static void g4x_hdmi_enable_port(struct intel_encoder *encoder,
+				 const struct intel_crtc_state *pipe_config)
 {
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -175,6 +173,16 @@ static void g4x_enable_hdmi(struct intel_atomic_state *state,
 
 	intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
 	intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
+}
+
+static void g4x_enable_hdmi(struct intel_atomic_state *state,
+			    struct intel_encoder *encoder,
+			    const struct intel_crtc_state *pipe_config,
+			    const struct drm_connector_state *conn_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+	g4x_hdmi_enable_port(encoder, pipe_config);
 
 	drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio &&
 		    !pipe_config->has_hdmi_sink);
@@ -294,6 +302,11 @@ static void vlv_enable_hdmi(struct intel_atomic_state *state,
 			    const struct intel_crtc_state *pipe_config,
 			    const struct drm_connector_state *conn_state)
 {
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+	drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio &&
+		    !pipe_config->has_hdmi_sink);
+	intel_audio_codec_enable(encoder, pipe_config, conn_state);
 }
 
 static void intel_disable_hdmi(struct intel_atomic_state *state,
@@ -415,7 +428,7 @@ static void vlv_hdmi_pre_enable(struct intel_atomic_state *state,
 			      pipe_config->has_infoframe,
 			      pipe_config, conn_state);
 
-	g4x_enable_hdmi(state, encoder, pipe_config, conn_state);
+	g4x_hdmi_enable_port(encoder, pipe_config);
 
 	vlv_wait_port_ready(dev_priv, dig_port, 0x0);
 }
@@ -492,7 +505,7 @@ static void chv_hdmi_pre_enable(struct intel_atomic_state *state,
 			      pipe_config->has_infoframe,
 			      pipe_config, conn_state);
 
-	g4x_enable_hdmi(state, encoder, pipe_config, conn_state);
+	g4x_hdmi_enable_port(encoder, pipe_config);
 
 	vlv_wait_port_ready(dev_priv, dig_port, 0x0);
 
-- 
GitLab


From 3153eebb7a76e663ac76d6670dc113296de96622 Mon Sep 17 00:00:00 2001
From: Khaled Almahallawy <khaled.almahallawy@intel.com>
Date: Wed, 23 Nov 2022 14:09:26 -0800
Subject: [PATCH 387/875] drm/i915/display: Don't disable DDI/Transcoder when
 setting phy test pattern

Bspecs has updated recently to remove the restriction to disable
DDI/Transcoder before setting PHY test pattern. This update is to
address PHY compliance test failures observed on a port with LTTPR.
The issue is that when Transc. is disabled, the main link signals fed
to LTTPR will be dropped invalidating link training, which will affect
the quality of the phy test pattern when the transcoder is enabled again.

v2: Update commit message (Clint)
v3: Add missing Signed-off in v2
v4: Update Bspec and commit message for pre-gen12 (Jani)

Bspec: 50482, 7555
Fixes: 8cdf72711928 ("drm/i915/dp: Program vswing, pre-emphasis, test-pattern")
Cc: Imre Deak <imre.deak@intel.com>
Cc: Clint Taylor <clinton.a.taylor@intel.com>
CC: Jani Nikula <jani.nikula@intel.com>
Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
Reviewed-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221123220926.170034-1-khaled.almahallawy@intel.com
(cherry picked from commit be4a847652056b067d6dc6fe0fc024a9e2e987ca)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 59 -------------------------
 1 file changed, 59 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 67089711d9e25..75070eb07d4bf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3679,61 +3679,6 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
 	}
 }
 
-static void
-intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
-				  const struct intel_crtc_state *crtc_state)
-{
-	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-	struct drm_device *dev = dig_port->base.base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
-	enum pipe pipe = crtc->pipe;
-	u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
-
-	trans_ddi_func_ctl_value = intel_de_read(dev_priv,
-						 TRANS_DDI_FUNC_CTL(pipe));
-	trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
-	dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
-
-	trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
-				      TGL_TRANS_DDI_PORT_MASK);
-	trans_conf_value &= ~PIPECONF_ENABLE;
-	dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
-
-	intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
-	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
-		       trans_ddi_func_ctl_value);
-	intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
-}
-
-static void
-intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
-				 const struct intel_crtc_state *crtc_state)
-{
-	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-	struct drm_device *dev = dig_port->base.base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	enum port port = dig_port->base.port;
-	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
-	enum pipe pipe = crtc->pipe;
-	u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
-
-	trans_ddi_func_ctl_value = intel_de_read(dev_priv,
-						 TRANS_DDI_FUNC_CTL(pipe));
-	trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
-	dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
-
-	trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
-				    TGL_TRANS_DDI_SELECT_PORT(port);
-	trans_conf_value |= PIPECONF_ENABLE;
-	dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
-
-	intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
-	intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
-	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
-		       trans_ddi_func_ctl_value);
-}
-
 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
 					 const struct intel_crtc_state *crtc_state)
 {
@@ -3752,14 +3697,10 @@ static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
 	intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
 				  link_status);
 
-	intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
-
 	intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
 
 	intel_dp_phy_pattern_update(intel_dp, crtc_state);
 
-	intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
-
 	drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
 			  intel_dp->train_set, crtc_state->lane_count);
 
-- 
GitLab


From 31a2e6cbe8a4eb0d1650fff4b77872b744e14a62 Mon Sep 17 00:00:00 2001
From: Chris Wilson <chris.p.wilson@intel.com>
Date: Fri, 2 Dec 2022 12:28:42 +0000
Subject: [PATCH 388/875] drm/i915/migrate: Account for the reserved_space

If the ring is nearly full when calling into emit_pte(), we might
incorrectly trample the reserved_space when constructing the packet to
emit the PTEs. This then triggers the GEM_BUG_ON(rq->reserved_space >
ring->space) when later submitting the request, since the request itself
doesn't have enough space left in the ring to emit things like
workarounds, breadcrumbs etc.

v2: Fix the whitespace errors

Testcase: igt@i915_selftests@live_emit_pte_full_ring
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7535
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6889
Fixes: cf586021642d ("drm/i915/gt: Pipelined page migration")
Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Nirmoy Das <nirmoy.das@intel.com>
Cc: <stable@vger.kernel.org> # v5.15+
Tested-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221202122844.428006-1-matthew.auld@intel.com
(cherry picked from commit 35168a6c4ed53db4f786858bac23b1474fd7d0dc)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_migrate.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
index b405a04135ca2..b783f6f740c8b 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -342,6 +342,16 @@ static int emit_no_arbitration(struct i915_request *rq)
 	return 0;
 }
 
+static int max_pte_pkt_size(struct i915_request *rq, int pkt)
+{
+	struct intel_ring *ring = rq->ring;
+
+	pkt = min_t(int, pkt, (ring->space - rq->reserved_space) / sizeof(u32) + 5);
+	pkt = min_t(int, pkt, (ring->size - ring->emit) / sizeof(u32) + 5);
+
+	return pkt;
+}
+
 static int emit_pte(struct i915_request *rq,
 		    struct sgt_dma *it,
 		    enum i915_cache_level cache_level,
@@ -388,8 +398,7 @@ static int emit_pte(struct i915_request *rq,
 		return PTR_ERR(cs);
 
 	/* Pack as many PTE updates as possible into a single MI command */
-	pkt = min_t(int, dword_length, ring->space / sizeof(u32) + 5);
-	pkt = min_t(int, pkt, (ring->size - ring->emit) / sizeof(u32) + 5);
+	pkt = max_pte_pkt_size(rq, dword_length);
 
 	hdr = cs;
 	*cs++ = MI_STORE_DATA_IMM | REG_BIT(21); /* as qword elements */
@@ -422,8 +431,7 @@ static int emit_pte(struct i915_request *rq,
 				}
 			}
 
-			pkt = min_t(int, dword_rem, ring->space / sizeof(u32) + 5);
-			pkt = min_t(int, pkt, (ring->size - ring->emit) / sizeof(u32) + 5);
+			pkt = max_pte_pkt_size(rq, dword_rem);
 
 			hdr = cs;
 			*cs++ = MI_STORE_DATA_IMM | REG_BIT(21);
-- 
GitLab


From 47ea20762bb7875a62e10433a3cd5d34e9133f47 Mon Sep 17 00:00:00 2001
From: Shikang Fan <shikang.fan@amd.com>
Date: Thu, 8 Dec 2022 19:53:14 +0800
Subject: [PATCH 389/875] drm/amdgpu: Add an extra evict_resource call during
 device_suspend.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

- evict_resource is taking too long causing sriov full access mode timeout.
  So, add an extra evict_resource in the beginning as an early evict.

Signed-off-by: Shikang Fan <shikang.fan@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index cfa411c120724..64660a41d53ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4112,6 +4112,11 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
 
 	adev->in_suspend = true;
 
+	/* Evict the majority of BOs before grabbing the full access */
+	r = amdgpu_device_evict_resources(adev);
+	if (r)
+		return r;
+
 	if (amdgpu_sriov_vf(adev)) {
 		amdgpu_virt_fini_data_exchange(adev);
 		r = amdgpu_virt_request_full_gpu(adev, false);
-- 
GitLab


From 01258b62c62710297dab4e2b72f46e01be392cc6 Mon Sep 17 00:00:00 2001
From: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Date: Fri, 9 Dec 2022 10:59:37 +0100
Subject: [PATCH 390/875] wifi: ti: remove obsolete lines in the Makefile

Commit 06463f6e98df ("wifi: wl1251: drop support for platform data")
removes TI WiLink platform data, but leaves some dead lines in the
Makefile.

Remove these obsolete lines in the Makefile.

Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Reviewed-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20221209095937.17773-1-lukas.bulwahn@gmail.com
---
 drivers/net/wireless/ti/Makefile | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/net/wireless/ti/Makefile b/drivers/net/wireless/ti/Makefile
index 0530dd744275c..05ee016594f8c 100644
--- a/drivers/net/wireless/ti/Makefile
+++ b/drivers/net/wireless/ti/Makefile
@@ -3,6 +3,3 @@ obj-$(CONFIG_WLCORE)			+= wlcore/
 obj-$(CONFIG_WL12XX)			+= wl12xx/
 obj-$(CONFIG_WL1251)			+= wl1251/
 obj-$(CONFIG_WL18XX)			+= wl18xx/
-
-# small builtin driver bit
-obj-$(CONFIG_WILINK_PLATFORM_DATA)	+= wilink_platform_data.o
-- 
GitLab


From 0debed5b117d11e33cba52870c4dcb64f5911891 Mon Sep 17 00:00:00 2001
From: ChiYuan Huang <cy_huang@richtek.com>
Date: Wed, 14 Dec 2022 09:37:11 +0800
Subject: [PATCH 391/875] regulator: core: Fix resolve supply lookup issue

From Marek's log, the previous change modify the parent of rdev.
https://lore.kernel.org/all/58b92e75-f373-dae7-7031-8abd465bb874@samsung.com/

In 'regulator_resolve_supply', it uses the parent DT node of rdev as the
DT-lookup starting node. But the parent DT node may not exist. This will
cause the NULL supply issue.

This patch modify the parent of rdev back to the device that provides
from 'regulator_config' in 'regulator_register'.

Fixes: 8f3cbcd6b440 ("regulator: core: Use different devices for resource allocation and DT lookup")
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: ChiYuan Huang <cy_huang@richtek.com>
Link: https://lore.kernel.org/r/1670981831-12583-1-git-send-email-u0084500@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 drivers/regulator/core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index c84e8d78dc7ed..35a7785c53f65 100644
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
@@ -5539,7 +5539,7 @@ regulator_register(struct device *dev,
 
 	/* register with sysfs */
 	rdev->dev.class = &regulator_class;
-	rdev->dev.parent = dev;
+	rdev->dev.parent = config->dev;
 	dev_set_name(&rdev->dev, "regulator.%lu",
 		    (unsigned long) atomic_inc_return(&regulator_no));
 	dev_set_drvdata(&rdev->dev, rdev);
-- 
GitLab


From 3b553e0041a65e499fa4e25ee146f01f4ec4e617 Mon Sep 17 00:00:00 2001
From: Christophe Leroy <christophe.leroy@csgroup.eu>
Date: Wed, 14 Dec 2022 14:41:33 +0100
Subject: [PATCH 392/875] spi: fsl_spi: Don't change speed while chipselect is
 active

Commit c9bfcb315104 ("spi_mpc83xx: much improved driver") made
modifications to the driver to not perform speed changes while
chipselect is active. But those changes where lost with the
convertion to tranfer_one.

Previous implementation was allowing speed changes during
message transfer when cs_change flag was set.
At the time being, core SPI does not provide any feature to change
speed while chipselect is off, so do not allow any speed change during
message transfer, and perform the transfer setup in prepare_message
in order to set correct speed while chipselect is still off.

Reported-by: Herve Codina <herve.codina@bootlin.com>
Fixes: 64ca1a034f00 ("spi: fsl_spi: Convert to transfer_one")
Cc: stable@vger.kernel.org
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Tested-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Herve Codina <herve.codina@bootlin.com>
Link: https://lore.kernel.org/r/8aab84c51aa330cf91f4b43782a1c483e150a4e3.1671025244.git.christophe.leroy@csgroup.eu
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 drivers/spi/spi-fsl-spi.c | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c
index 731624f157fc0..93152144fd2ec 100644
--- a/drivers/spi/spi-fsl-spi.c
+++ b/drivers/spi/spi-fsl-spi.c
@@ -333,13 +333,26 @@ static int fsl_spi_prepare_message(struct spi_controller *ctlr,
 {
 	struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(ctlr);
 	struct spi_transfer *t;
+	struct spi_transfer *first;
+
+	first = list_first_entry(&m->transfers, struct spi_transfer,
+				 transfer_list);
 
 	/*
 	 * In CPU mode, optimize large byte transfers to use larger
 	 * bits_per_word values to reduce number of interrupts taken.
+	 *
+	 * Some glitches can appear on the SPI clock when the mode changes.
+	 * Check that there is no speed change during the transfer and set it up
+	 * now to change the mode without having a chip-select asserted.
 	 */
-	if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
-		list_for_each_entry(t, &m->transfers, transfer_list) {
+	list_for_each_entry(t, &m->transfers, transfer_list) {
+		if (t->speed_hz != first->speed_hz) {
+			dev_err(&m->spi->dev,
+				"speed_hz cannot change during message.\n");
+			return -EINVAL;
+		}
+		if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
 			if (t->len < 256 || t->bits_per_word != 8)
 				continue;
 			if ((t->len & 3) == 0)
@@ -348,7 +361,7 @@ static int fsl_spi_prepare_message(struct spi_controller *ctlr,
 				t->bits_per_word = 16;
 		}
 	}
-	return 0;
+	return fsl_spi_setup_transfer(m->spi, first);
 }
 
 static int fsl_spi_transfer_one(struct spi_controller *controller,
-- 
GitLab


From 9c3db58bf8f7d0007049f686ce8c419eed4325d1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
Date: Wed, 7 Dec 2022 08:47:30 +0100
Subject: [PATCH 393/875] drm/amdgpu: fixx NULL pointer deref in
 gmc_v9_0_get_vm_pte
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

We not only need to make sure that we have a BO, but also that the BO
has some backing store.

Fixes: d1a372af1c3d ("drm/amdgpu: Set MTYPE in PTE based on BO flags")
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 50386eb2eec8d..08d6cf79fb15d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1185,6 +1185,8 @@ static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
 				struct amdgpu_bo_va_mapping *mapping,
 				uint64_t *flags)
 {
+	struct amdgpu_bo *bo = mapping->bo_va->base.bo;
+
 	*flags &= ~AMDGPU_PTE_EXECUTABLE;
 	*flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
 
@@ -1196,7 +1198,7 @@ static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
 		*flags &= ~AMDGPU_PTE_VALID;
 	}
 
-	if (mapping->bo_va->base.bo)
+	if (bo && bo->tbo.resource)
 		gmc_v9_0_get_coherence_flags(adev, mapping->bo_va->base.bo,
 					     mapping, flags);
 }
-- 
GitLab


From 4d2ccd96ac25846749fc58691f5142a966e65b3a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
Date: Wed, 16 Nov 2022 15:45:36 +0100
Subject: [PATCH 394/875] drm/amdgpu: WARN when freeing kernel memory during
 suspend
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When buffers are freed during suspend there is no guarantee that
they can be re-allocated during resume.

The PSP subsystem seems to be quite buggy regarding this, so add
a WARN_ON() to point out those bugs.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexdeucher@amd.com>
Tested-by: Guilherme G. Piccoli <gpiccoli@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 2df55cc7e07f6..3393c1a6a0ff1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -422,6 +422,8 @@ void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
 	if (*bo == NULL)
 		return;
 
+	WARN_ON(amdgpu_ttm_adev((*bo)->tbo.bdev)->in_suspend);
+
 	if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
 		if (cpu_addr)
 			amdgpu_bo_kunmap(*bo);
-- 
GitLab


From fe6872adb05e85bde38f2cdec01a0f4cfb826998 Mon Sep 17 00:00:00 2001
From: Yifan Zhang <yifan1.zhang@amd.com>
Date: Thu, 8 Dec 2022 11:55:15 +0800
Subject: [PATCH 395/875] drm/amd/display: Add DCN314 display SG Support

Add display SG support for DCN 3.1.4.

Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 77277d90b6e2f..50c783e19f5ab 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1503,6 +1503,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 		case IP_VERSION(3, 0, 1):
 		case IP_VERSION(3, 1, 2):
 		case IP_VERSION(3, 1, 3):
+		case IP_VERSION(3, 1, 4):
 		case IP_VERSION(3, 1, 5):
 		case IP_VERSION(3, 1, 6):
 			init_data.flags.gpu_vm_support = true;
-- 
GitLab


From f95f51a4c3357eabf74fe14ab7daa5b5c0422b27 Mon Sep 17 00:00:00 2001
From: Felix Kuehling <Felix.Kuehling@amd.com>
Date: Wed, 21 Apr 2021 21:09:54 -0400
Subject: [PATCH 396/875] drm/amdgpu: Add notifier lock for KFD userptrs

Add a per-process MMU notifier lock for processing notifiers from
userptrs. Use that lock to properly synchronize page table updates with
MMU notifiers.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Xiaogang Chen<Xiaogang.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h    |  13 +-
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 212 ++++++++++++------
 drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c       |  12 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h       |   3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c       |  17 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h       |   6 +
 6 files changed, 172 insertions(+), 91 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index f50e3ba4d7a58..589939631ed46 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -29,6 +29,7 @@
 #include <linux/mm.h>
 #include <linux/kthread.h>
 #include <linux/workqueue.h>
+#include <linux/mmu_notifier.h>
 #include <kgd_kfd_interface.h>
 #include <drm/ttm/ttm_execbuf_util.h>
 #include "amdgpu_sync.h"
@@ -65,6 +66,7 @@ struct kgd_mem {
 	struct mutex lock;
 	struct amdgpu_bo *bo;
 	struct dma_buf *dmabuf;
+	struct hmm_range *range;
 	struct list_head attachments;
 	/* protected by amdkfd_process_info.lock */
 	struct ttm_validate_buffer validate_list;
@@ -75,7 +77,7 @@ struct kgd_mem {
 
 	uint32_t alloc_flags;
 
-	atomic_t invalid;
+	uint32_t invalid;
 	struct amdkfd_process_info *process_info;
 
 	struct amdgpu_sync sync;
@@ -131,7 +133,8 @@ struct amdkfd_process_info {
 	struct amdgpu_amdkfd_fence *eviction_fence;
 
 	/* MMU-notifier related fields */
-	atomic_t evicted_bos;
+	struct mutex notifier_lock;
+	uint32_t evicted_bos;
 	struct delayed_work restore_userptr_work;
 	struct pid *pid;
 	bool block_mmu_notifications;
@@ -180,7 +183,8 @@ int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data);
 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm);
 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f);
 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo);
-int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm);
+int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
+				unsigned long cur_seq, struct kgd_mem *mem);
 #else
 static inline
 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
@@ -201,7 +205,8 @@ int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
 }
 
 static inline
-int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm)
+int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
+				unsigned long cur_seq, struct kgd_mem *mem)
 {
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 8782916e64a04..0a854bb8b47e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -964,7 +964,9 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr,
 		 * later stage when it is scheduled by another ioctl called by
 		 * CRIU master process for the target pid for restore.
 		 */
-		atomic_inc(&mem->invalid);
+		mutex_lock(&process_info->notifier_lock);
+		mem->invalid++;
+		mutex_unlock(&process_info->notifier_lock);
 		mutex_unlock(&process_info->lock);
 		return 0;
 	}
@@ -1301,6 +1303,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
 			return -ENOMEM;
 
 		mutex_init(&info->lock);
+		mutex_init(&info->notifier_lock);
 		INIT_LIST_HEAD(&info->vm_list_head);
 		INIT_LIST_HEAD(&info->kfd_bo_list);
 		INIT_LIST_HEAD(&info->userptr_valid_list);
@@ -1317,7 +1320,6 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
 		}
 
 		info->pid = get_task_pid(current->group_leader, PIDTYPE_PID);
-		atomic_set(&info->evicted_bos, 0);
 		INIT_DELAYED_WORK(&info->restore_userptr_work,
 				  amdgpu_amdkfd_restore_userptr_worker);
 
@@ -1372,6 +1374,7 @@ reserve_pd_fail:
 		put_pid(info->pid);
 create_evict_fence_fail:
 		mutex_destroy(&info->lock);
+		mutex_destroy(&info->notifier_lock);
 		kfree(info);
 	}
 	return ret;
@@ -1496,6 +1499,7 @@ void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
 		cancel_delayed_work_sync(&process_info->restore_userptr_work);
 		put_pid(process_info->pid);
 		mutex_destroy(&process_info->lock);
+		mutex_destroy(&process_info->notifier_lock);
 		kfree(process_info);
 	}
 }
@@ -1548,7 +1552,9 @@ int amdgpu_amdkfd_criu_resume(void *p)
 
 	mutex_lock(&pinfo->lock);
 	pr_debug("scheduling work\n");
-	atomic_inc(&pinfo->evicted_bos);
+	mutex_lock(&pinfo->notifier_lock);
+	pinfo->evicted_bos++;
+	mutex_unlock(&pinfo->notifier_lock);
 	if (!READ_ONCE(pinfo->block_mmu_notifications)) {
 		ret = -EINVAL;
 		goto out_unlock;
@@ -1773,8 +1779,13 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
 	list_del(&bo_list_entry->head);
 	mutex_unlock(&process_info->lock);
 
-	/* No more MMU notifiers */
-	amdgpu_hmm_unregister(mem->bo);
+	/* Cleanup user pages and MMU notifiers */
+	if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
+		amdgpu_hmm_unregister(mem->bo);
+		mutex_lock(&process_info->notifier_lock);
+		amdgpu_ttm_tt_discard_user_pages(mem->bo->tbo.ttm, mem->range);
+		mutex_unlock(&process_info->notifier_lock);
+	}
 
 	ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx);
 	if (unlikely(ret))
@@ -1864,6 +1875,16 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
 	 */
 	mutex_lock(&mem->process_info->lock);
 
+	/* Lock notifier lock. If we find an invalid userptr BO, we can be
+	 * sure that the MMU notifier is no longer running
+	 * concurrently and the queues are actually stopped
+	 */
+	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
+		mutex_lock(&mem->process_info->notifier_lock);
+		is_invalid_userptr = !!mem->invalid;
+		mutex_unlock(&mem->process_info->notifier_lock);
+	}
+
 	mutex_lock(&mem->lock);
 
 	domain = mem->domain;
@@ -2241,34 +2262,38 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev,
  *
  * Runs in MMU notifier, may be in RECLAIM_FS context. This means it
  * cannot do any memory allocations, and cannot take any locks that
- * are held elsewhere while allocating memory. Therefore this is as
- * simple as possible, using atomic counters.
+ * are held elsewhere while allocating memory.
  *
  * It doesn't do anything to the BO itself. The real work happens in
  * restore, where we get updated page addresses. This function only
  * ensures that GPU access to the BO is stopped.
  */
-int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem,
-				struct mm_struct *mm)
+int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
+				unsigned long cur_seq, struct kgd_mem *mem)
 {
 	struct amdkfd_process_info *process_info = mem->process_info;
-	int evicted_bos;
 	int r = 0;
 
-	/* Do not process MMU notifications until stage-4 IOCTL is received */
+	/* Do not process MMU notifications during CRIU restore until
+	 * KFD_CRIU_OP_RESUME IOCTL is received
+	 */
 	if (READ_ONCE(process_info->block_mmu_notifications))
 		return 0;
 
-	atomic_inc(&mem->invalid);
-	evicted_bos = atomic_inc_return(&process_info->evicted_bos);
-	if (evicted_bos == 1) {
+	mutex_lock(&process_info->notifier_lock);
+	mmu_interval_set_seq(mni, cur_seq);
+
+	mem->invalid++;
+	if (++process_info->evicted_bos == 1) {
 		/* First eviction, stop the queues */
-		r = kgd2kfd_quiesce_mm(mm, KFD_QUEUE_EVICTION_TRIGGER_USERPTR);
+		r = kgd2kfd_quiesce_mm(mni->mm,
+				       KFD_QUEUE_EVICTION_TRIGGER_USERPTR);
 		if (r)
 			pr_err("Failed to quiesce KFD\n");
 		schedule_delayed_work(&process_info->restore_userptr_work,
 			msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
 	}
+	mutex_unlock(&process_info->notifier_lock);
 
 	return r;
 }
@@ -2285,54 +2310,58 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info,
 	struct kgd_mem *mem, *tmp_mem;
 	struct amdgpu_bo *bo;
 	struct ttm_operation_ctx ctx = { false, false };
-	int invalid, ret;
+	uint32_t invalid;
+	int ret = 0;
 
-	/* Move all invalidated BOs to the userptr_inval_list and
-	 * release their user pages by migration to the CPU domain
-	 */
+	mutex_lock(&process_info->notifier_lock);
+
+	/* Move all invalidated BOs to the userptr_inval_list */
 	list_for_each_entry_safe(mem, tmp_mem,
 				 &process_info->userptr_valid_list,
-				 validate_list.head) {
-		if (!atomic_read(&mem->invalid))
-			continue; /* BO is still valid */
-
-		bo = mem->bo;
-
-		if (amdgpu_bo_reserve(bo, true))
-			return -EAGAIN;
-		amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
-		ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
-		amdgpu_bo_unreserve(bo);
-		if (ret) {
-			pr_err("%s: Failed to invalidate userptr BO\n",
-			       __func__);
-			return -EAGAIN;
-		}
-
-		list_move_tail(&mem->validate_list.head,
-			       &process_info->userptr_inval_list);
-	}
-
-	if (list_empty(&process_info->userptr_inval_list))
-		return 0; /* All evicted userptr BOs were freed */
+				 validate_list.head)
+		if (mem->invalid)
+			list_move_tail(&mem->validate_list.head,
+				       &process_info->userptr_inval_list);
 
 	/* Go through userptr_inval_list and update any invalid user_pages */
 	list_for_each_entry(mem, &process_info->userptr_inval_list,
 			    validate_list.head) {
-		struct hmm_range *range;
-
-		invalid = atomic_read(&mem->invalid);
+		invalid = mem->invalid;
 		if (!invalid)
 			/* BO hasn't been invalidated since the last
-			 * revalidation attempt. Keep its BO list.
+			 * revalidation attempt. Keep its page list.
 			 */
 			continue;
 
 		bo = mem->bo;
 
+		amdgpu_ttm_tt_discard_user_pages(bo->tbo.ttm, mem->range);
+		mem->range = NULL;
+
+		/* BO reservations and getting user pages (hmm_range_fault)
+		 * must happen outside the notifier lock
+		 */
+		mutex_unlock(&process_info->notifier_lock);
+
+		/* Move the BO to system (CPU) domain if necessary to unmap
+		 * and free the SG table
+		 */
+		if (bo->tbo.resource->mem_type != TTM_PL_SYSTEM) {
+			if (amdgpu_bo_reserve(bo, true))
+				return -EAGAIN;
+			amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
+			ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
+			amdgpu_bo_unreserve(bo);
+			if (ret) {
+				pr_err("%s: Failed to invalidate userptr BO\n",
+				       __func__);
+				return -EAGAIN;
+			}
+		}
+
 		/* Get updated user pages */
 		ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages,
-						   &range);
+						   &mem->range);
 		if (ret) {
 			pr_debug("Failed %d to get user pages\n", ret);
 
@@ -2345,30 +2374,32 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info,
 			 */
 			if (ret != -EFAULT)
 				return ret;
-		} else {
 
-			/*
-			 * FIXME: Cannot ignore the return code, must hold
-			 * notifier_lock
-			 */
-			amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range);
+			ret = 0;
 		}
 
+		mutex_lock(&process_info->notifier_lock);
+
 		/* Mark the BO as valid unless it was invalidated
 		 * again concurrently.
 		 */
-		if (atomic_cmpxchg(&mem->invalid, invalid, 0) != invalid)
-			return -EAGAIN;
+		if (mem->invalid != invalid) {
+			ret = -EAGAIN;
+			goto unlock_out;
+		}
+		mem->invalid = 0;
 	}
 
-	return 0;
+unlock_out:
+	mutex_unlock(&process_info->notifier_lock);
+
+	return ret;
 }
 
 /* Validate invalid userptr BOs
  *
- * Validates BOs on the userptr_inval_list, and moves them back to the
- * userptr_valid_list. Also updates GPUVM page tables with new page
- * addresses and waits for the page table updates to complete.
+ * Validates BOs on the userptr_inval_list. Also updates GPUVM page tables
+ * with new page addresses and waits for the page table updates to complete.
  */
 static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
 {
@@ -2439,9 +2470,6 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
 			}
 		}
 
-		list_move_tail(&mem->validate_list.head,
-			       &process_info->userptr_valid_list);
-
 		/* Update mapping. If the BO was not validated
 		 * (because we couldn't get user pages), this will
 		 * clear the page table entries, which will result in
@@ -2457,7 +2485,9 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
 			if (ret) {
 				pr_err("%s: update PTE failed\n", __func__);
 				/* make sure this gets validated again */
-				atomic_inc(&mem->invalid);
+				mutex_lock(&process_info->notifier_lock);
+				mem->invalid++;
+				mutex_unlock(&process_info->notifier_lock);
 				goto unreserve_out;
 			}
 		}
@@ -2477,6 +2507,36 @@ out_no_mem:
 	return ret;
 }
 
+/* Confirm that all user pages are valid while holding the notifier lock
+ *
+ * Moves valid BOs from the userptr_inval_list back to userptr_val_list.
+ */
+static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_info)
+{
+	struct kgd_mem *mem, *tmp_mem;
+	int ret = 0;
+
+	list_for_each_entry_safe(mem, tmp_mem,
+				 &process_info->userptr_inval_list,
+				 validate_list.head) {
+		bool valid = amdgpu_ttm_tt_get_user_pages_done(
+				mem->bo->tbo.ttm, mem->range);
+
+		mem->range = NULL;
+		if (!valid) {
+			WARN(!mem->invalid, "Invalid BO not marked invalid");
+			ret = -EAGAIN;
+			continue;
+		}
+		WARN(mem->invalid, "Valid BO is marked invalid");
+
+		list_move_tail(&mem->validate_list.head,
+			       &process_info->userptr_valid_list);
+	}
+
+	return ret;
+}
+
 /* Worker callback to restore evicted userptr BOs
  *
  * Tries to update and validate all userptr BOs. If successful and no
@@ -2491,9 +2551,11 @@ static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
 			     restore_userptr_work);
 	struct task_struct *usertask;
 	struct mm_struct *mm;
-	int evicted_bos;
+	uint32_t evicted_bos;
 
-	evicted_bos = atomic_read(&process_info->evicted_bos);
+	mutex_lock(&process_info->notifier_lock);
+	evicted_bos = process_info->evicted_bos;
+	mutex_unlock(&process_info->notifier_lock);
 	if (!evicted_bos)
 		return;
 
@@ -2516,9 +2578,6 @@ static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
 	 * and we can just restart the queues.
 	 */
 	if (!list_empty(&process_info->userptr_inval_list)) {
-		if (atomic_read(&process_info->evicted_bos) != evicted_bos)
-			goto unlock_out; /* Concurrent eviction, try again */
-
 		if (validate_invalid_user_pages(process_info))
 			goto unlock_out;
 	}
@@ -2527,10 +2586,17 @@ static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
 	 * be a first eviction that calls quiesce_mm. The eviction
 	 * reference counting inside KFD will handle this case.
 	 */
-	if (atomic_cmpxchg(&process_info->evicted_bos, evicted_bos, 0) !=
-	    evicted_bos)
-		goto unlock_out;
-	evicted_bos = 0;
+	mutex_lock(&process_info->notifier_lock);
+	if (process_info->evicted_bos != evicted_bos)
+		goto unlock_notifier_out;
+
+	if (confirm_valid_user_pages_locked(process_info)) {
+		WARN(1, "User pages unexpectedly invalid");
+		goto unlock_notifier_out;
+	}
+
+	process_info->evicted_bos = evicted_bos = 0;
+
 	if (kgd2kfd_resume_mm(mm)) {
 		pr_err("%s: Failed to resume KFD\n", __func__);
 		/* No recovery from this failure. Probably the CP is
@@ -2538,6 +2604,8 @@ static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
 		 */
 	}
 
+unlock_notifier_out:
+	mutex_unlock(&process_info->notifier_lock);
 unlock_out:
 	mutex_unlock(&process_info->lock);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
index 65715cb395d83..2dadcfe43d03d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
@@ -105,17 +105,11 @@ static bool amdgpu_hmm_invalidate_hsa(struct mmu_interval_notifier *mni,
 				      unsigned long cur_seq)
 {
 	struct amdgpu_bo *bo = container_of(mni, struct amdgpu_bo, notifier);
-	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 
 	if (!mmu_notifier_range_blockable(range))
 		return false;
 
-	mutex_lock(&adev->notifier_lock);
-
-	mmu_interval_set_seq(mni, cur_seq);
-
-	amdgpu_amdkfd_evict_userptr(bo->kfd_bo, bo->notifier.mm);
-	mutex_unlock(&adev->notifier_lock);
+	amdgpu_amdkfd_evict_userptr(mni, cur_seq, bo->kfd_bo);
 
 	return true;
 }
@@ -244,9 +238,9 @@ out_free_range:
 	return r;
 }
 
-int amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range)
+bool amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range)
 {
-	int r;
+	bool r;
 
 	r = mmu_interval_read_retry(hmm_range->notifier,
 				    hmm_range->notifier_seq);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h
index 13ed94d3b01b8..e2edcd010cccb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h
@@ -29,12 +29,13 @@
 #include <linux/rwsem.h>
 #include <linux/workqueue.h>
 #include <linux/interval_tree.h>
+#include <linux/mmu_notifier.h>
 
 int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier,
 			       uint64_t start, uint64_t npages, bool readonly,
 			       void *owner, struct page **pages,
 			       struct hmm_range **phmm_range);
-int amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range);
+bool amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range);
 
 #if defined(CONFIG_HMM_MIRROR)
 int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index b4236572eae1b..f0e4c73094388 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -695,8 +695,19 @@ out_unlock:
 	return r;
 }
 
+/* amdgpu_ttm_tt_discard_user_pages - Discard range and pfn array allocations
+ */
+void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm,
+				      struct hmm_range *range)
+{
+	struct amdgpu_ttm_tt *gtt = (void *)ttm;
+
+	if (gtt && gtt->userptr && range)
+		amdgpu_hmm_range_get_pages_done(range);
+}
+
 /*
- * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
+ * amdgpu_ttm_tt_get_user_pages_done - stop HMM track the CPU page table change
  * Check if the pages backing this ttm range have been invalidated
  *
  * Returns: true if pages are still valid
@@ -714,10 +725,6 @@ bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm,
 
 	WARN_ONCE(!range->hmm_pfns, "No user pages to check\n");
 
-	/*
-	 * FIXME: Must always hold notifier_lock for this, and must
-	 * not ignore the return code.
-	 */
 	return !amdgpu_hmm_range_get_pages_done(range);
 }
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index b4d8ba2789f36..e2cd5894afc9d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -159,6 +159,8 @@ uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);
 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages,
 				 struct hmm_range **range);
+void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm,
+				      struct hmm_range *range);
 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm,
 				       struct hmm_range *range);
 #else
@@ -168,6 +170,10 @@ static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
 {
 	return -EPERM;
 }
+static inline void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm,
+						    struct hmm_range *range)
+{
+}
 static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm,
 						     struct hmm_range *range)
 {
-- 
GitLab


From 592cd24a08763975c75be850a7d4e461bfd353bf Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Fri, 9 Dec 2022 16:05:12 +0800
Subject: [PATCH 397/875] drm/amd/pm: add missing SMU13.0.0 mm_dpm feature
 mapping

Without this, the pp_dpm_vclk and pp_dpm_dclk outputs are not with
correct data.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.0.x
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 87d7c66e49ef2..21d89c3302f1e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -210,6 +210,8 @@ static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] =
 	FEA_MAP(MEM_TEMP_READ),
 	FEA_MAP(ATHUB_MMHUB_PG),
 	FEA_MAP(SOC_PCC),
+	[SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
+	[SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
 };
 
 static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {
-- 
GitLab


From e0607c10ebf551a654c3577fc74b4bf5533e1cea Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Fri, 9 Dec 2022 16:09:58 +0800
Subject: [PATCH 398/875] drm/amd/pm: add missing SMU13.0.7 mm_dpm feature
 mapping

Without this, the pp_dpm_vclk and pp_dpm_dclk outputs are not with
correct data.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.0.x
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index c3c9ef523e59d..c270f94a1b86f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -189,6 +189,8 @@ static struct cmn2asic_mapping smu_v13_0_7_feature_mask_map[SMU_FEATURE_COUNT] =
 	FEA_MAP(MEM_TEMP_READ),
 	FEA_MAP(ATHUB_MMHUB_PG),
 	FEA_MAP(SOC_PCC),
+	[SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
+	[SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
 };
 
 static struct cmn2asic_mapping smu_v13_0_7_table_map[SMU_TABLE_COUNT] = {
-- 
GitLab


From 56b0989e2939811c11ed9c449ff84cf85878ffe3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
Date: Fri, 25 Nov 2022 16:04:25 +0100
Subject: [PATCH 399/875] drm/amdgpu: fix GDS/GWS/OA switch handling
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Bas pointed out that this isn't working as expected and could cause
crashes. Fix the handling by storing the marker that a switch is needed
inside the job instead.

Reported-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 42 +++++++++++++++----
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.h |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 54 +++++++++----------------
 3 files changed, 54 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index 2a9a2593dc183..01878145a5867 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -165,6 +165,26 @@ bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev,
 		atomic_read(&adev->gpu_reset_counter);
 }
 
+/* Check if we need to switch to another set of resources */
+static bool amdgpu_vmid_gds_switch_needed(struct amdgpu_vmid *id,
+					  struct amdgpu_job *job)
+{
+	return id->gds_base != job->gds_base ||
+		id->gds_size != job->gds_size ||
+		id->gws_base != job->gws_base ||
+		id->gws_size != job->gws_size ||
+		id->oa_base != job->oa_base ||
+		id->oa_size != job->oa_size;
+}
+
+/* Check if the id is compatible with the job */
+static bool amdgpu_vmid_compatible(struct amdgpu_vmid *id,
+				   struct amdgpu_job *job)
+{
+	return  id->pd_gpu_addr == job->vm_pd_addr &&
+		!amdgpu_vmid_gds_switch_needed(id, job);
+}
+
 /**
  * amdgpu_vmid_grab_idle - grab idle VMID
  *
@@ -265,7 +285,7 @@ static int amdgpu_vmid_grab_reserved(struct amdgpu_vm *vm,
 
 	*id = vm->reserved_vmid[vmhub];
 	if ((*id)->owner != vm->immediate.fence_context ||
-	    (*id)->pd_gpu_addr != job->vm_pd_addr ||
+	    !amdgpu_vmid_compatible(*id, job) ||
 	    (*id)->flushed_updates < updates ||
 	    !(*id)->last_flush ||
 	    ((*id)->last_flush->context != fence_context &&
@@ -294,7 +314,6 @@ static int amdgpu_vmid_grab_reserved(struct amdgpu_vm *vm,
 	if (r)
 		return r;
 
-	(*id)->flushed_updates = updates;
 	job->vm_needs_flush = needs_flush;
 	return 0;
 }
@@ -333,7 +352,7 @@ static int amdgpu_vmid_grab_used(struct amdgpu_vm *vm,
 		if ((*id)->owner != vm->immediate.fence_context)
 			continue;
 
-		if ((*id)->pd_gpu_addr != job->vm_pd_addr)
+		if (!amdgpu_vmid_compatible(*id, job))
 			continue;
 
 		if (!(*id)->last_flush ||
@@ -355,7 +374,6 @@ static int amdgpu_vmid_grab_used(struct amdgpu_vm *vm,
 		if (r)
 			return r;
 
-		(*id)->flushed_updates = updates;
 		job->vm_needs_flush |= needs_flush;
 		return 0;
 	}
@@ -408,22 +426,30 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 			if (r)
 				goto error;
 
-			id->flushed_updates = amdgpu_vm_tlb_seq(vm);
 			job->vm_needs_flush = true;
 		}
 
 		list_move_tail(&id->list, &id_mgr->ids_lru);
 	}
 
-	id->pd_gpu_addr = job->vm_pd_addr;
-	id->owner = vm->immediate.fence_context;
-
+	job->gds_switch_needed = amdgpu_vmid_gds_switch_needed(id, job);
 	if (job->vm_needs_flush) {
+		id->flushed_updates = amdgpu_vm_tlb_seq(vm);
 		dma_fence_put(id->last_flush);
 		id->last_flush = NULL;
 	}
 	job->vmid = id - id_mgr->ids;
 	job->pasid = vm->pasid;
+
+	id->gds_base = job->gds_base;
+	id->gds_size = job->gds_size;
+	id->gws_base = job->gws_base;
+	id->gws_size = job->gws_size;
+	id->oa_base = job->oa_base;
+	id->oa_size = job->oa_size;
+	id->pd_gpu_addr = job->vm_pd_addr;
+	id->owner = vm->immediate.fence_context;
+
 	trace_amdgpu_vm_grab_id(vm, ring, job);
 
 error:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
index a372802ea4e09..02e85b040bafa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
@@ -53,6 +53,7 @@ struct amdgpu_job {
 	uint32_t		preamble_status;
 	uint32_t                preemption_status;
 	bool                    vm_needs_flush;
+	bool			gds_switch_needed;
 	uint64_t		vm_pd_addr;
 	unsigned		vmid;
 	unsigned		pasid;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index c05cff979004c..245c66ea10e73 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -484,25 +484,20 @@ bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
 	struct amdgpu_device *adev = ring->adev;
 	unsigned vmhub = ring->funcs->vmhub;
 	struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
-	struct amdgpu_vmid *id;
-	bool gds_switch_needed;
-	bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
 
 	if (job->vmid == 0)
 		return false;
-	id = &id_mgr->ids[job->vmid];
-	gds_switch_needed = ring->funcs->emit_gds_switch && (
-		id->gds_base != job->gds_base ||
-		id->gds_size != job->gds_size ||
-		id->gws_base != job->gws_base ||
-		id->gws_size != job->gws_size ||
-		id->oa_base != job->oa_base ||
-		id->oa_size != job->oa_size);
-
-	if (amdgpu_vmid_had_gpu_reset(adev, id))
+
+	if (job->vm_needs_flush || ring->has_compute_vm_bug)
+		return true;
+
+	if (ring->funcs->emit_gds_switch && job->gds_switch_needed)
 		return true;
 
-	return vm_flush_needed || gds_switch_needed;
+	if (amdgpu_vmid_had_gpu_reset(adev, &id_mgr->ids[job->vmid]))
+		return true;
+
+	return false;
 }
 
 /**
@@ -524,13 +519,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
 	unsigned vmhub = ring->funcs->vmhub;
 	struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
 	struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
-	bool gds_switch_needed = ring->funcs->emit_gds_switch && (
-		id->gds_base != job->gds_base ||
-		id->gds_size != job->gds_size ||
-		id->gws_base != job->gws_base ||
-		id->gws_size != job->gws_size ||
-		id->oa_base != job->oa_base ||
-		id->oa_size != job->oa_size);
+	bool gds_switch_needed = ring->funcs->emit_gds_switch &&
+		job->gds_switch_needed;
 	bool vm_flush_needed = job->vm_needs_flush;
 	struct dma_fence *fence = NULL;
 	bool pasid_mapping_needed = false;
@@ -577,6 +567,14 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
 	if (pasid_mapping_needed)
 		amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
 
+	if (!ring->is_mes_queue && ring->funcs->emit_gds_switch &&
+	    gds_switch_needed) {
+		amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
+					    job->gds_size, job->gws_base,
+					    job->gws_size, job->oa_base,
+					    job->oa_size);
+	}
+
 	if (vm_flush_needed || pasid_mapping_needed) {
 		r = amdgpu_fence_emit(ring, &fence, NULL, 0);
 		if (r)
@@ -601,20 +599,6 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
 	}
 	dma_fence_put(fence);
 
-	if (!ring->is_mes_queue && ring->funcs->emit_gds_switch &&
-	    gds_switch_needed) {
-		id->gds_base = job->gds_base;
-		id->gds_size = job->gds_size;
-		id->gws_base = job->gws_base;
-		id->gws_size = job->gws_size;
-		id->oa_base = job->oa_base;
-		id->oa_size = job->oa_size;
-		amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
-					    job->gds_size, job->gws_base,
-					    job->gws_size, job->oa_base,
-					    job->oa_size);
-	}
-
 	if (ring->funcs->patch_cond_exec)
 		amdgpu_ring_patch_cond_exec(ring, patch_offset);
 
-- 
GitLab


From 5f3c40e9e2460c42f5bf6c51b1e393d7159241c3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
Date: Fri, 25 Nov 2022 16:42:45 +0100
Subject: [PATCH 400/875] drm/amdgpu: cleanup SPM support a bit
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This should probably not access job->vm and also emit the SPM switch
under the conditional execute.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 9 +++++----
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index 01878145a5867..6949dfec75d53 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -315,6 +315,7 @@ static int amdgpu_vmid_grab_reserved(struct amdgpu_vm *vm,
 		return r;
 
 	job->vm_needs_flush = needs_flush;
+	job->spm_update_needed = true;
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
index 02e85b040bafa..52f2e313ea17f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
@@ -54,6 +54,7 @@ struct amdgpu_job {
 	uint32_t                preemption_status;
 	bool                    vm_needs_flush;
 	bool			gds_switch_needed;
+	bool			spm_update_needed;
 	uint64_t		vm_pd_addr;
 	unsigned		vmid;
 	unsigned		pasid;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 245c66ea10e73..a05cce3f3170f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -519,22 +519,20 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
 	unsigned vmhub = ring->funcs->vmhub;
 	struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
 	struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
+	bool spm_update_needed = job->spm_update_needed;
 	bool gds_switch_needed = ring->funcs->emit_gds_switch &&
 		job->gds_switch_needed;
 	bool vm_flush_needed = job->vm_needs_flush;
 	struct dma_fence *fence = NULL;
 	bool pasid_mapping_needed = false;
 	unsigned patch_offset = 0;
-	bool update_spm_vmid_needed = (job->vm && (job->vm->reserved_vmid[vmhub] != NULL));
 	int r;
 
-	if (update_spm_vmid_needed && adev->gfx.rlc.funcs->update_spm_vmid)
-		adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid);
-
 	if (amdgpu_vmid_had_gpu_reset(adev, id)) {
 		gds_switch_needed = true;
 		vm_flush_needed = true;
 		pasid_mapping_needed = true;
+		spm_update_needed = true;
 	}
 
 	mutex_lock(&id_mgr->lock);
@@ -567,6 +565,9 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
 	if (pasid_mapping_needed)
 		amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
 
+	if (spm_update_needed && adev->gfx.rlc.funcs->update_spm_vmid)
+		adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid);
+
 	if (!ring->is_mes_queue && ring->funcs->emit_gds_switch &&
 	    gds_switch_needed) {
 		amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
-- 
GitLab


From 053499f7b45dc56758240615569b349fe9e2fc8d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
Date: Fri, 25 Nov 2022 16:45:09 +0100
Subject: [PATCH 401/875] drm/amdgpu: stop waiting for the VM during unreserve
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This is completely pointless since the VMID always stays allocated until
the VM is idle.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 16 ----------------
 1 file changed, 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index a05cce3f3170f..dc379dc22c77b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2368,7 +2368,6 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 	union drm_amdgpu_vm *args = data;
 	struct amdgpu_device *adev = drm_to_adev(dev);
 	struct amdgpu_fpriv *fpriv = filp->driver_priv;
-	long timeout = msecs_to_jiffies(2000);
 	int r;
 
 	switch (args->in.op) {
@@ -2380,21 +2379,6 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 			return r;
 		break;
 	case AMDGPU_VM_OP_UNRESERVE_VMID:
-		if (amdgpu_sriov_runtime(adev))
-			timeout = 8 * timeout;
-
-		/* Wait vm idle to make sure the vmid set in SPM_VMID is
-		 * not referenced anymore.
-		 */
-		r = amdgpu_bo_reserve(fpriv->vm.root.bo, true);
-		if (r)
-			return r;
-
-		r = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
-		if (r < 0)
-			return r;
-
-		amdgpu_bo_unreserve(fpriv->vm.root.bo);
 		amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
 		break;
 	default:
-- 
GitLab


From e44a0fe630c58b0a87d8281f5c1077a3479e5fce Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
Date: Fri, 25 Nov 2022 17:04:25 +0100
Subject: [PATCH 402/875] drm/amdgpu: rework reserved VMID handling
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Instead of reserving a VMID for a single process allow that many
processes use the reserved ID. This allows for proper isolation
between the processes.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 45 ++++++++++++-------------
 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h |  3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h  |  6 +---
 3 files changed, 24 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index 6949dfec75d53..fcb711a11a5b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -278,12 +278,13 @@ static int amdgpu_vmid_grab_reserved(struct amdgpu_vm *vm,
 {
 	struct amdgpu_device *adev = ring->adev;
 	unsigned vmhub = ring->funcs->vmhub;
+	struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
 	uint64_t fence_context = adev->fence_context + ring->idx;
 	bool needs_flush = vm->use_cpu_for_update;
 	uint64_t updates = amdgpu_vm_tlb_seq(vm);
 	int r;
 
-	*id = vm->reserved_vmid[vmhub];
+	*id = id_mgr->reserved;
 	if ((*id)->owner != vm->immediate.fence_context ||
 	    !amdgpu_vmid_compatible(*id, job) ||
 	    (*id)->flushed_updates < updates ||
@@ -462,31 +463,27 @@ int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
 			       struct amdgpu_vm *vm,
 			       unsigned vmhub)
 {
-	struct amdgpu_vmid_mgr *id_mgr;
-	struct amdgpu_vmid *idle;
-	int r = 0;
+	struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
 
-	id_mgr = &adev->vm_manager.id_mgr[vmhub];
 	mutex_lock(&id_mgr->lock);
 	if (vm->reserved_vmid[vmhub])
 		goto unlock;
-	if (atomic_inc_return(&id_mgr->reserved_vmid_num) >
-	    AMDGPU_VM_MAX_RESERVED_VMID) {
-		DRM_ERROR("Over limitation of reserved vmid\n");
-		atomic_dec(&id_mgr->reserved_vmid_num);
-		r = -EINVAL;
-		goto unlock;
+
+	++id_mgr->reserved_use_count;
+	if (!id_mgr->reserved) {
+		struct amdgpu_vmid *id;
+
+		id = list_first_entry(&id_mgr->ids_lru, struct amdgpu_vmid,
+				      list);
+		/* Remove from normal round robin handling */
+		list_del_init(&id->list);
+		id_mgr->reserved = id;
 	}
-	/* Select the first entry VMID */
-	idle = list_first_entry(&id_mgr->ids_lru, struct amdgpu_vmid, list);
-	list_del_init(&idle->list);
-	vm->reserved_vmid[vmhub] = idle;
-	mutex_unlock(&id_mgr->lock);
+	vm->reserved_vmid[vmhub] = true;
 
-	return 0;
 unlock:
 	mutex_unlock(&id_mgr->lock);
-	return r;
+	return 0;
 }
 
 void amdgpu_vmid_free_reserved(struct amdgpu_device *adev,
@@ -496,12 +493,12 @@ void amdgpu_vmid_free_reserved(struct amdgpu_device *adev,
 	struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
 
 	mutex_lock(&id_mgr->lock);
-	if (vm->reserved_vmid[vmhub]) {
-		list_add(&vm->reserved_vmid[vmhub]->list,
-			&id_mgr->ids_lru);
-		vm->reserved_vmid[vmhub] = NULL;
-		atomic_dec(&id_mgr->reserved_vmid_num);
+	if (vm->reserved_vmid[vmhub] &&
+	    !--id_mgr->reserved_use_count) {
+		/* give the reserved ID back to normal round robin */
+		list_add(&id_mgr->reserved->list, &id_mgr->ids_lru);
 	}
+	vm->reserved_vmid[vmhub] = false;
 	mutex_unlock(&id_mgr->lock);
 }
 
@@ -568,7 +565,7 @@ void amdgpu_vmid_mgr_init(struct amdgpu_device *adev)
 
 		mutex_init(&id_mgr->lock);
 		INIT_LIST_HEAD(&id_mgr->ids_lru);
-		atomic_set(&id_mgr->reserved_vmid_num, 0);
+		id_mgr->reserved_use_count = 0;
 
 		/* manage only VMIDs not used by KFD */
 		id_mgr->num_ids = adev->vm_manager.first_kfd_vmid;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
index 57efe61dceedc..d1cc09b45da4a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
@@ -67,7 +67,8 @@ struct amdgpu_vmid_mgr {
 	unsigned		num_ids;
 	struct list_head	ids_lru;
 	struct amdgpu_vmid	ids[AMDGPU_NUM_VMID];
-	atomic_t		reserved_vmid_num;
+	struct amdgpu_vmid	*reserved;
+	unsigned int		reserved_use_count;
 };
 
 int amdgpu_pasid_alloc(unsigned int bits);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 6546e786bf008..094bb48073031 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -119,9 +119,6 @@ struct amdgpu_bo_vm;
 /* Reserve 2MB at top/bottom of address space for kernel use */
 #define AMDGPU_VA_RESERVED_SIZE			(2ULL << 20)
 
-/* max vmids dedicated for process */
-#define AMDGPU_VM_MAX_RESERVED_VMID	1
-
 /* See vm_update_mode */
 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)
@@ -298,8 +295,7 @@ struct amdgpu_vm {
 	struct dma_fence	*last_unlocked;
 
 	unsigned int		pasid;
-	/* dedicated to vm */
-	struct amdgpu_vmid	*reserved_vmid[AMDGPU_MAX_VMHUBS];
+	bool			reserved_vmid[AMDGPU_MAX_VMHUBS];
 
 	/* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */
 	bool					use_cpu_for_update;
-- 
GitLab


From ea011ee10231f5fa6cbb415007048ca0bb948baf Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Fri, 2 Dec 2022 17:47:22 +0000
Subject: [PATCH 403/875] io_uring: protect cq_timeouts with timeout_lock

Read cq_timeouts in io_flush_timeouts() only after taking the
timeout_lock, as it's protected by it. There are many places where we
also grab ->completion_lock, but for instance io_timeout_fn() doesn't
and still modifies cq_timeouts.

Cc: stable@vger.kernel.org
Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
Link: https://lore.kernel.org/r/9c79544dd6cf5c4018cb1bab99cf481a93ea46ef.1670002973.git.asml.silence@gmail.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 io_uring/timeout.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/io_uring/timeout.c b/io_uring/timeout.c
index 5b4bc93fd6e07..4c6a5666541cf 100644
--- a/io_uring/timeout.c
+++ b/io_uring/timeout.c
@@ -72,10 +72,12 @@ static bool io_kill_timeout(struct io_kiocb *req, int status)
 __cold void io_flush_timeouts(struct io_ring_ctx *ctx)
 	__must_hold(&ctx->completion_lock)
 {
-	u32 seq = ctx->cached_cq_tail - atomic_read(&ctx->cq_timeouts);
+	u32 seq;
 	struct io_timeout *timeout, *tmp;
 
 	spin_lock_irq(&ctx->timeout_lock);
+	seq = ctx->cached_cq_tail - atomic_read(&ctx->cq_timeouts);
+
 	list_for_each_entry_safe(timeout, tmp, &ctx->timeout_list, list) {
 		struct io_kiocb *req = cmd_to_io_kiocb(timeout);
 		u32 events_needed, events_got;
-- 
GitLab


From 6971253f078766543c716db708ba2c787826690d Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Fri, 2 Dec 2022 17:47:23 +0000
Subject: [PATCH 404/875] io_uring: revise completion_lock locking

io_kill_timeouts() doesn't post any events but queues everything to
task_work. Locking there is needed for protecting linked requests
traversing, we should grab completion_lock directly instead of using
io_cq_[un]lock helpers. Same goes for __io_req_find_next_prep().

Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
Link: https://lore.kernel.org/r/88e75d481a65dc295cb59722bb1cf76402d1c06b.1670002973.git.asml.silence@gmail.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 io_uring/io_uring.c | 16 ++++++++++++++--
 io_uring/io_uring.h | 11 -----------
 io_uring/timeout.c  |  8 ++++++--
 3 files changed, 20 insertions(+), 15 deletions(-)

diff --git a/io_uring/io_uring.c b/io_uring/io_uring.c
index b521186efa5c7..698c54f951eaf 100644
--- a/io_uring/io_uring.c
+++ b/io_uring/io_uring.c
@@ -597,6 +597,18 @@ static inline void __io_cq_unlock(struct io_ring_ctx *ctx)
 		spin_unlock(&ctx->completion_lock);
 }
 
+static inline void io_cq_lock(struct io_ring_ctx *ctx)
+	__acquires(ctx->completion_lock)
+{
+	spin_lock(&ctx->completion_lock);
+}
+
+static inline void io_cq_unlock(struct io_ring_ctx *ctx)
+	__releases(ctx->completion_lock)
+{
+	spin_unlock(&ctx->completion_lock);
+}
+
 /* keep it inlined for io_submit_flush_completions() */
 static inline void __io_cq_unlock_post(struct io_ring_ctx *ctx)
 	__releases(ctx->completion_lock)
@@ -1074,9 +1086,9 @@ static void __io_req_find_next_prep(struct io_kiocb *req)
 {
 	struct io_ring_ctx *ctx = req->ctx;
 
-	io_cq_lock(ctx);
+	spin_lock(&ctx->completion_lock);
 	io_disarm_next(req);
-	io_cq_unlock_post(ctx);
+	spin_unlock(&ctx->completion_lock);
 }
 
 static inline struct io_kiocb *io_req_find_next(struct io_kiocb *req)
diff --git a/io_uring/io_uring.h b/io_uring/io_uring.h
index 1b2f0b2cc888c..c117e029c8dcc 100644
--- a/io_uring/io_uring.h
+++ b/io_uring/io_uring.h
@@ -87,17 +87,6 @@ static inline void io_req_task_work_add(struct io_kiocb *req)
 #define io_for_each_link(pos, head) \
 	for (pos = (head); pos; pos = pos->link)
 
-static inline void io_cq_lock(struct io_ring_ctx *ctx)
-	__acquires(ctx->completion_lock)
-{
-	spin_lock(&ctx->completion_lock);
-}
-
-static inline void io_cq_unlock(struct io_ring_ctx *ctx)
-{
-	spin_unlock(&ctx->completion_lock);
-}
-
 void io_cq_unlock_post(struct io_ring_ctx *ctx);
 
 static inline struct io_uring_cqe *io_get_cqe_overflow(struct io_ring_ctx *ctx,
diff --git a/io_uring/timeout.c b/io_uring/timeout.c
index 4c6a5666541cf..eae005b2d1d21 100644
--- a/io_uring/timeout.c
+++ b/io_uring/timeout.c
@@ -624,7 +624,11 @@ __cold bool io_kill_timeouts(struct io_ring_ctx *ctx, struct task_struct *tsk,
 	struct io_timeout *timeout, *tmp;
 	int canceled = 0;
 
-	io_cq_lock(ctx);
+	/*
+	 * completion_lock is needed for io_match_task(). Take it before
+	 * timeout_lockfirst to keep locking ordering.
+	 */
+	spin_lock(&ctx->completion_lock);
 	spin_lock_irq(&ctx->timeout_lock);
 	list_for_each_entry_safe(timeout, tmp, &ctx->timeout_list, list) {
 		struct io_kiocb *req = cmd_to_io_kiocb(timeout);
@@ -634,6 +638,6 @@ __cold bool io_kill_timeouts(struct io_ring_ctx *ctx, struct task_struct *tsk,
 			canceled++;
 	}
 	spin_unlock_irq(&ctx->timeout_lock);
-	io_cq_unlock_post(ctx);
+	spin_unlock(&ctx->completion_lock);
 	return canceled != 0;
 }
-- 
GitLab


From e5f30f6fb29a0b8fa7ca784e44571a610b949b04 Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Fri, 2 Dec 2022 17:47:24 +0000
Subject: [PATCH 405/875] io_uring: ease timeout flush locking requirements

We don't need completion_lock for timeout flushing, don't take it.

Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
Link: https://lore.kernel.org/r/1e3dc657975ac445b80e7bdc40050db783a5935a.1670002973.git.asml.silence@gmail.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 io_uring/io_uring.c | 9 ++++-----
 io_uring/timeout.c  | 2 --
 2 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/io_uring/io_uring.c b/io_uring/io_uring.c
index 698c54f951eaf..fc64072c53eb3 100644
--- a/io_uring/io_uring.c
+++ b/io_uring/io_uring.c
@@ -572,12 +572,11 @@ static void io_eventfd_flush_signal(struct io_ring_ctx *ctx)
 
 void __io_commit_cqring_flush(struct io_ring_ctx *ctx)
 {
-	if (ctx->off_timeout_used || ctx->drain_active) {
+	if (ctx->off_timeout_used)
+		io_flush_timeouts(ctx);
+	if (ctx->drain_active) {
 		spin_lock(&ctx->completion_lock);
-		if (ctx->off_timeout_used)
-			io_flush_timeouts(ctx);
-		if (ctx->drain_active)
-			io_queue_deferred(ctx);
+		io_queue_deferred(ctx);
 		spin_unlock(&ctx->completion_lock);
 	}
 	if (ctx->has_evfd)
diff --git a/io_uring/timeout.c b/io_uring/timeout.c
index eae005b2d1d21..826a51bca3e49 100644
--- a/io_uring/timeout.c
+++ b/io_uring/timeout.c
@@ -50,7 +50,6 @@ static inline void io_put_req(struct io_kiocb *req)
 }
 
 static bool io_kill_timeout(struct io_kiocb *req, int status)
-	__must_hold(&req->ctx->completion_lock)
 	__must_hold(&req->ctx->timeout_lock)
 {
 	struct io_timeout_data *io = req->async_data;
@@ -70,7 +69,6 @@ static bool io_kill_timeout(struct io_kiocb *req, int status)
 }
 
 __cold void io_flush_timeouts(struct io_ring_ctx *ctx)
-	__must_hold(&ctx->completion_lock)
 {
 	u32 seq;
 	struct io_timeout *timeout, *tmp;
-- 
GitLab


From 64dc8c732f5c2b406cc752e6aaa1bd5471159cab Mon Sep 17 00:00:00 2001
From: Yu Kuai <yukuai3@huawei.com>
Date: Wed, 14 Dec 2022 11:04:30 +0800
Subject: [PATCH 406/875] block, bfq: fix possible uaf for 'bfqq->bic'
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Our test report a uaf for 'bfqq->bic' in 5.10:

==================================================================
BUG: KASAN: use-after-free in bfq_select_queue+0x378/0xa30

CPU: 6 PID: 2318352 Comm: fsstress Kdump: loaded Not tainted 5.10.0-60.18.0.50.h602.kasan.eulerosv2r11.x86_64 #1
Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.12.1-0-ga5cab58-20220320_160524-szxrtosci10000 04/01/2014
Call Trace:
 bfq_select_queue+0x378/0xa30
 bfq_dispatch_request+0xe8/0x130
 blk_mq_do_dispatch_sched+0x62/0xb0
 __blk_mq_sched_dispatch_requests+0x215/0x2a0
 blk_mq_sched_dispatch_requests+0x8f/0xd0
 __blk_mq_run_hw_queue+0x98/0x180
 __blk_mq_delay_run_hw_queue+0x22b/0x240
 blk_mq_run_hw_queue+0xe3/0x190
 blk_mq_sched_insert_requests+0x107/0x200
 blk_mq_flush_plug_list+0x26e/0x3c0
 blk_finish_plug+0x63/0x90
 __iomap_dio_rw+0x7b5/0x910
 iomap_dio_rw+0x36/0x80
 ext4_dio_read_iter+0x146/0x190 [ext4]
 ext4_file_read_iter+0x1e2/0x230 [ext4]
 new_sync_read+0x29f/0x400
 vfs_read+0x24e/0x2d0
 ksys_read+0xd5/0x1b0
 do_syscall_64+0x33/0x40
 entry_SYSCALL_64_after_hwframe+0x61/0xc6

Commit 3bc5e683c67d ("bfq: Split shared queues on move between cgroups")
changes that move process to a new cgroup will allocate a new bfqq to
use, however, the old bfqq and new bfqq can point to the same bic:

1) Initial state, two process with io in the same cgroup.

Process 1       Process 2
 (BIC1)          (BIC2)
  |  Λ            |  Λ
  |  |            |  |
  V  |            V  |
  bfqq1           bfqq2

2) bfqq1 is merged to bfqq2.

Process 1       Process 2
 (BIC1)          (BIC2)
  |               |
   \-------------\|
                  V
  bfqq1           bfqq2(coop)

3) Process 1 exit, then issue new io(denoce IOA) from Process 2.

 (BIC2)
  |  Λ
  |  |
  V  |
  bfqq2(coop)

4) Before IOA is completed, move Process 2 to another cgroup and issue io.

Process 2
 (BIC2)
   Λ
   |\--------------\
   |                V
  bfqq2           bfqq3

Now that BIC2 points to bfqq3, while bfqq2 and bfqq3 both point to BIC2.
If all the requests are completed, and Process 2 exit, BIC2 will be
freed while there is no guarantee that bfqq2 will be freed before BIC2.

Fix the problem by clearing bfqq->bic while bfqq is detached from bic.

Fixes: 3bc5e683c67d ("bfq: Split shared queues on move between cgroups")
Suggested-by: Jan Kara <jack@suse.cz>
Signed-off-by: Yu Kuai <yukuai3@huawei.com>
Reviewed-by: Jan Kara <jack@suse.cz>
Link: https://lore.kernel.org/r/20221214030430.3304151-1-yukuai1@huaweicloud.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 block/bfq-iosched.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/block/bfq-iosched.c b/block/bfq-iosched.c
index a72304c728fce..b111a7b8dca6a 100644
--- a/block/bfq-iosched.c
+++ b/block/bfq-iosched.c
@@ -386,6 +386,12 @@ static void bfq_put_stable_ref(struct bfq_queue *bfqq);
 
 void bic_set_bfqq(struct bfq_io_cq *bic, struct bfq_queue *bfqq, bool is_sync)
 {
+	struct bfq_queue *old_bfqq = bic->bfqq[is_sync];
+
+	/* Clear bic pointer if bfqq is detached from this bic */
+	if (old_bfqq && old_bfqq->bic == bic)
+		old_bfqq->bic = NULL;
+
 	/*
 	 * If bfqq != NULL, then a non-stable queue merge between
 	 * bic->bfqq and bfqq is happening here. This causes troubles
@@ -5311,7 +5317,6 @@ static void bfq_exit_icq_bfqq(struct bfq_io_cq *bic, bool is_sync)
 		unsigned long flags;
 
 		spin_lock_irqsave(&bfqd->lock, flags);
-		bfqq->bic = NULL;
 		bfq_exit_bfqq(bfqd, bfqq);
 		bic_set_bfqq(bic, NULL, is_sync);
 		spin_unlock_irqrestore(&bfqd->lock, flags);
-- 
GitLab


From 452af7dc59033a76372d51a24682503377872b11 Mon Sep 17 00:00:00 2001
From: Yu Kuai <yukuai3@huawei.com>
Date: Wed, 14 Dec 2022 11:31:54 +0800
Subject: [PATCH 407/875] block, bfq: don't return bfqg from
 __bfq_bic_change_cgroup()

The return value is not used, hence remove it.

Signed-off-by: Yu Kuai <yukuai3@huawei.com>
Reviewed-by: Jan Kara <jack@suse.cz>
Link: https://lore.kernel.org/r/20221214033155.3455754-2-yukuai1@huaweicloud.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 block/bfq-cgroup.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/block/bfq-cgroup.c b/block/bfq-cgroup.c
index 627476bc64957..23dc355a106d1 100644
--- a/block/bfq-cgroup.c
+++ b/block/bfq-cgroup.c
@@ -724,9 +724,9 @@ void bfq_bfqq_move(struct bfq_data *bfqd, struct bfq_queue *bfqq,
  * sure that the reference to cgroup is valid across the call (see
  * comments in bfq_bic_update_cgroup on this issue)
  */
-static void *__bfq_bic_change_cgroup(struct bfq_data *bfqd,
-				     struct bfq_io_cq *bic,
-				     struct bfq_group *bfqg)
+static void __bfq_bic_change_cgroup(struct bfq_data *bfqd,
+				    struct bfq_io_cq *bic,
+				    struct bfq_group *bfqg)
 {
 	struct bfq_queue *async_bfqq = bic_to_bfqq(bic, 0);
 	struct bfq_queue *sync_bfqq = bic_to_bfqq(bic, 1);
@@ -776,8 +776,6 @@ static void *__bfq_bic_change_cgroup(struct bfq_data *bfqd,
 			}
 		}
 	}
-
-	return bfqg;
 }
 
 void bfq_bic_update_cgroup(struct bfq_io_cq *bic, struct bio *bio)
-- 
GitLab


From 337366e02b370d2800110fbc99940f6ddddcbdfa Mon Sep 17 00:00:00 2001
From: Yu Kuai <yukuai3@huawei.com>
Date: Wed, 14 Dec 2022 11:31:55 +0800
Subject: [PATCH 408/875] block, bfq: replace 0/1 with false/true in bic apis

Just to make the code a litter cleaner, there are no functional changes.

Signed-off-by: Yu Kuai <yukuai3@huawei.com>
Reviewed-by: Jan Kara <jack@suse.cz>
Link: https://lore.kernel.org/r/20221214033155.3455754-3-yukuai1@huaweicloud.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 block/bfq-cgroup.c  | 8 ++++----
 block/bfq-iosched.c | 4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/block/bfq-cgroup.c b/block/bfq-cgroup.c
index 23dc355a106d1..1b2829e99dad0 100644
--- a/block/bfq-cgroup.c
+++ b/block/bfq-cgroup.c
@@ -728,15 +728,15 @@ static void __bfq_bic_change_cgroup(struct bfq_data *bfqd,
 				    struct bfq_io_cq *bic,
 				    struct bfq_group *bfqg)
 {
-	struct bfq_queue *async_bfqq = bic_to_bfqq(bic, 0);
-	struct bfq_queue *sync_bfqq = bic_to_bfqq(bic, 1);
+	struct bfq_queue *async_bfqq = bic_to_bfqq(bic, false);
+	struct bfq_queue *sync_bfqq = bic_to_bfqq(bic, true);
 	struct bfq_entity *entity;
 
 	if (async_bfqq) {
 		entity = &async_bfqq->entity;
 
 		if (entity->sched_data != &bfqg->sched_data) {
-			bic_set_bfqq(bic, NULL, 0);
+			bic_set_bfqq(bic, NULL, false);
 			bfq_release_process_ref(bfqd, async_bfqq);
 		}
 	}
@@ -772,7 +772,7 @@ static void __bfq_bic_change_cgroup(struct bfq_data *bfqd,
 				 */
 				bfq_put_cooperator(sync_bfqq);
 				bfq_release_process_ref(bfqd, sync_bfqq);
-				bic_set_bfqq(bic, NULL, 1);
+				bic_set_bfqq(bic, NULL, true);
 			}
 		}
 	}
diff --git a/block/bfq-iosched.c b/block/bfq-iosched.c
index b111a7b8dca6a..dc576b90ddfe7 100644
--- a/block/bfq-iosched.c
+++ b/block/bfq-iosched.c
@@ -3114,7 +3114,7 @@ bfq_merge_bfqqs(struct bfq_data *bfqd, struct bfq_io_cq *bic,
 	/*
 	 * Merge queues (that is, let bic redirect its requests to new_bfqq)
 	 */
-	bic_set_bfqq(bic, new_bfqq, 1);
+	bic_set_bfqq(bic, new_bfqq, true);
 	bfq_mark_bfqq_coop(new_bfqq);
 	/*
 	 * new_bfqq now belongs to at least two bics (it is a shared queue):
@@ -6562,7 +6562,7 @@ bfq_split_bfqq(struct bfq_io_cq *bic, struct bfq_queue *bfqq)
 		return bfqq;
 	}
 
-	bic_set_bfqq(bic, NULL, 1);
+	bic_set_bfqq(bic, NULL, true);
 
 	bfq_put_cooperator(bfqq);
 
-- 
GitLab


From ff1cc97b1f4c10db224f276d9615b22835b8c424 Mon Sep 17 00:00:00 2001
From: "Jiri Slaby (SUSE)" <jirislaby@kernel.org>
Date: Tue, 13 Dec 2022 13:08:26 +0100
Subject: [PATCH 409/875] block/blk-iocost (gcc13): keep large values in a new
 enum

Since gcc13, each member of an enum has the same type as the enum [1]. And
that is inherited from its members. Provided:
  VTIME_PER_SEC_SHIFT     = 37,
  VTIME_PER_SEC           = 1LLU << VTIME_PER_SEC_SHIFT,
  ...
  AUTOP_CYCLE_NSEC        = 10LLU * NSEC_PER_SEC,
the named type is unsigned long.

This generates warnings with gcc-13:
  block/blk-iocost.c: In function 'ioc_weight_prfill':
  block/blk-iocost.c:3037:37: error: format '%u' expects argument of type 'unsigned int', but argument 4 has type 'long unsigned int'

  block/blk-iocost.c: In function 'ioc_weight_show':
  block/blk-iocost.c:3047:34: error: format '%u' expects argument of type 'unsigned int', but argument 3 has type 'long unsigned int'

So split the anonymous enum with large values to a separate enum, so
that they don't affect other members.

[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=36113

Cc: Martin Liska <mliska@suse.cz>
Cc: Tejun Heo <tj@kernel.org>
Cc: Josef Bacik <josef@toxicpanda.com>
Cc: Jens Axboe <axboe@kernel.dk>
Cc: cgroups@vger.kernel.org
Cc: linux-block@vger.kernel.org
Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org>
Link: https://lore.kernel.org/r/20221213120826.17446-1-jirislaby@kernel.org
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 block/blk-iocost.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/block/blk-iocost.c b/block/blk-iocost.c
index d1bdc12deaa70..549ddc9e0c6f4 100644
--- a/block/blk-iocost.c
+++ b/block/blk-iocost.c
@@ -232,7 +232,9 @@ enum {
 
 	/* 1/64k is granular enough and can easily be handled w/ u32 */
 	WEIGHT_ONE		= 1 << 16,
+};
 
+enum {
 	/*
 	 * As vtime is used to calculate the cost of each IO, it needs to
 	 * be fairly high precision.  For example, it should be able to
-- 
GitLab


From 85c50197716c60fe57f411339c579462e563ac57 Mon Sep 17 00:00:00 2001
From: "Isaac J. Manjarres" <isaacmanjarres@google.com>
Date: Thu, 8 Dec 2022 13:29:01 -0800
Subject: [PATCH 410/875] loop: Fix the max_loop commandline argument treatment
 when it is set to 0

Currently, the max_loop commandline argument can be used to specify how
many loop block devices are created at init time. If it is not
specified on the commandline, CONFIG_BLK_DEV_LOOP_MIN_COUNT loop block
devices will be created.

The max_loop commandline argument can be used to override the value of
CONFIG_BLK_DEV_LOOP_MIN_COUNT. However, when max_loop is set to 0
through the commandline, the current logic treats it as if it had not
been set, and creates CONFIG_BLK_DEV_LOOP_MIN_COUNT devices anyway.

Fix this by starting max_loop off as set to CONFIG_BLK_DEV_LOOP_MIN_COUNT.
This preserves the intended behavior of creating
CONFIG_BLK_DEV_LOOP_MIN_COUNT loop block devices if the max_loop
commandline parameter is not specified, and allowing max_loop to
be respected for all values, including 0.

This allows environments that can create all of their required loop
block devices on demand to not have to unnecessarily preallocate loop
block devices.

Fixes: 732850827450 ("remove artificial software max_loop limit")
Cc: stable@vger.kernel.org
Cc: Ken Chen <kenchen@google.com>
Signed-off-by: Isaac J. Manjarres <isaacmanjarres@google.com>
Link: https://lore.kernel.org/r/20221208212902.765781-1-isaacmanjarres@google.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 drivers/block/loop.c | 28 ++++++++++++----------------
 1 file changed, 12 insertions(+), 16 deletions(-)

diff --git a/drivers/block/loop.c b/drivers/block/loop.c
index 1f8f3b87bdfa8..df628e30bca41 100644
--- a/drivers/block/loop.c
+++ b/drivers/block/loop.c
@@ -1773,7 +1773,16 @@ static const struct block_device_operations lo_fops = {
 /*
  * And now the modules code and kernel interface.
  */
-static int max_loop;
+
+/*
+ * If max_loop is specified, create that many devices upfront.
+ * This also becomes a hard limit. If max_loop is not specified,
+ * create CONFIG_BLK_DEV_LOOP_MIN_COUNT loop devices at module
+ * init time. Loop devices can be requested on-demand with the
+ * /dev/loop-control interface, or be instantiated by accessing
+ * a 'dead' device node.
+ */
+static int max_loop = CONFIG_BLK_DEV_LOOP_MIN_COUNT;
 module_param(max_loop, int, 0444);
 MODULE_PARM_DESC(max_loop, "Maximum number of loop devices");
 module_param(max_part, int, 0444);
@@ -2181,7 +2190,7 @@ MODULE_ALIAS("devname:loop-control");
 
 static int __init loop_init(void)
 {
-	int i, nr;
+	int i;
 	int err;
 
 	part_shift = 0;
@@ -2209,19 +2218,6 @@ static int __init loop_init(void)
 		goto err_out;
 	}
 
-	/*
-	 * If max_loop is specified, create that many devices upfront.
-	 * This also becomes a hard limit. If max_loop is not specified,
-	 * create CONFIG_BLK_DEV_LOOP_MIN_COUNT loop devices at module
-	 * init time. Loop devices can be requested on-demand with the
-	 * /dev/loop-control interface, or be instantiated by accessing
-	 * a 'dead' device node.
-	 */
-	if (max_loop)
-		nr = max_loop;
-	else
-		nr = CONFIG_BLK_DEV_LOOP_MIN_COUNT;
-
 	err = misc_register(&loop_misc);
 	if (err < 0)
 		goto err_out;
@@ -2233,7 +2229,7 @@ static int __init loop_init(void)
 	}
 
 	/* pre-create number of devices given by config or max_loop */
-	for (i = 0; i < nr; i++)
+	for (i = 0; i < max_loop; i++)
 		loop_add(i);
 
 	printk(KERN_INFO "loop: module loaded\n");
-- 
GitLab


From 952d19190c6d482ec725f22e8bc8646bc0189d41 Mon Sep 17 00:00:00 2001
From: Matthew Auld <matthew.auld@intel.com>
Date: Mon, 12 Dec 2022 17:19:57 +0000
Subject: [PATCH 411/875] drm/i915/migrate: fix corner case in CCS aux copying
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

In the case of lmem -> lmem transfers, which is currently only possible
with small-bar systems, we need to ensure we copy the CCS aux state
as-is, rather than nuke it. This should fix some nasty display
corruption sometimes seen on DG2 small-bar systems, when also using
DG2_RC_CCS_CC for the surface.

Fixes: e3afc690188b ("drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers")
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Nirmoy Das <nirmoy.das@intel.com>
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Shuicheng Lin <shuicheng.lin@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221212171958.82593-1-matthew.auld@intel.com
(cherry picked from commit b29d26fbcb862526d5047caec82878be2eb75c0f)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_migrate.c | 37 +++++++++++++++++++------
 1 file changed, 29 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
index b783f6f740c8b..5fb74e71f27b5 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -837,14 +837,35 @@ intel_context_migrate_copy(struct intel_context *ce,
 			if (err)
 				goto out_rq;
 
-			/*
-			 * While we can't always restore/manage the CCS state,
-			 * we still need to ensure we don't leak the CCS state
-			 * from the previous user, so make sure we overwrite it
-			 * with something.
-			 */
-			err = emit_copy_ccs(rq, dst_offset, INDIRECT_ACCESS,
-					    dst_offset, DIRECT_ACCESS, len);
+			if (src_is_lmem) {
+				/*
+				 * If the src is already in lmem, then we must
+				 * be doing an lmem -> lmem transfer, and so
+				 * should be safe to directly copy the CCS
+				 * state. In this case we have either
+				 * initialised the CCS aux state when first
+				 * clearing the pages (since it is already
+				 * allocated in lmem), or the user has
+				 * potentially populated it, in which case we
+				 * need to copy the CCS state as-is.
+				 */
+				err = emit_copy_ccs(rq,
+						    dst_offset, INDIRECT_ACCESS,
+						    src_offset, INDIRECT_ACCESS,
+						    len);
+			} else {
+				/*
+				 * While we can't always restore/manage the CCS
+				 * state, we still need to ensure we don't leak
+				 * the CCS state from the previous user, so make
+				 * sure we overwrite it with something.
+				 */
+				err = emit_copy_ccs(rq,
+						    dst_offset, INDIRECT_ACCESS,
+						    dst_offset, DIRECT_ACCESS,
+						    len);
+			}
+
 			if (err)
 				goto out_rq;
 
-- 
GitLab


From ad0fca2dceeab8fdd8e1135f4b4ef2dc46c2ead9 Mon Sep 17 00:00:00 2001
From: Matthew Auld <matthew.auld@intel.com>
Date: Mon, 12 Dec 2022 17:19:58 +0000
Subject: [PATCH 412/875] drm/i915/ttm: consider CCS for backup objects
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

It seems we can have one or more framebuffers that are still pinned when
suspending lmem, in such a case we end up creating a shmem backup
object, instead of evicting the object directly, but this will skip
copying the CCS aux state, since we don't allocate the extra storage for
the CCS pages as part of the ttm_tt construction. Since we can already
deal with pinned objects just fine, it doesn't seem too nasty to just
extend to support dealing with the CCS aux state, if the object is a
pinned framebuffer. This fixes display corruption (like in gnome-shell)
seen on DG2 when returning from suspend.

Fixes: da0595ae91da ("drm/i915/migrate: Evict and restore the flatccs capable lmem obj")
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Nirmoy Das <nirmoy.das@intel.com>
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Shuicheng Lin <shuicheng.lin@intel.com>
Cc: <stable@vger.kernel.org> # v5.19+
Tested-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221212171958.82593-2-matthew.auld@intel.com
(cherry picked from commit 95df9cc24bee8a09d39c62bcef4319b984814e18)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_object.c     |  3 +++
 .../gpu/drm/i915/gem/i915_gem_object_types.h   | 10 ++++++----
 drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c     | 18 +++++++++++++++++-
 3 files changed, 26 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 733696057761c..1a0886b8aaa1d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -785,6 +785,9 @@ bool i915_gem_object_needs_ccs_pages(struct drm_i915_gem_object *obj)
 	if (!HAS_FLAT_CCS(to_i915(obj->base.dev)))
 		return false;
 
+	if (obj->flags & I915_BO_ALLOC_CCS_AUX)
+		return true;
+
 	for (i = 0; i < obj->mm.n_placements; i++) {
 		/* Compression is not allowed for the objects with smem placement */
 		if (obj->mm.placements[i]->type == INTEL_MEMORY_SYSTEM)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index d0d6772e6f36a..ab4c2f90a5643 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -327,16 +327,18 @@ struct drm_i915_gem_object {
  * dealing with userspace objects the CPU fault handler is free to ignore this.
  */
 #define I915_BO_ALLOC_GPU_ONLY	  BIT(6)
+#define I915_BO_ALLOC_CCS_AUX	  BIT(7)
 #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
 			     I915_BO_ALLOC_VOLATILE | \
 			     I915_BO_ALLOC_CPU_CLEAR | \
 			     I915_BO_ALLOC_USER | \
 			     I915_BO_ALLOC_PM_VOLATILE | \
 			     I915_BO_ALLOC_PM_EARLY | \
-			     I915_BO_ALLOC_GPU_ONLY)
-#define I915_BO_READONLY          BIT(7)
-#define I915_TILING_QUIRK_BIT     8 /* unknown swizzling; do not release! */
-#define I915_BO_PROTECTED         BIT(9)
+			     I915_BO_ALLOC_GPU_ONLY | \
+			     I915_BO_ALLOC_CCS_AUX)
+#define I915_BO_READONLY          BIT(8)
+#define I915_TILING_QUIRK_BIT     9 /* unknown swizzling; do not release! */
+#define I915_BO_PROTECTED         BIT(10)
 	/**
 	 * @mem_flags - Mutable placement-related flags
 	 *
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
index 07e49f22f2de3..7e67742bc65e0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
@@ -50,6 +50,7 @@ static int i915_ttm_backup(struct i915_gem_apply_to_region *apply,
 		container_of(bo->bdev, typeof(*i915), bdev);
 	struct drm_i915_gem_object *backup;
 	struct ttm_operation_ctx ctx = {};
+	unsigned int flags;
 	int err = 0;
 
 	if (bo->resource->mem_type == I915_PL_SYSTEM || obj->ttm.backup)
@@ -65,7 +66,22 @@ static int i915_ttm_backup(struct i915_gem_apply_to_region *apply,
 	if (obj->flags & I915_BO_ALLOC_PM_VOLATILE)
 		return 0;
 
-	backup = i915_gem_object_create_shmem(i915, obj->base.size);
+	/*
+	 * It seems that we might have some framebuffers still pinned at this
+	 * stage, but for such objects we might also need to deal with the CCS
+	 * aux state. Make sure we force the save/restore of the CCS state,
+	 * otherwise we might observe display corruption, when returning from
+	 * suspend.
+	 */
+	flags = 0;
+	if (i915_gem_object_needs_ccs_pages(obj)) {
+		WARN_ON_ONCE(!i915_gem_object_is_framebuffer(obj));
+		WARN_ON_ONCE(!pm_apply->allow_gpu);
+
+		flags = I915_BO_ALLOC_CCS_AUX;
+	}
+	backup = i915_gem_object_create_region(i915->mm.regions[INTEL_REGION_SMEM],
+					       obj->base.size, 0, flags);
 	if (IS_ERR(backup))
 		return PTR_ERR(backup);
 
-- 
GitLab


From 73278d483378cf850ade923a1107a70297b2602a Mon Sep 17 00:00:00 2001
From: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Date: Mon, 12 Dec 2022 08:32:20 +0000
Subject: [PATCH 413/875] media: v4l2-ctrls-api.c: add back dropped
 ctrl->is_new = 1

The patch adding support for dynamically allocated arrays accidentally
dropped the line setting ctrl->is_new to 1, thus new string values were
always ignored.

Fixes: fb582cba4492 ("media: v4l2-ctrls: add support for dynamically allocated arrays.")
Reported-by: Alice Yuan <alice.yuan@nxp.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
---
 drivers/media/v4l2-core/v4l2-ctrls-api.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/media/v4l2-core/v4l2-ctrls-api.c b/drivers/media/v4l2-core/v4l2-ctrls-api.c
index d0a3aa3806fbd..3d3b6dc24ca63 100644
--- a/drivers/media/v4l2-core/v4l2-ctrls-api.c
+++ b/drivers/media/v4l2-core/v4l2-ctrls-api.c
@@ -150,6 +150,7 @@ static int user_to_new(struct v4l2_ext_control *c, struct v4l2_ctrl *ctrl)
 			 * then return an error.
 			 */
 			if (strlen(ctrl->p_new.p_char) == ctrl->maximum && last)
+			ctrl->is_new = 1;
 				return -ERANGE;
 		}
 		return ret;
-- 
GitLab


From 7fabed7ae6185ef7f5967f3a2271c906ec6b7b7d Mon Sep 17 00:00:00 2001
From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Date: Thu, 8 Dec 2022 15:19:56 +0100
Subject: [PATCH 414/875] media: sun6i-csi: bridge: Error out on invalid port
 to fix warning

The enabled variable is only set for a valid port and used later,
which triggers an uninitialized use smatch warning. Explicitly error
out in that case to fix the warning.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Fixes: 0d2b746b1bef ("media: sun6i-csi: Add bridge v4l2 subdev with port management")
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
---
 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
index ebfc870d2af50..4db950973ce2a 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
@@ -663,7 +663,7 @@ sun6i_csi_bridge_notifier_bound(struct v4l2_async_notifier *notifier,
 		enabled = !bridge->source_parallel.expected;
 		break;
 	default:
-		break;
+		return -EINVAL;
 	}
 
 	source->subdev = remote_subdev;
-- 
GitLab


From f2c174e5018ed3360fdfeb6f9cd5c05e6086d134 Mon Sep 17 00:00:00 2001
From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Date: Thu, 8 Dec 2022 15:19:58 +0100
Subject: [PATCH 415/875] media: sun6i-csi: capture: Remove useless ret
 initialization

There is no particular need to assign ret when declaring it as
it will be assigned before there is any chance to return it.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
---
 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
index 6d34f5c0768f1..cf6aadbc130b8 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
@@ -832,7 +832,7 @@ static int sun6i_csi_capture_open(struct file *file)
 {
 	struct sun6i_csi_device *csi_dev = video_drvdata(file);
 	struct sun6i_csi_capture *capture = &csi_dev->capture;
-	int ret = 0;
+	int ret;
 
 	if (mutex_lock_interruptible(&capture->lock))
 		return -ERESTARTSYS;
-- 
GitLab


From 52109d91d2f91e9cc7a14ee46443e374a21573cf Mon Sep 17 00:00:00 2001
From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Date: Thu, 8 Dec 2022 15:19:59 +0100
Subject: [PATCH 416/875] media: sun6i-mipi-csi2: Clarify return code handling
 in stream off path

Explicitly set ret to zero instead of assigning it and overwriting it
later, which is a bit confusing to understand.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
---
 .../media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c   | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
index 484ac5f054d53..a220ce849b413 100644
--- a/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
+++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
@@ -188,7 +188,8 @@ static int sun6i_mipi_csi2_s_stream(struct v4l2_subdev *subdev, int on)
 		return -ENODEV;
 
 	if (!on) {
-		ret = v4l2_subdev_call(source_subdev, video, s_stream, 0);
+		v4l2_subdev_call(source_subdev, video, s_stream, 0);
+		ret = 0;
 		goto disable;
 	}
 
@@ -280,8 +281,6 @@ static int sun6i_mipi_csi2_s_stream(struct v4l2_subdev *subdev, int on)
 	return 0;
 
 disable:
-	if (!on)
-		ret = 0;
 	phy_power_off(dphy);
 	sun6i_mipi_csi2_disable(csi2_dev);
 
-- 
GitLab


From 761ebebabd0953fde1e6b77d6ff54356dc1639c4 Mon Sep 17 00:00:00 2001
From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Date: Thu, 8 Dec 2022 15:20:00 +0100
Subject: [PATCH 417/875] media: sun8i-a83t-mipi-csi2: Clarify return code
 handling in stream off path

Explicitly set ret to zero instead of assigning it and overwriting it
later, which is a bit confusing to understand.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
---
 .../sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c        | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c
index d993c09a48202..cd2e92ae22933 100644
--- a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c
+++ b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c
@@ -220,7 +220,8 @@ static int sun8i_a83t_mipi_csi2_s_stream(struct v4l2_subdev *subdev, int on)
 		return -ENODEV;
 
 	if (!on) {
-		ret = v4l2_subdev_call(source_subdev, video, s_stream, 0);
+		v4l2_subdev_call(source_subdev, video, s_stream, 0);
+		ret = 0;
 		goto disable;
 	}
 
@@ -312,8 +313,6 @@ static int sun8i_a83t_mipi_csi2_s_stream(struct v4l2_subdev *subdev, int on)
 	return 0;
 
 disable:
-	if (!on)
-		ret = 0;
 	phy_power_off(dphy);
 	sun8i_a83t_mipi_csi2_disable(csi2_dev);
 
-- 
GitLab


From 504307f2b3ae2625ed591efe073c2d14d568dfc8 Mon Sep 17 00:00:00 2001
From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Date: Thu, 8 Dec 2022 15:20:01 +0100
Subject: [PATCH 418/875] media: sun6i-isp: proc: Fix return code handling in
 stream off path

Explicitly set ret to zero on disable path to avoid a related smatch
warning. This makes initialization at declaration useless.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Fixes: e3185e1d7c14 ("media: staging: media: Add support for the Allwinner A31 ISP")
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
---
 drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_proc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_proc.c b/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_proc.c
index d69d2be0add23..a95709d2c5736 100644
--- a/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_proc.c
+++ b/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_proc.c
@@ -173,8 +173,7 @@ static int sun6i_isp_proc_s_stream(struct v4l2_subdev *subdev, int on)
 	struct sun6i_isp_proc_source *source;
 	struct v4l2_subdev *source_subdev;
 	struct media_pad *remote_pad;
-	/* Initialize to 0 to use both in disable label (ret != 0) and off. */
-	int ret = 0;
+	int ret;
 
 	/* Source */
 
@@ -195,6 +194,7 @@ static int sun6i_isp_proc_s_stream(struct v4l2_subdev *subdev, int on)
 	if (!on) {
 		sun6i_isp_proc_irq_disable(isp_dev);
 		v4l2_subdev_call(source_subdev, video, s_stream, 0);
+		ret = 0;
 		goto disable;
 	}
 
-- 
GitLab


From f72af770947825cd9947ce8b979bf9d6fe699c73 Mon Sep 17 00:00:00 2001
From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Date: Thu, 8 Dec 2022 15:20:02 +0100
Subject: [PATCH 419/875] media: sun6i-isp: proc: Error out on invalid port to
 fix warning

The enabled variable is only set for a valid port and used later,
which triggers an uninitialized use smatch warning. Explicitly error
out in that case to fix the warning.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Fixes: e3185e1d7c14 ("media: staging: media: Add support for the Allwinner A31 ISP")
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
---
 drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_proc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_proc.c b/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_proc.c
index a95709d2c5736..4f34c1bc8be95 100644
--- a/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_proc.c
+++ b/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_proc.c
@@ -416,7 +416,7 @@ static int sun6i_isp_proc_notifier_bound(struct v4l2_async_notifier *notifier,
 		enabled = !proc->source_csi0.expected;
 		break;
 	default:
-		break;
+		return -EINVAL;
 	}
 
 	source->subdev = remote_subdev;
-- 
GitLab


From 44723b8c4692566237321d658b482025bb0235f8 Mon Sep 17 00:00:00 2001
From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Date: Thu, 8 Dec 2022 15:20:03 +0100
Subject: [PATCH 420/875] media: sun6i-isp: proc: Declare subdev ops as static

The static keyword is missing in the v4l2 subdev ops definition for the
proc.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Fixes: e3185e1d7c14 ("media: staging: media: Add support for the Allwinner A31 ISP")
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
---
 drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_proc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_proc.c b/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_proc.c
index 4f34c1bc8be95..1ca4673df2b3a 100644
--- a/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_proc.c
+++ b/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_proc.c
@@ -342,7 +342,7 @@ static const struct v4l2_subdev_pad_ops sun6i_isp_proc_pad_ops = {
 	.set_fmt	= sun6i_isp_proc_set_fmt,
 };
 
-const struct v4l2_subdev_ops sun6i_isp_proc_subdev_ops = {
+static const struct v4l2_subdev_ops sun6i_isp_proc_subdev_ops = {
 	.video	= &sun6i_isp_proc_video_ops,
 	.pad	= &sun6i_isp_proc_pad_ops,
 };
-- 
GitLab


From 7266eb7c5a52efe8dc19a34c45c0fc8e3c0e4137 Mon Sep 17 00:00:00 2001
From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Date: Thu, 8 Dec 2022 15:20:04 +0100
Subject: [PATCH 421/875] media: sun6i-isp: capture: Fix uninitialized variable
 use

While the stride_chroma variable was previously initialized to zero,
it's actually stride_chroma_div4 that is set to hardware registers.

Initialize it to zero instead to avoid an uninitialized variable use
and get rid of the associated smatch warning.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Fixes: e3185e1d7c14 ("media: staging: media: Add support for the Allwinner A31 ISP")
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
---
 drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_capture.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_capture.c b/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_capture.c
index 4b592820845a9..1595a9607775b 100644
--- a/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_capture.c
+++ b/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_capture.c
@@ -108,8 +108,8 @@ sun6i_isp_capture_buffer_configure(struct sun6i_isp_device *isp_dev,
 void sun6i_isp_capture_configure(struct sun6i_isp_device *isp_dev)
 {
 	unsigned int width, height;
-	unsigned int stride_luma, stride_chroma = 0;
-	unsigned int stride_luma_div4, stride_chroma_div4;
+	unsigned int stride_luma, stride_chroma;
+	unsigned int stride_luma_div4, stride_chroma_div4 = 0;
 	const struct sun6i_isp_capture_format *format;
 	const struct v4l2_format_info *info;
 	u32 pixelformat;
-- 
GitLab


From 94c34359c88737d903c44d1c1a265cfdc58acd0e Mon Sep 17 00:00:00 2001
From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Date: Thu, 8 Dec 2022 15:20:05 +0100
Subject: [PATCH 422/875] media: sun6i-isp: params: Fix incorrect indentation

Remove a heading whitespace that results in a smatch warning.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Fixes: e3185e1d7c14 ("media: staging: media: Add support for the Allwinner A31 ISP")
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
---
 drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_params.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_params.c b/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_params.c
index 8039e311cb1c3..7b41a13162b9a 100644
--- a/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_params.c
+++ b/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_params.c
@@ -183,8 +183,8 @@ void sun6i_isp_params_configure(struct sun6i_isp_device *isp_dev)
 	if (state->configured)
 		goto complete;
 
-	 sun6i_isp_params_configure_modules(isp_dev,
-					    &sun6i_isp_params_config_default);
+	sun6i_isp_params_configure_modules(isp_dev,
+					   &sun6i_isp_params_config_default);
 
 	state->configured = true;
 
-- 
GitLab


From 542d3c03fd895eb8370992293498332ea383a3b9 Mon Sep 17 00:00:00 2001
From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Date: Thu, 8 Dec 2022 15:20:06 +0100
Subject: [PATCH 423/875] media: sun6i-isp: params: Unregister pending buffer
 on cleanup

The state cleanup helper should unregister the pending buffer from
the state after returning it to v4l2, like it is done for other
buffers in the wait queue.

Before this change, the pending buffer from a previous run might have
been returned at the beginning of the next run, causing an error.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Fixes: e3185e1d7c14 ("media: staging: media: Add support for the Allwinner A31 ISP")
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
---
 drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_params.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_params.c b/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_params.c
index 7b41a13162b9a..e28be895b4861 100644
--- a/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_params.c
+++ b/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_params.c
@@ -208,6 +208,8 @@ static void sun6i_isp_params_state_cleanup(struct sun6i_isp_device *isp_dev,
 		vb2_buffer = &state->pending->v4l2_buffer.vb2_buf;
 		vb2_buffer_done(vb2_buffer, error ? VB2_BUF_STATE_ERROR :
 				VB2_BUF_STATE_QUEUED);
+
+		state->pending = NULL;
 	}
 
 	list_for_each_entry(isp_buffer, &state->queue, list) {
-- 
GitLab


From ff5870a76c2abda389650d3711cdddc031d12665 Mon Sep 17 00:00:00 2001
From: Moises Cardona <moisesmcardona@gmail.com>
Date: Wed, 14 Dec 2022 07:08:30 -0500
Subject: [PATCH 424/875] ASoC: Intel: Add HP Stream 8 to bytcr_rt5640.c

The bytcr_rt5640.c file already supports the HP Stream 7.

The HP Stream 8 is almost identical in terms of the hardware
with the exception of it having stereo speakers, a SIM
card slot and the obvious size difference.

Signed-off-by: Moises Cardona <moisesmcardona@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20221214120830.1572474-1-moisesmcardona@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/boards/bytcr_rt5640.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/sound/soc/intel/boards/bytcr_rt5640.c b/sound/soc/intel/boards/bytcr_rt5640.c
index 44e6a0f1e2d90..4699ca79f3ea6 100644
--- a/sound/soc/intel/boards/bytcr_rt5640.c
+++ b/sound/soc/intel/boards/bytcr_rt5640.c
@@ -811,6 +811,16 @@ static const struct dmi_system_id byt_rt5640_quirk_table[] = {
 					BYT_RT5640_SSP0_AIF1 |
 					BYT_RT5640_MCLK_EN),
 	},
+	{	/* HP Stream 8 */
+		.matches = {
+			DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
+			DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "HP Stream 8 Tablet"),
+		},
+		.driver_data = (void *)(BYTCR_INPUT_DEFAULTS |
+					BYT_RT5640_JD_NOT_INV |
+					BYT_RT5640_SSP0_AIF1 |
+					BYT_RT5640_MCLK_EN),
+	},
 	{	/* I.T.Works TW891 */
 		.matches = {
 			DMI_EXACT_MATCH(DMI_SYS_VENDOR, "To be filled by O.E.M."),
-- 
GitLab


From 813e693023ba10da9e75067780f8378465bf27cc Mon Sep 17 00:00:00 2001
From: Tejun Heo <tj@kernel.org>
Date: Sat, 10 Dec 2022 08:33:10 -1000
Subject: [PATCH 425/875] blk-iolatency: Fix memory leak on add_disk() failures

When a gendisk is successfully initialized but add_disk() fails such as when
a loop device has invalid number of minor device numbers specified,
blkcg_init_disk() is called during init and then blkcg_exit_disk() during
error handling. Unfortunately, iolatency gets initialized in the former but
doesn't get cleaned up in the latter.

This is because, in non-error cases, the cleanup is performed by
del_gendisk() calling rq_qos_exit(), the assumption being that rq_qos
policies, iolatency being one of them, can only be activated once the disk
is fully registered and visible. That assumption is true for wbt and iocost,
but not so for iolatency as it gets initialized before add_disk() is called.

It is desirable to lazy-init rq_qos policies because they are optional
features and add to hot path overhead once initialized - each IO has to walk
all the registered rq_qos policies. So, we want to switch iolatency to lazy
init too. However, that's a bigger change. As a fix for the immediate
problem, let's just add an extra call to rq_qos_exit() in blkcg_exit_disk().
This is safe because duplicate calls to rq_qos_exit() become noop's.

Signed-off-by: Tejun Heo <tj@kernel.org>
Reported-by: darklight2357@icloud.com
Cc: Josef Bacik <josef@toxicpanda.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Fixes: d70675121546 ("block: introduce blk-iolatency io controller")
Cc: stable@vger.kernel.org # v4.19+
Reviewed-by: Christoph Hellwig <hch@lst.de>
Link: https://lore.kernel.org/r/Y5TQ5gm3O4HXrXR3@slm.duckdns.org
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 block/blk-cgroup.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/block/blk-cgroup.c b/block/blk-cgroup.c
index 50ac0dce95b84..ce6a2b7d3dfb2 100644
--- a/block/blk-cgroup.c
+++ b/block/blk-cgroup.c
@@ -33,6 +33,7 @@
 #include "blk-cgroup.h"
 #include "blk-ioprio.h"
 #include "blk-throttle.h"
+#include "blk-rq-qos.h"
 
 /*
  * blkcg_pol_mutex protects blkcg_policy[] and policy [de]activation.
@@ -1322,6 +1323,7 @@ err_unlock:
 void blkcg_exit_disk(struct gendisk *disk)
 {
 	blkg_destroy_all(disk);
+	rq_qos_exit(disk->queue);
 	blk_throtl_exit(disk);
 }
 
-- 
GitLab


From 28afcb0ad54c858d0f426b340e88e0277a375597 Mon Sep 17 00:00:00 2001
From: Luben Tuikov <luben.tuikov@amd.com>
Date: Mon, 12 Dec 2022 12:04:42 -0500
Subject: [PATCH 426/875] drm/amdgpu: Check if fru_addr is not NULL (v2)

Always check if fru_addr is not NULL. This commit also fixes a "smatch"
warning.

v2: Add a Fixes tag.

Cc: Alex Deucher <Alexander.Deucher@amd.com>
Cc: Dan Carpenter <error27@gmail.com>
Cc: kernel test robot <lkp@intel.com>
Cc: AMD Graphics <amd-gfx@lists.freedesktop.org>
Fixes: afbe5d1e4bd7c7 ("drm/amdgpu: Bug-fix: Reading I2C FRU data on newer ASICs")
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Kent Russell <kent.russell@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
index 2c38ac7bc643d..4620c4712ce32 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
@@ -64,7 +64,8 @@ static bool is_fru_eeprom_supported(struct amdgpu_device *adev, u32 *fru_addr)
 			    sizeof(atom_ctx->vbios_version)) ||
 		    strnstr(atom_ctx->vbios_version, "D163",
 			    sizeof(atom_ctx->vbios_version))) {
-			*fru_addr = FRU_EEPROM_MADDR_6;
+			if (fru_addr)
+				*fru_addr = FRU_EEPROM_MADDR_6;
 			return true;
 		} else {
 			return false;
@@ -83,7 +84,8 @@ static bool is_fru_eeprom_supported(struct amdgpu_device *adev, u32 *fru_addr)
 				    sizeof(atom_ctx->vbios_version))) {
 				return false;
 			} else {
-				*fru_addr = FRU_EEPROM_MADDR_6;
+				if (fru_addr)
+					*fru_addr = FRU_EEPROM_MADDR_6;
 				return true;
 			}
 		} else {
-- 
GitLab


From 7554886daa31eacc8e7fac9e15bbce67d10b8f1f Mon Sep 17 00:00:00 2001
From: Luben Tuikov <luben.tuikov@amd.com>
Date: Sat, 10 Dec 2022 02:51:19 -0500
Subject: [PATCH 427/875] drm/amdgpu: Fix size validation for non-exclusive
 domains (v4)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Fix amdgpu_bo_validate_size() to check whether the TTM domain manager for the
requested memory exists, else we get a kernel oops when dereferencing "man".

v2: Make the patch standalone, i.e. not dependent on local patches.
v3: Preserve old behaviour and just check that the manager pointer is not
    NULL.
v4: Complain if GTT domain requested and it is uninitialized--most likely a
    bug.

Cc: Alex Deucher <Alexander.Deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: AMD Graphics <amd-gfx@lists.freedesktop.org>
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 19 ++++++++-----------
 1 file changed, 8 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 3393c1a6a0ff1..26c6e9b2d4606 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -448,27 +448,24 @@ static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
 
 	/*
 	 * If GTT is part of requested domains the check must succeed to
-	 * allow fall back to GTT
+	 * allow fall back to GTT.
 	 */
 	if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 		man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
 
-		if (size < man->size)
+		if (man && size < man->size)
 			return true;
-		else
-			goto fail;
-	}
-
-	if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
+		else if (!man)
+			WARN_ON_ONCE("GTT domain requested but GTT mem manager uninitialized");
+		goto fail;
+	} else if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
 		man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
 
-		if (size < man->size)
+		if (man && size < man->size)
 			return true;
-		else
-			goto fail;
+		goto fail;
 	}
 
-
 	/* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */
 	return true;
 
-- 
GitLab


From 3273f11675ef11959d25a56df3279f712bcd41b7 Mon Sep 17 00:00:00 2001
From: Luben Tuikov <luben.tuikov@amd.com>
Date: Wed, 14 Dec 2022 03:56:03 -0500
Subject: [PATCH 428/875] drm/amdgpu: Remove unnecessary domain argument
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Remove the "domain" argument to amdgpu_bo_create_kernel_at() since this
function takes an "offset" argument which is the offset off of VRAM, and as
such allocation always takes place in VRAM. Thus, the "domain" argument is
unnecessary.

Cc: Alex Deucher <Alexander.Deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: AMD Graphics <amd-gfx@lists.freedesktop.org>
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 10 +++++-----
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c    |  7 -------
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c   |  1 -
 4 files changed, 6 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 26c6e9b2d4606..0f63859414807 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -346,17 +346,16 @@ int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
  * @adev: amdgpu device object
  * @offset: offset of the BO
  * @size: size of the BO
- * @domain: where to place it
  * @bo_ptr:  used to initialize BOs in structures
  * @cpu_addr: optional CPU address mapping
  *
- * Creates a kernel BO at a specific offset in the address space of the domain.
+ * Creates a kernel BO at a specific offset in VRAM.
  *
  * Returns:
  * 0 on success, negative error code otherwise.
  */
 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
-			       uint64_t offset, uint64_t size, uint32_t domain,
+			       uint64_t offset, uint64_t size,
 			       struct amdgpu_bo **bo_ptr, void **cpu_addr)
 {
 	struct ttm_operation_ctx ctx = { false, false };
@@ -366,8 +365,9 @@ int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
 	offset &= PAGE_MASK;
 	size = ALIGN(size, PAGE_SIZE);
 
-	r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, domain, bo_ptr,
-				      NULL, cpu_addr);
+	r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE,
+				      AMDGPU_GEM_DOMAIN_VRAM, bo_ptr, NULL,
+				      cpu_addr);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 147b79c10cbb6..93207badf83f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -284,7 +284,7 @@ int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
 			    u32 domain, struct amdgpu_bo **bo_ptr,
 			    u64 *gpu_addr, void **cpu_addr);
 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
-			       uint64_t offset, uint64_t size, uint32_t domain,
+			       uint64_t offset, uint64_t size,
 			       struct amdgpu_bo **bo_ptr, void **cpu_addr);
 int amdgpu_bo_create_user(struct amdgpu_device *adev,
 			  struct amdgpu_bo_param *bp,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index f0e4c73094388..55e0284b2bddd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1576,7 +1576,6 @@ static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
 	return amdgpu_bo_create_kernel_at(adev,
 					  adev->mman.fw_vram_usage_start_offset,
 					  adev->mman.fw_vram_usage_size,
-					  AMDGPU_GEM_DOMAIN_VRAM,
 					  &adev->mman.fw_vram_usage_reserved_bo,
 					  &adev->mman.fw_vram_usage_va);
 }
@@ -1602,7 +1601,6 @@ static int amdgpu_ttm_drv_reserve_vram_init(struct amdgpu_device *adev)
 	return amdgpu_bo_create_kernel_at(adev,
 					  adev->mman.drv_vram_usage_start_offset,
 					  adev->mman.drv_vram_usage_size,
-					  AMDGPU_GEM_DOMAIN_VRAM,
 					  &adev->mman.drv_vram_usage_reserved_bo,
 					  &adev->mman.drv_vram_usage_va);
 }
@@ -1683,7 +1681,6 @@ static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
 		ret = amdgpu_bo_create_kernel_at(adev,
 					 ctx->c2p_train_data_offset,
 					 ctx->train_data_size,
-					 AMDGPU_GEM_DOMAIN_VRAM,
 					 &ctx->c2p_bo,
 					 NULL);
 		if (ret) {
@@ -1697,7 +1694,6 @@ static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
 	ret = amdgpu_bo_create_kernel_at(adev,
 				adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
 				adev->mman.discovery_tmr_size,
-				AMDGPU_GEM_DOMAIN_VRAM,
 				&adev->mman.discovery_memory,
 				NULL);
 	if (ret) {
@@ -1798,21 +1794,18 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
 	 * avoid display artifacts while transitioning between pre-OS
 	 * and driver.  */
 	r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
-				       AMDGPU_GEM_DOMAIN_VRAM,
 				       &adev->mman.stolen_vga_memory,
 				       NULL);
 	if (r)
 		return r;
 	r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
 				       adev->mman.stolen_extended_size,
-				       AMDGPU_GEM_DOMAIN_VRAM,
 				       &adev->mman.stolen_extended_memory,
 				       NULL);
 	if (r)
 		return r;
 	r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_reserved_offset,
 				       adev->mman.stolen_reserved_size,
-				       AMDGPU_GEM_DOMAIN_VRAM,
 				       &adev->mman.stolen_reserved_memory,
 				       NULL);
 	if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 15544f262ec15..2994b9db196ff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -395,7 +395,6 @@ static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev)
 		 */
 		if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT,
 					       AMDGPU_GPU_PAGE_SIZE,
-					       AMDGPU_GEM_DOMAIN_VRAM,
 					       &bo, NULL))
 			DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp);
 
-- 
GitLab


From 47722220660cfb935e27e62d385959ecc296cddb Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
Date: Mon, 12 Dec 2022 17:31:57 +0100
Subject: [PATCH 429/875] drm/amdgpu: revert "generally allow over-commit
 during BO allocation"
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This reverts commit f9d00a4a8dc8fff951c97b3213f90d6bc7a72175.

This causes problem for KFD because when we overcommit we accidentially
bind the BO to GTT for moving it into VRAM. We also need to make sure
that this is done only as fallback after trying to evict first.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c    | 16 +++++++++++++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c |  6 +++++-
 2 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 62e98f1ad770b..a0780a4e3e618 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -113,7 +113,7 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
 	bp.resv = resv;
 	bp.preferred_domain = initial_domain;
 	bp.flags = flags;
-	bp.domain = initial_domain | AMDGPU_GEM_DOMAIN_CPU;
+	bp.domain = initial_domain;
 	bp.bo_ptr_size = sizeof(struct amdgpu_bo);
 
 	r = amdgpu_bo_create_user(adev, &bp, &ubo);
@@ -332,10 +332,20 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
 	}
 
 	initial_domain = (u32)(0xffffffff & args->in.domains);
+retry:
 	r = amdgpu_gem_object_create(adev, size, args->in.alignment,
-				     initial_domain, flags, ttm_bo_type_device,
-				     resv, &gobj);
+				     initial_domain,
+				     flags, ttm_bo_type_device, resv, &gobj);
 	if (r && r != -ERESTARTSYS) {
+		if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
+			flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+			goto retry;
+		}
+
+		if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
+			initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
+			goto retry;
+		}
 		DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n",
 				size, initial_domain, args->in.alignment, r);
 	}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 0f63859414807..4e684c2afc709 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -580,7 +580,11 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
 		bo->flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
 
 	bo->tbo.bdev = &adev->mman.bdev;
-	amdgpu_bo_placement_from_domain(bo, bp->domain);
+	if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA |
+			  AMDGPU_GEM_DOMAIN_GDS))
+		amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
+	else
+		amdgpu_bo_placement_from_domain(bo, bp->domain);
 	if (bp->type == ttm_bo_type_kernel)
 		bo->tbo.priority = 1;
 
-- 
GitLab


From 1a17e5b513ceebf21100027745b8731b4728edf7 Mon Sep 17 00:00:00 2001
From: Kees Cook <keescook@chromium.org>
Date: Fri, 9 Dec 2022 11:54:57 -0800
Subject: [PATCH 430/875] LoadPin: Ignore the "contents" argument of the LSM
 hooks

LoadPin only enforces the read-only origin of kernel file reads. Whether
or not it was a partial read isn't important. Remove the overly
conservative checks so that things like partial firmware reads will
succeed (i.e. reading a firmware header).

Fixes: 2039bda1fa8d ("LSM: Add "contents" flag to kernel_read_file hook")
Cc: Paul Moore <paul@paul-moore.com>
Cc: James Morris <jmorris@namei.org>
Cc: "Serge E. Hallyn" <serge@hallyn.com>
Cc: linux-security-module@vger.kernel.org
Signed-off-by: Kees Cook <keescook@chromium.org>
Acked-by: Serge Hallyn <serge@hallyn.com>
Tested-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://lore.kernel.org/r/20221209195453.never.494-kees@kernel.org
---
 security/loadpin/loadpin.c | 30 ++++++++++++++++++------------
 1 file changed, 18 insertions(+), 12 deletions(-)

diff --git a/security/loadpin/loadpin.c b/security/loadpin/loadpin.c
index de41621f4998e..110a5ab2b46bc 100644
--- a/security/loadpin/loadpin.c
+++ b/security/loadpin/loadpin.c
@@ -122,21 +122,11 @@ static void loadpin_sb_free_security(struct super_block *mnt_sb)
 	}
 }
 
-static int loadpin_read_file(struct file *file, enum kernel_read_file_id id,
-			     bool contents)
+static int loadpin_check(struct file *file, enum kernel_read_file_id id)
 {
 	struct super_block *load_root;
 	const char *origin = kernel_read_file_id_str(id);
 
-	/*
-	 * If we will not know that we'll be seeing the full contents
-	 * then we cannot trust a load will be complete and unchanged
-	 * off disk. Treat all contents=false hooks as if there were
-	 * no associated file struct.
-	 */
-	if (!contents)
-		file = NULL;
-
 	/* If the file id is excluded, ignore the pinning. */
 	if ((unsigned int)id < ARRAY_SIZE(ignore_read_file_id) &&
 	    ignore_read_file_id[id]) {
@@ -192,9 +182,25 @@ static int loadpin_read_file(struct file *file, enum kernel_read_file_id id,
 	return 0;
 }
 
+static int loadpin_read_file(struct file *file, enum kernel_read_file_id id,
+			     bool contents)
+{
+	/*
+	 * LoadPin only cares about the _origin_ of a file, not its
+	 * contents, so we can ignore the "are full contents available"
+	 * argument here.
+	 */
+	return loadpin_check(file, id);
+}
+
 static int loadpin_load_data(enum kernel_load_data_id id, bool contents)
 {
-	return loadpin_read_file(NULL, (enum kernel_read_file_id) id, contents);
+	/*
+	 * LoadPin only cares about the _origin_ of a file, not its
+	 * contents, so a NULL file is passed, and we can ignore the
+	 * state of "contents".
+	 */
+	return loadpin_check(NULL, (enum kernel_read_file_id) id);
 }
 
 static struct security_hook_list loadpin_hooks[] __lsm_ro_after_init = {
-- 
GitLab


From 00dd027f721e0458418f7750d8a5a664ed3e5994 Mon Sep 17 00:00:00 2001
From: Kees Cook <keescook@chromium.org>
Date: Wed, 14 Dec 2022 14:35:47 -0800
Subject: [PATCH 431/875] docs: Fix path paste-o for /sys/kernel/warn_count

Running "make htmldocs" shows that "/sys/kernel/oops_count" was
duplicated. This should have been "warn_count":

  Warning: /sys/kernel/oops_count is defined 2 times:
  ./Documentation/ABI/testing/sysfs-kernel-warn_count:0
  ./Documentation/ABI/testing/sysfs-kernel-oops_count:0

Fix the typo.

Reported-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/linux-doc/202212110529.A3Qav8aR-lkp@intel.com
Fixes: 8b05aa263361 ("panic: Expose "warn_count" to sysfs")
Cc: linux-hardening@vger.kernel.org
Signed-off-by: Kees Cook <keescook@chromium.org>
---
 Documentation/ABI/testing/sysfs-kernel-warn_count | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/ABI/testing/sysfs-kernel-warn_count b/Documentation/ABI/testing/sysfs-kernel-warn_count
index 08f083d2fd51b..90a029813717d 100644
--- a/Documentation/ABI/testing/sysfs-kernel-warn_count
+++ b/Documentation/ABI/testing/sysfs-kernel-warn_count
@@ -1,4 +1,4 @@
-What:		/sys/kernel/oops_count
+What:		/sys/kernel/warn_count
 Date:		November 2022
 KernelVersion:	6.2.0
 Contact:	Linux Kernel Hardening List <linux-hardening@vger.kernel.org>
-- 
GitLab


From 3b7ddab8a19aefc768f345fd3782af35b4a68d9b Mon Sep 17 00:00:00 2001
From: wuqiang <wuqiang.matt@bytedance.com>
Date: Thu, 10 Nov 2022 16:15:02 +0800
Subject: [PATCH 432/875] kprobes: kretprobe events missing on 2-core KVM guest

Default value of maxactive is set as num_possible_cpus() for nonpreemptable
systems. For a 2-core system, only 2 kretprobe instances would be allocated
in default, then these 2 instances for execve kretprobe are very likely to
be used up with a pipelined command.

Here's the testcase: a shell script was added to crontab, and the content
of the script is:

  #!/bin/sh
  do_something_magic `tr -dc a-z < /dev/urandom | head -c 10`

cron will trigger a series of program executions (4 times every hour). Then
events loss would be noticed normally after 3-4 hours of testings.

The issue is caused by a burst of series of execve requests. The best number
of kretprobe instances could be different case by case, and should be user's
duty to determine, but num_possible_cpus() as the default value is inadequate
especially for systems with small number of cpus.

This patch enables the logic for preemption as default, thus increases the
minimum of maxactive to 10 for nonpreemptable systems.

Link: https://lore.kernel.org/all/20221110081502.492289-1-wuqiang.matt@bytedance.com/

Signed-off-by: wuqiang <wuqiang.matt@bytedance.com>
Reviewed-by: Solar Designer <solar@openwall.com>
Acked-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
Signed-off-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
---
 Documentation/trace/kprobes.rst | 3 +--
 kernel/kprobes.c                | 8 ++------
 2 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/Documentation/trace/kprobes.rst b/Documentation/trace/kprobes.rst
index 48cf778a24680..fc7ce76eab655 100644
--- a/Documentation/trace/kprobes.rst
+++ b/Documentation/trace/kprobes.rst
@@ -131,8 +131,7 @@ For example, if the function is non-recursive and is called with a
 spinlock held, maxactive = 1 should be enough.  If the function is
 non-recursive and can never relinquish the CPU (e.g., via a semaphore
 or preemption), NR_CPUS should be enough.  If maxactive <= 0, it is
-set to a default value.  If CONFIG_PREEMPT is enabled, the default
-is max(10, 2*NR_CPUS).  Otherwise, the default is NR_CPUS.
+set to a default value: max(10, 2*NR_CPUS).
 
 It's not a disaster if you set maxactive too low; you'll just miss
 some probes.  In the kretprobe struct, the nmissed field is set to
diff --git a/kernel/kprobes.c b/kernel/kprobes.c
index a35074f0daa1a..1c18ecf9f98b1 100644
--- a/kernel/kprobes.c
+++ b/kernel/kprobes.c
@@ -2213,13 +2213,9 @@ int register_kretprobe(struct kretprobe *rp)
 	rp->kp.post_handler = NULL;
 
 	/* Pre-allocate memory for max kretprobe instances */
-	if (rp->maxactive <= 0) {
-#ifdef CONFIG_PREEMPTION
+	if (rp->maxactive <= 0)
 		rp->maxactive = max_t(unsigned int, 10, 2*num_possible_cpus());
-#else
-		rp->maxactive = num_possible_cpus();
-#endif
-	}
+
 #ifdef CONFIG_KRETPROBE_ON_RETHOOK
 	rp->rh = rethook_alloc((void *)rp, kretprobe_rethook_handler);
 	if (!rp->rh)
-- 
GitLab


From b26a124cbfa80f42bfc4e63e1d5643ca98159d66 Mon Sep 17 00:00:00 2001
From: "Masami Hiramatsu (Google)" <mhiramat@kernel.org>
Date: Mon, 14 Nov 2022 13:47:56 +0900
Subject: [PATCH 433/875] tracing/probes: Add symstr type for dynamic events

Add 'symstr' type for storing the kernel symbol as a string data
instead of the symbol address. This allows us to filter the
events by wildcard symbol name.

e.g.
  # echo 'e:wqfunc workqueue.workqueue_execute_start symname=$function:symstr' >> dynamic_events
  # cat events/eprobes/wqfunc/format
  name: wqfunc
  ID: 2110
  format:
  	field:unsigned short common_type;	offset:0;	size:2;	signed:0;
  	field:unsigned char common_flags;	offset:2;	size:1;	signed:0;
  	field:unsigned char common_preempt_count;	offset:3;	size:1;	signed:0;
  	field:int common_pid;	offset:4;	size:4;	signed:1;

  	field:__data_loc char[] symname;	offset:8;	size:4;	signed:1;

  print fmt: " symname=\"%s\"", __get_str(symname)

Note that there is already 'symbol' type which just change the
print format (so it still stores the symbol address in the tracing
ring buffer.) On the other hand, 'symstr' type stores the actual
"symbol+offset/size" data as a string.

Link: https://lore.kernel.org/all/166679930847.1528100.4124308529180235965.stgit@devnote3/

Signed-off-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
---
 Documentation/trace/kprobetrace.rst |  8 +++--
 kernel/trace/trace.c                |  2 +-
 kernel/trace/trace_probe.c          | 44 ++++++++++++++++++---------
 kernel/trace/trace_probe.h          | 16 +++++++---
 kernel/trace/trace_probe_tmpl.h     | 47 +++++++++++++++++++++++++++--
 5 files changed, 91 insertions(+), 26 deletions(-)

diff --git a/Documentation/trace/kprobetrace.rst b/Documentation/trace/kprobetrace.rst
index 4274cc6a2f94f..08a2a6a3782f0 100644
--- a/Documentation/trace/kprobetrace.rst
+++ b/Documentation/trace/kprobetrace.rst
@@ -58,8 +58,8 @@ Synopsis of kprobe_events
   NAME=FETCHARG : Set NAME as the argument name of FETCHARG.
   FETCHARG:TYPE : Set TYPE as the type of FETCHARG. Currently, basic types
 		  (u8/u16/u32/u64/s8/s16/s32/s64), hexadecimal types
-		  (x8/x16/x32/x64), "string", "ustring" and bitfield
-		  are supported.
+		  (x8/x16/x32/x64), "string", "ustring", "symbol", "symstr"
+                  and bitfield are supported.
 
   (\*1) only for the probe on function entry (offs == 0).
   (\*2) only for return probe.
@@ -96,6 +96,10 @@ offset, and container-size (usually 32). The syntax is::
 
 Symbol type('symbol') is an alias of u32 or u64 type (depends on BITS_PER_LONG)
 which shows given pointer in "symbol+offset" style.
+On the other hand, symbol-string type ('symstr') converts the given address to
+"symbol+offset/symbolsize" style and stores it as a null-terminated string.
+With 'symstr' type, you can filter the event with wildcard pattern of the
+symbols, and you don't need to solve symbol name by yourself.
 For $comm, the default type is "string"; any other type is invalid.
 
 .. _user_mem_access:
diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
index c6c7a0af3ed2f..9ee519ad164e9 100644
--- a/kernel/trace/trace.c
+++ b/kernel/trace/trace.c
@@ -5608,7 +5608,7 @@ static const char readme_msg[] =
 	"\t           +|-[u]<offset>(<fetcharg>), \\imm-value, \\\"imm-string\"\n"
 	"\t     type: s8/16/32/64, u8/16/32/64, x8/16/32/64, string, symbol,\n"
 	"\t           b<bit-width>@<bit-offset>/<container-size>, ustring,\n"
-	"\t           <type>\\[<array-size>\\]\n"
+	"\t           symstr, <type>\\[<array-size>\\]\n"
 #ifdef CONFIG_HIST_TRIGGERS
 	"\t    field: <stype> <name>;\n"
 	"\t    stype: u8/u16/u32/u64, s8/s16/s32/s64, pid_t,\n"
diff --git a/kernel/trace/trace_probe.c b/kernel/trace/trace_probe.c
index 36dff277de464..dfec4af857b40 100644
--- a/kernel/trace/trace_probe.c
+++ b/kernel/trace/trace_probe.c
@@ -76,9 +76,11 @@ const char PRINT_TYPE_FMT_NAME(string)[] = "\\\"%s\\\"";
 /* Fetch type information table */
 static const struct fetch_type probe_fetch_types[] = {
 	/* Special types */
-	__ASSIGN_FETCH_TYPE("string", string, string, sizeof(u32), 1,
+	__ASSIGN_FETCH_TYPE("string", string, string, sizeof(u32), 1, 1,
 			    "__data_loc char[]"),
-	__ASSIGN_FETCH_TYPE("ustring", string, string, sizeof(u32), 1,
+	__ASSIGN_FETCH_TYPE("ustring", string, string, sizeof(u32), 1, 1,
+			    "__data_loc char[]"),
+	__ASSIGN_FETCH_TYPE("symstr", string, string, sizeof(u32), 1, 1,
 			    "__data_loc char[]"),
 	/* Basic types */
 	ASSIGN_FETCH_TYPE(u8,  u8,  0),
@@ -662,16 +664,26 @@ static int traceprobe_parse_probe_arg_body(const char *argv, ssize_t *size,
 
 	ret = -EINVAL;
 	/* Store operation */
-	if (!strcmp(parg->type->name, "string") ||
-	    !strcmp(parg->type->name, "ustring")) {
-		if (code->op != FETCH_OP_DEREF && code->op != FETCH_OP_UDEREF &&
-		    code->op != FETCH_OP_IMM && code->op != FETCH_OP_COMM &&
-		    code->op != FETCH_OP_DATA && code->op != FETCH_OP_TP_ARG) {
-			trace_probe_log_err(offset + (t ? (t - arg) : 0),
-					    BAD_STRING);
-			goto fail;
+	if (parg->type->is_string) {
+		if (!strcmp(parg->type->name, "symstr")) {
+			if (code->op != FETCH_OP_REG && code->op != FETCH_OP_STACK &&
+			    code->op != FETCH_OP_RETVAL && code->op != FETCH_OP_ARG &&
+			    code->op != FETCH_OP_DEREF && code->op != FETCH_OP_TP_ARG) {
+				trace_probe_log_err(offset + (t ? (t - arg) : 0),
+						    BAD_SYMSTRING);
+				goto fail;
+			}
+		} else {
+			if (code->op != FETCH_OP_DEREF && code->op != FETCH_OP_UDEREF &&
+			    code->op != FETCH_OP_IMM && code->op != FETCH_OP_COMM &&
+			    code->op != FETCH_OP_DATA && code->op != FETCH_OP_TP_ARG) {
+				trace_probe_log_err(offset + (t ? (t - arg) : 0),
+						    BAD_STRING);
+				goto fail;
+			}
 		}
-		if ((code->op == FETCH_OP_IMM || code->op == FETCH_OP_COMM ||
+		if (!strcmp(parg->type->name, "symstr") ||
+		    (code->op == FETCH_OP_IMM || code->op == FETCH_OP_COMM ||
 		     code->op == FETCH_OP_DATA) || code->op == FETCH_OP_TP_ARG ||
 		     parg->count) {
 			/*
@@ -679,6 +691,8 @@ static int traceprobe_parse_probe_arg_body(const char *argv, ssize_t *size,
 			 * must be kept, and if parg->count != 0, this is an
 			 * array of string pointers instead of string address
 			 * itself.
+			 * For the symstr, it doesn't need to dereference, thus
+			 * it just get the value.
 			 */
 			code++;
 			if (code->op != FETCH_OP_NOP) {
@@ -690,6 +704,8 @@ static int traceprobe_parse_probe_arg_body(const char *argv, ssize_t *size,
 		if (!strcmp(parg->type->name, "ustring") ||
 		    code->op == FETCH_OP_UDEREF)
 			code->op = FETCH_OP_ST_USTRING;
+		else if (!strcmp(parg->type->name, "symstr"))
+			code->op = FETCH_OP_ST_SYMSTR;
 		else
 			code->op = FETCH_OP_ST_STRING;
 		code->size = parg->type->size;
@@ -919,8 +935,7 @@ static int __set_print_fmt(struct trace_probe *tp, char *buf, int len,
 	for (i = 0; i < tp->nr_args; i++) {
 		parg = tp->args + i;
 		if (parg->count) {
-			if ((strcmp(parg->type->name, "string") == 0) ||
-			    (strcmp(parg->type->name, "ustring") == 0))
+			if (parg->type->is_string)
 				fmt = ", __get_str(%s[%d])";
 			else
 				fmt = ", REC->%s[%d]";
@@ -928,8 +943,7 @@ static int __set_print_fmt(struct trace_probe *tp, char *buf, int len,
 				pos += snprintf(buf + pos, LEN_OR_ZERO,
 						fmt, parg->name, j);
 		} else {
-			if ((strcmp(parg->type->name, "string") == 0) ||
-			    (strcmp(parg->type->name, "ustring") == 0))
+			if (parg->type->is_string)
 				fmt = ", __get_str(%s)";
 			else
 				fmt = ", REC->%s";
diff --git a/kernel/trace/trace_probe.h b/kernel/trace/trace_probe.h
index de38f1c037762..0838b74f403b6 100644
--- a/kernel/trace/trace_probe.h
+++ b/kernel/trace/trace_probe.h
@@ -98,6 +98,7 @@ enum fetch_op {
 	FETCH_OP_ST_UMEM,	/* Mem: .offset, .size */
 	FETCH_OP_ST_STRING,	/* String: .offset, .size */
 	FETCH_OP_ST_USTRING,	/* User String: .offset, .size */
+	FETCH_OP_ST_SYMSTR,	/* Kernel Symbol String: .offset, .size */
 	// Stage 4 (modify) op
 	FETCH_OP_MOD_BF,	/* Bitfield: .basesize, .lshift, .rshift */
 	// Stage 5 (loop) op
@@ -133,7 +134,8 @@ struct fetch_insn {
 struct fetch_type {
 	const char		*name;		/* Name of type */
 	size_t			size;		/* Byte size of type */
-	int			is_signed;	/* Signed flag */
+	bool			is_signed;	/* Signed flag */
+	bool			is_string;	/* String flag */
 	print_type_func_t	print;		/* Print functions */
 	const char		*fmt;		/* Format string */
 	const char		*fmttype;	/* Name in format file */
@@ -177,16 +179,19 @@ DECLARE_BASIC_PRINT_TYPE_FUNC(symbol);
 #define _ADDR_FETCH_TYPE(t) __ADDR_FETCH_TYPE(t)
 #define ADDR_FETCH_TYPE _ADDR_FETCH_TYPE(BITS_PER_LONG)
 
-#define __ASSIGN_FETCH_TYPE(_name, ptype, ftype, _size, sign, _fmttype)	\
-	{.name = _name,				\
+#define __ASSIGN_FETCH_TYPE(_name, ptype, ftype, _size, sign, str, _fmttype)	\
+	{.name = _name,					\
 	 .size = _size,					\
-	 .is_signed = sign,				\
+	 .is_signed = (bool)sign,			\
+	 .is_string = (bool)str,			\
 	 .print = PRINT_TYPE_FUNC_NAME(ptype),		\
 	 .fmt = PRINT_TYPE_FMT_NAME(ptype),		\
 	 .fmttype = _fmttype,				\
 	}
+
+/* Non string types can use these macros */
 #define _ASSIGN_FETCH_TYPE(_name, ptype, ftype, _size, sign, _fmttype)	\
-	__ASSIGN_FETCH_TYPE(_name, ptype, ftype, _size, sign, #_fmttype)
+	__ASSIGN_FETCH_TYPE(_name, ptype, ftype, _size, sign, 0, #_fmttype)
 #define ASSIGN_FETCH_TYPE(ptype, ftype, sign)			\
 	_ASSIGN_FETCH_TYPE(#ptype, ptype, ftype, sizeof(ftype), sign, ptype)
 
@@ -431,6 +436,7 @@ extern int traceprobe_define_arg_fields(struct trace_event_call *event_call,
 	C(ARRAY_TOO_BIG,	"Array number is too big"),		\
 	C(BAD_TYPE,		"Unknown type is specified"),		\
 	C(BAD_STRING,		"String accepts only memory argument"),	\
+	C(BAD_SYMSTRING,	"Symbol String doesn't accept data/userdata"),	\
 	C(BAD_BITFIELD,		"Invalid bitfield"),			\
 	C(ARG_NAME_TOO_LONG,	"Argument name is too long"),		\
 	C(NO_ARG_NAME,		"Argument name is not specified"),	\
diff --git a/kernel/trace/trace_probe_tmpl.h b/kernel/trace/trace_probe_tmpl.h
index b3bdb8ddb8622..5cea672243f61 100644
--- a/kernel/trace/trace_probe_tmpl.h
+++ b/kernel/trace/trace_probe_tmpl.h
@@ -67,6 +67,37 @@ probe_mem_read(void *dest, void *src, size_t size);
 static nokprobe_inline int
 probe_mem_read_user(void *dest, void *src, size_t size);
 
+static nokprobe_inline int
+fetch_store_symstrlen(unsigned long addr)
+{
+	char namebuf[KSYM_SYMBOL_LEN];
+	int ret;
+
+	ret = sprint_symbol(namebuf, addr);
+	if (ret < 0)
+		return 0;
+
+	return ret + 1;
+}
+
+/*
+ * Fetch a null-terminated symbol string + offset. Caller MUST set *(u32 *)buf
+ * with max length and relative data location.
+ */
+static nokprobe_inline int
+fetch_store_symstring(unsigned long addr, void *dest, void *base)
+{
+	int maxlen = get_loc_len(*(u32 *)dest);
+	void *__dest;
+
+	if (unlikely(!maxlen))
+		return -ENOMEM;
+
+	__dest = get_loc_data(dest, base);
+
+	return sprint_symbol(__dest, addr);
+}
+
 /* From the 2nd stage, routine is same */
 static nokprobe_inline int
 process_fetch_insn_bottom(struct fetch_insn *code, unsigned long val,
@@ -99,16 +130,22 @@ stage2:
 stage3:
 	/* 3rd stage: store value to buffer */
 	if (unlikely(!dest)) {
-		if (code->op == FETCH_OP_ST_STRING) {
+		switch (code->op) {
+		case FETCH_OP_ST_STRING:
 			ret = fetch_store_strlen(val + code->offset);
 			code++;
 			goto array;
-		} else if (code->op == FETCH_OP_ST_USTRING) {
+		case FETCH_OP_ST_USTRING:
 			ret += fetch_store_strlen_user(val + code->offset);
 			code++;
 			goto array;
-		} else
+		case FETCH_OP_ST_SYMSTR:
+			ret += fetch_store_symstrlen(val + code->offset);
+			code++;
+			goto array;
+		default:
 			return -EILSEQ;
+		}
 	}
 
 	switch (code->op) {
@@ -129,6 +166,10 @@ stage3:
 		loc = *(u32 *)dest;
 		ret = fetch_store_string_user(val + code->offset, dest, base);
 		break;
+	case FETCH_OP_ST_SYMSTR:
+		loc = *(u32 *)dest;
+		ret = fetch_store_symstring(val + code->offset, dest, base);
+		break;
 	default:
 		return -EILSEQ;
 	}
-- 
GitLab


From d4505aa6afae17a20c2f3ccfbfb7a07881b7ae02 Mon Sep 17 00:00:00 2001
From: "Masami Hiramatsu (Google)" <mhiramat@kernel.org>
Date: Mon, 14 Nov 2022 13:47:56 +0900
Subject: [PATCH 434/875] tracing/probes: Reject symbol/symstr type for uprobe

Since uprobe's argument must contain the user-space data, that
should not be converted to kernel symbols. Reject if user
specifies these types on uprobe events. e.g.

 /sys/kernel/debug/tracing # echo 'p /bin/sh:10 %ax:symbol' >> uprobe_events
 sh: write error: Invalid argument
 /sys/kernel/debug/tracing # echo 'p /bin/sh:10 %ax:symstr' >> uprobe_events
 sh: write error: Invalid argument
 /sys/kernel/debug/tracing # cat error_log
 [ 1783.134883] trace_uprobe: error: Unknown type is specified
   Command: p /bin/sh:10 %ax:symbol
                             ^
 [ 1792.201120] trace_uprobe: error: Unknown type is specified
   Command: p /bin/sh:10 %ax:symstr
                             ^
Link: https://lore.kernel.org/all/166679931679.1528100.15540755370726009882.stgit@devnote3/

Signed-off-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
---
 kernel/trace/trace_probe.c                    | 21 ++++++++++++-------
 kernel/trace/trace_probe.h                    |  3 ++-
 kernel/trace/trace_uprobe.c                   |  3 ++-
 .../test.d/kprobe/uprobe_syntax_errors.tc     |  5 +++++
 4 files changed, 22 insertions(+), 10 deletions(-)

diff --git a/kernel/trace/trace_probe.c b/kernel/trace/trace_probe.c
index dfec4af857b40..960bb7693a843 100644
--- a/kernel/trace/trace_probe.c
+++ b/kernel/trace/trace_probe.c
@@ -100,10 +100,15 @@ static const struct fetch_type probe_fetch_types[] = {
 	ASSIGN_FETCH_TYPE_END
 };
 
-static const struct fetch_type *find_fetch_type(const char *type)
+static const struct fetch_type *find_fetch_type(const char *type, unsigned long flags)
 {
 	int i;
 
+	/* Reject the symbol/symstr for uprobes */
+	if (type && (flags & TPARG_FL_USER) &&
+	    (!strcmp(type, "symbol") || !strcmp(type, "symstr")))
+		return NULL;
+
 	if (!type)
 		type = DEFAULT_FETCH_TYPE_STR;
 
@@ -121,13 +126,13 @@ static const struct fetch_type *find_fetch_type(const char *type)
 
 		switch (bs) {
 		case 8:
-			return find_fetch_type("u8");
+			return find_fetch_type("u8", flags);
 		case 16:
-			return find_fetch_type("u16");
+			return find_fetch_type("u16", flags);
 		case 32:
-			return find_fetch_type("u32");
+			return find_fetch_type("u32", flags);
 		case 64:
-			return find_fetch_type("u64");
+			return find_fetch_type("u64", flags);
 		default:
 			goto fail;
 		}
@@ -480,7 +485,7 @@ parse_probe_arg(char *arg, const struct fetch_type *type,
 					    DEREF_OPEN_BRACE);
 			return -EINVAL;
 		} else {
-			const struct fetch_type *t2 = find_fetch_type(NULL);
+			const struct fetch_type *t2 = find_fetch_type(NULL, flags);
 
 			*tmp = '\0';
 			ret = parse_probe_arg(arg, t2, &code, end, flags, offs);
@@ -632,9 +637,9 @@ static int traceprobe_parse_probe_arg_body(const char *argv, ssize_t *size,
 		/* The type of $comm must be "string", and not an array. */
 		if (parg->count || (t && strcmp(t, "string")))
 			goto out;
-		parg->type = find_fetch_type("string");
+		parg->type = find_fetch_type("string", flags);
 	} else
-		parg->type = find_fetch_type(t);
+		parg->type = find_fetch_type(t, flags);
 	if (!parg->type) {
 		trace_probe_log_err(offset + (t ? (t - arg) : 0), BAD_TYPE);
 		goto out;
diff --git a/kernel/trace/trace_probe.h b/kernel/trace/trace_probe.h
index 0838b74f403b6..23acfd1c38122 100644
--- a/kernel/trace/trace_probe.h
+++ b/kernel/trace/trace_probe.h
@@ -358,7 +358,8 @@ int trace_probe_create(const char *raw_command, int (*createfn)(int, const char
 #define TPARG_FL_KERNEL BIT(1)
 #define TPARG_FL_FENTRY BIT(2)
 #define TPARG_FL_TPOINT BIT(3)
-#define TPARG_FL_MASK	GENMASK(3, 0)
+#define TPARG_FL_USER   BIT(4)
+#define TPARG_FL_MASK	GENMASK(4, 0)
 
 extern int traceprobe_parse_probe_arg(struct trace_probe *tp, int i,
 				const char *argv, unsigned int flags);
diff --git a/kernel/trace/trace_uprobe.c b/kernel/trace/trace_uprobe.c
index fb58e86dd1178..8d64b6553aedf 100644
--- a/kernel/trace/trace_uprobe.c
+++ b/kernel/trace/trace_uprobe.c
@@ -691,7 +691,8 @@ static int __trace_uprobe_create(int argc, const char **argv)
 	for (i = 0; i < argc && i < MAX_TRACE_ARGS; i++) {
 		trace_probe_log_set_index(i + 2);
 		ret = traceprobe_parse_probe_arg(&tu->tp, i, argv[i],
-					is_return ? TPARG_FL_RETURN : 0);
+					(is_return ? TPARG_FL_RETURN : 0) |
+					TPARG_FL_USER);
 		if (ret)
 			goto error;
 	}
diff --git a/tools/testing/selftests/ftrace/test.d/kprobe/uprobe_syntax_errors.tc b/tools/testing/selftests/ftrace/test.d/kprobe/uprobe_syntax_errors.tc
index f5e3f9e4a01fe..c817158b99db6 100644
--- a/tools/testing/selftests/ftrace/test.d/kprobe/uprobe_syntax_errors.tc
+++ b/tools/testing/selftests/ftrace/test.d/kprobe/uprobe_syntax_errors.tc
@@ -23,4 +23,9 @@ check_error 'p /bin/sh:10^%hoge'	# BAD_ADDR_SUFFIX
 check_error 'p /bin/sh:10(10)^%return'	# BAD_REFCNT_SUFFIX
 fi
 
+# symstr is not supported by uprobe
+if grep -q ".*symstr.*" README; then
+check_error 'p /bin/sh:10 $stack0:^symstr'	# BAD_TYPE
+fi
+
 exit 0
-- 
GitLab


From f68022ae0aeb0803450e05abc0e984027c33ef1b Mon Sep 17 00:00:00 2001
From: Kristina Martsenko <kristina.martsenko@arm.com>
Date: Fri, 9 Dec 2022 17:34:41 +0000
Subject: [PATCH 435/875] lkdtm: cfi: Make PAC test work with GCC 7 and 8
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The CFI test uses the branch-protection=none compiler attribute to
disable PAC return address protection on a function. While newer GCC
versions support this attribute, older versions (GCC 7 and 8) instead
supported the sign-return-address=none attribute, leading to a build
failure when the test is built with older compilers. Fix it by checking
which attribute is supported and using the correct one.

Fixes: 2e53b877dc12 ("lkdtm: Add CFI_BACKWARD to test ROP mitigations")
Reported-by: Daniel Díaz <daniel.diaz@linaro.org>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Signed-off-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/all/CAEUSe78kDPxQmQqCWW-_9LCgJDFhAeMoVBFnX9QLx18Z4uT4VQ@mail.gmail.com/
---
 drivers/misc/lkdtm/cfi.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/misc/lkdtm/cfi.c b/drivers/misc/lkdtm/cfi.c
index 5245cf6013c95..fc28714ae3a61 100644
--- a/drivers/misc/lkdtm/cfi.c
+++ b/drivers/misc/lkdtm/cfi.c
@@ -54,7 +54,11 @@ static void lkdtm_CFI_FORWARD_PROTO(void)
 # ifdef CONFIG_ARM64_BTI_KERNEL
 #  define __no_pac             "branch-protection=bti"
 # else
-#  define __no_pac             "branch-protection=none"
+#  ifdef CONFIG_CC_HAS_BRANCH_PROT_PAC_RET
+#   define __no_pac            "branch-protection=none"
+#  else
+#   define __no_pac            "sign-return-address=none"
+#  endif
 # endif
 # define __no_ret_protection   __noscs __attribute__((__target__(__no_pac)))
 #else
-- 
GitLab


From d6a9fb87e9d18f3394a9845546bbe868efdccfd2 Mon Sep 17 00:00:00 2001
From: Nathan Chancellor <nathan@kernel.org>
Date: Wed, 14 Dec 2022 16:26:03 -0700
Subject: [PATCH 436/875] security: Restrict CONFIG_ZERO_CALL_USED_REGS to gcc
 or clang > 15.0.6

A bad bug in clang's implementation of -fzero-call-used-regs can result
in NULL pointer dereferences (see the links above the check for more
information). Restrict CONFIG_CC_HAS_ZERO_CALL_USED_REGS to either a
supported GCC version or a clang newer than 15.0.6, which will catch
both a theoretical 15.0.7 and the upcoming 16.0.0, which will both have
the bug fixed.

Cc: stable@vger.kernel.org # v5.15+
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/r/20221214232602.4118147-1-nathan@kernel.org
---
 security/Kconfig.hardening | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/security/Kconfig.hardening b/security/Kconfig.hardening
index d766b7d0ffd13..53baa95cb644f 100644
--- a/security/Kconfig.hardening
+++ b/security/Kconfig.hardening
@@ -257,6 +257,9 @@ config INIT_ON_FREE_DEFAULT_ON
 
 config CC_HAS_ZERO_CALL_USED_REGS
 	def_bool $(cc-option,-fzero-call-used-regs=used-gpr)
+	# https://github.com/ClangBuiltLinux/linux/issues/1766
+	# https://github.com/llvm/llvm-project/issues/59242
+	depends on !CC_IS_CLANG || CLANG_VERSION > 150006
 
 config ZERO_CALL_USED_REGS
 	bool "Enable register zeroing on function exit"
-- 
GitLab


From 76d62f24db07f22ccf9bc18ca793c27d4ebef721 Mon Sep 17 00:00:00 2001
From: John Stultz <jstultz@google.com>
Date: Wed, 14 Dec 2022 23:18:34 +0000
Subject: [PATCH 437/875] pstore: Switch pmsg_lock to an rt_mutex to avoid
 priority inversion

Wei Wang reported seeing priority inversion caused latencies
caused by contention on pmsg_lock, and suggested it be switched
to a rt_mutex.

I was initially hesitant this would help, as the tasks in that
trace all seemed to be SCHED_NORMAL, so the benefit would be
limited to only nice boosting.

However, another similar issue was raised where the priority
inversion was seen did involve a blocked RT task so it is clear
this would be helpful in that case.

Cc: Wei Wang <wvw@google.com>
Cc: Midas Chien<midaschieh@google.com>
Cc: Connor O'Brien <connoro@google.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Anton Vorontsov <anton@enomsg.org>
Cc: Colin Cross <ccross@android.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: kernel-team@android.com
Fixes: 9d5438f462ab ("pstore: Add pmsg - user-space accessible pstore object")
Reported-by: Wei Wang <wvw@google.com>
Signed-off-by: John Stultz <jstultz@google.com>
Signed-off-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/r/20221214231834.3711880-1-jstultz@google.com
---
 fs/pstore/pmsg.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/fs/pstore/pmsg.c b/fs/pstore/pmsg.c
index d8542ec2f38c6..18cf94b597e05 100644
--- a/fs/pstore/pmsg.c
+++ b/fs/pstore/pmsg.c
@@ -7,9 +7,10 @@
 #include <linux/device.h>
 #include <linux/fs.h>
 #include <linux/uaccess.h>
+#include <linux/rtmutex.h>
 #include "internal.h"
 
-static DEFINE_MUTEX(pmsg_lock);
+static DEFINE_RT_MUTEX(pmsg_lock);
 
 static ssize_t write_pmsg(struct file *file, const char __user *buf,
 			  size_t count, loff_t *ppos)
@@ -28,9 +29,9 @@ static ssize_t write_pmsg(struct file *file, const char __user *buf,
 	if (!access_ok(buf, count))
 		return -EFAULT;
 
-	mutex_lock(&pmsg_lock);
+	rt_mutex_lock(&pmsg_lock);
 	ret = psinfo->write_user(&record, buf);
-	mutex_unlock(&pmsg_lock);
+	rt_mutex_unlock(&pmsg_lock);
 	return ret ? ret : count;
 }
 
-- 
GitLab


From cb3543cff90a4448ed560ac86c98033ad5fecda9 Mon Sep 17 00:00:00 2001
From: Johan Hovold <johan+linaro@kernel.org>
Date: Thu, 15 Dec 2022 11:46:46 +0100
Subject: [PATCH 438/875] regulator: core: fix deadlock on regulator enable

When updating the operating mode as part of regulator enable, the caller
has already locked the regulator tree and drms_uA_update() must not try
to do the same in order not to trigger a deadlock.

The lock inversion is reported by lockdep as:

  ======================================================
  WARNING: possible circular locking dependency detected
  6.1.0-next-20221215 #142 Not tainted
  ------------------------------------------------------
  udevd/154 is trying to acquire lock:
  ffffc11f123d7e50 (regulator_list_mutex){+.+.}-{3:3}, at: regulator_lock_dependent+0x54/0x280

  but task is already holding lock:
  ffff80000e4c36e8 (regulator_ww_class_acquire){+.+.}-{0:0}, at: regulator_enable+0x34/0x80

  which lock already depends on the new lock.

  ...

   Possible unsafe locking scenario:

         CPU0                    CPU1
         ----                    ----
    lock(regulator_ww_class_acquire);
                                 lock(regulator_list_mutex);
                                 lock(regulator_ww_class_acquire);
    lock(regulator_list_mutex);

   *** DEADLOCK ***

just before probe of a Qualcomm UFS controller (occasionally) deadlocks
when enabling one of its regulators.

Fixes: 9243a195be7a ("regulator: core: Change voltage setting path")
Fixes: f8702f9e4aa7 ("regulator: core: Use ww_mutex for regulators locking")
Cc: stable@vger.kernel.org      # 5.0
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221215104646.19818-1-johan+linaro@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 drivers/regulator/core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index 35a7785c53f65..c661be129818c 100644
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
@@ -1002,7 +1002,7 @@ static int drms_uA_update(struct regulator_dev *rdev)
 		/* get input voltage */
 		input_uV = 0;
 		if (rdev->supply)
-			input_uV = regulator_get_voltage(rdev->supply);
+			input_uV = regulator_get_voltage_rdev(rdev->supply->rdev);
 		if (input_uV <= 0)
 			input_uV = rdev->constraints->input_uV;
 
-- 
GitLab


From 1eb206208b0f3f707c67134ef6ba394410effb67 Mon Sep 17 00:00:00 2001
From: Yuwei Guan <ssawgyw@gmail.com>
Date: Thu, 10 Nov 2022 19:26:22 +0800
Subject: [PATCH 439/875] block, bfq: only do counting of pending-request for
 BFQ_GROUP_IOSCHED

The 'bfqd->num_groups_with_pending_reqs' is used when
CONFIG_BFQ_GROUP_IOSCHED is enabled, so let the variables and processes
take effect when CONFIG_BFQ_GROUP_IOSCHED is enabled.

Cc: Yu Kuai <yukuai3@huawei.com>
Signed-off-by: Yuwei Guan <Yuwei.Guan@zeekrlife.com>
Reviewed-by: Jan Kara <jack@suse.cz>
Reviewed-by: Yu Kuai <yukuai3@huawei.com>
Link: https://lore.kernel.org/r/20221110112622.389332-1-Yuwei.Guan@zeekrlife.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 block/bfq-iosched.c | 2 ++
 block/bfq-iosched.h | 4 ++++
 block/bfq-wf2q.c    | 8 ++++----
 3 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/block/bfq-iosched.c b/block/bfq-iosched.c
index dc576b90ddfe7..16f43bbc575a0 100644
--- a/block/bfq-iosched.c
+++ b/block/bfq-iosched.c
@@ -7063,7 +7063,9 @@ static int bfq_init_queue(struct request_queue *q, struct elevator_type *e)
 	bfqd->idle_slice_timer.function = bfq_idle_slice_timer;
 
 	bfqd->queue_weights_tree = RB_ROOT_CACHED;
+#ifdef CONFIG_BFQ_GROUP_IOSCHED
 	bfqd->num_groups_with_pending_reqs = 0;
+#endif
 
 	INIT_LIST_HEAD(&bfqd->active_list);
 	INIT_LIST_HEAD(&bfqd->idle_list);
diff --git a/block/bfq-iosched.h b/block/bfq-iosched.h
index 9fa89577322d4..41aa151ccc223 100644
--- a/block/bfq-iosched.h
+++ b/block/bfq-iosched.h
@@ -197,8 +197,10 @@ struct bfq_entity {
 	/* flag, set to request a weight, ioprio or ioprio_class change  */
 	int prio_changed;
 
+#ifdef CONFIG_BFQ_GROUP_IOSCHED
 	/* flag, set if the entity is counted in groups_with_pending_reqs */
 	bool in_groups_with_pending_reqs;
+#endif
 
 	/* last child queue of entity created (for non-leaf entities) */
 	struct bfq_queue *last_bfqq_created;
@@ -491,6 +493,7 @@ struct bfq_data {
 	 */
 	struct rb_root_cached queue_weights_tree;
 
+#ifdef CONFIG_BFQ_GROUP_IOSCHED
 	/*
 	 * Number of groups with at least one process that
 	 * has at least one request waiting for completion. Note that
@@ -538,6 +541,7 @@ struct bfq_data {
 	 * with no request waiting for completion.
 	 */
 	unsigned int num_groups_with_pending_reqs;
+#endif
 
 	/*
 	 * Per-class (RT, BE, IDLE) number of bfq_queues containing
diff --git a/block/bfq-wf2q.c b/block/bfq-wf2q.c
index b02b53658ed46..ea4c3d757fdd1 100644
--- a/block/bfq-wf2q.c
+++ b/block/bfq-wf2q.c
@@ -1612,28 +1612,28 @@ void bfq_requeue_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq,
 
 void bfq_add_bfqq_in_groups_with_pending_reqs(struct bfq_queue *bfqq)
 {
+#ifdef CONFIG_BFQ_GROUP_IOSCHED
 	struct bfq_entity *entity = &bfqq->entity;
 
 	if (!entity->in_groups_with_pending_reqs) {
 		entity->in_groups_with_pending_reqs = true;
-#ifdef CONFIG_BFQ_GROUP_IOSCHED
 		if (!(bfqq_group(bfqq)->num_queues_with_pending_reqs++))
 			bfqq->bfqd->num_groups_with_pending_reqs++;
-#endif
 	}
+#endif
 }
 
 void bfq_del_bfqq_in_groups_with_pending_reqs(struct bfq_queue *bfqq)
 {
+#ifdef CONFIG_BFQ_GROUP_IOSCHED
 	struct bfq_entity *entity = &bfqq->entity;
 
 	if (entity->in_groups_with_pending_reqs) {
 		entity->in_groups_with_pending_reqs = false;
-#ifdef CONFIG_BFQ_GROUP_IOSCHED
 		if (!(--bfqq_group(bfqq)->num_queues_with_pending_reqs))
 			bfqq->bfqd->num_groups_with_pending_reqs--;
-#endif
 	}
+#endif
 }
 
 /*
-- 
GitLab


From d36a9ea5e7766961e753ee38d4c331bbe6ef659b Mon Sep 17 00:00:00 2001
From: Ming Lei <ming.lei@redhat.com>
Date: Thu, 15 Dec 2022 10:16:29 +0800
Subject: [PATCH 440/875] block: fix use-after-free of q->q_usage_counter

For blk-mq, queue release handler is usually called after
blk_mq_freeze_queue_wait() returns. However, the
q_usage_counter->release() handler may not be run yet at that time, so
this can cause a use-after-free.

Fix the issue by moving percpu_ref_exit() into blk_free_queue_rcu().
Since ->release() is called with rcu read lock held, it is agreed that
the race should be covered in caller per discussion from the two links.

Reported-by: Zhang Wensheng <zhangwensheng@huaweicloud.com>
Reported-by: Zhong Jinghua <zhongjinghua@huawei.com>
Link: https://lore.kernel.org/linux-block/Y5prfOjyyjQKUrtH@T590/T/#u
Link: https://lore.kernel.org/lkml/Y4%2FmzMd4evRg9yDi@fedora/
Cc: Hillf Danton <hdanton@sina.com>
Cc: Yu Kuai <yukuai3@huawei.com>
Cc: Dennis Zhou <dennis@kernel.org>
Fixes: 2b0d3d3e4fcf ("percpu_ref: reduce memory footprint of percpu_ref in fast path")
Signed-off-by: Ming Lei <ming.lei@redhat.com>
Link: https://lore.kernel.org/r/20221215021629.74870-1-ming.lei@redhat.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 block/blk-core.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/block/blk-core.c b/block/blk-core.c
index 3866b6c4cd889..9321767470dc5 100644
--- a/block/blk-core.c
+++ b/block/blk-core.c
@@ -254,14 +254,15 @@ EXPORT_SYMBOL_GPL(blk_clear_pm_only);
 
 static void blk_free_queue_rcu(struct rcu_head *rcu_head)
 {
-	kmem_cache_free(blk_requestq_cachep,
-			container_of(rcu_head, struct request_queue, rcu_head));
+	struct request_queue *q = container_of(rcu_head,
+			struct request_queue, rcu_head);
+
+	percpu_ref_exit(&q->q_usage_counter);
+	kmem_cache_free(blk_requestq_cachep, q);
 }
 
 static void blk_free_queue(struct request_queue *q)
 {
-	percpu_ref_exit(&q->q_usage_counter);
-
 	if (q->poll_stat)
 		blk_stat_remove_callback(q, q->poll_cb);
 	blk_stat_free_callback(q->poll_cb);
-- 
GitLab


From a12a383e59ce486abd719b6bda33c353a3b385e7 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Thu, 15 Dec 2022 14:43:37 +0100
Subject: [PATCH 441/875] ASoC: lochnagar: Fix unused lochnagar_of_match
 warning
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

lochnagar_of_match is used unconditionally, so COMPILE_TEST builds
without OF warn:

  sound/soc/codecs/lochnagar-sc.c:247:34: error: ‘lochnagar_of_match’ defined but not used [-Werror=unused-const-variable=]

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221215134337.77944-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/codecs/lochnagar-sc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/codecs/lochnagar-sc.c b/sound/soc/codecs/lochnagar-sc.c
index 13fbd8830b09f..5e0bd0d24ed37 100644
--- a/sound/soc/codecs/lochnagar-sc.c
+++ b/sound/soc/codecs/lochnagar-sc.c
@@ -253,7 +253,7 @@ MODULE_DEVICE_TABLE(of, lochnagar_of_match);
 static struct platform_driver lochnagar_sc_codec_driver = {
 	.driver = {
 		.name = "lochnagar-soundcard",
-		.of_match_table = of_match_ptr(lochnagar_of_match),
+		.of_match_table = lochnagar_of_match,
 	},
 
 	.probe = lochnagar_sc_probe,
-- 
GitLab


From a8cf95f93610eb8282f8b6d0117ba78b74588d6b Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Fri, 2 Dec 2022 17:47:25 +0000
Subject: [PATCH 442/875] io_uring: fix overflow handling regression

Because the single task locking series got reordered ahead of the
timeout and completion lock changes, two hunks inadvertently ended up
using __io_fill_cqe_req() rather than io_fill_cqe_req(). This meant
that we dropped overflow handling in those two spots. Reinstate the
correct CQE filling helper.

Fixes: f66f73421f0a ("io_uring: skip spinlocking for ->task_complete")
Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 io_uring/io_uring.c | 2 +-
 io_uring/rw.c       | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/io_uring/io_uring.c b/io_uring/io_uring.c
index fc64072c53eb3..4601e48a173d1 100644
--- a/io_uring/io_uring.c
+++ b/io_uring/io_uring.c
@@ -927,7 +927,7 @@ static void __io_req_complete_post(struct io_kiocb *req)
 
 	io_cq_lock(ctx);
 	if (!(req->flags & REQ_F_CQE_SKIP))
-		__io_fill_cqe_req(ctx, req);
+		io_fill_cqe_req(ctx, req);
 
 	/*
 	 * If we're the last reference to this request, add to our locked
diff --git a/io_uring/rw.c b/io_uring/rw.c
index b9cac5706e8da..8227af2e1c0f5 100644
--- a/io_uring/rw.c
+++ b/io_uring/rw.c
@@ -1062,7 +1062,7 @@ int io_do_iopoll(struct io_ring_ctx *ctx, bool force_nonspin)
 			continue;
 
 		req->cqe.flags = io_put_kbuf(req, 0);
-		__io_fill_cqe_req(req->ctx, req);
+		io_fill_cqe_req(req->ctx, req);
 	}
 
 	if (unlikely(!nr_events))
-- 
GitLab


From 1794f6a9535bb5234c2b747d1bc6dad03249245a Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Fri, 2 Dec 2022 13:56:35 +0800
Subject: [PATCH 443/875] drm/amd/pm: enable GPO dynamic control support for
 SMU13.0.0

To better support UMD pstate profilings, the GPO feature needs
to be switched on/off accordingly.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.0.x
---
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h      |  3 ++-
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h      |  3 +++
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c    | 15 +++++++++++++++
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  |  2 ++
 4 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
index a4e3425b1027c..4180c71d930f1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
@@ -241,7 +241,8 @@
 	__SMU_DUMMY_MAP(GetGfxOffEntryCount),		 \
 	__SMU_DUMMY_MAP(LogGfxOffResidency),			\
 	__SMU_DUMMY_MAP(SetNumBadMemoryPagesRetired),		\
-	__SMU_DUMMY_MAP(SetBadMemoryPagesRetiredFlagsPerChannel),
+	__SMU_DUMMY_MAP(SetBadMemoryPagesRetiredFlagsPerChannel), \
+	__SMU_DUMMY_MAP(AllowGpo),
 
 #undef __SMU_DUMMY_MAP
 #define __SMU_DUMMY_MAP(type)	SMU_MSG_##type
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index 865d6358918d2..ea29ac6a80e69 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -272,6 +272,9 @@ int smu_v13_0_init_pptable_microcode(struct smu_context *smu);
 
 int smu_v13_0_run_btc(struct smu_context *smu);
 
+int smu_v13_0_gpo_control(struct smu_context *smu,
+			  bool enablement);
+
 int smu_v13_0_deep_sleep_control(struct smu_context *smu,
 				 bool enablement);
 
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index f5e90e0a99dfe..e3a80ac987df1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -2180,6 +2180,21 @@ int smu_v13_0_run_btc(struct smu_context *smu)
 	return res;
 }
 
+int smu_v13_0_gpo_control(struct smu_context *smu,
+			  bool enablement)
+{
+	int res;
+
+	res = smu_cmn_send_smc_msg_with_param(smu,
+					      SMU_MSG_AllowGpo,
+					      enablement ? 1 : 0,
+					      NULL);
+	if (res)
+		dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement);
+
+	return res;
+}
+
 int smu_v13_0_deep_sleep_control(struct smu_context *smu,
 				 bool enablement)
 {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 21d89c3302f1e..cc66828c7a846 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -144,6 +144,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] =
 	MSG_MAP(SetNumBadMemoryPagesRetired,	PPSMC_MSG_SetNumBadMemoryPagesRetired,   0),
 	MSG_MAP(SetBadMemoryPagesRetiredFlagsPerChannel,
 			    PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel,   0),
+	MSG_MAP(AllowGpo,			PPSMC_MSG_SetGpoAllow,           0),
 };
 
 static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = {
@@ -1949,6 +1950,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
 	.set_df_cstate = smu_v13_0_0_set_df_cstate,
 	.send_hbm_bad_pages_num = smu_v13_0_0_smu_send_bad_mem_page_num,
 	.send_hbm_bad_channel_flag = smu_v13_0_0_send_bad_mem_channel_flag,
+	.gpo_control = smu_v13_0_gpo_control,
 };
 
 void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
-- 
GitLab


From 62b9f835a6c60171845642afec4ce4b44865f10f Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Fri, 2 Dec 2022 14:03:45 +0800
Subject: [PATCH 444/875] drm/amd/pm: enable GPO dynamic control support for
 SMU13.0.7

To better support UMD pstate profilings, the GPO feature needs
to be switched on/off accordingly.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.0.x
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index c270f94a1b86f..ab1c004606be1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -123,6 +123,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] =
 	MSG_MAP(SetMGpuFanBoostLimitRpm,	PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),
 	MSG_MAP(DFCstateControl,		PPSMC_MSG_SetExternalClientDfCstateAllow, 0),
 	MSG_MAP(ArmD3,				PPSMC_MSG_ArmD3,                       0),
+	MSG_MAP(AllowGpo,			PPSMC_MSG_SetGpoAllow,           0),
 };
 
 static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = {
@@ -1690,6 +1691,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
 	.mode1_reset = smu_v13_0_mode1_reset,
 	.set_mp1_state = smu_v13_0_7_set_mp1_state,
 	.set_df_cstate = smu_v13_0_7_set_df_cstate,
+	.gpo_control = smu_v13_0_gpo_control,
 };
 
 void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)
-- 
GitLab


From 32a7819ff8e25375c7515aaae5cfcb8c44a461b7 Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Mon, 5 Dec 2022 14:53:34 +0800
Subject: [PATCH 445/875] drm/amd/pm: correct SMU13.0.0 pstate profiling clock
 settings

Correct the pstate standard/peak profiling mode clock settings
for SMU13.0.0.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.0.x
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 22 +++++++++++++------
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index cc66828c7a846..d689fcab963d9 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -1307,9 +1307,17 @@ static int smu_v13_0_0_populate_umd_state_clk(struct smu_context *smu)
 				&dpm_context->dpm_tables.fclk_table;
 	struct smu_umd_pstate_table *pstate_table =
 				&smu->pstate_table;
+	struct smu_table_context *table_context = &smu->smu_table;
+	PPTable_t *pptable = table_context->driver_pptable;
+	DriverReportedClocks_t driver_clocks =
+			pptable->SkuTable.DriverReportedClocks;
 
 	pstate_table->gfxclk_pstate.min = gfx_table->min;
-	pstate_table->gfxclk_pstate.peak = gfx_table->max;
+	if (driver_clocks.GameClockAc &&
+	    (driver_clocks.GameClockAc < gfx_table->max))
+		pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc;
+	else
+		pstate_table->gfxclk_pstate.peak = gfx_table->max;
 
 	pstate_table->uclk_pstate.min = mem_table->min;
 	pstate_table->uclk_pstate.peak = mem_table->max;
@@ -1326,12 +1334,12 @@ static int smu_v13_0_0_populate_umd_state_clk(struct smu_context *smu)
 	pstate_table->fclk_pstate.min = fclk_table->min;
 	pstate_table->fclk_pstate.peak = fclk_table->max;
 
-	/*
-	 * For now, just use the mininum clock frequency.
-	 * TODO: update them when the real pstate settings available
-	 */
-	pstate_table->gfxclk_pstate.standard = gfx_table->min;
-	pstate_table->uclk_pstate.standard = mem_table->min;
+	if (driver_clocks.BaseClockAc &&
+	    driver_clocks.BaseClockAc < gfx_table->max)
+		pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc;
+	else
+		pstate_table->gfxclk_pstate.standard = gfx_table->max;
+	pstate_table->uclk_pstate.standard = mem_table->max;
 	pstate_table->socclk_pstate.standard = soc_table->min;
 	pstate_table->vclk_pstate.standard = vclk_table->min;
 	pstate_table->dclk_pstate.standard = dclk_table->min;
-- 
GitLab


From 7a18e089eff02f17eaee49fc18641f5d16a8284b Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Mon, 5 Dec 2022 15:33:31 +0800
Subject: [PATCH 446/875] drm/amd/pm: update SMU13.0.0 reported maximum shader
 clock

Update the reported maximum shader clock to the value which can
be guarded to be achieved on all cards. This is to align with
Window setting.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.0.x
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 70 ++++++++++++++++++-
 1 file changed, 69 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index d689fcab963d9..713fb6ad39f66 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -543,6 +543,23 @@ static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu)
 						     dpm_table);
 		if (ret)
 			return ret;
+
+		/*
+		 * Update the reported maximum shader clock to the value
+		 * which can be guarded to be achieved on all cards. This
+		 * is aligned with Window setting. And considering that value
+		 * might be not the peak frequency the card can achieve, it
+		 * is normal some real-time clock frequency can overtake this
+		 * labelled maximum clock frequency(for example in pp_dpm_sclk
+		 * sysfs output).
+		 */
+		if (skutable->DriverReportedClocks.GameClockAc &&
+		    (dpm_table->dpm_levels[dpm_table->count - 1].value >
+		    skutable->DriverReportedClocks.GameClockAc)) {
+			dpm_table->dpm_levels[dpm_table->count - 1].value =
+				skutable->DriverReportedClocks.GameClockAc;
+			dpm_table->max = skutable->DriverReportedClocks.GameClockAc;
+		}
 	} else {
 		dpm_table->count = 1;
 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
@@ -805,6 +822,57 @@ static int smu_v13_0_0_get_smu_metrics_data(struct smu_context *smu,
 	return ret;
 }
 
+static int smu_v13_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
+					     enum smu_clk_type clk_type,
+					     uint32_t *min,
+					     uint32_t *max)
+{
+	struct smu_13_0_dpm_context *dpm_context =
+		smu->smu_dpm.dpm_context;
+	struct smu_13_0_dpm_table *dpm_table;
+
+	switch (clk_type) {
+	case SMU_MCLK:
+	case SMU_UCLK:
+		/* uclk dpm table */
+		dpm_table = &dpm_context->dpm_tables.uclk_table;
+		break;
+	case SMU_GFXCLK:
+	case SMU_SCLK:
+		/* gfxclk dpm table */
+		dpm_table = &dpm_context->dpm_tables.gfx_table;
+		break;
+	case SMU_SOCCLK:
+		/* socclk dpm table */
+		dpm_table = &dpm_context->dpm_tables.soc_table;
+		break;
+	case SMU_FCLK:
+		/* fclk dpm table */
+		dpm_table = &dpm_context->dpm_tables.fclk_table;
+		break;
+	case SMU_VCLK:
+	case SMU_VCLK1:
+		/* vclk dpm table */
+		dpm_table = &dpm_context->dpm_tables.vclk_table;
+		break;
+	case SMU_DCLK:
+	case SMU_DCLK1:
+		/* dclk dpm table */
+		dpm_table = &dpm_context->dpm_tables.dclk_table;
+		break;
+	default:
+		dev_err(smu->adev->dev, "Unsupported clock type!\n");
+		return -EINVAL;
+	}
+
+	if (min)
+		*min = dpm_table->min;
+	if (max)
+		*max = dpm_table->max;
+
+	return 0;
+}
+
 static int smu_v13_0_0_read_sensor(struct smu_context *smu,
 				   enum amd_pp_sensors sensor,
 				   void *data,
@@ -1910,7 +1978,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
 	.get_enabled_mask = smu_cmn_get_enabled_mask,
 	.dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
 	.dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
-	.get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq,
+	.get_dpm_ultimate_freq = smu_v13_0_0_get_dpm_ultimate_freq,
 	.get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
 	.read_sensor = smu_v13_0_0_read_sensor,
 	.feature_is_enabled = smu_cmn_feature_is_enabled,
-- 
GitLab


From abe3bf7425fb695a9b37394af18b9ea58a800802 Mon Sep 17 00:00:00 2001
From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Date: Mon, 12 Dec 2022 21:14:17 +0100
Subject: [PATCH 447/875] btrfs: fix an error handling path in btrfs_rename()

If new_whiteout_inode() fails, some resources need to be freed.
Add the missing goto to the error handling path.

Fixes: ab3c5c18e8fa ("btrfs: setup qstr from dentrys using fscrypt helper")
Reviewed-by: Sweet Tea Dorminy <sweettea-kernel@dorminy.me>
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Reviewed-by: David Sterba <dsterba@suse.com>
Signed-off-by: David Sterba <dsterba@suse.com>
---
 fs/btrfs/inode.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index 905ea19df125b..bfcbe64eb8b3a 100644
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c
@@ -9377,8 +9377,10 @@ static int btrfs_rename(struct user_namespace *mnt_userns,
 
 	if (flags & RENAME_WHITEOUT) {
 		whiteout_args.inode = new_whiteout_inode(mnt_userns, old_dir);
-		if (!whiteout_args.inode)
-			return -ENOMEM;
+		if (!whiteout_args.inode) {
+			ret = -ENOMEM;
+			goto out_fscrypt_names;
+		}
 		ret = btrfs_new_inode_prepare(&whiteout_args, &trans_num_items);
 		if (ret)
 			goto out_whiteout_inode;
-- 
GitLab


From db0a4a7b8e95f9312a59a67cbd5bc589f090e13d Mon Sep 17 00:00:00 2001
From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Date: Mon, 12 Dec 2022 21:01:43 +0100
Subject: [PATCH 448/875] btrfs: fix an error handling path in
 btrfs_defrag_leaves()

All error handling paths end to 'out', except this memory allocation
failure.

This is spurious. So branch to the error handling path also in this case.
It will add a call to:

	memset(&root->defrag_progress, 0,
	       sizeof(root->defrag_progress));

Fixes: 6702ed490ca0 ("Btrfs: Add run time btree defrag, and an ioctl to force btree defrag")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Reviewed-by: David Sterba <dsterba@suse.com>
Signed-off-by: David Sterba <dsterba@suse.com>
---
 fs/btrfs/defrag.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/fs/btrfs/defrag.c b/fs/btrfs/defrag.c
index 0a3c261b69c9f..d81b764a76446 100644
--- a/fs/btrfs/defrag.c
+++ b/fs/btrfs/defrag.c
@@ -358,8 +358,10 @@ int btrfs_defrag_leaves(struct btrfs_trans_handle *trans,
 		goto out;
 
 	path = btrfs_alloc_path();
-	if (!path)
-		return -ENOMEM;
+	if (!path) {
+		ret = -ENOMEM;
+		goto out;
+	}
 
 	level = btrfs_header_level(root->node);
 
-- 
GitLab


From c68f72900a12a56c5e9890e6f2ca5119234c9a75 Mon Sep 17 00:00:00 2001
From: Filipe Manana <fdmanana@suse.com>
Date: Tue, 13 Dec 2022 10:42:26 +0000
Subject: [PATCH 449/875] btrfs: fix leak of fs devices after removing btrfs
 module

When removing the btrfs module we are not calling btrfs_cleanup_fs_uuids()
which results in leaking btrfs_fs_devices structures and other resources.
This is a regression recently introduced by a refactoring of the module
initialization and exit sequence, which simply removed the call to
btrfs_cleanup_fs_uuids() in the exit path, resulting in the leaks.

So fix this by calling btrfs_cleanup_fs_uuids() at exit_btrfs_fs().

Fixes: 5565b8e0adcd ("btrfs: make module init/exit match their sequence")
Reviewed-by: Josef Bacik <josef@toxicpanda.com>
Signed-off-by: Filipe Manana <fdmanana@suse.com>
Reviewed-by: David Sterba <dsterba@suse.com>
Signed-off-by: David Sterba <dsterba@suse.com>
---
 fs/btrfs/super.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c
index 93f52ee85f6fe..d5de18d6517e7 100644
--- a/fs/btrfs/super.c
+++ b/fs/btrfs/super.c
@@ -2514,6 +2514,7 @@ static __always_inline void btrfs_exit_btrfs_fs(void)
 static void __exit exit_btrfs_fs(void)
 {
 	btrfs_exit_btrfs_fs();
+	btrfs_cleanup_fs_uuids();
 }
 
 static int __init init_btrfs_fs(void)
-- 
GitLab


From f1f0460c0ca97a4a6570f211c81579294a6cc7be Mon Sep 17 00:00:00 2001
From: Josef Bacik <josef@toxicpanda.com>
Date: Tue, 13 Dec 2022 16:57:44 -0500
Subject: [PATCH 450/875] btrfs: restore BTRFS_SEQ_LAST when looking up qgroup
 backref lookup

In the patch a2c8d27e5ee8 ("btrfs: use a structure to pass arguments to
backref walking functions") Filipe converted everybody to using a new
context struct to use for backref lookups, but accidentally dropped the
BTRFS_SEQ_LAST usage that exists for qgroups.  Add this back so we have
the previous behavior.

Fixes: a2c8d27e5ee8 ("btrfs: use a structure to pass arguments to backref walking functions")
Signed-off-by: Josef Bacik <josef@toxicpanda.com>
Reviewed-by: David Sterba <dsterba@suse.com>
Signed-off-by: David Sterba <dsterba@suse.com>
---
 fs/btrfs/qgroup.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/fs/btrfs/qgroup.c b/fs/btrfs/qgroup.c
index 5c636e00d77da..d275bf24b250b 100644
--- a/fs/btrfs/qgroup.c
+++ b/fs/btrfs/qgroup.c
@@ -2787,6 +2787,7 @@ int btrfs_qgroup_account_extents(struct btrfs_trans_handle *trans)
 			 * current root. It's safe inside commit_transaction().
 			 */
 			ctx.trans = trans;
+			ctx.time_seq = BTRFS_SEQ_LAST;
 			ret = btrfs_find_all_roots(&ctx, false);
 			if (ret < 0)
 				goto cleanup;
-- 
GitLab


From 0a3212de8ab3e2ce5808c6265855e528d4a6767b Mon Sep 17 00:00:00 2001
From: Naohiro Aota <naohiro.aota@wdc.com>
Date: Wed, 14 Dec 2022 11:06:07 +0900
Subject: [PATCH 451/875] btrfs: fix trace event name typo for
 FLUSH_DELAYED_REFS

Fix a typo of printing FLUSH_DELAYED_REFS event in flush_space() as
FLUSH_ELAYED_REFS.

Reviewed-by: Johannes Thumshirn <johannes.thumshirn@wdc.com>
Signed-off-by: Naohiro Aota <naohiro.aota@wdc.com>
Reviewed-by: David Sterba <dsterba@suse.com>
Signed-off-by: David Sterba <dsterba@suse.com>
---
 include/trace/events/btrfs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/trace/events/btrfs.h b/include/trace/events/btrfs.h
index 0bce0b4ff2faf..6548b5b5aa608 100644
--- a/include/trace/events/btrfs.h
+++ b/include/trace/events/btrfs.h
@@ -98,7 +98,7 @@ struct raid56_bio_trace_info;
 	EM( FLUSH_DELALLOC_WAIT,	"FLUSH_DELALLOC_WAIT")		\
 	EM( FLUSH_DELALLOC_FULL,	"FLUSH_DELALLOC_FULL")		\
 	EM( FLUSH_DELAYED_REFS_NR,	"FLUSH_DELAYED_REFS_NR")	\
-	EM( FLUSH_DELAYED_REFS,		"FLUSH_ELAYED_REFS")		\
+	EM( FLUSH_DELAYED_REFS,		"FLUSH_DELAYED_REFS")		\
 	EM( ALLOC_CHUNK,		"ALLOC_CHUNK")			\
 	EM( ALLOC_CHUNK_FORCE,		"ALLOC_CHUNK_FORCE")		\
 	EM( RUN_DELAYED_IPUTS,		"RUN_DELAYED_IPUTS")		\
-- 
GitLab


From 44a84da45272b3f4beb90025a64cfbde18f1aef0 Mon Sep 17 00:00:00 2001
From: Dylan Yudaken <dylany@meta.com>
Date: Thu, 15 Dec 2022 10:41:38 -0800
Subject: [PATCH 452/875] io_uring: use call_rcu_hurry if signaling an eventfd

io_uring uses call_rcu in the case it needs to signal an eventfd as a
result of an eventfd signal, since recursing eventfd signals are not
allowed. This should be calling the new call_rcu_hurry API to not delay
the signal.

Signed-off-by: Dylan Yudaken <dylany@meta.com>

Cc: Joel Fernandes (Google) <joel@joelfernandes.org>
Cc: Paul E. McKenney <paulmck@kernel.org>
Acked-by: Paul E. McKenney <paulmck@kernel.org>
Reviewed-by: Joel Fernandes (Google) <joel@joelfernandes.org>
Link: https://lore.kernel.org/r/20221215184138.795576-1-dylany@meta.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 io_uring/io_uring.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/io_uring/io_uring.c b/io_uring/io_uring.c
index 4601e48a173d1..16a323a9ff70d 100644
--- a/io_uring/io_uring.c
+++ b/io_uring/io_uring.c
@@ -538,7 +538,7 @@ static void io_eventfd_signal(struct io_ring_ctx *ctx)
 	} else {
 		atomic_inc(&ev_fd->refs);
 		if (!atomic_fetch_or(BIT(IO_EVENTFD_OP_SIGNAL_BIT), &ev_fd->ops))
-			call_rcu(&ev_fd->rcu, io_eventfd_ops);
+			call_rcu_hurry(&ev_fd->rcu, io_eventfd_ops);
 		else
 			atomic_dec(&ev_fd->refs);
 	}
-- 
GitLab


From b248586a49a7729f73c504b1e7b958caea45e927 Mon Sep 17 00:00:00 2001
From: Paulo Alcantara <pc@cjr.nz>
Date: Tue, 13 Dec 2022 09:15:23 -0300
Subject: [PATCH 453/875] cifs: set correct tcon status after initial tree
 connect

cifs_tcon::status wasn't correctly updated to TID_GOOD after initial
tree connect thus staying at TID_NEW as long as it was connected.

Cc: stable@vger.kernel.org
Signed-off-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/connect.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c
index e80252a832257..eda75c99a0f57 100644
--- a/fs/cifs/connect.c
+++ b/fs/cifs/connect.c
@@ -2600,6 +2600,7 @@ cifs_get_tcon(struct cifs_ses *ses, struct smb3_fs_context *ctx)
 	tcon->nodelete = ctx->nodelete;
 	tcon->local_lease = ctx->local_lease;
 	INIT_LIST_HEAD(&tcon->pending_opens);
+	tcon->status = TID_GOOD;
 
 	/* schedule query interfaces poll */
 	INIT_DELAYED_WORK(&tcon->query_interfaces,
-- 
GitLab


From 53eab8e76667b124615a943a033cdf97c80c242a Mon Sep 17 00:00:00 2001
From: Jens Axboe <axboe@kernel.dk>
Date: Fri, 16 Dec 2022 08:20:31 -0700
Subject: [PATCH 454/875] block: don't clear REQ_ALLOC_CACHE for non-polled
 requests

Since commit:

b99182c501c3 ("bio: add pcpu caching for non-polling bio_put")

we support bio caching for IRQ based IO as well, hence there's no need
to manually clear REQ_ALLOC_CACHE if we disable polling on a request.

Reviewed-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 include/linux/bio.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/include/linux/bio.h b/include/linux/bio.h
index b231a665682a3..22078a28d7cb1 100644
--- a/include/linux/bio.h
+++ b/include/linux/bio.h
@@ -782,8 +782,7 @@ static inline void bio_set_polled(struct bio *bio, struct kiocb *kiocb)
 
 static inline void bio_clear_polled(struct bio *bio)
 {
-	/* can't support alloc cache if we turn off polling */
-	bio->bi_opf &= ~(REQ_POLLED | REQ_ALLOC_CACHE);
+	bio->bi_opf &= ~REQ_POLLED;
 }
 
 struct bio *blk_next_bio(struct bio *bio, struct block_device *bdev,
-- 
GitLab


From 86fe0fa8747fb1bc4cc44fc1966e0959fe752f38 Mon Sep 17 00:00:00 2001
From: Paulo Alcantara <pc@cjr.nz>
Date: Fri, 16 Dec 2022 14:00:19 -0300
Subject: [PATCH 455/875] cifs: set correct ipc status after initial tree
 connect

cifs_tcon::status wasn't correctly updated to TID_GOOD after
establishing initial IPC connection thus staying at TID_NEW as long as
it wasn't reconnected.

Cc: stable@vger.kernel.org
Signed-off-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/connect.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c
index eda75c99a0f57..f51715d3e2f2e 100644
--- a/fs/cifs/connect.c
+++ b/fs/cifs/connect.c
@@ -1871,6 +1871,9 @@ cifs_setup_ipc(struct cifs_ses *ses, struct smb3_fs_context *ctx)
 
 	cifs_dbg(FYI, "IPC tcon rc=%d ipc tid=0x%x\n", rc, tcon->tid);
 
+	spin_lock(&tcon->tc_lock);
+	tcon->status = TID_GOOD;
+	spin_unlock(&tcon->tc_lock);
 	ses->tcon_ipc = tcon;
 out:
 	return rc;
@@ -2278,10 +2281,10 @@ cifs_get_smb_ses(struct TCP_Server_Info *server, struct smb3_fs_context *ctx)
 	list_add(&ses->smb_ses_list, &server->smb_ses_list);
 	spin_unlock(&cifs_tcp_ses_lock);
 
-	free_xid(xid);
-
 	cifs_setup_ipc(ses, ctx);
 
+	free_xid(xid);
+
 	return ses;
 
 get_ses_fail:
-- 
GitLab


From 7535b832c6399b5ebfc5b53af5c51dd915ee2538 Mon Sep 17 00:00:00 2001
From: Kees Cook <keescook@chromium.org>
Date: Fri, 16 Dec 2022 12:26:57 -0800
Subject: [PATCH 456/875] exit: Use READ_ONCE() for all oops/warn limit reads

Use a temporary variable to take full advantage of READ_ONCE() behavior.
Without this, the report (and even the test) might be out of sync with
the initial test.

Reported-by: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/lkml/Y5x7GXeluFmZ8E0E@hirez.programming.kicks-ass.net
Fixes: 9fc9e278a5c0 ("panic: Introduce warn_limit")
Fixes: d4ccd54d28d3 ("exit: Put an upper limit on how often we can oops")
Cc: "Eric W. Biederman" <ebiederm@xmission.com>
Cc: Jann Horn <jannh@google.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Petr Mladek <pmladek@suse.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Luis Chamberlain <mcgrof@kernel.org>
Cc: Marco Elver <elver@google.com>
Cc: tangmeng <tangmeng@uniontech.com>
Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Cc: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Kees Cook <keescook@chromium.org>
---
 kernel/exit.c  | 6 ++++--
 kernel/panic.c | 7 +++++--
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/kernel/exit.c b/kernel/exit.c
index deffb8e4b1b24..15dc2ec80c467 100644
--- a/kernel/exit.c
+++ b/kernel/exit.c
@@ -931,6 +931,7 @@ void __noreturn make_task_dead(int signr)
 	 * Then do everything else.
 	 */
 	struct task_struct *tsk = current;
+	unsigned int limit;
 
 	if (unlikely(in_interrupt()))
 		panic("Aiee, killing interrupt handler!");
@@ -954,8 +955,9 @@ void __noreturn make_task_dead(int signr)
 	 * To make sure this can't happen, place an upper bound on how often the
 	 * kernel may oops without panic().
 	 */
-	if (atomic_inc_return(&oops_count) >= READ_ONCE(oops_limit) && oops_limit)
-		panic("Oopsed too often (kernel.oops_limit is %d)", oops_limit);
+	limit = READ_ONCE(oops_limit);
+	if (atomic_inc_return(&oops_count) >= limit && limit)
+		panic("Oopsed too often (kernel.oops_limit is %d)", limit);
 
 	/*
 	 * We're taking recursive faults here in make_task_dead. Safest is to just
diff --git a/kernel/panic.c b/kernel/panic.c
index 54deb743b2d5a..7834c9854e026 100644
--- a/kernel/panic.c
+++ b/kernel/panic.c
@@ -231,12 +231,15 @@ static void panic_print_sys_info(bool console_flush)
 
 void check_panic_on_warn(const char *origin)
 {
+	unsigned int limit;
+
 	if (panic_on_warn)
 		panic("%s: panic_on_warn set ...\n", origin);
 
-	if (atomic_inc_return(&warn_count) >= READ_ONCE(warn_limit) && warn_limit)
+	limit = READ_ONCE(warn_limit);
+	if (atomic_inc_return(&warn_count) >= limit && limit)
 		panic("%s: system warned too often (kernel.warn_limit is %d)",
-		      origin, warn_limit);
+		      origin, limit);
 }
 
 /**
-- 
GitLab


From 6434ec0186b80c734aa7a2acf95f75f5c6dd943b Mon Sep 17 00:00:00 2001
From: Jens Axboe <axboe@kernel.dk>
Date: Sat, 17 Dec 2022 13:40:17 -0700
Subject: [PATCH 457/875] io_uring: don't use TIF_NOTIFY_SIGNAL to test for
 availability of task_work

Use task_work_pending() as a better test for whether we have task_work
or not, TIF_NOTIFY_SIGNAL is only valid if the any of the task_work
items had been queued with TWA_SIGNAL as the notification mechanism.
Hence task_work_pending() is a more reliable check.

Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 io_uring/io_uring.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/io_uring/io_uring.h b/io_uring/io_uring.h
index c117e029c8dcc..e9f0d41ebb996 100644
--- a/io_uring/io_uring.h
+++ b/io_uring/io_uring.h
@@ -266,8 +266,7 @@ static inline int io_run_task_work(void)
 
 static inline bool io_task_work_pending(struct io_ring_ctx *ctx)
 {
-	return test_thread_flag(TIF_NOTIFY_SIGNAL) ||
-		!wq_list_empty(&ctx->work_llist);
+	return task_work_pending(current) || !wq_list_empty(&ctx->work_llist);
 }
 
 static inline int io_run_task_work_ctx(struct io_ring_ctx *ctx)
-- 
GitLab


From 35d90f95cfa773b7e3b1f57ba15ce06a470f354c Mon Sep 17 00:00:00 2001
From: Jens Axboe <axboe@kernel.dk>
Date: Sat, 17 Dec 2022 13:42:24 -0700
Subject: [PATCH 458/875] io_uring: include task_work run after scheduling in
 wait for events

It's quite possible that we got woken up because task_work was queued,
and we need to process this task_work to generate the events waited for.
If we return to the wait loop without running task_work, we'll end up
adding the task to the waitqueue again, only to call
io_cqring_wait_schedule() again which will run the task_work. This is
less efficient than it could be, as it requires adding to the cq_wait
queue again. It also triggers the wakeup path for completions as
cq_wait is now non-empty with the task itself, and it'll require another
lock grab and deletion to remove ourselves from the waitqueue.

Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 io_uring/io_uring.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/io_uring/io_uring.c b/io_uring/io_uring.c
index 16a323a9ff70d..ff2bbac1a10f4 100644
--- a/io_uring/io_uring.c
+++ b/io_uring/io_uring.c
@@ -2481,7 +2481,14 @@ static inline int io_cqring_wait_schedule(struct io_ring_ctx *ctx,
 	}
 	if (!schedule_hrtimeout(&timeout, HRTIMER_MODE_ABS))
 		return -ETIME;
-	return 1;
+
+	/*
+	 * Run task_work after scheduling. If we got woken because of
+	 * task_work being processed, run it now rather than let the caller
+	 * do another wait loop.
+	 */
+	ret = io_run_task_work_sig(ctx);
+	return ret < 0 ? ret : 1;
 }
 
 /*
@@ -2546,6 +2553,8 @@ static int io_cqring_wait(struct io_ring_ctx *ctx, int min_events,
 		prepare_to_wait_exclusive(&ctx->cq_wait, &iowq.wq,
 						TASK_INTERRUPTIBLE);
 		ret = io_cqring_wait_schedule(ctx, &iowq, timeout);
+		if (__io_cqring_events_user(ctx) >= min_events)
+			break;
 		cond_resched();
 	} while (ret > 0);
 
-- 
GitLab


From e0cb05a02c5333323a32324d8e4048b7575d8ff5 Mon Sep 17 00:00:00 2001
From: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Date: Mon, 28 Nov 2022 01:24:17 +0530
Subject: [PATCH 459/875] dt-bindings: mailbox: qcom: Add SM4250 APCS
 compatible

Add compatible for the Qualcomm SM4250 APCS block.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
---
 .../devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml       | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
index f24fd84b4b05c..05fbef6486fed 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
@@ -28,6 +28,7 @@ properties:
               - qcom,sc8180x-apss-shared
               - qcom,sdm660-apcs-hmss-global
               - qcom,sdm845-apss-shared
+              - qcom,sm4250-apcs-hmss-global
               - qcom,sm6125-apcs-hmss-global
               - qcom,sm6115-apcs-hmss-global
               - qcom,sm8150-apss-shared
-- 
GitLab


From e2cb0eac3d1d1acc8203634f3243859d95e4b37c Mon Sep 17 00:00:00 2001
From: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Date: Mon, 28 Nov 2022 01:24:18 +0530
Subject: [PATCH 460/875] mailbox: qcom-apcs-ipc: Add SM4250 APCS IPC support

Enable SM4250 APCS IPC support by adding the compatible.
It reuses msm8994_apcs_data.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
---
 drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index f1f0e87a79e66..0e9f9cba86684 100644
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -156,6 +156,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = {
 	{ .compatible = "qcom,sc8180x-apss-shared", .data = &apps_shared_apcs_data },
 	{ .compatible = "qcom,sdm660-apcs-hmss-global", .data = &msm8994_apcs_data },
 	{ .compatible = "qcom,sdm845-apss-shared", .data = &apps_shared_apcs_data },
+	{ .compatible = "qcom,sm4250-apcs-hmss-global", .data = &msm8994_apcs_data },
 	{ .compatible = "qcom,sm6125-apcs-hmss-global", .data = &msm8994_apcs_data },
 	{ .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data },
 	{ .compatible = "qcom,sm6115-apcs-hmss-global", .data = &msm8994_apcs_data },
-- 
GitLab


From 31c8d06e55acc325c64596f148d5405dbe4adf30 Mon Sep 17 00:00:00 2001
From: Nicolas Frayer <nfrayer@baylibre.com>
Date: Tue, 22 Nov 2022 21:22:44 +0100
Subject: [PATCH 461/875] mailbox: config: ti-msgmgr: Default set to ARCH_K3
 for TI msg manager

Defaulting the build to ARCH_K3 for the TI message manager driver.

Signed-off-by: Nicolas Frayer <nfrayer@baylibre.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
---
 drivers/mailbox/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 05d6fae800e37..3515ab67da484 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -136,6 +136,7 @@ config STI_MBOX
 config TI_MESSAGE_MANAGER
 	tristate "Texas Instruments Message Manager Driver"
 	depends on ARCH_KEYSTONE || ARCH_K3
+	default ARCH_K3
 	help
 	  An implementation of Message Manager slave driver for Keystone
 	  and K3 architecture SoCs from Texas Instruments. Message Manager
-- 
GitLab


From 76f708f635403d826ebea17ccce60d47c6671e22 Mon Sep 17 00:00:00 2001
From: Luca Weiss <luca@z3ntu.xyz>
Date: Sun, 16 Oct 2022 11:00:32 +0200
Subject: [PATCH 462/875] dt-bindings: mailbox: qcom-ipcc: Add sc8280xp
 compatible

Document the sc8280xp compatible, and at the same time also make sure
the list is sorted alphabetically.

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
---
 Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
index baca4786ff946..bc599a8646379 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
+++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
@@ -24,12 +24,13 @@ properties:
   compatible:
     items:
       - enum:
+          - qcom,sc7280-ipcc
+          - qcom,sc8280xp-ipcc
           - qcom,sm6350-ipcc
           - qcom,sm6375-ipcc
           - qcom,sm8250-ipcc
           - qcom,sm8350-ipcc
           - qcom,sm8450-ipcc
-          - qcom,sc7280-ipcc
       - const: qcom,ipcc
 
   reg:
-- 
GitLab


From 8b9b08bd8d6adda032ae65a3a2f87ee989500c02 Mon Sep 17 00:00:00 2001
From: ye xingchen <ye.xingchen@zte.com.cn>
Date: Thu, 17 Nov 2022 19:29:11 +0800
Subject: [PATCH 463/875] mailbox: rockchip: Use device_get_match_data() to
 simplify the code

Directly get the match data with device_get_match_data().

Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
---
 drivers/mailbox/rockchip-mailbox.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/mailbox/rockchip-mailbox.c b/drivers/mailbox/rockchip-mailbox.c
index 979acc810f307..e02d3c9e36939 100644
--- a/drivers/mailbox/rockchip-mailbox.c
+++ b/drivers/mailbox/rockchip-mailbox.c
@@ -164,7 +164,6 @@ MODULE_DEVICE_TABLE(of, rockchp_mbox_of_match);
 static int rockchip_mbox_probe(struct platform_device *pdev)
 {
 	struct rockchip_mbox *mb;
-	const struct of_device_id *match;
 	const struct rockchip_mbox_data *drv_data;
 	struct resource *res;
 	int ret, irq, i;
@@ -172,8 +171,7 @@ static int rockchip_mbox_probe(struct platform_device *pdev)
 	if (!pdev->dev.of_node)
 		return -ENODEV;
 
-	match = of_match_node(rockchip_mbox_of_match, pdev->dev.of_node);
-	drv_data = (const struct rockchip_mbox_data *)match->data;
+	drv_data = (const struct rockchip_mbox_data *) device_get_match_data(&pdev->dev);
 
 	mb = devm_kzalloc(&pdev->dev, sizeof(*mb), GFP_KERNEL);
 	if (!mb)
-- 
GitLab


From 23ba2e7fa282dd8e6c51c284ab1ea184c96c88b2 Mon Sep 17 00:00:00 2001
From: Yongqiang Niu <yongqiang.niu@mediatek.com>
Date: Thu, 15 Dec 2022 15:28:03 +0800
Subject: [PATCH 464/875] mailbox: mtk-cmdq: Use GCE_CTRL_BY_SW definition
 instead of number

Use GCE_CTRL_BY_SW definition instead of number

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
---
 drivers/mailbox/mtk-cmdq-mailbox.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 9465f9081515d..c3cb24f51699a 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -38,6 +38,7 @@
 #define CMDQ_THR_PRIORITY		0x40
 
 #define GCE_GCTL_VALUE			0x48
+#define GCE_CTRL_BY_SW				GENMASK(2, 0)
 
 #define CMDQ_THR_ACTIVE_SLOT_CYCLES	0x3200
 #define CMDQ_THR_ENABLED		0x1
@@ -129,7 +130,8 @@ static void cmdq_init(struct cmdq *cmdq)
 
 	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
 	if (cmdq->control_by_sw)
-		writel(0x7, cmdq->base + GCE_GCTL_VALUE);
+		writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
+
 	writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
 	for (i = 0; i <= CMDQ_MAX_EVENT; i++)
 		writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
-- 
GitLab


From 63f40a7f5dbdb70f8574754475346a9e72ccef6c Mon Sep 17 00:00:00 2001
From: Yongqiang Niu <yongqiang.niu@mediatek.com>
Date: Thu, 15 Dec 2022 15:28:04 +0800
Subject: [PATCH 465/875] mailbox: mtk-cmdq: add gce software ddr enable
 private data

if gce work control by software, we need set software enable
for MT8186 Soc

there is a handshake flow between gce and ddr hardware,
if not set ddr enable flag of gce, ddr will fall into idle
mode, then gce instructions will not process done.
we need set this flag of gce to tell ddr when gce is idle or busy
controlled by software flow.

0x48[2:0] means control by software
0x48[18:16] means ddr enable
0x48[2:0] is pre-condition of 0x48[18:16].
if we want set 0x48[18:16] ddr enable, 0x48[2:0] must be set at same
time.
and only these bits is useful, other bits is useless bits

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
---
 drivers/mailbox/mtk-cmdq-mailbox.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index c3cb24f51699a..d2363c6b8b7a5 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -39,6 +39,7 @@
 
 #define GCE_GCTL_VALUE			0x48
 #define GCE_CTRL_BY_SW				GENMASK(2, 0)
+#define GCE_DDR_EN				GENMASK(18, 16)
 
 #define CMDQ_THR_ACTIVE_SLOT_CYCLES	0x3200
 #define CMDQ_THR_ENABLED		0x1
@@ -81,6 +82,7 @@ struct cmdq {
 	bool			suspended;
 	u8			shift_pa;
 	bool			control_by_sw;
+	bool			sw_ddr_en;
 	u32			gce_num;
 };
 
@@ -88,6 +90,7 @@ struct gce_plat {
 	u32 thread_nr;
 	u8 shift;
 	bool control_by_sw;
+	bool sw_ddr_en;
 	u32 gce_num;
 };
 
@@ -127,10 +130,16 @@ static void cmdq_thread_resume(struct cmdq_thread *thread)
 static void cmdq_init(struct cmdq *cmdq)
 {
 	int i;
+	u32 gctl_regval = 0;
 
 	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
 	if (cmdq->control_by_sw)
-		writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
+		gctl_regval = GCE_CTRL_BY_SW;
+	if (cmdq->sw_ddr_en)
+		gctl_regval |= GCE_DDR_EN;
+
+	if (gctl_regval)
+		writel(gctl_regval, cmdq->base + GCE_GCTL_VALUE);
 
 	writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
 	for (i = 0; i <= CMDQ_MAX_EVENT; i++)
@@ -545,6 +554,7 @@ static int cmdq_probe(struct platform_device *pdev)
 	cmdq->thread_nr = plat_data->thread_nr;
 	cmdq->shift_pa = plat_data->shift;
 	cmdq->control_by_sw = plat_data->control_by_sw;
+	cmdq->sw_ddr_en = plat_data->sw_ddr_en;
 	cmdq->gce_num = plat_data->gce_num;
 	cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
 	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
-- 
GitLab


From 7abd037aa581dcdc16c30ebdea758a4e3877f8e1 Mon Sep 17 00:00:00 2001
From: Yongqiang Niu <yongqiang.niu@mediatek.com>
Date: Thu, 15 Dec 2022 15:28:05 +0800
Subject: [PATCH 466/875] mailbox: mtk-cmdq: add gce ddr enable support flow

add gce ddr enable control flow when gce suspend/resume

when all cmdq instruction task has been processed done,
we need set this gce ddr enable to disable status to tell
cmdq hardware gce there is none task need process, and the hardware
can go into idle mode and no access ddr anymore, then the spm can go
into suspend.

the original issue is gce still access ddr when cmdq suspend function
call, but there is no task run.
so, we need control gce access ddr with this flow.
when cmdq suspend function, there is no task need process, we can
disable gce access ddr, to make sure system go into suspend success.

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
---
 drivers/mailbox/mtk-cmdq-mailbox.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index d2363c6b8b7a5..53904511598d9 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -94,6 +94,18 @@ struct gce_plat {
 	u32 gce_num;
 };
 
+static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable)
+{
+	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
+
+	if (enable)
+		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
+	else
+		writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
+
+	clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
+}
+
 u8 cmdq_get_shift_pa(struct mbox_chan *chan)
 {
 	struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
@@ -322,6 +334,9 @@ static int cmdq_suspend(struct device *dev)
 	if (task_running)
 		dev_warn(dev, "exist running task(s) in suspend\n");
 
+	if (cmdq->sw_ddr_en)
+		cmdq_sw_ddr_enable(cmdq, false);
+
 	clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
 
 	return 0;
@@ -333,6 +348,10 @@ static int cmdq_resume(struct device *dev)
 
 	WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks));
 	cmdq->suspended = false;
+
+	if (cmdq->sw_ddr_en)
+		cmdq_sw_ddr_enable(cmdq, true);
+
 	return 0;
 }
 
@@ -340,6 +359,9 @@ static int cmdq_remove(struct platform_device *pdev)
 {
 	struct cmdq *cmdq = platform_get_drvdata(pdev);
 
+	if (cmdq->sw_ddr_en)
+		cmdq_sw_ddr_enable(cmdq, false);
+
 	clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
 	return 0;
 }
-- 
GitLab


From 926d6214f66955f0c066175127cbcf2eaae5ad6b Mon Sep 17 00:00:00 2001
From: Yongqiang Niu <yongqiang.niu@mediatek.com>
Date: Thu, 15 Dec 2022 15:28:06 +0800
Subject: [PATCH 467/875] mailbox: mtk-cmdq: add MT8186 support

add MT8186 cmdq support

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
---
 drivers/mailbox/mtk-cmdq-mailbox.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 53904511598d9..c5229f377c5e3 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -694,9 +694,18 @@ static const struct gce_plat gce_plat_v6 = {
 	.gce_num = 2
 };
 
+static const struct gce_plat gce_plat_v7 = {
+	.thread_nr = 24,
+	.shift = 3,
+	.control_by_sw = true,
+	.sw_ddr_en = true,
+	.gce_num = 1
+};
+
 static const struct of_device_id cmdq_of_ids[] = {
 	{.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},
 	{.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},
+	{.compatible = "mediatek,mt8186-gce", .data = (void *)&gce_plat_v7},
 	{.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4},
 	{.compatible = "mediatek,mt8192-gce", .data = (void *)&gce_plat_v5},
 	{.compatible = "mediatek,mt8195-gce", .data = (void *)&gce_plat_v6},
-- 
GitLab


From ab47d0bfdf88faac0eb02749e5bfaa306e004300 Mon Sep 17 00:00:00 2001
From: Conor Dooley <conor.dooley@microchip.com>
Date: Wed, 23 Nov 2022 17:56:52 +0000
Subject: [PATCH 468/875] mailbox: mpfs: read the system controller's status

Some services explicitly return an error code in their response, but
others rely on the system controller to set a status in its status
register. The meaning of the bits varies based on what service is
requested, so pass it back up to the driver that requested the service
in the first place. The field in the message struct already existed, but
was unused until now.

If the system controller is busy, in which case we should never actually
be in the interrupt handler, or if the service fails the mailbox itself
should not be read. Callers should check the status before operating on
the response.

There's an existing, but unused, #define for the mailbox mask - but it
was incorrect. It was doing a GENMASK_ULL(32, 16) which should've just
been a GENMASK(31, 16), so fix that up and start using it.

Fixes: 83d7b1560810 ("mbox: add polarfire soc system controller mailbox")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
---
 drivers/mailbox/mailbox-mpfs.c | 31 ++++++++++++++++++++++++++++---
 1 file changed, 28 insertions(+), 3 deletions(-)

diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c
index cfacb3f320a64..853901acaeec2 100644
--- a/drivers/mailbox/mailbox-mpfs.c
+++ b/drivers/mailbox/mailbox-mpfs.c
@@ -2,7 +2,7 @@
 /*
  * Microchip PolarFire SoC (MPFS) system controller/mailbox controller driver
  *
- * Copyright (c) 2020 Microchip Corporation. All rights reserved.
+ * Copyright (c) 2020-2022 Microchip Corporation. All rights reserved.
  *
  * Author: Conor Dooley <conor.dooley@microchip.com>
  *
@@ -56,7 +56,7 @@
 #define SCB_STATUS_NOTIFY_MASK BIT(SCB_STATUS_NOTIFY)
 
 #define SCB_STATUS_POS (16)
-#define SCB_STATUS_MASK GENMASK_ULL(SCB_STATUS_POS + SCB_MASK_WIDTH, SCB_STATUS_POS)
+#define SCB_STATUS_MASK GENMASK(SCB_STATUS_POS + SCB_MASK_WIDTH - 1, SCB_STATUS_POS)
 
 struct mpfs_mbox {
 	struct mbox_controller controller;
@@ -130,13 +130,38 @@ static void mpfs_mbox_rx_data(struct mbox_chan *chan)
 	struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv;
 	struct mpfs_mss_response *response = mbox->response;
 	u16 num_words = ALIGN((response->resp_size), (4)) / 4U;
-	u32 i;
+	u32 i, status;
 
 	if (!response->resp_msg) {
 		dev_err(mbox->dev, "failed to assign memory for response %d\n", -ENOMEM);
 		return;
 	}
 
+	/*
+	 * The status is stored in bits 31:16 of the SERVICES_SR register.
+	 * It is only valid when BUSY == 0.
+	 * We should *never* get an interrupt while the controller is
+	 * still in the busy state. If we do, something has gone badly
+	 * wrong & the content of the mailbox would not be valid.
+	 */
+	if (mpfs_mbox_busy(mbox)) {
+		dev_err(mbox->dev, "got an interrupt but system controller is busy\n");
+		response->resp_status = 0xDEAD;
+		return;
+	}
+
+	status = readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET);
+
+	/*
+	 * If the status of the individual servers is non-zero, the service has
+	 * failed. The contents of the mailbox at this point are not be valid,
+	 * so don't bother reading them. Set the status so that the driver
+	 * implementing the service can handle the result.
+	 */
+	response->resp_status = (status & SCB_STATUS_MASK) >> SCB_STATUS_POS;
+	if (response->resp_status)
+		return;
+
 	if (!mpfs_mbox_busy(mbox)) {
 		for (i = 0; i < num_words; i++) {
 			response->resp_msg[i] =
-- 
GitLab


From 359f608f66b4434fb83b74e23ad14631ea3efc4e Mon Sep 17 00:00:00 2001
From: Elvis Wang <Elvis.Wang@mediatek.com>
Date: Thu, 1 Dec 2022 15:13:15 +0800
Subject: [PATCH 469/875] dt-bindings: mailbox: add GCE header file for mt8188

Add Global Command Engine(GCE) header file to define the GCE thread priority,
GCE subsys id, event and constant for mt8188.

Signed-off-by: Elvis Wang <Elvis.Wang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno<angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
---
 .../dt-bindings/mailbox/mediatek,mt8188-gce.h | 967 ++++++++++++++++++
 1 file changed, 967 insertions(+)
 create mode 100644 include/dt-bindings/mailbox/mediatek,mt8188-gce.h

diff --git a/include/dt-bindings/mailbox/mediatek,mt8188-gce.h b/include/dt-bindings/mailbox/mediatek,mt8188-gce.h
new file mode 100644
index 0000000000000..119865787b47c
--- /dev/null
+++ b/include/dt-bindings/mailbox/mediatek,mt8188-gce.h
@@ -0,0 +1,967 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ *
+ */
+#ifndef _DT_BINDINGS_GCE_MT8188_H
+#define _DT_BINDINGS_GCE_MT8188_H
+
+#define CMDQ_THR_PRIO_LOWEST		0
+#define CMDQ_THR_PRIO_1			1
+#define CMDQ_THR_PRIO_2			2
+#define CMDQ_THR_PRIO_3			3
+#define CMDQ_THR_PRIO_4			4
+#define CMDQ_THR_PRIO_5			5
+#define CMDQ_THR_PRIO_6			6
+#define CMDQ_THR_PRIO_HIGHEST		7
+
+#define SUBSYS_1400XXXX                 0
+#define SUBSYS_1401XXXX			1
+#define SUBSYS_1402XXXX			2
+#define SUBSYS_1c00XXXX			3
+#define SUBSYS_1c01XXXX			4
+#define SUBSYS_1c02XXXX			5
+#define SUBSYS_1c10XXXX			6
+#define SUBSYS_1c11XXXX			7
+#define SUBSYS_1c12XXXX			8
+#define SUBSYS_14f0XXXX			9
+#define SUBSYS_14f1XXXX			10
+#define SUBSYS_14f2XXXX			11
+#define SUBSYS_1800XXXX			12
+#define SUBSYS_1801XXXX			13
+#define SUBSYS_1802XXXX			14
+#define SUBSYS_1803XXXX			15
+#define SUBSYS_1032XXXX			16
+#define SUBSYS_1033XXXX			17
+#define SUBSYS_1600XXXX			18
+#define SUBSYS_1601XXXX			19
+#define SUBSYS_14e0XXXX			20
+#define SUBSYS_1c20XXXX			21
+#define SUBSYS_1c30XXXX			22
+#define SUBSYS_1c40XXXX			23
+#define SUBSYS_1c50XXXX			24
+#define SUBSYS_1c60XXXX			25
+#define SUBSYS_NO_SUPPORT		99
+
+#define CMDQ_EVENT_IMG_SOF				0
+#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_0		1
+#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_1		2
+#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_2		3
+#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_3		4
+#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_4		5
+#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_5		6
+#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_6		7
+#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_7		8
+#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_8		9
+#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_9		10
+#define CMDQ_EVENT_IMG_TRAW0_DMA_ERROR_INT		11
+#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_0		12
+#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_1		13
+#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_2		14
+#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_3		15
+#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_4		16
+#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_5		17
+#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_6		18
+#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_7		19
+#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_8		20
+#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_9		21
+#define CMDQ_EVENT_IMG_TRAW1_DMA_ERROR_INT		22
+#define CMDQ_EVENT_IMG_ADL_RESERVED			23
+#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_0		24
+#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_1		25
+#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_2		26
+#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_3		27
+#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_4		28
+#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_5		29
+#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_6		30
+#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_7		31
+#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_8		32
+#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_9		33
+#define CMDQ_EVENT_IMG_DIP_DMA_ERR			34
+#define CMDQ_EVENT_IMG_DIP_NR_DMA_ERR			35
+#define CMDQ_EVENT_DIP_DUMMY_0				36
+#define CMDQ_EVENT_DIP_DUMMY_1				37
+#define CMDQ_EVENT_DIP_DUMMY_2				38
+#define CMDQ_EVENT_IMG_WPE_EIS_GCE_FRAME_DONE	39
+#define CMDQ_EVENT_IMG_WPE_EIS_DONE_SYNC_OUT	40
+#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_0	41
+#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_1	42
+#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_2	43
+#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_3	44
+#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_4	45
+#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_5	46
+#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_6	47
+#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_7	48
+#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_8	49
+#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_9	50
+#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_0	51
+#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_1	52
+#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_2	53
+#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_3	54
+#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_4	55
+#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_5	56
+#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_6	57
+#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_7	58
+#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_8	59
+#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_9	60
+#define CMDQ_EVENT_IMG_PQDIP_A_DMA_ERR		61
+#define CMDQ_EVENT_WPE0_DUMMY_0			62
+#define CMDQ_EVENT_WPE0_DUMMY_1			63
+#define CMDQ_EVENT_WPE0_DUMMY_2			64
+#define CMDQ_EVENT_IMG_WPE_TNR_GCE_FRAME_DONE	65
+#define CMDQ_EVENT_IMG_WPE_TNR_DONE_SYNC_OUT	66
+#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_0	67
+#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_1	68
+#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_2	69
+#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_3	70
+#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_4	71
+#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_5	72
+#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_6	73
+#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_7	74
+#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_8	75
+#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_9	76
+#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_0	77
+#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_1	78
+#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_2	79
+#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_3	80
+#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_4	81
+#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_5	82
+#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_6	83
+#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_7	84
+#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_8	85
+#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_9	86
+#define CMDQ_EVENT_IMG_PQDIP_B_DMA_ERR		87
+#define CMDQ_EVENT_WPE1_DUMMY_0			88
+#define CMDQ_EVENT_WPE1_DUMMY_1			89
+#define CMDQ_EVENT_WPE1_DUMMY_2			90
+#define CMDQ_EVENT_IMG_WPE_LITE_GCE_FRAME_DONE	91
+#define CMDQ_EVENT_IMG_WPE_LITE_DONE_SYNC_OUT	92
+#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_0	93
+#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_1	94
+#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_2	95
+#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_3	96
+#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_4	97
+#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_5	98
+#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_6	99
+#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_7	100
+#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_8	101
+#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_9	102
+#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_0	103
+#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_1	104
+#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_2	105
+#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_3	106
+#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_4	107
+#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_5	108
+#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_6	109
+#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_7	110
+#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_8	111
+#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_9	112
+#define CMDQ_EVENT_IMG_XTRAW_DMA_ERR_EVENT	113
+#define CMDQ_EVENT_WPE2_DUMMY_0			114
+#define CMDQ_EVENT_WPE2_DUMMY_1			115
+#define CMDQ_EVENT_WPE2_DUMMY_2			116
+#define CMDQ_EVENT_IMG_IMGSYS_IPE_DUMMY		117
+#define CMDQ_EVENT_IMG_IMGSYS_IPE_FDVT_DONE	118
+#define CMDQ_EVENT_IMG_IMGSYS_IPE_ME_DONE	119
+#define CMDQ_EVENT_IMG_IMGSYS_IPE_DVS_DONE	120
+#define CMDQ_EVENT_IMG_IMGSYS_IPE_DVP_DONE	121
+#define CMDQ_EVENT_FDVT1_RESERVED		122
+#define CMDQ_EVENT_IMG_ENG_EVENT		123
+#define CMDQ_EVENT_CAMSUBA_SW_PASS1_DONE		129
+#define CMDQ_EVENT_CAMSUBB_SW_PASS1_DONE		130
+#define CMDQ_EVENT_CAMSUBC_SW_PASS1_DONE		131
+#define CMDQ_EVENT_GCAMSV_A_1_SW_PASS1_DONE		132
+#define CMDQ_EVENT_GCAMSV_A_2_SW_PASS1_DONE		133
+#define CMDQ_EVENT_GCAMSV_B_1_SW_PASS1_DONE		134
+#define CMDQ_EVENT_GCAMSV_B_2_SW_PASS1_DONE		135
+#define CMDQ_EVENT_GCAMSV_C_1_SW_PASS1_DONE		136
+#define CMDQ_EVENT_GCAMSV_C_2_SW_PASS1_DONE		137
+#define CMDQ_EVENT_GCAMSV_D_1_SW_PASS1_DONE		138
+#define CMDQ_EVENT_GCAMSV_D_2_SW_PASS1_DONE		139
+#define CMDQ_EVENT_GCAMSV_E_1_SW_PASS1_DONE		140
+#define CMDQ_EVENT_GCAMSV_E_2_SW_PASS1_DONE		141
+#define CMDQ_EVENT_GCAMSV_F_1_SW_PASS1_DONE		142
+#define CMDQ_EVENT_GCAMSV_F_2_SW_PASS1_DONE		143
+#define CMDQ_EVENT_GCAMSV_G_1_SW_PASS1_DONE		144
+#define CMDQ_EVENT_GCAMSV_G_2_SW_PASS1_DONE		145
+#define CMDQ_EVENT_GCAMSV_H_1_SW_PASS1_DONE		146
+#define CMDQ_EVENT_GCAMSV_H_2_SW_PASS1_DONE		147
+#define CMDQ_EVENT_GCAMSV_I_1_SW_PASS1_DONE		148
+#define CMDQ_EVENT_GCAMSV_I_2_SW_PASS1_DONE		149
+#define CMDQ_EVENT_GCAMSV_J_1_SW_PASS1_DONE		150
+#define CMDQ_EVENT_GCAMSV_J_2_SW_PASS1_DONE		151
+#define CMDQ_EVENT_MRAW_0_SW_PASS1_DONE			152
+#define CMDQ_EVENT_MRAW_1_SW_PASS1_DONE			153
+#define CMDQ_EVENT_MRAW_2_SW_PASS1_DONE			154
+#define CMDQ_EVENT_MRAW_3_SW_PASS1_DONE			155
+#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL		156
+#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL		157
+#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL		158
+#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL		159
+#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL		160
+#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL		161
+#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL		162
+#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL		163
+#define CMDQ_EVENT_SENINF_CAM8_FIFO_FULL		164
+#define CMDQ_EVENT_SENINF_CAM9_FIFO_FULL		165
+#define CMDQ_EVENT_SENINF_CAM10_FIFO_FULL		166
+#define CMDQ_EVENT_SENINF_CAM11_FIFO_FULL		167
+#define CMDQ_EVENT_SENINF_CAM12_FIFO_FULL		168
+#define CMDQ_EVENT_SENINF_CAM13_FIFO_FULL		169
+#define CMDQ_EVENT_SENINF_CAM14_FIFO_FULL		170
+#define CMDQ_EVENT_SENINF_CAM15_FIFO_FULL		171
+#define CMDQ_EVENT_SENINF_CAM16_FIFO_FULL		172
+#define CMDQ_EVENT_SENINF_CAM17_FIFO_FULL		173
+#define CMDQ_EVENT_SENINF_CAM18_FIFO_FULL		174
+#define CMDQ_EVENT_SENINF_CAM19_FIFO_FULL		175
+#define CMDQ_EVENT_SENINF_CAM20_FIFO_FULL		176
+#define CMDQ_EVENT_SENINF_CAM21_FIFO_FULL		177
+#define CMDQ_EVENT_SENINF_CAM22_FIFO_FULL		178
+#define CMDQ_EVENT_SENINF_CAM23_FIFO_FULL		179
+#define CMDQ_EVENT_SENINF_CAM24_FIFO_FULL		180
+#define CMDQ_EVENT_SENINF_CAM25_FIFO_FULL		181
+#define CMDQ_EVENT_SENINF_CAM26_FIFO_FULL		182
+#define CMDQ_EVENT_TG_OVRUN_MRAW0_INT			183
+#define CMDQ_EVENT_TG_OVRUN_MRAW1_INT			184
+#define CMDQ_EVENT_TG_OVRUN_MRAW2_INT			185
+#define CMDQ_EVENT_TG_OVRUN_MRAW3_INT			186
+#define CMDQ_EVENT_DMA_R1_ERROR_MRAW0_INT		187
+#define CMDQ_EVENT_DMA_R1_ERROR_MRAW1_INT		188
+#define CMDQ_EVENT_DMA_R1_ERROR_MRAW2_INT		189
+#define CMDQ_EVENT_DMA_R1_ERROR_MRAW3_INT		190
+#define CMDQ_EVENT_PDA0_IRQO_EVENT_DONE_D1		191
+#define CMDQ_EVENT_PDA1_IRQO_EVENT_DONE_D1		192
+#define CMDQ_EVENT_CAM_SUBA_TG_INT1				193
+#define CMDQ_EVENT_CAM_SUBA_TG_INT2				194
+#define CMDQ_EVENT_CAM_SUBA_TG_INT3				195
+#define CMDQ_EVENT_CAM_SUBA_TG_INT4				196
+#define CMDQ_EVENT_CAM_SUBB_TG_INT1				197
+#define CMDQ_EVENT_CAM_SUBB_TG_INT2				198
+#define CMDQ_EVENT_CAM_SUBB_TG_INT3				199
+#define CMDQ_EVENT_CAM_SUBB_TG_INT4				200
+#define CMDQ_EVENT_CAM_SUBC_TG_INT1				201
+#define CMDQ_EVENT_CAM_SUBC_TG_INT2				202
+#define CMDQ_EVENT_CAM_SUBC_TG_INT3				203
+#define CMDQ_EVENT_CAM_SUBC_TG_INT4				204
+#define CMDQ_EVENT_CAM_SUBA_IMGO_R1_LOW_LATENCY_LINE_CNT_INT	205
+#define CMDQ_EVENT_CAM_SUBA_YUVO_R1_LOW_LATENCY_LINE_CNT_INT	206
+#define CMDQ_EVENT_CAM_SUBA_YUVO_R3_LOW_LATENCY_LINE_CNT_INT	207
+#define CMDQ_EVENT_CAM_SUBA_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT	208
+#define CMDQ_EVENT_CAM_SUBB_IMGO_R1_LOW_LATENCY_LINE_CNT_INT	209
+#define CMDQ_EVENT_CAM_SUBB_YUVO_R1_LOW_LATENCY_LINE_CNT_INT	210
+#define CMDQ_EVENT_CAM_SUBB_YUVO_R3_LOW_LATENCY_LINE_CNT_INT	211
+#define CMDQ_EVENT_CAM_SUBB_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT	212
+#define CMDQ_EVENT_CAM_SUBC_IMGO_R1_LOW_LATENCY_LINE_CNT_INT	213
+#define CMDQ_EVENT_CAM_SUBC_YUVO_R1_LOW_LATENCY_LINE_CNT_INT	214
+#define CMDQ_EVENT_CAM_SUBC_YUVO_R3_LOW_LATENCY_LINE_CNT_INT	215
+#define CMDQ_EVENT_CAM_SUBC_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT	216
+#define CMDQ_EVENT_RAW_SEL_SOF_SUBA				217
+#define CMDQ_EVENT_RAW_SEL_SOF_SUBB				218
+#define CMDQ_EVENT_RAW_SEL_SOF_SUBC				219
+#define CMDQ_EVENT_CAM_SUBA_RING_BUFFER_OVERFLOW_INT_IN		220
+#define CMDQ_EVENT_CAM_SUBB_RING_BUFFER_OVERFLOW_INT_IN		221
+#define CMDQ_EVENT_CAM_SUBC_RING_BUFFER_OVERFLOW_INT_IN		222
+#define CMDQ_EVENT_VPP0_MDP_RDMA_SOF				256
+#define CMDQ_EVENT_VPP0_MDP_FG_SOF				257
+#define CMDQ_EVENT_VPP0_STITCH_SOF				258
+#define CMDQ_EVENT_VPP0_MDP_HDR_SOF				259
+#define CMDQ_EVENT_VPP0_MDP_AAL_SOF				260
+#define CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF			261
+#define CMDQ_EVENT_VPP0_MDP_TDSHP_SOF				262
+#define CMDQ_EVENT_VPP0_DISP_COLOR_SOF				263
+#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_SOF			264
+#define CMDQ_EVENT_VPP0_VPP_PADDING_IN_PADDING_SOF		265
+#define CMDQ_EVENT_VPP0_MDP_TCC_IN_SOF				266
+#define CMDQ_EVENT_VPP0_MDP_WROT_SOF				267
+#define CMDQ_EVENT_VPP0_WARP0_MMSYS_TOP_RELAY_SOF_PRE		269
+#define CMDQ_EVENT_VPP0_WARP1_MMSYS_TOP_RELAY_SOF_PRE		270
+#define CMDQ_EVENT_VPP0_VPP1_MMSYS_TOP_RELAY_SOF		271
+#define CMDQ_EVENT_VPP0_VPP1_IN_MMSYS_TOP_RELAY_SOF_PRE		272
+#define CMDQ_EVENT_VPP0_DISP_RDMA_SOF				273
+#define CMDQ_EVENT_VPP0_DISP_WDMA_SOF				274
+#define CMDQ_EVENT_VPP0_MDP_HMS_SOF				275
+#define CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE			288
+#define CMDQ_EVENT_VPP0_MDP_FG_TILE_DONE			289
+#define CMDQ_EVENT_VPP0_STITCH_FRAME_DONE			290
+#define CMDQ_EVENT_VPP0_MDP_HDR_FRAME_DONE			291
+#define CMDQ_EVENT_VPP0_MDP_AAL_FRAME_DONE			292
+#define CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE			293
+#define CMDQ_EVENT_VPP0_MDP_TDSHP_FRAME_DONE			294
+#define CMDQ_EVENT_VPP0_DISP_COLOR_FRAME_DONE			295
+#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_FRAME_DONE		296
+#define CMDQ_EVENT_VPP0_VPP_PADDING_IN_PADDING_FRAME_DONE	297
+#define CMDQ_EVENT_VPP0_MDP_TCC_TCC_FRAME_DONE			298
+#define CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE			299
+#define CMDQ_EVENT_VPP0_DISP_RDMA_FRAME_DONE			305
+#define CMDQ_EVENT_VPP0_DISP_WDMA_FRAME_DONE			306
+#define CMDQ_EVENT_VPP0_MDP_HMS_FRAME_DONE			307
+#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_0		320
+#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_1		321
+#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_2		322
+#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_3		323
+#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_4		324
+#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_5		325
+#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_6		326
+#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_7		327
+#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_8		328
+#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_9		329
+#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_10		330
+#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_11		331
+#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_12		332
+#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_13		333
+#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_14		334
+#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_15		335
+#define CMDQ_EVENT_VPP0_DISP_RDMA_0_UNDERRUN			336
+#define CMDQ_EVENT_VPP0_DISP_RDMA_1_UNDERRUN			337
+#define CMDQ_EVENT_VPP0_U_MERGE4_UNDERRUN			338
+#define CMDQ_EVENT_VPP0_U_VPP_SPLIT_VIDEO_0_OVERFLOW		339
+#define CMDQ_EVENT_VPP0_U_VPP_SPLIT_VIDEO_1_OVERFLOW		340
+#define CMDQ_EVENT_VPP0_DSI_0_UNDERRUN				341
+#define CMDQ_EVENT_VPP0_DSI_1_UNDERRUN				342
+#define CMDQ_EVENT_VPP0_DP_INTF_0				343
+#define CMDQ_EVENT_VPP0_DP_INTF_1				344
+#define CMDQ_EVENT_VPP0_DPI_0					345
+#define CMDQ_EVENT_VPP0_DPI_1					346
+#define CMDQ_EVENT_VPP0_MDP_RDMA_SW_RST_DONE			352
+#define CMDQ_EVENT_VPP0_MDP_RDMA_PM_VALID_EVENT			353
+#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_FRAME_RESET_DONE_PULSE	354
+#define CMDQ_EVENT_VPP0_MDP_WROT_SW_RST_DONE			355
+#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_0		356
+#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_1		357
+#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_2		358
+#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_3		359
+#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_4		360
+#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_5		361
+#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_6		362
+#define CMDQ_EVENT_VPP0_DISP_RDMA_DISP_RDMA_VALID_EVENT		363
+#define CMDQ_EVENT_VPP0_DISP_RDMA_DISP_RDMA_TARGET_LINE_EVENT	364
+#define CMDQ_EVENT_VPP0_DISP_WDMA_SW_RST_DONE			365
+#define CMDQ_EVENT_VPP0_DISP_WDMA_WDMA_VALID_EVENT		366
+#define CMDQ_EVENT_VPP0_DISP_WDMA_WDMA_TARGET_LINE_EVENT	367
+#define CMDQ_EVENT_VPP1_HDMI_META_SOF				384
+#define CMDQ_EVENT_VPP1_DGI_SOF					385
+#define CMDQ_EVENT_VPP1_VPP_SPLIT_SOF				386
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_TCC_SOF			387
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF			388
+#define CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF			389
+#define CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF			390
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_FG_SOF			391
+#define CMDQ_EVENT_VPP1_SVPP2_MDP_FG_SOF			392
+#define CMDQ_EVENT_VPP1_SVPP3_MDP_FG_SOF			393
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_HDR_SOF			394
+#define CMDQ_EVENT_VPP1_SVPP2_MDP_HDR_SOF			395
+#define CMDQ_EVENT_VPP1_SVPP3_MDP_HDR_SOF			396
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_AAL_SOF			397
+#define CMDQ_EVENT_VPP1_SVPP2_MDP_AAL_SOF			398
+#define CMDQ_EVENT_VPP1_SVPP3_MDP_AAL_SOF			399
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF			400
+#define CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF			401
+#define CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF			402
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_TDSHP_SOF			403
+#define CMDQ_EVENT_VPP1_SVPP2_MDP_TDSHP_SOF			404
+#define CMDQ_EVENT_VPP1_SVPP3_MDP_TDSHP_SOF			405
+#define CMDQ_EVENT_VPP1_SVPP2_VPP_MERGE_SOF			406
+#define CMDQ_EVENT_VPP1_SVPP3_VPP_MERGE_SOF			407
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_COLOR_SOF			408
+#define CMDQ_EVENT_VPP1_SVPP2_MDP_COLOR_SOF			409
+#define CMDQ_EVENT_VPP1_SVPP3_MDP_COLOR_SOF			410
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_SOF			411
+#define CMDQ_EVENT_VPP1_SVPP1_VPP_PAD_SOF			412
+#define CMDQ_EVENT_VPP1_SVPP2_VPP_PAD_SOF			413
+#define CMDQ_EVENT_VPP1_SVPP3_VPP_PAD_SOF			414
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF			415
+#define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF			416
+#define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF			417
+#define CMDQ_EVENT_VPP1_VPP0_DL_IRLY_SOF			418
+#define CMDQ_EVENT_VPP1_VPP0_DL_ORLY_SOF			419
+#define CMDQ_EVENT_VPP1_VDO0_DL_ORLY_0_SOF			420
+#define CMDQ_EVENT_VPP1_VDO0_DL_ORLY_1_SOF			421
+#define CMDQ_EVENT_VPP1_VDO1_DL_ORLY_0_SOF			422
+#define CMDQ_EVENT_VPP1_VDO1_DL_ORLY_1_SOF			423
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE		424
+#define CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE		425
+#define CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE		426
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE		427
+#define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE		428
+#define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE		429
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_FRAME_DONE		430
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE		431
+#define CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE		432
+#define CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE		433
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_FG_TILE_DONE			434
+#define CMDQ_EVENT_VPP1_SVPP2_MDP_FG_TILE_DONE			435
+#define CMDQ_EVENT_VPP1_SVPP3_MDP_FG_TILE_DONE			436
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_HDR_FRAME_DONE		437
+#define CMDQ_EVENT_VPP1_SVPP2_MDP_HDR_FRAME_DONE		438
+#define CMDQ_EVENT_VPP1_SVPP3_MDP_HDR_FRAME_DONE		439
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_AAL_FRAME_DONE		440
+#define CMDQ_EVENT_VPP1_SVPP2_MDP_AAL_FRAME_DONE		441
+#define CMDQ_EVENT_VPP1_SVPP3_MDP_AAL_FRAME_DONE		442
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_TDSHP_FRAME_DONE		443
+#define CMDQ_EVENT_VPP1_SVPP2_MDP_TDSHP_FRAME_DONE		444
+#define CMDQ_EVENT_VPP1_SVPP3_MDP_TDSHP_FRAME_DONE		445
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_COLOR_FRAME_DONE		446
+#define CMDQ_EVENT_VPP1_SVPP2_MDP_COLOR_FRAME_DONE		447
+#define CMDQ_EVENT_VPP1_SVPP3_MDP_COLOR_FRAME_DONE		448
+#define CMDQ_EVENT_VPP1_SVPP1_VPP_PAD_FRAME_DONE		449
+#define CMDQ_EVENT_VPP1_SVPP2_VPP_PAD_FRAME_DONE		450
+#define CMDQ_EVENT_VPP1_SVPP3_VPP_PAD_FRAME_DONE		451
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_TCC_FRAME_DONE		452
+#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_0		456
+#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_1		457
+#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_2		458
+#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_3		459
+#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_4		460
+#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_5		461
+#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_6		462
+#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_7		463
+#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_8		464
+#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_9		465
+#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_10		466
+#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_11		467
+#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_12		468
+#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_13		469
+#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_14		470
+#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_15		471
+#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_0		472
+#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_1		473
+#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_2		474
+#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_3		475
+#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_4		476
+#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_5		477
+#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_6		478
+#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_7		479
+#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_8		480
+#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_9		481
+#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_10		482
+#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_11		483
+#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_12		484
+#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_13		485
+#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_14		486
+#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_15		487
+#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_0			488
+#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_1			489
+#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_2			490
+#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_3			491
+#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_4			492
+#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_5			493
+#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_6			494
+#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_7			495
+#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_8			496
+#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_9			497
+#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_10			498
+#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_11			499
+#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_12			500
+#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_13			501
+#define CMDQ_EVENT_VPP1_SVPP3_VPP_MERGE_GCE_EVENT		502
+#define CMDQ_EVENT_VPP1_SVPP2_VPP_MERGE_GCE_EVENT		503
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_GCE_EVENT			504
+#define CMDQ_EVENT_VPP1_VPP_SPLIT_DGI_GCE_EVENT			505
+#define CMDQ_EVENT_VPP1_VPP_SPLIT_HDMI_GCE_EVENT		506
+#define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SW_RST_DONE_GCE_EVENT	507
+#define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SW_RST_DONE_GCE_EVENT	508
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SW_RST_DONE_GCE_EVENT	509
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_NEW_EVENT_0		510
+#define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_NEW_EVENT_1		511
+#define CMDQ_EVENT_VDO0_DISP_OVL0_SOF				512
+#define CMDQ_EVENT_VDO0_DISP_WDMA0_SOF				513
+#define CMDQ_EVENT_VDO0_DISP_RDMA0_SOF				514
+#define CMDQ_EVENT_VDO0_DISP_COLOR0_SOF				515
+#define CMDQ_EVENT_VDO0_DISP_CCORR0_SOF				516
+#define CMDQ_EVENT_VDO0_DISP_AAL0_SOF				517
+#define CMDQ_EVENT_VDO0_DISP_GAMMA0_SOF				518
+#define CMDQ_EVENT_VDO0_DISP_DITHER0_SOF			519
+#define CMDQ_EVENT_VDO0_DSI0_SOF				520
+#define CMDQ_EVENT_VDO0_DSC_WRAP0C0_SOF			521
+#define CMDQ_EVENT_VDO0_DISP_OVL1_SOF			522
+#define CMDQ_EVENT_VDO0_DISP_WDMA1_SOF			523
+#define CMDQ_EVENT_VDO0_DISP_RDMA1_SOF			524
+#define CMDQ_EVENT_VDO0_DISP_COLOR1_SOF			525
+#define CMDQ_EVENT_VDO0_DISP_CCORR1_SOF			526
+#define CMDQ_EVENT_VDO0_DISP_AAL1_SOF			527
+#define CMDQ_EVENT_VDO0_DISP_GAMMA1_SOF			528
+#define CMDQ_EVENT_VDO0_DISP_DITHER1_SOF		529
+#define CMDQ_EVENT_VDO0_DSI1_SOF			530
+#define CMDQ_EVENT_VDO0_DSC_WRAP0C1_SOF			531
+#define CMDQ_EVENT_VDO0_VPP_MERGE0_SOF			532
+#define CMDQ_EVENT_VDO0_DP_INTF0_SOF			533
+#define CMDQ_EVENT_VDO0_DISP_DPI0_SOF			534
+#define CMDQ_EVENT_VDO0_DISP_DPI1_SOF			535
+#define CMDQ_EVENT_VDO0_DISP_POSTMASK0_SOF		536
+#define CMDQ_EVENT_VDO0_MDP_WROT0_SOF			537
+#define CMDQ_EVENT_VDO0_DISP_RSZ0_SOF			538
+#define CMDQ_EVENT_VDO0_VPP1_DL_RELAY0_SOF		539
+#define CMDQ_EVENT_VDO0_VPP1_DL_RELAY1_SOF		540
+#define CMDQ_EVENT_VDO0_VDO1_DL_RELAY2_SOF		541
+#define CMDQ_EVENT_VDO0_VDO0_DL_RELAY3_SOF		542
+#define CMDQ_EVENT_VDO0_VDO0_DL_RELAY4_SOF		543
+#define CMDQ_EVENT_VDO0_DISP_PWM0_SOF			544
+#define CMDQ_EVENT_VDO0_DISP_PWM1_SOF			545
+#define CMDQ_EVENT_VDO0_DISP_OVL0_O_FRAME_DONE		546
+#define CMDQ_EVENT_VDO0_DISP_WDMA0_FRAME_DONE		547
+#define CMDQ_EVENT_VDO0_DISP_RDMA0_FRAME_DONE		548
+#define CMDQ_EVENT_VDO0_DISP_COLOR0_O_FRAME_DONE	549
+#define CMDQ_EVENT_VDO0_DISP_CCORR0_O_FRAME_DONE	550
+#define CMDQ_EVENT_VDO0_DISP_AAL0_O_FRAME_DONE		551
+#define CMDQ_EVENT_VDO0_DISP_GAMMA0_O_FRAME_DONE	552
+#define CMDQ_EVENT_VDO0_DISP_DITHER0_O_FRAME_DONE	553
+#define CMDQ_EVENT_VDO0_DSI0_FRAME_DONE			554
+#define CMDQ_EVENT_VDO0_DSC_WRAP0_O_FRAME_DONE_0	555
+#define CMDQ_EVENT_VDO0_DISP_OVL1_O_FRAME_DONE		556
+#define CMDQ_EVENT_VDO0_DISP_WDMA1_O_FRAME_DONE		557
+#define CMDQ_EVENT_VDO0_DISP_RDMA1_O_FRAME_DONE		558
+#define CMDQ_EVENT_VDO0_DISP_COLOR1_O_FRAME_DONE	559
+#define CMDQ_EVENT_VDO0_DISP_CCORR1_O_FRAME_DONE	560
+#define CMDQ_EVENT_VDO0_DISP_AAL1_O_FRAME_DONE		561
+#define CMDQ_EVENT_VDO0_DISP_GAMMA1_O_FRAME_DONE	562
+#define CMDQ_EVENT_VDO0_DISP_DITHER1_O_FRAME_DONE	563
+#define CMDQ_EVENT_VDO0_DSI1_FRAME_DONE			564
+#define CMDQ_EVENT_VDO0_DSC_WRAP0_O_FRAME_DONE_1	565
+#define CMDQ_EVENT_VDO0_DP_INTF0_FRAME_DONE		567
+#define CMDQ_EVENT_VDO0_DISP_DPI0_O_FRAME_DONE		568
+#define CMDQ_EVENT_VDO0_DISP_DPI1_O_FRAME_DONE		569
+#define CMDQ_EVENT_VDO0_DISP_POSTMASK0_O_FRAME_DONE	570
+#define CMDQ_EVENT_VDO0_MDP_WROT0_O_FRAME_DONE		571
+#define CMDQ_EVENT_VDO0_DISP_RSZ0_O_FRAME_DONE		572
+#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0		574
+#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_1		575
+#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_2		576
+#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_3		577
+#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_4		578
+#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_5		579
+#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_6		580
+#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_7		581
+#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_8		582
+#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_9		583
+#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_10		584
+#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_11		585
+#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_12		586
+#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_13		587
+#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_14		588
+#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_15		589
+#define CMDQ_EVENT_VDO0_DISP_RDMA_0_UNDERRUN		590
+#define CMDQ_EVENT_VDO0_DISP_RDMA_1_UNDERRUN		591
+#define CMDQ_EVENT_VDO0_U_MERGE4_UNDERRUN		592
+#define CMDQ_EVENT_VDO0_DSI_0_UNDERRUN			595
+#define CMDQ_EVENT_VDO0_DSI_1_UNDERRUN			596
+#define CMDQ_EVENT_VDO0_DP_INTF_0			597
+#define CMDQ_EVENT_VDO0_DP_INTF_1			598
+#define CMDQ_EVENT_VDO0_DPI_0				599
+#define CMDQ_EVENT_VDO0_DPI_1				600
+#define CMDQ_EVENT_VDO0_DISP_SMIASSERT_ENG_EVENT	606
+#define CMDQ_EVENT_VDO0_DSI0_O_DSI_IRQ_EVENT_MM		607
+#define CMDQ_EVENT_VDO0_DSI0_TE_ENG_EVENT_MM		608
+#define CMDQ_EVENT_VDO0_DSI0_O_DSI_DONE_EVENT_MM	609
+#define CMDQ_EVENT_VDO0_DSI0_O_DSI_VACTL_EVENT_MM	610
+#define CMDQ_EVENT_VDO0_DSI1_O_DSI_IRQ_EVENT_MM		611
+#define CMDQ_EVENT_VDO0_DSI1_TE_ENG_EVENT_MM		612
+#define CMDQ_EVENT_VDO0_DSI1_O_DSI_DONE_EVENT_MM	613
+#define CMDQ_EVENT_VDO0_DSI1_O_DSI_VACTL_EVENT_MM	614
+#define CMDQ_EVENT_VDO0_DP_INTF0_O_DP_VSYNC_START_EVENT_MM		615
+#define CMDQ_EVENT_VDO0_DP_INTF0_O_DP_VSYNC_END_EVENT_MM		616
+#define CMDQ_EVENT_VDO0_DP_INTF0_O_DP_VDE_START_EVENT_MM		617
+#define CMDQ_EVENT_VDO0_DP_INTF0_O_DP_VDE_END_EVENT_MM			618
+#define CMDQ_EVENT_VDO0_DP_INTF0_O_VACT_TARGET_LINE_EVENT_MM		619
+#define CMDQ_EVENT_VDO0_DP_INTF0_O_LAST_SAFE_BLANK_EVENT_MM		620
+#define CMDQ_EVENT_VDO0_DP_INTF0_O_LAST_LINE_EVENT_MM			621
+#define CMDQ_EVENT_VDO0_DP_INTF0_O_TRIGGER_LOOP_CLEAR_EVENT_MM		622
+#define CMDQ_EVENT_VDO0_DP_INTF0_O_TARGET_LINE_0_EVENT_MM		623
+#define CMDQ_EVENT_VDO0_DP_INTF0_O_TARGET_LINE_1_EVENT_MM		624
+#define CMDQ_EVENT_VDO0_DISP_POSTMASK0_O_FRAME_RESET_DONE_PULSE		625
+#define CMDQ_EVENT_VDO0_VPP_MERGE0_O_VPP_MERGE_EVENT			626
+#define CMDQ_EVENT_VDO0_DISP_OVL0_O_FRAME_RESET_DONE_PULSE		627
+#define CMDQ_EVENT_VDO0_DISP_RDMA0_O_DISP_RDMA_TARGET_LINE_EVENT	628
+#define CMDQ_EVENT_VDO0_DISP_WDMA0_O_WDMA_TARGET_LINE_EVENT		629
+#define CMDQ_EVENT_VDO0_DISP_WDMA0_O_SW_RST_DONE			630
+#define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_0		631
+#define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_1		632
+#define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_2		633
+#define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_3		634
+#define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_4		635
+#define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_5		636
+#define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_6		637
+#define CMDQ_EVENT_VDO0_MDP_WROT0_O_SW_RST_DONE				638
+#define CMDQ_EVENT_VDO0_RESERVED					639
+#define CMDQ_EVENT_VDO1_MDP_RDMA0_SOF				640
+#define CMDQ_EVENT_VDO1_MDP_RDMA1_SOF				641
+#define CMDQ_EVENT_VDO1_MDP_RDMA2_SOF				642
+#define CMDQ_EVENT_VDO1_MDP_RDMA3_SOF				643
+#define CMDQ_EVENT_VDO1_MDP_RDMA4_SOF				644
+#define CMDQ_EVENT_VDO1_MDP_RDMA5_SOF				645
+#define CMDQ_EVENT_VDO1_MDP_RDMA6_SOF				646
+#define CMDQ_EVENT_VDO1_MDP_RDMA7_SOF				647
+#define CMDQ_EVENT_VDO1_DISP_PADDING0_SOF			648
+#define CMDQ_EVENT_VDO1_DISP_PADDING1_SOF			649
+#define CMDQ_EVENT_VDO1_DISP_PADDING2_SOF			650
+#define CMDQ_EVENT_VDO1_DISP_PADDING3_SOF			651
+#define CMDQ_EVENT_VDO1_DISP_PADDING4_SOF			652
+#define CMDQ_EVENT_VDO1_DISP_PADDING5_SOF			653
+#define CMDQ_EVENT_VDO1_DISP_PADDING6_SOF			654
+#define CMDQ_EVENT_VDO1_DISP_PADDING7_SOF			655
+#define CMDQ_EVENT_VDO1_DISP_RSZ0_SOF				656
+#define CMDQ_EVENT_VDO1_DISP_RSZ1_SOF				657
+#define CMDQ_EVENT_VDO1_DISP_RSZ2_SOF				658
+#define CMDQ_EVENT_VDO1_DISP_RSZ3_SOF				659
+#define CMDQ_EVENT_VDO1_VPP_MERGE0_SOF				660
+#define CMDQ_EVENT_VDO1_VPP_MERGE1_SOF				661
+#define CMDQ_EVENT_VDO1_VPP_MERGE2_SOF				662
+#define CMDQ_EVENT_VDO1_VPP_MERGE3_SOF				663
+#define CMDQ_EVENT_VDO1_VPP_MERGE4_SOF				664
+#define CMDQ_EVENT_VDO1_VPP2_DL_RELAY_SOF			665
+#define CMDQ_EVENT_VDO1_VPP3_DL_RELAY_SOF			666
+#define CMDQ_EVENT_VDO0_DSC_DL_ASYNC_SOF			667
+#define CMDQ_EVENT_VDO0_MERGE_DL_ASYNC_SOF			668
+#define CMDQ_EVENT_VDO1_OUT_DL_RELAY_SOF			669
+#define CMDQ_EVENT_VDO1_DISP_MIXER_SOF				670
+#define CMDQ_EVENT_VDO1_HDR_VDO_FE0_SOF				671
+#define CMDQ_EVENT_VDO1_HDR_VDO_FE1_SOF				672
+#define CMDQ_EVENT_VDO1_HDR_GFX_FE0_SOF				673
+#define CMDQ_EVENT_VDO1_HDR_GFX_FE1_SOF				674
+#define CMDQ_EVENT_VDO1_HDR_VDO_BE0_SOF				675
+#define CMDQ_EVENT_VDO1_HDR_MLOAD_SOF				676
+#define CMDQ_EVENT_VDO1_DPI0_EXT_SOF				677
+#define CMDQ_EVENT_VDO1_DPI1_EXT_SOF				678
+#define CMDQ_EVENT_VDO1_DP_INTF_EXT_EXT_SOF			679
+#define CMDQ_EVENT_VDO1_MDP_RDMA0_FRAME_DONE		680
+#define CMDQ_EVENT_VDO1_MDP_RDMA1_FRAME_DONE		681
+#define CMDQ_EVENT_VDO1_MDP_RDMA2_FRAME_DONE		682
+#define CMDQ_EVENT_VDO1_MDP_RDMA3_FRAME_DONE		683
+#define CMDQ_EVENT_VDO1_MDP_RDMA4_FRAME_DONE		684
+#define CMDQ_EVENT_VDO1_MDP_RDMA5_FRAME_DONE		685
+#define CMDQ_EVENT_VDO1_MDP_RDMA6_FRAME_DONE		686
+#define CMDQ_EVENT_VDO1_MDP_RDMA7_FRAME_DONE		687
+#define CMDQ_EVENT_VDO1_DISP_PADDING0_FRAME_DONE	688
+#define CMDQ_EVENT_VDO1_DISP_PADDING1_FRAME_DONE	689
+#define CMDQ_EVENT_VDO1_DISP_PADDING2_FRAME_DONE	690
+#define CMDQ_EVENT_VDO1_DISP_PADDING3_FRAME_DONE	691
+#define CMDQ_EVENT_VDO1_DISP_PADDING4_FRAME_DONE	692
+#define CMDQ_EVENT_VDO1_DISP_PADDING5_FRAME_DONE	693
+#define CMDQ_EVENT_VDO1_DISP_PADDING6_FRAME_DONE	694
+#define CMDQ_EVENT_VDO1_DISP_PADDING7_FRAME_DONE	695
+#define CMDQ_EVENT_VDO1_DISP_RSZ0_FRAME_DONE		696
+#define CMDQ_EVENT_VDO1_DISP_RSZ1_FRAME_DONE		697
+#define CMDQ_EVENT_VDO1_DISP_RSZ2_FRAME_DONE		698
+#define CMDQ_EVENT_VDO1_DISP_RSZ3_FRAME_DONE		699
+#define CMDQ_EVENT_VDO1_VPP_MERGE0_FRAME_DONE		700
+#define CMDQ_EVENT_VDO1_VPP_MERGE1_FRAME_DONE		701
+#define CMDQ_EVENT_VDO1_VPP_MERGE2_FRAME_DONE		702
+#define CMDQ_EVENT_VDO1_VPP_MERGE3_FRAME_DONE		703
+#define CMDQ_EVENT_VDO1_VPP_MERGE4_FRAME_DONE		704
+#define CMDQ_EVENT_VDO1_DPI0_FRAME_DONE			705
+#define CMDQ_EVENT_VDO1_DPI1_FRAME_DONE			706
+#define CMDQ_EVENT_VDO1_DP_INTF0_FRAME_DONE		707
+#define CMDQ_EVENT_VDO1_DISP_MIXER_FRAME_DONE_MM	708
+#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0		709
+#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_1		710
+#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_2		711
+#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_3		712
+#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_4		713
+#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_5		714
+#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_6		715
+#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_7		716
+#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_8		717
+#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_9		718
+#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_10		719
+#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_11		720
+#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_12		721
+#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_13		722
+#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_14		723
+#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_15		724
+#define CMDQ_EVENT_VDO1_DISP_RDMA_0_UNDERRUN		725
+#define CMDQ_EVENT_VDO1_DISP_RDMA_1_UNDERRUN		726
+#define CMDQ_EVENT_VDO1_U_MERGE4_UNDERRUN		727
+#define CMDQ_EVENT_VDO1_U_VPP_SPLIT_VIDEO_0_OVERFLOW	728
+#define CMDQ_EVENT_VDO1_U_VPP_SPLIT_VIDEO_1_OVERFLOW	729
+#define CMDQ_EVENT_VDO1_DSI_0_UNDERRUN			730
+#define CMDQ_EVENT_VDO1_DSI_1_UNDERRUN			731
+#define CMDQ_EVENT_VDO1_DP_INTF_0			732
+#define CMDQ_EVENT_VDO1_DP_INTF_1			733
+#define CMDQ_EVENT_VDO1_DPI_0				734
+#define CMDQ_EVENT_VDO1_DPI_1				735
+#define CMDQ_EVENT_VDO1_MDP_RDMA0_SW_RST_DONE		741
+#define CMDQ_EVENT_VDO1_MDP_RDMA1_SW_RST_DONE		742
+#define CMDQ_EVENT_VDO1_MDP_RDMA2_SW_RST_DONE		743
+#define CMDQ_EVENT_VDO1_MDP_RDMA3_SW_RST_DONE		744
+#define CMDQ_EVENT_VDO1_MDP_RDMA4_SW_RST_DONE		745
+#define CMDQ_EVENT_VDO1_MDP_RDMA5_SW_RST_DONE		746
+#define CMDQ_EVENT_VDO1_MDP_RDMA6_SW_RST_DONE		747
+#define CMDQ_EVENT_VDO1_MDP_RDMA7_SW_RST_DONE		748
+#define CMDQ_EVENT_VDO1_DP0_VDE_END_ENG_EVENT_MM	749
+#define CMDQ_EVENT_VDO1_DP0_VDE_START_ENG_EVENT_MM	750
+#define CMDQ_EVENT_VDO1_DP0_VSYNC_END_ENG_EVENT_MM	751
+#define CMDQ_EVENT_VDO1_DP0_VSYNC_START_ENG_EVENT_MM	752
+#define CMDQ_EVENT_VDO1_DP0_TARGET_LINE_ENG_EVENT_MM	753
+#define CMDQ_EVENT_VDO1_VPP_MERGE0_EVENT		754
+#define CMDQ_EVENT_VDO1_VPP_MERGE1_EVENT		755
+#define CMDQ_EVENT_VDO1_VPP_MERGE2_EVENT		756
+#define CMDQ_EVENT_VDO1_VPP_MERGE3_EVENT		757
+#define CMDQ_EVENT_VDO1_VPP_MERGE4_EVENT		758
+#define CMDQ_EVENT_VDO1_HDMITX_EVENT			759
+#define CMDQ_EVENT_VDO1_HDR_VDO_BE0_ADL_TRIG_EVENT_MM		760
+#define CMDQ_EVENT_VDO1_HDR_GFX_FE1_THDR_ADL_TRIG_EVENT_MM	761
+#define CMDQ_EVENT_VDO1_HDR_GFX_FE1_DM_ADL_TRIG_EVENT_MM	762
+#define CMDQ_EVENT_VDO1_HDR_GFX_FE0_THDR_ADL_TRIG_EVENT_MM	763
+#define CMDQ_EVENT_VDO1_HDR_GFX_FE0_DM_ADL_TRIG_EVENT_MM	764
+#define CMDQ_EVENT_VDO1_HDR_VDO_FE1_ADL_TRIG_EVENT_MM		765
+#define CMDQ_EVENT_VDO1_HDR_VDO_FE1_AD0_TRIG_EVENT_MM		766
+#define CMDQ_EVENT_VDO1_DPI0_TARGET_LINE_1_EVENT_MM		767
+#define CMDQ_EVENT_HANDSHAKE_0		768
+#define CMDQ_EVENT_HANDSHAKE_1		769
+#define CMDQ_EVENT_HANDSHAKE_2		770
+#define CMDQ_EVENT_HANDSHAKE_3		771
+#define CMDQ_EVENT_HANDSHAKE_4		772
+#define CMDQ_EVENT_HANDSHAKE_5		773
+#define CMDQ_EVENT_HANDSHAKE_6		774
+#define CMDQ_EVENT_HANDSHAKE_7		775
+#define CMDQ_EVENT_HANDSHAKE_8		776
+#define CMDQ_EVENT_HANDSHAKE_9		777
+#define CMDQ_EVENT_HANDSHAKE_10		778
+#define CMDQ_EVENT_HANDSHAKE_11		779
+#define CMDQ_EVENT_HANDSHAKE_12		780
+#define CMDQ_EVENT_HANDSHAKE_13		781
+#define CMDQ_EVENT_HANDSHAKE_14		782
+#define CMDQ_EVENT_HANDSHAKE_15		783
+#define CMDQ_EVENT_VDEC_SOC_EVENT_0	800
+#define CMDQ_EVENT_VDEC_SOC_EVENT_1	801
+#define CMDQ_EVENT_VDEC_SOC_EVENT_2	802
+#define CMDQ_EVENT_VDEC_SOC_EVENT_3	803
+#define CMDQ_EVENT_VDEC_SOC_EVENT_4	804
+#define CMDQ_EVENT_VDEC_SOC_EVENT_5	805
+#define CMDQ_EVENT_VDEC_SOC_EVENT_6	806
+#define CMDQ_EVENT_VDEC_SOC_EVENT_7	807
+#define CMDQ_EVENT_VDEC_SOC_EVENT_8	808
+#define CMDQ_EVENT_VDEC_SOC_EVENT_9	809
+#define CMDQ_EVENT_VDEC_SOC_EVENT_10	810
+#define CMDQ_EVENT_VDEC_SOC_EVENT_11	811
+#define CMDQ_EVENT_VDEC_SOC_EVENT_12	812
+#define CMDQ_EVENT_VDEC_SOC_EVENT_13	813
+#define CMDQ_EVENT_VDEC_SOC_EVENT_14	814
+#define CMDQ_EVENT_VDEC_SOC_EVENT_15	815
+#define CMDQ_EVENT_VDEC_CORE0_EVENT_0	832
+#define CMDQ_EVENT_VDEC_CORE0_EVENT_1	833
+#define CMDQ_EVENT_VDEC_CORE0_EVENT_2	834
+#define CMDQ_EVENT_VDEC_CORE0_EVENT_3	835
+#define CMDQ_EVENT_VDEC_CORE0_EVENT_4	836
+#define CMDQ_EVENT_VDEC_CORE0_EVENT_5	837
+#define CMDQ_EVENT_VDEC_CORE0_EVENT_6	838
+#define CMDQ_EVENT_VDEC_CORE0_EVENT_7	839
+#define CMDQ_EVENT_VDEC_CORE0_EVENT_8	840
+#define CMDQ_EVENT_VDEC_CORE0_EVENT_9	841
+#define CMDQ_EVENT_VDEC_CORE0_EVENT_10	842
+#define CMDQ_EVENT_VDEC_CORE0_EVENT_11	843
+#define CMDQ_EVENT_VDEC_CORE0_EVENT_12	844
+#define CMDQ_EVENT_VDEC_CORE0_EVENT_13	845
+#define CMDQ_EVENT_VDEC_CORE0_EVENT_14	846
+#define CMDQ_EVENT_VDEC_CORE0_EVENT_15	847
+#define CMDQ_EVENT_VENC_TOP_VENC_FRAME_DONE		865
+#define CMDQ_EVENT_VENC_TOP_VENC_PAUSE_DONE		866
+#define CMDQ_EVENT_VENC_TOP_JPGENC_DONE			867
+#define CMDQ_EVENT_VENC_TOP_VENC_MB_DONE		868
+#define CMDQ_EVENT_VENC_TOP_VENC_128BYTE_DONE		869
+#define CMDQ_EVENT_VENC_TOP_JPGDEC_DONE			870
+#define CMDQ_EVENT_VENC_TOP_VENC_SLICE_DONE		871
+#define CMDQ_EVENT_VENC_TOP_JPGDEC_INSUFF_DONE		872
+#define CMDQ_EVENT_VENC_TOP_WP_2ND_STAGE_DONE		874
+#define CMDQ_EVENT_VENC_TOP_WP_3RD_STAGE_DONE		875
+#define CMDQ_EVENT_VENC_TOP_PPS_HEADER_DONE		876
+#define CMDQ_EVENT_VENC_TOP_SPS_HEADER_DONE		877
+#define CMDQ_EVENT_VENC_TOP_VPS_HEADER_DONE		878
+#define CMDQ_EVENT_WPE_VPP0_WPE_GCE_FRAME_DONE		882
+#define CMDQ_EVENT_WPE_VPP0_WPE_DONE_SYNC_OUT		883
+#define CMDQ_EVENT_SVPP1_MDP_OVL_NEW_EVENT_2		896
+#define CMDQ_EVENT_SVPP1_MDP_OVL_NEW_EVENT_3		897
+#define CMDQ_EVENT_SVPP1_MDP_OVL_NEW_EVENT_4		898
+#define CMDQ_EVENT_SVPP1_MDP_OVL_NEW_EVENT_5		899
+#define CMDQ_EVENT_SVPP1_MDP_OVL_NEW_EVENT_6		900
+#define CMDQ_EVENT_VDO1_DPI0_TARGET_LINE_0_EVENT_MM		928
+#define CMDQ_EVENT_VDO1_DPI0_TRIGGER_LOOP_CLEAR_EVENT_MM	929
+#define CMDQ_EVENT_VDO1_DPI0_LAST_LINE_EVENT_MM			930
+#define CMDQ_EVENT_VDO1_DPI0_LAST_SAFE_BLANK_EVENT_MM		931
+#define CMDQ_EVENT_VDO1_DPI0_VSYNC_START_EVENT_MM		932
+#define CMDQ_EVENT_VDO1_DPI1_TARGET_LINE_1_EVENT_MM		933
+#define CMDQ_EVENT_VDO1_DPI1_TARGET_LINE_0_EVENT_MM		934
+#define CMDQ_EVENT_VDO1_DPI1_TRIGGER_LOOP_CLEAR_EVENT_MM	935
+#define CMDQ_EVENT_VDO1_DPI1_LAST_LINE_EVENT_MM			936
+#define CMDQ_EVENT_VDO1_DPI1_LAST_SAFE_BLANK_EVENT_MM		937
+#define CMDQ_EVENT_VDO1_DPI1_VSYNC_START_EVENT_MM		938
+#define CMDQ_EVENT_VDO1_DP_INTF_TARGET_LINE_1_EVENT_MM		939
+#define CMDQ_EVENT_VDO1_DP_INTF_TARGET_LINE_0_EVENT_MM		940
+#define CMDQ_EVENT_VDO1_DP_INTF_TRIGGER_LOOP_CLEAR_EVENT_MM	941
+#define CMDQ_EVENT_VDO1_DP_INTF_LAST_LINE_EVENT_MM		942
+#define CMDQ_EVENT_VDO1_DP_INTF_LAST_SAFE_BLANK_EVENT_MM	943
+#define CMDQ_EVENT_VBLANK_FALLING		946
+#define CMDQ_EVENT_VSC_FINISH			947
+#define CMDQ_EVENT_TPR_0			962
+#define CMDQ_EVENT_TPR_1			963
+#define CMDQ_EVENT_TPR_2			964
+#define CMDQ_EVENT_TPR_3			965
+#define CMDQ_EVENT_TPR_4			966
+#define CMDQ_EVENT_TPR_5			967
+#define CMDQ_EVENT_TPR_6			968
+#define CMDQ_EVENT_TPR_7			969
+#define CMDQ_EVENT_TPR_8			970
+#define CMDQ_EVENT_TPR_9			971
+#define CMDQ_EVENT_TPR_10			972
+#define CMDQ_EVENT_TPR_11			973
+#define CMDQ_EVENT_TPR_12			974
+#define CMDQ_EVENT_TPR_13			975
+#define CMDQ_EVENT_TPR_14			976
+#define CMDQ_EVENT_TPR_15			977
+#define CMDQ_EVENT_TPR_16			978
+#define CMDQ_EVENT_TPR_17			979
+#define CMDQ_EVENT_TPR_18			980
+#define CMDQ_EVENT_TPR_19			981
+#define CMDQ_EVENT_TPR_20			982
+#define CMDQ_EVENT_TPR_21			983
+#define CMDQ_EVENT_TPR_22			984
+#define CMDQ_EVENT_TPR_23			985
+#define CMDQ_EVENT_TPR_24			986
+#define CMDQ_EVENT_TPR_25			987
+#define CMDQ_EVENT_TPR_26			988
+#define CMDQ_EVENT_TPR_27			989
+#define CMDQ_EVENT_TPR_28			990
+#define CMDQ_EVENT_TPR_29			991
+#define CMDQ_EVENT_TPR_30			992
+#define CMDQ_EVENT_TPR_31			993
+#define CMDQ_EVENT_TPR_TIMEOUT_0	994
+#define CMDQ_EVENT_TPR_TIMEOUT_1	995
+#define CMDQ_EVENT_TPR_TIMEOUT_2	996
+#define CMDQ_EVENT_TPR_TIMEOUT_3	997
+#define CMDQ_EVENT_TPR_TIMEOUT_4	998
+#define CMDQ_EVENT_TPR_TIMEOUT_5	999
+#define CMDQ_EVENT_TPR_TIMEOUT_6	1000
+#define CMDQ_EVENT_TPR_TIMEOUT_7	1001
+#define CMDQ_EVENT_TPR_TIMEOUT_8	1002
+#define CMDQ_EVENT_TPR_TIMEOUT_9	1003
+#define CMDQ_EVENT_TPR_TIMEOUT_10	1004
+#define CMDQ_EVENT_TPR_TIMEOUT_11	1005
+#define CMDQ_EVENT_TPR_TIMEOUT_12	1006
+#define CMDQ_EVENT_TPR_TIMEOUT_13	1007
+#define CMDQ_EVENT_TPR_TIMEOUT_14	1008
+#define CMDQ_EVENT_TPR_TIMEOUT_15	1009
+#define CMDQ_EVENT_OUTPIN_0		1018
+#define CMDQ_EVENT_OUTPIN_1		1019
+
+#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_EIS			124
+#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_TNR			125
+#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_LITE			126
+#define CMDQ_SYNC_TOKEN_IMGSYS_TRAW			127
+#define CMDQ_SYNC_TOKEN_IMGSYS_LTRAW			128
+#define CMDQ_SYNC_TOKEN_CAMSYS_POOL_1			223
+#define CMDQ_SYNC_TOKEN_CAMSYS_POOL_2			224
+#define CMDQ_SYNC_TOKEN_CAMSYS_POOL_3			225
+#define CMDQ_SYNC_TOKEN_CAMSYS_POOL_4			226
+#define CMDQ_SYNC_TOKEN_CAMSYS_POOL_5			227
+#define CMDQ_SYNC_TOKEN_CAMSYS_POOL_6			228
+#define CMDQ_SYNC_TOKEN_CAMSYS_POOL_7			229
+#define CMDQ_SYNC_TOKEN_CAMSYS_POOL_8			230
+#define CMDQ_SYNC_TOKEN_CAMSYS_POOL_9			231
+#define CMDQ_SYNC_TOKEN_CAMSYS_POOL_10			232
+#define CMDQ_SYNC_TOKEN_IMGSYS_XTRAW			233
+#define CMDQ_SYNC_TOKEN_IMGSYS_DIP			234
+#define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_A			235
+#define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_B			236
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_1			237
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_2			238
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_3			239
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_4			240
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_5			241
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_6			242
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_7			243
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_8			244
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_9			245
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_10			246
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_11			247
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_12			248
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_13			249
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_14			250
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_15			251
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_16			252
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_17			253
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_18			254
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_19			255
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_20			276
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_21			277
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_22			278
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_23			279
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_24			280
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_25			281
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_26			282
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_27			283
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_28			284
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_29			285
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_30			286
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_31			287
+#define CMDQ_SYNC_TOKEN_IPESYS_ME			300
+#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_TRAW			301
+#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_LTRAW		302
+#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_XTRAW		303
+#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_DIP			304
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_32			308
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_33			309
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_34			310
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_35			311
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_36			312
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_37			313
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_38			314
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_39			315
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_40			316
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_41			370
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_42			371
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_43			372
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_44			373
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_45			374
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_46			375
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_47			376
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_48			377
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_49			378
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_50			379
+#define CMDQ_SYNC_TOKEN_TZMP_ISP_WAIT			380
+#define CMDQ_SYNC_TOKEN_TZMP_ISP_SET			381
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_51			790
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_52			791
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_53			792
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_54			793
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_55			794
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_56			795
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_57			796
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_58			797
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_59			798
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_60			799
+#define CMDQ_SYNC_TOKEN_PREBUILT_MDP_WAIT		816
+#define CMDQ_SYNC_TOKEN_PREBUILT_MDP_SET		817
+#define CMDQ_SYNC_TOKEN_PREBUILT_MDP_LOCK		818
+#define CMDQ_SYNC_TOKEN_PREBUILT_MML_WAIT		819
+#define CMDQ_SYNC_TOKEN_PREBUILT_MML_SET		820
+#define CMDQ_SYNC_TOKEN_PREBUILT_MML_LOCK		821
+#define CMDQ_SYNC_TOKEN_PREBUILT_VFMT_WAIT		822
+#define CMDQ_SYNC_TOKEN_PREBUILT_VFMT_SET		823
+#define CMDQ_SYNC_TOKEN_PREBUILT_VFMT_LOCK		824
+#define CMDQ_SYNC_TOKEN_PREBUILT_DISP_WAIT		825
+#define CMDQ_SYNC_TOKEN_PREBUILT_DISP_SET		826
+#define CMDQ_SYNC_TOKEN_PREBUILT_DISP_LOCK		827
+#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY			848
+#define CMDQ_SYNC_TOKEN_STREAM_EOF			849
+#define CMDQ_SYNC_TOKEN_ESD_EOF				850
+#define CMDQ_SYNC_TOKEN_STREAM_BLOCK			851
+#define CMDQ_SYNC_TOKEN_CABC_EOF			852
+#define CMDQ_SYNC_TOKEN_VENC_INPUT_READY		853
+#define CMDQ_SYNC_TOKEN_VENC_EOF			854
+#define CMDQ_SYNC_TOKEN_SECURE_THR_EOF			855
+#define CMDQ_SYNC_TOKEN_USER_0				856
+#define CMDQ_SYNC_TOKEN_USER_1				857
+#define CMDQ_SYNC_TOKEN_POLL_MONITOR			858
+#define CMDQ_TOKEN_TPR_LOCK				859
+#define CMDQ_SYNC_TOKEN_MSS				860
+#define CMDQ_SYNC_TOKEN_MSF				861
+#define CMDQ_SYNC_TOKEN_GPR_SET_0			884
+#define CMDQ_SYNC_TOKEN_GPR_SET_1			885
+#define CMDQ_SYNC_TOKEN_GPR_SET_2			886
+#define CMDQ_SYNC_TOKEN_GPR_SET_3			887
+#define CMDQ_SYNC_TOKEN_GPR_SET_4			888
+#define CMDQ_SYNC_RESOURCE_WROT0			889
+#define CMDQ_SYNC_RESOURCE_WROT1			890
+#define CMDQ_SYNC_TOKEN_DISP_VA_START			1012
+#define CMDQ_SYNC_TOKEN_DISP_VA_END			1013
+
+#endif
-- 
GitLab


From f2b53c2956207b76c42407f3c089a2c1561a58ef Mon Sep 17 00:00:00 2001
From: Elvis Wang <Elvis.Wang@mediatek.com>
Date: Thu, 1 Dec 2022 15:13:16 +0800
Subject: [PATCH 470/875] dt-bindings: mailbox: mediatek,gce-mailbox: add
 mt8188 compatible name

Add mt8188 compatible name.

Signed-off-by: Elvis Wang <Elvis.Wang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno<angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
---
 .../devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml        | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
index c579ac074ca7d..d383b2ab3ce86 100644
--- a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
+++ b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
@@ -21,6 +21,7 @@ properties:
       - mediatek,mt8173-gce
       - mediatek,mt8183-gce
       - mediatek,mt8186-gce
+      - mediatek,mt8188-gce
       - mediatek,mt8192-gce
       - mediatek,mt8195-gce
 
-- 
GitLab


From 165b7643f2df890066b1b4e8a387888a600ca9bf Mon Sep 17 00:00:00 2001
From: Yang Yingliang <yangyingliang@huawei.com>
Date: Fri, 25 Nov 2022 14:35:48 +0800
Subject: [PATCH 471/875] mailbox: arm_mhuv2: Fix return value check in
 mhuv2_probe()

If devm_of_iomap() fails, it returns ERR_PTR() and never
return NULL, so replace NULL pointer check with IS_ERR()
to fix this problem.

Fixes: 5a6338cce9f4 ("mailbox: arm_mhuv2: Add driver")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
---
 drivers/mailbox/arm_mhuv2.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mailbox/arm_mhuv2.c b/drivers/mailbox/arm_mhuv2.c
index a47aef8df52fd..c6d4957c4da83 100644
--- a/drivers/mailbox/arm_mhuv2.c
+++ b/drivers/mailbox/arm_mhuv2.c
@@ -1062,8 +1062,8 @@ static int mhuv2_probe(struct amba_device *adev, const struct amba_id *id)
 	int ret = -EINVAL;
 
 	reg = devm_of_iomap(dev, dev->of_node, 0, NULL);
-	if (!reg)
-		return -ENOMEM;
+	if (IS_ERR(reg))
+		return PTR_ERR(reg);
 
 	mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
 	if (!mhu)
-- 
GitLab


From acabe12c6106b105ac8285d6d5ba2aeeab74fd47 Mon Sep 17 00:00:00 2001
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Date: Wed, 2 Nov 2022 11:07:36 +0100
Subject: [PATCH 472/875] mailbox: mtk-cmdq-mailbox: Use platform data directly
 instead of copying

Copying platform data to struct cmdq serves to no purpose, as that
data is never modified during runtime: it's worth at this point
storing a pointer to gce_plat in gce and.

Remove all duplicated `struct gce_plat` members from `struct gce`
and reuse the platform data across the driver to save some memory.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
---
 drivers/mailbox/mtk-cmdq-mailbox.c | 88 +++++++++++++-----------------
 1 file changed, 39 insertions(+), 49 deletions(-)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index c5229f377c5e3..a460ee26eb112 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -75,15 +75,11 @@ struct cmdq {
 	struct mbox_controller	mbox;
 	void __iomem		*base;
 	int			irq;
-	u32			thread_nr;
 	u32			irq_mask;
+	const struct gce_plat	*pdata;
 	struct cmdq_thread	*thread;
 	struct clk_bulk_data	clocks[CMDQ_GCE_NUM_MAX];
 	bool			suspended;
-	u8			shift_pa;
-	bool			control_by_sw;
-	bool			sw_ddr_en;
-	u32			gce_num;
 };
 
 struct gce_plat {
@@ -96,21 +92,21 @@ struct gce_plat {
 
 static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable)
 {
-	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
+	WARN_ON(clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks));
 
 	if (enable)
 		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
 	else
 		writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
 
-	clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
+	clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks);
 }
 
 u8 cmdq_get_shift_pa(struct mbox_chan *chan)
 {
 	struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
 
-	return cmdq->shift_pa;
+	return cmdq->pdata->shift;
 }
 EXPORT_SYMBOL(cmdq_get_shift_pa);
 
@@ -144,10 +140,10 @@ static void cmdq_init(struct cmdq *cmdq)
 	int i;
 	u32 gctl_regval = 0;
 
-	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
-	if (cmdq->control_by_sw)
+	WARN_ON(clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks));
+	if (cmdq->pdata->control_by_sw)
 		gctl_regval = GCE_CTRL_BY_SW;
-	if (cmdq->sw_ddr_en)
+	if (cmdq->pdata->sw_ddr_en)
 		gctl_regval |= GCE_DDR_EN;
 
 	if (gctl_regval)
@@ -156,7 +152,7 @@ static void cmdq_init(struct cmdq *cmdq)
 	writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
 	for (i = 0; i <= CMDQ_MAX_EVENT; i++)
 		writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
-	clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
+	clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks);
 }
 
 static int cmdq_thread_reset(struct cmdq *cmdq, struct cmdq_thread *thread)
@@ -201,7 +197,7 @@ static void cmdq_task_insert_into_thread(struct cmdq_task *task)
 				prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
 	prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] =
 		(u64)CMDQ_JUMP_BY_PA << 32 |
-		(task->pa_base >> task->cmdq->shift_pa);
+		(task->pa_base >> task->cmdq->pdata->shift);
 	dma_sync_single_for_device(dev, prev_task->pa_base,
 				   prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
 
@@ -235,7 +231,7 @@ static void cmdq_task_handle_error(struct cmdq_task *task)
 	next_task = list_first_entry_or_null(&thread->task_busy_list,
 			struct cmdq_task, list_entry);
 	if (next_task)
-		writel(next_task->pa_base >> cmdq->shift_pa,
+		writel(next_task->pa_base >> cmdq->pdata->shift,
 		       thread->base + CMDQ_THR_CURR_ADDR);
 	cmdq_thread_resume(thread);
 }
@@ -266,7 +262,7 @@ static void cmdq_thread_irq_handler(struct cmdq *cmdq,
 	else
 		return;
 
-	curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->shift_pa;
+	curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->pdata->shift;
 
 	list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
 				 list_entry) {
@@ -289,7 +285,7 @@ static void cmdq_thread_irq_handler(struct cmdq *cmdq,
 
 	if (list_empty(&thread->task_busy_list)) {
 		cmdq_thread_disable(cmdq, thread);
-		clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
+		clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks);
 	}
 }
 
@@ -303,7 +299,7 @@ static irqreturn_t cmdq_irq_handler(int irq, void *dev)
 	if (!(irq_status ^ cmdq->irq_mask))
 		return IRQ_NONE;
 
-	for_each_clear_bit(bit, &irq_status, cmdq->thread_nr) {
+	for_each_clear_bit(bit, &irq_status, cmdq->pdata->thread_nr) {
 		struct cmdq_thread *thread = &cmdq->thread[bit];
 
 		spin_lock_irqsave(&thread->chan->lock, flags);
@@ -323,7 +319,7 @@ static int cmdq_suspend(struct device *dev)
 
 	cmdq->suspended = true;
 
-	for (i = 0; i < cmdq->thread_nr; i++) {
+	for (i = 0; i < cmdq->pdata->thread_nr; i++) {
 		thread = &cmdq->thread[i];
 		if (!list_empty(&thread->task_busy_list)) {
 			task_running = true;
@@ -334,10 +330,10 @@ static int cmdq_suspend(struct device *dev)
 	if (task_running)
 		dev_warn(dev, "exist running task(s) in suspend\n");
 
-	if (cmdq->sw_ddr_en)
+	if (cmdq->pdata->sw_ddr_en)
 		cmdq_sw_ddr_enable(cmdq, false);
 
-	clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
+	clk_bulk_unprepare(cmdq->pdata->gce_num, cmdq->clocks);
 
 	return 0;
 }
@@ -346,10 +342,10 @@ static int cmdq_resume(struct device *dev)
 {
 	struct cmdq *cmdq = dev_get_drvdata(dev);
 
-	WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks));
+	WARN_ON(clk_bulk_prepare(cmdq->pdata->gce_num, cmdq->clocks));
 	cmdq->suspended = false;
 
-	if (cmdq->sw_ddr_en)
+	if (cmdq->pdata->sw_ddr_en)
 		cmdq_sw_ddr_enable(cmdq, true);
 
 	return 0;
@@ -359,10 +355,10 @@ static int cmdq_remove(struct platform_device *pdev)
 {
 	struct cmdq *cmdq = platform_get_drvdata(pdev);
 
-	if (cmdq->sw_ddr_en)
+	if (cmdq->pdata->sw_ddr_en)
 		cmdq_sw_ddr_enable(cmdq, false);
 
-	clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
+	clk_bulk_unprepare(cmdq->pdata->gce_num, cmdq->clocks);
 	return 0;
 }
 
@@ -388,7 +384,7 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
 	task->pkt = pkt;
 
 	if (list_empty(&thread->task_busy_list)) {
-		WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
+		WARN_ON(clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks));
 
 		/*
 		 * The thread reset will clear thread related register to 0,
@@ -398,9 +394,9 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
 		 */
 		WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
 
-		writel(task->pa_base >> cmdq->shift_pa,
+		writel(task->pa_base >> cmdq->pdata->shift,
 		       thread->base + CMDQ_THR_CURR_ADDR);
-		writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
+		writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->pdata->shift,
 		       thread->base + CMDQ_THR_END_ADDR);
 
 		writel(thread->priority, thread->base + CMDQ_THR_PRIORITY);
@@ -409,20 +405,20 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
 	} else {
 		WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
 		curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) <<
-			cmdq->shift_pa;
+			cmdq->pdata->shift;
 		end_pa = readl(thread->base + CMDQ_THR_END_ADDR) <<
-			cmdq->shift_pa;
+			cmdq->pdata->shift;
 		/* check boundary */
 		if (curr_pa == end_pa - CMDQ_INST_SIZE ||
 		    curr_pa == end_pa) {
 			/* set to this task directly */
-			writel(task->pa_base >> cmdq->shift_pa,
+			writel(task->pa_base >> cmdq->pdata->shift,
 			       thread->base + CMDQ_THR_CURR_ADDR);
 		} else {
 			cmdq_task_insert_into_thread(task);
 			smp_mb(); /* modify jump before enable thread */
 		}
-		writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
+		writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->pdata->shift,
 		       thread->base + CMDQ_THR_END_ADDR);
 		cmdq_thread_resume(thread);
 	}
@@ -461,7 +457,7 @@ static void cmdq_mbox_shutdown(struct mbox_chan *chan)
 	}
 
 	cmdq_thread_disable(cmdq, thread);
-	clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
+	clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks);
 
 done:
 	/*
@@ -501,7 +497,7 @@ static int cmdq_mbox_flush(struct mbox_chan *chan, unsigned long timeout)
 
 	cmdq_thread_resume(thread);
 	cmdq_thread_disable(cmdq, thread);
-	clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
+	clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks);
 
 out:
 	spin_unlock_irqrestore(&thread->chan->lock, flags);
@@ -548,7 +544,6 @@ static int cmdq_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct cmdq *cmdq;
 	int err, i;
-	struct gce_plat *plat_data;
 	struct device_node *phandle = dev->of_node;
 	struct device_node *node;
 	int alias_id = 0;
@@ -567,18 +562,13 @@ static int cmdq_probe(struct platform_device *pdev)
 	if (cmdq->irq < 0)
 		return cmdq->irq;
 
-	plat_data = (struct gce_plat *)of_device_get_match_data(dev);
-	if (!plat_data) {
+	cmdq->pdata = device_get_match_data(dev);
+	if (!cmdq->pdata) {
 		dev_err(dev, "failed to get match data\n");
 		return -EINVAL;
 	}
 
-	cmdq->thread_nr = plat_data->thread_nr;
-	cmdq->shift_pa = plat_data->shift;
-	cmdq->control_by_sw = plat_data->control_by_sw;
-	cmdq->sw_ddr_en = plat_data->sw_ddr_en;
-	cmdq->gce_num = plat_data->gce_num;
-	cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
+	cmdq->irq_mask = GENMASK(cmdq->pdata->thread_nr - 1, 0);
 	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
 			       "mtk_cmdq", cmdq);
 	if (err < 0) {
@@ -589,10 +579,10 @@ static int cmdq_probe(struct platform_device *pdev)
 	dev_dbg(dev, "cmdq device: addr:0x%p, va:0x%p, irq:%d\n",
 		dev, cmdq->base, cmdq->irq);
 
-	if (cmdq->gce_num > 1) {
+	if (cmdq->pdata->gce_num > 1) {
 		for_each_child_of_node(phandle->parent, node) {
 			alias_id = of_alias_get_id(node, clk_name);
-			if (alias_id >= 0 && alias_id < cmdq->gce_num) {
+			if (alias_id >= 0 && alias_id < cmdq->pdata->gce_num) {
 				cmdq->clocks[alias_id].id = clk_names[alias_id];
 				cmdq->clocks[alias_id].clk = of_clk_get(node, 0);
 				if (IS_ERR(cmdq->clocks[alias_id].clk)) {
@@ -614,12 +604,12 @@ static int cmdq_probe(struct platform_device *pdev)
 	}
 
 	cmdq->mbox.dev = dev;
-	cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr,
+	cmdq->mbox.chans = devm_kcalloc(dev, cmdq->pdata->thread_nr,
 					sizeof(*cmdq->mbox.chans), GFP_KERNEL);
 	if (!cmdq->mbox.chans)
 		return -ENOMEM;
 
-	cmdq->mbox.num_chans = cmdq->thread_nr;
+	cmdq->mbox.num_chans = cmdq->pdata->thread_nr;
 	cmdq->mbox.ops = &cmdq_mbox_chan_ops;
 	cmdq->mbox.of_xlate = cmdq_xlate;
 
@@ -627,12 +617,12 @@ static int cmdq_probe(struct platform_device *pdev)
 	cmdq->mbox.txdone_irq = false;
 	cmdq->mbox.txdone_poll = false;
 
-	cmdq->thread = devm_kcalloc(dev, cmdq->thread_nr,
+	cmdq->thread = devm_kcalloc(dev, cmdq->pdata->thread_nr,
 					sizeof(*cmdq->thread), GFP_KERNEL);
 	if (!cmdq->thread)
 		return -ENOMEM;
 
-	for (i = 0; i < cmdq->thread_nr; i++) {
+	for (i = 0; i < cmdq->pdata->thread_nr; i++) {
 		cmdq->thread[i].base = cmdq->base + CMDQ_THR_BASE +
 				CMDQ_THR_SIZE * i;
 		INIT_LIST_HEAD(&cmdq->thread[i].task_busy_list);
@@ -647,7 +637,7 @@ static int cmdq_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, cmdq);
 
-	WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks));
+	WARN_ON(clk_bulk_prepare(cmdq->pdata->gce_num, cmdq->clocks));
 
 	cmdq_init(cmdq);
 
-- 
GitLab


From a6792a0cdef0b1c2d77920246283a72537e60e94 Mon Sep 17 00:00:00 2001
From: Yang Yingliang <yangyingliang@huawei.com>
Date: Thu, 10 Nov 2022 23:08:22 +0800
Subject: [PATCH 473/875] mailbox: zynq-ipi: fix error handling while
 device_register() fails

If device_register() fails, it has two issues:
1. The name allocated by dev_set_name() is leaked.
2. The parent of device is not NULL, device_unregister() is called
   in zynqmp_ipi_free_mboxes(), it will lead a kernel crash because
   of removing not added device.

Call put_device() to give up the reference, so the name is freed in
kobject_cleanup(). Add device registered check in zynqmp_ipi_free_mboxes()
to avoid null-ptr-deref.

Fixes: 4981b82ba2ff ("mailbox: ZynqMP IPI mailbox controller")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
---
 drivers/mailbox/zynqmp-ipi-mailbox.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mailbox/zynqmp-ipi-mailbox.c b/drivers/mailbox/zynqmp-ipi-mailbox.c
index 31a0fa9142744..12e004ff1a147 100644
--- a/drivers/mailbox/zynqmp-ipi-mailbox.c
+++ b/drivers/mailbox/zynqmp-ipi-mailbox.c
@@ -493,6 +493,7 @@ static int zynqmp_ipi_mbox_probe(struct zynqmp_ipi_mbox *ipi_mbox,
 	ret = device_register(&ipi_mbox->dev);
 	if (ret) {
 		dev_err(dev, "Failed to register ipi mbox dev.\n");
+		put_device(&ipi_mbox->dev);
 		return ret;
 	}
 	mdev = &ipi_mbox->dev;
@@ -619,7 +620,8 @@ static void zynqmp_ipi_free_mboxes(struct zynqmp_ipi_pdata *pdata)
 		ipi_mbox = &pdata->ipi_mboxes[i];
 		if (ipi_mbox->dev.parent) {
 			mbox_controller_unregister(&ipi_mbox->mbox);
-			device_unregister(&ipi_mbox->dev);
+			if (device_is_registered(&ipi_mbox->dev))
+				device_unregister(&ipi_mbox->dev);
 		}
 	}
 }
-- 
GitLab


From 16edcfef77147748c43c9c58ce18f59c61d1c357 Mon Sep 17 00:00:00 2001
From: Ricardo Ribalda <ribalda@chromium.org>
Date: Wed, 30 Nov 2022 13:58:22 +0100
Subject: [PATCH 474/875] mailbox: mtk-cmdq: Do not request irq until we are
 ready

If the system comes from kexec() the peripheral might trigger an IRQ
befoe we are ready for it. Triggering a crash due to an access to
invalid memory.

Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
---
 drivers/mailbox/mtk-cmdq-mailbox.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index a460ee26eb112..b18d47ea13a0e 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -569,12 +569,6 @@ static int cmdq_probe(struct platform_device *pdev)
 	}
 
 	cmdq->irq_mask = GENMASK(cmdq->pdata->thread_nr - 1, 0);
-	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
-			       "mtk_cmdq", cmdq);
-	if (err < 0) {
-		dev_err(dev, "failed to register ISR (%d)\n", err);
-		return err;
-	}
 
 	dev_dbg(dev, "cmdq device: addr:0x%p, va:0x%p, irq:%d\n",
 		dev, cmdq->base, cmdq->irq);
@@ -641,6 +635,13 @@ static int cmdq_probe(struct platform_device *pdev)
 
 	cmdq_init(cmdq);
 
+	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
+			       "mtk_cmdq", cmdq);
+	if (err < 0) {
+		dev_err(dev, "failed to register ISR (%d)\n", err);
+		return err;
+	}
+
 	return 0;
 }
 
-- 
GitLab


From 53c60d1004270045d63cdee91aa77c145282d7e4 Mon Sep 17 00:00:00 2001
From: Abel Vesa <abel.vesa@linaro.org>
Date: Wed, 16 Nov 2022 13:34:57 +0200
Subject: [PATCH 475/875] dt-bindings: mailbox: qcom-ipcc: Add compatible for
 SM8550

Document the compatible for SM8550 mailbox.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
---
 Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
index bc599a8646379..f5c73437fef48 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
+++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
@@ -31,6 +31,7 @@ properties:
           - qcom,sm8250-ipcc
           - qcom,sm8350-ipcc
           - qcom,sm8450-ipcc
+          - qcom,sm8550-ipcc
       - const: qcom,ipcc
 
   reg:
-- 
GitLab


From 0e13e7b448005612972eae36c0f698c21d1e2f8a Mon Sep 17 00:00:00 2001
From: Bastien Nocera <hadess@hadess.net>
Date: Thu, 15 Dec 2022 16:44:16 +0100
Subject: [PATCH 476/875] HID: logitech-hidpp: Guard FF init code against
 non-USB devices

The Force Feedback code assumes that all the devices passed to it will
be USB devices, but that might not be the case for emulated devices.
Guard against a crash by checking the device type before poking at USB
properties.

Cc: stable@vger.kernel.org # v5.16+
Reported-by: Benjamin Tissoires <benjamin.tissoires@redhat.com>
Signed-off-by: Bastien Nocera <hadess@hadess.net>
Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com>
Link: https://lore.kernel.org/r/20221215154416.111704-1-hadess@hadess.net
---
 drivers/hid/hid-logitech-hidpp.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/hid/hid-logitech-hidpp.c b/drivers/hid/hid-logitech-hidpp.c
index c6e4a96e882e6..abf2c95e4d0b0 100644
--- a/drivers/hid/hid-logitech-hidpp.c
+++ b/drivers/hid/hid-logitech-hidpp.c
@@ -2548,12 +2548,17 @@ static int hidpp_ff_init(struct hidpp_device *hidpp,
 	struct hid_device *hid = hidpp->hid_dev;
 	struct hid_input *hidinput;
 	struct input_dev *dev;
-	const struct usb_device_descriptor *udesc = &(hid_to_usb_dev(hid)->descriptor);
-	const u16 bcdDevice = le16_to_cpu(udesc->bcdDevice);
+	struct usb_device_descriptor *udesc;
+	u16 bcdDevice;
 	struct ff_device *ff;
 	int error, j, num_slots = data->num_effects;
 	u8 version;
 
+	if (!hid_is_usb(hid)) {
+		hid_err(hid, "device is not USB\n");
+		return -ENODEV;
+	}
+
 	if (list_empty(&hid->inputs)) {
 		hid_err(hid, "no inputs found\n");
 		return -ENODEV;
@@ -2567,6 +2572,8 @@ static int hidpp_ff_init(struct hidpp_device *hidpp,
 	}
 
 	/* Get firmware release */
+	udesc = &(hid_to_usb_dev(hid)->descriptor);
+	bcdDevice = le16_to_cpu(udesc->bcdDevice);
 	version = bcdDevice & 255;
 
 	/* Set supported force feedback capabilities */
-- 
GitLab


From 67c90d14018775556d5420382ace86521421f9ff Mon Sep 17 00:00:00 2001
From: Enrik Berkhan <Enrik.Berkhan@inka.de>
Date: Thu, 3 Nov 2022 23:27:12 +0100
Subject: [PATCH 477/875] HID: mcp2221: don't connect hidraw
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The MCP2221 driver should not connect to the hidraw userspace interface,
as it needs exclusive access to the chip.

If you want to use /dev/hidrawX with the MCP2221, you need to avoid
binding this driver to the device and use the hid generic driver instead
(e.g. using udev rules).

Cc: stable@vger.kernel.org
Reported-by: Sven Zühlsdorf <sven.zuehlsdorf@vigem.de>
Signed-off-by: Enrik Berkhan <Enrik.Berkhan@inka.de>
Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com>
Link: https://lore.kernel.org/r/20221103222714.21566-2-Enrik.Berkhan@inka.de
---
 drivers/hid/hid-mcp2221.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/hid/hid-mcp2221.c b/drivers/hid/hid-mcp2221.c
index 5886543b17f34..e61dd039354b8 100644
--- a/drivers/hid/hid-mcp2221.c
+++ b/drivers/hid/hid-mcp2221.c
@@ -1110,12 +1110,19 @@ static int mcp2221_probe(struct hid_device *hdev,
 		return ret;
 	}
 
-	ret = hid_hw_start(hdev, HID_CONNECT_HIDRAW);
+	/*
+	 * This driver uses the .raw_event callback and therefore does not need any
+	 * HID_CONNECT_xxx flags.
+	 */
+	ret = hid_hw_start(hdev, 0);
 	if (ret) {
 		hid_err(hdev, "can't start hardware\n");
 		return ret;
 	}
 
+	hid_info(hdev, "USB HID v%x.%02x Device [%s] on %s\n", hdev->version >> 8,
+			hdev->version & 0xff, hdev->name, hdev->phys);
+
 	ret = hid_hw_open(hdev);
 	if (ret) {
 		hid_err(hdev, "can't open device\n");
@@ -1145,8 +1152,7 @@ static int mcp2221_probe(struct hid_device *hdev,
 	mcp->adapter.retries = 1;
 	mcp->adapter.dev.parent = &hdev->dev;
 	snprintf(mcp->adapter.name, sizeof(mcp->adapter.name),
-			"MCP2221 usb-i2c bridge on hidraw%d",
-			((struct hidraw *)hdev->hidraw)->minor);
+			"MCP2221 usb-i2c bridge");
 
 	ret = devm_i2c_add_adapter(&hdev->dev, &mcp->adapter);
 	if (ret) {
-- 
GitLab


From 0ee29814c6be17a924761d3712eb8ad63cfe13ac Mon Sep 17 00:00:00 2001
From: Roderick Colenbrander <roderick@gaikai.com>
Date: Mon, 12 Dec 2022 20:49:35 -0800
Subject: [PATCH 478/875] HID: playstation: fix free of uninialized pointer for
 DS4 in Bluetooth.

The 'buf' variable is only used in the USB (if-path) and not in the Bluetooth
else-path. Since it is not set to NULL. this results in freeing an uninitialized
pointer. Since the else code-path doesn't need buf, just return 0.

Fixes: 2d77474a2392 ("HID: playstation: add DualShock4 bluetooth support.")
Signed-off-by: Roderick Colenbrander <roderick.colenbrander@sony.com>
Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com>
Link: https://lore.kernel.org/r/20221213044935.1775499-2-roderick.colenbrander@sony.com
---
 drivers/hid/Kconfig           | 2 +-
 drivers/hid/hid-playstation.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/hid/Kconfig b/drivers/hid/Kconfig
index 17cce4c50e8dc..e2a5d30c88956 100644
--- a/drivers/hid/Kconfig
+++ b/drivers/hid/Kconfig
@@ -897,7 +897,7 @@ config HID_PLAYSTATION
 	select CRC32
 	select POWER_SUPPLY
 	help
-	  Provides support for Sony PS5 controllers including support for
+	  Provides support for Sony PS4/PS5 controllers including support for
 	  its special functionalities e.g. touchpad, lights and motion
 	  sensors.
 
diff --git a/drivers/hid/hid-playstation.c b/drivers/hid/hid-playstation.c
index 7b5aef538044a..f399bf0d3c8cc 100644
--- a/drivers/hid/hid-playstation.c
+++ b/drivers/hid/hid-playstation.c
@@ -1916,7 +1916,7 @@ static int dualshock4_get_mac_address(struct dualshock4 *ds4)
 		if (ret != sizeof(ds4->base.mac_address))
 			return -EINVAL;
 
-		ret = 0;
+		return 0;
 	}
 
 err_free:
-- 
GitLab


From c877ce47e1378dbafa6f1bf84c0c83a05ca8972a Mon Sep 17 00:00:00 2001
From: Paulo Alcantara <pc@cjr.nz>
Date: Mon, 12 Dec 2022 23:39:37 -0300
Subject: [PATCH 479/875] cifs: reduce roundtrips on create/qinfo requests

To work around some Window servers that return
STATUS_OBJECT_NAME_INVALID on query infos under DFS namespaces that
contain non-ASCII characters, we started checking for -ENOENT on every
file open, and if so, then send additional requests to figure out
whether it is a DFS link or not.  It means that all those requests
will be sent to every non-existing file.

So, in order to reduce the number of roundtrips, check earlier whether
status code is STATUS_OBJECT_NAME_INVALID and tcon supports dfs, and
if so, then map -ENOENT to -EREMOTE so mount or automount will take
care of chasing the DFS link -- if it isn't an DFS link, then -ENOENT
will be returned appropriately.

Before patch

  SMB2 438 Create Request File: ada.test\dfs\foo;GetInfo Request...
  SMB2 310 Create Response, Error: STATUS_OBJECT_NAME_NOT_FOUND;...
  SMB2 228 Ioctl Request FSCTL_DFS_GET_REFERRALS, File: \ada.test\dfs\foo
  SMB2 143 Ioctl Response, Error: STATUS_OBJECT_PATH_NOT_FOUND
  SMB2 438 Create Request File: ada.test\dfs\foo;GetInfo Request...
  SMB2 310 Create Response, Error: STATUS_OBJECT_NAME_NOT_FOUND;...
  SMB2 228 Ioctl Request FSCTL_DFS_GET_REFERRALS, File: \ada.test\dfs\foo
  SMB2 143 Ioctl Response, Error: STATUS_OBJECT_PATH_NOT_FOUND

After patch

  SMB2 438 Create Request File: ada.test\dfs\foo;GetInfo Request...
  SMB2 310 Create Response, Error: STATUS_OBJECT_NAME_NOT_FOUND;...
  SMB2 438 Create Request File: ada.test\dfs\foo;GetInfo Request...
  SMB2 310 Create Response, Error: STATUS_OBJECT_NAME_NOT_FOUND;...

Signed-off-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/connect.c   | 16 ----------------
 fs/cifs/inode.c     |  6 ------
 fs/cifs/misc.c      | 45 --------------------------------------------
 fs/cifs/smb2inode.c | 46 ++++++++++++++++++++++++++++++++-------------
 fs/cifs/smb2ops.c   | 28 +++++++++++++++++++++++----
 5 files changed, 57 insertions(+), 84 deletions(-)

diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c
index f51715d3e2f2e..b04706835e028 100644
--- a/fs/cifs/connect.c
+++ b/fs/cifs/connect.c
@@ -3547,9 +3547,6 @@ static int is_path_remote(struct mount_ctx *mnt_ctx)
 	struct cifs_tcon *tcon = mnt_ctx->tcon;
 	struct smb3_fs_context *ctx = mnt_ctx->fs_ctx;
 	char *full_path;
-#ifdef CONFIG_CIFS_DFS_UPCALL
-	bool nodfs = cifs_sb->mnt_cifs_flags & CIFS_MOUNT_NO_DFS;
-#endif
 
 	if (!server->ops->is_path_accessible)
 		return -EOPNOTSUPP;
@@ -3566,19 +3563,6 @@ static int is_path_remote(struct mount_ctx *mnt_ctx)
 
 	rc = server->ops->is_path_accessible(xid, tcon, cifs_sb,
 					     full_path);
-#ifdef CONFIG_CIFS_DFS_UPCALL
-	if (nodfs) {
-		if (rc == -EREMOTE)
-			rc = -EOPNOTSUPP;
-		goto out;
-	}
-
-	/* path *might* exist with non-ASCII characters in DFS root
-	 * try again with full path (only if nodfs is not set) */
-	if (rc == -ENOENT && is_tcon_dfs(tcon))
-		rc = cifs_dfs_query_info_nonascii_quirk(xid, tcon, cifs_sb,
-							full_path);
-#endif
 	if (rc != 0 && rc != -EREMOTE)
 		goto out;
 
diff --git a/fs/cifs/inode.c b/fs/cifs/inode.c
index 286a5400b94e5..f145a59af89be 100644
--- a/fs/cifs/inode.c
+++ b/fs/cifs/inode.c
@@ -993,12 +993,6 @@ int cifs_get_inode_info(struct inode **inode, const char *full_path,
 		}
 		rc = server->ops->query_path_info(xid, tcon, cifs_sb, full_path, &tmp_data,
 						  &adjust_tz, &is_reparse_point);
-#ifdef CONFIG_CIFS_DFS_UPCALL
-		if (rc == -ENOENT && is_tcon_dfs(tcon))
-			rc = cifs_dfs_query_info_nonascii_quirk(xid, tcon,
-								cifs_sb,
-								full_path);
-#endif
 		data = &tmp_data;
 	}
 
diff --git a/fs/cifs/misc.c b/fs/cifs/misc.c
index 1cbecd64d697f..062175994e879 100644
--- a/fs/cifs/misc.c
+++ b/fs/cifs/misc.c
@@ -1314,49 +1314,4 @@ int cifs_update_super_prepath(struct cifs_sb_info *cifs_sb, char *prefix)
 	cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_USE_PREFIX_PATH;
 	return 0;
 }
-
-/** cifs_dfs_query_info_nonascii_quirk
- * Handle weird Windows SMB server behaviour. It responds with
- * STATUS_OBJECT_NAME_INVALID code to SMB2 QUERY_INFO request
- * for "\<server>\<dfsname>\<linkpath>" DFS reference,
- * where <dfsname> contains non-ASCII unicode symbols.
- *
- * Check such DFS reference.
- */
-int cifs_dfs_query_info_nonascii_quirk(const unsigned int xid,
-				       struct cifs_tcon *tcon,
-				       struct cifs_sb_info *cifs_sb,
-				       const char *linkpath)
-{
-	char *treename, *dfspath, sep;
-	int treenamelen, linkpathlen, rc;
-
-	treename = tcon->tree_name;
-	/* MS-DFSC: All paths in REQ_GET_DFS_REFERRAL and RESP_GET_DFS_REFERRAL
-	 * messages MUST be encoded with exactly one leading backslash, not two
-	 * leading backslashes.
-	 */
-	sep = CIFS_DIR_SEP(cifs_sb);
-	if (treename[0] == sep && treename[1] == sep)
-		treename++;
-	linkpathlen = strlen(linkpath);
-	treenamelen = strnlen(treename, MAX_TREE_SIZE + 1);
-	dfspath = kzalloc(treenamelen + linkpathlen + 1, GFP_KERNEL);
-	if (!dfspath)
-		return -ENOMEM;
-	if (treenamelen)
-		memcpy(dfspath, treename, treenamelen);
-	memcpy(dfspath + treenamelen, linkpath, linkpathlen);
-	rc = dfs_cache_find(xid, tcon->ses, cifs_sb->local_nls,
-			    cifs_remap(cifs_sb), dfspath, NULL, NULL);
-	if (rc == 0) {
-		cifs_dbg(FYI, "DFS ref '%s' is found, emulate -EREMOTE\n",
-			 dfspath);
-		rc = -EREMOTE;
-	} else {
-		cifs_dbg(FYI, "%s: dfs_cache_find returned %d\n", __func__, rc);
-	}
-	kfree(dfspath);
-	return rc;
-}
 #endif
diff --git a/fs/cifs/smb2inode.c b/fs/cifs/smb2inode.c
index fbd46db1023ae..8521adf9ce790 100644
--- a/fs/cifs/smb2inode.c
+++ b/fs/cifs/smb2inode.c
@@ -556,22 +556,42 @@ int smb2_query_path_info(const unsigned int xid, struct cifs_tcon *tcon,
 	rc = smb2_compound_op(xid, tcon, cifs_sb, full_path, FILE_READ_ATTRIBUTES, FILE_OPEN,
 			      create_options, ACL_NO_MODE, data, SMB2_OP_QUERY_INFO, cfile,
 			      NULL, NULL, err_iov, err_buftype);
-	if (rc == -EOPNOTSUPP) {
-		if (err_iov[0].iov_base && err_buftype[0] != CIFS_NO_BUFFER &&
-		    ((struct smb2_hdr *)err_iov[0].iov_base)->Command == SMB2_CREATE &&
-		    ((struct smb2_hdr *)err_iov[0].iov_base)->Status == STATUS_STOPPED_ON_SYMLINK) {
-			rc = smb2_parse_symlink_response(cifs_sb, err_iov, &data->symlink_target);
+	if (rc) {
+		struct smb2_hdr *hdr = err_iov[0].iov_base;
+
+		if (unlikely(!hdr || err_buftype[0] == CIFS_NO_BUFFER))
+			goto out;
+		if (rc == -EOPNOTSUPP && hdr->Command == SMB2_CREATE &&
+		    hdr->Status == STATUS_STOPPED_ON_SYMLINK) {
+			rc = smb2_parse_symlink_response(cifs_sb, err_iov,
+							 &data->symlink_target);
 			if (rc)
 				goto out;
-		}
-		*reparse = true;
-		create_options |= OPEN_REPARSE_POINT;
 
-		/* Failed on a symbolic link - query a reparse point info */
-		cifs_get_readable_path(tcon, full_path, &cfile);
-		rc = smb2_compound_op(xid, tcon, cifs_sb, full_path, FILE_READ_ATTRIBUTES,
-				      FILE_OPEN, create_options, ACL_NO_MODE, data,
-				      SMB2_OP_QUERY_INFO, cfile, NULL, NULL, NULL, NULL);
+			*reparse = true;
+			create_options |= OPEN_REPARSE_POINT;
+
+			/* Failed on a symbolic link - query a reparse point info */
+			cifs_get_readable_path(tcon, full_path, &cfile);
+			rc = smb2_compound_op(xid, tcon, cifs_sb, full_path,
+					      FILE_READ_ATTRIBUTES, FILE_OPEN,
+					      create_options, ACL_NO_MODE, data,
+					      SMB2_OP_QUERY_INFO, cfile, NULL, NULL,
+					      NULL, NULL);
+			goto out;
+		} else if (rc != -EREMOTE && IS_ENABLED(CONFIG_CIFS_DFS_UPCALL) &&
+			   hdr->Status == STATUS_OBJECT_NAME_INVALID) {
+			/*
+			 * Handle weird Windows SMB server behaviour. It responds with
+			 * STATUS_OBJECT_NAME_INVALID code to SMB2 QUERY_INFO request
+			 * for "\<server>\<dfsname>\<linkpath>" DFS reference,
+			 * where <dfsname> contains non-ASCII unicode symbols.
+			 */
+			rc = -EREMOTE;
+		}
+		if (rc == -EREMOTE && IS_ENABLED(CONFIG_CIFS_DFS_UPCALL) && cifs_sb &&
+		    (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_NO_DFS))
+			rc = -EOPNOTSUPP;
 	}
 
 out:
diff --git a/fs/cifs/smb2ops.c b/fs/cifs/smb2ops.c
index d33b00ac37de2..dc160de7a6de4 100644
--- a/fs/cifs/smb2ops.c
+++ b/fs/cifs/smb2ops.c
@@ -796,7 +796,9 @@ smb2_is_path_accessible(const unsigned int xid, struct cifs_tcon *tcon,
 	int rc;
 	__le16 *utf16_path;
 	__u8 oplock = SMB2_OPLOCK_LEVEL_NONE;
+	int err_buftype = CIFS_NO_BUFFER;
 	struct cifs_open_parms oparms;
+	struct kvec err_iov = {};
 	struct cifs_fid fid;
 	struct cached_fid *cfid;
 
@@ -820,14 +822,32 @@ smb2_is_path_accessible(const unsigned int xid, struct cifs_tcon *tcon,
 	oparms.fid = &fid;
 	oparms.reconnect = false;
 
-	rc = SMB2_open(xid, &oparms, utf16_path, &oplock, NULL, NULL, NULL,
-		       NULL);
+	rc = SMB2_open(xid, &oparms, utf16_path, &oplock, NULL, NULL,
+		       &err_iov, &err_buftype);
 	if (rc) {
-		kfree(utf16_path);
-		return rc;
+		struct smb2_hdr *hdr = err_iov.iov_base;
+
+		if (unlikely(!hdr || err_buftype == CIFS_NO_BUFFER))
+			goto out;
+		/*
+		 * Handle weird Windows SMB server behaviour. It responds with
+		 * STATUS_OBJECT_NAME_INVALID code to SMB2 QUERY_INFO request
+		 * for "\<server>\<dfsname>\<linkpath>" DFS reference,
+		 * where <dfsname> contains non-ASCII unicode symbols.
+		 */
+		if (rc != -EREMOTE && IS_ENABLED(CONFIG_CIFS_DFS_UPCALL) &&
+		    hdr->Status == STATUS_OBJECT_NAME_INVALID)
+			rc = -EREMOTE;
+		if (rc == -EREMOTE && IS_ENABLED(CONFIG_CIFS_DFS_UPCALL) && cifs_sb &&
+		    (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_NO_DFS))
+			rc = -EOPNOTSUPP;
+		goto out;
 	}
 
 	rc = SMB2_close(xid, tcon, fid.persistent_fid, fid.volatile_fid);
+
+out:
+	free_rsp_buf(err_buftype, err_iov.iov_base);
 	kfree(utf16_path);
 	return rc;
 }
-- 
GitLab


From 9fd29a5bae6e8f94b410374099a6fddb253d2d5f Mon Sep 17 00:00:00 2001
From: Paulo Alcantara <pc@cjr.nz>
Date: Tue, 4 Oct 2022 18:41:20 -0300
Subject: [PATCH 480/875] cifs: use fs_context for automounts

Use filesystem context support to handle dfs links.

Signed-off-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/cifs_dfs_ref.c | 100 +++++++++++++++++------------------------
 1 file changed, 40 insertions(+), 60 deletions(-)

diff --git a/fs/cifs/cifs_dfs_ref.c b/fs/cifs/cifs_dfs_ref.c
index b0864da9ef434..020e71fe1454e 100644
--- a/fs/cifs/cifs_dfs_ref.c
+++ b/fs/cifs/cifs_dfs_ref.c
@@ -258,61 +258,23 @@ compose_mount_options_err:
 	goto compose_mount_options_out;
 }
 
-/**
- * cifs_dfs_do_mount - mounts specified path using DFS full path
- *
- * Always pass down @fullpath to smb3_do_mount() so we can use the root server
- * to perform failover in case we failed to connect to the first target in the
- * referral.
- *
- * @mntpt:		directory entry for the path we are trying to automount
- * @cifs_sb:		parent/root superblock
- * @fullpath:		full path in UNC format
- */
-static struct vfsmount *cifs_dfs_do_mount(struct dentry *mntpt,
-					  struct cifs_sb_info *cifs_sb,
-					  const char *fullpath)
-{
-	struct vfsmount *mnt;
-	char *mountdata;
-	char *devname;
-
-	devname = kstrdup(fullpath, GFP_KERNEL);
-	if (!devname)
-		return ERR_PTR(-ENOMEM);
-
-	convert_delimiter(devname, '/');
-
-	/* TODO: change to call fs_context_for_mount(), fill in context directly, call fc_mount */
-
-	/* See afs_mntpt_do_automount in fs/afs/mntpt.c for an example */
-
-	/* strip first '\' from fullpath */
-	mountdata = cifs_compose_mount_options(cifs_sb->ctx->mount_options,
-					       fullpath + 1, NULL, NULL);
-	if (IS_ERR(mountdata)) {
-		kfree(devname);
-		return (struct vfsmount *)mountdata;
-	}
-
-	mnt = vfs_submount(mntpt, &cifs_fs_type, devname, mountdata);
-	kfree(mountdata);
-	kfree(devname);
-	return mnt;
-}
-
 /*
  * Create a vfsmount that we can automount
  */
-static struct vfsmount *cifs_dfs_do_automount(struct dentry *mntpt)
+static struct vfsmount *cifs_dfs_do_automount(struct path *path)
 {
+	int rc;
+	struct dentry *mntpt = path->dentry;
+	struct fs_context *fc;
 	struct cifs_sb_info *cifs_sb;
-	void *page;
+	void *page = NULL;
+	struct smb3_fs_context *ctx, *cur_ctx;
+	struct smb3_fs_context tmp;
 	char *full_path;
 	struct vfsmount *mnt;
 
-	cifs_dbg(FYI, "in %s\n", __func__);
-	BUG_ON(IS_ROOT(mntpt));
+	if (IS_ROOT(mntpt))
+		return ERR_PTR(-ESTALE);
 
 	/*
 	 * The MSDFS spec states that paths in DFS referral requests and
@@ -321,29 +283,47 @@ static struct vfsmount *cifs_dfs_do_automount(struct dentry *mntpt)
 	 * gives us the latter, so we must adjust the result.
 	 */
 	cifs_sb = CIFS_SB(mntpt->d_sb);
-	if (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_NO_DFS) {
-		mnt = ERR_PTR(-EREMOTE);
-		goto cdda_exit;
-	}
+	if (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_NO_DFS)
+		return ERR_PTR(-EREMOTE);
+
+	cur_ctx = cifs_sb->ctx;
+
+	fc = fs_context_for_submount(path->mnt->mnt_sb->s_type, mntpt);
+	if (IS_ERR(fc))
+		return ERR_CAST(fc);
+
+	ctx = smb3_fc2context(fc);
 
 	page = alloc_dentry_path();
 	/* always use tree name prefix */
 	full_path = build_path_from_dentry_optional_prefix(mntpt, page, true);
 	if (IS_ERR(full_path)) {
 		mnt = ERR_CAST(full_path);
-		goto free_full_path;
+		goto out;
 	}
 
-	convert_delimiter(full_path, '\\');
+	convert_delimiter(full_path, '/');
 	cifs_dbg(FYI, "%s: full_path: %s\n", __func__, full_path);
 
-	mnt = cifs_dfs_do_mount(mntpt, cifs_sb, full_path);
-	cifs_dbg(FYI, "%s: cifs_dfs_do_mount:%s , mnt:%p\n", __func__, full_path + 1, mnt);
+	tmp = *cur_ctx;
+	tmp.source = full_path;
+	tmp.UNC = tmp.prepath = NULL;
+
+	rc = smb3_fs_context_dup(ctx, &tmp);
+	if (rc) {
+		mnt = ERR_PTR(rc);
+		goto out;
+	}
+
+	rc = smb3_parse_devname(full_path, ctx);
+	if (!rc)
+		mnt = fc_mount(fc);
+	else
+		mnt = ERR_PTR(rc);
 
-free_full_path:
+out:
+	put_fs_context(fc);
 	free_dentry_path(page);
-cdda_exit:
-	cifs_dbg(FYI, "leaving %s\n" , __func__);
 	return mnt;
 }
 
@@ -354,9 +334,9 @@ struct vfsmount *cifs_dfs_d_automount(struct path *path)
 {
 	struct vfsmount *newmnt;
 
-	cifs_dbg(FYI, "in %s\n", __func__);
+	cifs_dbg(FYI, "%s: %pd\n", __func__, path->dentry);
 
-	newmnt = cifs_dfs_do_automount(path->dentry);
+	newmnt = cifs_dfs_do_automount(path);
 	if (IS_ERR(newmnt)) {
 		cifs_dbg(FYI, "leaving %s [automount failed]\n" , __func__);
 		return newmnt;
-- 
GitLab


From abdb1742a312388651f04ca04e6e2ec2b0af5288 Mon Sep 17 00:00:00 2001
From: Paulo Alcantara <pc@cjr.nz>
Date: Tue, 4 Oct 2022 18:41:27 -0300
Subject: [PATCH 481/875] cifs: get rid of mount options string parsing

After switching to filesystem context support, we no longer need to
handle mount options string when chasing dfs referrals.  Now, we set
the new values directly into smb3_fs_context.

Start working on a separate source file to handle most dfs related
mount functions as connect.c has already became too big.  The
remaining functions will be moved gradually in follow-up patches.

Signed-off-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/Makefile       |   2 +-
 fs/cifs/cifs_dfs_ref.c | 141 +----------------------------------------
 fs/cifs/cifsfs.c       |   6 --
 fs/cifs/cifsproto.h    |   7 +-
 fs/cifs/connect.c      | 100 ++---------------------------
 fs/cifs/dfs.c          |  76 ++++++++++++++++++++++
 fs/cifs/dfs.h          |  16 +++++
 7 files changed, 101 insertions(+), 247 deletions(-)
 create mode 100644 fs/cifs/dfs.c
 create mode 100644 fs/cifs/dfs.h

diff --git a/fs/cifs/Makefile b/fs/cifs/Makefile
index 7c9785973f496..304a7f6cc13ac 100644
--- a/fs/cifs/Makefile
+++ b/fs/cifs/Makefile
@@ -21,7 +21,7 @@ cifs-$(CONFIG_CIFS_XATTR) += xattr.o
 
 cifs-$(CONFIG_CIFS_UPCALL) += cifs_spnego.o
 
-cifs-$(CONFIG_CIFS_DFS_UPCALL) += cifs_dfs_ref.o dfs_cache.o
+cifs-$(CONFIG_CIFS_DFS_UPCALL) += cifs_dfs_ref.o dfs_cache.o dfs.o
 
 cifs-$(CONFIG_CIFS_SWN_UPCALL) += netlink.o cifs_swn.o
 
diff --git a/fs/cifs/cifs_dfs_ref.c b/fs/cifs/cifs_dfs_ref.c
index 020e71fe1454e..cae8a52c6d9a0 100644
--- a/fs/cifs/cifs_dfs_ref.c
+++ b/fs/cifs/cifs_dfs_ref.c
@@ -60,7 +60,7 @@ void cifs_dfs_release_automount_timer(void)
  * Returns pointer to the built string, or a ERR_PTR. Caller is responsible
  * for freeing the returned string.
  */
-static char *
+char *
 cifs_build_devname(char *nodename, const char *prepath)
 {
 	size_t pplen;
@@ -119,145 +119,6 @@ cifs_build_devname(char *nodename, const char *prepath)
 	return dev;
 }
 
-
-/**
- * cifs_compose_mount_options	-	creates mount options for referral
- * @sb_mountdata:	parent/root DFS mount options (template)
- * @fullpath:		full path in UNC format
- * @ref:		optional server's referral
- * @devname:		return the built cifs device name if passed pointer not NULL
- * creates mount options for submount based on template options sb_mountdata
- * and replacing unc,ip,prefixpath options with ones we've got form ref_unc.
- *
- * Returns: pointer to new mount options or ERR_PTR.
- * Caller is responsible for freeing returned value if it is not error.
- */
-char *cifs_compose_mount_options(const char *sb_mountdata,
-				 const char *fullpath,
-				 const struct dfs_info3_param *ref,
-				 char **devname)
-{
-	int rc;
-	char *name;
-	char *mountdata = NULL;
-	const char *prepath = NULL;
-	int md_len;
-	char *tkn_e;
-	char *srvIP = NULL;
-	char sep = ',';
-	int off, noff;
-
-	if (sb_mountdata == NULL)
-		return ERR_PTR(-EINVAL);
-
-	if (ref) {
-		if (WARN_ON_ONCE(!ref->node_name || ref->path_consumed < 0))
-			return ERR_PTR(-EINVAL);
-
-		if (strlen(fullpath) - ref->path_consumed) {
-			prepath = fullpath + ref->path_consumed;
-			/* skip initial delimiter */
-			if (*prepath == '/' || *prepath == '\\')
-				prepath++;
-		}
-
-		name = cifs_build_devname(ref->node_name, prepath);
-		if (IS_ERR(name)) {
-			rc = PTR_ERR(name);
-			name = NULL;
-			goto compose_mount_options_err;
-		}
-	} else {
-		name = cifs_build_devname((char *)fullpath, NULL);
-		if (IS_ERR(name)) {
-			rc = PTR_ERR(name);
-			name = NULL;
-			goto compose_mount_options_err;
-		}
-	}
-
-	rc = dns_resolve_server_name_to_ip(name, &srvIP, NULL);
-	if (rc < 0) {
-		cifs_dbg(FYI, "%s: Failed to resolve server part of %s to IP: %d\n",
-			 __func__, name, rc);
-		goto compose_mount_options_err;
-	}
-
-	/*
-	 * In most cases, we'll be building a shorter string than the original,
-	 * but we do have to assume that the address in the ip= option may be
-	 * much longer than the original. Add the max length of an address
-	 * string to the length of the original string to allow for worst case.
-	 */
-	md_len = strlen(sb_mountdata) + INET6_ADDRSTRLEN;
-	mountdata = kzalloc(md_len + sizeof("ip=") + 1, GFP_KERNEL);
-	if (mountdata == NULL) {
-		rc = -ENOMEM;
-		goto compose_mount_options_err;
-	}
-
-	/* copy all options except of unc,ip,prefixpath */
-	off = 0;
-	if (strncmp(sb_mountdata, "sep=", 4) == 0) {
-			sep = sb_mountdata[4];
-			strncpy(mountdata, sb_mountdata, 5);
-			off += 5;
-	}
-
-	do {
-		tkn_e = strchr(sb_mountdata + off, sep);
-		if (tkn_e == NULL)
-			noff = strlen(sb_mountdata + off);
-		else
-			noff = tkn_e - (sb_mountdata + off) + 1;
-
-		if (strncasecmp(sb_mountdata + off, "cruid=", 6) == 0) {
-			off += noff;
-			continue;
-		}
-		if (strncasecmp(sb_mountdata + off, "unc=", 4) == 0) {
-			off += noff;
-			continue;
-		}
-		if (strncasecmp(sb_mountdata + off, "ip=", 3) == 0) {
-			off += noff;
-			continue;
-		}
-		if (strncasecmp(sb_mountdata + off, "prefixpath=", 11) == 0) {
-			off += noff;
-			continue;
-		}
-		strncat(mountdata, sb_mountdata + off, noff);
-		off += noff;
-	} while (tkn_e);
-	strcat(mountdata, sb_mountdata + off);
-	mountdata[md_len] = '\0';
-
-	/* copy new IP and ref share name */
-	if (mountdata[strlen(mountdata) - 1] != sep)
-		strncat(mountdata, &sep, 1);
-	strcat(mountdata, "ip=");
-	strcat(mountdata, srvIP);
-
-	if (devname)
-		*devname = name;
-	else
-		kfree(name);
-
-	/*cifs_dbg(FYI, "%s: parent mountdata: %s\n", __func__, sb_mountdata);*/
-	/*cifs_dbg(FYI, "%s: submount mountdata: %s\n", __func__, mountdata );*/
-
-compose_mount_options_out:
-	kfree(srvIP);
-	return mountdata;
-
-compose_mount_options_err:
-	kfree(mountdata);
-	mountdata = ERR_PTR(rc);
-	kfree(name);
-	goto compose_mount_options_out;
-}
-
 /*
  * Create a vfsmount that we can automount
  */
diff --git a/fs/cifs/cifsfs.c b/fs/cifs/cifsfs.c
index 914cbb9de482c..10e00c6249228 100644
--- a/fs/cifs/cifsfs.c
+++ b/fs/cifs/cifsfs.c
@@ -896,12 +896,6 @@ cifs_smb3_do_mount(struct file_system_type *fs_type,
 		goto out;
 	}
 
-	rc = cifs_setup_volume_info(cifs_sb->ctx, NULL, NULL);
-	if (rc) {
-		root = ERR_PTR(rc);
-		goto out;
-	}
-
 	rc = cifs_setup_cifs_sb(cifs_sb);
 	if (rc) {
 		root = ERR_PTR(rc);
diff --git a/fs/cifs/cifsproto.h b/fs/cifs/cifsproto.h
index 7d4b37eeec98b..4b1f7315ca162 100644
--- a/fs/cifs/cifsproto.h
+++ b/fs/cifs/cifsproto.h
@@ -75,9 +75,7 @@ extern char *cifs_build_path_to_root(struct smb3_fs_context *ctx,
 				     struct cifs_tcon *tcon,
 				     int add_treename);
 extern char *build_wildcard_path_from_dentry(struct dentry *direntry);
-extern char *cifs_compose_mount_options(const char *sb_mountdata,
-		const char *fullpath, const struct dfs_info3_param *ref,
-		char **devname);
+char *cifs_build_devname(char *nodename, const char *prepath);
 extern void delete_mid(struct mid_q_entry *mid);
 extern void release_mid(struct mid_q_entry *mid);
 extern void cifs_wake_up_task(struct mid_q_entry *mid);
@@ -561,9 +559,6 @@ extern int check_mf_symlink(unsigned int xid, struct cifs_tcon *tcon,
 extern int E_md4hash(const unsigned char *passwd, unsigned char *p16,
 			const struct nls_table *codepage);
 
-extern int
-cifs_setup_volume_info(struct smb3_fs_context *ctx, const char *mntopts, const char *devname);
-
 extern struct TCP_Server_Info *
 cifs_find_tcp_session(struct smb3_fs_context *ctx);
 
diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c
index b04706835e028..94d1741ced215 100644
--- a/fs/cifs/connect.c
+++ b/fs/cifs/connect.c
@@ -46,6 +46,7 @@
 #include "smbdirect.h"
 #include "dns_resolve.h"
 #ifdef CONFIG_CIFS_DFS_UPCALL
+#include "dfs.h"
 #include "dfs_cache.h"
 #endif
 #include "fs_context.h"
@@ -3397,95 +3398,8 @@ build_unc_path_to_root(const struct smb3_fs_context *ctx,
 	cifs_dbg(FYI, "%s: full_path=%s\n", __func__, full_path);
 	return full_path;
 }
-
-/*
- * expand_dfs_referral - Update cifs_sb from dfs referral path
- *
- * cifs_sb->ctx->mount_options will be (re-)allocated to a string containing updated options for the
- * submount.  Otherwise it will be left untouched.
- */
-static int expand_dfs_referral(struct mount_ctx *mnt_ctx, const char *full_path,
-			       struct dfs_info3_param *referral)
-{
-	int rc;
-	struct cifs_sb_info *cifs_sb = mnt_ctx->cifs_sb;
-	struct smb3_fs_context *ctx = mnt_ctx->fs_ctx;
-	char *fake_devname = NULL, *mdata = NULL;
-
-	mdata = cifs_compose_mount_options(cifs_sb->ctx->mount_options, full_path + 1, referral,
-					   &fake_devname);
-	if (IS_ERR(mdata)) {
-		rc = PTR_ERR(mdata);
-		mdata = NULL;
-	} else {
-		/*
-		 * We can not clear out the whole structure since we no longer have an explicit
-		 * function to parse a mount-string. Instead we need to clear out the individual
-		 * fields that are no longer valid.
-		 */
-		kfree(ctx->prepath);
-		ctx->prepath = NULL;
-		rc = cifs_setup_volume_info(ctx, mdata, fake_devname);
-	}
-	kfree(fake_devname);
-	kfree(cifs_sb->ctx->mount_options);
-	cifs_sb->ctx->mount_options = mdata;
-
-	return rc;
-}
 #endif
 
-/* TODO: all callers to this are broken. We are not parsing mount_options here
- * we should pass a clone of the original context?
- */
-int
-cifs_setup_volume_info(struct smb3_fs_context *ctx, const char *mntopts, const char *devname)
-{
-	int rc;
-
-	if (devname) {
-		cifs_dbg(FYI, "%s: devname=%s\n", __func__, devname);
-		rc = smb3_parse_devname(devname, ctx);
-		if (rc) {
-			cifs_dbg(VFS, "%s: failed to parse %s: %d\n", __func__, devname, rc);
-			return rc;
-		}
-	}
-
-	if (mntopts) {
-		char *ip;
-
-		rc = smb3_parse_opt(mntopts, "ip", &ip);
-		if (rc) {
-			cifs_dbg(VFS, "%s: failed to parse ip options: %d\n", __func__, rc);
-			return rc;
-		}
-
-		rc = cifs_convert_address((struct sockaddr *)&ctx->dstaddr, ip, strlen(ip));
-		kfree(ip);
-		if (!rc) {
-			cifs_dbg(VFS, "%s: failed to convert ip address\n", __func__);
-			return -EINVAL;
-		}
-	}
-
-	if (ctx->nullauth) {
-		cifs_dbg(FYI, "Anonymous login\n");
-		kfree(ctx->username);
-		ctx->username = NULL;
-	} else if (ctx->username) {
-		/* BB fixme parse for domain name here */
-		cifs_dbg(FYI, "Username: %s\n", ctx->username);
-	} else {
-		cifs_dbg(VFS, "No username specified\n");
-	/* In userspace mount helper we can get user name from alternate
-	   locations such as env variables and files on disk */
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
 static int
 cifs_are_all_path_components_accessible(struct TCP_Server_Info *server,
 					unsigned int xid,
@@ -3630,7 +3544,6 @@ static int connect_dfs_target(struct mount_ctx *mnt_ctx, const char *full_path,
 	int rc;
 	struct dfs_info3_param ref = {};
 	struct cifs_sb_info *cifs_sb = mnt_ctx->cifs_sb;
-	char *oldmnt = cifs_sb->ctx->mount_options;
 
 	cifs_dbg(FYI, "%s: full_path=%s ref_path=%s target=%s\n", __func__, full_path, ref_path,
 		 dfs_cache_get_tgt_name(tit));
@@ -3639,15 +3552,14 @@ static int connect_dfs_target(struct mount_ctx *mnt_ctx, const char *full_path,
 	if (rc)
 		goto out;
 
-	rc = expand_dfs_referral(mnt_ctx, full_path, &ref);
+	rc = dfs_parse_target_referral(full_path + 1, &ref, mnt_ctx->fs_ctx);
 	if (rc)
 		goto out;
 
-	/* Connect to new target only if we were redirected (e.g. mount options changed) */
-	if (oldmnt != cifs_sb->ctx->mount_options) {
-		mount_put_conns(mnt_ctx);
-		rc = mount_get_dfs_conns(mnt_ctx);
-	}
+	/* XXX: maybe check if we were actually redirected and avoid reconnecting? */
+	mount_put_conns(mnt_ctx);
+	rc = mount_get_dfs_conns(mnt_ctx);
+
 	if (!rc) {
 		if (cifs_is_referral_server(mnt_ctx->tcon, &ref))
 			set_root_ses(mnt_ctx);
diff --git a/fs/cifs/dfs.c b/fs/cifs/dfs.c
new file mode 100644
index 0000000000000..0b15d7e9f818a
--- /dev/null
+++ b/fs/cifs/dfs.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Paulo Alcantara <palcantara@suse.de>
+ */
+
+#include "cifsproto.h"
+#include "cifs_debug.h"
+#include "dns_resolve.h"
+#include "fs_context.h"
+#include "dfs.h"
+
+/* Resolve UNC server name and set destination ip address in fs context */
+static int resolve_unc(const char *path, struct smb3_fs_context *ctx)
+{
+	int rc;
+	char *ip = NULL;
+
+	rc = dns_resolve_server_name_to_ip(path, &ip, NULL);
+	if (rc < 0) {
+		cifs_dbg(FYI, "%s: failed to resolve UNC server name: %d\n", __func__, rc);
+		return rc;
+	}
+
+	if (!cifs_convert_address((struct sockaddr *)&ctx->dstaddr, ip, strlen(ip))) {
+		cifs_dbg(VFS, "%s: could not determinate destination address\n", __func__);
+		rc = -EHOSTUNREACH;
+	} else
+		rc = 0;
+
+	kfree(ip);
+	return rc;
+}
+
+/**
+ * dfs_parse_target_referral - set fs context for dfs target referral
+ *
+ * @full_path: full path in UNC format.
+ * @ref: dfs referral pointer.
+ * @ctx: smb3 fs context pointer.
+ *
+ * Return zero if dfs referral was parsed correctly, otherwise non-zero.
+ */
+int dfs_parse_target_referral(const char *full_path, const struct dfs_info3_param *ref,
+			      struct smb3_fs_context *ctx)
+{
+	int rc;
+	const char *prepath = NULL;
+	char *path;
+
+	if (!full_path || !*full_path || !ref || !ctx)
+		return -EINVAL;
+
+	if (WARN_ON_ONCE(!ref->node_name || ref->path_consumed < 0))
+		return -EINVAL;
+
+	if (strlen(full_path) - ref->path_consumed) {
+		prepath = full_path + ref->path_consumed;
+		/* skip initial delimiter */
+		if (*prepath == '/' || *prepath == '\\')
+			prepath++;
+	}
+
+	path = cifs_build_devname(ref->node_name, prepath);
+	if (IS_ERR(path))
+		return PTR_ERR(path);
+
+	rc = smb3_parse_devname(path, ctx);
+	if (rc)
+		goto out;
+
+	rc = resolve_unc(path, ctx);
+
+out:
+	kfree(path);
+	return rc;
+}
diff --git a/fs/cifs/dfs.h b/fs/cifs/dfs.h
new file mode 100644
index 0000000000000..af09903b435a1
--- /dev/null
+++ b/fs/cifs/dfs.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022 Paulo Alcantara <palcantara@suse.de>
+ */
+
+#ifndef _CIFS_DFS_H
+#define _CIFS_DFS_H
+
+#include "cifsglob.h"
+#include "fs_context.h"
+
+int dfs_parse_target_referral(const char *full_path, const struct dfs_info3_param *ref,
+			      struct smb3_fs_context *ctx);
+
+
+#endif /* _CIFS_DFS_H */
-- 
GitLab


From 2301bc103ac4acb6d6b6e5860eeed448c4ba2df0 Mon Sep 17 00:00:00 2001
From: Paulo Alcantara <pc@cjr.nz>
Date: Tue, 4 Oct 2022 18:41:31 -0300
Subject: [PATCH 482/875] cifs: remove unused smb3_fs_context::mount_options

Just remove it as it's no longer used during mount.

Signed-off-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/fs_context.c | 9 ---------
 fs/cifs/fs_context.h | 2 --
 2 files changed, 11 deletions(-)

diff --git a/fs/cifs/fs_context.c b/fs/cifs/fs_context.c
index 2c92a821e0284..40fbf46886ccf 100644
--- a/fs/cifs/fs_context.c
+++ b/fs/cifs/fs_context.c
@@ -308,7 +308,6 @@ smb3_fs_context_dup(struct smb3_fs_context *new_ctx, struct smb3_fs_context *ctx
 {
 	memcpy(new_ctx, ctx, sizeof(*ctx));
 	new_ctx->prepath = NULL;
-	new_ctx->mount_options = NULL;
 	new_ctx->nodename = NULL;
 	new_ctx->username = NULL;
 	new_ctx->password = NULL;
@@ -321,7 +320,6 @@ smb3_fs_context_dup(struct smb3_fs_context *new_ctx, struct smb3_fs_context *ctx
 	 * Make sure to stay in sync with smb3_cleanup_fs_context_contents()
 	 */
 	DUP_CTX_STR(prepath);
-	DUP_CTX_STR(mount_options);
 	DUP_CTX_STR(username);
 	DUP_CTX_STR(password);
 	DUP_CTX_STR(server_hostname);
@@ -569,17 +567,12 @@ static const struct fs_context_operations smb3_fs_context_ops = {
 static int smb3_fs_context_parse_monolithic(struct fs_context *fc,
 					   void *data)
 {
-	struct smb3_fs_context *ctx = smb3_fc2context(fc);
 	char *options = data, *key;
 	int ret = 0;
 
 	if (!options)
 		return 0;
 
-	ctx->mount_options = kstrdup(data, GFP_KERNEL);
-	if (ctx->mount_options == NULL)
-		return -ENOMEM;
-
 	ret = security_sb_eat_lsm_opts(options, &fc->security);
 	if (ret)
 		return ret;
@@ -1581,8 +1574,6 @@ smb3_cleanup_fs_context_contents(struct smb3_fs_context *ctx)
 	/*
 	 * Make sure this stays in sync with smb3_fs_context_dup()
 	 */
-	kfree(ctx->mount_options);
-	ctx->mount_options = NULL;
 	kfree(ctx->username);
 	ctx->username = NULL;
 	kfree_sensitive(ctx->password);
diff --git a/fs/cifs/fs_context.h b/fs/cifs/fs_context.h
index bbaee4c2281f8..159bcfd509d40 100644
--- a/fs/cifs/fs_context.h
+++ b/fs/cifs/fs_context.h
@@ -264,8 +264,6 @@ struct smb3_fs_context {
 	__u16 compression; /* compression algorithm 0xFFFF default 0=disabled */
 	bool rootfs:1; /* if it's a SMB root file system */
 	bool witness:1; /* use witness protocol */
-
-	char *mount_options;
 };
 
 extern const struct fs_parameter_spec smb3_fs_parameters[];
-- 
GitLab


From 6d740164d8903e6a0e98c30f80fac6af19ce0a21 Mon Sep 17 00:00:00 2001
From: Paulo Alcantara <pc@cjr.nz>
Date: Tue, 4 Oct 2022 18:41:36 -0300
Subject: [PATCH 483/875] cifs: set resolved ip in sockaddr

All callers from dns_resolve_server_name_to_ip() used to convert the
ip addr string back to sockaddr, so do that inside
dns_resolve_server_name_to_ip() and avoid duplicating code.

Signed-off-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/connect.c     | 28 +++++++++++--------------
 fs/cifs/dfs.c         | 24 +--------------------
 fs/cifs/dfs_cache.c   | 17 +++++----------
 fs/cifs/dns_resolve.c | 49 +++++++++++++++++++++----------------------
 fs/cifs/dns_resolve.h |  4 +++-
 fs/cifs/misc.c        | 36 +++++++++----------------------
 6 files changed, 55 insertions(+), 103 deletions(-)

diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c
index 94d1741ced215..af386c5f019e7 100644
--- a/fs/cifs/connect.c
+++ b/fs/cifs/connect.c
@@ -91,7 +91,8 @@ static int reconn_set_ipaddr_from_hostname(struct TCP_Server_Info *server)
 {
 	int rc;
 	int len;
-	char *unc, *ipaddr = NULL;
+	char *unc;
+	struct sockaddr_storage ss;
 	time64_t expiry, now;
 	unsigned long ttl = SMB_DNS_RESOLVE_INTERVAL_DEFAULT;
 
@@ -111,7 +112,11 @@ static int reconn_set_ipaddr_from_hostname(struct TCP_Server_Info *server)
 	}
 	scnprintf(unc, len, "\\\\%s", server->hostname);
 
-	rc = dns_resolve_server_name_to_ip(unc, &ipaddr, &expiry);
+	spin_lock(&server->srv_lock);
+	ss = server->dstaddr;
+	spin_unlock(&server->srv_lock);
+
+	rc = dns_resolve_server_name_to_ip(unc, (struct sockaddr *)&ss, &expiry);
 	kfree(unc);
 
 	if (rc < 0) {
@@ -121,22 +126,13 @@ static int reconn_set_ipaddr_from_hostname(struct TCP_Server_Info *server)
 	}
 
 	spin_lock(&server->srv_lock);
-	rc = cifs_convert_address((struct sockaddr *)&server->dstaddr, ipaddr,
-				  strlen(ipaddr));
+	memcpy(&server->dstaddr, &ss, sizeof(server->dstaddr));
 	spin_unlock(&server->srv_lock);
-	kfree(ipaddr);
 
-	/* rc == 1 means success here */
-	if (rc) {
-		now = ktime_get_real_seconds();
-		if (expiry && expiry > now)
-			/*
-			 * To make sure we don't use the cached entry, retry 1s
-			 * after expiry.
-			 */
-			ttl = max_t(unsigned long, expiry - now, SMB_DNS_RESOLVE_INTERVAL_MIN) + 1;
-	}
-	rc = !rc ? -1 : 0;
+	now = ktime_get_real_seconds();
+	if (expiry && expiry > now)
+		/* To make sure we don't use the cached entry, retry 1s */
+		ttl = max_t(unsigned long, expiry - now, SMB_DNS_RESOLVE_INTERVAL_MIN) + 1;
 
 requeue_resolve:
 	cifs_dbg(FYI, "%s: next dns resolution scheduled for %lu seconds in the future\n",
diff --git a/fs/cifs/dfs.c b/fs/cifs/dfs.c
index 0b15d7e9f818a..ce21438cadec9 100644
--- a/fs/cifs/dfs.c
+++ b/fs/cifs/dfs.c
@@ -9,28 +9,6 @@
 #include "fs_context.h"
 #include "dfs.h"
 
-/* Resolve UNC server name and set destination ip address in fs context */
-static int resolve_unc(const char *path, struct smb3_fs_context *ctx)
-{
-	int rc;
-	char *ip = NULL;
-
-	rc = dns_resolve_server_name_to_ip(path, &ip, NULL);
-	if (rc < 0) {
-		cifs_dbg(FYI, "%s: failed to resolve UNC server name: %d\n", __func__, rc);
-		return rc;
-	}
-
-	if (!cifs_convert_address((struct sockaddr *)&ctx->dstaddr, ip, strlen(ip))) {
-		cifs_dbg(VFS, "%s: could not determinate destination address\n", __func__);
-		rc = -EHOSTUNREACH;
-	} else
-		rc = 0;
-
-	kfree(ip);
-	return rc;
-}
-
 /**
  * dfs_parse_target_referral - set fs context for dfs target referral
  *
@@ -68,7 +46,7 @@ int dfs_parse_target_referral(const char *full_path, const struct dfs_info3_para
 	if (rc)
 		goto out;
 
-	rc = resolve_unc(path, ctx);
+	rc = dns_resolve_server_name_to_ip(path, (struct sockaddr *)&ctx->dstaddr, NULL);
 
 out:
 	kfree(path);
diff --git a/fs/cifs/dfs_cache.c b/fs/cifs/dfs_cache.c
index e70915ad75410..17b6d533c9666 100644
--- a/fs/cifs/dfs_cache.c
+++ b/fs/cifs/dfs_cache.c
@@ -1314,8 +1314,7 @@ static bool target_share_equal(struct TCP_Server_Info *server, const char *s1, c
 	char unc[sizeof("\\\\") + SERVER_NAME_LENGTH] = {0};
 	const char *host;
 	size_t hostlen;
-	char *ip = NULL;
-	struct sockaddr sa;
+	struct sockaddr_storage ss;
 	bool match;
 	int rc;
 
@@ -1330,23 +1329,17 @@ static bool target_share_equal(struct TCP_Server_Info *server, const char *s1, c
 	extract_unc_hostname(s1, &host, &hostlen);
 	scnprintf(unc, sizeof(unc), "\\\\%.*s", (int)hostlen, host);
 
-	rc = dns_resolve_server_name_to_ip(unc, &ip, NULL);
+	rc = dns_resolve_server_name_to_ip(unc, (struct sockaddr *)&ss, NULL);
 	if (rc < 0) {
 		cifs_dbg(FYI, "%s: could not resolve %.*s. assuming server address matches.\n",
 			 __func__, (int)hostlen, host);
 		return true;
 	}
 
-	if (!cifs_convert_address(&sa, ip, strlen(ip))) {
-		cifs_dbg(VFS, "%s: failed to convert address \'%s\'. skip address matching.\n",
-			 __func__, ip);
-	} else {
-		cifs_server_lock(server);
-		match = cifs_match_ipaddr((struct sockaddr *)&server->dstaddr, &sa);
-		cifs_server_unlock(server);
-	}
+	cifs_server_lock(server);
+	match = cifs_match_ipaddr((struct sockaddr *)&server->dstaddr, (struct sockaddr *)&ss);
+	cifs_server_unlock(server);
 
-	kfree(ip);
 	return match;
 }
 
diff --git a/fs/cifs/dns_resolve.c b/fs/cifs/dns_resolve.c
index 0458d28d71aa6..8bf8978bc5d66 100644
--- a/fs/cifs/dns_resolve.c
+++ b/fs/cifs/dns_resolve.c
@@ -12,6 +12,7 @@
  *
  */
 
+#include <linux/inet.h>
 #include <linux/slab.h>
 #include <linux/dns_resolver.h>
 #include "dns_resolve.h"
@@ -25,17 +26,13 @@
  * @ip_addr: Where to return the IP address.
  * @expiry: Where to return the expiry time for the dns record.
  *
- * The IP address will be returned in string form, and the caller is
- * responsible for freeing it.
- *
- * Returns length of result on success, -ve on error.
+ * Returns zero success, -ve on error.
  */
 int
-dns_resolve_server_name_to_ip(const char *unc, char **ip_addr, time64_t *expiry)
+dns_resolve_server_name_to_ip(const char *unc, struct sockaddr *ip_addr, time64_t *expiry)
 {
-	struct sockaddr_storage ss;
 	const char *hostname, *sep;
-	char *name;
+	char *ip;
 	int len, rc;
 
 	if (!ip_addr || !unc)
@@ -60,30 +57,32 @@ dns_resolve_server_name_to_ip(const char *unc, char **ip_addr, time64_t *expiry)
 			 __func__, unc);
 
 	/* Try to interpret hostname as an IPv4 or IPv6 address */
-	rc = cifs_convert_address((struct sockaddr *)&ss, hostname, len);
-	if (rc > 0)
-		goto name_is_IP_address;
+	rc = cifs_convert_address(ip_addr, hostname, len);
+	if (rc > 0) {
+		cifs_dbg(FYI, "%s: unc is IP, skipping dns upcall: %*.*s\n", __func__, len, len,
+			 hostname);
+		return 0;
+	}
 
 	/* Perform the upcall */
 	rc = dns_query(current->nsproxy->net_ns, NULL, hostname, len,
-		       NULL, ip_addr, expiry, false);
-	if (rc < 0)
+		       NULL, &ip, expiry, false);
+	if (rc < 0) {
 		cifs_dbg(FYI, "%s: unable to resolve: %*.*s\n",
 			 __func__, len, len, hostname);
-	else
+	} else {
 		cifs_dbg(FYI, "%s: resolved: %*.*s to %s expiry %llu\n",
-			 __func__, len, len, hostname, *ip_addr,
+			 __func__, len, len, hostname, ip,
 			 expiry ? (*expiry) : 0);
-	return rc;
 
-name_is_IP_address:
-	name = kmalloc(len + 1, GFP_KERNEL);
-	if (!name)
-		return -ENOMEM;
-	memcpy(name, hostname, len);
-	name[len] = 0;
-	cifs_dbg(FYI, "%s: unc is IP, skipping dns upcall: %s\n",
-		 __func__, name);
-	*ip_addr = name;
-	return 0;
+		rc = cifs_convert_address(ip_addr, ip, strlen(ip));
+		kfree(ip);
+
+		if (!rc) {
+			cifs_dbg(FYI, "%s: unable to determine ip address\n", __func__);
+			rc = -EHOSTUNREACH;
+		} else
+			rc = 0;
+	}
+	return rc;
 }
diff --git a/fs/cifs/dns_resolve.h b/fs/cifs/dns_resolve.h
index afc0df381246b..6eb0c15a24406 100644
--- a/fs/cifs/dns_resolve.h
+++ b/fs/cifs/dns_resolve.h
@@ -11,8 +11,10 @@
 #ifndef _DNS_RESOLVE_H
 #define _DNS_RESOLVE_H
 
+#include <linux/net.h>
+
 #ifdef __KERNEL__
-extern int dns_resolve_server_name_to_ip(const char *unc, char **ip_addr, time64_t *expiry);
+int dns_resolve_server_name_to_ip(const char *unc, struct sockaddr *ip_addr, time64_t *expiry);
 #endif /* KERNEL */
 
 #endif /* _DNS_RESOLVE_H */
diff --git a/fs/cifs/misc.c b/fs/cifs/misc.c
index 062175994e879..4d3c586785a59 100644
--- a/fs/cifs/misc.c
+++ b/fs/cifs/misc.c
@@ -1258,44 +1258,28 @@ int match_target_ip(struct TCP_Server_Info *server,
 		    bool *result)
 {
 	int rc;
-	char *target, *tip = NULL;
-	struct sockaddr tipaddr;
+	char *target;
+	struct sockaddr_storage ss;
 
 	*result = false;
 
 	target = kzalloc(share_len + 3, GFP_KERNEL);
-	if (!target) {
-		rc = -ENOMEM;
-		goto out;
-	}
+	if (!target)
+		return -ENOMEM;
 
 	scnprintf(target, share_len + 3, "\\\\%.*s", (int)share_len, share);
 
 	cifs_dbg(FYI, "%s: target name: %s\n", __func__, target + 2);
 
-	rc = dns_resolve_server_name_to_ip(target, &tip, NULL);
-	if (rc < 0)
-		goto out;
-
-	cifs_dbg(FYI, "%s: target ip: %s\n", __func__, tip);
+	rc = dns_resolve_server_name_to_ip(target, (struct sockaddr *)&ss, NULL);
+	kfree(target);
 
-	if (!cifs_convert_address(&tipaddr, tip, strlen(tip))) {
-		cifs_dbg(VFS, "%s: failed to convert target ip address\n",
-			 __func__);
-		rc = -EINVAL;
-		goto out;
-	}
+	if (rc < 0)
+		return rc;
 
-	*result = cifs_match_ipaddr((struct sockaddr *)&server->dstaddr,
-				    &tipaddr);
+	*result = cifs_match_ipaddr((struct sockaddr *)&server->dstaddr, (struct sockaddr *)&ss);
 	cifs_dbg(FYI, "%s: ip addresses match: %u\n", __func__, *result);
-	rc = 0;
-
-out:
-	kfree(target);
-	kfree(tip);
-
-	return rc;
+	return 0;
 }
 
 int cifs_update_super_prepath(struct cifs_sb_info *cifs_sb, char *prefix)
-- 
GitLab


From a73a26d97eca082fe13c964e5541543c1e78dc55 Mon Sep 17 00:00:00 2001
From: Paulo Alcantara <pc@cjr.nz>
Date: Tue, 11 Oct 2022 18:16:07 -0300
Subject: [PATCH 484/875] cifs: split out ses and tcon retrieval from
 mount_get_conns()

Introduce and export two helpers for getting session and tcon during
mount(2).  Those will be used by dfs when retrieving sessions and
tcons separately while chasing referrals.  Besides, export
cifs_mount_ctx structure as it will be used by dfs code as well.

No functional changes.

Signed-off-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/cifsglob.h  |  14 ++++++
 fs/cifs/cifsproto.h |   2 +
 fs/cifs/connect.c   | 101 +++++++++++++++++++++++++++-----------------
 3 files changed, 78 insertions(+), 39 deletions(-)

diff --git a/fs/cifs/cifsglob.h b/fs/cifs/cifsglob.h
index 82f2d3070c266..799e64427fdee 100644
--- a/fs/cifs/cifsglob.h
+++ b/fs/cifs/cifsglob.h
@@ -1760,6 +1760,20 @@ struct file_list {
 	struct cifsFileInfo *cfile;
 };
 
+struct cifs_mount_ctx {
+	struct cifs_sb_info *cifs_sb;
+	struct smb3_fs_context *fs_ctx;
+	unsigned int xid;
+	struct TCP_Server_Info *server;
+	struct cifs_ses *ses;
+	struct cifs_tcon *tcon;
+#ifdef CONFIG_CIFS_DFS_UPCALL
+	struct cifs_ses *root_ses;
+	uuid_t mount_id;
+	char *origin_fullpath, *leaf_fullpath;
+#endif
+};
+
 static inline void free_dfs_info_param(struct dfs_info3_param *param)
 {
 	if (param) {
diff --git a/fs/cifs/cifsproto.h b/fs/cifs/cifsproto.h
index 4b1f7315ca162..4ae3e83759411 100644
--- a/fs/cifs/cifsproto.h
+++ b/fs/cifs/cifsproto.h
@@ -242,6 +242,8 @@ extern int cifs_read_page_from_socket(struct TCP_Server_Info *server,
 					unsigned int page_offset,
 					unsigned int to_read);
 extern int cifs_setup_cifs_sb(struct cifs_sb_info *cifs_sb);
+int cifs_mount_get_session(struct cifs_mount_ctx *mnt_ctx);
+int cifs_mount_get_tcon(struct cifs_mount_ctx *mnt_ctx);
 extern int cifs_match_super(struct super_block *, void *);
 extern int cifs_mount(struct cifs_sb_info *cifs_sb, struct smb3_fs_context *ctx);
 extern void cifs_umount(struct cifs_sb_info *);
diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c
index af386c5f019e7..5e465025708de 100644
--- a/fs/cifs/connect.c
+++ b/fs/cifs/connect.c
@@ -62,20 +62,6 @@ extern bool disable_legacy_dialects;
 /* Drop the connection to not overload the server */
 #define NUM_STATUS_IO_TIMEOUT   5
 
-struct mount_ctx {
-	struct cifs_sb_info *cifs_sb;
-	struct smb3_fs_context *fs_ctx;
-	unsigned int xid;
-	struct TCP_Server_Info *server;
-	struct cifs_ses *ses;
-	struct cifs_tcon *tcon;
-#ifdef CONFIG_CIFS_DFS_UPCALL
-	struct cifs_ses *root_ses;
-	uuid_t mount_id;
-	char *origin_fullpath, *leaf_fullpath;
-#endif
-};
-
 static int ip_connect(struct TCP_Server_Info *server);
 static int generic_ip_connect(struct TCP_Server_Info *server);
 static void tlink_rb_insert(struct rb_root *root, struct tcon_link *new_tlink);
@@ -3191,7 +3177,7 @@ int cifs_setup_cifs_sb(struct cifs_sb_info *cifs_sb)
 }
 
 /* Release all succeed connections */
-static inline void mount_put_conns(struct mount_ctx *mnt_ctx)
+static inline void mount_put_conns(struct cifs_mount_ctx *mnt_ctx)
 {
 	int rc = 0;
 
@@ -3205,19 +3191,22 @@ static inline void mount_put_conns(struct mount_ctx *mnt_ctx)
 	free_xid(mnt_ctx->xid);
 }
 
-/* Get connections for tcp, ses and tcon */
-static int mount_get_conns(struct mount_ctx *mnt_ctx)
+int cifs_mount_get_session(struct cifs_mount_ctx *mnt_ctx)
 {
-	int rc = 0;
 	struct TCP_Server_Info *server = NULL;
+	struct smb3_fs_context *ctx;
 	struct cifs_ses *ses = NULL;
-	struct cifs_tcon *tcon = NULL;
-	struct smb3_fs_context *ctx = mnt_ctx->fs_ctx;
-	struct cifs_sb_info *cifs_sb = mnt_ctx->cifs_sb;
 	unsigned int xid;
+	int rc = 0;
 
 	xid = get_xid();
 
+	if (WARN_ON_ONCE(!mnt_ctx || !mnt_ctx->fs_ctx)) {
+		rc = -EINVAL;
+		goto out;
+	}
+	ctx = mnt_ctx->fs_ctx;
+
 	/* get a reference to a tcp session */
 	server = cifs_get_tcp_session(ctx, NULL);
 	if (IS_ERR(server)) {
@@ -3238,11 +3227,36 @@ static int mount_get_conns(struct mount_ctx *mnt_ctx)
 					    SMB2_GLOBAL_CAP_PERSISTENT_HANDLES))) {
 		cifs_server_dbg(VFS, "persistent handles not supported by server\n");
 		rc = -EOPNOTSUPP;
+	}
+
+out:
+	mnt_ctx->xid = xid;
+	mnt_ctx->server = server;
+	mnt_ctx->ses = ses;
+	mnt_ctx->tcon = NULL;
+
+	return rc;
+}
+
+int cifs_mount_get_tcon(struct cifs_mount_ctx *mnt_ctx)
+{
+	struct TCP_Server_Info *server;
+	struct cifs_sb_info *cifs_sb;
+	struct smb3_fs_context *ctx;
+	struct cifs_tcon *tcon = NULL;
+	int rc = 0;
+
+	if (WARN_ON_ONCE(!mnt_ctx || !mnt_ctx->server || !mnt_ctx->ses || !mnt_ctx->fs_ctx ||
+			 !mnt_ctx->cifs_sb)) {
+		rc = -EINVAL;
 		goto out;
 	}
+	server = mnt_ctx->server;
+	ctx = mnt_ctx->fs_ctx;
+	cifs_sb = mnt_ctx->cifs_sb;
 
 	/* search for existing tcon to this server share */
-	tcon = cifs_get_tcon(ses, ctx);
+	tcon = cifs_get_tcon(mnt_ctx->ses, ctx);
 	if (IS_ERR(tcon)) {
 		rc = PTR_ERR(tcon);
 		tcon = NULL;
@@ -3260,7 +3274,7 @@ static int mount_get_conns(struct mount_ctx *mnt_ctx)
 		 * reset of caps checks mount to see if unix extensions disabled
 		 * for just this mount.
 		 */
-		reset_cifs_unix_caps(xid, tcon, cifs_sb, ctx);
+		reset_cifs_unix_caps(mnt_ctx->xid, tcon, cifs_sb, ctx);
 		spin_lock(&tcon->ses->server->srv_lock);
 		if ((tcon->ses->server->tcpStatus == CifsNeedReconnect) &&
 		    (le64_to_cpu(tcon->fsUnixInfo.Capability) &
@@ -3276,7 +3290,7 @@ static int mount_get_conns(struct mount_ctx *mnt_ctx)
 
 	/* do not care if a following call succeed - informational */
 	if (!tcon->pipe && server->ops->qfs_tcon) {
-		server->ops->qfs_tcon(xid, tcon, cifs_sb);
+		server->ops->qfs_tcon(mnt_ctx->xid, tcon, cifs_sb);
 		if (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_RO_CACHE) {
 			if (tcon->fsDevInfo.DeviceCharacteristics &
 			    cpu_to_le32(FILE_READ_ONLY_DEVICE))
@@ -3309,14 +3323,22 @@ static int mount_get_conns(struct mount_ctx *mnt_ctx)
 		cifs_fscache_get_super_cookie(tcon);
 
 out:
-	mnt_ctx->server = server;
-	mnt_ctx->ses = ses;
 	mnt_ctx->tcon = tcon;
-	mnt_ctx->xid = xid;
-
 	return rc;
 }
 
+/* Get connections for tcp, ses and tcon */
+static int mount_get_conns(struct cifs_mount_ctx *mnt_ctx)
+{
+	int rc;
+
+	rc = cifs_mount_get_session(mnt_ctx);
+	if (rc)
+		return rc;
+
+	return cifs_mount_get_tcon(mnt_ctx);
+}
+
 static int mount_setup_tlink(struct cifs_sb_info *cifs_sb, struct cifs_ses *ses,
 			     struct cifs_tcon *tcon)
 {
@@ -3345,7 +3367,7 @@ static int mount_setup_tlink(struct cifs_sb_info *cifs_sb, struct cifs_ses *ses,
 
 #ifdef CONFIG_CIFS_DFS_UPCALL
 /* Get unique dfs connections */
-static int mount_get_dfs_conns(struct mount_ctx *mnt_ctx)
+static int mount_get_dfs_conns(struct cifs_mount_ctx *mnt_ctx)
 {
 	int rc;
 
@@ -3448,7 +3470,7 @@ cifs_are_all_path_components_accessible(struct TCP_Server_Info *server,
  *
  * Return -EREMOTE if it is, otherwise 0 or -errno.
  */
-static int is_path_remote(struct mount_ctx *mnt_ctx)
+static int is_path_remote(struct cifs_mount_ctx *mnt_ctx)
 {
 	int rc;
 	struct cifs_sb_info *cifs_sb = mnt_ctx->cifs_sb;
@@ -3492,7 +3514,7 @@ out:
 }
 
 #ifdef CONFIG_CIFS_DFS_UPCALL
-static void set_root_ses(struct mount_ctx *mnt_ctx)
+static void set_root_ses(struct cifs_mount_ctx *mnt_ctx)
 {
 	if (mnt_ctx->ses) {
 		spin_lock(&cifs_tcp_ses_lock);
@@ -3503,7 +3525,8 @@ static void set_root_ses(struct mount_ctx *mnt_ctx)
 	mnt_ctx->root_ses = mnt_ctx->ses;
 }
 
-static int is_dfs_mount(struct mount_ctx *mnt_ctx, bool *isdfs, struct dfs_cache_tgt_list *root_tl)
+static int is_dfs_mount(struct cifs_mount_ctx *mnt_ctx, bool *isdfs,
+			struct dfs_cache_tgt_list *root_tl)
 {
 	int rc;
 	struct cifs_sb_info *cifs_sb = mnt_ctx->cifs_sb;
@@ -3534,7 +3557,7 @@ static int is_dfs_mount(struct mount_ctx *mnt_ctx, bool *isdfs, struct dfs_cache
 	return 0;
 }
 
-static int connect_dfs_target(struct mount_ctx *mnt_ctx, const char *full_path,
+static int connect_dfs_target(struct cifs_mount_ctx *mnt_ctx, const char *full_path,
 			      const char *ref_path, struct dfs_cache_tgt_iterator *tit)
 {
 	int rc;
@@ -3568,7 +3591,7 @@ out:
 	return rc;
 }
 
-static int connect_dfs_root(struct mount_ctx *mnt_ctx, struct dfs_cache_tgt_list *root_tl)
+static int connect_dfs_root(struct cifs_mount_ctx *mnt_ctx, struct dfs_cache_tgt_list *root_tl)
 {
 	int rc;
 	char *full_path;
@@ -3613,7 +3636,7 @@ out:
 	return rc;
 }
 
-static int __follow_dfs_link(struct mount_ctx *mnt_ctx)
+static int __follow_dfs_link(struct cifs_mount_ctx *mnt_ctx)
 {
 	int rc;
 	struct cifs_sb_info *cifs_sb = mnt_ctx->cifs_sb;
@@ -3662,7 +3685,7 @@ out:
 	return rc;
 }
 
-static int follow_dfs_link(struct mount_ctx *mnt_ctx)
+static int follow_dfs_link(struct cifs_mount_ctx *mnt_ctx)
 {
 	int rc;
 	struct cifs_sb_info *cifs_sb = mnt_ctx->cifs_sb;
@@ -3695,7 +3718,7 @@ static int follow_dfs_link(struct mount_ctx *mnt_ctx)
 }
 
 /* Set up DFS referral paths for failover */
-static void setup_server_referral_paths(struct mount_ctx *mnt_ctx)
+static void setup_server_referral_paths(struct cifs_mount_ctx *mnt_ctx)
 {
 	struct TCP_Server_Info *server = mnt_ctx->server;
 
@@ -3710,7 +3733,7 @@ static void setup_server_referral_paths(struct mount_ctx *mnt_ctx)
 int cifs_mount(struct cifs_sb_info *cifs_sb, struct smb3_fs_context *ctx)
 {
 	int rc;
-	struct mount_ctx mnt_ctx = { .cifs_sb = cifs_sb, .fs_ctx = ctx, };
+	struct cifs_mount_ctx mnt_ctx = { .cifs_sb = cifs_sb, .fs_ctx = ctx, };
 	struct dfs_cache_tgt_list tl = DFS_CACHE_TGT_LIST_INIT(tl);
 	bool isdfs;
 
@@ -3770,7 +3793,7 @@ error:
 int cifs_mount(struct cifs_sb_info *cifs_sb, struct smb3_fs_context *ctx)
 {
 	int rc = 0;
-	struct mount_ctx mnt_ctx = { .cifs_sb = cifs_sb, .fs_ctx = ctx, };
+	struct cifs_mount_ctx mnt_ctx = { .cifs_sb = cifs_sb, .fs_ctx = ctx, };
 
 	rc = mount_get_conns(&mnt_ctx);
 	if (rc)
-- 
GitLab


From a1c0d00572fca4adcb40e1fbd3acd481fc75e20b Mon Sep 17 00:00:00 2001
From: Paulo Alcantara <pc@cjr.nz>
Date: Thu, 17 Nov 2022 13:23:49 -0300
Subject: [PATCH 485/875] cifs: share dfs connections and supers

When matching DFS superblocks we can't rely on either the server's
address or tcon's UNC name from mount(2) as the existing servers and
tcons might be connected to somewhere else.  Instead, check if
superblock is dfs, and if so, match its original source pathname with
the new mount's source pathname.

For DFS connections, instead of checking server's address, match its
referral path as it could be connected to different targets.

Signed-off-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/cifs_debug.c |   8 +
 fs/cifs/cifsglob.h   |   5 -
 fs/cifs/cifsproto.h  |   2 +
 fs/cifs/connect.c    | 417 +++++++------------------------------------
 fs/cifs/dfs.c        | 226 +++++++++++++++++++++++
 fs/cifs/dfs.h        |  15 ++
 fs/cifs/dfs_cache.c  |  14 +-
 fs/cifs/fs_context.c |   4 +
 fs/cifs/fs_context.h |   1 +
 9 files changed, 323 insertions(+), 369 deletions(-)

diff --git a/fs/cifs/cifs_debug.c b/fs/cifs/cifs_debug.c
index 90850da390aeb..56b23def4c95d 100644
--- a/fs/cifs/cifs_debug.c
+++ b/fs/cifs/cifs_debug.c
@@ -372,6 +372,14 @@ skip_rdma:
 		seq_printf(m, "\nIn Send: %d In MaxReq Wait: %d",
 				atomic_read(&server->in_send),
 				atomic_read(&server->num_waiters));
+		if (IS_ENABLED(CONFIG_CIFS_DFS_UPCALL)) {
+			if (server->origin_fullpath)
+				seq_printf(m, "\nDFS origin full path: %s",
+					   server->origin_fullpath);
+			if (server->leaf_fullpath)
+				seq_printf(m, "\nDFS leaf full path:   %s",
+					   server->leaf_fullpath);
+		}
 
 		seq_printf(m, "\n\n\tSessions: ");
 		i = 0;
diff --git a/fs/cifs/cifsglob.h b/fs/cifs/cifsglob.h
index 799e64427fdee..2e2976f1874fa 100644
--- a/fs/cifs/cifsglob.h
+++ b/fs/cifs/cifsglob.h
@@ -738,8 +738,6 @@ struct TCP_Server_Info {
 	bool use_swn_dstaddr;
 	struct sockaddr_storage swn_dstaddr;
 #endif
-#ifdef CONFIG_CIFS_DFS_UPCALL
-	bool is_dfs_conn; /* if a dfs connection */
 	struct mutex refpath_lock; /* protects leaf_fullpath */
 	/*
 	 * Canonical DFS full paths that were used to chase referrals in mount and reconnect.
@@ -753,7 +751,6 @@ struct TCP_Server_Info {
 	 * format: \\HOST\SHARE\[OPTIONAL PATH]
 	 */
 	char *origin_fullpath, *leaf_fullpath, *current_fullpath;
-#endif
 };
 
 static inline bool is_smb1(struct TCP_Server_Info *server)
@@ -1767,11 +1764,9 @@ struct cifs_mount_ctx {
 	struct TCP_Server_Info *server;
 	struct cifs_ses *ses;
 	struct cifs_tcon *tcon;
-#ifdef CONFIG_CIFS_DFS_UPCALL
 	struct cifs_ses *root_ses;
 	uuid_t mount_id;
 	char *origin_fullpath, *leaf_fullpath;
-#endif
 };
 
 static inline void free_dfs_info_param(struct dfs_info3_param *param)
diff --git a/fs/cifs/cifsproto.h b/fs/cifs/cifsproto.h
index 4ae3e83759411..4efe1bc9783e8 100644
--- a/fs/cifs/cifsproto.h
+++ b/fs/cifs/cifsproto.h
@@ -242,7 +242,9 @@ extern int cifs_read_page_from_socket(struct TCP_Server_Info *server,
 					unsigned int page_offset,
 					unsigned int to_read);
 extern int cifs_setup_cifs_sb(struct cifs_sb_info *cifs_sb);
+void cifs_mount_put_conns(struct cifs_mount_ctx *mnt_ctx);
 int cifs_mount_get_session(struct cifs_mount_ctx *mnt_ctx);
+int cifs_is_path_remote(struct cifs_mount_ctx *mnt_ctx);
 int cifs_mount_get_tcon(struct cifs_mount_ctx *mnt_ctx);
 extern int cifs_match_super(struct super_block *, void *);
 extern int cifs_mount(struct cifs_sb_info *cifs_sb, struct smb3_fs_context *ctx);
diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c
index 5e465025708de..a66cb23a954e2 100644
--- a/fs/cifs/connect.c
+++ b/fs/cifs/connect.c
@@ -546,16 +546,8 @@ static int reconnect_dfs_server(struct TCP_Server_Info *server)
 
 int cifs_reconnect(struct TCP_Server_Info *server, bool mark_smb_session)
 {
-	/* If tcp session is not an dfs connection, then reconnect to last target server */
-	spin_lock(&server->srv_lock);
-	if (!server->is_dfs_conn) {
-		spin_unlock(&server->srv_lock);
-		return __cifs_reconnect(server, mark_smb_session);
-	}
-	spin_unlock(&server->srv_lock);
-
 	mutex_lock(&server->refpath_lock);
-	if (!server->origin_fullpath || !server->leaf_fullpath) {
+	if (!server->leaf_fullpath) {
 		mutex_unlock(&server->refpath_lock);
 		return __cifs_reconnect(server, mark_smb_session);
 	}
@@ -1367,9 +1359,7 @@ match_port(struct TCP_Server_Info *server, struct sockaddr *addr)
 	return port == *sport;
 }
 
-static bool
-match_address(struct TCP_Server_Info *server, struct sockaddr *addr,
-	      struct sockaddr *srcaddr)
+static bool match_server_address(struct TCP_Server_Info *server, struct sockaddr *addr)
 {
 	switch (addr->sa_family) {
 	case AF_INET: {
@@ -1398,9 +1388,6 @@ match_address(struct TCP_Server_Info *server, struct sockaddr *addr,
 		return false; /* don't expect to be here */
 	}
 
-	if (!cifs_match_ipaddr(srcaddr, (struct sockaddr *)&server->srcaddr))
-		return false;
-
 	return true;
 }
 
@@ -1428,7 +1415,8 @@ match_security(struct TCP_Server_Info *server, struct smb3_fs_context *ctx)
 }
 
 /* this function must be called with srv_lock held */
-static int match_server(struct TCP_Server_Info *server, struct smb3_fs_context *ctx)
+static int match_server(struct TCP_Server_Info *server, struct smb3_fs_context *ctx,
+			bool dfs_super_cmp)
 {
 	struct sockaddr *addr = (struct sockaddr *)&ctx->dstaddr;
 
@@ -1453,15 +1441,30 @@ static int match_server(struct TCP_Server_Info *server, struct smb3_fs_context *
 	if (!net_eq(cifs_net_ns(server), current->nsproxy->net_ns))
 		return 0;
 
-	if (strcasecmp(server->hostname, ctx->server_hostname))
-		return 0;
-
-	if (!match_address(server, addr,
-			   (struct sockaddr *)&ctx->srcaddr))
-		return 0;
-
-	if (!match_port(server, addr))
+	if (!cifs_match_ipaddr((struct sockaddr *)&ctx->srcaddr,
+			       (struct sockaddr *)&server->srcaddr))
 		return 0;
+	/*
+	 * When matching DFS superblocks, we only check for original source pathname as the
+	 * currently connected target might be different than the one parsed earlier in i.e.
+	 * mount.cifs(8).
+	 */
+	if (dfs_super_cmp) {
+		if (!ctx->source || !server->origin_fullpath ||
+		    strcasecmp(server->origin_fullpath, ctx->source))
+			return 0;
+	} else {
+		/* Skip addr, hostname and port matching for DFS connections */
+		if (server->leaf_fullpath) {
+			if (!ctx->leaf_fullpath ||
+			    strcasecmp(server->leaf_fullpath, ctx->leaf_fullpath))
+				return 0;
+		} else if (strcasecmp(server->hostname, ctx->server_hostname) ||
+			   !match_server_address(server, addr) ||
+			   !match_port(server, addr)) {
+			return 0;
+		}
+	}
 
 	if (!match_security(server, ctx))
 		return 0;
@@ -1489,23 +1492,11 @@ cifs_find_tcp_session(struct smb3_fs_context *ctx)
 	spin_lock(&cifs_tcp_ses_lock);
 	list_for_each_entry(server, &cifs_tcp_ses_list, tcp_ses_list) {
 		spin_lock(&server->srv_lock);
-#ifdef CONFIG_CIFS_DFS_UPCALL
-		/*
-		 * DFS failover implementation in cifs_reconnect() requires unique tcp sessions for
-		 * DFS connections to do failover properly, so avoid sharing them with regular
-		 * shares or even links that may connect to same server but having completely
-		 * different failover targets.
-		 */
-		if (server->is_dfs_conn) {
-			spin_unlock(&server->srv_lock);
-			continue;
-		}
-#endif
 		/*
 		 * Skip ses channels since they're only handled in lower layers
 		 * (e.g. cifs_send_recv).
 		 */
-		if (CIFS_SERVER_IS_CHAN(server) || !match_server(server, ctx)) {
+		if (CIFS_SERVER_IS_CHAN(server) || !match_server(server, ctx, false)) {
 			spin_unlock(&server->srv_lock);
 			continue;
 		}
@@ -1600,6 +1591,15 @@ cifs_get_tcp_session(struct smb3_fs_context *ctx,
 		goto out_err;
 	}
 
+	if (ctx->leaf_fullpath) {
+		tcp_ses->leaf_fullpath = kstrdup(ctx->leaf_fullpath, GFP_KERNEL);
+		if (!tcp_ses->leaf_fullpath) {
+			rc = -ENOMEM;
+			goto out_err;
+		}
+		tcp_ses->current_fullpath = tcp_ses->leaf_fullpath;
+	}
+
 	if (ctx->nosharesock)
 		tcp_ses->nosharesock = true;
 
@@ -1748,6 +1748,7 @@ out_err:
 		if (CIFS_SERVER_IS_CHAN(tcp_ses))
 			cifs_put_tcp_session(tcp_ses->primary_server, false);
 		kfree(tcp_ses->hostname);
+		kfree(tcp_ses->leaf_fullpath);
 		if (tcp_ses->ssocket)
 			sock_release(tcp_ses->ssocket);
 		kfree(tcp_ses);
@@ -2277,11 +2278,12 @@ get_ses_fail:
 }
 
 /* this function must be called with tc_lock held */
-static int match_tcon(struct cifs_tcon *tcon, struct smb3_fs_context *ctx)
+static int match_tcon(struct cifs_tcon *tcon, struct smb3_fs_context *ctx, bool dfs_super_cmp)
 {
 	if (tcon->status == TID_EXITING)
 		return 0;
-	if (strncmp(tcon->tree_name, ctx->UNC, MAX_TREE_SIZE))
+	/* Skip UNC validation when matching DFS superblocks */
+	if (!dfs_super_cmp && strncmp(tcon->tree_name, ctx->UNC, MAX_TREE_SIZE))
 		return 0;
 	if (tcon->seal != ctx->seal)
 		return 0;
@@ -2304,7 +2306,7 @@ cifs_find_tcon(struct cifs_ses *ses, struct smb3_fs_context *ctx)
 	spin_lock(&cifs_tcp_ses_lock);
 	list_for_each_entry(tcon, &ses->tcon_list, tcon_list) {
 		spin_lock(&tcon->tc_lock);
-		if (!match_tcon(tcon, ctx)) {
+		if (!match_tcon(tcon, ctx, false)) {
 			spin_unlock(&tcon->tc_lock);
 			continue;
 		}
@@ -2699,6 +2701,7 @@ cifs_match_super(struct super_block *sb, void *data)
 	struct cifs_ses *ses;
 	struct cifs_tcon *tcon;
 	struct tcon_link *tlink;
+	bool dfs_super_cmp;
 	int rc = 0;
 
 	spin_lock(&cifs_tcp_ses_lock);
@@ -2713,14 +2716,16 @@ cifs_match_super(struct super_block *sb, void *data)
 	ses = tcon->ses;
 	tcp_srv = ses->server;
 
+	dfs_super_cmp = IS_ENABLED(CONFIG_CIFS_DFS_UPCALL) && tcp_srv->origin_fullpath;
+
 	ctx = mnt_data->ctx;
 
 	spin_lock(&tcp_srv->srv_lock);
 	spin_lock(&ses->ses_lock);
 	spin_lock(&tcon->tc_lock);
-	if (!match_server(tcp_srv, ctx) ||
+	if (!match_server(tcp_srv, ctx, dfs_super_cmp) ||
 	    !match_session(ses, ctx) ||
-	    !match_tcon(tcon, ctx) ||
+	    !match_tcon(tcon, ctx, dfs_super_cmp) ||
 	    !match_prepath(sb, mnt_data)) {
 		rc = 0;
 		goto out;
@@ -3177,7 +3182,7 @@ int cifs_setup_cifs_sb(struct cifs_sb_info *cifs_sb)
 }
 
 /* Release all succeed connections */
-static inline void mount_put_conns(struct cifs_mount_ctx *mnt_ctx)
+void cifs_mount_put_conns(struct cifs_mount_ctx *mnt_ctx)
 {
 	int rc = 0;
 
@@ -3327,18 +3332,6 @@ out:
 	return rc;
 }
 
-/* Get connections for tcp, ses and tcon */
-static int mount_get_conns(struct cifs_mount_ctx *mnt_ctx)
-{
-	int rc;
-
-	rc = cifs_mount_get_session(mnt_ctx);
-	if (rc)
-		return rc;
-
-	return cifs_mount_get_tcon(mnt_ctx);
-}
-
 static int mount_setup_tlink(struct cifs_sb_info *cifs_sb, struct cifs_ses *ses,
 			     struct cifs_tcon *tcon)
 {
@@ -3365,59 +3358,6 @@ static int mount_setup_tlink(struct cifs_sb_info *cifs_sb, struct cifs_ses *ses,
 	return 0;
 }
 
-#ifdef CONFIG_CIFS_DFS_UPCALL
-/* Get unique dfs connections */
-static int mount_get_dfs_conns(struct cifs_mount_ctx *mnt_ctx)
-{
-	int rc;
-
-	mnt_ctx->fs_ctx->nosharesock = true;
-	rc = mount_get_conns(mnt_ctx);
-	if (mnt_ctx->server) {
-		cifs_dbg(FYI, "%s: marking tcp session as a dfs connection\n", __func__);
-		spin_lock(&mnt_ctx->server->srv_lock);
-		mnt_ctx->server->is_dfs_conn = true;
-		spin_unlock(&mnt_ctx->server->srv_lock);
-	}
-	return rc;
-}
-
-/*
- * cifs_build_path_to_root returns full path to root when we do not have an
- * existing connection (tcon)
- */
-static char *
-build_unc_path_to_root(const struct smb3_fs_context *ctx,
-		       const struct cifs_sb_info *cifs_sb, bool useppath)
-{
-	char *full_path, *pos;
-	unsigned int pplen = useppath && ctx->prepath ?
-		strlen(ctx->prepath) + 1 : 0;
-	unsigned int unc_len = strnlen(ctx->UNC, MAX_TREE_SIZE + 1);
-
-	if (unc_len > MAX_TREE_SIZE)
-		return ERR_PTR(-EINVAL);
-
-	full_path = kmalloc(unc_len + pplen + 1, GFP_KERNEL);
-	if (full_path == NULL)
-		return ERR_PTR(-ENOMEM);
-
-	memcpy(full_path, ctx->UNC, unc_len);
-	pos = full_path + unc_len;
-
-	if (pplen) {
-		*pos = CIFS_DIR_SEP(cifs_sb);
-		memcpy(pos + 1, ctx->prepath, pplen);
-		pos += pplen;
-	}
-
-	*pos = '\0'; /* add trailing null */
-	convert_delimiter(full_path, CIFS_DIR_SEP(cifs_sb));
-	cifs_dbg(FYI, "%s: full_path=%s\n", __func__, full_path);
-	return full_path;
-}
-#endif
-
 static int
 cifs_are_all_path_components_accessible(struct TCP_Server_Info *server,
 					unsigned int xid,
@@ -3470,7 +3410,7 @@ cifs_are_all_path_components_accessible(struct TCP_Server_Info *server,
  *
  * Return -EREMOTE if it is, otherwise 0 or -errno.
  */
-static int is_path_remote(struct cifs_mount_ctx *mnt_ctx)
+int cifs_is_path_remote(struct cifs_mount_ctx *mnt_ctx)
 {
 	int rc;
 	struct cifs_sb_info *cifs_sb = mnt_ctx->cifs_sb;
@@ -3514,250 +3454,19 @@ out:
 }
 
 #ifdef CONFIG_CIFS_DFS_UPCALL
-static void set_root_ses(struct cifs_mount_ctx *mnt_ctx)
-{
-	if (mnt_ctx->ses) {
-		spin_lock(&cifs_tcp_ses_lock);
-		mnt_ctx->ses->ses_count++;
-		spin_unlock(&cifs_tcp_ses_lock);
-		dfs_cache_add_refsrv_session(&mnt_ctx->mount_id, mnt_ctx->ses);
-	}
-	mnt_ctx->root_ses = mnt_ctx->ses;
-}
-
-static int is_dfs_mount(struct cifs_mount_ctx *mnt_ctx, bool *isdfs,
-			struct dfs_cache_tgt_list *root_tl)
-{
-	int rc;
-	struct cifs_sb_info *cifs_sb = mnt_ctx->cifs_sb;
-	struct smb3_fs_context *ctx = mnt_ctx->fs_ctx;
-
-	*isdfs = true;
-
-	rc = mount_get_conns(mnt_ctx);
-	/*
-	 * If called with 'nodfs' mount option, then skip DFS resolving.  Otherwise unconditionally
-	 * try to get an DFS referral (even cached) to determine whether it is an DFS mount.
-	 *
-	 * Skip prefix path to provide support for DFS referrals from w2k8 servers which don't seem
-	 * to respond with PATH_NOT_COVERED to requests that include the prefix.
-	 */
-	if ((cifs_sb->mnt_cifs_flags & CIFS_MOUNT_NO_DFS) ||
-	    dfs_cache_find(mnt_ctx->xid, mnt_ctx->ses, cifs_sb->local_nls, cifs_remap(cifs_sb),
-			   ctx->UNC + 1, NULL, root_tl)) {
-		if (rc)
-			return rc;
-		/* Check if it is fully accessible and then mount it */
-		rc = is_path_remote(mnt_ctx);
-		if (!rc)
-			*isdfs = false;
-		else if (rc != -EREMOTE)
-			return rc;
-	}
-	return 0;
-}
-
-static int connect_dfs_target(struct cifs_mount_ctx *mnt_ctx, const char *full_path,
-			      const char *ref_path, struct dfs_cache_tgt_iterator *tit)
-{
-	int rc;
-	struct dfs_info3_param ref = {};
-	struct cifs_sb_info *cifs_sb = mnt_ctx->cifs_sb;
-
-	cifs_dbg(FYI, "%s: full_path=%s ref_path=%s target=%s\n", __func__, full_path, ref_path,
-		 dfs_cache_get_tgt_name(tit));
-
-	rc = dfs_cache_get_tgt_referral(ref_path, tit, &ref);
-	if (rc)
-		goto out;
-
-	rc = dfs_parse_target_referral(full_path + 1, &ref, mnt_ctx->fs_ctx);
-	if (rc)
-		goto out;
-
-	/* XXX: maybe check if we were actually redirected and avoid reconnecting? */
-	mount_put_conns(mnt_ctx);
-	rc = mount_get_dfs_conns(mnt_ctx);
-
-	if (!rc) {
-		if (cifs_is_referral_server(mnt_ctx->tcon, &ref))
-			set_root_ses(mnt_ctx);
-		rc = dfs_cache_update_tgthint(mnt_ctx->xid, mnt_ctx->root_ses, cifs_sb->local_nls,
-					      cifs_remap(cifs_sb), ref_path, tit);
-	}
-
-out:
-	free_dfs_info_param(&ref);
-	return rc;
-}
-
-static int connect_dfs_root(struct cifs_mount_ctx *mnt_ctx, struct dfs_cache_tgt_list *root_tl)
-{
-	int rc;
-	char *full_path;
-	struct cifs_sb_info *cifs_sb = mnt_ctx->cifs_sb;
-	struct smb3_fs_context *ctx = mnt_ctx->fs_ctx;
-	struct dfs_cache_tgt_iterator *tit;
-
-	/* Put initial connections as they might be shared with other mounts.  We need unique dfs
-	 * connections per mount to properly failover, so mount_get_dfs_conns() must be used from
-	 * now on.
-	 */
-	mount_put_conns(mnt_ctx);
-	mount_get_dfs_conns(mnt_ctx);
-	set_root_ses(mnt_ctx);
-
-	full_path = build_unc_path_to_root(ctx, cifs_sb, true);
-	if (IS_ERR(full_path))
-		return PTR_ERR(full_path);
-
-	mnt_ctx->origin_fullpath = dfs_cache_canonical_path(ctx->UNC, cifs_sb->local_nls,
-							    cifs_remap(cifs_sb));
-	if (IS_ERR(mnt_ctx->origin_fullpath)) {
-		rc = PTR_ERR(mnt_ctx->origin_fullpath);
-		mnt_ctx->origin_fullpath = NULL;
-		goto out;
-	}
-
-	/* Try all dfs root targets */
-	for (rc = -ENOENT, tit = dfs_cache_get_tgt_iterator(root_tl);
-	     tit; tit = dfs_cache_get_next_tgt(root_tl, tit)) {
-		rc = connect_dfs_target(mnt_ctx, full_path, mnt_ctx->origin_fullpath + 1, tit);
-		if (!rc) {
-			mnt_ctx->leaf_fullpath = kstrdup(mnt_ctx->origin_fullpath, GFP_KERNEL);
-			if (!mnt_ctx->leaf_fullpath)
-				rc = -ENOMEM;
-			break;
-		}
-	}
-
-out:
-	kfree(full_path);
-	return rc;
-}
-
-static int __follow_dfs_link(struct cifs_mount_ctx *mnt_ctx)
-{
-	int rc;
-	struct cifs_sb_info *cifs_sb = mnt_ctx->cifs_sb;
-	struct smb3_fs_context *ctx = mnt_ctx->fs_ctx;
-	char *full_path;
-	struct dfs_cache_tgt_list tl = DFS_CACHE_TGT_LIST_INIT(tl);
-	struct dfs_cache_tgt_iterator *tit;
-
-	full_path = build_unc_path_to_root(ctx, cifs_sb, true);
-	if (IS_ERR(full_path))
-		return PTR_ERR(full_path);
-
-	kfree(mnt_ctx->leaf_fullpath);
-	mnt_ctx->leaf_fullpath = dfs_cache_canonical_path(full_path, cifs_sb->local_nls,
-							  cifs_remap(cifs_sb));
-	if (IS_ERR(mnt_ctx->leaf_fullpath)) {
-		rc = PTR_ERR(mnt_ctx->leaf_fullpath);
-		mnt_ctx->leaf_fullpath = NULL;
-		goto out;
-	}
-
-	/* Get referral from dfs link */
-	rc = dfs_cache_find(mnt_ctx->xid, mnt_ctx->root_ses, cifs_sb->local_nls,
-			    cifs_remap(cifs_sb), mnt_ctx->leaf_fullpath + 1, NULL, &tl);
-	if (rc)
-		goto out;
-
-	/* Try all dfs link targets.  If an I/O fails from currently connected DFS target with an
-	 * error other than STATUS_PATH_NOT_COVERED (-EREMOTE), then retry it from other targets as
-	 * specified in MS-DFSC "3.1.5.2 I/O Operation to Target Fails with an Error Other Than
-	 * STATUS_PATH_NOT_COVERED."
-	 */
-	for (rc = -ENOENT, tit = dfs_cache_get_tgt_iterator(&tl);
-	     tit; tit = dfs_cache_get_next_tgt(&tl, tit)) {
-		rc = connect_dfs_target(mnt_ctx, full_path, mnt_ctx->leaf_fullpath + 1, tit);
-		if (!rc) {
-			rc = is_path_remote(mnt_ctx);
-			if (!rc || rc == -EREMOTE)
-				break;
-		}
-	}
-
-out:
-	kfree(full_path);
-	dfs_cache_free_tgts(&tl);
-	return rc;
-}
-
-static int follow_dfs_link(struct cifs_mount_ctx *mnt_ctx)
-{
-	int rc;
-	struct cifs_sb_info *cifs_sb = mnt_ctx->cifs_sb;
-	struct smb3_fs_context *ctx = mnt_ctx->fs_ctx;
-	char *full_path;
-	int num_links = 0;
-
-	full_path = build_unc_path_to_root(ctx, cifs_sb, true);
-	if (IS_ERR(full_path))
-		return PTR_ERR(full_path);
-
-	kfree(mnt_ctx->origin_fullpath);
-	mnt_ctx->origin_fullpath = dfs_cache_canonical_path(full_path, cifs_sb->local_nls,
-							    cifs_remap(cifs_sb));
-	kfree(full_path);
-
-	if (IS_ERR(mnt_ctx->origin_fullpath)) {
-		rc = PTR_ERR(mnt_ctx->origin_fullpath);
-		mnt_ctx->origin_fullpath = NULL;
-		return rc;
-	}
-
-	do {
-		rc = __follow_dfs_link(mnt_ctx);
-		if (!rc || rc != -EREMOTE)
-			break;
-	} while (rc = -ELOOP, ++num_links < MAX_NESTED_LINKS);
-
-	return rc;
-}
-
-/* Set up DFS referral paths for failover */
-static void setup_server_referral_paths(struct cifs_mount_ctx *mnt_ctx)
-{
-	struct TCP_Server_Info *server = mnt_ctx->server;
-
-	mutex_lock(&server->refpath_lock);
-	server->origin_fullpath = mnt_ctx->origin_fullpath;
-	server->leaf_fullpath = mnt_ctx->leaf_fullpath;
-	server->current_fullpath = mnt_ctx->leaf_fullpath;
-	mutex_unlock(&server->refpath_lock);
-	mnt_ctx->origin_fullpath = mnt_ctx->leaf_fullpath = NULL;
-}
-
 int cifs_mount(struct cifs_sb_info *cifs_sb, struct smb3_fs_context *ctx)
 {
-	int rc;
 	struct cifs_mount_ctx mnt_ctx = { .cifs_sb = cifs_sb, .fs_ctx = ctx, };
-	struct dfs_cache_tgt_list tl = DFS_CACHE_TGT_LIST_INIT(tl);
 	bool isdfs;
+	int rc;
 
-	rc = is_dfs_mount(&mnt_ctx, &isdfs, &tl);
+	uuid_gen(&mnt_ctx.mount_id);
+	rc = dfs_mount_share(&mnt_ctx, &isdfs);
 	if (rc)
 		goto error;
 	if (!isdfs)
 		goto out;
 
-	/* proceed as DFS mount */
-	uuid_gen(&mnt_ctx.mount_id);
-	rc = connect_dfs_root(&mnt_ctx, &tl);
-	dfs_cache_free_tgts(&tl);
-
-	if (rc)
-		goto error;
-
-	rc = is_path_remote(&mnt_ctx);
-	if (rc)
-		rc = follow_dfs_link(&mnt_ctx);
-	if (rc)
-		goto error;
-
-	setup_server_referral_paths(&mnt_ctx);
 	/*
 	 * After reconnecting to a different server, unique ids won't match anymore, so we disable
 	 * serverino. This prevents dentry revalidation to think the dentry are stale (ESTALE).
@@ -3786,7 +3495,7 @@ error:
 	dfs_cache_put_refsrv_sessions(&mnt_ctx.mount_id);
 	kfree(mnt_ctx.origin_fullpath);
 	kfree(mnt_ctx.leaf_fullpath);
-	mount_put_conns(&mnt_ctx);
+	cifs_mount_put_conns(&mnt_ctx);
 	return rc;
 }
 #else
@@ -3795,17 +3504,19 @@ int cifs_mount(struct cifs_sb_info *cifs_sb, struct smb3_fs_context *ctx)
 	int rc = 0;
 	struct cifs_mount_ctx mnt_ctx = { .cifs_sb = cifs_sb, .fs_ctx = ctx, };
 
-	rc = mount_get_conns(&mnt_ctx);
+	rc = cifs_mount_get_session(&mnt_ctx);
 	if (rc)
 		goto error;
 
-	if (mnt_ctx.tcon) {
-		rc = is_path_remote(&mnt_ctx);
-		if (rc == -EREMOTE)
-			rc = -EOPNOTSUPP;
-		if (rc)
-			goto error;
-	}
+	rc = cifs_mount_get_tcon(&mnt_ctx);
+	if (rc)
+		goto error;
+
+	rc = cifs_is_path_remote(&mnt_ctx);
+	if (rc == -EREMOTE)
+		rc = -EOPNOTSUPP;
+	if (rc)
+		goto error;
 
 	rc = mount_setup_tlink(cifs_sb, mnt_ctx.ses, mnt_ctx.tcon);
 	if (rc)
@@ -3815,7 +3526,7 @@ int cifs_mount(struct cifs_sb_info *cifs_sb, struct smb3_fs_context *ctx)
 	return rc;
 
 error:
-	mount_put_conns(&mnt_ctx);
+	cifs_mount_put_conns(&mnt_ctx);
 	return rc;
 }
 #endif
diff --git a/fs/cifs/dfs.c b/fs/cifs/dfs.c
index ce21438cadec9..88a0cab335b4b 100644
--- a/fs/cifs/dfs.c
+++ b/fs/cifs/dfs.c
@@ -3,6 +3,7 @@
  * Copyright (c) 2022 Paulo Alcantara <palcantara@suse.de>
  */
 
+#include <linux/namei.h>
 #include "cifsproto.h"
 #include "cifs_debug.h"
 #include "dns_resolve.h"
@@ -52,3 +53,228 @@ out:
 	kfree(path);
 	return rc;
 }
+
+/*
+ * cifs_build_path_to_root returns full path to root when we do not have an
+ * existing connection (tcon)
+ */
+static char *build_unc_path_to_root(const struct smb3_fs_context *ctx,
+				    const struct cifs_sb_info *cifs_sb, bool useppath)
+{
+	char *full_path, *pos;
+	unsigned int pplen = useppath && ctx->prepath ? strlen(ctx->prepath) + 1 : 0;
+	unsigned int unc_len = strnlen(ctx->UNC, MAX_TREE_SIZE + 1);
+
+	if (unc_len > MAX_TREE_SIZE)
+		return ERR_PTR(-EINVAL);
+
+	full_path = kmalloc(unc_len + pplen + 1, GFP_KERNEL);
+	if (full_path == NULL)
+		return ERR_PTR(-ENOMEM);
+
+	memcpy(full_path, ctx->UNC, unc_len);
+	pos = full_path + unc_len;
+
+	if (pplen) {
+		*pos = CIFS_DIR_SEP(cifs_sb);
+		memcpy(pos + 1, ctx->prepath, pplen);
+		pos += pplen;
+	}
+
+	*pos = '\0'; /* add trailing null */
+	convert_delimiter(full_path, CIFS_DIR_SEP(cifs_sb));
+	cifs_dbg(FYI, "%s: full_path=%s\n", __func__, full_path);
+	return full_path;
+}
+
+static int get_session(struct cifs_mount_ctx *mnt_ctx, const char *full_path)
+{
+	struct smb3_fs_context *ctx = mnt_ctx->fs_ctx;
+	int rc;
+
+	ctx->leaf_fullpath = (char *)full_path;
+	rc = cifs_mount_get_session(mnt_ctx);
+	ctx->leaf_fullpath = NULL;
+
+	return rc;
+}
+
+static void set_root_ses(struct cifs_mount_ctx *mnt_ctx)
+{
+	if (mnt_ctx->ses) {
+		spin_lock(&cifs_tcp_ses_lock);
+		mnt_ctx->ses->ses_count++;
+		spin_unlock(&cifs_tcp_ses_lock);
+		dfs_cache_add_refsrv_session(&mnt_ctx->mount_id, mnt_ctx->ses);
+	}
+	mnt_ctx->root_ses = mnt_ctx->ses;
+}
+
+static int get_dfs_conn(struct cifs_mount_ctx *mnt_ctx, const char *ref_path, const char *full_path,
+			const struct dfs_cache_tgt_iterator *tit)
+{
+	struct smb3_fs_context *ctx = mnt_ctx->fs_ctx;
+	struct dfs_info3_param ref = {};
+	int rc;
+
+	rc = dfs_cache_get_tgt_referral(ref_path + 1, tit, &ref);
+	if (rc)
+		return rc;
+
+	rc = dfs_parse_target_referral(full_path + 1, &ref, ctx);
+	if (rc)
+		goto out;
+
+	cifs_mount_put_conns(mnt_ctx);
+	rc = get_session(mnt_ctx, ref_path);
+	if (rc)
+		goto out;
+
+	if (ref.flags & DFSREF_REFERRAL_SERVER)
+		set_root_ses(mnt_ctx);
+
+	rc = -EREMOTE;
+	if (ref.flags & DFSREF_STORAGE_SERVER) {
+		rc = cifs_mount_get_tcon(mnt_ctx);
+		if (rc)
+			goto out;
+
+		/* some servers may not advertise referral capability under ref.flags */
+		if (!(ref.flags & DFSREF_REFERRAL_SERVER) &&
+		    is_tcon_dfs(mnt_ctx->tcon))
+			set_root_ses(mnt_ctx);
+
+		rc = cifs_is_path_remote(mnt_ctx);
+	}
+
+out:
+	free_dfs_info_param(&ref);
+	return rc;
+}
+
+static int __dfs_mount_share(struct cifs_mount_ctx *mnt_ctx)
+{
+	struct cifs_sb_info *cifs_sb = mnt_ctx->cifs_sb;
+	struct smb3_fs_context *ctx = mnt_ctx->fs_ctx;
+	char *ref_path = NULL, *full_path = NULL;
+	struct dfs_cache_tgt_iterator *tit;
+	struct TCP_Server_Info *server;
+	char *origin_fullpath = NULL;
+	int num_links = 0;
+	int rc;
+
+	ref_path = dfs_get_path(cifs_sb, ctx->UNC);
+	if (IS_ERR(ref_path))
+		return PTR_ERR(ref_path);
+
+	full_path = build_unc_path_to_root(ctx, cifs_sb, true);
+	if (IS_ERR(full_path)) {
+		rc = PTR_ERR(full_path);
+		full_path = NULL;
+		goto out;
+	}
+
+	origin_fullpath = kstrdup(full_path, GFP_KERNEL);
+	if (!origin_fullpath) {
+		rc = -ENOMEM;
+		goto out;
+	}
+
+	do {
+		struct dfs_cache_tgt_list tl = DFS_CACHE_TGT_LIST_INIT(tl);
+
+		rc = dfs_get_referral(mnt_ctx, ref_path + 1, NULL, &tl);
+		if (rc)
+			break;
+
+		tit = dfs_cache_get_tgt_iterator(&tl);
+		if (!tit) {
+			cifs_dbg(VFS, "%s: dfs referral (%s) with no targets\n", __func__,
+				 ref_path + 1);
+			rc = -ENOENT;
+			dfs_cache_free_tgts(&tl);
+			break;
+		}
+
+		do {
+			rc = get_dfs_conn(mnt_ctx, ref_path, full_path, tit);
+			if (!rc)
+				break;
+			if (rc == -EREMOTE) {
+				if (++num_links > MAX_NESTED_LINKS) {
+					rc = -ELOOP;
+					break;
+				}
+				kfree(ref_path);
+				kfree(full_path);
+				ref_path = full_path = NULL;
+
+				full_path = build_unc_path_to_root(ctx, cifs_sb, true);
+				if (IS_ERR(full_path)) {
+					rc = PTR_ERR(full_path);
+					full_path = NULL;
+				} else {
+					ref_path = dfs_get_path(cifs_sb, full_path);
+					if (IS_ERR(ref_path)) {
+						rc = PTR_ERR(ref_path);
+						ref_path = NULL;
+					}
+				}
+				break;
+			}
+		} while ((tit = dfs_cache_get_next_tgt(&tl, tit)));
+		dfs_cache_free_tgts(&tl);
+	} while (rc == -EREMOTE);
+
+	if (!rc) {
+		server = mnt_ctx->server;
+
+		mutex_lock(&server->refpath_lock);
+		server->origin_fullpath = origin_fullpath;
+		server->current_fullpath = server->leaf_fullpath;
+		mutex_unlock(&server->refpath_lock);
+		origin_fullpath = NULL;
+	}
+
+out:
+	kfree(origin_fullpath);
+	kfree(ref_path);
+	kfree(full_path);
+	return rc;
+}
+
+int dfs_mount_share(struct cifs_mount_ctx *mnt_ctx, bool *isdfs)
+{
+	struct cifs_sb_info *cifs_sb = mnt_ctx->cifs_sb;
+	struct smb3_fs_context *ctx = mnt_ctx->fs_ctx;
+	int rc;
+
+	*isdfs = false;
+
+	rc = get_session(mnt_ctx, NULL);
+	if (rc)
+		return rc;
+	mnt_ctx->root_ses = mnt_ctx->ses;
+	/*
+	 * If called with 'nodfs' mount option, then skip DFS resolving.  Otherwise unconditionally
+	 * try to get an DFS referral (even cached) to determine whether it is an DFS mount.
+	 *
+	 * Skip prefix path to provide support for DFS referrals from w2k8 servers which don't seem
+	 * to respond with PATH_NOT_COVERED to requests that include the prefix.
+	 */
+	if ((cifs_sb->mnt_cifs_flags & CIFS_MOUNT_NO_DFS) ||
+	    dfs_get_referral(mnt_ctx, ctx->UNC + 1, NULL, NULL)) {
+		rc = cifs_mount_get_tcon(mnt_ctx);
+		if (rc)
+			return rc;
+
+		rc = cifs_is_path_remote(mnt_ctx);
+		if (!rc || rc != -EREMOTE)
+			return rc;
+	}
+
+	*isdfs = true;
+	set_root_ses(mnt_ctx);
+
+	return __dfs_mount_share(mnt_ctx);
+}
diff --git a/fs/cifs/dfs.h b/fs/cifs/dfs.h
index af09903b435a1..bbe2ec25b0c2e 100644
--- a/fs/cifs/dfs.h
+++ b/fs/cifs/dfs.h
@@ -8,9 +8,24 @@
 
 #include "cifsglob.h"
 #include "fs_context.h"
+#include "cifs_unicode.h"
 
 int dfs_parse_target_referral(const char *full_path, const struct dfs_info3_param *ref,
 			      struct smb3_fs_context *ctx);
+int dfs_mount_share(struct cifs_mount_ctx *mnt_ctx, bool *isdfs);
 
+static inline char *dfs_get_path(struct cifs_sb_info *cifs_sb, const char *path)
+{
+	return dfs_cache_canonical_path(path, cifs_sb->local_nls, cifs_remap(cifs_sb));
+}
+
+static inline int dfs_get_referral(struct cifs_mount_ctx *mnt_ctx, const char *path,
+				   struct dfs_info3_param *ref, struct dfs_cache_tgt_list *tl)
+{
+	struct cifs_sb_info *cifs_sb = mnt_ctx->cifs_sb;
+
+	return dfs_cache_find(mnt_ctx->xid, mnt_ctx->root_ses, cifs_sb->local_nls,
+			      cifs_remap(cifs_sb), path, ref, tl);
+}
 
 #endif /* _CIFS_DFS_H */
diff --git a/fs/cifs/dfs_cache.c b/fs/cifs/dfs_cache.c
index 17b6d533c9666..bf5e674f43b88 100644
--- a/fs/cifs/dfs_cache.c
+++ b/fs/cifs/dfs_cache.c
@@ -1519,12 +1519,8 @@ static void refresh_mounts(struct cifs_ses **sessions)
 
 	spin_lock(&cifs_tcp_ses_lock);
 	list_for_each_entry(server, &cifs_tcp_ses_list, tcp_ses_list) {
-		spin_lock(&server->srv_lock);
-		if (!server->is_dfs_conn) {
-			spin_unlock(&server->srv_lock);
+		if (!server->leaf_fullpath)
 			continue;
-		}
-		spin_unlock(&server->srv_lock);
 
 		list_for_each_entry(ses, &server->smb_ses_list, smb_ses_list) {
 			list_for_each_entry(tcon, &ses->tcon_list, tcon_list) {
@@ -1545,12 +1541,8 @@ static void refresh_mounts(struct cifs_ses **sessions)
 		list_del_init(&tcon->ulist);
 
 		mutex_lock(&server->refpath_lock);
-		if (server->origin_fullpath) {
-			if (server->leaf_fullpath && strcasecmp(server->leaf_fullpath,
-								server->origin_fullpath))
-				__refresh_tcon(server->leaf_fullpath + 1, sessions, tcon, false);
-			__refresh_tcon(server->origin_fullpath + 1, sessions, tcon, false);
-		}
+		if (server->leaf_fullpath)
+			__refresh_tcon(server->leaf_fullpath + 1, sessions, tcon, false);
 		mutex_unlock(&server->refpath_lock);
 
 		cifs_put_tcon(tcon);
diff --git a/fs/cifs/fs_context.c b/fs/cifs/fs_context.c
index 40fbf46886ccf..6d13f8207e96a 100644
--- a/fs/cifs/fs_context.c
+++ b/fs/cifs/fs_context.c
@@ -316,6 +316,7 @@ smb3_fs_context_dup(struct smb3_fs_context *new_ctx, struct smb3_fs_context *ctx
 	new_ctx->UNC = NULL;
 	new_ctx->source = NULL;
 	new_ctx->iocharset = NULL;
+	new_ctx->leaf_fullpath = NULL;
 	/*
 	 * Make sure to stay in sync with smb3_cleanup_fs_context_contents()
 	 */
@@ -328,6 +329,7 @@ smb3_fs_context_dup(struct smb3_fs_context *new_ctx, struct smb3_fs_context *ctx
 	DUP_CTX_STR(domainname);
 	DUP_CTX_STR(nodename);
 	DUP_CTX_STR(iocharset);
+	DUP_CTX_STR(leaf_fullpath);
 
 	return 0;
 }
@@ -1592,6 +1594,8 @@ smb3_cleanup_fs_context_contents(struct smb3_fs_context *ctx)
 	ctx->iocharset = NULL;
 	kfree(ctx->prepath);
 	ctx->prepath = NULL;
+	kfree(ctx->leaf_fullpath);
+	ctx->leaf_fullpath = NULL;
 }
 
 void
diff --git a/fs/cifs/fs_context.h b/fs/cifs/fs_context.h
index 159bcfd509d40..44cb5639ed3ba 100644
--- a/fs/cifs/fs_context.h
+++ b/fs/cifs/fs_context.h
@@ -264,6 +264,7 @@ struct smb3_fs_context {
 	__u16 compression; /* compression algorithm 0xFFFF default 0=disabled */
 	bool rootfs:1; /* if it's a SMB root file system */
 	bool witness:1; /* use witness protocol */
+	char *leaf_fullpath;
 };
 
 extern const struct fs_parameter_spec smb3_fs_parameters[];
-- 
GitLab


From cb3f6d8764529c33269c3478c17641cb097a615b Mon Sep 17 00:00:00 2001
From: Paulo Alcantara <pc@cjr.nz>
Date: Tue, 13 Dec 2022 00:29:22 -0300
Subject: [PATCH 486/875] cifs: don't refresh cached referrals from unactive
 mounts

There is no point refreshing cached referrals from unactive mounts as
they will no longer be used and new mounts will either create or
refresh them anyway.

Signed-off-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/dfs_cache.c | 73 +--------------------------------------------
 1 file changed, 1 insertion(+), 72 deletions(-)

diff --git a/fs/cifs/dfs_cache.c b/fs/cifs/dfs_cache.c
index bf5e674f43b88..bef6725343972 100644
--- a/fs/cifs/dfs_cache.c
+++ b/fs/cifs/dfs_cache.c
@@ -1549,74 +1549,6 @@ static void refresh_mounts(struct cifs_ses **sessions)
 	}
 }
 
-static void refresh_cache(struct cifs_ses **sessions)
-{
-	int i;
-	struct cifs_ses *ses;
-	unsigned int xid;
-	char *ref_paths[CACHE_MAX_ENTRIES];
-	int count = 0;
-	struct cache_entry *ce;
-
-	/*
-	 * Refresh all cached entries.  Get all new referrals outside critical section to avoid
-	 * starvation while performing SMB2 IOCTL on broken or slow connections.
-
-	 * The cache entries may cover more paths than the active mounts
-	 * (e.g. domain-based DFS referrals or multi tier DFS setups).
-	 */
-	down_read(&htable_rw_lock);
-	for (i = 0; i < CACHE_HTABLE_SIZE; i++) {
-		struct hlist_head *l = &cache_htable[i];
-
-		hlist_for_each_entry(ce, l, hlist) {
-			if (count == ARRAY_SIZE(ref_paths))
-				goto out_unlock;
-			if (hlist_unhashed(&ce->hlist) || !cache_entry_expired(ce) ||
-			    IS_ERR(find_ipc_from_server_path(sessions, ce->path)))
-				continue;
-			ref_paths[count++] = kstrdup(ce->path, GFP_ATOMIC);
-		}
-	}
-
-out_unlock:
-	up_read(&htable_rw_lock);
-
-	for (i = 0; i < count; i++) {
-		char *path = ref_paths[i];
-		struct dfs_info3_param *refs = NULL;
-		int numrefs = 0;
-		int rc = 0;
-
-		if (!path)
-			continue;
-
-		ses = find_ipc_from_server_path(sessions, path);
-		if (IS_ERR(ses))
-			goto next_referral;
-
-		xid = get_xid();
-		rc = get_dfs_referral(xid, ses, path, &refs, &numrefs);
-		free_xid(xid);
-
-		if (!rc) {
-			down_write(&htable_rw_lock);
-			ce = lookup_cache_entry(path);
-			/*
-			 * We need to re-check it because other tasks might have it deleted or
-			 * updated.
-			 */
-			if (!IS_ERR(ce) && cache_entry_expired(ce))
-				update_cache_entry_locked(ce, refs, numrefs);
-			up_write(&htable_rw_lock);
-		}
-
-next_referral:
-		kfree(path);
-		free_dfs_info_array(refs, numrefs);
-	}
-}
-
 /*
  * Worker that will refresh DFS cache and active mounts based on lowest TTL value from a DFS
  * referral.
@@ -1654,11 +1586,8 @@ static void refresh_cache_worker(struct work_struct *work)
 		i += count;
 	}
 
-	if (sessions[0]) {
-		/* Refresh all active mounts and cached entries */
+	if (sessions[0])
 		refresh_mounts(sessions);
-		refresh_cache(sessions);
-	}
 
 	list_for_each_entry_safe(mg, tmp_mg, &mglist, refresh_list) {
 		list_del_init(&mg->refresh_list);
-- 
GitLab


From 6916881f443f67f6893b504fa2171468c8aed915 Mon Sep 17 00:00:00 2001
From: Paulo Alcantara <pc@cjr.nz>
Date: Tue, 13 Dec 2022 01:23:16 -0300
Subject: [PATCH 487/875] cifs: fix refresh of cached referrals

We can't rely on cifs_tcon::ses to refresh cached referral as the
server target might not respond to referrals, e.g. share is not hosted
in a DFS root server.  Consider the following

  mount //dom/dfs/link -> /root1/dfs/link -> /fs0/share

where fs0 can't get a referral for "/root1/dfs/link".

To simplify and fix the access of dfs root sessions, store the dfs
root session pointer directly to new sessions so making it easier to
select the appropriate ipc connection and use it for failover or cache
refresh.

Signed-off-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/cifsglob.h  |   3 +
 fs/cifs/connect.c   |   5 +-
 fs/cifs/dfs.c       |   6 ++
 fs/cifs/dfs_cache.c | 140 ++++++++------------------------------------
 4 files changed, 37 insertions(+), 117 deletions(-)

diff --git a/fs/cifs/cifsglob.h b/fs/cifs/cifsglob.h
index 2e2976f1874fa..cfdd5bf701a1c 100644
--- a/fs/cifs/cifsglob.h
+++ b/fs/cifs/cifsglob.h
@@ -107,6 +107,8 @@
 
 #define CIFS_MAX_WORKSTATION_LEN  (__NEW_UTS_LEN + 1)  /* reasonable max for client */
 
+#define CIFS_DFS_ROOT_SES(ses) ((ses)->dfs_root_ses ?: (ses))
+
 /*
  * CIFS vfs client Status information (based on what we know.)
  */
@@ -1099,6 +1101,7 @@ struct cifs_ses {
 	 */
 	unsigned long chans_need_reconnect;
 	/* ========= end: protected by chan_lock ======== */
+	struct cifs_ses *dfs_root_ses;
 };
 
 static inline bool
diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c
index a66cb23a954e2..db3a2b3ac497f 100644
--- a/fs/cifs/connect.c
+++ b/fs/cifs/connect.c
@@ -4150,7 +4150,8 @@ static int __tree_connect_dfs_target(const unsigned int xid, struct cifs_tcon *t
 	int rc;
 	struct TCP_Server_Info *server = tcon->ses->server;
 	const struct smb_version_operations *ops = server->ops;
-	struct cifs_tcon *ipc = tcon->ses->tcon_ipc;
+	struct cifs_ses *root_ses = CIFS_DFS_ROOT_SES(tcon->ses);
+	struct cifs_tcon *ipc = root_ses->tcon_ipc;
 	char *share = NULL, *prefix = NULL;
 	const char *tcp_host;
 	size_t tcp_host_len;
@@ -4208,7 +4209,7 @@ static int __tree_connect_dfs_target(const unsigned int xid, struct cifs_tcon *t
 		 * reconnect so either the demultiplex thread or the echo worker will reconnect to
 		 * newly resolved target.
 		 */
-		if (dfs_cache_find(xid, tcon->ses, cifs_sb->local_nls, cifs_remap(cifs_sb), target,
+		if (dfs_cache_find(xid, root_ses, cifs_sb->local_nls, cifs_remap(cifs_sb), target,
 				   NULL, &ntl)) {
 			rc = ops->tree_connect(xid, tcon->ses, tree, tcon, cifs_sb->local_nls);
 			if (rc)
diff --git a/fs/cifs/dfs.c b/fs/cifs/dfs.c
index 88a0cab335b4b..fbc8e880a1fe3 100644
--- a/fs/cifs/dfs.c
+++ b/fs/cifs/dfs.c
@@ -95,7 +95,13 @@ static int get_session(struct cifs_mount_ctx *mnt_ctx, const char *full_path)
 	ctx->leaf_fullpath = (char *)full_path;
 	rc = cifs_mount_get_session(mnt_ctx);
 	ctx->leaf_fullpath = NULL;
+	if (!rc) {
+		struct cifs_ses *ses = mnt_ctx->ses;
 
+		mutex_lock(&ses->session_mutex);
+		ses->dfs_root_ses = mnt_ctx->root_ses;
+		mutex_unlock(&ses->session_mutex);
+	}
 	return rc;
 }
 
diff --git a/fs/cifs/dfs_cache.c b/fs/cifs/dfs_cache.c
index bef6725343972..95cc3951420ed 100644
--- a/fs/cifs/dfs_cache.c
+++ b/fs/cifs/dfs_cache.c
@@ -83,27 +83,6 @@ static void refresh_cache_worker(struct work_struct *work);
 
 static DECLARE_DELAYED_WORK(refresh_task, refresh_cache_worker);
 
-static void get_ipc_unc(const char *ref_path, char *ipc, size_t ipclen)
-{
-	const char *host;
-	size_t len;
-
-	extract_unc_hostname(ref_path, &host, &len);
-	scnprintf(ipc, ipclen, "\\\\%.*s\\IPC$", (int)len, host);
-}
-
-static struct cifs_ses *find_ipc_from_server_path(struct cifs_ses **ses, const char *path)
-{
-	char unc[SERVER_NAME_LENGTH + sizeof("//x/IPC$")] = {0};
-
-	get_ipc_unc(path, unc, sizeof(unc));
-	for (; *ses; ses++) {
-		if (!strcasecmp(unc, (*ses)->tcon_ipc->tree_name))
-			return *ses;
-	}
-	return ERR_PTR(-ENOENT);
-}
-
 static void __mount_group_release(struct mount_group *mg)
 {
 	int i;
@@ -760,8 +739,6 @@ static int get_dfs_referral(const unsigned int xid, struct cifs_ses *ses, const
 	int rc;
 	int i;
 
-	cifs_dbg(FYI, "%s: get an DFS referral for %s\n", __func__, path);
-
 	*refs = NULL;
 	*numrefs = 0;
 
@@ -770,6 +747,7 @@ static int get_dfs_referral(const unsigned int xid, struct cifs_ses *ses, const
 	if (unlikely(!cache_cp))
 		return -EINVAL;
 
+	cifs_dbg(FYI, "%s: ipc=%s referral=%s\n", __func__, ses->tcon_ipc->tree_name, path);
 	rc =  ses->server->ops->get_dfs_refer(xid, ses, path, refs, numrefs, cache_cp,
 					      NO_MAP_UNI_RSVD);
 	if (!rc) {
@@ -1366,10 +1344,9 @@ static void mark_for_reconnect_if_needed(struct cifs_tcon *tcon, struct dfs_cach
 }
 
 /* Refresh dfs referral of tcon and mark it for reconnect if needed */
-static int __refresh_tcon(const char *path, struct cifs_ses **sessions, struct cifs_tcon *tcon,
-			  bool force_refresh)
+static int __refresh_tcon(const char *path, struct cifs_tcon *tcon, bool force_refresh)
 {
-	struct cifs_ses *ses;
+	struct cifs_ses *ses = CIFS_DFS_ROOT_SES(tcon->ses);
 	struct cache_entry *ce;
 	struct dfs_info3_param *refs = NULL;
 	int numrefs = 0;
@@ -1378,11 +1355,7 @@ static int __refresh_tcon(const char *path, struct cifs_ses **sessions, struct c
 	int rc = 0;
 	unsigned int xid;
 
-	ses = find_ipc_from_server_path(sessions, path);
-	if (IS_ERR(ses)) {
-		cifs_dbg(FYI, "%s: could not find ipc session\n", __func__);
-		return PTR_ERR(ses);
-	}
+	xid = get_xid();
 
 	down_read(&htable_rw_lock);
 	ce = lookup_cache_entry(path);
@@ -1399,12 +1372,9 @@ static int __refresh_tcon(const char *path, struct cifs_ses **sessions, struct c
 		goto out;
 	}
 
-	xid = get_xid();
 	rc = get_dfs_referral(xid, ses, path, &refs, &numrefs);
-	free_xid(xid);
-
-	/* Create or update a cache entry with the new referral */
 	if (!rc) {
+		/* Create or update a cache entry with the new referral */
 		dump_refs(refs, numrefs);
 
 		down_write(&htable_rw_lock);
@@ -1419,24 +1389,20 @@ static int __refresh_tcon(const char *path, struct cifs_ses **sessions, struct c
 	}
 
 out:
+	free_xid(xid);
 	dfs_cache_free_tgts(&tl);
 	free_dfs_info_array(refs, numrefs);
 	return rc;
 }
 
-static int refresh_tcon(struct cifs_ses **sessions, struct cifs_tcon *tcon, bool force_refresh)
+static int refresh_tcon(struct cifs_tcon *tcon, bool force_refresh)
 {
 	struct TCP_Server_Info *server = tcon->ses->server;
 
 	mutex_lock(&server->refpath_lock);
-	if (server->origin_fullpath) {
-		if (server->leaf_fullpath && strcasecmp(server->leaf_fullpath,
-							server->origin_fullpath))
-			__refresh_tcon(server->leaf_fullpath + 1, sessions, tcon, force_refresh);
-		__refresh_tcon(server->origin_fullpath + 1, sessions, tcon, force_refresh);
-	}
+	if (server->leaf_fullpath)
+		__refresh_tcon(server->leaf_fullpath + 1, tcon, force_refresh);
 	mutex_unlock(&server->refpath_lock);
-
 	return 0;
 }
 
@@ -1454,9 +1420,6 @@ int dfs_cache_remount_fs(struct cifs_sb_info *cifs_sb)
 {
 	struct cifs_tcon *tcon;
 	struct TCP_Server_Info *server;
-	struct mount_group *mg;
-	struct cifs_ses *sessions[CACHE_MAX_ENTRIES + 1] = {NULL};
-	int rc;
 
 	if (!cifs_sb || !cifs_sb->master_tlink)
 		return -EINVAL;
@@ -1473,21 +1436,6 @@ int dfs_cache_remount_fs(struct cifs_sb_info *cifs_sb)
 		cifs_dbg(FYI, "%s: no dfs mount group id\n", __func__);
 		return -EINVAL;
 	}
-
-	mutex_lock(&mount_group_list_lock);
-	mg = find_mount_group_locked(&cifs_sb->dfs_mount_id);
-	if (IS_ERR(mg)) {
-		mutex_unlock(&mount_group_list_lock);
-		cifs_dbg(FYI, "%s: no ipc session for refreshing referral\n", __func__);
-		return PTR_ERR(mg);
-	}
-	kref_get(&mg->refcount);
-	mutex_unlock(&mount_group_list_lock);
-
-	spin_lock(&mg->lock);
-	memcpy(&sessions, mg->sessions, mg->num_sessions * sizeof(mg->sessions[0]));
-	spin_unlock(&mg->lock);
-
 	/*
 	 * After reconnecting to a different server, unique ids won't match anymore, so we disable
 	 * serverino. This prevents dentry revalidation to think the dentry are stale (ESTALE).
@@ -1498,17 +1446,15 @@ int dfs_cache_remount_fs(struct cifs_sb_info *cifs_sb)
 	 * that have different prefix paths.
 	 */
 	cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_USE_PREFIX_PATH;
-	rc = refresh_tcon(sessions, tcon, true);
 
-	kref_put(&mg->refcount, mount_group_release);
-	return rc;
+	return refresh_tcon(tcon, true);
 }
 
 /*
- * Refresh all active dfs mounts regardless of whether they are in cache or not.
- * (cache can be cleared)
+ * Worker that will refresh DFS cache from all active mounts based on lowest TTL value
+ * from a DFS referral.
  */
-static void refresh_mounts(struct cifs_ses **sessions)
+static void refresh_cache_worker(struct work_struct *work)
 {
 	struct TCP_Server_Info *server;
 	struct cifs_ses *ses;
@@ -1523,9 +1469,19 @@ static void refresh_mounts(struct cifs_ses **sessions)
 			continue;
 
 		list_for_each_entry(ses, &server->smb_ses_list, smb_ses_list) {
+			struct cifs_ses *root_ses = CIFS_DFS_ROOT_SES(ses);
+
+			spin_lock(&root_ses->ses_lock);
+			if (root_ses->ses_status != SES_GOOD) {
+				spin_unlock(&root_ses->ses_lock);
+				continue;
+			}
+			spin_unlock(&root_ses->ses_lock);
+
 			list_for_each_entry(tcon, &ses->tcon_list, tcon_list) {
 				spin_lock(&tcon->tc_lock);
-				if (!tcon->ipc && !tcon->need_reconnect) {
+				if (!tcon->ipc && tcon->status != TID_NEW &&
+				    tcon->status != TID_NEED_TCON) {
 					tcon->tc_count++;
 					list_add_tail(&tcon->ulist, &tcons);
 				}
@@ -1542,57 +1498,11 @@ static void refresh_mounts(struct cifs_ses **sessions)
 
 		mutex_lock(&server->refpath_lock);
 		if (server->leaf_fullpath)
-			__refresh_tcon(server->leaf_fullpath + 1, sessions, tcon, false);
+			__refresh_tcon(server->leaf_fullpath + 1, tcon, false);
 		mutex_unlock(&server->refpath_lock);
 
 		cifs_put_tcon(tcon);
 	}
-}
-
-/*
- * Worker that will refresh DFS cache and active mounts based on lowest TTL value from a DFS
- * referral.
- */
-static void refresh_cache_worker(struct work_struct *work)
-{
-	struct list_head mglist;
-	struct mount_group *mg, *tmp_mg;
-	struct cifs_ses *sessions[CACHE_MAX_ENTRIES + 1] = {NULL};
-	int max_sessions = ARRAY_SIZE(sessions) - 1;
-	int i = 0, count;
-
-	INIT_LIST_HEAD(&mglist);
-
-	/* Get refereces of mount groups */
-	mutex_lock(&mount_group_list_lock);
-	list_for_each_entry(mg, &mount_group_list, list) {
-		kref_get(&mg->refcount);
-		list_add(&mg->refresh_list, &mglist);
-	}
-	mutex_unlock(&mount_group_list_lock);
-
-	/* Fill in local array with an NULL-terminated list of all referral server sessions */
-	list_for_each_entry(mg, &mglist, refresh_list) {
-		if (i >= max_sessions)
-			break;
-
-		spin_lock(&mg->lock);
-		if (i + mg->num_sessions > max_sessions)
-			count = max_sessions - i;
-		else
-			count = mg->num_sessions;
-		memcpy(&sessions[i], mg->sessions, count * sizeof(mg->sessions[0]));
-		spin_unlock(&mg->lock);
-		i += count;
-	}
-
-	if (sessions[0])
-		refresh_mounts(sessions);
-
-	list_for_each_entry_safe(mg, tmp_mg, &mglist, refresh_list) {
-		list_del_init(&mg->refresh_list);
-		kref_put(&mg->refcount, mount_group_release);
-	}
 
 	spin_lock(&cache_ttl_lock);
 	queue_delayed_work(dfscache_wq, &refresh_task, cache_ttl * HZ);
-- 
GitLab


From 8332858569a096cff02e157555d839e0be921ec7 Mon Sep 17 00:00:00 2001
From: Paulo Alcantara <pc@cjr.nz>
Date: Tue, 13 Dec 2022 11:30:30 -0300
Subject: [PATCH 488/875] cifs: refresh root referrals

Also refresh cached root referrals so the other cached referrals may
have a better chance to have a working root server to issue the
referrals on.

Signed-off-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/dfs_cache.c | 40 ++++++++++++++++++++++------------------
 1 file changed, 22 insertions(+), 18 deletions(-)

diff --git a/fs/cifs/dfs_cache.c b/fs/cifs/dfs_cache.c
index 95cc3951420ed..cb83b86eafe64 100644
--- a/fs/cifs/dfs_cache.c
+++ b/fs/cifs/dfs_cache.c
@@ -1346,14 +1346,15 @@ static void mark_for_reconnect_if_needed(struct cifs_tcon *tcon, struct dfs_cach
 /* Refresh dfs referral of tcon and mark it for reconnect if needed */
 static int __refresh_tcon(const char *path, struct cifs_tcon *tcon, bool force_refresh)
 {
+	struct dfs_cache_tgt_list tl = DFS_CACHE_TGT_LIST_INIT(tl);
 	struct cifs_ses *ses = CIFS_DFS_ROOT_SES(tcon->ses);
-	struct cache_entry *ce;
+	struct cifs_tcon *ipc = ses->tcon_ipc;
 	struct dfs_info3_param *refs = NULL;
-	int numrefs = 0;
 	bool needs_refresh = false;
-	struct dfs_cache_tgt_list tl = DFS_CACHE_TGT_LIST_INIT(tl);
-	int rc = 0;
+	struct cache_entry *ce;
 	unsigned int xid;
+	int numrefs = 0;
+	int rc = 0;
 
 	xid = get_xid();
 
@@ -1372,6 +1373,14 @@ static int __refresh_tcon(const char *path, struct cifs_tcon *tcon, bool force_r
 		goto out;
 	}
 
+	spin_lock(&ipc->tc_lock);
+	if (ses->ses_status != SES_GOOD || ipc->status != TID_GOOD) {
+		spin_unlock(&ipc->tc_lock);
+		cifs_dbg(FYI, "%s: skip cache refresh due to disconnected ipc\n", __func__);
+		goto out;
+	}
+	spin_unlock(&ipc->tc_lock);
+
 	rc = get_dfs_referral(xid, ses, path, &refs, &numrefs);
 	if (!rc) {
 		/* Create or update a cache entry with the new referral */
@@ -1457,9 +1466,9 @@ int dfs_cache_remount_fs(struct cifs_sb_info *cifs_sb)
 static void refresh_cache_worker(struct work_struct *work)
 {
 	struct TCP_Server_Info *server;
-	struct cifs_ses *ses;
 	struct cifs_tcon *tcon, *ntcon;
 	struct list_head tcons;
+	struct cifs_ses *ses;
 
 	INIT_LIST_HEAD(&tcons);
 
@@ -1469,23 +1478,15 @@ static void refresh_cache_worker(struct work_struct *work)
 			continue;
 
 		list_for_each_entry(ses, &server->smb_ses_list, smb_ses_list) {
-			struct cifs_ses *root_ses = CIFS_DFS_ROOT_SES(ses);
-
-			spin_lock(&root_ses->ses_lock);
-			if (root_ses->ses_status != SES_GOOD) {
-				spin_unlock(&root_ses->ses_lock);
-				continue;
+			if (ses->tcon_ipc) {
+				ses->ses_count++;
+				list_add_tail(&ses->tcon_ipc->ulist, &tcons);
 			}
-			spin_unlock(&root_ses->ses_lock);
-
 			list_for_each_entry(tcon, &ses->tcon_list, tcon_list) {
-				spin_lock(&tcon->tc_lock);
-				if (!tcon->ipc && tcon->status != TID_NEW &&
-				    tcon->status != TID_NEED_TCON) {
+				if (!tcon->ipc) {
 					tcon->tc_count++;
 					list_add_tail(&tcon->ulist, &tcons);
 				}
-				spin_unlock(&tcon->tc_lock);
 			}
 		}
 	}
@@ -1501,7 +1502,10 @@ static void refresh_cache_worker(struct work_struct *work)
 			__refresh_tcon(server->leaf_fullpath + 1, tcon, false);
 		mutex_unlock(&server->refpath_lock);
 
-		cifs_put_tcon(tcon);
+		if (tcon->ipc)
+			cifs_put_smb_ses(tcon->ses);
+		else
+			cifs_put_tcon(tcon);
 	}
 
 	spin_lock(&cache_ttl_lock);
-- 
GitLab


From 1d04a6fe75eef16dd1816b112edb4406fd1fbffd Mon Sep 17 00:00:00 2001
From: Paulo Alcantara <pc@cjr.nz>
Date: Fri, 16 Dec 2022 21:41:31 -0300
Subject: [PATCH 489/875] cifs: don't block in dfs_cache_noreq_update_tgthint()

Avoid blocking in dfs_cache_noreq_update_tgthint() while reconnecting
servers or tcons as the cache refresh worker or new mounts might
already be updating their targets.

Move some more dfs related code out of connect.c while at it.

Signed-off-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/connect.c   | 264 +-------------------------------------------
 fs/cifs/dfs.c       | 259 +++++++++++++++++++++++++++++++++++++++++++
 fs/cifs/dfs_cache.c |  18 ++-
 fs/cifs/dfs_cache.h |   2 +-
 4 files changed, 269 insertions(+), 274 deletions(-)

diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c
index db3a2b3ac497f..41009ef7878f9 100644
--- a/fs/cifs/connect.c
+++ b/fs/cifs/connect.c
@@ -529,9 +529,7 @@ static int reconnect_dfs_server(struct TCP_Server_Info *server)
 		mod_delayed_work(cifsiod_wq, &server->reconnect, 0);
 	} while (server->tcpStatus == CifsNeedReconnect);
 
-	if (target_hint)
-		dfs_cache_noreq_update_tgthint(refpath, target_hint);
-
+	dfs_cache_noreq_update_tgthint(refpath, target_hint);
 	dfs_cache_free_tgts(&tl);
 
 	/* Need to set up echo worker again once connection has been established */
@@ -4079,265 +4077,7 @@ cifs_prune_tlinks(struct work_struct *work)
 				TLINK_IDLE_EXPIRE);
 }
 
-#ifdef CONFIG_CIFS_DFS_UPCALL
-/* Update dfs referral path of superblock */
-static int update_server_fullpath(struct TCP_Server_Info *server, struct cifs_sb_info *cifs_sb,
-				  const char *target)
-{
-	int rc = 0;
-	size_t len = strlen(target);
-	char *refpath, *npath;
-
-	if (unlikely(len < 2 || *target != '\\'))
-		return -EINVAL;
-
-	if (target[1] == '\\') {
-		len += 1;
-		refpath = kmalloc(len, GFP_KERNEL);
-		if (!refpath)
-			return -ENOMEM;
-
-		scnprintf(refpath, len, "%s", target);
-	} else {
-		len += sizeof("\\");
-		refpath = kmalloc(len, GFP_KERNEL);
-		if (!refpath)
-			return -ENOMEM;
-
-		scnprintf(refpath, len, "\\%s", target);
-	}
-
-	npath = dfs_cache_canonical_path(refpath, cifs_sb->local_nls, cifs_remap(cifs_sb));
-	kfree(refpath);
-
-	if (IS_ERR(npath)) {
-		rc = PTR_ERR(npath);
-	} else {
-		mutex_lock(&server->refpath_lock);
-		kfree(server->leaf_fullpath);
-		server->leaf_fullpath = npath;
-		mutex_unlock(&server->refpath_lock);
-		server->current_fullpath = server->leaf_fullpath;
-	}
-	return rc;
-}
-
-static int target_share_matches_server(struct TCP_Server_Info *server, const char *tcp_host,
-				       size_t tcp_host_len, char *share, bool *target_match)
-{
-	int rc = 0;
-	const char *dfs_host;
-	size_t dfs_host_len;
-
-	*target_match = true;
-	extract_unc_hostname(share, &dfs_host, &dfs_host_len);
-
-	/* Check if hostnames or addresses match */
-	if (dfs_host_len != tcp_host_len || strncasecmp(dfs_host, tcp_host, dfs_host_len) != 0) {
-		cifs_dbg(FYI, "%s: %.*s doesn't match %.*s\n", __func__, (int)dfs_host_len,
-			 dfs_host, (int)tcp_host_len, tcp_host);
-		rc = match_target_ip(server, dfs_host, dfs_host_len, target_match);
-		if (rc)
-			cifs_dbg(VFS, "%s: failed to match target ip: %d\n", __func__, rc);
-	}
-	return rc;
-}
-
-static int __tree_connect_dfs_target(const unsigned int xid, struct cifs_tcon *tcon,
-				     struct cifs_sb_info *cifs_sb, char *tree, bool islink,
-				     struct dfs_cache_tgt_list *tl)
-{
-	int rc;
-	struct TCP_Server_Info *server = tcon->ses->server;
-	const struct smb_version_operations *ops = server->ops;
-	struct cifs_ses *root_ses = CIFS_DFS_ROOT_SES(tcon->ses);
-	struct cifs_tcon *ipc = root_ses->tcon_ipc;
-	char *share = NULL, *prefix = NULL;
-	const char *tcp_host;
-	size_t tcp_host_len;
-	struct dfs_cache_tgt_iterator *tit;
-	bool target_match;
-
-	extract_unc_hostname(server->hostname, &tcp_host, &tcp_host_len);
-
-	tit = dfs_cache_get_tgt_iterator(tl);
-	if (!tit) {
-		rc = -ENOENT;
-		goto out;
-	}
-
-	/* Try to tree connect to all dfs targets */
-	for (; tit; tit = dfs_cache_get_next_tgt(tl, tit)) {
-		const char *target = dfs_cache_get_tgt_name(tit);
-		struct dfs_cache_tgt_list ntl = DFS_CACHE_TGT_LIST_INIT(ntl);
-
-		kfree(share);
-		kfree(prefix);
-		share = prefix = NULL;
-
-		/* Check if share matches with tcp ses */
-		rc = dfs_cache_get_tgt_share(server->current_fullpath + 1, tit, &share, &prefix);
-		if (rc) {
-			cifs_dbg(VFS, "%s: failed to parse target share: %d\n", __func__, rc);
-			break;
-		}
-
-		rc = target_share_matches_server(server, tcp_host, tcp_host_len, share,
-						 &target_match);
-		if (rc)
-			break;
-		if (!target_match) {
-			rc = -EHOSTUNREACH;
-			continue;
-		}
-
-		if (ipc->need_reconnect) {
-			scnprintf(tree, MAX_TREE_SIZE, "\\\\%s\\IPC$", server->hostname);
-			rc = ops->tree_connect(xid, ipc->ses, tree, ipc, cifs_sb->local_nls);
-			if (rc)
-				break;
-		}
-
-		scnprintf(tree, MAX_TREE_SIZE, "\\%s", share);
-		if (!islink) {
-			rc = ops->tree_connect(xid, tcon->ses, tree, tcon, cifs_sb->local_nls);
-			break;
-		}
-		/*
-		 * If no dfs referrals were returned from link target, then just do a TREE_CONNECT
-		 * to it.  Otherwise, cache the dfs referral and then mark current tcp ses for
-		 * reconnect so either the demultiplex thread or the echo worker will reconnect to
-		 * newly resolved target.
-		 */
-		if (dfs_cache_find(xid, root_ses, cifs_sb->local_nls, cifs_remap(cifs_sb), target,
-				   NULL, &ntl)) {
-			rc = ops->tree_connect(xid, tcon->ses, tree, tcon, cifs_sb->local_nls);
-			if (rc)
-				continue;
-			rc = dfs_cache_noreq_update_tgthint(server->current_fullpath + 1, tit);
-			if (!rc)
-				rc = cifs_update_super_prepath(cifs_sb, prefix);
-		} else {
-			/* Target is another dfs share */
-			rc = update_server_fullpath(server, cifs_sb, target);
-			dfs_cache_free_tgts(tl);
-
-			if (!rc) {
-				rc = -EREMOTE;
-				list_replace_init(&ntl.tl_list, &tl->tl_list);
-			} else
-				dfs_cache_free_tgts(&ntl);
-		}
-		break;
-	}
-
-out:
-	kfree(share);
-	kfree(prefix);
-
-	return rc;
-}
-
-static int tree_connect_dfs_target(const unsigned int xid, struct cifs_tcon *tcon,
-				   struct cifs_sb_info *cifs_sb, char *tree, bool islink,
-				   struct dfs_cache_tgt_list *tl)
-{
-	int rc;
-	int num_links = 0;
-	struct TCP_Server_Info *server = tcon->ses->server;
-
-	do {
-		rc = __tree_connect_dfs_target(xid, tcon, cifs_sb, tree, islink, tl);
-		if (!rc || rc != -EREMOTE)
-			break;
-	} while (rc = -ELOOP, ++num_links < MAX_NESTED_LINKS);
-	/*
-	 * If we couldn't tree connect to any targets from last referral path, then retry from
-	 * original referral path.
-	 */
-	if (rc && server->current_fullpath != server->origin_fullpath) {
-		server->current_fullpath = server->origin_fullpath;
-		cifs_signal_cifsd_for_reconnect(server, true);
-	}
-
-	dfs_cache_free_tgts(tl);
-	return rc;
-}
-
-int cifs_tree_connect(const unsigned int xid, struct cifs_tcon *tcon, const struct nls_table *nlsc)
-{
-	int rc;
-	struct TCP_Server_Info *server = tcon->ses->server;
-	const struct smb_version_operations *ops = server->ops;
-	struct super_block *sb = NULL;
-	struct cifs_sb_info *cifs_sb;
-	struct dfs_cache_tgt_list tl = DFS_CACHE_TGT_LIST_INIT(tl);
-	char *tree;
-	struct dfs_info3_param ref = {0};
-
-	/* only send once per connect */
-	spin_lock(&tcon->tc_lock);
-	if (tcon->ses->ses_status != SES_GOOD ||
-	    (tcon->status != TID_NEW &&
-	    tcon->status != TID_NEED_TCON)) {
-		spin_unlock(&tcon->tc_lock);
-		return 0;
-	}
-	tcon->status = TID_IN_TCON;
-	spin_unlock(&tcon->tc_lock);
-
-	tree = kzalloc(MAX_TREE_SIZE, GFP_KERNEL);
-	if (!tree) {
-		rc = -ENOMEM;
-		goto out;
-	}
-
-	if (tcon->ipc) {
-		scnprintf(tree, MAX_TREE_SIZE, "\\\\%s\\IPC$", server->hostname);
-		rc = ops->tree_connect(xid, tcon->ses, tree, tcon, nlsc);
-		goto out;
-	}
-
-	sb = cifs_get_tcp_super(server);
-	if (IS_ERR(sb)) {
-		rc = PTR_ERR(sb);
-		cifs_dbg(VFS, "%s: could not find superblock: %d\n", __func__, rc);
-		goto out;
-	}
-
-	cifs_sb = CIFS_SB(sb);
-
-	/* If it is not dfs or there was no cached dfs referral, then reconnect to same share */
-	if (!server->current_fullpath ||
-	    dfs_cache_noreq_find(server->current_fullpath + 1, &ref, &tl)) {
-		rc = ops->tree_connect(xid, tcon->ses, tcon->tree_name, tcon, cifs_sb->local_nls);
-		goto out;
-	}
-
-	rc = tree_connect_dfs_target(xid, tcon, cifs_sb, tree, ref.server_type == DFS_TYPE_LINK,
-				     &tl);
-	free_dfs_info_param(&ref);
-
-out:
-	kfree(tree);
-	cifs_put_tcp_super(sb);
-
-	if (rc) {
-		spin_lock(&tcon->tc_lock);
-		if (tcon->status == TID_IN_TCON)
-			tcon->status = TID_NEED_TCON;
-		spin_unlock(&tcon->tc_lock);
-	} else {
-		spin_lock(&tcon->tc_lock);
-		if (tcon->status == TID_IN_TCON)
-			tcon->status = TID_GOOD;
-		spin_unlock(&tcon->tc_lock);
-		tcon->need_reconnect = false;
-	}
-
-	return rc;
-}
-#else
+#ifndef CONFIG_CIFS_DFS_UPCALL
 int cifs_tree_connect(const unsigned int xid, struct cifs_tcon *tcon, const struct nls_table *nlsc)
 {
 	int rc;
diff --git a/fs/cifs/dfs.c b/fs/cifs/dfs.c
index fbc8e880a1fe3..5afabca654c11 100644
--- a/fs/cifs/dfs.c
+++ b/fs/cifs/dfs.c
@@ -284,3 +284,262 @@ int dfs_mount_share(struct cifs_mount_ctx *mnt_ctx, bool *isdfs)
 
 	return __dfs_mount_share(mnt_ctx);
 }
+
+/* Update dfs referral path of superblock */
+static int update_server_fullpath(struct TCP_Server_Info *server, struct cifs_sb_info *cifs_sb,
+				  const char *target)
+{
+	int rc = 0;
+	size_t len = strlen(target);
+	char *refpath, *npath;
+
+	if (unlikely(len < 2 || *target != '\\'))
+		return -EINVAL;
+
+	if (target[1] == '\\') {
+		len += 1;
+		refpath = kmalloc(len, GFP_KERNEL);
+		if (!refpath)
+			return -ENOMEM;
+
+		scnprintf(refpath, len, "%s", target);
+	} else {
+		len += sizeof("\\");
+		refpath = kmalloc(len, GFP_KERNEL);
+		if (!refpath)
+			return -ENOMEM;
+
+		scnprintf(refpath, len, "\\%s", target);
+	}
+
+	npath = dfs_cache_canonical_path(refpath, cifs_sb->local_nls, cifs_remap(cifs_sb));
+	kfree(refpath);
+
+	if (IS_ERR(npath)) {
+		rc = PTR_ERR(npath);
+	} else {
+		mutex_lock(&server->refpath_lock);
+		kfree(server->leaf_fullpath);
+		server->leaf_fullpath = npath;
+		mutex_unlock(&server->refpath_lock);
+		server->current_fullpath = server->leaf_fullpath;
+	}
+	return rc;
+}
+
+static int target_share_matches_server(struct TCP_Server_Info *server, const char *tcp_host,
+				       size_t tcp_host_len, char *share, bool *target_match)
+{
+	int rc = 0;
+	const char *dfs_host;
+	size_t dfs_host_len;
+
+	*target_match = true;
+	extract_unc_hostname(share, &dfs_host, &dfs_host_len);
+
+	/* Check if hostnames or addresses match */
+	if (dfs_host_len != tcp_host_len || strncasecmp(dfs_host, tcp_host, dfs_host_len) != 0) {
+		cifs_dbg(FYI, "%s: %.*s doesn't match %.*s\n", __func__, (int)dfs_host_len,
+			 dfs_host, (int)tcp_host_len, tcp_host);
+		rc = match_target_ip(server, dfs_host, dfs_host_len, target_match);
+		if (rc)
+			cifs_dbg(VFS, "%s: failed to match target ip: %d\n", __func__, rc);
+	}
+	return rc;
+}
+
+static int __tree_connect_dfs_target(const unsigned int xid, struct cifs_tcon *tcon,
+				     struct cifs_sb_info *cifs_sb, char *tree, bool islink,
+				     struct dfs_cache_tgt_list *tl)
+{
+	int rc;
+	struct TCP_Server_Info *server = tcon->ses->server;
+	const struct smb_version_operations *ops = server->ops;
+	struct cifs_ses *root_ses = CIFS_DFS_ROOT_SES(tcon->ses);
+	struct cifs_tcon *ipc = root_ses->tcon_ipc;
+	char *share = NULL, *prefix = NULL;
+	const char *tcp_host;
+	size_t tcp_host_len;
+	struct dfs_cache_tgt_iterator *tit;
+	bool target_match;
+
+	extract_unc_hostname(server->hostname, &tcp_host, &tcp_host_len);
+
+	tit = dfs_cache_get_tgt_iterator(tl);
+	if (!tit) {
+		rc = -ENOENT;
+		goto out;
+	}
+
+	/* Try to tree connect to all dfs targets */
+	for (; tit; tit = dfs_cache_get_next_tgt(tl, tit)) {
+		const char *target = dfs_cache_get_tgt_name(tit);
+		struct dfs_cache_tgt_list ntl = DFS_CACHE_TGT_LIST_INIT(ntl);
+
+		kfree(share);
+		kfree(prefix);
+		share = prefix = NULL;
+
+		/* Check if share matches with tcp ses */
+		rc = dfs_cache_get_tgt_share(server->current_fullpath + 1, tit, &share, &prefix);
+		if (rc) {
+			cifs_dbg(VFS, "%s: failed to parse target share: %d\n", __func__, rc);
+			break;
+		}
+
+		rc = target_share_matches_server(server, tcp_host, tcp_host_len, share,
+						 &target_match);
+		if (rc)
+			break;
+		if (!target_match) {
+			rc = -EHOSTUNREACH;
+			continue;
+		}
+
+		dfs_cache_noreq_update_tgthint(server->current_fullpath + 1, tit);
+
+		if (ipc->need_reconnect) {
+			scnprintf(tree, MAX_TREE_SIZE, "\\\\%s\\IPC$", server->hostname);
+			rc = ops->tree_connect(xid, ipc->ses, tree, ipc, cifs_sb->local_nls);
+			if (rc)
+				break;
+		}
+
+		scnprintf(tree, MAX_TREE_SIZE, "\\%s", share);
+		if (!islink) {
+			rc = ops->tree_connect(xid, tcon->ses, tree, tcon, cifs_sb->local_nls);
+			break;
+		}
+		/*
+		 * If no dfs referrals were returned from link target, then just do a TREE_CONNECT
+		 * to it.  Otherwise, cache the dfs referral and then mark current tcp ses for
+		 * reconnect so either the demultiplex thread or the echo worker will reconnect to
+		 * newly resolved target.
+		 */
+		if (dfs_cache_find(xid, root_ses, cifs_sb->local_nls, cifs_remap(cifs_sb), target,
+				   NULL, &ntl)) {
+			rc = ops->tree_connect(xid, tcon->ses, tree, tcon, cifs_sb->local_nls);
+			if (rc)
+				continue;
+
+			rc = cifs_update_super_prepath(cifs_sb, prefix);
+		} else {
+			/* Target is another dfs share */
+			rc = update_server_fullpath(server, cifs_sb, target);
+			dfs_cache_free_tgts(tl);
+
+			if (!rc) {
+				rc = -EREMOTE;
+				list_replace_init(&ntl.tl_list, &tl->tl_list);
+			} else
+				dfs_cache_free_tgts(&ntl);
+		}
+		break;
+	}
+
+out:
+	kfree(share);
+	kfree(prefix);
+
+	return rc;
+}
+
+static int tree_connect_dfs_target(const unsigned int xid, struct cifs_tcon *tcon,
+				   struct cifs_sb_info *cifs_sb, char *tree, bool islink,
+				   struct dfs_cache_tgt_list *tl)
+{
+	int rc;
+	int num_links = 0;
+	struct TCP_Server_Info *server = tcon->ses->server;
+
+	do {
+		rc = __tree_connect_dfs_target(xid, tcon, cifs_sb, tree, islink, tl);
+		if (!rc || rc != -EREMOTE)
+			break;
+	} while (rc = -ELOOP, ++num_links < MAX_NESTED_LINKS);
+	/*
+	 * If we couldn't tree connect to any targets from last referral path, then retry from
+	 * original referral path.
+	 */
+	if (rc && server->current_fullpath != server->origin_fullpath) {
+		server->current_fullpath = server->origin_fullpath;
+		cifs_signal_cifsd_for_reconnect(server, true);
+	}
+
+	dfs_cache_free_tgts(tl);
+	return rc;
+}
+
+int cifs_tree_connect(const unsigned int xid, struct cifs_tcon *tcon, const struct nls_table *nlsc)
+{
+	int rc;
+	struct TCP_Server_Info *server = tcon->ses->server;
+	const struct smb_version_operations *ops = server->ops;
+	struct super_block *sb = NULL;
+	struct cifs_sb_info *cifs_sb;
+	struct dfs_cache_tgt_list tl = DFS_CACHE_TGT_LIST_INIT(tl);
+	char *tree;
+	struct dfs_info3_param ref = {0};
+
+	/* only send once per connect */
+	spin_lock(&tcon->tc_lock);
+	if (tcon->ses->ses_status != SES_GOOD ||
+	    (tcon->status != TID_NEW &&
+	    tcon->status != TID_NEED_TCON)) {
+		spin_unlock(&tcon->tc_lock);
+		return 0;
+	}
+	tcon->status = TID_IN_TCON;
+	spin_unlock(&tcon->tc_lock);
+
+	tree = kzalloc(MAX_TREE_SIZE, GFP_KERNEL);
+	if (!tree) {
+		rc = -ENOMEM;
+		goto out;
+	}
+
+	if (tcon->ipc) {
+		scnprintf(tree, MAX_TREE_SIZE, "\\\\%s\\IPC$", server->hostname);
+		rc = ops->tree_connect(xid, tcon->ses, tree, tcon, nlsc);
+		goto out;
+	}
+
+	sb = cifs_get_tcp_super(server);
+	if (IS_ERR(sb)) {
+		rc = PTR_ERR(sb);
+		cifs_dbg(VFS, "%s: could not find superblock: %d\n", __func__, rc);
+		goto out;
+	}
+
+	cifs_sb = CIFS_SB(sb);
+
+	/* If it is not dfs or there was no cached dfs referral, then reconnect to same share */
+	if (!server->current_fullpath ||
+	    dfs_cache_noreq_find(server->current_fullpath + 1, &ref, &tl)) {
+		rc = ops->tree_connect(xid, tcon->ses, tcon->tree_name, tcon, cifs_sb->local_nls);
+		goto out;
+	}
+
+	rc = tree_connect_dfs_target(xid, tcon, cifs_sb, tree, ref.server_type == DFS_TYPE_LINK,
+				     &tl);
+	free_dfs_info_param(&ref);
+
+out:
+	kfree(tree);
+	cifs_put_tcp_super(sb);
+
+	if (rc) {
+		spin_lock(&tcon->tc_lock);
+		if (tcon->status == TID_IN_TCON)
+			tcon->status = TID_NEED_TCON;
+		spin_unlock(&tcon->tc_lock);
+	} else {
+		spin_lock(&tcon->tc_lock);
+		if (tcon->status == TID_IN_TCON)
+			tcon->status = TID_GOOD;
+		spin_unlock(&tcon->tc_lock);
+		tcon->need_reconnect = false;
+	}
+
+	return rc;
+}
diff --git a/fs/cifs/dfs_cache.c b/fs/cifs/dfs_cache.c
index cb83b86eafe64..43ad1176dcb9d 100644
--- a/fs/cifs/dfs_cache.c
+++ b/fs/cifs/dfs_cache.c
@@ -1082,26 +1082,23 @@ out_free_path:
  *
  * Return zero if the target hint was updated successfully, otherwise non-zero.
  */
-int dfs_cache_noreq_update_tgthint(const char *path, const struct dfs_cache_tgt_iterator *it)
+void dfs_cache_noreq_update_tgthint(const char *path, const struct dfs_cache_tgt_iterator *it)
 {
-	int rc;
-	struct cache_entry *ce;
 	struct cache_dfs_tgt *t;
+	struct cache_entry *ce;
 
-	if (!it)
-		return -EINVAL;
+	if (!path || !it)
+		return;
 
 	cifs_dbg(FYI, "%s: path: %s\n", __func__, path);
 
-	down_write(&htable_rw_lock);
+	if (!down_write_trylock(&htable_rw_lock))
+		return;
 
 	ce = lookup_cache_entry(path);
-	if (IS_ERR(ce)) {
-		rc = PTR_ERR(ce);
+	if (IS_ERR(ce))
 		goto out_unlock;
-	}
 
-	rc = 0;
 	t = ce->tgthint;
 
 	if (unlikely(!strcasecmp(it->it_name, t->name)))
@@ -1118,7 +1115,6 @@ int dfs_cache_noreq_update_tgthint(const char *path, const struct dfs_cache_tgt_
 
 out_unlock:
 	up_write(&htable_rw_lock);
-	return rc;
 }
 
 /**
diff --git a/fs/cifs/dfs_cache.h b/fs/cifs/dfs_cache.h
index 52070d1df1897..f7cff0be93274 100644
--- a/fs/cifs/dfs_cache.h
+++ b/fs/cifs/dfs_cache.h
@@ -38,7 +38,7 @@ int dfs_cache_noreq_find(const char *path, struct dfs_info3_param *ref,
 int dfs_cache_update_tgthint(const unsigned int xid, struct cifs_ses *ses,
 			     const struct nls_table *cp, int remap, const char *path,
 			     const struct dfs_cache_tgt_iterator *it);
-int dfs_cache_noreq_update_tgthint(const char *path, const struct dfs_cache_tgt_iterator *it);
+void dfs_cache_noreq_update_tgthint(const char *path, const struct dfs_cache_tgt_iterator *it);
 int dfs_cache_get_tgt_referral(const char *path, const struct dfs_cache_tgt_iterator *it,
 			       struct dfs_info3_param *ref);
 int dfs_cache_get_tgt_share(char *path, const struct dfs_cache_tgt_iterator *it, char **share,
-- 
GitLab


From a85ceafd41927e41a4103d228a993df7edd8823b Mon Sep 17 00:00:00 2001
From: Paulo Alcantara <pc@cjr.nz>
Date: Fri, 16 Dec 2022 22:03:41 -0300
Subject: [PATCH 490/875] cifs: fix confusing debug message

Since rc was initialised to -ENOMEM in cifs_get_smb_ses(), when an
existing smb session was found, free_xid() would be called and then
print

  CIFS: fs/cifs/connect.c: Existing tcp session with server found
  CIFS: fs/cifs/connect.c: VFS: in cifs_get_smb_ses as Xid: 44 with uid: 0
  CIFS: fs/cifs/connect.c: Existing smb sess found (status=1)
  CIFS: fs/cifs/connect.c: VFS: leaving cifs_get_smb_ses (xid = 44) rc = -12

Fix this by initialising rc to 0 and then let free_xid() print this
instead

  CIFS: fs/cifs/connect.c: Existing tcp session with server found
  CIFS: fs/cifs/connect.c: VFS: in cifs_get_smb_ses as Xid: 14 with uid: 0
  CIFS: fs/cifs/connect.c: Existing smb sess found (status=1)
  CIFS: fs/cifs/connect.c: VFS: leaving cifs_get_smb_ses (xid = 14) rc = 0

Signed-off-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Cc: stable@vger.kernel.org
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/connect.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c
index 41009ef7878f9..069e894d59174 100644
--- a/fs/cifs/connect.c
+++ b/fs/cifs/connect.c
@@ -2142,7 +2142,7 @@ cifs_set_cifscreds(struct smb3_fs_context *ctx __attribute__((unused)),
 struct cifs_ses *
 cifs_get_smb_ses(struct TCP_Server_Info *server, struct smb3_fs_context *ctx)
 {
-	int rc = -ENOMEM;
+	int rc = 0;
 	unsigned int xid;
 	struct cifs_ses *ses;
 	struct sockaddr_in *addr = (struct sockaddr_in *)&server->dstaddr;
@@ -2191,6 +2191,8 @@ cifs_get_smb_ses(struct TCP_Server_Info *server, struct smb3_fs_context *ctx)
 		return ses;
 	}
 
+	rc = -ENOMEM;
+
 	cifs_dbg(FYI, "Existing smb sess not found\n");
 	ses = sesInfoAlloc();
 	if (ses == NULL)
-- 
GitLab


From 466611e4af8252dce253cfaebdc7b0019acdbe7e Mon Sep 17 00:00:00 2001
From: Paulo Alcantara <pc@cjr.nz>
Date: Fri, 16 Dec 2022 23:25:38 -0300
Subject: [PATCH 491/875] cifs: fix source pathname comparison of dfs supers

We store the TCP_Server_Info::origin_fullpath path canonicalised
(e.g. with '\\' path separators), so ignore separators when comparing
it with smb3_fs_context::source.

Signed-off-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/connect.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c
index 069e894d59174..a66c7422b8bcd 100644
--- a/fs/cifs/connect.c
+++ b/fs/cifs/connect.c
@@ -1412,6 +1412,20 @@ match_security(struct TCP_Server_Info *server, struct smb3_fs_context *ctx)
 	return true;
 }
 
+static bool dfs_src_pathname_equal(const char *s1, const char *s2)
+{
+	if (strlen(s1) != strlen(s2))
+		return false;
+	for (; *s1; s1++, s2++) {
+		if (*s1 == '/' || *s1 == '\\') {
+			if (*s2 != '/' && *s2 != '\\')
+				return false;
+		} else if (tolower(*s1) != tolower(*s2))
+			return false;
+	}
+	return true;
+}
+
 /* this function must be called with srv_lock held */
 static int match_server(struct TCP_Server_Info *server, struct smb3_fs_context *ctx,
 			bool dfs_super_cmp)
@@ -1449,7 +1463,7 @@ static int match_server(struct TCP_Server_Info *server, struct smb3_fs_context *
 	 */
 	if (dfs_super_cmp) {
 		if (!ctx->source || !server->origin_fullpath ||
-		    strcasecmp(server->origin_fullpath, ctx->source))
+		    !dfs_src_pathname_equal(server->origin_fullpath, ctx->source))
 			return 0;
 	} else {
 		/* Skip addr, hostname and port matching for DFS connections */
-- 
GitLab


From 6fbdd5ab240443e3f8574eb9d407d03daace1ddc Mon Sep 17 00:00:00 2001
From: Paulo Alcantara <pc@cjr.nz>
Date: Sat, 17 Dec 2022 00:46:11 -0300
Subject: [PATCH 492/875] cifs: optimize reconnect of nested links

There is no point going all the way back to the original dfs full path
if reconnect of tcon did not finish due a nested link found as newly
resolved target for the current referral.  So, just mark current
server for reconnect as we already set @current_fullpath to the new
dfs referral in update_server_fullpath().

Signed-off-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/dfs.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/fs/cifs/dfs.c b/fs/cifs/dfs.c
index 5afabca654c11..b541e68378f64 100644
--- a/fs/cifs/dfs.c
+++ b/fs/cifs/dfs.c
@@ -451,6 +451,7 @@ static int tree_connect_dfs_target(const unsigned int xid, struct cifs_tcon *tco
 	int rc;
 	int num_links = 0;
 	struct TCP_Server_Info *server = tcon->ses->server;
+	char *old_fullpath = server->leaf_fullpath;
 
 	do {
 		rc = __tree_connect_dfs_target(xid, tcon, cifs_sb, tree, islink, tl);
@@ -458,13 +459,11 @@ static int tree_connect_dfs_target(const unsigned int xid, struct cifs_tcon *tco
 			break;
 	} while (rc = -ELOOP, ++num_links < MAX_NESTED_LINKS);
 	/*
-	 * If we couldn't tree connect to any targets from last referral path, then retry from
-	 * original referral path.
+	 * If we couldn't tree connect to any targets from last referral path, then
+	 * retry it from newly resolved dfs referral.
 	 */
-	if (rc && server->current_fullpath != server->origin_fullpath) {
-		server->current_fullpath = server->origin_fullpath;
+	if (rc && server->leaf_fullpath != old_fullpath)
 		cifs_signal_cifsd_for_reconnect(server, true);
-	}
 
 	dfs_cache_free_tgts(tl);
 	return rc;
-- 
GitLab


From 25cf01b7c9200d6ace5a59125d8166435dd9dea7 Mon Sep 17 00:00:00 2001
From: Paulo Alcantara <pc@cjr.nz>
Date: Sat, 17 Dec 2022 21:04:14 -0300
Subject: [PATCH 493/875] cifs: set correct status of tcon ipc when
 reconnecting

The status of tcon ipcs were not being set to TID_NEED_RECO when
marking sessions and tcons to be reconnected, therefore not sending
tree connect to those ipcs in cifs_tree_connect() and leaving them
disconnected.

Cc: stable@vger.kernel.org
Signed-off-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/connect.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c
index a66c7422b8bcd..16da583536a46 100644
--- a/fs/cifs/connect.c
+++ b/fs/cifs/connect.c
@@ -262,8 +262,10 @@ cifs_mark_tcp_ses_conns_for_reconnect(struct TCP_Server_Info *server,
 			tcon->need_reconnect = true;
 			tcon->status = TID_NEED_RECON;
 		}
-		if (ses->tcon_ipc)
+		if (ses->tcon_ipc) {
 			ses->tcon_ipc->need_reconnect = true;
+			ses->tcon_ipc->status = TID_NEED_RECON;
+		}
 
 next_session:
 		spin_unlock(&ses->chan_lock);
-- 
GitLab


From 7ad54b98fc1f141cfb70cfe2a3d6def5a85169ff Mon Sep 17 00:00:00 2001
From: Paulo Alcantara <pc@cjr.nz>
Date: Sun, 18 Dec 2022 14:37:32 -0300
Subject: [PATCH 494/875] cifs: use origin fullpath for automounts

Use TCP_Server_Info::origin_fullpath instead of cifs_tcon::tree_name
when building source paths for automounts as it will be useful for
domain-based DFS referrals where the connections and referrals would
get either re-used from the cache or re-created when chasing the dfs
link.

Signed-off-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/cifs_dfs_ref.c | 24 ++++++++++++++++++++----
 fs/cifs/cifsproto.h    |  3 +++
 fs/cifs/dfs.h          | 15 +++++++++++++++
 fs/cifs/dir.c          | 21 +++++++++++++++------
 4 files changed, 53 insertions(+), 10 deletions(-)

diff --git a/fs/cifs/cifs_dfs_ref.c b/fs/cifs/cifs_dfs_ref.c
index cae8a52c6d9a0..2b1a8d55b4ec4 100644
--- a/fs/cifs/cifs_dfs_ref.c
+++ b/fs/cifs/cifs_dfs_ref.c
@@ -21,8 +21,7 @@
 #include "cifsfs.h"
 #include "dns_resolve.h"
 #include "cifs_debug.h"
-#include "cifs_unicode.h"
-#include "dfs_cache.h"
+#include "dfs.h"
 #include "fs_context.h"
 
 static LIST_HEAD(cifs_dfs_automount_list);
@@ -119,6 +118,17 @@ cifs_build_devname(char *nodename, const char *prepath)
 	return dev;
 }
 
+static int set_dest_addr(struct smb3_fs_context *ctx, const char *full_path)
+{
+	struct sockaddr *addr = (struct sockaddr *)&ctx->dstaddr;
+	int rc;
+
+	rc = dns_resolve_server_name_to_ip(full_path, addr, NULL);
+	if (!rc)
+		cifs_set_port(addr, ctx->port);
+	return rc;
+}
+
 /*
  * Create a vfsmount that we can automount
  */
@@ -156,8 +166,7 @@ static struct vfsmount *cifs_dfs_do_automount(struct path *path)
 	ctx = smb3_fc2context(fc);
 
 	page = alloc_dentry_path();
-	/* always use tree name prefix */
-	full_path = build_path_from_dentry_optional_prefix(mntpt, page, true);
+	full_path = dfs_get_automount_devname(mntpt, page);
 	if (IS_ERR(full_path)) {
 		mnt = ERR_CAST(full_path);
 		goto out;
@@ -168,6 +177,7 @@ static struct vfsmount *cifs_dfs_do_automount(struct path *path)
 
 	tmp = *cur_ctx;
 	tmp.source = full_path;
+	tmp.leaf_fullpath = NULL;
 	tmp.UNC = tmp.prepath = NULL;
 
 	rc = smb3_fs_context_dup(ctx, &tmp);
@@ -176,6 +186,12 @@ static struct vfsmount *cifs_dfs_do_automount(struct path *path)
 		goto out;
 	}
 
+	rc = set_dest_addr(ctx, full_path);
+	if (rc) {
+		mnt = ERR_PTR(rc);
+		goto out;
+	}
+
 	rc = smb3_parse_devname(full_path, ctx);
 	if (!rc)
 		mnt = fc_mount(fc);
diff --git a/fs/cifs/cifsproto.h b/fs/cifs/cifsproto.h
index 4efe1bc9783e8..1207b39686fb9 100644
--- a/fs/cifs/cifsproto.h
+++ b/fs/cifs/cifsproto.h
@@ -57,6 +57,9 @@ extern void exit_cifs_idmap(void);
 extern int init_cifs_spnego(void);
 extern void exit_cifs_spnego(void);
 extern const char *build_path_from_dentry(struct dentry *, void *);
+char *__build_path_from_dentry_optional_prefix(struct dentry *direntry, void *page,
+					       const char *tree, int tree_len,
+					       bool prefix);
 extern char *build_path_from_dentry_optional_prefix(struct dentry *direntry,
 						    void *page, bool prefix);
 static inline void *alloc_dentry_path(void)
diff --git a/fs/cifs/dfs.h b/fs/cifs/dfs.h
index bbe2ec25b0c2e..344bea6d8bab1 100644
--- a/fs/cifs/dfs.h
+++ b/fs/cifs/dfs.h
@@ -28,4 +28,19 @@ static inline int dfs_get_referral(struct cifs_mount_ctx *mnt_ctx, const char *p
 			      cifs_remap(cifs_sb), path, ref, tl);
 }
 
+static inline char *dfs_get_automount_devname(struct dentry *dentry, void *page)
+{
+	struct cifs_sb_info *cifs_sb = CIFS_SB(dentry->d_sb);
+	struct cifs_tcon *tcon = cifs_sb_master_tcon(cifs_sb);
+	struct TCP_Server_Info *server = tcon->ses->server;
+
+	if (unlikely(!server->origin_fullpath))
+		return ERR_PTR(-EREMOTE);
+
+	return __build_path_from_dentry_optional_prefix(dentry, page,
+							server->origin_fullpath,
+							strlen(server->origin_fullpath),
+							true);
+}
+
 #endif /* _CIFS_DFS_H */
diff --git a/fs/cifs/dir.c b/fs/cifs/dir.c
index 8b1c371585564..ad4208bf1e321 100644
--- a/fs/cifs/dir.c
+++ b/fs/cifs/dir.c
@@ -78,14 +78,13 @@ build_path_from_dentry(struct dentry *direntry, void *page)
 						      prefix);
 }
 
-char *
-build_path_from_dentry_optional_prefix(struct dentry *direntry, void *page,
-				       bool prefix)
+char *__build_path_from_dentry_optional_prefix(struct dentry *direntry, void *page,
+					       const char *tree, int tree_len,
+					       bool prefix)
 {
 	int dfsplen;
 	int pplen = 0;
 	struct cifs_sb_info *cifs_sb = CIFS_SB(direntry->d_sb);
-	struct cifs_tcon *tcon = cifs_sb_master_tcon(cifs_sb);
 	char dirsep = CIFS_DIR_SEP(cifs_sb);
 	char *s;
 
@@ -93,7 +92,7 @@ build_path_from_dentry_optional_prefix(struct dentry *direntry, void *page,
 		return ERR_PTR(-ENOMEM);
 
 	if (prefix)
-		dfsplen = strnlen(tcon->tree_name, MAX_TREE_SIZE + 1);
+		dfsplen = strnlen(tree, tree_len + 1);
 	else
 		dfsplen = 0;
 
@@ -123,7 +122,7 @@ build_path_from_dentry_optional_prefix(struct dentry *direntry, void *page,
 	}
 	if (dfsplen) {
 		s -= dfsplen;
-		memcpy(s, tcon->tree_name, dfsplen);
+		memcpy(s, tree, dfsplen);
 		if (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_POSIX_PATHS) {
 			int i;
 			for (i = 0; i < dfsplen; i++) {
@@ -135,6 +134,16 @@ build_path_from_dentry_optional_prefix(struct dentry *direntry, void *page,
 	return s;
 }
 
+char *build_path_from_dentry_optional_prefix(struct dentry *direntry, void *page,
+					     bool prefix)
+{
+	struct cifs_sb_info *cifs_sb = CIFS_SB(direntry->d_sb);
+	struct cifs_tcon *tcon = cifs_sb_master_tcon(cifs_sb);
+
+	return __build_path_from_dentry_optional_prefix(direntry, page, tcon->tree_name,
+							MAX_TREE_SIZE, prefix);
+}
+
 /*
  * Don't allow path components longer than the server max.
  * Don't allow the separator character in a path component.
-- 
GitLab


From f60ffa662d1427cfd31fe9d895c3566ac50bfe52 Mon Sep 17 00:00:00 2001
From: Paulo Alcantara <pc@cjr.nz>
Date: Mon, 19 Dec 2022 10:21:50 -0300
Subject: [PATCH 495/875] cifs: don't leak -ENOMEM in smb2_open_file()

A NULL error response might be a valid case where smb2_reconnect()
failed to reconnect the session and tcon due to a disconnected server
prior to issuing the I/O operation, so don't leak -ENOMEM to userspace
on such occasions.

Fixes: 76894f3e2f71 ("cifs: improve symlink handling for smb2+")
Signed-off-by: Paulo Alcantara (SUSE) <pc@cjr.nz>
Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/smb2file.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/fs/cifs/smb2file.c b/fs/cifs/smb2file.c
index ffbd9a99fc128..ba6cc50af390f 100644
--- a/fs/cifs/smb2file.c
+++ b/fs/cifs/smb2file.c
@@ -122,8 +122,8 @@ int smb2_open_file(const unsigned int xid, struct cifs_open_parms *oparms, __u32
 		struct smb2_hdr *hdr = err_iov.iov_base;
 
 		if (unlikely(!err_iov.iov_base || err_buftype == CIFS_NO_BUFFER))
-			rc = -ENOMEM;
-		else if (hdr->Status == STATUS_STOPPED_ON_SYMLINK) {
+			goto out;
+		if (hdr->Status == STATUS_STOPPED_ON_SYMLINK) {
 			rc = smb2_parse_symlink_response(oparms->cifs_sb, &err_iov,
 							 &data->symlink_target);
 			if (!rc) {
-- 
GitLab


From aacfc939cc42293fbcfe113040b4e8abaef68429 Mon Sep 17 00:00:00 2001
From: Steve French <stfrench@microsoft.com>
Date: Thu, 15 Dec 2022 20:03:17 -0600
Subject: [PATCH 496/875] cifs: update internal module number

To 2.41

Signed-off-by: Steve French <stfrench@microsoft.com>
---
 fs/cifs/cifsfs.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/fs/cifs/cifsfs.h b/fs/cifs/cifsfs.h
index 00a573e0ad0e1..63a0ac2b93558 100644
--- a/fs/cifs/cifsfs.h
+++ b/fs/cifs/cifsfs.h
@@ -153,6 +153,6 @@ extern const struct export_operations cifs_export_ops;
 #endif /* CONFIG_CIFS_NFSD_EXPORT */
 
 /* when changing internal version - update following two lines at same time */
-#define SMB3_PRODUCT_BUILD 40
-#define CIFS_VERSION   "2.40"
+#define SMB3_PRODUCT_BUILD 41
+#define CIFS_VERSION   "2.41"
 #endif				/* _CIFSFS_H */
-- 
GitLab


From 990a4de57e44f4f4cfc33c90d2ec5d285b7c8342 Mon Sep 17 00:00:00 2001
From: Jens Axboe <axboe@kernel.dk>
Date: Mon, 19 Dec 2022 07:28:26 -0700
Subject: [PATCH 497/875] io_uring/net: ensure compat import handlers clear
 free_iov

If we're not allocating the vectors because the count is below
UIO_FASTIOV, we still do need to properly clear ->free_iov to prevent
an erronous free of on-stack data.

Reported-by: Jiri Slaby <jirislaby@gmail.com>
Fixes: 4c17a496a7a0 ("io_uring/net: fix cleanup double free free_iov init")
Cc: stable@vger.kernel.org
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 io_uring/net.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/io_uring/net.c b/io_uring/net.c
index 5229976cb5829..f76b688f476e7 100644
--- a/io_uring/net.c
+++ b/io_uring/net.c
@@ -494,6 +494,7 @@ static int __io_compat_recvmsg_copy_hdr(struct io_kiocb *req,
 	if (req->flags & REQ_F_BUFFER_SELECT) {
 		compat_ssize_t clen;
 
+		iomsg->free_iov = NULL;
 		if (msg.msg_iovlen == 0) {
 			sr->len = 0;
 		} else if (msg.msg_iovlen > 1) {
-- 
GitLab


From 66dfc517e8ec530b1d8d4776c05e3f264f38ecb8 Mon Sep 17 00:00:00 2001
From: Arnaldo Carvalho de Melo <acme@redhat.com>
Date: Sat, 17 Dec 2022 11:37:15 -0300
Subject: [PATCH 498/875] perf python: Don't stop building if python setuptools
 isn't installed

The python3-setuptools package is needed to build the python binding, so
that one can use things like:

  # ~acme/git/perf/tools/perf/python/twatch.py
  cpu: 6, pid: 4573, tid: 2184618 { type: exit, pid: 4573, ppid: 4172, tid: 2184618, ptid: 4172, time: 12563190090107}
  cpu: 24, pid: 4573, tid: 4573 { type: fork, pid: 4573, ppid: 4573, tid: 2190991, ptid: 4573, time: 12563415289331}
  cpu: 29, pid: 4573, tid: 2190991 { type: comm, pid: 4573, tid: 2190991, comm: StreamT~ns #401 }
  cpu: 29, pid: 4573, tid: 2190991 { type: comm, pid: 4573, tid: 2190991, comm: StreamT~ns #401 }
  ^CTraceback (most recent call last):
    File "/var/home/acme/git/perf/tools/perf/python/twatch.py", line 61, in <module>
      main()
    File "/var/home/acme/git/perf/tools/perf/python/twatch.py", line 33, in main
      evlist.poll(timeout = -1)
  KeyboardInterrupt

  #

That have 'import perf;'.

But distros don't always have that python3-setuptools (or equivalent)
installed, which was breaking the build. Just check if it is installed
and emit a warning that such binding isn't being built and continue the
build without it:

With it:

  $ rpm -q python3-setuptools
  python3-setuptools-59.6.0-3.fc36.noarch
  $ rm -rf /tmp/build/perf; mkdir -p /tmp/build/perf
  $ make O=/tmp/build/perf -C tools/perf install-bin
  make: Entering directory '/var/home/acme/git/perf/tools/perf'
  <SNIP>
  ...                               libpython: [ on  ]
  <SNIP>
    GEN     /tmp/build/perf/python/perf.cpython-310-x86_64-linux-gnu.so
  <SNIP>
  $ ls -la /tmp/build/perf/python/perf.cpython-310-x86_64-linux-gnu.so
  -rwxr-xr-x. 1 acme acme 1609112 Dec 17 11:39 /tmp/build/perf/python/perf.cpython-310-x86_64-linux-gnu.so
  $

Without it:

  $ sudo rpm -e python3-setuptools
  $ rm -rf /tmp/build/perf ; mkdir -p /tmp/build/perf
  $ make O=/tmp/build/perf -C tools/perf install-bin
  make: Entering directory '/var/home/acme/git/perf/tools/perf'
  <SNIP>
  ...                               libpython: [ on  ]
  <SNIP>
  $ ls -la /tmp/build/perf/python/perf.cpython-310-x86_64-linux-gnu.so
  ls: cannot access '/tmp/build/perf/python/perf.cpython-310-x86_64-linux-gnu.so': No such file or directory
  $

Reported-by: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Link: http://lore.kernel.org/lkml/Y53XHw3rlsaaUgOs@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/Makefile.config | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config
index 83ed969b95b4a..c21bd6010be13 100644
--- a/tools/perf/Makefile.config
+++ b/tools/perf/Makefile.config
@@ -890,8 +890,13 @@ else
       else
          LDFLAGS += $(PYTHON_EMBED_LDFLAGS)
          EXTLIBS += $(PYTHON_EMBED_LIBADD)
-         PYTHON_EXTENSION_SUFFIX := $(shell $(PYTHON) -c 'from importlib import machinery; print(machinery.EXTENSION_SUFFIXES[0])')
-         LANG_BINDINGS += $(obj-perf)python/perf$(PYTHON_EXTENSION_SUFFIX)
+         PYTHON_SETUPTOOLS_INSTALLED := $(shell $(PYTHON) -c 'import setuptools;' 2> /dev/null && echo "yes" || echo "no")
+         ifeq ($(PYTHON_SETUPTOOLS_INSTALLED), yes)
+           PYTHON_EXTENSION_SUFFIX := $(shell $(PYTHON) -c 'from importlib import machinery; print(machinery.EXTENSION_SUFFIXES[0])')
+           LANG_BINDINGS += $(obj-perf)python/perf$(PYTHON_EXTENSION_SUFFIX)
+	 else
+           msg := $(warning Missing python setuptools, the python binding won't be built, please install python3-setuptools or equivalent);
+         endif
          CFLAGS += -DHAVE_LIBPYTHON_SUPPORT
          $(call detected,CONFIG_LIBPYTHON)
       endif
-- 
GitLab


From 0bc1d0e2c16736a75f73a94d3a73370801a6ceb2 Mon Sep 17 00:00:00 2001
From: Arnaldo Carvalho de Melo <acme@redhat.com>
Date: Mon, 19 Dec 2022 12:21:58 -0300
Subject: [PATCH 499/875] tools headers disabled-cpufeatures: Sync with the
 kernel sources

To pick the changes from:

  15e15d64bd8e12d8 ("x86/cpufeatures: Add X86_FEATURE_XENPV to disabled-features.h")

This only causes these perf files to be rebuilt:

  CC       /tmp/build/perf/bench/mem-memcpy-x86-64-asm.o
  CC       /tmp/build/perf/bench/mem-memset-x86-64-asm.o

And addresses this perf build warning:

  Warning: Kernel ABI header at 'tools/arch/x86/include/asm/disabled-features.h' differs from latest version at 'arch/x86/include/asm/disabled-features.h'
  diff -u tools/arch/x86/include/asm/disabled-features.h arch/x86/include/asm/disabled-features.h

Cc:  Hunter <adrian.hunter@intel.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Ian Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Juergen Gross <jgross@suse.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/lkml/Y6B2w3WqifB%2FV70T@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/arch/x86/include/asm/disabled-features.h | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/tools/arch/x86/include/asm/disabled-features.h b/tools/arch/x86/include/asm/disabled-features.h
index 33d2cd04d2544..c44b56f7ffba0 100644
--- a/tools/arch/x86/include/asm/disabled-features.h
+++ b/tools/arch/x86/include/asm/disabled-features.h
@@ -69,6 +69,12 @@
 # define DISABLE_UNRET		(1 << (X86_FEATURE_UNRET & 31))
 #endif
 
+#ifdef CONFIG_CALL_DEPTH_TRACKING
+# define DISABLE_CALL_DEPTH_TRACKING	0
+#else
+# define DISABLE_CALL_DEPTH_TRACKING	(1 << (X86_FEATURE_CALL_DEPTH & 31))
+#endif
+
 #ifdef CONFIG_INTEL_IOMMU_SVM
 # define DISABLE_ENQCMD		0
 #else
@@ -81,6 +87,12 @@
 # define DISABLE_SGX	(1 << (X86_FEATURE_SGX & 31))
 #endif
 
+#ifdef CONFIG_XEN_PV
+# define DISABLE_XENPV		0
+#else
+# define DISABLE_XENPV		(1 << (X86_FEATURE_XENPV & 31))
+#endif
+
 #ifdef CONFIG_INTEL_TDX_GUEST
 # define DISABLE_TDX_GUEST	0
 #else
@@ -98,10 +110,11 @@
 #define DISABLED_MASK5	0
 #define DISABLED_MASK6	0
 #define DISABLED_MASK7	(DISABLE_PTI)
-#define DISABLED_MASK8	(DISABLE_TDX_GUEST)
+#define DISABLED_MASK8	(DISABLE_XENPV|DISABLE_TDX_GUEST)
 #define DISABLED_MASK9	(DISABLE_SGX)
 #define DISABLED_MASK10	0
-#define DISABLED_MASK11	(DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET)
+#define DISABLED_MASK11	(DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET| \
+			 DISABLE_CALL_DEPTH_TRACKING)
 #define DISABLED_MASK12	0
 #define DISABLED_MASK13	0
 #define DISABLED_MASK14	0
-- 
GitLab


From 6c3e8955d4bd9811a6e1761eea412a14fb51a2e6 Mon Sep 17 00:00:00 2001
From: Pavel Begunkov <asml.silence@gmail.com>
Date: Mon, 19 Dec 2022 15:11:40 +0000
Subject: [PATCH 500/875] io_uring/net: fix cleanup after recycle

Don't access io_async_msghdr io_netmsg_recycle(), it may be reallocated.

Cc: stable@vger.kernel.org
Fixes: 9bb66906f23e5 ("io_uring: support multishot in recvmsg")
Signed-off-by: Pavel Begunkov <asml.silence@gmail.com>
Link: https://lore.kernel.org/r/9e326f4ad4046ddadf15bf34bf3fa58c6372f6b5.1671461985.git.asml.silence@gmail.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 io_uring/net.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/io_uring/net.c b/io_uring/net.c
index f76b688f476e7..fbc34a7c27439 100644
--- a/io_uring/net.c
+++ b/io_uring/net.c
@@ -820,10 +820,10 @@ retry_multishot:
 		goto retry_multishot;
 
 	if (mshot_finished) {
-		io_netmsg_recycle(req, issue_flags);
 		/* fast path, check for non-NULL to avoid function call */
 		if (kmsg->free_iov)
 			kfree(kmsg->free_iov);
+		io_netmsg_recycle(req, issue_flags);
 		req->flags &= ~REQ_F_NEED_CLEANUP;
 	}
 
-- 
GitLab


From 51c4f2bf5397b34b79a6712221606e0ab2e6f7ed Mon Sep 17 00:00:00 2001
From: Arnaldo Carvalho de Melo <acme@redhat.com>
Date: Thu, 1 Jul 2021 13:39:15 -0300
Subject: [PATCH 501/875] tools headers cpufeatures: Sync with the kernel
 sources

To pick the changes from:

  5e85c4ebf206e50c ("x86: KVM: Advertise AVX-IFMA CPUID to user space")
  af2872f622547656 ("x86: KVM: Advertise AMX-FP16 CPUID to user space")
  6a19d7aa5821522e ("x86: KVM: Advertise CMPccXADD CPUID to user space")
  aaa65d17eec372c6 ("x86/tsx: Add a feature bit for TSX control MSR support")
  b1599915f09157e9 ("x86/cpufeatures: Move X86_FEATURE_CALL_DEPTH from bit 18 to bit 19 of word 11, to leave space for WIP X86_FEATURE_SGX_EDECCSSA bit")
  16a7fe3728a8b832 ("KVM/VMX: Allow exposing EDECCSSA user leaf function to KVM guest")
  80e4c1cd42fff110 ("x86/retbleed: Add X86_FEATURE_CALL_DEPTH")
  7df548840c496b01 ("x86/bugs: Add "unknown" reporting for MMIO Stale Data")

This only causes these perf files to be rebuilt:

  CC       /tmp/build/perf/bench/mem-memcpy-x86-64-asm.o
  CC       /tmp/build/perf/bench/mem-memset-x86-64-asm.o

And addresses this perf build warning:

  Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h'
  diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h

Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Chang S. Bae <chang.seok.bae@intel.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Jiaxi Chen <jiaxi.chen@linux.intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kai Huang <kai.huang@intel.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/lkml/Y6CD%2FIcEbDW5X%2FpN@kernel.org/
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/arch/x86/include/asm/cpufeatures.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index b71f4f2ecdd57..61012476d66e0 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -304,10 +304,16 @@
 #define X86_FEATURE_UNRET		(11*32+15) /* "" AMD BTB untrain return */
 #define X86_FEATURE_USE_IBPB_FW		(11*32+16) /* "" Use IBPB during runtime firmware calls */
 #define X86_FEATURE_RSB_VMEXIT_LITE	(11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */
+#define X86_FEATURE_SGX_EDECCSSA	(11*32+18) /* "" SGX EDECCSSA user leaf function */
+#define X86_FEATURE_CALL_DEPTH		(11*32+19) /* "" Call depth tracking for RSB stuffing */
+#define X86_FEATURE_MSR_TSX_CTRL	(11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
 #define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */
 #define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
+#define X86_FEATURE_CMPCCXADD           (12*32+ 7) /* "" CMPccXADD instructions */
+#define X86_FEATURE_AMX_FP16		(12*32+21) /* "" AMX fp16 Support */
+#define X86_FEATURE_AVX_IFMA            (12*32+23) /* "" Support for VPMADD52[H,L]UQ */
 
 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
 #define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
-- 
GitLab


From 43a3ce77aee917ac3b247e925853646fac4c05a6 Mon Sep 17 00:00:00 2001
From: Arnaldo Carvalho de Melo <acme@redhat.com>
Date: Thu, 17 Dec 2020 14:58:51 -0300
Subject: [PATCH 502/875] tools headers UAPI: Sync linux/fscrypt.h with the
 kernel sources

To pick the changes from:

  f8b435f93b7630af ("fscrypt: remove unused Speck definitions")
  e0cefada1383c5ce ("fscrypt: Add SM4 XTS/CTS symmetric algorithm support")

That don't result in any changes in tooling, just causes this to be
rebuilt:

  CC      /tmp/build/perf-urgent/trace/beauty/sync_file_range.o
  LD      /tmp/build/perf-urgent/trace/beauty/perf-in.o

addressing this perf build warning:

  Warning: Kernel ABI header at 'tools/include/uapi/linux/fscrypt.h' differs from latest version at 'include/uapi/linux/fscrypt.h'
  diff -u tools/include/uapi/linux/fscrypt.h include/uapi/linux/fscrypt.h

Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Eric Biggers <ebiggers@google.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Tianjia Zhang <tianjia.zhang@linux.alibaba.com>
Link: https://lore.kernel.org/lkml/Y6CHSS6Rn9YOqpAd@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/include/uapi/linux/fscrypt.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/include/uapi/linux/fscrypt.h b/tools/include/uapi/linux/fscrypt.h
index a756b29afcc23..fd1fb0d5389d3 100644
--- a/tools/include/uapi/linux/fscrypt.h
+++ b/tools/include/uapi/linux/fscrypt.h
@@ -26,6 +26,8 @@
 #define FSCRYPT_MODE_AES_256_CTS		4
 #define FSCRYPT_MODE_AES_128_CBC		5
 #define FSCRYPT_MODE_AES_128_CTS		6
+#define FSCRYPT_MODE_SM4_XTS			7
+#define FSCRYPT_MODE_SM4_CTS			8
 #define FSCRYPT_MODE_ADIANTUM			9
 #define FSCRYPT_MODE_AES_256_HCTR2		10
 /* If adding a mode number > 10, update FSCRYPT_MODE_MAX in fscrypt_private.h */
@@ -185,8 +187,6 @@ struct fscrypt_get_key_status_arg {
 #define FS_ENCRYPTION_MODE_AES_256_CTS	FSCRYPT_MODE_AES_256_CTS
 #define FS_ENCRYPTION_MODE_AES_128_CBC	FSCRYPT_MODE_AES_128_CBC
 #define FS_ENCRYPTION_MODE_AES_128_CTS	FSCRYPT_MODE_AES_128_CTS
-#define FS_ENCRYPTION_MODE_SPECK128_256_XTS	7	/* removed */
-#define FS_ENCRYPTION_MODE_SPECK128_256_CTS	8	/* removed */
 #define FS_ENCRYPTION_MODE_ADIANTUM	FSCRYPT_MODE_ADIANTUM
 #define FS_KEY_DESC_PREFIX		FSCRYPT_KEY_DESC_PREFIX
 #define FS_KEY_DESC_PREFIX_SIZE		FSCRYPT_KEY_DESC_PREFIX_SIZE
-- 
GitLab


From 5ad70eb27d2b87ec722fedd23638354be37ea0b0 Mon Sep 17 00:00:00 2001
From: Ammar Faizi <ammarfaizi2@gnuweeb.org>
Date: Mon, 19 Dec 2022 23:45:21 +0700
Subject: [PATCH 503/875] MAINTAINERS: io_uring: Add
 include/trace/events/io_uring.h

This header file was introduced in commit c826bd7a743f ("io_uring: add
set of tracing events"). It didn't get added to the io_uring
maintainers section. Add this header file to the io_uring maintainers
section.

Signed-off-by: Ammar Faizi <ammarfaizi2@gnuweeb.org>
Link: https://lore.kernel.org/r/20221219164521.2481728-1-ammar.faizi@intel.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index bb77a3ed9d542..aa19c15f82a9c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10825,6 +10825,7 @@ T:	git git://git.kernel.dk/liburing
 F:	io_uring/
 F:	include/linux/io_uring.h
 F:	include/linux/io_uring_types.h
+F:	include/trace/events/io_uring.h
 F:	include/uapi/linux/io_uring.h
 F:	tools/io_uring/
 
-- 
GitLab


From cc074822465d18a2d39e0b3e2b48b6766a568db2 Mon Sep 17 00:00:00 2001
From: Hou Tao <houtao1@huawei.com>
Date: Sat, 17 Dec 2022 14:21:44 +0800
Subject: [PATCH 504/875] bpf: Define sock security related BTF IDs under
 CONFIG_SECURITY_NETWORK

There are warnings reported from resolve_btfids when building vmlinux
with CONFIG_SECURITY_NETWORK disabled:

  WARN: resolve_btfids: unresolved symbol bpf_lsm_sk_free_security
  WARN: resolve_btfids: unresolved symbol bpf_lsm_sk_alloc_security

So only define BTF IDs for these LSM hooks when CONFIG_SECURITY_NETWORK
is enabled.

Fixes: c0c852dd1876 ("bpf: Do not mark certain LSM hook arguments as trusted")
Signed-off-by: Hou Tao <houtao1@huawei.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Acked-by: Yonghong Song <yhs@fb.com>
Link: https://lore.kernel.org/bpf/20221217062144.2507222-1-houtao@huaweicloud.com
---
 kernel/bpf/bpf_lsm.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/kernel/bpf/bpf_lsm.c b/kernel/bpf/bpf_lsm.c
index 9ea42a45da470..a4a41ee3e80b5 100644
--- a/kernel/bpf/bpf_lsm.c
+++ b/kernel/bpf/bpf_lsm.c
@@ -351,8 +351,10 @@ BTF_ID(func, bpf_lsm_bpf_prog_alloc_security)
 BTF_ID(func, bpf_lsm_bpf_prog_free_security)
 BTF_ID(func, bpf_lsm_file_alloc_security)
 BTF_ID(func, bpf_lsm_file_free_security)
+#ifdef CONFIG_SECURITY_NETWORK
 BTF_ID(func, bpf_lsm_sk_alloc_security)
 BTF_ID(func, bpf_lsm_sk_free_security)
+#endif /* CONFIG_SECURITY_NETWORK */
 BTF_ID(func, bpf_lsm_task_free)
 BTF_SET_END(untrusted_lsm_hooks)
 
-- 
GitLab


From 53ffa6a9f83b2170c60591da1ead8791d5a42e81 Mon Sep 17 00:00:00 2001
From: Jiasheng Jiang <jiasheng@iscas.ac.cn>
Date: Tue, 20 Dec 2022 10:49:21 +0800
Subject: [PATCH 505/875] HID: amd_sfh: Add missing check for
 dma_alloc_coherent

Add check for the return value of the dma_alloc_coherent since
it may return NULL pointer if allocation fails.

Fixes: 4b2c53d93a4b ("SFH:Transport Driver to add support of AMD Sensor Fusion Hub (SFH)")
Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn>
Acked-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com>
Link: https://lore.kernel.org/r/20221220024921.21992-1-jiasheng@iscas.ac.cn
---
 drivers/hid/amd-sfh-hid/amd_sfh_client.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/hid/amd-sfh-hid/amd_sfh_client.c b/drivers/hid/amd-sfh-hid/amd_sfh_client.c
index 8275bba636119..ab125f79408f2 100644
--- a/drivers/hid/amd-sfh-hid/amd_sfh_client.c
+++ b/drivers/hid/amd-sfh-hid/amd_sfh_client.c
@@ -237,6 +237,10 @@ int amd_sfh_hid_client_init(struct amd_mp2_dev *privdata)
 		in_data->sensor_virt_addr[i] = dma_alloc_coherent(dev, sizeof(int) * 8,
 								  &cl_data->sensor_dma_addr[i],
 								  GFP_KERNEL);
+		if (!in_data->sensor_virt_addr[i]) {
+			rc = -ENOMEM;
+			goto cleanup;
+		}
 		cl_data->sensor_sts[i] = SENSOR_DISABLED;
 		cl_data->sensor_requested_cnt[i] = 0;
 		cl_data->cur_hid_dev = i;
-- 
GitLab


From 1c4c0b28b517d778d37900deedfe91088839f07a Mon Sep 17 00:00:00 2001
From: Johannes Berg <johannes.berg@intel.com>
Date: Tue, 13 Dec 2022 23:15:04 +0200
Subject: [PATCH 506/875] wifi: iwlwifi: fw: skip PPAG for JF
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

For JF RFs we don't support PPAG, but many firmware
images lie about it. Always skip support for JF to
avoid firmware errors when sending the command.

Reported-and-tested-by: Íñigo Huguet <ihuguet@redhat.com>
Link: https://lore.kernel.org/linux-wireless/CACT4oufQsqHGp6bah2c4+jPn2wG1oZqY=UKa_TmPx=F6Lxng8Q@mail.gmail.com
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Gregory Greenman <gregory.greenman@intel.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20221213225723.2a43415d8990.I9ac210740a45b41f1b2e15274e1daf4284f2808a@changeid
---
 drivers/net/wireless/intel/iwlwifi/fw/acpi.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/net/wireless/intel/iwlwifi/fw/acpi.c b/drivers/net/wireless/intel/iwlwifi/fw/acpi.c
index e6d64152c81a7..a02e5a67b7066 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/acpi.c
+++ b/drivers/net/wireless/intel/iwlwifi/fw/acpi.c
@@ -1106,6 +1106,11 @@ int iwl_read_ppag_table(struct iwl_fw_runtime *fwrt, union iwl_ppag_table_cmd *c
         int i, j, num_sub_bands;
         s8 *gain;
 
+	/* many firmware images for JF lie about this */
+	if (CSR_HW_RFID_TYPE(fwrt->trans->hw_rf_id) ==
+	    CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_JF))
+		return -EOPNOTSUPP;
+
         if (!fw_has_capa(&fwrt->fw->ucode_capa, IWL_UCODE_TLV_CAPA_SET_PPAG)) {
                 IWL_DEBUG_RADIO(fwrt,
                                 "PPAG capability not supported by FW, command not sent.\n");
-- 
GitLab


From 37fc9ad1617a303bbfd28870eb25aaa4766e79ab Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Thu, 15 Dec 2022 17:31:10 +0100
Subject: [PATCH 507/875] wifi: mt76: mt7996: select CONFIG_RELAY

Without CONFIG_RELAY, the driver fails to link:

ERROR: modpost: "relay_flush" [drivers/net/wireless/mediatek/mt76/mt7996/mt7996e.ko] undefined!
ERROR: modpost: "relay_switch_subbuf" [drivers/net/wireless/mediatek/mt76/mt7996/mt7996e.ko] undefined!
ERROR: modpost: "relay_open" [drivers/net/wireless/mediatek/mt76/mt7996/mt7996e.ko] undefined!
ERROR: modpost: "relay_reset" [drivers/net/wireless/mediatek/mt76/mt7996/mt7996e.ko] undefined!
ERROR: modpost: "relay_file_operations" [drivers/net/wireless/mediatek/mt76/mt7996/mt7996e.ko] undefined!

The same change was done in mt7915 for the corresponding copy of the code.

Fixes: 98686cd21624 ("wifi: mt76: mt7996: add driver for MediaTek Wi-Fi 7 (802.11be) devices")
See-also: 988845c9361a ("mt76: mt7915: add support for passing chip/firmware debug data to user space")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20221215163133.4152299-1-arnd@kernel.org
---
 drivers/net/wireless/mediatek/mt76/mt7996/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/wireless/mediatek/mt76/mt7996/Kconfig b/drivers/net/wireless/mediatek/mt76/mt7996/Kconfig
index 5c5fc569e6d59..79fb47a73c91d 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7996/Kconfig
+++ b/drivers/net/wireless/mediatek/mt76/mt7996/Kconfig
@@ -2,6 +2,7 @@
 config MT7996E
 	tristate "MediaTek MT7996 (PCIe) support"
 	select MT76_CONNAC_LIB
+	select RELAY
 	depends on MAC80211
 	depends on PCI
 	help
-- 
GitLab


From b7dc753fe33a707379e2254317794a4dad6c0fe2 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Thu, 15 Dec 2022 17:55:42 +0100
Subject: [PATCH 508/875] wifi: ath9k: use proper statements in conditionals
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

A previous cleanup patch accidentally broke some conditional
expressions by replacing the safe "do {} while (0)" constructs
with empty macros. gcc points this out when extra warnings
are enabled:

drivers/net/wireless/ath/ath9k/hif_usb.c: In function 'ath9k_skb_queue_complete':
drivers/net/wireless/ath/ath9k/hif_usb.c:251:57: error: suggest braces around empty body in an 'else' statement [-Werror=empty-body]
  251 |                         TX_STAT_INC(hif_dev, skb_failed);

Make both sets of macros proper expressions again.

Fixes: d7fc76039b74 ("ath9k: htc: clean up statistics macros")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Toke Høiland-Jørgensen <toke@toke.dk>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20221215165553.1950307-1-arnd@kernel.org
---
 drivers/net/wireless/ath/ath9k/htc.h | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/net/wireless/ath/ath9k/htc.h b/drivers/net/wireless/ath/ath9k/htc.h
index 30f0765fb9fd8..237f4ec2cffd7 100644
--- a/drivers/net/wireless/ath/ath9k/htc.h
+++ b/drivers/net/wireless/ath/ath9k/htc.h
@@ -327,9 +327,9 @@ static inline struct ath9k_htc_tx_ctl *HTC_SKB_CB(struct sk_buff *skb)
 }
 
 #ifdef CONFIG_ATH9K_HTC_DEBUGFS
-#define __STAT_SAFE(hif_dev, expr)	((hif_dev)->htc_handle->drv_priv ? (expr) : 0)
-#define CAB_STAT_INC(priv)		((priv)->debug.tx_stats.cab_queued++)
-#define TX_QSTAT_INC(priv, q)		((priv)->debug.tx_stats.queue_stats[q]++)
+#define __STAT_SAFE(hif_dev, expr)	do { ((hif_dev)->htc_handle->drv_priv ? (expr) : 0); } while (0)
+#define CAB_STAT_INC(priv)		do { ((priv)->debug.tx_stats.cab_queued++); } while (0)
+#define TX_QSTAT_INC(priv, q)		do { ((priv)->debug.tx_stats.queue_stats[q]++); } while (0)
 
 #define TX_STAT_INC(hif_dev, c) \
 		__STAT_SAFE((hif_dev), (hif_dev)->htc_handle->drv_priv->debug.tx_stats.c++)
@@ -378,10 +378,10 @@ void ath9k_htc_get_et_stats(struct ieee80211_hw *hw,
 			    struct ethtool_stats *stats, u64 *data);
 #else
 
-#define TX_STAT_INC(hif_dev, c)
-#define TX_STAT_ADD(hif_dev, c, a)
-#define RX_STAT_INC(hif_dev, c)
-#define RX_STAT_ADD(hif_dev, c, a)
+#define TX_STAT_INC(hif_dev, c)		do { } while (0)
+#define TX_STAT_ADD(hif_dev, c, a)	do { } while (0)
+#define RX_STAT_INC(hif_dev, c)		do { } while (0)
+#define RX_STAT_ADD(hif_dev, c, a)	do { } while (0)
 
 #define CAB_STAT_INC(priv)
 #define TX_QSTAT_INC(priv, c)
-- 
GitLab


From 1db1f392591aff13fd643f0ec7c1d5e27391d700 Mon Sep 17 00:00:00 2001
From: Jason Gerecke <killertofu@gmail.com>
Date: Thu, 1 Dec 2022 15:11:41 -0800
Subject: [PATCH 509/875] HID: wacom: Ensure bootloader PID is usable in hidraw
 mode

Some Wacom devices have a special "bootloader" mode that is used for
firmware flashing. When operating in this mode, the device cannot be
used for input, and the HID descriptor is not able to be processed by
the driver. The driver generates an "Unknown device_type" warning and
then returns an error code from wacom_probe(). This is a problem because
userspace still needs to be able to interact with the device via hidraw
to perform the firmware flash.

This commit adds a non-generic device definition for 056a:0094 which
is used when devices are in "bootloader" mode. It marks the devices
with a special BOOTLOADER type that is recognized by wacom_probe() and
wacom_raw_event(). When we see this type we ensure a hidraw device is
created and otherwise keep our hands off so that userspace is in full
control.

Signed-off-by: Jason Gerecke <jason.gerecke@wacom.com>
Tested-by: Tatsunosuke Tobita <tatsunosuke.tobita@wacom.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
---
 drivers/hid/wacom_sys.c | 8 ++++++++
 drivers/hid/wacom_wac.c | 4 ++++
 drivers/hid/wacom_wac.h | 1 +
 3 files changed, 13 insertions(+)

diff --git a/drivers/hid/wacom_sys.c b/drivers/hid/wacom_sys.c
index 634263e4556b0..fb538a6c4add8 100644
--- a/drivers/hid/wacom_sys.c
+++ b/drivers/hid/wacom_sys.c
@@ -155,6 +155,9 @@ static int wacom_raw_event(struct hid_device *hdev, struct hid_report *report,
 {
 	struct wacom *wacom = hid_get_drvdata(hdev);
 
+	if (wacom->wacom_wac.features.type == BOOTLOADER)
+		return 0;
+
 	if (size > WACOM_PKGLEN_MAX)
 		return 1;
 
@@ -2785,6 +2788,11 @@ static int wacom_probe(struct hid_device *hdev,
 		return error;
 	}
 
+	if (features->type == BOOTLOADER) {
+		hid_warn(hdev, "Using device in hidraw-only mode");
+		return hid_hw_start(hdev, HID_CONNECT_HIDRAW);
+	}
+
 	error = wacom_parse_and_register(wacom, false);
 	if (error)
 		return error;
diff --git a/drivers/hid/wacom_wac.c b/drivers/hid/wacom_wac.c
index 0f3d57b426846..9312d611db8e5 100644
--- a/drivers/hid/wacom_wac.c
+++ b/drivers/hid/wacom_wac.c
@@ -4882,6 +4882,9 @@ static const struct wacom_features wacom_features_0x3dd =
 static const struct wacom_features wacom_features_HID_ANY_ID =
 	{ "Wacom HID", .type = HID_GENERIC, .oVid = HID_ANY_ID, .oPid = HID_ANY_ID };
 
+static const struct wacom_features wacom_features_0x94 =
+	{ "Wacom Bootloader", .type = BOOTLOADER };
+
 #define USB_DEVICE_WACOM(prod)						\
 	HID_DEVICE(BUS_USB, HID_GROUP_WACOM, USB_VENDOR_ID_WACOM, prod),\
 	.driver_data = (kernel_ulong_t)&wacom_features_##prod
@@ -4955,6 +4958,7 @@ const struct hid_device_id wacom_ids[] = {
 	{ USB_DEVICE_WACOM(0x84) },
 	{ USB_DEVICE_WACOM(0x90) },
 	{ USB_DEVICE_WACOM(0x93) },
+	{ USB_DEVICE_WACOM(0x94) },
 	{ USB_DEVICE_WACOM(0x97) },
 	{ USB_DEVICE_WACOM(0x9A) },
 	{ USB_DEVICE_WACOM(0x9F) },
diff --git a/drivers/hid/wacom_wac.h b/drivers/hid/wacom_wac.h
index 5ca6c06d143be..16f221388563d 100644
--- a/drivers/hid/wacom_wac.h
+++ b/drivers/hid/wacom_wac.h
@@ -243,6 +243,7 @@ enum {
 	MTTPC,
 	MTTPC_B,
 	HID_GENERIC,
+	BOOTLOADER,
 	MAX_TYPE
 };
 
-- 
GitLab


From cec827d658dd5c287ea8925737d45f0a60e47422 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jos=C3=A9=20Exp=C3=B3sito?= <jose.exposito89@gmail.com>
Date: Thu, 24 Nov 2022 18:49:32 +0100
Subject: [PATCH 510/875] HID: Ignore HP Envy x360 eu0009nv stylus battery
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Battery status is reported for the HP Envy x360 eu0009nv stylus even
though it does not have battery.

Prevent it from always reporting the battery as low (1%).

Link: https://gitlab.freedesktop.org/libinput/libinput/-/issues/823
Reported-by: Ioannis Iliopoulos <jxftw2424@gmail.com>
Tested-by: Ioannis Iliopoulos <jxftw2424@gmail.com>
Signed-off-by: José Expósito <jose.exposito89@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
---
 drivers/hid/hid-ids.h   | 1 +
 drivers/hid/hid-input.c | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h
index 8f58c3c1bec31..f103177a1355a 100644
--- a/drivers/hid/hid-ids.h
+++ b/drivers/hid/hid-ids.h
@@ -412,6 +412,7 @@
 #define USB_DEVICE_ID_HP_X2_10_COVER	0x0755
 #define I2C_DEVICE_ID_HP_ENVY_X360_15	0x2d05
 #define I2C_DEVICE_ID_HP_ENVY_X360_15T_DR100	0x29CF
+#define I2C_DEVICE_ID_HP_ENVY_X360_EU0009NV	0x2CF9
 #define I2C_DEVICE_ID_HP_SPECTRE_X360_15	0x2817
 #define USB_DEVICE_ID_ASUS_UX550VE_TOUCHSCREEN	0x2544
 #define USB_DEVICE_ID_ASUS_UX550_TOUCHSCREEN	0x2706
diff --git a/drivers/hid/hid-input.c b/drivers/hid/hid-input.c
index 3a93cf04147d1..9b59e436df0a5 100644
--- a/drivers/hid/hid-input.c
+++ b/drivers/hid/hid-input.c
@@ -380,6 +380,8 @@ static const struct hid_device_id hid_battery_quirks[] = {
 	  HID_BATTERY_QUIRK_IGNORE },
 	{ HID_I2C_DEVICE(USB_VENDOR_ID_ELAN, I2C_DEVICE_ID_HP_ENVY_X360_15T_DR100),
 	  HID_BATTERY_QUIRK_IGNORE },
+	{ HID_I2C_DEVICE(USB_VENDOR_ID_ELAN, I2C_DEVICE_ID_HP_ENVY_X360_EU0009NV),
+	  HID_BATTERY_QUIRK_IGNORE },
 	{ HID_I2C_DEVICE(USB_VENDOR_ID_ELAN, I2C_DEVICE_ID_HP_SPECTRE_X360_15),
 	  HID_BATTERY_QUIRK_IGNORE },
 	{ HID_I2C_DEVICE(USB_VENDOR_ID_ELAN, I2C_DEVICE_ID_SURFACE_GO_TOUCHSCREEN),
-- 
GitLab


From 4eab1c2fe06c98a4dff258dd64800b6986c101e9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jos=C3=A9=20Exp=C3=B3sito?= <jose.exposito89@gmail.com>
Date: Mon, 28 Nov 2022 17:57:05 +0100
Subject: [PATCH 511/875] HID: multitouch: fix Asus ExpertBook P2 P2451FA
 trackpoint
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The HID descriptor of this device contains two mouse collections, one
for mouse emulation and the other for the trackpoint.

Both collections get merged and, because the first one defines X and Y,
the movemenent events reported by the trackpoint collection are
ignored.

Set the MT_CLS_WIN_8_FORCE_MULTI_INPUT class for this device to be able
to receive its reports.

This fix is similar to/based on commit 40d5bb87377a ("HID: multitouch:
enable multi-input as a quirk for some devices").

Link: https://gitlab.freedesktop.org/libinput/libinput/-/issues/825
Reported-by: Akito <the@akito.ooo>
Tested-by: Akito <the@akito.ooo>
Signed-off-by: José Expósito <jose.exposito89@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
---
 drivers/hid/hid-multitouch.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/hid/hid-multitouch.c b/drivers/hid/hid-multitouch.c
index 91a4d3fc30e08..372cbdd223e09 100644
--- a/drivers/hid/hid-multitouch.c
+++ b/drivers/hid/hid-multitouch.c
@@ -1967,6 +1967,10 @@ static const struct hid_device_id mt_devices[] = {
 		HID_DEVICE(BUS_I2C, HID_GROUP_MULTITOUCH_WIN_8,
 			USB_VENDOR_ID_ELAN, 0x313a) },
 
+	{ .driver_data = MT_CLS_WIN_8_FORCE_MULTI_INPUT,
+		HID_DEVICE(BUS_I2C, HID_GROUP_MULTITOUCH_WIN_8,
+			USB_VENDOR_ID_ELAN, 0x3148) },
+
 	/* Elitegroup panel */
 	{ .driver_data = MT_CLS_SERIAL,
 		MT_USB_DEVICE(USB_VENDOR_ID_ELITEGROUP,
-- 
GitLab


From 3d57f36c89d8ba32b2c312f397a37fd1a2dc7cfc Mon Sep 17 00:00:00 2001
From: Terry Junge <linuxhid@cosmicgizmosystems.com>
Date: Thu, 8 Dec 2022 15:05:06 -0800
Subject: [PATCH 512/875] HID: plantronics: Additional PIDs for double volume
 key presses quirk

I no longer work for Plantronics (aka Poly, aka HP) and do not have
access to the headsets in order to test. However, as noted by Maxim,
the other 32xx models that share the same base code set as the 3220
would need the same quirk. This patch adds the PIDs for the rest of
the Blackwire 32XX product family that require the quirk.

Plantronics Blackwire 3210 Series (047f:c055)
Plantronics Blackwire 3215 Series (047f:c057)
Plantronics Blackwire 3225 Series (047f:c058)

Quote from previous patch by Maxim Mikityanskiy
Plantronics Blackwire 3220 Series (047f:c056) sends HID reports twice
for each volume key press. This patch adds a quirk to hid-plantronics
for this product ID, which will ignore the second volume key press if
it happens within 5 ms from the last one that was handled.

The patch was tested on the mentioned model only, it shouldn't affect
other models, however, this quirk might be needed for them too.
Auto-repeat (when a key is held pressed) is not affected, because the
rate is about 3 times per second, which is far less frequent than once
in 5 ms.
End quote

Signed-off-by: Terry Junge <linuxhid@cosmicgizmosystems.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
---
 drivers/hid/hid-ids.h         | 3 +++
 drivers/hid/hid-plantronics.c | 9 +++++++++
 2 files changed, 12 insertions(+)

diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h
index f103177a1355a..82713ef3aaa64 100644
--- a/drivers/hid/hid-ids.h
+++ b/drivers/hid/hid-ids.h
@@ -996,7 +996,10 @@
 #define USB_DEVICE_ID_ORTEK_IHOME_IMAC_A210S	0x8003
 
 #define USB_VENDOR_ID_PLANTRONICS	0x047f
+#define USB_DEVICE_ID_PLANTRONICS_BLACKWIRE_3210_SERIES	0xc055
 #define USB_DEVICE_ID_PLANTRONICS_BLACKWIRE_3220_SERIES	0xc056
+#define USB_DEVICE_ID_PLANTRONICS_BLACKWIRE_3215_SERIES	0xc057
+#define USB_DEVICE_ID_PLANTRONICS_BLACKWIRE_3225_SERIES	0xc058
 
 #define USB_VENDOR_ID_PANASONIC		0x04da
 #define USB_DEVICE_ID_PANABOARD_UBT780	0x1044
diff --git a/drivers/hid/hid-plantronics.c b/drivers/hid/hid-plantronics.c
index e81b7cec2d124..3d414ae194acb 100644
--- a/drivers/hid/hid-plantronics.c
+++ b/drivers/hid/hid-plantronics.c
@@ -198,9 +198,18 @@ err:
 }
 
 static const struct hid_device_id plantronics_devices[] = {
+	{ HID_USB_DEVICE(USB_VENDOR_ID_PLANTRONICS,
+					 USB_DEVICE_ID_PLANTRONICS_BLACKWIRE_3210_SERIES),
+		.driver_data = PLT_QUIRK_DOUBLE_VOLUME_KEYS },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_PLANTRONICS,
 					 USB_DEVICE_ID_PLANTRONICS_BLACKWIRE_3220_SERIES),
 		.driver_data = PLT_QUIRK_DOUBLE_VOLUME_KEYS },
+	{ HID_USB_DEVICE(USB_VENDOR_ID_PLANTRONICS,
+					 USB_DEVICE_ID_PLANTRONICS_BLACKWIRE_3215_SERIES),
+		.driver_data = PLT_QUIRK_DOUBLE_VOLUME_KEYS },
+	{ HID_USB_DEVICE(USB_VENDOR_ID_PLANTRONICS,
+					 USB_DEVICE_ID_PLANTRONICS_BLACKWIRE_3225_SERIES),
+		.driver_data = PLT_QUIRK_DOUBLE_VOLUME_KEYS },
 	{ HID_USB_DEVICE(USB_VENDOR_ID_PLANTRONICS, HID_ANY_ID) },
 	{ }
 };
-- 
GitLab


From 54f27dc53f1764986d417cfafe1013806deba668 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jos=C3=A9=20Exp=C3=B3sito?= <jose.exposito89@gmail.com>
Date: Mon, 28 Nov 2022 17:55:24 +0100
Subject: [PATCH 513/875] HID: sony: Fix unused function warning
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Compiling this driver without setting "CONFIG_SONY_FF" generates the
following warning:

	drivers/hid/hid-sony.c:2358:20: warning: unused function
	'sony_send_output_report' [-Wunused-function]
	static inline void sony_send_output_report(struct sony_sc *sc)
	                   ^
	1 warning generated.

Add the missing preprocessor check to fix it.

Signed-off-by: José Expósito <jose.exposito89@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
---
 drivers/hid/hid-sony.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/hid/hid-sony.c b/drivers/hid/hid-sony.c
index 03691cdcfb8e1..13125997ab5e3 100644
--- a/drivers/hid/hid-sony.c
+++ b/drivers/hid/hid-sony.c
@@ -2355,11 +2355,13 @@ static void motion_send_output_report(struct sony_sc *sc)
 	hid_hw_output_report(hdev, (u8 *)report, MOTION_REPORT_0x02_SIZE);
 }
 
+#ifdef CONFIG_SONY_FF
 static inline void sony_send_output_report(struct sony_sc *sc)
 {
 	if (sc->send_output_report)
 		sc->send_output_report(sc);
 }
+#endif
 
 static void sony_state_worker(struct work_struct *work)
 {
-- 
GitLab


From bfa87ac86ce9ff879c5ac49bf09c3999859a8968 Mon Sep 17 00:00:00 2001
From: Alessandro Carminati <acarmina@redhat.com>
Date: Tue, 22 Nov 2022 18:36:48 +0100
Subject: [PATCH 514/875] rv/monitors: Move monitor structure in rodata

It makes sense to move the important monitor structure into rodata to
prevent accidental structure modification.

Link: https://lkml.kernel.org/r/20221122173648.4732-1-acarmina@redhat.com

Signed-off-by: Alessandro Carminati <acarmina@redhat.com>
Acked-by: Daniel Bristot de Oliveira <bristot@kernel.org>
Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>
---
 kernel/trace/rv/monitors/wip/wip.h   | 2 +-
 kernel/trace/rv/monitors/wwnr/wwnr.h | 2 +-
 tools/verification/dot2/dot2c.py     | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/kernel/trace/rv/monitors/wip/wip.h b/kernel/trace/rv/monitors/wip/wip.h
index dacc37b62a2c5..2e373f2c65ed7 100644
--- a/kernel/trace/rv/monitors/wip/wip.h
+++ b/kernel/trace/rv/monitors/wip/wip.h
@@ -27,7 +27,7 @@ struct automaton_wip {
 	bool final_states[state_max_wip];
 };
 
-static struct automaton_wip automaton_wip = {
+static const struct automaton_wip automaton_wip = {
 	.state_names = {
 		"preemptive",
 		"non_preemptive"
diff --git a/kernel/trace/rv/monitors/wwnr/wwnr.h b/kernel/trace/rv/monitors/wwnr/wwnr.h
index 118e576b91b4b..d0d9c4b8121b5 100644
--- a/kernel/trace/rv/monitors/wwnr/wwnr.h
+++ b/kernel/trace/rv/monitors/wwnr/wwnr.h
@@ -27,7 +27,7 @@ struct automaton_wwnr {
 	bool final_states[state_max_wwnr];
 };
 
-static struct automaton_wwnr automaton_wwnr = {
+static const struct automaton_wwnr automaton_wwnr = {
 	.state_names = {
 		"not_running",
 		"running"
diff --git a/tools/verification/dot2/dot2c.py b/tools/verification/dot2/dot2c.py
index be8a364a469b9..87d8a1e1470c6 100644
--- a/tools/verification/dot2/dot2c.py
+++ b/tools/verification/dot2/dot2c.py
@@ -111,7 +111,7 @@ class Dot2c(Automata):
 
     def format_aut_init_header(self):
         buff = []
-        buff.append("static struct %s %s = {" % (self.struct_automaton_def, self.var_automaton_def))
+        buff.append("static const struct %s %s = {" % (self.struct_automaton_def, self.var_automaton_def))
         return buff
 
     def __get_string_vector_per_line_content(self, buff):
-- 
GitLab


From eeac18e2bff3e1f62f59059d34c37e75f350a119 Mon Sep 17 00:00:00 2001
From: Arnaldo Carvalho de Melo <acme@redhat.com>
Date: Tue, 20 Dec 2022 14:16:01 -0300
Subject: [PATCH 515/875] tools headers UAPI: Sync drm/i915_drm.h with the
 kernel sources

To pick up the changes in:

  bc7ed4d30815bc43 ("drm/i915/perf: Apply Wa_18013179988")
  81d5f7d91492aa3a ("drm/i915/perf: Add 32-bit OAG and OAR formats for DG2")
  8133a6daad4e7274 ("drm/i915: enable PS64 support for DG2")
  b76c14c8fb2af1e4 ("drm/i915/huc: better define HuC status getparam possible return values.")
  94dfc73e7cf4a31d ("treewide: uapi: Replace zero-length arrays with flexible-array members")

That doesn't add any ioctl, so no changes in tooling.

This silences this perf build warning:

  Warning: Kernel ABI header at 'tools/include/uapi/drm/i915_drm.h' differs from latest version at 'include/uapi/drm/i915_drm.h'
  diff -u tools/include/uapi/drm/i915_drm.h include/uapi/drm/i915_drm.h

Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Gustavo A. R. Silva <gustavoars@kernel.org>
Cc: Ian Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Link: https://lore.kernel.org/lkml/Y6HukoRaZh2R4j5U@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/include/uapi/drm/i915_drm.h | 62 ++++++++++++++++++-------------
 1 file changed, 36 insertions(+), 26 deletions(-)

diff --git a/tools/include/uapi/drm/i915_drm.h b/tools/include/uapi/drm/i915_drm.h
index 520ad2691a99d..8df261c5ab9b1 100644
--- a/tools/include/uapi/drm/i915_drm.h
+++ b/tools/include/uapi/drm/i915_drm.h
@@ -645,6 +645,22 @@ typedef struct drm_i915_irq_wait {
  */
 #define   I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP	(1ul << 5)
 
+/*
+ * Query the status of HuC load.
+ *
+ * The query can fail in the following scenarios with the listed error codes:
+ *  -ENODEV if HuC is not present on this platform,
+ *  -EOPNOTSUPP if HuC firmware usage is disabled,
+ *  -ENOPKG if HuC firmware fetch failed,
+ *  -ENOEXEC if HuC firmware is invalid or mismatched,
+ *  -ENOMEM if i915 failed to prepare the FW objects for transfer to the uC,
+ *  -EIO if the FW transfer or the FW authentication failed.
+ *
+ * If the IOCTL is successful, the returned parameter will be set to one of the
+ * following values:
+ *  * 0 if HuC firmware load is not complete,
+ *  * 1 if HuC firmware is authenticated and running.
+ */
 #define I915_PARAM_HUC_STATUS		 42
 
 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
@@ -749,6 +765,12 @@ typedef struct drm_i915_irq_wait {
 /* Query if the kernel supports the I915_USERPTR_PROBE flag. */
 #define I915_PARAM_HAS_USERPTR_PROBE 56
 
+/*
+ * Frequency of the timestamps in OA reports. This used to be the same as the CS
+ * timestamp frequency, but differs on some platforms.
+ */
+#define I915_PARAM_OA_TIMESTAMP_FREQUENCY 57
+
 /* Must be kept compact -- no holes and well documented */
 
 /**
@@ -2650,6 +2672,10 @@ enum drm_i915_oa_format {
 	I915_OA_FORMAT_A12_B8_C8,
 	I915_OA_FORMAT_A32u40_A4u32_B8_C8,
 
+	/* DG2 */
+	I915_OAR_FORMAT_A32u40_A4u32_B8_C8,
+	I915_OA_FORMAT_A24u40_A14u32_B8_C8,
+
 	I915_OA_FORMAT_MAX	    /* non-ABI */
 };
 
@@ -3493,27 +3519,13 @@ struct drm_i915_gem_create_ext {
 	 *
 	 * The (page-aligned) allocated size for the object will be returned.
 	 *
-	 * DG2 64K min page size implications:
-	 *
-	 * On discrete platforms, starting from DG2, we have to contend with GTT
-	 * page size restrictions when dealing with I915_MEMORY_CLASS_DEVICE
-	 * objects.  Specifically the hardware only supports 64K or larger GTT
-	 * page sizes for such memory. The kernel will already ensure that all
-	 * I915_MEMORY_CLASS_DEVICE memory is allocated using 64K or larger page
-	 * sizes underneath.
-	 *
-	 * Note that the returned size here will always reflect any required
-	 * rounding up done by the kernel, i.e 4K will now become 64K on devices
-	 * such as DG2. The kernel will always select the largest minimum
-	 * page-size for the set of possible placements as the value to use when
-	 * rounding up the @size.
-	 *
-	 * Special DG2 GTT address alignment requirement:
-	 *
-	 * The GTT alignment will also need to be at least 2M for such objects.
+	 * On platforms like DG2/ATS the kernel will always use 64K or larger
+	 * pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a
+	 * minimum of 64K GTT alignment for such objects.
 	 *
-	 * Note that due to how the hardware implements 64K GTT page support, we
-	 * have some further complications:
+	 * NOTE: Previously the ABI here required a minimum GTT alignment of 2M
+	 * on DG2/ATS, due to how the hardware implemented 64K GTT page support,
+	 * where we had the following complications:
 	 *
 	 *   1) The entire PDE (which covers a 2MB virtual address range), must
 	 *   contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same
@@ -3522,12 +3534,10 @@ struct drm_i915_gem_create_ext {
 	 *   2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM
 	 *   objects.
 	 *
-	 * To keep things simple for userland, we mandate that any GTT mappings
-	 * must be aligned to and rounded up to 2MB. The kernel will internally
-	 * pad them out to the next 2MB boundary. As this only wastes virtual
-	 * address space and avoids userland having to copy any needlessly
-	 * complicated PDE sharing scheme (coloring) and only affects DG2, this
-	 * is deemed to be a good compromise.
+	 * However on actual production HW this was completely changed to now
+	 * allow setting a TLB hint at the PTE level (see PS64), which is a lot
+	 * more flexible than the above. With this the 2M restriction was
+	 * dropped where we now only require 64K.
 	 */
 	__u64 size;
 
-- 
GitLab


From a66558dcb1079c198ab0f56896195a353dae4428 Mon Sep 17 00:00:00 2001
From: Arnaldo Carvalho de Melo <acme@redhat.com>
Date: Fri, 7 Aug 2020 08:45:47 -0300
Subject: [PATCH 516/875] tools arch x86: Sync the msr-index.h copy with the
 kernel sources

To pick up the changes in:

  97fa21f65c3eb5bb ("x86/resctrl: Move MSR defines into msr-index.h")
  7420ae3bb977b46e ("x86/intel_epb: Set Alder Lake N and Raptor Lake P normal EPB")

Addressing these tools/perf build warnings:

    diff -u tools/arch/x86/include/asm/msr-index.h arch/x86/include/asm/msr-index.h
    Warning: Kernel ABI header at 'tools/arch/x86/include/asm/msr-index.h' differs from latest version at 'arch/x86/include/asm/msr-index.h'

That makes the beautification scripts to pick some new entries:

  $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > before
  $ cp arch/x86/include/asm/msr-index.h tools/arch/x86/include/asm/msr-index.h
  $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > after
  $ diff -u before after
  --- before	2022-12-20 14:28:40.893794072 -0300
  +++ after	2022-12-20 14:28:54.831993914 -0300
  @@ -266,6 +266,7 @@
   	[0xc0000104 - x86_64_specific_MSRs_offset] = "AMD64_TSC_RATIO",
   	[0xc000010e - x86_64_specific_MSRs_offset] = "AMD64_LBR_SELECT",
   	[0xc000010f - x86_64_specific_MSRs_offset] = "AMD_DBG_EXTN_CFG",
  +	[0xc0000200 - x86_64_specific_MSRs_offset] = "IA32_MBA_BW_BASE",
   	[0xc0000300 - x86_64_specific_MSRs_offset] = "AMD64_PERF_CNTR_GLOBAL_STATUS",
   	[0xc0000301 - x86_64_specific_MSRs_offset] = "AMD64_PERF_CNTR_GLOBAL_CTL",
   	[0xc0000302 - x86_64_specific_MSRs_offset] = "AMD64_PERF_CNTR_GLOBAL_STATUS_CLR",
  $

Now one can trace systemwide asking to see backtraces to where that MSR
is being read/written, see this example with a previous update:

  # perf trace -e msr:*_msr/max-stack=32/ --filter="msr>=IA32_U_CET && msr<=IA32_INT_SSP_TAB"
  ^C#

If we use -v (verbose mode) we can see what it does behind the scenes:

  # perf trace -v -e msr:*_msr/max-stack=32/ --filter="msr>=IA32_U_CET && msr<=IA32_INT_SSP_TAB"
  Using CPUID AuthenticAMD-25-21-0
  0x6a0
  0x6a8
  New filter for msr:read_msr: (msr>=0x6a0 && msr<=0x6a8) && (common_pid != 597499 && common_pid != 3313)
  0x6a0
  0x6a8
  New filter for msr:write_msr: (msr>=0x6a0 && msr<=0x6a8) && (common_pid != 597499 && common_pid != 3313)
  mmap size 528384B
  ^C#

Example with a frequent msr:

  # perf trace -v -e msr:*_msr/max-stack=32/ --filter="msr==IA32_SPEC_CTRL" --max-events 2
  Using CPUID AuthenticAMD-25-21-0
  0x48
  New filter for msr:read_msr: (msr==0x48) && (common_pid != 2612129 && common_pid != 3841)
  0x48
  New filter for msr:write_msr: (msr==0x48) && (common_pid != 2612129 && common_pid != 3841)
  mmap size 528384B
  Looking at the vmlinux_path (8 entries long)
  symsrc__init: build id mismatch for vmlinux.
  Using /proc/kcore for kernel data
  Using /proc/kallsyms for symbols
     0.000 Timer/2525383 msr:write_msr(msr: IA32_SPEC_CTRL, val: 6)
                                       do_trace_write_msr ([kernel.kallsyms])
                                       do_trace_write_msr ([kernel.kallsyms])
                                       __switch_to_xtra ([kernel.kallsyms])
                                       __switch_to ([kernel.kallsyms])
                                       __schedule ([kernel.kallsyms])
                                       schedule ([kernel.kallsyms])
                                       futex_wait_queue_me ([kernel.kallsyms])
                                       futex_wait ([kernel.kallsyms])
                                       do_futex ([kernel.kallsyms])
                                       __x64_sys_futex ([kernel.kallsyms])
                                       do_syscall_64 ([kernel.kallsyms])
                                       entry_SYSCALL_64_after_hwframe ([kernel.kallsyms])
                                       __futex_abstimed_wait_common64 (/usr/lib64/libpthread-2.33.so)
     0.030 :0/0 msr:write_msr(msr: IA32_SPEC_CTRL, val: 2)
                                       do_trace_write_msr ([kernel.kallsyms])
                                       do_trace_write_msr ([kernel.kallsyms])
                                       __switch_to_xtra ([kernel.kallsyms])
                                       __switch_to ([kernel.kallsyms])
                                       __schedule ([kernel.kallsyms])
                                       schedule_idle ([kernel.kallsyms])
                                       do_idle ([kernel.kallsyms])
                                       cpu_startup_entry ([kernel.kallsyms])
                                       secondary_startup_64_no_verify ([kernel.kallsyms])
  #

Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Link: https://lore.kernel.org/lkml/Y6HyTOGRNvKfCVe4@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/arch/x86/include/asm/msr-index.h | 24 +++++++++++++++++-------
 1 file changed, 17 insertions(+), 7 deletions(-)

diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
index f17ade084720d..37ff47552bcb7 100644
--- a/tools/arch/x86/include/asm/msr-index.h
+++ b/tools/arch/x86/include/asm/msr-index.h
@@ -4,12 +4,7 @@
 
 #include <linux/bits.h>
 
-/*
- * CPU model specific register (MSR) numbers.
- *
- * Do not add new entries to this file unless the definitions are shared
- * between multiple compilation units.
- */
+/* CPU model specific register (MSR) numbers. */
 
 /* x86-64 specific MSRs */
 #define MSR_EFER		0xc0000080 /* extended feature register */
@@ -537,7 +532,7 @@
 #define MSR_AMD64_DC_CFG		0xc0011022
 
 #define MSR_AMD64_DE_CFG		0xc0011029
-#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT	1
+#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT	 1
 #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE	BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
 
 #define MSR_AMD64_BU_CFG2		0xc001102a
@@ -798,6 +793,7 @@
 #define ENERGY_PERF_BIAS_PERFORMANCE		0
 #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE	4
 #define ENERGY_PERF_BIAS_NORMAL			6
+#define ENERGY_PERF_BIAS_NORMAL_POWERSAVE	7
 #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE	8
 #define ENERGY_PERF_BIAS_POWERSAVE		15
 
@@ -1052,6 +1048,20 @@
 #define VMX_BASIC_MEM_TYPE_WB	6LLU
 #define VMX_BASIC_INOUT		0x0040000000000000LLU
 
+/* Resctrl MSRs: */
+/* - Intel: */
+#define MSR_IA32_L3_QOS_CFG		0xc81
+#define MSR_IA32_L2_QOS_CFG		0xc82
+#define MSR_IA32_QM_EVTSEL		0xc8d
+#define MSR_IA32_QM_CTR			0xc8e
+#define MSR_IA32_PQR_ASSOC		0xc8f
+#define MSR_IA32_L3_CBM_BASE		0xc90
+#define MSR_IA32_L2_CBM_BASE		0xd10
+#define MSR_IA32_MBA_THRTL_BASE		0xd50
+
+/* - AMD: */
+#define MSR_IA32_MBA_BW_BASE		0xc0000200
+
 /* MSR_IA32_VMX_MISC bits */
 #define MSR_IA32_VMX_MISC_INTEL_PT                 (1ULL << 14)
 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
-- 
GitLab


From 6d5edd15c982b4e3768919776422ba8f01388be3 Mon Sep 17 00:00:00 2001
From: Arnaldo Carvalho de Melo <acme@redhat.com>
Date: Wed, 8 Sep 2021 16:09:08 -0300
Subject: [PATCH 517/875] tools headers UAPI: Sync powerpc syscall table with
 the kernel sources

To pick the changes in these csets:

  ce883a2ba310cd7c ("powerpc/32: fix syscall wrappers with 64-bit arguments")

That doesn't cause any changes in the perf tools.

This table is used in tools perf to allow features as described in the
last update to this file.

This addresses this perf build warning:

  Warning: Kernel ABI header at 'tools/perf/arch/powerpc/entry/syscalls/syscall.tbl' differs from latest version at 'arch/powerpc/kernel/syscalls/syscall.tbl'
  diff -u tools/perf/arch/powerpc/entry/syscalls/syscall.tbl arch/powerpc/kernel/syscalls/syscall.tbl

Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Andreas Schwab <schwab@linux-m68k.org>
Cc: Ian Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/lkml/Y6H0C5plZ4V4aiPm@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/arch/powerpc/entry/syscalls/syscall.tbl | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/tools/perf/arch/powerpc/entry/syscalls/syscall.tbl b/tools/perf/arch/powerpc/entry/syscalls/syscall.tbl
index e9e0df4f9a61a..a0be127475b1f 100644
--- a/tools/perf/arch/powerpc/entry/syscalls/syscall.tbl
+++ b/tools/perf/arch/powerpc/entry/syscalls/syscall.tbl
@@ -394,8 +394,11 @@
 305	common	signalfd			sys_signalfd			compat_sys_signalfd
 306	common	timerfd_create			sys_timerfd_create
 307	common	eventfd				sys_eventfd
-308	common	sync_file_range2		sys_sync_file_range2		compat_sys_ppc_sync_file_range2
-309	nospu	fallocate			sys_fallocate			compat_sys_fallocate
+308	32	sync_file_range2		sys_ppc_sync_file_range2	compat_sys_ppc_sync_file_range2
+308	64	sync_file_range2		sys_sync_file_range2
+308	spu	sync_file_range2		sys_sync_file_range2
+309	32	fallocate			sys_ppc_fallocate		compat_sys_fallocate
+309	64	fallocate			sys_fallocate
 310	nospu	subpage_prot			sys_subpage_prot
 311	32	timerfd_settime			sys_timerfd_settime32
 311	64	timerfd_settime			sys_timerfd_settime
-- 
GitLab


From 29d48b87db64b6697ddad007548e51d032081c59 Mon Sep 17 00:00:00 2001
From: Philip Yang <Philip.Yang@amd.com>
Date: Wed, 14 Dec 2022 10:15:17 -0500
Subject: [PATCH 518/875] drm/amdkfd: Fix kfd_process_device_init_vm error
 handling

Should only destroy the ib_mem and let process cleanup worker to free
the outstanding BOs. Reset the pointer in pdd->qpd structure, to avoid
NULL pointer access in process destroy worker.

 BUG: kernel NULL pointer dereference, address: 0000000000000010
 Call Trace:
  amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel+0x46/0xb0 [amdgpu]
  kfd_process_device_destroy_cwsr_dgpu+0x40/0x70 [amdgpu]
  kfd_process_destroy_pdds+0x71/0x190 [amdgpu]
  kfd_process_wq_release+0x2a2/0x3b0 [amdgpu]
  process_one_work+0x2a1/0x600
  worker_thread+0x39/0x3d0

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_process.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index a26257171ab7c..6caa9dd57ff15 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -689,13 +689,13 @@ void kfd_process_destroy_wq(void)
 }
 
 static void kfd_process_free_gpuvm(struct kgd_mem *mem,
-			struct kfd_process_device *pdd, void *kptr)
+			struct kfd_process_device *pdd, void **kptr)
 {
 	struct kfd_dev *dev = pdd->dev;
 
-	if (kptr) {
+	if (kptr && *kptr) {
 		amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(mem);
-		kptr = NULL;
+		*kptr = NULL;
 	}
 
 	amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(dev->adev, mem, pdd->drm_priv);
@@ -795,7 +795,7 @@ static void kfd_process_device_destroy_ib_mem(struct kfd_process_device *pdd)
 	if (!qpd->ib_kaddr || !qpd->ib_base)
 		return;
 
-	kfd_process_free_gpuvm(qpd->ib_mem, pdd, qpd->ib_kaddr);
+	kfd_process_free_gpuvm(qpd->ib_mem, pdd, &qpd->ib_kaddr);
 }
 
 struct kfd_process *kfd_create_process(struct file *filep)
@@ -1277,7 +1277,7 @@ static void kfd_process_device_destroy_cwsr_dgpu(struct kfd_process_device *pdd)
 	if (!dev->cwsr_enabled || !qpd->cwsr_kaddr || !qpd->cwsr_base)
 		return;
 
-	kfd_process_free_gpuvm(qpd->cwsr_mem, pdd, qpd->cwsr_kaddr);
+	kfd_process_free_gpuvm(qpd->cwsr_mem, pdd, &qpd->cwsr_kaddr);
 }
 
 void kfd_process_set_trap_handler(struct qcm_process_device *qpd,
@@ -1598,8 +1598,8 @@ int kfd_process_device_init_vm(struct kfd_process_device *pdd,
 	return 0;
 
 err_init_cwsr:
+	kfd_process_device_destroy_ib_mem(pdd);
 err_reserve_ib_mem:
-	kfd_process_device_free_bos(pdd);
 	pdd->drm_priv = NULL;
 
 	return ret;
-- 
GitLab


From 1a799c4c190ea9f0e81028e3eb3037ed0ab17ff5 Mon Sep 17 00:00:00 2001
From: Philip Yang <Philip.Yang@amd.com>
Date: Tue, 13 Dec 2022 00:50:03 -0500
Subject: [PATCH 519/875] drm/amdkfd: Fix double release compute pasid

If kfd_process_device_init_vm returns failure after vm is converted to
compute vm and vm->pasid set to compute pasid, KFD will not take
pdd->drm_file reference. As a result, drm close file handler maybe
called to release the compute pasid before KFD process destroy worker to
release the same pasid and set vm->pasid to zero, this generates below
WARNING backtrace and NULL pointer access.

Add helper amdgpu_amdkfd_gpuvm_set_vm_pasid and call it at the last step
of kfd_process_device_init_vm, to ensure vm pasid is the original pasid
if acquiring vm failed or is the compute pasid with pdd->drm_file
reference taken to avoid double release same pasid.

 amdgpu: Failed to create process VM object
 ida_free called for id=32770 which is not allocated.
 WARNING: CPU: 57 PID: 72542 at ../lib/idr.c:522 ida_free+0x96/0x140
 RIP: 0010:ida_free+0x96/0x140
 Call Trace:
  amdgpu_pasid_free_delayed+0xe1/0x2a0 [amdgpu]
  amdgpu_driver_postclose_kms+0x2d8/0x340 [amdgpu]
  drm_file_free.part.13+0x216/0x270 [drm]
  drm_close_helper.isra.14+0x60/0x70 [drm]
  drm_release+0x6e/0xf0 [drm]
  __fput+0xcc/0x280
  ____fput+0xe/0x20
  task_work_run+0x96/0xc0
  do_exit+0x3d0/0xc10

 BUG: kernel NULL pointer dereference, address: 0000000000000000
 RIP: 0010:ida_free+0x76/0x140
 Call Trace:
  amdgpu_pasid_free_delayed+0xe1/0x2a0 [amdgpu]
  amdgpu_driver_postclose_kms+0x2d8/0x340 [amdgpu]
  drm_file_free.part.13+0x216/0x270 [drm]
  drm_close_helper.isra.14+0x60/0x70 [drm]
  drm_release+0x6e/0xf0 [drm]
  __fput+0xcc/0x280
  ____fput+0xe/0x20
  task_work_run+0x96/0xc0
  do_exit+0x3d0/0xc10

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h    |  4 +-
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 39 +++++++++++++------
 drivers/gpu/drm/amd/amdkfd/kfd_process.c      | 12 ++++--
 3 files changed, 40 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 589939631ed46..0040deaf8a83a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -270,8 +270,10 @@ int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_
 	(&((struct amdgpu_fpriv *)					\
 		((struct drm_file *)(drm_priv))->driver_priv)->vm)
 
+int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev,
+				     struct file *filp, u32 pasid);
 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
-					struct file *filp, u32 pasid,
+					struct file *filp,
 					void **process_info,
 					struct dma_fence **ef);
 void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 0a854bb8b47e8..b15091d8310d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1429,10 +1429,9 @@ static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo)
 	amdgpu_bo_unreserve(bo);
 }
 
-int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
-					   struct file *filp, u32 pasid,
-					   void **process_info,
-					   struct dma_fence **ef)
+int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev,
+				     struct file *filp, u32 pasid)
+
 {
 	struct amdgpu_fpriv *drv_priv;
 	struct amdgpu_vm *avm;
@@ -1443,10 +1442,6 @@ int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
 		return ret;
 	avm = &drv_priv->vm;
 
-	/* Already a compute VM? */
-	if (avm->process_info)
-		return -EINVAL;
-
 	/* Free the original amdgpu allocated pasid,
 	 * will be replaced with kfd allocated pasid.
 	 */
@@ -1455,14 +1450,36 @@ int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
 		amdgpu_vm_set_pasid(adev, avm, 0);
 	}
 
-	/* Convert VM into a compute VM */
-	ret = amdgpu_vm_make_compute(adev, avm);
+	ret = amdgpu_vm_set_pasid(adev, avm, pasid);
 	if (ret)
 		return ret;
 
-	ret = amdgpu_vm_set_pasid(adev, avm, pasid);
+	return 0;
+}
+
+int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
+					   struct file *filp,
+					   void **process_info,
+					   struct dma_fence **ef)
+{
+	struct amdgpu_fpriv *drv_priv;
+	struct amdgpu_vm *avm;
+	int ret;
+
+	ret = amdgpu_file_to_fpriv(filp, &drv_priv);
 	if (ret)
 		return ret;
+	avm = &drv_priv->vm;
+
+	/* Already a compute VM? */
+	if (avm->process_info)
+		return -EINVAL;
+
+	/* Convert VM into a compute VM */
+	ret = amdgpu_vm_make_compute(adev, avm);
+	if (ret)
+		return ret;
+
 	/* Initialize KFD part of the VM and process info */
 	ret = init_kfd_vm(avm, process_info, ef);
 	if (ret)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 6caa9dd57ff15..51b1683ac5c1e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -1576,9 +1576,9 @@ int kfd_process_device_init_vm(struct kfd_process_device *pdd,
 	p = pdd->process;
 	dev = pdd->dev;
 
-	ret = amdgpu_amdkfd_gpuvm_acquire_process_vm(
-		dev->adev, drm_file, p->pasid,
-		&p->kgd_process_info, &p->ef);
+	ret = amdgpu_amdkfd_gpuvm_acquire_process_vm(dev->adev, drm_file,
+						     &p->kgd_process_info,
+						     &p->ef);
 	if (ret) {
 		pr_err("Failed to create process VM object\n");
 		return ret;
@@ -1593,10 +1593,16 @@ int kfd_process_device_init_vm(struct kfd_process_device *pdd,
 	if (ret)
 		goto err_init_cwsr;
 
+	ret = amdgpu_amdkfd_gpuvm_set_vm_pasid(dev->adev, drm_file, p->pasid);
+	if (ret)
+		goto err_set_pasid;
+
 	pdd->drm_file = drm_file;
 
 	return 0;
 
+err_set_pasid:
+	kfd_process_device_destroy_cwsr_dgpu(pdd);
 err_init_cwsr:
 	kfd_process_device_destroy_ib_mem(pdd);
 err_reserve_ib_mem:
-- 
GitLab


From d118b18fb1da02b41df2da78cb2794b3638d89cd Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Thu, 15 Dec 2022 17:36:31 +0100
Subject: [PATCH 520/875] drm/amd/pm: avoid large variable on kernel stack

The activity_monitor_external[] array is too big to fit on the
kernel stack, resulting in this warning with clang:

drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_7_ppt.c:1438:12: error: stack frame size (1040) exceeds limit (1024) in 'smu_v13_0_7_get_power_profile_mode' [-Werror,-Wframe-larger-than]

Use dynamic allocation instead. It should also be possible to
have single element here instead of the array, but this seems
easier.

v2: fix up argument to sizeof() (Alex)

Fixes: 334682ae8151 ("drm/amd/pm: enable workload type change on smu_v13_0_7")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  | 21 ++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index ab1c004606be1..07e3dc18c8b83 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -1440,7 +1440,7 @@ static int smu_v13_0_7_get_power_limit(struct smu_context *smu,
 
 static int smu_v13_0_7_get_power_profile_mode(struct smu_context *smu, char *buf)
 {
-	DpmActivityMonitorCoeffIntExternal_t activity_monitor_external[PP_SMC_POWER_PROFILE_COUNT];
+	DpmActivityMonitorCoeffIntExternal_t *activity_monitor_external;
 	uint32_t i, j, size = 0;
 	int16_t workload_type = 0;
 	int result = 0;
@@ -1448,6 +1448,12 @@ static int smu_v13_0_7_get_power_profile_mode(struct smu_context *smu, char *buf
 	if (!buf)
 		return -EINVAL;
 
+	activity_monitor_external = kcalloc(PP_SMC_POWER_PROFILE_COUNT,
+					    sizeof(*activity_monitor_external),
+					    GFP_KERNEL);
+	if (!activity_monitor_external)
+		return -ENOMEM;
+
 	size += sysfs_emit_at(buf, size, "                              ");
 	for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++)
 		size += sysfs_emit_at(buf, size, "%-14s%s", amdgpu_pp_profile_name[i],
@@ -1460,15 +1466,17 @@ static int smu_v13_0_7_get_power_profile_mode(struct smu_context *smu, char *buf
 		workload_type = smu_cmn_to_asic_specific_index(smu,
 							       CMN2ASIC_MAPPING_WORKLOAD,
 							       i);
-		if (workload_type < 0)
-			return -EINVAL;
+		if (workload_type < 0) {
+			result = -EINVAL;
+			goto out;
+		}
 
 		result = smu_cmn_update_table(smu,
 					  SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
 					  (void *)(&activity_monitor_external[i]), false);
 		if (result) {
 			dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
-			return result;
+			goto out;
 		}
 	}
 
@@ -1496,7 +1504,10 @@ do {													\
 	PRINT_DPM_MONITOR(Fclk_BoosterFreq);
 #undef PRINT_DPM_MONITOR
 
-	return size;
+	result = size;
+out:
+	kfree(activity_monitor_external);
+	return result;
 }
 
 static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
-- 
GitLab


From afa6646b1c5d3affd541f76bd7476e4b835a9174 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Fri, 16 Dec 2022 11:42:20 -0500
Subject: [PATCH 521/875] drm/amdgpu: skip MES for S0ix as well since it's part
 of GFX

It's also part of gfxoff.

Cc: stable@vger.kernel.org # 6.0, 6.1
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 64660a41d53ce..afe6af9c01385 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3016,14 +3016,15 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
 			continue;
 		}
 
-		/* skip suspend of gfx and psp for S0ix
+		/* skip suspend of gfx/mes and psp for S0ix
 		 * gfx is in gfxoff state, so on resume it will exit gfxoff just
 		 * like at runtime. PSP is also part of the always on hardware
 		 * so no need to suspend it.
 		 */
 		if (adev->in_s0ix &&
 		    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP ||
-		     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX))
+		     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
+		     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_MES))
 			continue;
 
 		/* XXX handle errors */
-- 
GitLab


From b235e5b51f7d557cf10cbb1245b6cdeb341e1e2b Mon Sep 17 00:00:00 2001
From: Arnaldo Carvalho de Melo <acme@redhat.com>
Date: Sun, 9 May 2021 09:39:02 -0300
Subject: [PATCH 522/875] tools headers UAPI: Sync linux/kvm.h with the kernel
 sources
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

To pick the changes in:

  86bdf3ebcfe1ded0 ("KVM: Support dirty ring in conjunction with bitmap")

That just rebuilds perf, as these patches don't add any new KVM ioctl to
be harvested for the the 'perf trace' ioctl syscall argument
beautifiers.

This is also by now used by tools/testing/selftests/kvm/, a simple test
build didn't succeed, but for another reason:

  lib/kvm_util.c: In function ‘vm_enable_dirty_ring’:
  lib/kvm_util.c:125:30: error: ‘KVM_CAP_DIRTY_LOG_RING_ACQ_REL’ undeclared (first use in this function); did you mean ‘KVM_CAP_DIRTY_LOG_RING’?
    125 |         if (vm_check_cap(vm, KVM_CAP_DIRTY_LOG_RING_ACQ_REL))
        |                              ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
        |                              KVM_CAP_DIRTY_LOG_RING

I'll send a separate patch for that.

This silences this perf build warning:

  Warning: Kernel ABI header at 'tools/include/uapi/linux/kvm.h' differs from latest version at 'include/uapi/linux/kvm.h'
  diff -u tools/include/uapi/linux/kvm.h include/uapi/linux/kvm.h

Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Gavin Shan <gshan@redhat.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Link: http://lore.kernel.org/lkml/Y6H3b1Q4Msjy5Yz3@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/include/uapi/linux/kvm.h | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/tools/include/uapi/linux/kvm.h b/tools/include/uapi/linux/kvm.h
index 21d6d29502e48..20522d4ba1e0d 100644
--- a/tools/include/uapi/linux/kvm.h
+++ b/tools/include/uapi/linux/kvm.h
@@ -98,7 +98,7 @@ struct kvm_userspace_memory_region {
 /*
  * The bit 0 ~ bit 15 of kvm_userspace_memory_region::flags are visible for
  * userspace, other bits are reserved for kvm internal use which are defined
- *in include/linux/kvm_host.h.
+ * in include/linux/kvm_host.h.
  */
 #define KVM_MEM_LOG_DIRTY_PAGES	(1UL << 0)
 #define KVM_MEM_READONLY	(1UL << 1)
@@ -477,6 +477,9 @@ struct kvm_run {
 #define KVM_MSR_EXIT_REASON_INVAL	(1 << 0)
 #define KVM_MSR_EXIT_REASON_UNKNOWN	(1 << 1)
 #define KVM_MSR_EXIT_REASON_FILTER	(1 << 2)
+#define KVM_MSR_EXIT_REASON_VALID_MASK	(KVM_MSR_EXIT_REASON_INVAL   |	\
+					 KVM_MSR_EXIT_REASON_UNKNOWN |	\
+					 KVM_MSR_EXIT_REASON_FILTER)
 			__u32 reason; /* kernel -> user */
 			__u32 index; /* kernel -> user */
 			__u64 data; /* kernel <-> user */
@@ -1170,6 +1173,8 @@ struct kvm_ppc_resize_hpt {
 #define KVM_CAP_S390_ZPCI_OP 221
 #define KVM_CAP_S390_CPU_TOPOLOGY 222
 #define KVM_CAP_DIRTY_LOG_RING_ACQ_REL 223
+#define KVM_CAP_S390_PROTECTED_ASYNC_DISABLE 224
+#define KVM_CAP_DIRTY_LOG_RING_WITH_BITMAP 225
 
 #ifdef KVM_CAP_IRQ_ROUTING
 
@@ -1259,6 +1264,7 @@ struct kvm_x86_mce {
 #define KVM_XEN_HVM_CONFIG_RUNSTATE		(1 << 3)
 #define KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL	(1 << 4)
 #define KVM_XEN_HVM_CONFIG_EVTCHN_SEND		(1 << 5)
+#define KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG	(1 << 6)
 
 struct kvm_xen_hvm_config {
 	__u32 flags;
@@ -1726,6 +1732,8 @@ enum pv_cmd_id {
 	KVM_PV_UNSHARE_ALL,
 	KVM_PV_INFO,
 	KVM_PV_DUMP,
+	KVM_PV_ASYNC_CLEANUP_PREPARE,
+	KVM_PV_ASYNC_CLEANUP_PERFORM,
 };
 
 struct kvm_pv_cmd {
@@ -1756,6 +1764,7 @@ struct kvm_xen_hvm_attr {
 	union {
 		__u8 long_mode;
 		__u8 vector;
+		__u8 runstate_update_flag;
 		struct {
 			__u64 gfn;
 		} shared_info;
@@ -1796,6 +1805,8 @@ struct kvm_xen_hvm_attr {
 /* Available with KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_EVTCHN_SEND */
 #define KVM_XEN_ATTR_TYPE_EVTCHN		0x3
 #define KVM_XEN_ATTR_TYPE_XEN_VERSION		0x4
+/* Available with KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG */
+#define KVM_XEN_ATTR_TYPE_RUNSTATE_UPDATE_FLAG	0x5
 
 /* Per-vCPU Xen attributes */
 #define KVM_XEN_VCPU_GET_ATTR	_IOWR(KVMIO, 0xca, struct kvm_xen_vcpu_attr)
-- 
GitLab


From 188ac720d364035008a54d249cf47b4cc100f819 Mon Sep 17 00:00:00 2001
From: Yang Jihong <yangjihong1@huawei.com>
Date: Tue, 20 Dec 2022 11:57:00 +0800
Subject: [PATCH 523/875] perf debug: Set debug_peo_args and redirect_to_stderr
 variable to correct values in perf_quiet_option()

When perf uses quiet mode, perf_quiet_option() sets the 'debug_peo_args'
variable to -1, and display_attr() incorrectly determines the value of
'debug_peo_args'.  As a result, unexpected information is displayed.

Before:

  # perf record --quiet -- ls > /dev/null
  ------------------------------------------------------------
  perf_event_attr:
    size                             128
    { sample_period, sample_freq }   4000
    sample_type                      IP|TID|TIME|PERIOD
    read_format                      ID|LOST
    disabled                         1
    inherit                          1
    mmap                             1
    comm                             1
    freq                             1
    enable_on_exec                   1
    task                             1
    precise_ip                       3
    sample_id_all                    1
    exclude_guest                    1
    mmap2                            1
    comm_exec                        1
    ksymbol                          1
    bpf_event                        1
  ------------------------------------------------------------
  ...

After:
  # perf record --quiet -- ls > /dev/null
  #

redirect_to_stderr is a similar problem.

Fixes: f78eaef0e0493f60 ("perf tools: Allow to force redirect pr_debug to stderr.")
Fixes: ccd26741f5e6bdf2 ("perf tool: Provide an option to print perf_event_open args and return value")
Suggested-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Yang Jihong <yangjihong1@huawei.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Carsten Haitzler <carsten.haitzler@arm.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: martin.lau@kernel.org
Cc: Masami Hiramatsu <mhiramat@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@amd.com>
Cc: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
Link: https://lore.kernel.org/r/20221220035702.188413-2-yangjihong1@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/debug.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/tools/perf/util/debug.c b/tools/perf/util/debug.c
index 65e6c22f38e4f..190e818a07176 100644
--- a/tools/perf/util/debug.c
+++ b/tools/perf/util/debug.c
@@ -241,6 +241,10 @@ int perf_quiet_option(void)
 		opt++;
 	}
 
+	/* For debug variables that are used as bool types, set to 0. */
+	redirect_to_stderr = 0;
+	debug_peo_args = 0;
+
 	return 0;
 }
 
-- 
GitLab


From 7c0a6144f9a6a53b1cf2f78f09ca35d59d267f1e Mon Sep 17 00:00:00 2001
From: Yang Jihong <yangjihong1@huawei.com>
Date: Tue, 20 Dec 2022 11:57:01 +0800
Subject: [PATCH 524/875] perf tools: Fix usage of the verbose variable

The data type of the verbose variable is integer and can be negative,
replace improperly used cases in a unified manner:
 1. if (verbose)        => if (verbose > 0)
 2. if (!verbose)       => if (verbose <= 0)
 3. if (XX && verbose)  => if (XX && verbose > 0)
 4. if (XX && !verbose) => if (XX && verbose <= 0)

Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Yang Jihong <yangjihong1@huawei.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Carsten Haitzler <carsten.haitzler@arm.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Martin KaFai Lau <martin.lau@kernel.org>
Cc: Masami Hiramatsu <mhiramat@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@amd.com>
Link: https://lore.kernel.org/r/20221220035702.188413-3-yangjihong1@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/builtin-lock.c                   | 6 +++---
 tools/perf/builtin-record.c                 | 4 ++--
 tools/perf/builtin-script.c                 | 2 +-
 tools/perf/builtin-stat.c                   | 4 ++--
 tools/perf/dlfilters/dlfilter-test-api-v0.c | 2 +-
 tools/perf/tests/builtin-test.c             | 2 +-
 tools/perf/tests/dlfilter-test.c            | 2 +-
 tools/perf/util/bpf_lock_contention.c       | 2 +-
 tools/perf/util/dlfilter.c                  | 2 +-
 9 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/tools/perf/builtin-lock.c b/tools/perf/builtin-lock.c
index 25c0a5e5051f2..6276dfbc94a1f 100644
--- a/tools/perf/builtin-lock.c
+++ b/tools/perf/builtin-lock.c
@@ -1029,7 +1029,7 @@ static int report_lock_contention_begin_event(struct evsel *evsel,
 		if (!ls)
 			return -ENOMEM;
 
-		if (aggr_mode == LOCK_AGGR_CALLER && verbose) {
+		if (aggr_mode == LOCK_AGGR_CALLER && verbose > 0) {
 			ls->callstack = get_callstack(sample, max_stack_depth);
 			if (ls->callstack == NULL)
 				return -ENOMEM;
@@ -1214,7 +1214,7 @@ static void print_bad_events(int bad, int total)
 	for (i = 0; i < BROKEN_MAX; i++)
 		broken += bad_hist[i];
 
-	if (quiet || (broken == 0 && !verbose))
+	if (quiet || (broken == 0 && verbose <= 0))
 		return;
 
 	pr_info("\n=== output for debug===\n\n");
@@ -1529,7 +1529,7 @@ static void print_contention_result(struct lock_contention *con)
 			break;
 		}
 
-		if (aggr_mode == LOCK_AGGR_CALLER && verbose) {
+		if (aggr_mode == LOCK_AGGR_CALLER && verbose > 0) {
 			struct map *kmap;
 			struct symbol *sym;
 			char buf[128];
diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c
index 8ecffa696ce32..29dcd454b8e21 100644
--- a/tools/perf/builtin-record.c
+++ b/tools/perf/builtin-record.c
@@ -3629,7 +3629,7 @@ static int record__init_thread_cpu_masks(struct record *rec, struct perf_cpu_map
 	for (t = 0; t < rec->nr_threads; t++) {
 		__set_bit(perf_cpu_map__cpu(cpus, t).cpu, rec->thread_masks[t].maps.bits);
 		__set_bit(perf_cpu_map__cpu(cpus, t).cpu, rec->thread_masks[t].affinity.bits);
-		if (verbose) {
+		if (verbose > 0) {
 			pr_debug("thread_masks[%d]: ", t);
 			mmap_cpu_mask__scnprintf(&rec->thread_masks[t].maps, "maps");
 			pr_debug("thread_masks[%d]: ", t);
@@ -3726,7 +3726,7 @@ static int record__init_thread_masks_spec(struct record *rec, struct perf_cpu_ma
 		}
 		rec->thread_masks = thread_masks;
 		rec->thread_masks[t] = thread_mask;
-		if (verbose) {
+		if (verbose > 0) {
 			pr_debug("thread_masks[%d]: ", t);
 			mmap_cpu_mask__scnprintf(&rec->thread_masks[t].maps, "maps");
 			pr_debug("thread_masks[%d]: ", t);
diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c
index 88888fb885c82..69394ac0a20dc 100644
--- a/tools/perf/builtin-script.c
+++ b/tools/perf/builtin-script.c
@@ -2233,7 +2233,7 @@ static void process_event(struct perf_script *script,
 	if (PRINT_FIELD(METRIC))
 		perf_sample__fprint_metric(script, thread, evsel, sample, fp);
 
-	if (verbose)
+	if (verbose > 0)
 		fflush(fp);
 }
 
diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c
index bf640abc9c41f..9f3e4b2575165 100644
--- a/tools/perf/builtin-stat.c
+++ b/tools/perf/builtin-stat.c
@@ -266,7 +266,7 @@ static void evlist__check_cpu_maps(struct evlist *evlist)
 		evsel__group_desc(leader, buf, sizeof(buf));
 		pr_warning("  %s\n", buf);
 
-		if (verbose) {
+		if (verbose > 0) {
 			cpu_map__snprint(leader->core.cpus, buf, sizeof(buf));
 			pr_warning("     %s: %s\n", leader->name, buf);
 			cpu_map__snprint(evsel->core.cpus, buf, sizeof(buf));
@@ -2493,7 +2493,7 @@ int cmd_stat(int argc, const char **argv)
 		if (iostat_mode == IOSTAT_LIST) {
 			iostat_list(evsel_list, &stat_config);
 			goto out;
-		} else if (verbose)
+		} else if (verbose > 0)
 			iostat_list(evsel_list, &stat_config);
 		if (iostat_mode == IOSTAT_RUN && !target__has_cpu(&target))
 			target.system_wide = true;
diff --git a/tools/perf/dlfilters/dlfilter-test-api-v0.c b/tools/perf/dlfilters/dlfilter-test-api-v0.c
index b17eb52a0694d..b1f51efd67d63 100644
--- a/tools/perf/dlfilters/dlfilter-test-api-v0.c
+++ b/tools/perf/dlfilters/dlfilter-test-api-v0.c
@@ -119,7 +119,7 @@ struct perf_dlfilter_fns perf_dlfilter_fns;
 static int verbose;
 
 #define pr_debug(fmt, ...) do { \
-		if (verbose) \
+		if (verbose > 0) \
 			fprintf(stderr, fmt, ##__VA_ARGS__); \
 	} while (0)
 
diff --git a/tools/perf/tests/builtin-test.c b/tools/perf/tests/builtin-test.c
index f6c16ad8ed506..cfa61493c7501 100644
--- a/tools/perf/tests/builtin-test.c
+++ b/tools/perf/tests/builtin-test.c
@@ -305,7 +305,7 @@ static int shell_test__run(struct test_suite *test, int subdir __maybe_unused)
 
 	path__join(script, sizeof(script) - 3, st->dir, st->file);
 
-	if (verbose)
+	if (verbose > 0)
 		strncat(script, " -v", sizeof(script) - strlen(script) - 1);
 
 	err = system(script);
diff --git a/tools/perf/tests/dlfilter-test.c b/tools/perf/tests/dlfilter-test.c
index 99aa72e425e4d..086fd2179e41f 100644
--- a/tools/perf/tests/dlfilter-test.c
+++ b/tools/perf/tests/dlfilter-test.c
@@ -88,7 +88,7 @@ static __printf(1, 2) int system_cmd(const char *fmt, ...)
 	if (ret <= 0 || ret >= MAXCMD)
 		return -1;
 
-	if (!verbose)
+	if (verbose <= 0)
 		strcat(cmd, REDIRECT_TO_DEV_NULL);
 
 	pr_debug("Command: %s\n", cmd);
diff --git a/tools/perf/util/bpf_lock_contention.c b/tools/perf/util/bpf_lock_contention.c
index 8e1b791dc58f1..df8dbb5191b43 100644
--- a/tools/perf/util/bpf_lock_contention.c
+++ b/tools/perf/util/bpf_lock_contention.c
@@ -215,7 +215,7 @@ int lock_contention_read(struct lock_contention *con)
 			break;
 		}
 
-		if (verbose) {
+		if (verbose > 0) {
 			st->callstack = memdup(stack_trace, stack_size);
 			if (st->callstack == NULL)
 				break;
diff --git a/tools/perf/util/dlfilter.c b/tools/perf/util/dlfilter.c
index 54e4d4495e00d..37beb75302888 100644
--- a/tools/perf/util/dlfilter.c
+++ b/tools/perf/util/dlfilter.c
@@ -579,7 +579,7 @@ static void list_filters(const char *dirname)
 		if (!get_filter_desc(dirname, entry->d_name, &desc, &long_desc))
 			continue;
 		printf("  %-36s %s\n", entry->d_name, desc ? desc : "");
-		if (verbose) {
+		if (verbose > 0) {
 			char *p = long_desc;
 			char *line;
 
-- 
GitLab


From 8b269b75551227796c1ddac2dbdb2ba504158c61 Mon Sep 17 00:00:00 2001
From: Yang Jihong <yangjihong1@huawei.com>
Date: Tue, 20 Dec 2022 11:57:02 +0800
Subject: [PATCH 525/875] perf probe: Check -v and -q options in the right
 place

Check the -q and -v options first to return earlier on error.

Before:

  # perf probe -q -v test
  probe-definition(0): test
  symbol:test file:(null) line:0 offset:0 return:0 lazy:(null)
  0 arguments
    Error: -v and -q are exclusive.

After:

  # perf probe -q -v test
    Error: -v and -q are exclusive.

Fixes: 5e17b28f1e246b98 ("perf probe: Add --quiet option to suppress output result message")
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Yang Jihong <yangjihong1@huawei.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Carsten Haitzler <carsten.haitzler@arm.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Martin KaFai Lau <martin.lau@kernel.org>
Cc: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
Cc: Masami Hiramatsu <mhiramat@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@amd.com>
Link: https://lore.kernel.org/r/20221220035702.188413-4-yangjihong1@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/builtin-probe.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/tools/perf/builtin-probe.c b/tools/perf/builtin-probe.c
index 2ae50fc9e5976..ed73d0b89ca2d 100644
--- a/tools/perf/builtin-probe.c
+++ b/tools/perf/builtin-probe.c
@@ -612,6 +612,15 @@ __cmd_probe(int argc, const char **argv)
 
 	argc = parse_options(argc, argv, options, probe_usage,
 			     PARSE_OPT_STOP_AT_NON_OPTION);
+
+	if (quiet) {
+		if (verbose != 0) {
+			pr_err("  Error: -v and -q are exclusive.\n");
+			return -EINVAL;
+		}
+		verbose = -1;
+	}
+
 	if (argc > 0) {
 		if (strcmp(argv[0], "-") == 0) {
 			usage_with_options_msg(probe_usage, options,
@@ -633,14 +642,6 @@ __cmd_probe(int argc, const char **argv)
 	if (ret)
 		return ret;
 
-	if (quiet) {
-		if (verbose != 0) {
-			pr_err("  Error: -v and -q are exclusive.\n");
-			return -EINVAL;
-		}
-		verbose = -1;
-	}
-
 	if (probe_conf.max_probes == 0)
 		probe_conf.max_probes = MAX_PROBES;
 
-- 
GitLab


From 59119c09ae748c6398e44925346ed9e3fa2b4679 Mon Sep 17 00:00:00 2001
From: Namhyung Kim <namhyung@kernel.org>
Date: Mon, 19 Dec 2022 12:17:27 -0800
Subject: [PATCH 526/875] perf lock contention: Factor out lock_type_table

Move it out of get_type_str() so that we can reuse the table for others
later.

Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Blake Jones <blakejones@google.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Song Liu <song@kernel.org>
Cc: bpf@vger.kernel.org
Link: https://lore.kernel.org/r/20221219201732.460111-2-namhyung@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/builtin-lock.c | 48 +++++++++++++++++++--------------------
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/tools/perf/builtin-lock.c b/tools/perf/builtin-lock.c
index 6276dfbc94a1f..311f83bc5ddb8 100644
--- a/tools/perf/builtin-lock.c
+++ b/tools/perf/builtin-lock.c
@@ -1437,30 +1437,30 @@ static void sort_result(void)
 	}
 }
 
-static const char *get_type_str(struct lock_stat *st)
-{
-	static const struct {
-		unsigned int flags;
-		const char *name;
-	} table[] = {
-		{ 0,				"semaphore" },
-		{ LCB_F_SPIN,			"spinlock" },
-		{ LCB_F_SPIN | LCB_F_READ,	"rwlock:R" },
-		{ LCB_F_SPIN | LCB_F_WRITE,	"rwlock:W"},
-		{ LCB_F_READ,			"rwsem:R" },
-		{ LCB_F_WRITE,			"rwsem:W" },
-		{ LCB_F_RT,			"rtmutex" },
-		{ LCB_F_RT | LCB_F_READ,	"rwlock-rt:R" },
-		{ LCB_F_RT | LCB_F_WRITE,	"rwlock-rt:W"},
-		{ LCB_F_PERCPU | LCB_F_READ,	"pcpu-sem:R" },
-		{ LCB_F_PERCPU | LCB_F_WRITE,	"pcpu-sem:W" },
-		{ LCB_F_MUTEX,			"mutex" },
-		{ LCB_F_MUTEX | LCB_F_SPIN,	"mutex" },
-	};
+static const struct {
+	unsigned int flags;
+	const char *name;
+} lock_type_table[] = {
+	{ 0,				"semaphore" },
+	{ LCB_F_SPIN,			"spinlock" },
+	{ LCB_F_SPIN | LCB_F_READ,	"rwlock:R" },
+	{ LCB_F_SPIN | LCB_F_WRITE,	"rwlock:W"},
+	{ LCB_F_READ,			"rwsem:R" },
+	{ LCB_F_WRITE,			"rwsem:W" },
+	{ LCB_F_RT,			"rtmutex" },
+	{ LCB_F_RT | LCB_F_READ,	"rwlock-rt:R" },
+	{ LCB_F_RT | LCB_F_WRITE,	"rwlock-rt:W"},
+	{ LCB_F_PERCPU | LCB_F_READ,	"pcpu-sem:R" },
+	{ LCB_F_PERCPU | LCB_F_WRITE,	"pcpu-sem:W" },
+	{ LCB_F_MUTEX,			"mutex" },
+	{ LCB_F_MUTEX | LCB_F_SPIN,	"mutex" },
+};
 
-	for (unsigned int i = 0; i < ARRAY_SIZE(table); i++) {
-		if (table[i].flags == st->flags)
-			return table[i].name;
+static const char *get_type_str(unsigned int flags)
+{
+	for (unsigned int i = 0; i < ARRAY_SIZE(lock_type_table); i++) {
+		if (lock_type_table[i].flags == flags)
+			return lock_type_table[i].name;
 	}
 	return "unknown";
 }
@@ -1514,7 +1514,7 @@ static void print_contention_result(struct lock_contention *con)
 
 		switch (aggr_mode) {
 		case LOCK_AGGR_CALLER:
-			pr_info("  %10s   %s\n", get_type_str(st), st->name);
+			pr_info("  %10s   %s\n", get_type_str(st->flags), st->name);
 			break;
 		case LOCK_AGGR_TASK:
 			pid = st->addr;
-- 
GitLab


From 272b981416f8be0180c4d8066f90635fa7c1c501 Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Thu, 15 Dec 2022 13:38:46 +0800
Subject: [PATCH 527/875] drm/amd/pm: bump SMU13.0.0 driver_if header to
 version 0x34

To fit the latest PMFW and suppress the warning emerged on driver loading.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.0, 6.1
---
 .../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h  | 2 +-
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h                    | 1 +
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c                  | 2 ++
 3 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
index b76f0f7e42998..d6b964cf73bd1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
@@ -522,9 +522,9 @@ typedef enum  {
   TEMP_HOTSPOT_M,
   TEMP_MEM,
   TEMP_VR_GFX,
+  TEMP_VR_SOC,
   TEMP_VR_MEM0,
   TEMP_VR_MEM1,
-  TEMP_VR_SOC,
   TEMP_VR_U,
   TEMP_LIQUID0,
   TEMP_LIQUID1,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index ea29ac6a80e69..e8c6febb8b64e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -28,6 +28,7 @@
 #define SMU13_DRIVER_IF_VERSION_INV 0xFFFFFFFF
 #define SMU13_DRIVER_IF_VERSION_YELLOW_CARP 0x04
 #define SMU13_DRIVER_IF_VERSION_ALDE 0x08
+#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_0 0x34
 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x07
 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04
 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_10 0x32
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index e3a80ac987df1..e54b760b875bf 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -290,6 +290,8 @@ int smu_v13_0_check_fw_version(struct smu_context *smu)
 		smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
 		break;
 	case IP_VERSION(13, 0, 0):
+		smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_0;
+		break;
 	case IP_VERSION(13, 0, 10):
 		smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_10;
 		break;
-- 
GitLab


From e73fc71e8f015d61f3adca7659cb209fd5117aa5 Mon Sep 17 00:00:00 2001
From: Evan Quan <evan.quan@amd.com>
Date: Fri, 16 Dec 2022 17:04:24 +0800
Subject: [PATCH 528/875] drm/amd/pm: correct the fan speed retrieving in PWM
 for some SMU13 asics

For SMU 13.0.0 and 13.0.7, the output from PMFW is in percent. Driver
need to convert that into correct PMW(255) based.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.0, 6.1
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c    | 17 ++++++++++++++---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c    | 17 ++++++++++++++---
 2 files changed, 28 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 713fb6ad39f66..9643b21c636a9 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -1441,12 +1441,23 @@ out:
 static int smu_v13_0_0_get_fan_speed_pwm(struct smu_context *smu,
 					 uint32_t *speed)
 {
+	int ret;
+
 	if (!speed)
 		return -EINVAL;
 
-	return smu_v13_0_0_get_smu_metrics_data(smu,
-						METRICS_CURR_FANPWM,
-						speed);
+	ret = smu_v13_0_0_get_smu_metrics_data(smu,
+					       METRICS_CURR_FANPWM,
+					       speed);
+	if (ret) {
+		dev_err(smu->adev->dev, "Failed to get fan speed(PWM)!");
+		return ret;
+	}
+
+	/* Convert the PMFW output which is in percent to pwm(255) based */
+	*speed = MIN(*speed * 255 / 100, 255);
+
+	return 0;
 }
 
 static int smu_v13_0_0_get_fan_speed_rpm(struct smu_context *smu,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 07e3dc18c8b83..5c6c6ad011ca6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -1363,12 +1363,23 @@ static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu)
 static int smu_v13_0_7_get_fan_speed_pwm(struct smu_context *smu,
 					 uint32_t *speed)
 {
+	int ret;
+
 	if (!speed)
 		return -EINVAL;
 
-	return smu_v13_0_7_get_smu_metrics_data(smu,
-						METRICS_CURR_FANPWM,
-						speed);
+	ret = smu_v13_0_7_get_smu_metrics_data(smu,
+					       METRICS_CURR_FANPWM,
+					       speed);
+	if (ret) {
+		dev_err(smu->adev->dev, "Failed to get fan speed(PWM)!");
+		return ret;
+	}
+
+	/* Convert the PMFW output which is in percent to pwm(255) based */
+	*speed = MIN(*speed * 255 / 100, 255);
+
+	return 0;
 }
 
 static int smu_v13_0_7_get_fan_speed_rpm(struct smu_context *smu,
-- 
GitLab


From 8660495a9c5b9afeec4cc006b3b75178f0fb2f10 Mon Sep 17 00:00:00 2001
From: Tim Huang <tim.huang@amd.com>
Date: Mon, 19 Dec 2022 18:32:32 +0800
Subject: [PATCH 529/875] drm/amdgpu: skip mes self test after s0i3 resume for
 MES IP v11.0

MES is part of gfxoff and MES suspend and resume are skipped for S0i3.
But the mes_self_test call path is still in the amdgpu_device_ip_late_init.
it's should also be skipped for s0ix as no hardware re-initialization
happened.

Besides, mes_self_test will free the BO that triggers a lot of warning
messages while in the suspend state.

[   81.656085] WARNING: CPU: 2 PID: 1550 at drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:425 amdgpu_bo_free_kernel+0xfc/0x110 [amdgpu]
[   81.679435] Call Trace:
[   81.679726]  <TASK>
[   81.679981]  amdgpu_mes_remove_hw_queue+0x17a/0x230 [amdgpu]
[   81.680857]  amdgpu_mes_self_test+0x390/0x430 [amdgpu]
[   81.681665]  mes_v11_0_late_init+0x37/0x50 [amdgpu]
[   81.682423]  amdgpu_device_ip_late_init+0x53/0x280 [amdgpu]
[   81.683257]  amdgpu_device_resume+0xae/0x2a0 [amdgpu]
[   81.684043]  amdgpu_pmops_resume+0x37/0x70 [amdgpu]
[   81.684818]  pci_pm_resume+0x5c/0xa0
[   81.685247]  ? pci_pm_thaw+0x90/0x90
[   81.685658]  dpm_run_callback+0x4e/0x160
[   81.686110]  device_resume+0xad/0x210
[   81.686529]  async_resume+0x1e/0x40
[   81.686931]  async_run_entry_fn+0x33/0x120
[   81.687405]  process_one_work+0x21d/0x3f0
[   81.687869]  worker_thread+0x4a/0x3c0
[   81.688293]  ? process_one_work+0x3f0/0x3f0
[   81.688777]  kthread+0xff/0x130
[   81.689157]  ? kthread_complete_and_exit+0x20/0x20
[   81.689707]  ret_from_fork+0x22/0x30
[   81.690118]  </TASK>
[   81.690380] ---[ end trace 0000000000000000 ]---

v2: make the comment clean and use adev->in_s0ix instead of
adev->suspend

Signed-off-by: Tim Huang <tim.huang@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.0, 6.1
---
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 5459366f49ffe..970b066b37bb9 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -1342,7 +1342,8 @@ static int mes_v11_0_late_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	if (!amdgpu_in_reset(adev) &&
+	/* it's only intended for use in mes_self_test case, not for s0ix and reset */
+	if (!amdgpu_in_reset(adev) && !adev->in_s0ix &&
 	    (adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3)))
 		amdgpu_mes_self_test(adev);
 
-- 
GitLab


From 560840afc3e63bbe5d9c5ef6b2ecf8f3589adff6 Mon Sep 17 00:00:00 2001
From: Boris Burkov <boris@bur.io>
Date: Wed, 14 Dec 2022 15:05:08 -0800
Subject: [PATCH 530/875] btrfs: fix resolving backrefs for inline extent
 followed by prealloc

If a file consists of an inline extent followed by a regular or prealloc
extent, then a legitimate attempt to resolve a logical address in the
non-inline region will result in add_all_parents reading the invalid
offset field of the inline extent. If the inline extent item is placed
in the leaf eb s.t. it is the first item, attempting to access the
offset field will not only be meaningless, it will go past the end of
the eb and cause this panic:

  [17.626048] BTRFS warning (device dm-2): bad eb member end: ptr 0x3fd4 start 30834688 member offset 16377 size 8
  [17.631693] general protection fault, probably for non-canonical address 0x5088000000000: 0000 [#1] SMP PTI
  [17.635041] CPU: 2 PID: 1267 Comm: btrfs Not tainted 5.12.0-07246-g75175d5adc74-dirty #199
  [17.637969] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org 04/01/2014
  [17.641995] RIP: 0010:btrfs_get_64+0xe7/0x110
  [17.649890] RSP: 0018:ffffc90001f73a08 EFLAGS: 00010202
  [17.651652] RAX: 0000000000000001 RBX: ffff88810c42d000 RCX: 0000000000000000
  [17.653921] RDX: 0005088000000000 RSI: ffffc90001f73a0f RDI: 0000000000000001
  [17.656174] RBP: 0000000000000ff9 R08: 0000000000000007 R09: c0000000fffeffff
  [17.658441] R10: ffffc90001f73790 R11: ffffc90001f73788 R12: ffff888106afe918
  [17.661070] R13: 0000000000003fd4 R14: 0000000000003f6f R15: cdcdcdcdcdcdcdcd
  [17.663617] FS:  00007f64e7627d80(0000) GS:ffff888237c80000(0000) knlGS:0000000000000000
  [17.666525] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
  [17.668664] CR2: 000055d4a39152e8 CR3: 000000010c596002 CR4: 0000000000770ee0
  [17.671253] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
  [17.673634] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
  [17.676034] PKRU: 55555554
  [17.677004] Call Trace:
  [17.677877]  add_all_parents+0x276/0x480
  [17.679325]  find_parent_nodes+0xfae/0x1590
  [17.680771]  btrfs_find_all_leafs+0x5e/0xa0
  [17.682217]  iterate_extent_inodes+0xce/0x260
  [17.683809]  ? btrfs_inode_flags_to_xflags+0x50/0x50
  [17.685597]  ? iterate_inodes_from_logical+0xa1/0xd0
  [17.687404]  iterate_inodes_from_logical+0xa1/0xd0
  [17.689121]  ? btrfs_inode_flags_to_xflags+0x50/0x50
  [17.691010]  btrfs_ioctl_logical_to_ino+0x131/0x190
  [17.692946]  btrfs_ioctl+0x104a/0x2f60
  [17.694384]  ? selinux_file_ioctl+0x182/0x220
  [17.695995]  ? __x64_sys_ioctl+0x84/0xc0
  [17.697394]  __x64_sys_ioctl+0x84/0xc0
  [17.698697]  do_syscall_64+0x33/0x40
  [17.700017]  entry_SYSCALL_64_after_hwframe+0x44/0xae
  [17.701753] RIP: 0033:0x7f64e72761b7
  [17.709355] RSP: 002b:00007ffefb067f58 EFLAGS: 00000246 ORIG_RAX: 0000000000000010
  [17.712088] RAX: ffffffffffffffda RBX: 0000000000000003 RCX: 00007f64e72761b7
  [17.714667] RDX: 00007ffefb067fb0 RSI: 00000000c0389424 RDI: 0000000000000003
  [17.717386] RBP: 00007ffefb06d188 R08: 000055d4a390d2b0 R09: 00007f64e7340a60
  [17.719938] R10: 0000000000000231 R11: 0000000000000246 R12: 0000000000000001
  [17.722383] R13: 0000000000000000 R14: 00000000c0389424 R15: 000055d4a38fd2a0
  [17.724839] Modules linked in:

Fix the bug by detecting the inline extent item in add_all_parents and
skipping to the next extent item.

CC: stable@vger.kernel.org # 4.9+
Reviewed-by: Qu Wenruo <wqu@suse.com>
Signed-off-by: Boris Burkov <boris@bur.io>
Signed-off-by: David Sterba <dsterba@suse.com>
---
 fs/btrfs/backref.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/fs/btrfs/backref.c b/fs/btrfs/backref.c
index 21c92c74bf71a..46851511b661b 100644
--- a/fs/btrfs/backref.c
+++ b/fs/btrfs/backref.c
@@ -484,6 +484,7 @@ static int add_all_parents(struct btrfs_backref_walk_ctx *ctx,
 	u64 wanted_disk_byte = ref->wanted_disk_byte;
 	u64 count = 0;
 	u64 data_offset;
+	u8 type;
 
 	if (level != 0) {
 		eb = path->nodes[level];
@@ -538,6 +539,9 @@ static int add_all_parents(struct btrfs_backref_walk_ctx *ctx,
 			continue;
 		}
 		fi = btrfs_item_ptr(eb, slot, struct btrfs_file_extent_item);
+		type = btrfs_file_extent_type(eb, fi);
+		if (type == BTRFS_FILE_EXTENT_INLINE)
+			goto next;
 		disk_byte = btrfs_file_extent_disk_bytenr(eb, fi);
 		data_offset = btrfs_file_extent_offset(eb, fi);
 
-- 
GitLab


From e7fc357ec03ee109da503af0dd31bbf68514e481 Mon Sep 17 00:00:00 2001
From: Josef Bacik <josef@toxicpanda.com>
Date: Fri, 16 Dec 2022 11:48:00 -0500
Subject: [PATCH 531/875] btrfs: scrub: fix uninitialized return value in
 recover_scrub_rbio
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Commit 75b470332965 ("btrfs: raid56: migrate recovery and scrub recovery
path to use error_bitmap") introduced an uninitialized return variable.

This can be caught by gcc 12.1 by -Wmaybe-uninitialized:

  CC [M]  fs/btrfs/raid56.o
fs/btrfs/raid56.c: In function ‘scrub_rbio’:
fs/btrfs/raid56.c:2801:15: warning: ‘ret’ may be used uninitialized [-Wmaybe-uninitialized]
 2801 |         ret = recover_scrub_rbio(rbio);
      |               ^~~~~~~~~~~~~~~~~~~~~~~~
fs/btrfs/raid56.c:2649:13: note: ‘ret’ was declared here
 2649 |         int ret;

The warning is disabled by default so we haven't caught that.

Due to the bug the raid56 scrub fstests have been failing since the
patch was merged, so initialize that.

Fixes: 75b470332965 ("btrfs: raid56: migrate recovery and scrub recovery path to use error_bitmap")
Signed-off-by: Josef Bacik <josef@toxicpanda.com>
Reviewed-by: David Sterba <dsterba@suse.com>
Signed-off-by: David Sterba <dsterba@suse.com>
---
 fs/btrfs/raid56.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/btrfs/raid56.c b/fs/btrfs/raid56.c
index 2d90a6b5eb00e..6a2cf754912df 100644
--- a/fs/btrfs/raid56.c
+++ b/fs/btrfs/raid56.c
@@ -2646,7 +2646,7 @@ static int recover_scrub_rbio(struct btrfs_raid_bio *rbio)
 	void **pointers = NULL;
 	void **unmap_array = NULL;
 	int sector_nr;
-	int ret;
+	int ret = 0;
 
 	/*
 	 * @pointers array stores the pointer for each sector.
-- 
GitLab


From fee4c19937439693f2420a916169d08e88576e8e Mon Sep 17 00:00:00 2001
From: Filipe Manana <fdmanana@suse.com>
Date: Tue, 20 Dec 2022 11:13:33 +0000
Subject: [PATCH 532/875] btrfs: fix fscrypt name leak after failure to join
 log transaction

When logging a new name, we don't expect to fail joining a log transaction
since we know at least one of the inodes was logged before in the current
transaction. However if we fail for some unexpected reason, we end up not
freeing the fscrypt name we previously allocated. So fix that by freeing
the name in case we failed to join a log transaction.

Fixes: ab3c5c18e8fa ("btrfs: setup qstr from dentrys using fscrypt helper")
Reviewed-by: Sweet Tea Dorminy <sweettea-kernel@dorminy.me>
Signed-off-by: Filipe Manana <fdmanana@suse.com>
Reviewed-by: David Sterba <dsterba@suse.com>
Signed-off-by: David Sterba <dsterba@suse.com>
---
 fs/btrfs/tree-log.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/fs/btrfs/tree-log.c b/fs/btrfs/tree-log.c
index a3c43f0b1c95c..fb52aa0600930 100644
--- a/fs/btrfs/tree-log.c
+++ b/fs/btrfs/tree-log.c
@@ -7459,8 +7459,11 @@ void btrfs_log_new_name(struct btrfs_trans_handle *trans,
 		 * not fail, but if it does, it's not serious, just bail out and
 		 * mark the log for a full commit.
 		 */
-		if (WARN_ON_ONCE(ret < 0))
+		if (WARN_ON_ONCE(ret < 0)) {
+			fscrypt_free_filename(&fname);
 			goto out;
+		}
+
 		log_pinned = true;
 
 		path = btrfs_alloc_path();
-- 
GitLab


From 54c3f1a81421f85e60ae2eaae7be3727a09916ee Mon Sep 17 00:00:00 2001
From: Jakub Kicinski <kuba@kernel.org>
Date: Mon, 19 Dec 2022 16:47:00 -0800
Subject: [PATCH 533/875] bpf: pull before calling skb_postpull_rcsum()

Anand hit a BUG() when pulling off headers on egress to a SW tunnel.
We get to skb_checksum_help() with an invalid checksum offset
(commit d7ea0d9df2a6 ("net: remove two BUG() from skb_checksum_help()")
converted those BUGs to WARN_ONs()).
He points out oddness in how skb_postpull_rcsum() gets used.
Indeed looks like we should pull before "postpull", otherwise
the CHECKSUM_PARTIAL fixup from skb_postpull_rcsum() will not
be able to do its job:

	if (skb->ip_summed == CHECKSUM_PARTIAL &&
	    skb_checksum_start_offset(skb) < 0)
		skb->ip_summed = CHECKSUM_NONE;

Reported-by: Anand Parthasarathy <anpartha@meta.com>
Fixes: 6578171a7ff0 ("bpf: add bpf_skb_change_proto helper")
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Acked-by: Stanislav Fomichev <sdf@google.com>
Link: https://lore.kernel.org/r/20221220004701.402165-1-kuba@kernel.org
Signed-off-by: Martin KaFai Lau <martin.lau@kernel.org>
---
 net/core/filter.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/net/core/filter.c b/net/core/filter.c
index 929358677183d..43cc1fe58a2c6 100644
--- a/net/core/filter.c
+++ b/net/core/filter.c
@@ -3180,15 +3180,18 @@ static int bpf_skb_generic_push(struct sk_buff *skb, u32 off, u32 len)
 
 static int bpf_skb_generic_pop(struct sk_buff *skb, u32 off, u32 len)
 {
+	void *old_data;
+
 	/* skb_ensure_writable() is not needed here, as we're
 	 * already working on an uncloned skb.
 	 */
 	if (unlikely(!pskb_may_pull(skb, off + len)))
 		return -ENOMEM;
 
-	skb_postpull_rcsum(skb, skb->data + off, len);
-	memmove(skb->data + len, skb->data, off);
+	old_data = skb->data;
 	__skb_pull(skb, len);
+	skb_postpull_rcsum(skb, old_data + off, len);
+	memmove(skb->data, old_data, off);
 
 	return 0;
 }
-- 
GitLab


From db918321275d648294a3fb2bdefeb99e33f00467 Mon Sep 17 00:00:00 2001
From: Christoph Hellwig <hch@lst.de>
Date: Tue, 20 Dec 2022 09:05:36 +0100
Subject: [PATCH 534/875] ALSA: memalloc: don't use GFP_COMP for non-coherent
 dma allocations

While not quite as bogus as for the dma-coherent allocations that were
fixed earlier, GFP_COMP for these allocations has no benefits for
the dma-direct case, and can't be supported at all by dma dma-iommu
backend which splits up allocations into smaller orders.  Due to an
oversight in ffcb75458460 that flag stopped being cleared for all
dma allocations, but only got rejected for coherent ones.

Start fixing this by not requesting __GFP_COMP in the sound code, which
is the only place that did this.

Fixes: ffcb75458460 ("dma-mapping: reject __GFP_COMP in dma_alloc_attrs")
Reported-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>
Reported-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Takashi Iwai <tiwai@suse.de>
Tested-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>
Tested-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
---
 sound/core/memalloc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sound/core/memalloc.c b/sound/core/memalloc.c
index 3cf5a87d69eaf..81025f50a5422 100644
--- a/sound/core/memalloc.c
+++ b/sound/core/memalloc.c
@@ -542,7 +542,7 @@ static void *snd_dma_noncontig_alloc(struct snd_dma_buffer *dmab, size_t size)
 	void *p;
 
 	sgt = dma_alloc_noncontiguous(dmab->dev.dev, size, dmab->dev.dir,
-				      DEFAULT_GFP | __GFP_COMP, 0);
+				      DEFAULT_GFP, 0);
 #ifdef CONFIG_SND_DMA_SGBUF
 	if (!sgt && !get_dma_ops(dmab->dev.dev)) {
 		if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_WC_SG)
@@ -820,7 +820,7 @@ static void *snd_dma_noncoherent_alloc(struct snd_dma_buffer *dmab, size_t size)
 	void *p;
 
 	p = dma_alloc_noncoherent(dmab->dev.dev, size, &dmab->addr,
-				  dmab->dev.dir, DEFAULT_GFP | __GFP_COMP);
+				  dmab->dev.dir, DEFAULT_GFP);
 	if (p)
 		dmab->dev.need_sync = dma_need_sync(dmab->dev.dev, dmab->addr);
 	return p;
-- 
GitLab


From 3622b86f49f84e52fb41fee9eb55f9290613dfc3 Mon Sep 17 00:00:00 2001
From: Christoph Hellwig <hch@lst.de>
Date: Tue, 20 Dec 2022 09:08:12 +0100
Subject: [PATCH 535/875] dma-mapping: reject GFP_COMP for noncoherent
 allocations

While not quite as bogus as for the dma-coherent allocations that were
fixed earlier, GFP_COMP for these allocations has no benefits for
the dma-direct case, and can't be supported at all by dma dma-iommu
backend which splits up allocations into smaller orders.  Due to an
oversight in ffcb75458460 that flag stopped being cleared for all
dma allocations, but only got rejected for coherent ones, so fix up
these callers to not allow __GFP_COMP as well after the sound code
has been fixed to not ask for it.

Fixes: ffcb75458460 ("dma-mapping: reject __GFP_COMP in dma_alloc_attrs")
Reported-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>
Reported-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Takashi Iwai <tiwai@suse.de>
Tested-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>
Tested-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
---
 kernel/dma/mapping.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index c026a5a5e0466..68106e3791f6c 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -560,6 +560,8 @@ static struct page *__dma_alloc_pages(struct device *dev, size_t size,
 		return NULL;
 	if (WARN_ON_ONCE(gfp & (__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM)))
 		return NULL;
+	if (WARN_ON_ONCE(gfp & __GFP_COMP))
+		return NULL;
 
 	size = PAGE_ALIGN(size);
 	if (dma_alloc_direct(dev, ops))
@@ -645,6 +647,8 @@ struct sg_table *dma_alloc_noncontiguous(struct device *dev, size_t size,
 
 	if (WARN_ON_ONCE(attrs & ~DMA_ATTR_ALLOC_SINGLE_PAGES))
 		return NULL;
+	if (WARN_ON_ONCE(gfp & __GFP_COMP))
+		return NULL;
 
 	if (ops && ops->alloc_noncontiguous)
 		sgt = ops->alloc_noncontiguous(dev, size, dir, gfp, attrs);
-- 
GitLab


From b5f96cb719d8ba220b565ddd3ba4ac0d8bcfb130 Mon Sep 17 00:00:00 2001
From: Klaus Jensen <k.jensen@samsung.com>
Date: Tue, 13 Dec 2022 09:58:07 +0100
Subject: [PATCH 536/875] nvme-pci: fix doorbell buffer value endianness

When using shadow doorbells, the event index and the doorbell values are
written to host memory. Prior to this patch, the values written would
erroneously be written in host endianness. This causes trouble on
big-endian platforms. Fix this by adding missing endian conversions.

This issue was noticed by Guenter while testing various big-endian
platforms under QEMU[1]. A similar fix required for hw/nvme in QEMU is
up for review as well[2].

  [1]: https://lore.kernel.org/qemu-devel/20221209110022.GA3396194@roeck-us.net/
  [2]: https://lore.kernel.org/qemu-devel/20221212114409.34972-4-its@irrelevant.dk/

Fixes: f9f38e33389c ("nvme: improve performance for virtual NVMe devices")
Reported-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/nvme/host/pci.c | 25 +++++++++++++------------
 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index f0f8027644bbf..0174428580545 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -144,9 +144,9 @@ struct nvme_dev {
 	mempool_t *iod_mempool;
 
 	/* shadow doorbell buffer support: */
-	u32 *dbbuf_dbs;
+	__le32 *dbbuf_dbs;
 	dma_addr_t dbbuf_dbs_dma_addr;
-	u32 *dbbuf_eis;
+	__le32 *dbbuf_eis;
 	dma_addr_t dbbuf_eis_dma_addr;
 
 	/* host memory buffer support: */
@@ -208,10 +208,10 @@ struct nvme_queue {
 #define NVMEQ_SQ_CMB		1
 #define NVMEQ_DELETE_ERROR	2
 #define NVMEQ_POLLED		3
-	u32 *dbbuf_sq_db;
-	u32 *dbbuf_cq_db;
-	u32 *dbbuf_sq_ei;
-	u32 *dbbuf_cq_ei;
+	__le32 *dbbuf_sq_db;
+	__le32 *dbbuf_cq_db;
+	__le32 *dbbuf_sq_ei;
+	__le32 *dbbuf_cq_ei;
 	struct completion delete_done;
 };
 
@@ -343,11 +343,11 @@ static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
 }
 
 /* Update dbbuf and return true if an MMIO is required */
-static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
-					      volatile u32 *dbbuf_ei)
+static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db,
+					      volatile __le32 *dbbuf_ei)
 {
 	if (dbbuf_db) {
-		u16 old_value;
+		u16 old_value, event_idx;
 
 		/*
 		 * Ensure that the queue is written before updating
@@ -355,8 +355,8 @@ static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
 		 */
 		wmb();
 
-		old_value = *dbbuf_db;
-		*dbbuf_db = value;
+		old_value = le32_to_cpu(*dbbuf_db);
+		*dbbuf_db = cpu_to_le32(value);
 
 		/*
 		 * Ensure that the doorbell is updated before reading the event
@@ -366,7 +366,8 @@ static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
 		 */
 		mb();
 
-		if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
+		event_idx = le32_to_cpu(*dbbuf_ei);
+		if (!nvme_dbbuf_need_event(event_idx, value, old_value))
 			return false;
 	}
 
-- 
GitLab


From c89a529e823d51dd23c7ec0c047c7a454a428541 Mon Sep 17 00:00:00 2001
From: Keith Busch <kbusch@kernel.org>
Date: Mon, 19 Dec 2022 10:59:06 -0800
Subject: [PATCH 537/875] nvme-pci: fix mempool alloc size

Convert the max size to bytes to match the units of the divisor that
calculates the worst-case number of PRP entries.

The result is used to determine how many PRP Lists are required. The
code was previously rounding this to 1 list, but we can require 2 in the
worst case. In that scenario, the driver would corrupt memory beyond the
size provided by the mempool.

While unlikely to occur (you'd need a 4MB in exactly 127 phys segments
on a queue that doesn't support SGLs), this memory corruption has been
observed by kfence.

Cc: Jens Axboe <axboe@kernel.dk>
Fixes: 943e942e6266f ("nvme-pci: limit max IO size and segments to avoid high order allocations")
Signed-off-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Jens Axboe <axboe@kernel.dk>
Reviewed-by: Kanchan Joshi <joshi.k@samsung.com>
Reviewed-by: Chaitanya Kulkarni <kch@nvidia.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/nvme/host/pci.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index 0174428580545..6e9d1c7409a9c 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -381,8 +381,8 @@ static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db,
  */
 static int nvme_pci_npages_prp(void)
 {
-	unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
-				      NVME_CTRL_PAGE_SIZE);
+	unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE;
+	unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE);
 	return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 }
 
-- 
GitLab


From 841734234a28fd5cd0889b84bd4d93a0988fa11e Mon Sep 17 00:00:00 2001
From: Keith Busch <kbusch@kernel.org>
Date: Mon, 19 Dec 2022 13:54:55 -0800
Subject: [PATCH 538/875] nvme-pci: fix page size checks

The size allocated out of the dma pool is at most NVME_CTRL_PAGE_SIZE,
which may be smaller than the PAGE_SIZE.

Fixes: c61b82c7b7134 ("nvme-pci: fix PRP pool size")
Signed-off-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/nvme/host/pci.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index 6e9d1c7409a9c..804b6a6cb43a9 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -36,7 +36,7 @@
 #define SQ_SIZE(q)	((q)->q_depth << (q)->sqes)
 #define CQ_SIZE(q)	((q)->q_depth * sizeof(struct nvme_completion))
 
-#define SGES_PER_PAGE	(PAGE_SIZE / sizeof(struct nvme_sgl_desc))
+#define SGES_PER_PAGE	(NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc))
 
 /*
  * These can be higher, but we need to ensure that any command doesn't
@@ -383,7 +383,7 @@ static int nvme_pci_npages_prp(void)
 {
 	unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE;
 	unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE);
-	return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
+	return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8);
 }
 
 /*
@@ -393,7 +393,7 @@ static int nvme_pci_npages_prp(void)
 static int nvme_pci_npages_sgl(void)
 {
 	return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
-			PAGE_SIZE);
+			NVME_CTRL_PAGE_SIZE);
 }
 
 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
@@ -709,7 +709,7 @@ static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
 		sge->length = cpu_to_le32(entries * sizeof(*sge));
 		sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
 	} else {
-		sge->length = cpu_to_le32(PAGE_SIZE);
+		sge->length = cpu_to_le32(NVME_CTRL_PAGE_SIZE);
 		sge->type = NVME_SGL_FMT_SEG_DESC << 4;
 	}
 }
-- 
GitLab


From 76ce51798cb16738a4a28a6662e7344aaf7ef769 Mon Sep 17 00:00:00 2001
From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Date: Sat, 17 Dec 2022 08:48:06 +0100
Subject: [PATCH 539/875] MIPS: ralink: mt7621: avoid to init common ralink
 reset controller

Commit 38a8553b0a22 ("clk: ralink: make system controller node a reset provider")
make system controller a reset provider for mt7621 ralink SoCs. Ralink init code
also tries to start previous common reset controller which at the end tries to
find device tree node 'ralink,rt2880-reset'. mt7621 device tree file is not
using at all this node anymore. Hence avoid to init this common reset controller
for mt7621 ralink SoCs to avoid 'Failed to find reset controller node' boot
error trace error.

Fixes: 64b2d6ffff86 ("staging: mt7621-dts: align resets with binding documentation")
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
 arch/mips/ralink/of.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
index ea8072acf8d94..01c132bc33d54 100644
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
@@ -21,6 +21,7 @@
 #include <asm/bootinfo.h>
 #include <asm/addrspace.h>
 #include <asm/prom.h>
+#include <asm/mach-ralink/ralink_regs.h>
 
 #include "common.h"
 
@@ -81,7 +82,8 @@ static int __init plat_of_setup(void)
 	__dt_register_buses(soc_info.compatible, "palmbus");
 
 	/* make sure that the reset controller is setup early */
-	ralink_rst_init();
+	if (ralink_soc != MT762X_SOC_MT7621AT)
+		ralink_rst_init();
 
 	return 0;
 }
-- 
GitLab


From 24b333a866a10d4be47b9968b9c05a3e9f326ff5 Mon Sep 17 00:00:00 2001
From: Florian Fainelli <f.fainelli@gmail.com>
Date: Tue, 20 Dec 2022 11:09:46 -0800
Subject: [PATCH 540/875] MIPS: dts: bcm63268: Add missing properties to the
 TWD node
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

We currently have a DTC warning with the current DTS due to the lack of
a suitable #address-cells and #size-cells property:

  DTC     arch/mips/boot/dts/brcm/bcm63268-comtrend-vr-3032u.dtb
arch/mips/boot/dts/brcm/bcm63268.dtsi:115.5-22: Warning (reg_format): /ubus/timer-mfd@10000080/timer@0:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1)
arch/mips/boot/dts/brcm/bcm63268.dtsi:120.5-22: Warning (reg_format): /ubus/timer-mfd@10000080/watchdog@1c:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1)
arch/mips/boot/dts/brcm/bcm63268.dtsi:111.4-35: Warning (ranges_format): /ubus/timer-mfd@10000080:ranges: "ranges" property has invalid length (12 bytes) (parent #address-cells == 1, child #address-cells == 2, #size-cells == 1)

Fixes: d3db4b96ab7f ("mips: dts: bcm63268: add TWD block timer")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
 arch/mips/boot/dts/brcm/bcm63268.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/boot/dts/brcm/bcm63268.dtsi b/arch/mips/boot/dts/brcm/bcm63268.dtsi
index c663efce91cf5..7b788757cb1eb 100644
--- a/arch/mips/boot/dts/brcm/bcm63268.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm63268.dtsi
@@ -109,6 +109,8 @@
 			compatible = "brcm,bcm7038-twd", "simple-mfd", "syscon";
 			reg = <0x10000080 0x30>;
 			ranges = <0x0 0x10000080 0x30>;
+			#address-cells = <1>;
+			#size-cells = <1>;
 
 			timer@0 {
 				compatible = "brcm,bcm6345-timer";
-- 
GitLab


From 11933cf1d91d57da9e5c53822a540bbdc2656c16 Mon Sep 17 00:00:00 2001
From: Christian Brauner <brauner@kernel.org>
Date: Sat, 17 Dec 2022 22:28:40 +0100
Subject: [PATCH 541/875] pnode: terminate at peers of source

The propagate_mnt() function handles mount propagation when creating
mounts and propagates the source mount tree @source_mnt to all
applicable nodes of the destination propagation mount tree headed by
@dest_mnt.

Unfortunately it contains a bug where it fails to terminate at peers of
@source_mnt when looking up copies of the source mount that become
masters for copies of the source mount tree mounted on top of slaves in
the destination propagation tree causing a NULL dereference.

Once the mechanics of the bug are understood it's easy to trigger.
Because of unprivileged user namespaces it is available to unprivileged
users.

While fixing this bug we've gotten confused multiple times due to
unclear terminology or missing concepts. So let's start this with some
clarifications:

* The terms "master" or "peer" denote a shared mount. A shared mount
  belongs to a peer group.

* A peer group is a set of shared mounts that propagate to each other.
  They are identified by a peer group id. The peer group id is available
  in @shared_mnt->mnt_group_id.
  Shared mounts within the same peer group have the same peer group id.
  The peers in a peer group can be reached via @shared_mnt->mnt_share.

* The terms "slave mount" or "dependent mount" denote a mount that
  receives propagation from a peer in a peer group. IOW, shared mounts
  may have slave mounts and slave mounts have shared mounts as their
  master. Slave mounts of a given peer in a peer group are listed on
  that peers slave list available at @shared_mnt->mnt_slave_list.

* The term "master mount" denotes a mount in a peer group. IOW, it
  denotes a shared mount or a peer mount in a peer group. The term
  "master mount" - or "master" for short - is mostly used when talking
  in the context of slave mounts that receive propagation from a master
  mount. A master mount of a slave identifies the closest peer group a
  slave mount receives propagation from. The master mount of a slave can
  be identified via @slave_mount->mnt_master. Different slaves may point
  to different masters in the same peer group.

* Multiple peers in a peer group can have non-empty ->mnt_slave_lists.
  Non-empty ->mnt_slave_lists of peers don't intersect. Consequently, to
  ensure all slave mounts of a peer group are visited the
  ->mnt_slave_lists of all peers in a peer group have to be walked.

* Slave mounts point to a peer in the closest peer group they receive
  propagation from via @slave_mnt->mnt_master (see above). Together with
  these peers they form a propagation group (see below). The closest
  peer group can thus be identified through the peer group id
  @slave_mnt->mnt_master->mnt_group_id of the peer/master that a slave
  mount receives propagation from.

* A shared-slave mount is a slave mount to a peer group pg1 while also
  a peer in another peer group pg2. IOW, a peer group may receive
  propagation from another peer group.

  If a peer group pg1 is a slave to another peer group pg2 then all
  peers in peer group pg1 point to the same peer in peer group pg2 via
  ->mnt_master. IOW, all peers in peer group pg1 appear on the same
  ->mnt_slave_list. IOW, they cannot be slaves to different peer groups.

* A pure slave mount is a slave mount that is a slave to a peer group
  but is not a peer in another peer group.

* A propagation group denotes the set of mounts consisting of a single
  peer group pg1 and all slave mounts and shared-slave mounts that point
  to a peer in that peer group via ->mnt_master. IOW, all slave mounts
  such that @slave_mnt->mnt_master->mnt_group_id is equal to
  @shared_mnt->mnt_group_id.

  The concept of a propagation group makes it easier to talk about a
  single propagation level in a propagation tree.

  For example, in propagate_mnt() the immediate peers of @dest_mnt and
  all slaves of @dest_mnt's peer group form a propagation group propg1.
  So a shared-slave mount that is a slave in propg1 and that is a peer
  in another peer group pg2 forms another propagation group propg2
  together with all slaves that point to that shared-slave mount in
  their ->mnt_master.

* A propagation tree refers to all mounts that receive propagation
  starting from a specific shared mount.

  For example, for propagate_mnt() @dest_mnt is the start of a
  propagation tree. The propagation tree ecompasses all mounts that
  receive propagation from @dest_mnt's peer group down to the leafs.

With that out of the way let's get to the actual algorithm.

We know that @dest_mnt is guaranteed to be a pure shared mount or a
shared-slave mount. This is guaranteed by a check in
attach_recursive_mnt(). So propagate_mnt() will first propagate the
source mount tree to all peers in @dest_mnt's peer group:

for (n = next_peer(dest_mnt); n != dest_mnt; n = next_peer(n)) {
        ret = propagate_one(n);
        if (ret)
               goto out;
}

Notice, that the peer propagation loop of propagate_mnt() doesn't
propagate @dest_mnt itself. @dest_mnt is mounted directly in
attach_recursive_mnt() after we propagated to the destination
propagation tree.

The mount that will be mounted on top of @dest_mnt is @source_mnt. This
copy was created earlier even before we entered attach_recursive_mnt()
and doesn't concern us a lot here.

It's just important to notice that when propagate_mnt() is called
@source_mnt will not yet have been mounted on top of @dest_mnt. Thus,
@source_mnt->mnt_parent will either still point to @source_mnt or - in
the case @source_mnt is moved and thus already attached - still to its
former parent.

For each peer @m in @dest_mnt's peer group propagate_one() will create a
new copy of the source mount tree and mount that copy @child on @m such
that @child->mnt_parent points to @m after propagate_one() returns.

propagate_one() will stash the last destination propagation node @m in
@last_dest and the last copy it created for the source mount tree in
@last_source.

Hence, if we call into propagate_one() again for the next destination
propagation node @m, @last_dest will point to the previous destination
propagation node and @last_source will point to the previous copy of the
source mount tree and mounted on @last_dest.

Each new copy of the source mount tree is created from the previous copy
of the source mount tree. This will become important later.

The peer loop in propagate_mnt() is straightforward. We iterate through
the peers copying and updating @last_source and @last_dest as we go
through them and mount each copy of the source mount tree @child on a
peer @m in @dest_mnt's peer group.

After propagate_mnt() handled the peers in @dest_mnt's peer group
propagate_mnt() will propagate the source mount tree down the
propagation tree that @dest_mnt's peer group propagates to:

for (m = next_group(dest_mnt, dest_mnt); m;
                m = next_group(m, dest_mnt)) {
        /* everything in that slave group */
        n = m;
        do {
                ret = propagate_one(n);
                if (ret)
                        goto out;
                n = next_peer(n);
        } while (n != m);
}

The next_group() helper will recursively walk the destination
propagation tree, descending into each propagation group of the
propagation tree.

The important part is that it takes care to propagate the source mount
tree to all peers in the peer group of a propagation group before it
propagates to the slaves to those peers in the propagation group. IOW,
it creates and mounts copies of the source mount tree that become
masters before it creates and mounts copies of the source mount tree
that become slaves to these masters.

It is important to remember that propagating the source mount tree to
each mount @m in the destination propagation tree simply means that we
create and mount new copies @child of the source mount tree on @m such
that @child->mnt_parent points to @m.

Since we know that each node @m in the destination propagation tree
headed by @dest_mnt's peer group will be overmounted with a copy of the
source mount tree and since we know that the propagation properties of
each copy of the source mount tree we create and mount at @m will mostly
mirror the propagation properties of @m. We can use that information to
create and mount the copies of the source mount tree that become masters
before their slaves.

The easy case is always when @m and @last_dest are peers in a peer group
of a given propagation group. In that case we know that we can simply
copy @last_source without having to figure out what the master for the
new copy @child of the source mount tree needs to be as we've done that
in a previous call to propagate_one().

The hard case is when we're dealing with a slave mount or a shared-slave
mount @m in a destination propagation group that we need to create and
mount a copy of the source mount tree on.

For each propagation group in the destination propagation tree we
propagate the source mount tree to we want to make sure that the copies
@child of the source mount tree we create and mount on slaves @m pick an
ealier copy of the source mount tree that we mounted on a master @m of
the destination propagation group as their master. This is a mouthful
but as far as we can tell that's the core of it all.

But, if we keep track of the masters in the destination propagation tree
@m we can use the information to find the correct master for each copy
of the source mount tree we create and mount at the slaves in the
destination propagation tree @m.

Let's walk through the base case as that's still fairly easy to grasp.

If we're dealing with the first slave in the propagation group that
@dest_mnt is in then we don't yet have marked any masters in the
destination propagation tree.

We know the master for the first slave to @dest_mnt's peer group is
simple @dest_mnt. So we expect this algorithm to yield a copy of the
source mount tree that was mounted on a peer in @dest_mnt's peer group
as the master for the copy of the source mount tree we want to mount at
the first slave @m:

for (n = m; ; n = p) {
        p = n->mnt_master;
        if (p == dest_master || IS_MNT_MARKED(p))
                break;
}

For the first slave we walk the destination propagation tree all the way
up to a peer in @dest_mnt's peer group. IOW, the propagation hierarchy
can be walked by walking up the @mnt->mnt_master hierarchy of the
destination propagation tree @m. We will ultimately find a peer in
@dest_mnt's peer group and thus ultimately @dest_mnt->mnt_master.

Btw, here the assumption we listed at the beginning becomes important.
Namely, that peers in a peer group pg1 that are slaves in another peer
group pg2 appear on the same ->mnt_slave_list. IOW, all slaves who are
peers in peer group pg1 point to the same peer in peer group pg2 via
their ->mnt_master. Otherwise the termination condition in the code
above would be wrong and next_group() would be broken too.

So the first iteration sets:

n = m;
p = n->mnt_master;

such that @p now points to a peer or @dest_mnt itself. We walk up one
more level since we don't have any marked mounts. So we end up with:

n = dest_mnt;
p = dest_mnt->mnt_master;

If @dest_mnt's peer group is not slave to another peer group then @p is
now NULL. If @dest_mnt's peer group is a slave to another peer group
then @p now points to @dest_mnt->mnt_master points which is a master
outside the propagation tree we're dealing with.

Now we need to figure out the master for the copy of the source mount
tree we're about to create and mount on the first slave of @dest_mnt's
peer group:

do {
        struct mount *parent = last_source->mnt_parent;
        if (last_source == first_source)
                break;
        done = parent->mnt_master == p;
        if (done && peers(n, parent))
                break;
        last_source = last_source->mnt_master;
} while (!done);

We know that @last_source->mnt_parent points to @last_dest and
@last_dest is the last peer in @dest_mnt's peer group we propagated to
in the peer loop in propagate_mnt().

Consequently, @last_source is the last copy we created and mount on that
last peer in @dest_mnt's peer group. So @last_source is the master we
want to pick.

We know that @last_source->mnt_parent->mnt_master points to
@last_dest->mnt_master. We also know that @last_dest->mnt_master is
either NULL or points to a master outside of the destination propagation
tree and so does @p. Hence:

done = parent->mnt_master == p;

is trivially true in the base condition.

We also know that for the first slave mount of @dest_mnt's peer group
that @last_dest either points @dest_mnt itself because it was
initialized to:

last_dest = dest_mnt;

at the beginning of propagate_mnt() or it will point to a peer of
@dest_mnt in its peer group. In both cases it is guaranteed that on the
first iteration @n and @parent are peers (Please note the check for
peers here as that's important.):

if (done && peers(n, parent))
        break;

So, as we expected, we select @last_source, which referes to the last
copy of the source mount tree we mounted on the last peer in @dest_mnt's
peer group, as the master of the first slave in @dest_mnt's peer group.
The rest is taken care of by clone_mnt(last_source, ...). We'll skip
over that part otherwise this becomes a blogpost.

At the end of propagate_mnt() we now mark @m->mnt_master as the first
master in the destination propagation tree that is distinct from
@dest_mnt->mnt_master. IOW, we mark @dest_mnt itself as a master.

By marking @dest_mnt or one of it's peers we are able to easily find it
again when we later lookup masters for other copies of the source mount
tree we mount copies of the source mount tree on slaves @m to
@dest_mnt's peer group. This, in turn allows us to find the master we
selected for the copies of the source mount tree we mounted on master in
the destination propagation tree again.

The important part is to realize that the code makes use of the fact
that the last copy of the source mount tree stashed in @last_source was
mounted on top of the previous destination propagation node @last_dest.
What this means is that @last_source allows us to walk the destination
propagation hierarchy the same way each destination propagation node @m
does.

If we take @last_source, which is the copy of @source_mnt we have
mounted on @last_dest in the previous iteration of propagate_one(), then
we know @last_source->mnt_parent points to @last_dest but we also know
that as we walk through the destination propagation tree that
@last_source->mnt_master will point to an earlier copy of the source
mount tree we mounted one an earlier destination propagation node @m.

IOW, @last_source->mnt_parent will be our hook into the destination
propagation tree and each consecutive @last_source->mnt_master will lead
us to an earlier propagation node @m via
@last_source->mnt_master->mnt_parent.

Hence, by walking up @last_source->mnt_master, each of which is mounted
on a node that is a master @m in the destination propagation tree we can
also walk up the destination propagation hierarchy.

So, for each new destination propagation node @m we use the previous
copy of @last_source and the fact it's mounted on the previous
propagation node @last_dest via @last_source->mnt_master->mnt_parent to
determine what the master of the new copy of @last_source needs to be.

The goal is to find the _closest_ master that the new copy of the source
mount tree we are about to create and mount on a slave @m in the
destination propagation tree needs to pick. IOW, we want to find a
suitable master in the propagation group.

As the propagation structure of the source mount propagation tree we
create mirrors the propagation structure of the destination propagation
tree we can find @m's closest master - i.e., a marked master - which is
a peer in the closest peer group that @m receives propagation from. We
store that closest master of @m in @p as before and record the slave to
that master in @n

We then search for this master @p via @last_source by walking up the
master hierarchy starting from the last copy of the source mount tree
stored in @last_source that we created and mounted on the previous
destination propagation node @m.

We will try to find the master by walking @last_source->mnt_master and
by comparing @last_source->mnt_master->mnt_parent->mnt_master to @p. If
we find @p then we can figure out what earlier copy of the source mount
tree needs to be the master for the new copy of the source mount tree
we're about to create and mount at the current destination propagation
node @m.

If @last_source->mnt_master->mnt_parent and @n are peers then we know
that the closest master they receive propagation from is
@last_source->mnt_master->mnt_parent->mnt_master. If not then the
closest immediate peer group that they receive propagation from must be
one level higher up.

This builds on the earlier clarification at the beginning that all peers
in a peer group which are slaves of other peer groups all point to the
same ->mnt_master, i.e., appear on the same ->mnt_slave_list, of the
closest peer group that they receive propagation from.

However, terminating the walk has corner cases.

If the closest marked master for a given destination node @m cannot be
found by walking up the master hierarchy via @last_source->mnt_master
then we need to terminate the walk when we encounter @source_mnt again.

This isn't an arbitrary termination. It simply means that the new copy
of the source mount tree we're about to create has a copy of the source
mount tree we created and mounted on a peer in @dest_mnt's peer group as
its master. IOW, @source_mnt is the peer in the closest peer group that
the new copy of the source mount tree receives propagation from.

We absolutely have to stop @source_mnt because @last_source->mnt_master
either points outside the propagation hierarchy we're dealing with or it
is NULL because @source_mnt isn't a shared-slave.

So continuing the walk past @source_mnt would cause a NULL dereference
via @last_source->mnt_master->mnt_parent. And so we have to stop the
walk when we encounter @source_mnt again.

One scenario where this can happen is when we first handled a series of
slaves of @dest_mnt's peer group and then encounter peers in a new peer
group that is a slave to @dest_mnt's peer group. We handle them and then
we encounter another slave mount to @dest_mnt that is a pure slave to
@dest_mnt's peer group. That pure slave will have a peer in @dest_mnt's
peer group as its master. Consequently, the new copy of the source mount
tree will need to have @source_mnt as it's master. So we walk the
propagation hierarchy all the way up to @source_mnt based on
@last_source->mnt_master.

So terminate on @source_mnt, easy peasy. Except, that the check misses
something that the rest of the algorithm already handles.

If @dest_mnt has peers in it's peer group the peer loop in
propagate_mnt():

for (n = next_peer(dest_mnt); n != dest_mnt; n = next_peer(n)) {
        ret = propagate_one(n);
        if (ret)
                goto out;
}

will consecutively update @last_source with each previous copy of the
source mount tree we created and mounted at the previous peer in
@dest_mnt's peer group. So after that loop terminates @last_source will
point to whatever copy of the source mount tree was created and mounted
on the last peer in @dest_mnt's peer group.

Furthermore, if there is even a single additional peer in @dest_mnt's
peer group then @last_source will __not__ point to @source_mnt anymore.
Because, as we mentioned above, @dest_mnt isn't even handled in this
loop but directly in attach_recursive_mnt(). So it can't even accidently
come last in that peer loop.

So the first time we handle a slave mount @m of @dest_mnt's peer group
the copy of the source mount tree we create will make the __last copy of
the source mount tree we created and mounted on the last peer in
@dest_mnt's peer group the master of the new copy of the source mount
tree we create and mount on the first slave of @dest_mnt's peer group__.

But this means that the termination condition that checks for
@source_mnt is wrong. The @source_mnt cannot be found anymore by
propagate_one(). Instead it will find the last copy of the source mount
tree we created and mounted for the last peer of @dest_mnt's peer group
again. And that is a peer of @source_mnt not @source_mnt itself.

IOW, we fail to terminate the loop correctly and ultimately dereference
@last_source->mnt_master->mnt_parent. When @source_mnt's peer group
isn't slave to another peer group then @last_source->mnt_master is NULL
causing the splat below.

For example, assume @dest_mnt is a pure shared mount and has three peers
in its peer group:

===================================================================================
                                         mount-id   mount-parent-id   peer-group-id
===================================================================================
(@dest_mnt) mnt_master[216]              309        297               shared:216
    \
     (@source_mnt) mnt_master[218]:      609        609               shared:218

(1) mnt_master[216]:                     607        605               shared:216
    \
     (P1) mnt_master[218]:               624        607               shared:218

(2) mnt_master[216]:                     576        574               shared:216
    \
     (P2) mnt_master[218]:               625        576               shared:218

(3) mnt_master[216]:                     545        543               shared:216
    \
     (P3) mnt_master[218]:               626        545               shared:218

After this sequence has been processed @last_source will point to (P3),
the copy generated for the third peer in @dest_mnt's peer group we
handled. So the copy of the source mount tree (P4) we create and mount
on the first slave of @dest_mnt's peer group:

===================================================================================
                                         mount-id   mount-parent-id   peer-group-id
===================================================================================
    mnt_master[216]                      309        297               shared:216
   /
  /
(S0) mnt_slave                           483        481               master:216
  \
   \    (P3) mnt_master[218]             626        545               shared:218
    \  /
     \/
    (P4) mnt_slave                       627        483               master:218

will pick the last copy of the source mount tree (P3) as master, not (S0).

When walking the propagation hierarchy via @last_source's master
hierarchy we encounter (P3) but not (S0), i.e., @source_mnt.

We can fix this in multiple ways:

(1) By setting @last_source to @source_mnt after we processed the peers
    in @dest_mnt's peer group right after the peer loop in
    propagate_mnt().

(2) By changing the termination condition that relies on finding exactly
    @source_mnt to finding a peer of @source_mnt.

(3) By only moving @last_source when we actually venture into a new peer
    group or some clever variant thereof.

The first two options are minimally invasive and what we want as a fix.
The third option is more intrusive but something we'd like to explore in
the near future.

This passes all LTP tests and specifically the mount propagation
testsuite part of it. It also holds up against all known reproducers of
this issues.

Final words.
First, this is a clever but __worringly__ underdocumented algorithm.
There isn't a single detailed comment to be found in next_group(),
propagate_one() or anywhere else in that file for that matter. This has
been a giant pain to understand and work through and a bug like this is
insanely difficult to fix without a detailed understanding of what's
happening. Let's not talk about the amount of time that was sunk into
fixing this.

Second, all the cool kids with access to
unshare --mount --user --map-root --propagation=unchanged
are going to have a lot of fun. IOW, triggerable by unprivileged users
while namespace_lock() lock is held.

[  115.848393] BUG: kernel NULL pointer dereference, address: 0000000000000010
[  115.848967] #PF: supervisor read access in kernel mode
[  115.849386] #PF: error_code(0x0000) - not-present page
[  115.849803] PGD 0 P4D 0
[  115.850012] Oops: 0000 [#1] PREEMPT SMP PTI
[  115.850354] CPU: 0 PID: 15591 Comm: mount Not tainted 6.1.0-rc7 #3
[  115.850851] Hardware name: innotek GmbH VirtualBox/VirtualBox, BIOS
VirtualBox 12/01/2006
[  115.851510] RIP: 0010:propagate_one.part.0+0x7f/0x1a0
[  115.851924] Code: 75 eb 4c 8b 05 c2 25 37 02 4c 89 ca 48 8b 4a 10
49 39 d0 74 1e 48 3b 81 e0 00 00 00 74 26 48 8b 92 e0 00 00 00 be 01
00 00 00 <48> 8b 4a 10 49 39 d0 75 e2 40 84 f6 74 38 4c 89 05 84 25 37
02 4d
[  115.853441] RSP: 0018:ffffb8d5443d7d50 EFLAGS: 00010282
[  115.853865] RAX: ffff8e4d87c41c80 RBX: ffff8e4d88ded780 RCX: ffff8e4da4333a00
[  115.854458] RDX: 0000000000000000 RSI: 0000000000000001 RDI: ffff8e4d88ded780
[  115.855044] RBP: ffff8e4d88ded780 R08: ffff8e4da4338000 R09: ffff8e4da43388c0
[  115.855693] R10: 0000000000000002 R11: ffffb8d540158000 R12: ffffb8d5443d7da8
[  115.856304] R13: ffff8e4d88ded780 R14: 0000000000000000 R15: 0000000000000000
[  115.856859] FS:  00007f92c90c9800(0000) GS:ffff8e4dfdc00000(0000)
knlGS:0000000000000000
[  115.857531] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[  115.858006] CR2: 0000000000000010 CR3: 0000000022f4c002 CR4: 00000000000706f0
[  115.858598] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[  115.859393] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
[  115.860099] Call Trace:
[  115.860358]  <TASK>
[  115.860535]  propagate_mnt+0x14d/0x190
[  115.860848]  attach_recursive_mnt+0x274/0x3e0
[  115.861212]  path_mount+0x8c8/0xa60
[  115.861503]  __x64_sys_mount+0xf6/0x140
[  115.861819]  do_syscall_64+0x5b/0x80
[  115.862117]  ? do_faccessat+0x123/0x250
[  115.862435]  ? syscall_exit_to_user_mode+0x17/0x40
[  115.862826]  ? do_syscall_64+0x67/0x80
[  115.863133]  ? syscall_exit_to_user_mode+0x17/0x40
[  115.863527]  ? do_syscall_64+0x67/0x80
[  115.863835]  ? do_syscall_64+0x67/0x80
[  115.864144]  ? do_syscall_64+0x67/0x80
[  115.864452]  ? exc_page_fault+0x70/0x170
[  115.864775]  entry_SYSCALL_64_after_hwframe+0x63/0xcd
[  115.865187] RIP: 0033:0x7f92c92b0ebe
[  115.865480] Code: 48 8b 0d 75 4f 0c 00 f7 d8 64 89 01 48 83 c8 ff
c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa 49 89 ca b8 a5 00 00
00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 42 4f 0c 00 f7 d8 64 89
01 48
[  115.866984] RSP: 002b:00007fff000aa728 EFLAGS: 00000246 ORIG_RAX:
00000000000000a5
[  115.867607] RAX: ffffffffffffffda RBX: 000055a77888d6b0 RCX: 00007f92c92b0ebe
[  115.868240] RDX: 000055a77888d8e0 RSI: 000055a77888e6e0 RDI: 000055a77888e620
[  115.868823] RBP: 0000000000000000 R08: 0000000000000000 R09: 0000000000000001
[  115.869403] R10: 0000000000001000 R11: 0000000000000246 R12: 000055a77888e620
[  115.869994] R13: 000055a77888d8e0 R14: 00000000ffffffff R15: 00007f92c93e4076
[  115.870581]  </TASK>
[  115.870763] Modules linked in: nft_fib_inet nft_fib_ipv4
nft_fib_ipv6 nft_fib nft_reject_inet nf_reject_ipv4 nf_reject_ipv6
nft_reject nft_ct nft_chain_nat nf_nat nf_conntrack nf_defrag_ipv6
nf_defrag_ipv4 ip_set rfkill nf_tables nfnetlink qrtr snd_intel8x0
sunrpc snd_ac97_codec ac97_bus snd_pcm snd_timer intel_rapl_msr
intel_rapl_common snd vboxguest intel_powerclamp video rapl joydev
soundcore i2c_piix4 wmi fuse zram xfs vmwgfx crct10dif_pclmul
crc32_pclmul crc32c_intel polyval_clmulni polyval_generic
drm_ttm_helper ttm e1000 ghash_clmulni_intel serio_raw ata_generic
pata_acpi scsi_dh_rdac scsi_dh_emc scsi_dh_alua dm_multipath
[  115.875288] CR2: 0000000000000010
[  115.875641] ---[ end trace 0000000000000000 ]---
[  115.876135] RIP: 0010:propagate_one.part.0+0x7f/0x1a0
[  115.876551] Code: 75 eb 4c 8b 05 c2 25 37 02 4c 89 ca 48 8b 4a 10
49 39 d0 74 1e 48 3b 81 e0 00 00 00 74 26 48 8b 92 e0 00 00 00 be 01
00 00 00 <48> 8b 4a 10 49 39 d0 75 e2 40 84 f6 74 38 4c 89 05 84 25 37
02 4d
[  115.878086] RSP: 0018:ffffb8d5443d7d50 EFLAGS: 00010282
[  115.878511] RAX: ffff8e4d87c41c80 RBX: ffff8e4d88ded780 RCX: ffff8e4da4333a00
[  115.879128] RDX: 0000000000000000 RSI: 0000000000000001 RDI: ffff8e4d88ded780
[  115.879715] RBP: ffff8e4d88ded780 R08: ffff8e4da4338000 R09: ffff8e4da43388c0
[  115.880359] R10: 0000000000000002 R11: ffffb8d540158000 R12: ffffb8d5443d7da8
[  115.880962] R13: ffff8e4d88ded780 R14: 0000000000000000 R15: 0000000000000000
[  115.881548] FS:  00007f92c90c9800(0000) GS:ffff8e4dfdc00000(0000)
knlGS:0000000000000000
[  115.882234] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[  115.882713] CR2: 0000000000000010 CR3: 0000000022f4c002 CR4: 00000000000706f0
[  115.883314] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[  115.883966] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400

Fixes: f2ebb3a921c1 ("smarter propagate_mnt()")
Fixes: 5ec0811d3037 ("propogate_mnt: Handle the first propogated copy being a slave")
Cc: <stable@vger.kernel.org>
Reported-by: Ditang Chen <ditang.c@gmail.com>
Signed-off-by: Seth Forshee (Digital Ocean) <sforshee@kernel.org>
Signed-off-by: Christian Brauner (Microsoft) <brauner@kernel.org>
---
If there are no big objections I'll get this to Linus rather sooner than later.
---
 fs/pnode.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/pnode.c b/fs/pnode.c
index 1106137c747a3..468e4e65a615d 100644
--- a/fs/pnode.c
+++ b/fs/pnode.c
@@ -244,7 +244,7 @@ static int propagate_one(struct mount *m)
 		}
 		do {
 			struct mount *parent = last_source->mnt_parent;
-			if (last_source == first_source)
+			if (peers(last_source, first_source))
 				break;
 			done = parent->mnt_master == p;
 			if (done && peers(n, parent))
-- 
GitLab


From 52ea806ad983490b3132a9e526e11a10dc2fd10c Mon Sep 17 00:00:00 2001
From: Jens Axboe <axboe@kernel.dk>
Date: Wed, 21 Dec 2022 07:05:09 -0700
Subject: [PATCH 542/875] io_uring: finish waiting before flushing overflow
 entries

If we have overflow entries being generated after we've done the
initial flush in io_cqring_wait(), then we could be flushing them in the
main wait loop as well. If that's done after having added ourselves
to the cq_wait waitqueue, then the task state can be != TASK_RUNNING
when we enter the overflow flush.

Check for the need to overflow flush, and finish our wait cycle first
if we have to do so.

Reported-and-tested-by: syzbot+cf6ea1d6bb30a4ce10b2@syzkaller.appspotmail.com
Link: https://lore.kernel.org/io-uring/000000000000cb143a05f04eee15@google.com/
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 io_uring/io_uring.c | 25 ++++++++++++++++---------
 1 file changed, 16 insertions(+), 9 deletions(-)

diff --git a/io_uring/io_uring.c b/io_uring/io_uring.c
index ff2bbac1a10f4..ac5d39eeb3d1e 100644
--- a/io_uring/io_uring.c
+++ b/io_uring/io_uring.c
@@ -677,16 +677,20 @@ static void __io_cqring_overflow_flush(struct io_ring_ctx *ctx)
 	io_cq_unlock_post(ctx);
 }
 
+static void io_cqring_do_overflow_flush(struct io_ring_ctx *ctx)
+{
+	/* iopoll syncs against uring_lock, not completion_lock */
+	if (ctx->flags & IORING_SETUP_IOPOLL)
+		mutex_lock(&ctx->uring_lock);
+	__io_cqring_overflow_flush(ctx);
+	if (ctx->flags & IORING_SETUP_IOPOLL)
+		mutex_unlock(&ctx->uring_lock);
+}
+
 static void io_cqring_overflow_flush(struct io_ring_ctx *ctx)
 {
-	if (test_bit(IO_CHECK_CQ_OVERFLOW_BIT, &ctx->check_cq)) {
-		/* iopoll syncs against uring_lock, not completion_lock */
-		if (ctx->flags & IORING_SETUP_IOPOLL)
-			mutex_lock(&ctx->uring_lock);
-		__io_cqring_overflow_flush(ctx);
-		if (ctx->flags & IORING_SETUP_IOPOLL)
-			mutex_unlock(&ctx->uring_lock);
-	}
+	if (test_bit(IO_CHECK_CQ_OVERFLOW_BIT, &ctx->check_cq))
+		io_cqring_do_overflow_flush(ctx);
 }
 
 void __io_put_task(struct task_struct *task, int nr)
@@ -2549,7 +2553,10 @@ static int io_cqring_wait(struct io_ring_ctx *ctx, int min_events,
 
 	trace_io_uring_cqring_wait(ctx, min_events);
 	do {
-		io_cqring_overflow_flush(ctx);
+		if (test_bit(IO_CHECK_CQ_OVERFLOW_BIT, &ctx->check_cq)) {
+			finish_wait(&ctx->cq_wait, &iowq.wq);
+			io_cqring_do_overflow_flush(ctx);
+		}
 		prepare_to_wait_exclusive(&ctx->cq_wait, &iowq.wq,
 						TASK_INTERRUPTIBLE);
 		ret = io_cqring_wait_schedule(ctx, &iowq, timeout);
-- 
GitLab


From 5eb119da94ac5d67a31eaa869621dc6e25eb125e Mon Sep 17 00:00:00 2001
From: Florian Westphal <fw@strlen.de>
Date: Thu, 15 Dec 2022 15:16:33 +0100
Subject: [PATCH 543/875] netfilter: conntrack: fix ipv6 exthdr error check

smatch warnings:
net/netfilter/nf_conntrack_proto.c:167 nf_confirm() warn: unsigned 'protoff' is never less than zero.

We need to check if ipv6_skip_exthdr() returned an error, but protoff is
unsigned.  Use a signed integer for this.

Fixes: a70e483460d5 ("netfilter: conntrack: merge ipv4+ipv6 confirm functions")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Florian Westphal <fw@strlen.de>
Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
---
 net/netfilter/nf_conntrack_proto.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/net/netfilter/nf_conntrack_proto.c b/net/netfilter/nf_conntrack_proto.c
index 99323fb12d0f5..ccef340be575e 100644
--- a/net/netfilter/nf_conntrack_proto.c
+++ b/net/netfilter/nf_conntrack_proto.c
@@ -141,6 +141,7 @@ unsigned int nf_confirm(void *priv,
 	struct nf_conn *ct;
 	bool seqadj_needed;
 	__be16 frag_off;
+	int start;
 	u8 pnum;
 
 	ct = nf_ct_get(skb, &ctinfo);
@@ -163,9 +164,11 @@ unsigned int nf_confirm(void *priv,
 		break;
 	case NFPROTO_IPV6:
 		pnum = ipv6_hdr(skb)->nexthdr;
-		protoff = ipv6_skip_exthdr(skb, sizeof(struct ipv6hdr), &pnum, &frag_off);
-		if (protoff < 0 || (frag_off & htons(~0x7)) != 0)
+		start = ipv6_skip_exthdr(skb, sizeof(struct ipv6hdr), &pnum, &frag_off);
+		if (start < 0 || (frag_off & htons(~0x7)) != 0)
 			return nf_conntrack_confirm(skb);
+
+		protoff = start;
 		break;
 	default:
 		return nf_conntrack_confirm(skb);
-- 
GitLab


From bed4a63ea4ae77cfe5aae004ef87379f0655260a Mon Sep 17 00:00:00 2001
From: Pablo Neira Ayuso <pablo@netfilter.org>
Date: Mon, 19 Dec 2022 20:07:52 +0100
Subject: [PATCH 544/875] netfilter: nf_tables: consolidate set description

Add the following fields to the set description:

- key type
- data type
- object type
- policy
- gc_int: garbage collection interval)
- timeout: element timeout

This prepares for stricter set type checks on updates in a follow up
patch.

Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
---
 include/net/netfilter/nf_tables.h | 12 +++++++
 net/netfilter/nf_tables_api.c     | 58 +++++++++++++++----------------
 2 files changed, 40 insertions(+), 30 deletions(-)

diff --git a/include/net/netfilter/nf_tables.h b/include/net/netfilter/nf_tables.h
index e69ce23566eab..4957b4775757b 100644
--- a/include/net/netfilter/nf_tables.h
+++ b/include/net/netfilter/nf_tables.h
@@ -312,17 +312,29 @@ struct nft_set_iter {
 /**
  *	struct nft_set_desc - description of set elements
  *
+ *	@ktype: key type
  *	@klen: key length
+ *	@dtype: data type
  *	@dlen: data length
+ *	@objtype: object type
+ *	@flags: flags
  *	@size: number of set elements
+ *	@policy: set policy
+ *	@gc_int: garbage collector interval
  *	@field_len: length of each field in concatenation, bytes
  *	@field_count: number of concatenated fields in element
  *	@expr: set must support for expressions
  */
 struct nft_set_desc {
+	u32			ktype;
 	unsigned int		klen;
+	u32			dtype;
 	unsigned int		dlen;
+	u32			objtype;
 	unsigned int		size;
+	u32			policy;
+	u32			gc_int;
+	u64			timeout;
 	u8			field_len[NFT_REG32_COUNT];
 	u8			field_count;
 	bool			expr;
diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c
index 832b881f7c174..1deecc1a6c003 100644
--- a/net/netfilter/nf_tables_api.c
+++ b/net/netfilter/nf_tables_api.c
@@ -3780,8 +3780,7 @@ static bool nft_set_ops_candidate(const struct nft_set_type *type, u32 flags)
 static const struct nft_set_ops *
 nft_select_set_ops(const struct nft_ctx *ctx,
 		   const struct nlattr * const nla[],
-		   const struct nft_set_desc *desc,
-		   enum nft_set_policies policy)
+		   const struct nft_set_desc *desc)
 {
 	struct nftables_pernet *nft_net = nft_pernet(ctx->net);
 	const struct nft_set_ops *ops, *bops;
@@ -3810,7 +3809,7 @@ nft_select_set_ops(const struct nft_ctx *ctx,
 		if (!ops->estimate(desc, flags, &est))
 			continue;
 
-		switch (policy) {
+		switch (desc->policy) {
 		case NFT_SET_POL_PERFORMANCE:
 			if (est.lookup < best.lookup)
 				break;
@@ -4392,7 +4391,6 @@ static int nf_tables_set_desc_parse(struct nft_set_desc *desc,
 static int nf_tables_newset(struct sk_buff *skb, const struct nfnl_info *info,
 			    const struct nlattr * const nla[])
 {
-	u32 ktype, dtype, flags, policy, gc_int, objtype;
 	struct netlink_ext_ack *extack = info->extack;
 	u8 genmask = nft_genmask_next(info->net);
 	u8 family = info->nfmsg->nfgen_family;
@@ -4405,10 +4403,10 @@ static int nf_tables_newset(struct sk_buff *skb, const struct nfnl_info *info,
 	struct nft_set *set;
 	struct nft_ctx ctx;
 	size_t alloc_size;
-	u64 timeout;
 	char *name;
 	int err, i;
 	u16 udlen;
+	u32 flags;
 	u64 size;
 
 	if (nla[NFTA_SET_TABLE] == NULL ||
@@ -4419,10 +4417,10 @@ static int nf_tables_newset(struct sk_buff *skb, const struct nfnl_info *info,
 
 	memset(&desc, 0, sizeof(desc));
 
-	ktype = NFT_DATA_VALUE;
+	desc.ktype = NFT_DATA_VALUE;
 	if (nla[NFTA_SET_KEY_TYPE] != NULL) {
-		ktype = ntohl(nla_get_be32(nla[NFTA_SET_KEY_TYPE]));
-		if ((ktype & NFT_DATA_RESERVED_MASK) == NFT_DATA_RESERVED_MASK)
+		desc.ktype = ntohl(nla_get_be32(nla[NFTA_SET_KEY_TYPE]));
+		if ((desc.ktype & NFT_DATA_RESERVED_MASK) == NFT_DATA_RESERVED_MASK)
 			return -EINVAL;
 	}
 
@@ -4447,17 +4445,17 @@ static int nf_tables_newset(struct sk_buff *skb, const struct nfnl_info *info,
 			return -EOPNOTSUPP;
 	}
 
-	dtype = 0;
+	desc.dtype = 0;
 	if (nla[NFTA_SET_DATA_TYPE] != NULL) {
 		if (!(flags & NFT_SET_MAP))
 			return -EINVAL;
 
-		dtype = ntohl(nla_get_be32(nla[NFTA_SET_DATA_TYPE]));
-		if ((dtype & NFT_DATA_RESERVED_MASK) == NFT_DATA_RESERVED_MASK &&
-		    dtype != NFT_DATA_VERDICT)
+		desc.dtype = ntohl(nla_get_be32(nla[NFTA_SET_DATA_TYPE]));
+		if ((desc.dtype & NFT_DATA_RESERVED_MASK) == NFT_DATA_RESERVED_MASK &&
+		    desc.dtype != NFT_DATA_VERDICT)
 			return -EINVAL;
 
-		if (dtype != NFT_DATA_VERDICT) {
+		if (desc.dtype != NFT_DATA_VERDICT) {
 			if (nla[NFTA_SET_DATA_LEN] == NULL)
 				return -EINVAL;
 			desc.dlen = ntohl(nla_get_be32(nla[NFTA_SET_DATA_LEN]));
@@ -4472,34 +4470,34 @@ static int nf_tables_newset(struct sk_buff *skb, const struct nfnl_info *info,
 		if (!(flags & NFT_SET_OBJECT))
 			return -EINVAL;
 
-		objtype = ntohl(nla_get_be32(nla[NFTA_SET_OBJ_TYPE]));
-		if (objtype == NFT_OBJECT_UNSPEC ||
-		    objtype > NFT_OBJECT_MAX)
+		desc.objtype = ntohl(nla_get_be32(nla[NFTA_SET_OBJ_TYPE]));
+		if (desc.objtype == NFT_OBJECT_UNSPEC ||
+		    desc.objtype > NFT_OBJECT_MAX)
 			return -EOPNOTSUPP;
 	} else if (flags & NFT_SET_OBJECT)
 		return -EINVAL;
 	else
-		objtype = NFT_OBJECT_UNSPEC;
+		desc.objtype = NFT_OBJECT_UNSPEC;
 
-	timeout = 0;
+	desc.timeout = 0;
 	if (nla[NFTA_SET_TIMEOUT] != NULL) {
 		if (!(flags & NFT_SET_TIMEOUT))
 			return -EINVAL;
 
-		err = nf_msecs_to_jiffies64(nla[NFTA_SET_TIMEOUT], &timeout);
+		err = nf_msecs_to_jiffies64(nla[NFTA_SET_TIMEOUT], &desc.timeout);
 		if (err)
 			return err;
 	}
-	gc_int = 0;
+	desc.gc_int = 0;
 	if (nla[NFTA_SET_GC_INTERVAL] != NULL) {
 		if (!(flags & NFT_SET_TIMEOUT))
 			return -EINVAL;
-		gc_int = ntohl(nla_get_be32(nla[NFTA_SET_GC_INTERVAL]));
+		desc.gc_int = ntohl(nla_get_be32(nla[NFTA_SET_GC_INTERVAL]));
 	}
 
-	policy = NFT_SET_POL_PERFORMANCE;
+	desc.policy = NFT_SET_POL_PERFORMANCE;
 	if (nla[NFTA_SET_POLICY] != NULL)
-		policy = ntohl(nla_get_be32(nla[NFTA_SET_POLICY]));
+		desc.policy = ntohl(nla_get_be32(nla[NFTA_SET_POLICY]));
 
 	if (nla[NFTA_SET_DESC] != NULL) {
 		err = nf_tables_set_desc_parse(&desc, nla[NFTA_SET_DESC]);
@@ -4544,7 +4542,7 @@ static int nf_tables_newset(struct sk_buff *skb, const struct nfnl_info *info,
 	if (!(info->nlh->nlmsg_flags & NLM_F_CREATE))
 		return -ENOENT;
 
-	ops = nft_select_set_ops(&ctx, nla, &desc, policy);
+	ops = nft_select_set_ops(&ctx, nla, &desc);
 	if (IS_ERR(ops))
 		return PTR_ERR(ops);
 
@@ -4584,18 +4582,18 @@ static int nf_tables_newset(struct sk_buff *skb, const struct nfnl_info *info,
 	set->table = table;
 	write_pnet(&set->net, net);
 	set->ops = ops;
-	set->ktype = ktype;
+	set->ktype = desc.ktype;
 	set->klen = desc.klen;
-	set->dtype = dtype;
-	set->objtype = objtype;
+	set->dtype = desc.dtype;
+	set->objtype = desc.objtype;
 	set->dlen = desc.dlen;
 	set->flags = flags;
 	set->size = desc.size;
-	set->policy = policy;
+	set->policy = desc.policy;
 	set->udlen = udlen;
 	set->udata = udata;
-	set->timeout = timeout;
-	set->gc_int = gc_int;
+	set->timeout = desc.timeout;
+	set->gc_int = desc.gc_int;
 
 	set->field_count = desc.field_count;
 	for (i = 0; i < desc.field_count; i++)
-- 
GitLab


From a8fe4154fa5a1bae590b243ed60f871e5a5e1378 Mon Sep 17 00:00:00 2001
From: Pablo Neira Ayuso <pablo@netfilter.org>
Date: Mon, 19 Dec 2022 18:00:10 +0100
Subject: [PATCH 545/875] netfilter: nf_tables: add function to create set
 stateful expressions

Add a helper function to allocate and initialize the stateful expressions
that are defined in a set.

This patch allows to reuse this code from the set update path, to check
that type of the update matches the existing set in the kernel.

Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
---
 net/netfilter/nf_tables_api.c | 106 ++++++++++++++++++++++------------
 1 file changed, 68 insertions(+), 38 deletions(-)

diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c
index 1deecc1a6c003..b9b0ae29f5f60 100644
--- a/net/netfilter/nf_tables_api.c
+++ b/net/netfilter/nf_tables_api.c
@@ -4388,6 +4388,59 @@ static int nf_tables_set_desc_parse(struct nft_set_desc *desc,
 	return err;
 }
 
+static int nft_set_expr_alloc(struct nft_ctx *ctx, struct nft_set *set,
+			      const struct nlattr * const *nla,
+			      struct nft_expr **exprs, int *num_exprs,
+			      u32 flags)
+{
+	struct nft_expr *expr;
+	int err, i;
+
+	if (nla[NFTA_SET_EXPR]) {
+		expr = nft_set_elem_expr_alloc(ctx, set, nla[NFTA_SET_EXPR]);
+		if (IS_ERR(expr)) {
+			err = PTR_ERR(expr);
+			goto err_set_expr_alloc;
+		}
+		exprs[0] = expr;
+		(*num_exprs)++;
+	} else if (nla[NFTA_SET_EXPRESSIONS]) {
+		struct nlattr *tmp;
+		int left;
+
+		if (!(flags & NFT_SET_EXPR)) {
+			err = -EINVAL;
+			goto err_set_expr_alloc;
+		}
+		i = 0;
+		nla_for_each_nested(tmp, nla[NFTA_SET_EXPRESSIONS], left) {
+			if (i == NFT_SET_EXPR_MAX) {
+				err = -E2BIG;
+				goto err_set_expr_alloc;
+			}
+			if (nla_type(tmp) != NFTA_LIST_ELEM) {
+				err = -EINVAL;
+				goto err_set_expr_alloc;
+			}
+			expr = nft_set_elem_expr_alloc(ctx, set, tmp);
+			if (IS_ERR(expr)) {
+				err = PTR_ERR(expr);
+				goto err_set_expr_alloc;
+			}
+			exprs[i++] = expr;
+			(*num_exprs)++;
+		}
+	}
+
+	return 0;
+
+err_set_expr_alloc:
+	for (i = 0; i < *num_exprs; i++)
+		nft_expr_destroy(ctx, exprs[i]);
+
+	return err;
+}
+
 static int nf_tables_newset(struct sk_buff *skb, const struct nfnl_info *info,
 			    const struct nlattr * const nla[])
 {
@@ -4395,7 +4448,6 @@ static int nf_tables_newset(struct sk_buff *skb, const struct nfnl_info *info,
 	u8 genmask = nft_genmask_next(info->net);
 	u8 family = info->nfmsg->nfgen_family;
 	const struct nft_set_ops *ops;
-	struct nft_expr *expr = NULL;
 	struct net *net = info->net;
 	struct nft_set_desc desc;
 	struct nft_table *table;
@@ -4403,6 +4455,7 @@ static int nf_tables_newset(struct sk_buff *skb, const struct nfnl_info *info,
 	struct nft_set *set;
 	struct nft_ctx ctx;
 	size_t alloc_size;
+	int num_exprs = 0;
 	char *name;
 	int err, i;
 	u16 udlen;
@@ -4529,6 +4582,8 @@ static int nf_tables_newset(struct sk_buff *skb, const struct nfnl_info *info,
 			return PTR_ERR(set);
 		}
 	} else {
+		struct nft_expr *exprs[NFT_SET_EXPR_MAX] = {};
+
 		if (info->nlh->nlmsg_flags & NLM_F_EXCL) {
 			NL_SET_BAD_ATTR(extack, nla[NFTA_SET_NAME]);
 			return -EEXIST;
@@ -4536,6 +4591,13 @@ static int nf_tables_newset(struct sk_buff *skb, const struct nfnl_info *info,
 		if (info->nlh->nlmsg_flags & NLM_F_REPLACE)
 			return -EOPNOTSUPP;
 
+		err = nft_set_expr_alloc(&ctx, set, nla, exprs, &num_exprs, flags);
+		if (err < 0)
+			return err;
+
+		for (i = 0; i < num_exprs; i++)
+			nft_expr_destroy(&ctx, exprs[i]);
+
 		return 0;
 	}
 
@@ -4603,43 +4665,11 @@ static int nf_tables_newset(struct sk_buff *skb, const struct nfnl_info *info,
 	if (err < 0)
 		goto err_set_init;
 
-	if (nla[NFTA_SET_EXPR]) {
-		expr = nft_set_elem_expr_alloc(&ctx, set, nla[NFTA_SET_EXPR]);
-		if (IS_ERR(expr)) {
-			err = PTR_ERR(expr);
-			goto err_set_expr_alloc;
-		}
-		set->exprs[0] = expr;
-		set->num_exprs++;
-	} else if (nla[NFTA_SET_EXPRESSIONS]) {
-		struct nft_expr *expr;
-		struct nlattr *tmp;
-		int left;
-
-		if (!(flags & NFT_SET_EXPR)) {
-			err = -EINVAL;
-			goto err_set_expr_alloc;
-		}
-		i = 0;
-		nla_for_each_nested(tmp, nla[NFTA_SET_EXPRESSIONS], left) {
-			if (i == NFT_SET_EXPR_MAX) {
-				err = -E2BIG;
-				goto err_set_expr_alloc;
-			}
-			if (nla_type(tmp) != NFTA_LIST_ELEM) {
-				err = -EINVAL;
-				goto err_set_expr_alloc;
-			}
-			expr = nft_set_elem_expr_alloc(&ctx, set, tmp);
-			if (IS_ERR(expr)) {
-				err = PTR_ERR(expr);
-				goto err_set_expr_alloc;
-			}
-			set->exprs[i++] = expr;
-			set->num_exprs++;
-		}
-	}
+	err = nft_set_expr_alloc(&ctx, set, nla, set->exprs, &num_exprs, flags);
+	if (err < 0)
+		goto err_set_destroy;
 
+	set->num_exprs = num_exprs;
 	set->handle = nf_tables_alloc_handle(table);
 
 	err = nft_trans_set_add(&ctx, NFT_MSG_NEWSET, set);
@@ -4653,7 +4683,7 @@ static int nf_tables_newset(struct sk_buff *skb, const struct nfnl_info *info,
 err_set_expr_alloc:
 	for (i = 0; i < set->num_exprs; i++)
 		nft_expr_destroy(&ctx, set->exprs[i]);
-
+err_set_destroy:
 	ops->destroy(set);
 err_set_init:
 	kfree(set->name);
-- 
GitLab


From f6594c372afd5cec8b1e9ee9ea8f8819d59c6fb1 Mon Sep 17 00:00:00 2001
From: Pablo Neira Ayuso <pablo@netfilter.org>
Date: Mon, 19 Dec 2022 20:09:00 +0100
Subject: [PATCH 546/875] netfilter: nf_tables: perform type checking for
 existing sets

If a ruleset declares a set name that matches an existing set in the
kernel, then validate that this declaration really refers to the same
set, otherwise bail out with EEXIST.

Currently, the kernel reports success when adding a set that already
exists in the kernel. This usually results in EINVAL errors at a later
stage, when the user adds elements to the set, if the set declaration
mismatches the existing set representation in the kernel.

Add a new function to check that the set declaration really refers to
the same existing set in the kernel.

Fixes: 96518518cc41 ("netfilter: add nftables")
Reported-by: Florian Westphal <fw@strlen.de>
Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
---
 net/netfilter/nf_tables_api.c | 36 ++++++++++++++++++++++++++++++++++-
 1 file changed, 35 insertions(+), 1 deletion(-)

diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c
index b9b0ae29f5f60..319887f4d3ef7 100644
--- a/net/netfilter/nf_tables_api.c
+++ b/net/netfilter/nf_tables_api.c
@@ -4441,6 +4441,34 @@ err_set_expr_alloc:
 	return err;
 }
 
+static bool nft_set_is_same(const struct nft_set *set,
+			    const struct nft_set_desc *desc,
+			    struct nft_expr *exprs[], u32 num_exprs, u32 flags)
+{
+	int i;
+
+	if (set->ktype != desc->ktype ||
+	    set->dtype != desc->dtype ||
+	    set->flags != flags ||
+	    set->klen != desc->klen ||
+	    set->dlen != desc->dlen ||
+	    set->field_count != desc->field_count ||
+	    set->num_exprs != num_exprs)
+		return false;
+
+	for (i = 0; i < desc->field_count; i++) {
+		if (set->field_len[i] != desc->field_len[i])
+			return false;
+	}
+
+	for (i = 0; i < num_exprs; i++) {
+		if (set->exprs[i]->ops != exprs[i]->ops)
+			return false;
+	}
+
+	return true;
+}
+
 static int nf_tables_newset(struct sk_buff *skb, const struct nfnl_info *info,
 			    const struct nlattr * const nla[])
 {
@@ -4595,10 +4623,16 @@ static int nf_tables_newset(struct sk_buff *skb, const struct nfnl_info *info,
 		if (err < 0)
 			return err;
 
+		err = 0;
+		if (!nft_set_is_same(set, &desc, exprs, num_exprs, flags)) {
+			NL_SET_BAD_ATTR(extack, nla[NFTA_SET_NAME]);
+			err = -EEXIST;
+		}
+
 		for (i = 0; i < num_exprs; i++)
 			nft_expr_destroy(&ctx, exprs[i]);
 
-		return 0;
+		return err;
 	}
 
 	if (!(info->nlh->nlmsg_flags & NLM_F_CREATE))
-- 
GitLab


From 7c0846125358f991d83f34ddde52956b196db3de Mon Sep 17 00:00:00 2001
From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Wed, 21 Dec 2022 08:56:43 -0800
Subject: [PATCH 547/875] m68k: remove broken strcmp implementation

The m68 hand-written assembler version of strcmp() has always been
broken: it returns the difference between the first non-matching byte
done as a 8-bit subtraction.

That is _almost_ right, but is broken for the overflow case.  The
strcmp() function should indeed return the sign of the difference
between the first byte that differs, but the subtraction needs to be
done in a wider type than 'char'.  Otherwise the ordering isn't actually
stable.

This went unnoticed for basically forever, because nobody ever cares
about non-US-ASCII orderings in the kernel (in fact, most users only
care about "exact match or not"), so overflows don't really happen in
practice, even if it was very very wrong.

But that mostly unnoticeable bug becomes very noticeable by the recent
change to make 'char' be unsigned in the kernel across all architectures
(commit 3bc753c06dd0: "kbuild: treat char as always unsigned"). Because
the code not only did the subtraction in the wrong type width, it also
used 'char' to then make the compiler expand the result from an 8-bit
difference to the 'int' return value.

So now with an unsigned char that incorrect arithmetic width was then
not even sign-expanded, and always returned just a positive integer.

We could re-instate the old broken code by just turning the 'char' into
'signed char' as has been done elsewhere where people depended on the
signedness of 'char', but since the whole function was broken to begin
with, and we have a non-broken default fallback implementation, let's
just remove this broken function entirely.

Reported-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/lkml/20221221145332.GA2399037@roeck-us.net/
Cc: Jason Donenfeld <Jason@zx2c4.com>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
---
 arch/m68k/include/asm/string.h | 20 --------------------
 1 file changed, 20 deletions(-)

diff --git a/arch/m68k/include/asm/string.h b/arch/m68k/include/asm/string.h
index f759d944c4499..f0f5021d6327d 100644
--- a/arch/m68k/include/asm/string.h
+++ b/arch/m68k/include/asm/string.h
@@ -38,26 +38,6 @@ static inline char *strncpy(char *dest, const char *src, size_t n)
 	return xdest;
 }
 
-#ifndef CONFIG_COLDFIRE
-#define __HAVE_ARCH_STRCMP
-static inline int strcmp(const char *cs, const char *ct)
-{
-	char res;
-
-	asm ("\n"
-		"1:	move.b	(%0)+,%2\n"	/* get *cs */
-		"	cmp.b	(%1)+,%2\n"	/* compare a byte */
-		"	jne	2f\n"		/* not equal, break out */
-		"	tst.b	%2\n"		/* at end of cs? */
-		"	jne	1b\n"		/* no, keep going */
-		"	jra	3f\n"		/* strings are equal */
-		"2:	sub.b	-(%1),%2\n"	/* *cs - *ct */
-		"3:"
-		: "+a" (cs), "+a" (ct), "=d" (res));
-	return res;
-}
-#endif /* CONFIG_COLDFIRE */
-
 #define __HAVE_ARCH_MEMMOVE
 extern void *memmove(void *, const void *, __kernel_size_t);
 
-- 
GitLab


From b4a7eff93c39f985b33ac114f83ac5b325f42151 Mon Sep 17 00:00:00 2001
From: Namhyung Kim <namhyung@kernel.org>
Date: Mon, 19 Dec 2022 12:17:28 -0800
Subject: [PATCH 548/875] perf lock contention: Add -Y/--type-filter option

The -Y/--type-filter option is to filter the result for specific lock
types only.  It can accept comma-separated values.  Note that it would
accept type names like one in the output.  spinlock, mutex, rwsem:R and
so on.

For RW-variant lock types, it converts the name to the both variants.
In other words, "rwsem" is same as "rwsem:R,rwsem:W".  Also note that
"mutex" has two different encoding - one for sleeping wait, another for
optimistic spinning.  Add "mutex-spin" entry for the lock_type_table so
that we can add it for "mutex" under the table.

  $ sudo ./perf lock record -a -- ./perf bench sched messaging

  $ sudo ./perf lock con -E 5 -Y spinlock
   contended  total wait   max wait  avg wait      type  caller

         802     1.26 ms   11.73 us   1.58 us  spinlock  __wake_up_common_lock+0x62
          13   787.16 us  105.44 us  60.55 us  spinlock  remove_wait_queue+0x14
          12   612.96 us   78.70 us  51.08 us  spinlock  prepare_to_wait+0x27
         114   340.68 us   12.61 us   2.99 us  spinlock  try_to_wake_up+0x1f5
          83   226.38 us    9.15 us   2.73 us  spinlock  folio_lruvec_lock_irqsave+0x5e

Committer notes:

Make get_type_flag() return UINT_MAX for error instad of -1UL, as that
function returns 'unsigned int' and we store the value on a 'unsigned
int' 'flags' variable which makes clang unhappy:

  35    98.23 fedora:37                     : FAIL clang version 15.0.6 (Fedora 15.0.6-1.fc37)
    builtin-lock.c:2012:14: error: result of comparison of constant 18446744073709551615 with expression of type 'unsigned int' is always true [-Werror,-Wtautological-constant-out-of-range-compare]
                            if (flags != -1UL) {
                                ~~~~~ ^  ~~~~
    builtin-lock.c:2021:14: error: result of comparison of constant 18446744073709551615 with expression of type 'unsigned int' is always true [-Werror,-Wtautological-constant-out-of-range-compare]
                            if (flags != -1UL) {
                                ~~~~~ ^  ~~~~
    builtin-lock.c:2037:14: error: result of comparison of constant 18446744073709551615 with expression of type 'unsigned int' is always true [-Werror,-Wtautological-constant-out-of-range-compare]
                            if (flags != -1UL) {
                                ~~~~~ ^  ~~~~
    3 errors generated.

Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Blake Jones <blakejones@google.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Song Liu <song@kernel.org>
Cc: bpf@vger.kernel.org
Link: https://lore.kernel.org/r/20221219201732.460111-3-namhyung@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/Documentation/perf-lock.txt |  23 +++--
 tools/perf/builtin-lock.c              | 116 ++++++++++++++++++++++++-
 tools/perf/util/lock-contention.h      |   5 ++
 3 files changed, 136 insertions(+), 8 deletions(-)

diff --git a/tools/perf/Documentation/perf-lock.txt b/tools/perf/Documentation/perf-lock.txt
index 38e79d45e4265..dea04ad5c28ea 100644
--- a/tools/perf/Documentation/perf-lock.txt
+++ b/tools/perf/Documentation/perf-lock.txt
@@ -143,25 +143,25 @@ CONTENTION OPTIONS
         System-wide collection from all CPUs.
 
 -C::
---cpu::
+--cpu=<value>::
 	Collect samples only on the list of CPUs provided. Multiple CPUs can be
 	provided as a comma-separated list with no space: 0,1. Ranges of CPUs
 	are specified with -: 0-2.  Default is to monitor all CPUs.
 
 -p::
---pid=::
+--pid=<value>::
 	Record events on existing process ID (comma separated list).
 
---tid=::
+--tid=<value>::
         Record events on existing thread ID (comma separated list).
 
---map-nr-entries::
+--map-nr-entries=<value>::
 	Maximum number of BPF map entries (default: 10240).
 
---max-stack::
+--max-stack=<value>::
 	Maximum stack depth when collecting lock contention (default: 8).
 
---stack-skip
+--stack-skip=<value>::
 	Number of stack depth to skip when finding a lock caller (default: 3).
 
 -E::
@@ -172,6 +172,17 @@ CONTENTION OPTIONS
 --lock-addr::
 	Show lock contention stat by address
 
+-Y::
+--type-filter=<value>::
+	Show lock contention only for given lock types (comma separated list).
+	Available values are:
+	  semaphore, spinlock, rwlock, rwlock:R, rwlock:W, rwsem, rwsem:R, rwsem:W,
+	  rtmutex, rwlock-rt, rwlock-rt:R, rwlock-rt:W, pcpu-sem, pcpu-sem:R, pcpu-sem:W,
+	  mutex
+
+	Note that RW-variant of locks have :R and :W suffix.  Names without the
+	suffix are shortcuts for the both variants.  Ex) rwsem = rwsem:R + rwsem:W.
+
 
 SEE ALSO
 --------
diff --git a/tools/perf/builtin-lock.c b/tools/perf/builtin-lock.c
index 311f83bc5ddb8..c73d02082cdf4 100644
--- a/tools/perf/builtin-lock.c
+++ b/tools/perf/builtin-lock.c
@@ -63,6 +63,8 @@ static int max_stack_depth = CONTENTION_STACK_DEPTH;
 static int stack_skip = CONTENTION_STACK_SKIP;
 static int print_nr_entries = INT_MAX / 2;
 
+static struct lock_filter filters;
+
 static enum lock_aggr_mode aggr_mode = LOCK_AGGR_ADDR;
 
 static struct thread_stat *thread_stat_find(u32 tid)
@@ -990,8 +992,9 @@ static int report_lock_contention_begin_event(struct evsel *evsel,
 	struct thread_stat *ts;
 	struct lock_seq_stat *seq;
 	u64 addr = evsel__intval(evsel, sample, "lock_addr");
+	unsigned int flags = evsel__intval(evsel, sample, "flags");
 	u64 key;
-	int ret;
+	int i, ret;
 
 	ret = get_key_by_aggr_mode(&key, addr, evsel, sample);
 	if (ret < 0)
@@ -1001,7 +1004,6 @@ static int report_lock_contention_begin_event(struct evsel *evsel,
 	if (!ls) {
 		char buf[128];
 		const char *name = "";
-		unsigned int flags = evsel__intval(evsel, sample, "flags");
 		struct machine *machine = &session->machines.host;
 		struct map *kmap;
 		struct symbol *sym;
@@ -1036,6 +1038,20 @@ static int report_lock_contention_begin_event(struct evsel *evsel,
 		}
 	}
 
+	if (filters.nr_types) {
+		bool found = false;
+
+		for (i = 0; i < filters.nr_types; i++) {
+			if (flags == filters.types[i]) {
+				found = true;
+				break;
+			}
+		}
+
+		if (!found)
+			return 0;
+	}
+
 	ts = thread_stat_findnew(sample->tid);
 	if (!ts)
 		return -ENOMEM;
@@ -1454,6 +1470,8 @@ static const struct {
 	{ LCB_F_PERCPU | LCB_F_WRITE,	"pcpu-sem:W" },
 	{ LCB_F_MUTEX,			"mutex" },
 	{ LCB_F_MUTEX | LCB_F_SPIN,	"mutex" },
+	/* alias for get_type_flag() */
+	{ LCB_F_MUTEX | LCB_F_SPIN,	"mutex-spin" },
 };
 
 static const char *get_type_str(unsigned int flags)
@@ -1465,6 +1483,21 @@ static const char *get_type_str(unsigned int flags)
 	return "unknown";
 }
 
+static unsigned int get_type_flag(const char *str)
+{
+	for (unsigned int i = 0; i < ARRAY_SIZE(lock_type_table); i++) {
+		if (!strcmp(lock_type_table[i].name, str))
+			return lock_type_table[i].flags;
+	}
+	return UINT_MAX;
+}
+
+static void lock_filter_finish(void)
+{
+	zfree(&filters.types);
+	filters.nr_types = 0;
+}
+
 static void sort_contention_result(void)
 {
 	sort_result();
@@ -1507,6 +1540,9 @@ static void print_contention_result(struct lock_contention *con)
 		if (st->broken)
 			bad++;
 
+		if (!st->wait_time_total)
+			continue;
+
 		list_for_each_entry(key, &lock_keys, list) {
 			key->print(key, st);
 			pr_info(" ");
@@ -1753,6 +1789,7 @@ static int __cmd_contention(int argc, const char **argv)
 	print_contention_result(&con);
 
 out_delete:
+	lock_filter_finish();
 	evlist__delete(con.evlist);
 	lock_contention_finish();
 	perf_session__delete(session);
@@ -1884,6 +1921,79 @@ static int parse_max_stack(const struct option *opt, const char *str,
 	return 0;
 }
 
+static bool add_lock_type(unsigned int flags)
+{
+	unsigned int *tmp;
+
+	tmp = realloc(filters.types, (filters.nr_types + 1) * sizeof(*filters.types));
+	if (tmp == NULL)
+		return false;
+
+	tmp[filters.nr_types++] = flags;
+	filters.types = tmp;
+	return true;
+}
+
+static int parse_lock_type(const struct option *opt __maybe_unused, const char *str,
+			   int unset __maybe_unused)
+{
+	char *s, *tmp, *tok;
+	int ret = 0;
+
+	s = strdup(str);
+	if (s == NULL)
+		return -1;
+
+	for (tok = strtok_r(s, ", ", &tmp); tok; tok = strtok_r(NULL, ", ", &tmp)) {
+		unsigned int flags = get_type_flag(tok);
+
+		if (flags == -1U) {
+			char buf[32];
+
+			if (strchr(tok, ':'))
+			    continue;
+
+			/* try :R and :W suffixes for rwlock, rwsem, ... */
+			scnprintf(buf, sizeof(buf), "%s:R", tok);
+			flags = get_type_flag(buf);
+			if (flags != UINT_MAX) {
+				if (!add_lock_type(flags)) {
+					ret = -1;
+					break;
+				}
+			}
+
+			scnprintf(buf, sizeof(buf), "%s:W", tok);
+			flags = get_type_flag(buf);
+			if (flags != UINT_MAX) {
+				if (!add_lock_type(flags)) {
+					ret = -1;
+					break;
+				}
+			}
+			continue;
+		}
+
+		if (!add_lock_type(flags)) {
+			ret = -1;
+			break;
+		}
+
+		if (!strcmp(tok, "mutex")) {
+			flags = get_type_flag("mutex-spin");
+			if (flags != UINT_MAX) {
+				if (!add_lock_type(flags)) {
+					ret = -1;
+					break;
+				}
+			}
+		}
+	}
+
+	free(s);
+	return ret;
+}
+
 int cmd_lock(int argc, const char **argv)
 {
 	const struct option lock_options[] = {
@@ -1947,6 +2057,8 @@ int cmd_lock(int argc, const char **argv)
 		    "Default: " __stringify(CONTENTION_STACK_SKIP)),
 	OPT_INTEGER('E', "entries", &print_nr_entries, "display this many functions"),
 	OPT_BOOLEAN('l', "lock-addr", &show_lock_addrs, "show lock stats by address"),
+	OPT_CALLBACK('Y', "type-filter", NULL, "FLAGS",
+		     "Filter specific type of locks", parse_lock_type),
 	OPT_PARENT(lock_options)
 	};
 
diff --git a/tools/perf/util/lock-contention.h b/tools/perf/util/lock-contention.h
index 47fd47fb56c1d..d5b75b222d8eb 100644
--- a/tools/perf/util/lock-contention.h
+++ b/tools/perf/util/lock-contention.h
@@ -5,6 +5,11 @@
 #include <linux/list.h>
 #include <linux/rbtree.h>
 
+struct lock_filter {
+	int			nr_types;
+	unsigned int		*types;
+};
+
 struct lock_stat {
 	struct hlist_node	hash_entry;
 	struct rb_node		rb;		/* used for sorting */
-- 
GitLab


From 529772c4df286159fea453957a6052e20b90e8a8 Mon Sep 17 00:00:00 2001
From: Namhyung Kim <namhyung@kernel.org>
Date: Mon, 19 Dec 2022 12:17:29 -0800
Subject: [PATCH 549/875] perf lock contention: Support lock type filtering for
 BPF

Likewise, add type_filter BPF hash map and check it when user gave a
lock type filter.

  $ sudo ./perf lock con -ab -Y rwlock -- ./perf bench sched messaging
  # Running 'sched/messaging' benchmark:
  # 20 sender and receiver processes per group
  # 10 groups == 400 processes run

       Total time: 0.203 [sec]
   contended  total wait  max wait  avg wait       type  caller

          15   156.19 us  19.45 us  10.41 us   rwlock:W  do_exit+0x36d
           1    11.12 us  11.12 us  11.12 us   rwlock:R  do_wait+0x8b
           1     5.09 us   5.09 us   5.09 us   rwlock:W  release_task+0x6e

Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Blake Jones <blakejones@google.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Song Liu <song@kernel.org>
Cc: bpf@vger.kernel.org
Link: https://lore.kernel.org/r/20221219201732.460111-4-namhyung@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/builtin-lock.c                     |  1 +
 tools/perf/util/bpf_lock_contention.c         | 15 ++++++++++++-
 .../perf/util/bpf_skel/lock_contention.bpf.c  | 21 +++++++++++++++++--
 tools/perf/util/lock-contention.h             |  1 +
 4 files changed, 35 insertions(+), 3 deletions(-)

diff --git a/tools/perf/builtin-lock.c b/tools/perf/builtin-lock.c
index c73d02082cdf4..171b0fb5c974d 100644
--- a/tools/perf/builtin-lock.c
+++ b/tools/perf/builtin-lock.c
@@ -1689,6 +1689,7 @@ static int __cmd_contention(int argc, const char **argv)
 		.map_nr_entries = bpf_map_entries,
 		.max_stack = max_stack_depth,
 		.stack_skip = stack_skip,
+		.filters = &filters,
 	};
 
 	session = perf_session__new(use_bpf ? NULL : &data, &eops);
diff --git a/tools/perf/util/bpf_lock_contention.c b/tools/perf/util/bpf_lock_contention.c
index df8dbb5191b43..58ac01b5a367a 100644
--- a/tools/perf/util/bpf_lock_contention.c
+++ b/tools/perf/util/bpf_lock_contention.c
@@ -20,7 +20,7 @@ static struct lock_contention_bpf *skel;
 int lock_contention_prepare(struct lock_contention *con)
 {
 	int i, fd;
-	int ncpus = 1, ntasks = 1;
+	int ncpus = 1, ntasks = 1, ntypes = 1;
 	struct evlist *evlist = con->evlist;
 	struct target *target = con->target;
 
@@ -46,9 +46,12 @@ int lock_contention_prepare(struct lock_contention *con)
 		ncpus = perf_cpu_map__nr(evlist->core.user_requested_cpus);
 	if (target__has_task(target))
 		ntasks = perf_thread_map__nr(evlist->core.threads);
+	if (con->filters->nr_types)
+		ntypes = con->filters->nr_types;
 
 	bpf_map__set_max_entries(skel->maps.cpu_filter, ncpus);
 	bpf_map__set_max_entries(skel->maps.task_filter, ntasks);
+	bpf_map__set_max_entries(skel->maps.type_filter, ntypes);
 
 	if (lock_contention_bpf__load(skel) < 0) {
 		pr_err("Failed to load lock-contention BPF skeleton\n");
@@ -90,6 +93,16 @@ int lock_contention_prepare(struct lock_contention *con)
 		bpf_map_update_elem(fd, &pid, &val, BPF_ANY);
 	}
 
+	if (con->filters->nr_types) {
+		u8 val = 1;
+
+		skel->bss->has_type = 1;
+		fd = bpf_map__fd(skel->maps.type_filter);
+
+		for (i = 0; i < con->filters->nr_types; i++)
+			bpf_map_update_elem(fd, &con->filters->types[i], &val, BPF_ANY);
+	}
+
 	/* these don't work well if in the rodata section */
 	skel->bss->stack_skip = con->stack_skip;
 	skel->bss->aggr_mode = con->aggr_mode;
diff --git a/tools/perf/util/bpf_skel/lock_contention.bpf.c b/tools/perf/util/bpf_skel/lock_contention.bpf.c
index 11b0fc7ee53b0..fb0128de7c004 100644
--- a/tools/perf/util/bpf_skel/lock_contention.bpf.c
+++ b/tools/perf/util/bpf_skel/lock_contention.bpf.c
@@ -62,10 +62,18 @@ struct {
 	__uint(max_entries, 1);
 } task_filter SEC(".maps");
 
+struct {
+	__uint(type, BPF_MAP_TYPE_HASH);
+	__uint(key_size, sizeof(__u32));
+	__uint(value_size, sizeof(__u8));
+	__uint(max_entries, 1);
+} type_filter SEC(".maps");
+
 /* control flags */
 int enabled;
 int has_cpu;
 int has_task;
+int has_type;
 int stack_skip;
 
 /* determine the key of lock stat */
@@ -74,7 +82,7 @@ int aggr_mode;
 /* error stat */
 int lost;
 
-static inline int can_record(void)
+static inline int can_record(u64 *ctx)
 {
 	if (has_cpu) {
 		__u32 cpu = bpf_get_smp_processor_id();
@@ -94,6 +102,15 @@ static inline int can_record(void)
 			return 0;
 	}
 
+	if (has_type) {
+		__u8 *ok;
+		__u32 flags = (__u32)ctx[1];
+
+		ok = bpf_map_lookup_elem(&type_filter, &flags);
+		if (!ok)
+			return 0;
+	}
+
 	return 1;
 }
 
@@ -116,7 +133,7 @@ int contention_begin(u64 *ctx)
 	__u32 pid;
 	struct tstamp_data *pelem;
 
-	if (!enabled || !can_record())
+	if (!enabled || !can_record(ctx))
 		return 0;
 
 	pid = bpf_get_current_pid_tgid();
diff --git a/tools/perf/util/lock-contention.h b/tools/perf/util/lock-contention.h
index d5b75b222d8eb..dc621386a16bc 100644
--- a/tools/perf/util/lock-contention.h
+++ b/tools/perf/util/lock-contention.h
@@ -118,6 +118,7 @@ struct lock_contention {
 	struct target *target;
 	struct machine *machine;
 	struct hlist_head *result;
+	struct lock_filter *filters;
 	unsigned long map_nr_entries;
 	int lost;
 	int max_stack;
-- 
GitLab


From 511e19b9e2112463c33a744ecb8a798056074408 Mon Sep 17 00:00:00 2001
From: Namhyung Kim <namhyung@kernel.org>
Date: Mon, 19 Dec 2022 12:17:30 -0800
Subject: [PATCH 550/875] perf lock contention: Add -L/--lock-filter option

The -L/--lock-filter option is to filter only given locks.  The locks
can be specified by address or name (if exists).

  $ sudo ./perf lock record -a  sleep 1

  $ sudo ./perf lock con -l
   contended  total wait  max wait  avg wait           address  symbol

          57     1.11 ms  42.83 us  19.54 us  ffff9f4140059000
          15   280.88 us  23.51 us  18.73 us  ffffffff9d007a40  jiffies_lock
           1    20.49 us  20.49 us  20.49 us  ffffffff9d0d50c0  rcu_state
           1     9.02 us   9.02 us   9.02 us  ffff9f41759e9ba0

  $ sudo ./perf lock con -L jiffies_lock,rcu_state
   contended  total wait  max wait  avg wait      type  caller

          15   280.88 us  23.51 us  18.73 us  spinlock  tick_sched_do_timer+0x93
           1    20.49 us  20.49 us  20.49 us  spinlock  __softirqentry_text_start+0xeb

  $ sudo ./perf lock con -L ffff9f4140059000
   contended  total wait  max wait  avg wait      type  caller

          38   779.40 us  42.83 us  20.51 us  spinlock  worker_thread+0x50
          11   216.30 us  39.87 us  19.66 us  spinlock  queue_work_on+0x39
           8   118.13 us  20.51 us  14.77 us  spinlock  kthread+0xe5

Committer testing:

  # uname -a
  Linux quaco 6.0.12-200.fc36.x86_64 #1 SMP PREEMPT_DYNAMIC Thu Dec 8 17:15:53 UTC 2022 x86_64 x86_64 x86_64 GNU/Linux
  # perf lock record
  ^C[ perf record: Woken up 1 times to write data ]
  # perf lock con -L jiffies_lock,rcu_state
   contended   total wait     max wait     avg wait         type   caller

  # perf lock con
   contended   total wait     max wait     avg wait         type   caller

           1      9.06 us      9.06 us      9.06 us     spinlock   call_timer_fn+0x24
  # perf lock con -L call
  ignore unknown symbol: call
   contended   total wait     max wait     avg wait         type   caller

           1      9.06 us      9.06 us      9.06 us     spinlock   call_timer_fn+0x24
  #

Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Tested-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Blake Jones <blakejones@google.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Song Liu <song@kernel.org>
Cc: bpf@vger.kernel.org
Link: https://lore.kernel.org/r/20221219201732.460111-5-namhyung@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/Documentation/perf-lock.txt |   4 +
 tools/perf/builtin-lock.c              | 140 +++++++++++++++++++++++--
 tools/perf/util/lock-contention.h      |   4 +
 3 files changed, 142 insertions(+), 6 deletions(-)

diff --git a/tools/perf/Documentation/perf-lock.txt b/tools/perf/Documentation/perf-lock.txt
index dea04ad5c28ea..0f9f720e599d3 100644
--- a/tools/perf/Documentation/perf-lock.txt
+++ b/tools/perf/Documentation/perf-lock.txt
@@ -183,6 +183,10 @@ CONTENTION OPTIONS
 	Note that RW-variant of locks have :R and :W suffix.  Names without the
 	suffix are shortcuts for the both variants.  Ex) rwsem = rwsem:R + rwsem:W.
 
+-L::
+--lock-filter=<value>::
+	Show lock contention only for given lock addresses or names (comma separated list).
+
 
 SEE ALSO
 --------
diff --git a/tools/perf/builtin-lock.c b/tools/perf/builtin-lock.c
index 171b0fb5c974d..718b82bfcdff9 100644
--- a/tools/perf/builtin-lock.c
+++ b/tools/perf/builtin-lock.c
@@ -32,6 +32,7 @@
 #include <semaphore.h>
 #include <math.h>
 #include <limits.h>
+#include <ctype.h>
 
 #include <linux/list.h>
 #include <linux/hash.h>
@@ -995,24 +996,52 @@ static int report_lock_contention_begin_event(struct evsel *evsel,
 	unsigned int flags = evsel__intval(evsel, sample, "flags");
 	u64 key;
 	int i, ret;
+	static bool kmap_loaded;
+	struct machine *machine = &session->machines.host;
+	struct map *kmap;
+	struct symbol *sym;
 
 	ret = get_key_by_aggr_mode(&key, addr, evsel, sample);
 	if (ret < 0)
 		return ret;
 
+	if (!kmap_loaded) {
+		unsigned long *addrs;
+
+		/* make sure it loads the kernel map to find lock symbols */
+		map__load(machine__kernel_map(machine));
+		kmap_loaded = true;
+
+		/* convert (kernel) symbols to addresses */
+		for (i = 0; i < filters.nr_syms; i++) {
+			sym = machine__find_kernel_symbol_by_name(machine,
+								  filters.syms[i],
+								  &kmap);
+			if (sym == NULL) {
+				pr_warning("ignore unknown symbol: %s\n",
+					   filters.syms[i]);
+				continue;
+			}
+
+			addrs = realloc(filters.addrs,
+					(filters.nr_addrs + 1) * sizeof(*addrs));
+			if (addrs == NULL) {
+				pr_warning("memory allocation failure\n");
+				return -ENOMEM;
+			}
+
+			addrs[filters.nr_addrs++] = kmap->unmap_ip(kmap, sym->start);
+			filters.addrs = addrs;
+		}
+	}
+
 	ls = lock_stat_find(key);
 	if (!ls) {
 		char buf[128];
 		const char *name = "";
-		struct machine *machine = &session->machines.host;
-		struct map *kmap;
-		struct symbol *sym;
 
 		switch (aggr_mode) {
 		case LOCK_AGGR_ADDR:
-			/* make sure it loads the kernel map to find lock symbols */
-			map__load(machine__kernel_map(machine));
-
 			sym = machine__find_kernel_symbol(machine, key, &kmap);
 			if (sym)
 				name = sym->name;
@@ -1052,6 +1081,20 @@ static int report_lock_contention_begin_event(struct evsel *evsel,
 			return 0;
 	}
 
+	if (filters.nr_addrs) {
+		bool found = false;
+
+		for (i = 0; i < filters.nr_addrs; i++) {
+			if (addr == filters.addrs[i]) {
+				found = true;
+				break;
+			}
+		}
+
+		if (!found)
+			return 0;
+	}
+
 	ts = thread_stat_findnew(sample->tid);
 	if (!ts)
 		return -ENOMEM;
@@ -1496,6 +1539,15 @@ static void lock_filter_finish(void)
 {
 	zfree(&filters.types);
 	filters.nr_types = 0;
+
+	zfree(&filters.addrs);
+	filters.nr_addrs = 0;
+
+	for (int i = 0; i < filters.nr_syms; i++)
+		free(filters.syms[i]);
+
+	zfree(&filters.syms);
+	filters.nr_syms = 0;
 }
 
 static void sort_contention_result(void)
@@ -1995,6 +2047,80 @@ static int parse_lock_type(const struct option *opt __maybe_unused, const char *
 	return ret;
 }
 
+static bool add_lock_addr(unsigned long addr)
+{
+	unsigned long *tmp;
+
+	tmp = realloc(filters.addrs, (filters.nr_addrs + 1) * sizeof(*filters.addrs));
+	if (tmp == NULL) {
+		pr_err("Memory allocation failure\n");
+		return false;
+	}
+
+	tmp[filters.nr_addrs++] = addr;
+	filters.addrs = tmp;
+	return true;
+}
+
+static bool add_lock_sym(char *name)
+{
+	char **tmp;
+	char *sym = strdup(name);
+
+	if (sym == NULL) {
+		pr_err("Memory allocation failure\n");
+		return false;
+	}
+
+	tmp = realloc(filters.syms, (filters.nr_syms + 1) * sizeof(*filters.syms));
+	if (tmp == NULL) {
+		pr_err("Memory allocation failure\n");
+		free(sym);
+		return false;
+	}
+
+	tmp[filters.nr_syms++] = sym;
+	filters.syms = tmp;
+	return true;
+}
+
+static int parse_lock_addr(const struct option *opt __maybe_unused, const char *str,
+			   int unset __maybe_unused)
+{
+	char *s, *tmp, *tok;
+	int ret = 0;
+	u64 addr;
+
+	s = strdup(str);
+	if (s == NULL)
+		return -1;
+
+	for (tok = strtok_r(s, ", ", &tmp); tok; tok = strtok_r(NULL, ", ", &tmp)) {
+		char *end;
+
+		addr = strtoul(tok, &end, 16);
+		if (*end == '\0') {
+			if (!add_lock_addr(addr)) {
+				ret = -1;
+				break;
+			}
+			continue;
+		}
+
+		/*
+		 * At this moment, we don't have kernel symbols.  Save the symbols
+		 * in a separate list and resolve them to addresses later.
+		 */
+		if (!add_lock_sym(tok)) {
+			ret = -1;
+			break;
+		}
+	}
+
+	free(s);
+	return ret;
+}
+
 int cmd_lock(int argc, const char **argv)
 {
 	const struct option lock_options[] = {
@@ -2060,6 +2186,8 @@ int cmd_lock(int argc, const char **argv)
 	OPT_BOOLEAN('l', "lock-addr", &show_lock_addrs, "show lock stats by address"),
 	OPT_CALLBACK('Y', "type-filter", NULL, "FLAGS",
 		     "Filter specific type of locks", parse_lock_type),
+	OPT_CALLBACK('L', "lock-filter", NULL, "ADDRS/NAMES",
+		     "Filter specific address/symbol of locks", parse_lock_addr),
 	OPT_PARENT(lock_options)
 	};
 
diff --git a/tools/perf/util/lock-contention.h b/tools/perf/util/lock-contention.h
index dc621386a16bc..b99e83fccf5c5 100644
--- a/tools/perf/util/lock-contention.h
+++ b/tools/perf/util/lock-contention.h
@@ -7,7 +7,11 @@
 
 struct lock_filter {
 	int			nr_types;
+	int			nr_addrs;
+	int			nr_syms;
 	unsigned int		*types;
+	unsigned long		*addrs;
+	char			**syms;
 };
 
 struct lock_stat {
-- 
GitLab


From 5e3febe7b7b99f942311ddfa05bb06910d06b14d Mon Sep 17 00:00:00 2001
From: Namhyung Kim <namhyung@kernel.org>
Date: Mon, 19 Dec 2022 12:17:31 -0800
Subject: [PATCH 551/875] perf lock contention: Support lock addr/name
 filtering for BPF

Likewise, add addr_filter BPF hash map and check it with the lock
address.

  $ sudo ./perf lock con -ab -L tasklist_lock -- ./perf bench sched messaging
  # Running 'sched/messaging' benchmark:
  # 20 sender and receiver processes per group
  # 10 groups == 400 processes run

       Total time: 0.169 [sec]
   contended  total wait  max wait  avg wait      type  caller

          18   174.09 us  25.31 us   9.67 us  rwlock:W  do_exit+0x36d
           5    32.34 us  10.87 us   6.47 us  rwlock:R  do_wait+0x8b
           4    15.41 us   4.73 us   3.85 us  rwlock:W  release_task+0x6e

Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Blake Jones <blakejones@google.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Song Liu <song@kernel.org>
Cc: bpf@vger.kernel.org
Link: https://lore.kernel.org/r/20221219201732.460111-6-namhyung@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/bpf_lock_contention.c         | 42 ++++++++++++++++++-
 .../perf/util/bpf_skel/lock_contention.bpf.c  | 17 ++++++++
 2 files changed, 58 insertions(+), 1 deletion(-)

diff --git a/tools/perf/util/bpf_lock_contention.c b/tools/perf/util/bpf_lock_contention.c
index 58ac01b5a367a..0236334fd69b0 100644
--- a/tools/perf/util/bpf_lock_contention.c
+++ b/tools/perf/util/bpf_lock_contention.c
@@ -20,7 +20,7 @@ static struct lock_contention_bpf *skel;
 int lock_contention_prepare(struct lock_contention *con)
 {
 	int i, fd;
-	int ncpus = 1, ntasks = 1, ntypes = 1;
+	int ncpus = 1, ntasks = 1, ntypes = 1, naddrs = 1;
 	struct evlist *evlist = con->evlist;
 	struct target *target = con->target;
 
@@ -49,9 +49,39 @@ int lock_contention_prepare(struct lock_contention *con)
 	if (con->filters->nr_types)
 		ntypes = con->filters->nr_types;
 
+	/* resolve lock name filters to addr */
+	if (con->filters->nr_syms) {
+		struct symbol *sym;
+		struct map *kmap;
+		unsigned long *addrs;
+
+		for (i = 0; i < con->filters->nr_syms; i++) {
+			sym = machine__find_kernel_symbol_by_name(con->machine,
+								  con->filters->syms[i],
+								  &kmap);
+			if (sym == NULL) {
+				pr_warning("ignore unknown symbol: %s\n",
+					   con->filters->syms[i]);
+				continue;
+			}
+
+			addrs = realloc(con->filters->addrs,
+					(con->filters->nr_addrs + 1) * sizeof(*addrs));
+			if (addrs == NULL) {
+				pr_warning("memory allocation failure\n");
+				continue;
+			}
+
+			addrs[con->filters->nr_addrs++] = kmap->unmap_ip(kmap, sym->start);
+			con->filters->addrs = addrs;
+		}
+		naddrs = con->filters->nr_addrs;
+	}
+
 	bpf_map__set_max_entries(skel->maps.cpu_filter, ncpus);
 	bpf_map__set_max_entries(skel->maps.task_filter, ntasks);
 	bpf_map__set_max_entries(skel->maps.type_filter, ntypes);
+	bpf_map__set_max_entries(skel->maps.addr_filter, naddrs);
 
 	if (lock_contention_bpf__load(skel) < 0) {
 		pr_err("Failed to load lock-contention BPF skeleton\n");
@@ -103,6 +133,16 @@ int lock_contention_prepare(struct lock_contention *con)
 			bpf_map_update_elem(fd, &con->filters->types[i], &val, BPF_ANY);
 	}
 
+	if (con->filters->nr_addrs) {
+		u8 val = 1;
+
+		skel->bss->has_addr = 1;
+		fd = bpf_map__fd(skel->maps.addr_filter);
+
+		for (i = 0; i < con->filters->nr_addrs; i++)
+			bpf_map_update_elem(fd, &con->filters->addrs[i], &val, BPF_ANY);
+	}
+
 	/* these don't work well if in the rodata section */
 	skel->bss->stack_skip = con->stack_skip;
 	skel->bss->aggr_mode = con->aggr_mode;
diff --git a/tools/perf/util/bpf_skel/lock_contention.bpf.c b/tools/perf/util/bpf_skel/lock_contention.bpf.c
index fb0128de7c004..ad0ca5d505577 100644
--- a/tools/perf/util/bpf_skel/lock_contention.bpf.c
+++ b/tools/perf/util/bpf_skel/lock_contention.bpf.c
@@ -69,11 +69,19 @@ struct {
 	__uint(max_entries, 1);
 } type_filter SEC(".maps");
 
+struct {
+	__uint(type, BPF_MAP_TYPE_HASH);
+	__uint(key_size, sizeof(__u64));
+	__uint(value_size, sizeof(__u8));
+	__uint(max_entries, 1);
+} addr_filter SEC(".maps");
+
 /* control flags */
 int enabled;
 int has_cpu;
 int has_task;
 int has_type;
+int has_addr;
 int stack_skip;
 
 /* determine the key of lock stat */
@@ -111,6 +119,15 @@ static inline int can_record(u64 *ctx)
 			return 0;
 	}
 
+	if (has_addr) {
+		__u8 *ok;
+		__u64 addr = ctx[0];
+
+		ok = bpf_map_lookup_elem(&addr_filter, &addr);
+		if (!ok)
+			return 0;
+	}
+
 	return 1;
 }
 
-- 
GitLab


From cb459c89b734f9fcfd201a6ef993c063a703ec73 Mon Sep 17 00:00:00 2001
From: Namhyung Kim <namhyung@kernel.org>
Date: Mon, 19 Dec 2022 12:17:32 -0800
Subject: [PATCH 552/875] perf test: Update 'perf lock contention' test

Add more tests for the new filters.

  $ sudo perf test contention -v
   87: kernel lock contention analysis test                            :
  --- start ---
  test child forked, pid 412379
  Testing perf lock record and perf lock contention
  Testing perf lock contention --use-bpf
  Testing perf lock record and perf lock contention at the same time
  Testing perf lock contention --threads
  Testing perf lock contention --lock-addr
  Testing perf lock contention --type-filter
  Testing perf lock contention --lock-filter
  test child finished with 0
  ---- end ----
  kernel lock contention analysis test: Ok

Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Tested-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Blake Jones <blakejones@google.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Song Liu <song@kernel.org>
Cc: bpf@vger.kernel.org
Link: https://lore.kernel.org/r/20221219201732.460111-7-namhyung@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/tests/shell/lock_contention.sh | 58 ++++++++++++++++++++++-
 1 file changed, 57 insertions(+), 1 deletion(-)

diff --git a/tools/perf/tests/shell/lock_contention.sh b/tools/perf/tests/shell/lock_contention.sh
index cc9ceb9e19caf..b05f1b1ca6c8f 100755
--- a/tools/perf/tests/shell/lock_contention.sh
+++ b/tools/perf/tests/shell/lock_contention.sh
@@ -115,7 +115,7 @@ test_aggr_addr()
 	fi
 
 	# the perf lock contention output goes to the stderr
-	perf lock con -a -b -t -E 1 -q -- perf bench sched messaging > /dev/null 2> ${result}
+	perf lock con -a -b -l -E 1 -q -- perf bench sched messaging > /dev/null 2> ${result}
 	if [ $(cat "${result}" | wc -l) != "1" ]; then
 		echo "[Fail] BPF result count is not 1:" $(cat "${result}" | wc -l)
 		err=1
@@ -123,6 +123,60 @@ test_aggr_addr()
 	fi
 }
 
+test_type_filter()
+{
+	echo "Testing perf lock contention --type-filter (w/ spinlock)"
+	perf lock contention -i ${perfdata} -Y spinlock -q 2> ${result}
+	if [ $(grep -c -v spinlock "${result}") != "0" ]; then
+		echo "[Fail] Recorded should not have non-spinlocks:" $(cat "${result}")
+		err=1
+		exit
+	fi
+
+	if ! perf lock con -b true > /dev/null 2>&1 ; then
+		return
+	fi
+
+	perf lock con -a -b -Y spinlock -q -- perf bench sched messaging > /dev/null 2> ${result}
+	if [ $(grep -c -v spinlock "${result}") != "0" ]; then
+		echo "[Fail] Recorded should not have non-spinlocks:" $(cat "${result}")
+		err=1
+		exit
+	fi
+}
+
+test_lock_filter()
+{
+	echo "Testing perf lock contention --lock-filter (w/ tasklist_lock)"
+	perf lock contention -i ${perfdata} -l -q 2> ${result}
+	if [ $(grep -c tasklist_lock "${result}") != "1" ]; then
+		echo "[Skip] Could not find 'tasklist_lock'"
+		return
+	fi
+
+	perf lock contention -i ${perfdata} -L tasklist_lock -q 2> ${result}
+
+	# find out the type of tasklist_lock
+	local type=$(head -1 "${result}" | awk '{ print $8 }' | sed -e 's/:.*//')
+
+	if [ $(grep -c -v "${type}" "${result}") != "0" ]; then
+		echo "[Fail] Recorded should not have non-${type} locks:" $(cat "${result}")
+		err=1
+		exit
+	fi
+
+	if ! perf lock con -b true > /dev/null 2>&1 ; then
+		return
+	fi
+
+	perf lock con -a -b -L tasklist_lock -q -- perf bench sched messaging > /dev/null 2> ${result}
+	if [ $(grep -c -v "${type}" "${result}") != "0" ]; then
+		echo "[Fail] Recorded should not have non-${type} locks:" $(cat "${result}")
+		err=1
+		exit
+	fi
+}
+
 check
 
 test_record
@@ -130,5 +184,7 @@ test_bpf
 test_record_concurrent
 test_aggr_task
 test_aggr_addr
+test_type_filter
+test_lock_filter
 
 exit ${err}
-- 
GitLab


From 0c0a0db87e1c159aa7a2a52bfbec0be604c65f86 Mon Sep 17 00:00:00 2001
From: Changbin Du <changbin.du@gmail.com>
Date: Sun, 18 Dec 2022 06:51:51 +0800
Subject: [PATCH 553/875] perf tools: Add .DELETE_ON_ERROR special Makefile
 target to clean up partially updated files on error.

As kbuild, this adds .DELETE_ON_ERROR special target to clean up
partially updated files on error. A known issue is the empty vmlinux.h
generted by bpftool if it failed to dump btf info.

Reviewed-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Changbin Du <changbin.du@gmail.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andrii Nakryiko <andrii.nakryiko@gmail.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20221217225151.90387-1-changbin.du@gmail.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/Makefile.perf | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf
index 9b7886ce0674e..13e7d26e77f04 100644
--- a/tools/perf/Makefile.perf
+++ b/tools/perf/Makefile.perf
@@ -1151,3 +1151,6 @@ FORCE:
 .PHONY: archheaders
 
 endif # force_fixdep
+
+# Delete partially updated (corrupted) files on error
+.DELETE_ON_ERROR:
-- 
GitLab


From b50d691e50e600fab82b423be871860537d75dc9 Mon Sep 17 00:00:00 2001
From: Michael Petlan <mpetlan@redhat.com>
Date: Mon, 19 Dec 2022 17:30:08 +0100
Subject: [PATCH 554/875] perf test: Fix "all PMU test" to skip parametrized
 events

Parametrized events are not only a powerpc domain. They occur on other
platforms too (e.g. aarch64). They should be ignored in this testcase,
since proper setup of the parameters is out of scope of this script.

Let's not filter them out by PMU name, but rather based on the fact that
they expect a parameter.

Fixes: 451ed8058c69a3fe ("perf test: Fix "all PMU test" to skip hv_24x7/hv_gpci tests on powerpc")
Signed-off-by: Michael Petlan <mpetlan@redhat.com>
Cc: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Cc: Disha Goel <disgoel@linux.vnet.ibm.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Nageswara R Sastry <rnsastry@linux.ibm.com>
Link: https://lore.kernel.org/r/20221219163008.9691-1-mpetlan@redhat.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/tests/shell/stat_all_pmu.sh | 13 ++-----------
 1 file changed, 2 insertions(+), 11 deletions(-)

diff --git a/tools/perf/tests/shell/stat_all_pmu.sh b/tools/perf/tests/shell/stat_all_pmu.sh
index 9c9ef33e0b3c6..c779554191731 100755
--- a/tools/perf/tests/shell/stat_all_pmu.sh
+++ b/tools/perf/tests/shell/stat_all_pmu.sh
@@ -4,17 +4,8 @@
 
 set -e
 
-for p in $(perf list --raw-dump pmu); do
-  # In powerpc, skip the events for hv_24x7 and hv_gpci.
-  # These events needs input values to be filled in for
-  # core, chip, partition id based on system.
-  # Example: hv_24x7/CPM_ADJUNCT_INST,domain=?,core=?/
-  # hv_gpci/event,partition_id=?/
-  # Hence skip these events for ppc.
-  if echo "$p" |grep -Eq 'hv_24x7|hv_gpci' ; then
-    echo "Skipping: Event '$p' in powerpc"
-    continue
-  fi
+# Test all PMU events; however exclude parametrized ones (name contains '?')
+for p in $(perf list --raw-dump pmu | sed 's/[[:graph:]]\+?[[:graph:]]\+[[:space:]]//g'); do
   echo "Testing $p"
   result=$(perf stat -e "$p" true 2>&1)
   if ! echo "$result" | grep -q "$p" && ! echo "$result" | grep -q "<not supported>" ; then
-- 
GitLab


From ea335ef3ddcdc17d616753743f92718e723341fb Mon Sep 17 00:00:00 2001
From: Namhyung Kim <namhyung@kernel.org>
Date: Thu, 15 Dec 2022 11:28:09 -0800
Subject: [PATCH 555/875] perf srcline: Do not return NULL for srcline

The code assumes non-NULL srcline value always, let's return the usual
SRCLINE_UNKNOWN ("??:0") string instead.

Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Acked-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Milian Wolff <milian.wolff@kdab.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20221215192817.2734573-2-namhyung@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/srcline.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/perf/util/srcline.c b/tools/perf/util/srcline.c
index af468e3bb6fab..5319efb16a5a3 100644
--- a/tools/perf/util/srcline.c
+++ b/tools/perf/util/srcline.c
@@ -716,7 +716,7 @@ out:
 
 	if (!show_addr)
 		return (show_sym && sym) ?
-			    strndup(sym->name, sym->namelen) : NULL;
+			    strndup(sym->name, sym->namelen) : SRCLINE_UNKNOWN;
 
 	if (sym) {
 		if (asprintf(&srcline, "%s+%" PRIu64, show_sym ? sym->name : "",
-- 
GitLab


From 06ea72a42d96ddcbac53f3b08a1c56d13b1c014a Mon Sep 17 00:00:00 2001
From: Namhyung Kim <namhyung@kernel.org>
Date: Thu, 15 Dec 2022 11:28:11 -0800
Subject: [PATCH 556/875] perf symbol: Add filename__has_section()

The filename__has_section() is to check if the given section name is in
the binary.  It'd be used for checking debug info for srcline.

Committer notes:

Added missing  __maybe_unused to the unused filename__has_section()
arguments in tools/perf/util/symbol-minimal.c.

Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Acked-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Milian Wolff <milian.wolff@kdab.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20221215192817.2734573-4-namhyung@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/symbol-elf.c     | 28 ++++++++++++++++++++++++++++
 tools/perf/util/symbol-minimal.c |  5 +++++
 tools/perf/util/symbol.h         |  1 +
 3 files changed, 34 insertions(+)

diff --git a/tools/perf/util/symbol-elf.c b/tools/perf/util/symbol-elf.c
index 80345695b1360..96767d1b3f1c2 100644
--- a/tools/perf/util/symbol-elf.c
+++ b/tools/perf/util/symbol-elf.c
@@ -233,6 +233,34 @@ Elf_Scn *elf_section_by_name(Elf *elf, GElf_Ehdr *ep,
 	return NULL;
 }
 
+bool filename__has_section(const char *filename, const char *sec)
+{
+	int fd;
+	Elf *elf;
+	GElf_Ehdr ehdr;
+	GElf_Shdr shdr;
+	bool found = false;
+
+	fd = open(filename, O_RDONLY);
+	if (fd < 0)
+		return false;
+
+	elf = elf_begin(fd, PERF_ELF_C_READ_MMAP, NULL);
+	if (elf == NULL)
+		goto out;
+
+	if (gelf_getehdr(elf, &ehdr) == NULL)
+		goto elf_out;
+
+	found = !!elf_section_by_name(elf, &ehdr, &shdr, sec, NULL);
+
+elf_out:
+	elf_end(elf);
+out:
+	close(fd);
+	return found;
+}
+
 static int elf_read_program_header(Elf *elf, u64 vaddr, GElf_Phdr *phdr)
 {
 	size_t i, phdrnum;
diff --git a/tools/perf/util/symbol-minimal.c b/tools/perf/util/symbol-minimal.c
index f9eb0bee7f157..a81a14769bd10 100644
--- a/tools/perf/util/symbol-minimal.c
+++ b/tools/perf/util/symbol-minimal.c
@@ -385,3 +385,8 @@ char *dso__demangle_sym(struct dso *dso __maybe_unused,
 {
 	return NULL;
 }
+
+bool filename__has_section(const char *filename __maybe_unused, const char *sec __maybe_unused)
+{
+	return false;
+}
diff --git a/tools/perf/util/symbol.h b/tools/perf/util/symbol.h
index e297de14184c5..f735108c4d4ec 100644
--- a/tools/perf/util/symbol.h
+++ b/tools/perf/util/symbol.h
@@ -165,6 +165,7 @@ int modules__parse(const char *filename, void *arg,
 					 u64 start, u64 size));
 int filename__read_debuglink(const char *filename, char *debuglink,
 			     size_t size);
+bool filename__has_section(const char *filename, const char *sec);
 
 struct perf_env;
 int symbol__init(struct perf_env *env);
-- 
GitLab


From 3b27222dd6cf7578c35b5903bf9d183a88d13744 Mon Sep 17 00:00:00 2001
From: Namhyung Kim <namhyung@kernel.org>
Date: Thu, 15 Dec 2022 11:28:12 -0800
Subject: [PATCH 557/875] perf srcline: Skip srcline if .debug_line is missing

The srcline info is from the .debug_line section.  No need to setup
addr2line subprocess if the section is missing.

Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Acked-by: Ian Rogers <irogers@google.com>
Link: https://lore.kernel.org/r/20221215192817.2734573-5-namhyung@kernel.org
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Milian Wolff <milian.wolff@kdab.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: LKML <linux-kernel@vger.kernel.org>
Cc: linux-perf-users@vger.kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/srcline.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tools/perf/util/srcline.c b/tools/perf/util/srcline.c
index 5319efb16a5a3..2c212e2e1b653 100644
--- a/tools/perf/util/srcline.c
+++ b/tools/perf/util/srcline.c
@@ -550,6 +550,9 @@ static int addr2line(const char *dso_name, u64 addr,
 	size_t inline_count = 0;
 
 	if (!a2l) {
+		if (!filename__has_section(dso_name, ".debug_line"))
+			goto out;
+
 		dso->a2l = addr2line_subprocess_init(dso_name);
 		a2l = dso->a2l;
 	}
-- 
GitLab


From d5e33ce06ba4a0fcf7815ff9edc3f651f7ae502e Mon Sep 17 00:00:00 2001
From: Namhyung Kim <namhyung@kernel.org>
Date: Thu, 15 Dec 2022 11:28:13 -0800
Subject: [PATCH 558/875] perf srcline: Conditionally suppress addr2line
 warnings

It has symbol_conf.disable_add2line_warn to suppress some warnings.  Let's
make it consistent with others.

Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Acked-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Milian Wolff <milian.wolff@kdab.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20221215192817.2734573-6-namhyung@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/srcline.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/tools/perf/util/srcline.c b/tools/perf/util/srcline.c
index 2c212e2e1b653..33321867416b3 100644
--- a/tools/perf/util/srcline.c
+++ b/tools/perf/util/srcline.c
@@ -573,13 +573,15 @@ static int addr2line(const char *dso_name, u64 addr,
 	 * "??"/"??:0" lines.
 	 */
 	if (fprintf(a2l->to_child, "%016"PRIx64"\n,\n", addr) < 0 || fflush(a2l->to_child) != 0) {
-		pr_warning("%s %s: could not send request\n", __func__, dso_name);
+		if (!symbol_conf.disable_add2line_warn)
+			pr_warning("%s %s: could not send request\n", __func__, dso_name);
 		goto out;
 	}
 
 	switch (read_addr2line_record(a2l, &record_function, &record_filename, &record_line_nr)) {
 	case -1:
-		pr_warning("%s %s: could not read first record\n", __func__, dso_name);
+		if (!symbol_conf.disable_add2line_warn)
+			pr_warning("%s %s: could not read first record\n", __func__, dso_name);
 		goto out;
 	case 0:
 		/*
@@ -588,14 +590,17 @@ static int addr2line(const char *dso_name, u64 addr,
 		 */
 		switch (read_addr2line_record(a2l, NULL, NULL, NULL)) {
 		case -1:
-			pr_warning("%s %s: could not read delimiter record\n", __func__, dso_name);
+			if (!symbol_conf.disable_add2line_warn)
+				pr_warning("%s %s: could not read delimiter record\n",
+					   __func__, dso_name);
 			break;
 		case 0:
 			/* As expected. */
 			break;
 		default:
-			pr_warning("%s %s: unexpected record instead of sentinel",
-				   __func__, dso_name);
+			if (!symbol_conf.disable_add2line_warn)
+				pr_warning("%s %s: unexpected record instead of sentinel",
+					   __func__, dso_name);
 			break;
 		}
 		goto out;
-- 
GitLab


From cb6e92c764272ca288398ad6442bbb0f064c2da8 Mon Sep 17 00:00:00 2001
From: Namhyung Kim <namhyung@kernel.org>
Date: Thu, 15 Dec 2022 11:28:14 -0800
Subject: [PATCH 559/875] perf hist: Add perf_hpp_fmt->init() callback

In __hists__insert_output_entry(), it calls fmt->sort() for dynamic
entries with NULL to update column width for tracepoint fields.
But it's a hacky abuse of the sort callback, better to have a proper
callback for that.  I'll add more use cases later.

Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Acked-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Milian Wolff <milian.wolff@kdab.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20221215192817.2734573-7-namhyung@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/hist.c | 10 +++++-----
 tools/perf/util/hist.h |  1 +
 tools/perf/util/sort.c | 31 ++++++++++++++++++++++++++-----
 tools/perf/util/sort.h |  1 +
 4 files changed, 33 insertions(+), 10 deletions(-)

diff --git a/tools/perf/util/hist.c b/tools/perf/util/hist.c
index 17a05e943b44b..b6e4b4edde43b 100644
--- a/tools/perf/util/hist.c
+++ b/tools/perf/util/hist.c
@@ -1781,8 +1781,8 @@ static void hierarchy_insert_output_entry(struct rb_root_cached *root,
 
 	/* update column width of dynamic entry */
 	perf_hpp_list__for_each_sort_list(he->hpp_list, fmt) {
-		if (perf_hpp__is_dynamic_entry(fmt))
-			fmt->sort(fmt, he, NULL);
+		if (fmt->init)
+			fmt->init(fmt, he);
 	}
 }
 
@@ -1879,10 +1879,10 @@ static void __hists__insert_output_entry(struct rb_root_cached *entries,
 	rb_link_node(&he->rb_node, parent, p);
 	rb_insert_color_cached(&he->rb_node, entries, leftmost);
 
+	/* update column width of dynamic entries */
 	perf_hpp_list__for_each_sort_list(&perf_hpp_list, fmt) {
-		if (perf_hpp__is_dynamic_entry(fmt) &&
-		    perf_hpp__defined_dynamic_entry(fmt, he->hists))
-			fmt->sort(fmt, he, NULL);  /* update column width */
+		if (fmt->init)
+			fmt->init(fmt, he);
 	}
 }
 
diff --git a/tools/perf/util/hist.h b/tools/perf/util/hist.h
index ebd8a8f783ee6..d93a4e510dc77 100644
--- a/tools/perf/util/hist.h
+++ b/tools/perf/util/hist.h
@@ -272,6 +272,7 @@ struct perf_hpp_fmt {
 		      struct hists *hists, int line, int *span);
 	int (*width)(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp,
 		     struct hists *hists);
+	void (*init)(struct perf_hpp_fmt *fmt, struct hist_entry *he);
 	int (*color)(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp,
 		     struct hist_entry *he);
 	int (*entry)(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp,
diff --git a/tools/perf/util/sort.c b/tools/perf/util/sort.c
index 0ecc2cb137920..f6333b3dca35b 100644
--- a/tools/perf/util/sort.c
+++ b/tools/perf/util/sort.c
@@ -2251,6 +2251,19 @@ static void hse_free(struct perf_hpp_fmt *fmt)
 	free(hse);
 }
 
+static void hse_init(struct perf_hpp_fmt *fmt, struct hist_entry *he)
+{
+	struct hpp_sort_entry *hse;
+
+	if (!perf_hpp__is_sort_entry(fmt))
+		return;
+
+	hse = container_of(fmt, struct hpp_sort_entry, hpp);
+
+	if (hse->se->se_init)
+		hse->se->se_init(he);
+}
+
 static struct hpp_sort_entry *
 __sort_dimension__alloc_hpp(struct sort_dimension *sd, int level)
 {
@@ -2274,6 +2287,7 @@ __sort_dimension__alloc_hpp(struct sort_dimension *sd, int level)
 	hse->hpp.sort = __sort__hpp_sort;
 	hse->hpp.equal = __sort__hpp_equal;
 	hse->hpp.free = hse_free;
+	hse->hpp.init = hse_init;
 
 	INIT_LIST_HEAD(&hse->hpp.list);
 	INIT_LIST_HEAD(&hse->hpp.sort_list);
@@ -2556,11 +2570,6 @@ static int64_t __sort__hde_cmp(struct perf_hpp_fmt *fmt,
 
 	hde = container_of(fmt, struct hpp_dynamic_entry, hpp);
 
-	if (b == NULL) {
-		update_dynamic_len(hde, a);
-		return 0;
-	}
-
 	field = hde->field;
 	if (field->flags & TEP_FIELD_IS_DYNAMIC) {
 		unsigned long long dyn;
@@ -2610,6 +2619,17 @@ static void hde_free(struct perf_hpp_fmt *fmt)
 	free(hde);
 }
 
+static void __sort__hde_init(struct perf_hpp_fmt *fmt, struct hist_entry *he)
+{
+	struct hpp_dynamic_entry *hde;
+
+	if (!perf_hpp__is_dynamic_entry(fmt))
+		return;
+
+	hde = container_of(fmt, struct hpp_dynamic_entry, hpp);
+	update_dynamic_len(hde, he);
+}
+
 static struct hpp_dynamic_entry *
 __alloc_dynamic_entry(struct evsel *evsel, struct tep_format_field *field,
 		      int level)
@@ -2632,6 +2652,7 @@ __alloc_dynamic_entry(struct evsel *evsel, struct tep_format_field *field,
 	hde->hpp.entry  = __sort__hde_entry;
 	hde->hpp.color  = NULL;
 
+	hde->hpp.init = __sort__hde_init;
 	hde->hpp.cmp = __sort__hde_cmp;
 	hde->hpp.collapse = __sort__hde_cmp;
 	hde->hpp.sort = __sort__hde_cmp;
diff --git a/tools/perf/util/sort.h b/tools/perf/util/sort.h
index 04ff8b61a2a7c..921715e6aec4c 100644
--- a/tools/perf/util/sort.h
+++ b/tools/perf/util/sort.h
@@ -282,6 +282,7 @@ struct sort_entry {
 	int	(*se_snprintf)(struct hist_entry *he, char *bf, size_t size,
 			       unsigned int width);
 	int	(*se_filter)(struct hist_entry *he, int type, const void *arg);
+	void	(*se_init)(struct hist_entry *he);
 	u8	se_width_idx;
 };
 
-- 
GitLab


From ec222d7e7cfd09276891ffdf57d75858fe148c9f Mon Sep 17 00:00:00 2001
From: Namhyung Kim <namhyung@kernel.org>
Date: Thu, 15 Dec 2022 11:28:15 -0800
Subject: [PATCH 560/875] perf hist: Improve srcline sort key performance

The sort_entry->cmp() will be called for eventy sample data to find a
matching entry.  When it has 'srcline' sort key, that means it needs to
call addr2line or libbfd everytime.

This is not optimal because many samples will have same address and it
just can call addr2line once.  So postpone the actual srcline check to
the sort_entry->collpase() and compare addresses in ->cmp().

Also it needs to add ->init() callback to make sure it has srcline info.
If a sample has a unique data, chances are the entry can be sorted out
by other (previous) keys and callbacks in sort_srcline never called.

Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Acked-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Milian Wolff <milian.wolff@kdab.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20221215192817.2734573-8-namhyung@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/sort.c | 29 +++++++++++++++++++++++++++--
 1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/tools/perf/util/sort.c b/tools/perf/util/sort.c
index f6333b3dca35b..913045c5b2b28 100644
--- a/tools/perf/util/sort.c
+++ b/tools/perf/util/sort.c
@@ -373,6 +373,18 @@ char *hist_entry__srcline(struct hist_entry *he)
 
 static int64_t
 sort__srcline_cmp(struct hist_entry *left, struct hist_entry *right)
+{
+	int64_t ret;
+
+	ret = _sort__addr_cmp(left->ip, right->ip);
+	if (ret)
+		return ret;
+
+	return sort__dso_cmp(left, right);
+}
+
+static int64_t
+sort__srcline_collapse(struct hist_entry *left, struct hist_entry *right)
 {
 	if (!left->srcline)
 		left->srcline = hist_entry__srcline(left);
@@ -382,18 +394,31 @@ sort__srcline_cmp(struct hist_entry *left, struct hist_entry *right)
 	return strcmp(right->srcline, left->srcline);
 }
 
-static int hist_entry__srcline_snprintf(struct hist_entry *he, char *bf,
-					size_t size, unsigned int width)
+static int64_t
+sort__srcline_sort(struct hist_entry *left, struct hist_entry *right)
+{
+	return sort__srcline_collapse(left, right);
+}
+
+static void
+sort__srcline_init(struct hist_entry *he)
 {
 	if (!he->srcline)
 		he->srcline = hist_entry__srcline(he);
+}
 
+static int hist_entry__srcline_snprintf(struct hist_entry *he, char *bf,
+					size_t size, unsigned int width)
+{
 	return repsep_snprintf(bf, size, "%-.*s", width, he->srcline);
 }
 
 struct sort_entry sort_srcline = {
 	.se_header	= "Source:Line",
 	.se_cmp		= sort__srcline_cmp,
+	.se_collapse	= sort__srcline_collapse,
+	.se_sort	= sort__srcline_sort,
+	.se_init	= sort__srcline_init,
 	.se_snprintf	= hist_entry__srcline_snprintf,
 	.se_width_idx	= HISTC_SRCLINE,
 };
-- 
GitLab


From f0cdde28fecc0d7ff85c315b2abf206ef27c0174 Mon Sep 17 00:00:00 2001
From: Namhyung Kim <namhyung@kernel.org>
Date: Thu, 15 Dec 2022 11:28:16 -0800
Subject: [PATCH 561/875] perf hist: Improve srcfile sort key performance

Likewise, modify ->cmp() callback to compare sample address and map
address.  And add ->collapse() and ->sort() to check the actual
srcfile string.  Also add ->init() to make sure it has the srcfile.

Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Acked-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Milian Wolff <milian.wolff@kdab.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20221215192817.2734573-9-namhyung@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/sort.c | 27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/tools/perf/util/sort.c b/tools/perf/util/sort.c
index 913045c5b2b28..c290539dcf437 100644
--- a/tools/perf/util/sort.c
+++ b/tools/perf/util/sort.c
@@ -569,18 +569,41 @@ sort__srcfile_cmp(struct hist_entry *left, struct hist_entry *right)
 	return strcmp(right->srcfile, left->srcfile);
 }
 
-static int hist_entry__srcfile_snprintf(struct hist_entry *he, char *bf,
-					size_t size, unsigned int width)
+static int64_t
+sort__srcfile_collapse(struct hist_entry *left, struct hist_entry *right)
+{
+	if (!left->srcfile)
+		left->srcfile = hist_entry__get_srcfile(left);
+	if (!right->srcfile)
+		right->srcfile = hist_entry__get_srcfile(right);
+
+	return strcmp(right->srcfile, left->srcfile);
+}
+
+static int64_t
+sort__srcfile_sort(struct hist_entry *left, struct hist_entry *right)
+{
+	return sort__srcfile_collapse(left, right);
+}
+
+static void sort__srcfile_init(struct hist_entry *he)
 {
 	if (!he->srcfile)
 		he->srcfile = hist_entry__get_srcfile(he);
+}
 
+static int hist_entry__srcfile_snprintf(struct hist_entry *he, char *bf,
+					size_t size, unsigned int width)
+{
 	return repsep_snprintf(bf, size, "%-.*s", width, he->srcfile);
 }
 
 struct sort_entry sort_srcfile = {
 	.se_header	= "Source File",
 	.se_cmp		= sort__srcfile_cmp,
+	.se_collapse	= sort__srcfile_collapse,
+	.se_sort	= sort__srcfile_sort,
+	.se_init	= sort__srcfile_init,
 	.se_snprintf	= hist_entry__srcfile_snprintf,
 	.se_width_idx	= HISTC_SRCFILE,
 };
-- 
GitLab


From ad9ef9eb64a2230c12fa5c6c98aed176428012e8 Mon Sep 17 00:00:00 2001
From: Namhyung Kim <namhyung@kernel.org>
Date: Thu, 15 Dec 2022 11:28:17 -0800
Subject: [PATCH 562/875] perf hist: Improve srcline_{from,to} sort key
 performance

Likewise, modify ->cmp() callback to compare sample address and map
address.  And add ->collapse() and ->sort() to check the actual
srcfile string.  Also add ->init() to make sure it has the srcfile.

Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Acked-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Milian Wolff <milian.wolff@kdab.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20221215192817.2734573-10-namhyung@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/sort.c | 42 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/tools/perf/util/sort.c b/tools/perf/util/sort.c
index c290539dcf437..e188f74698dd3 100644
--- a/tools/perf/util/sort.c
+++ b/tools/perf/util/sort.c
@@ -432,6 +432,12 @@ static char *addr_map_symbol__srcline(struct addr_map_symbol *ams)
 
 static int64_t
 sort__srcline_from_cmp(struct hist_entry *left, struct hist_entry *right)
+{
+	return left->branch_info->from.addr - right->branch_info->from.addr;
+}
+
+static int64_t
+sort__srcline_from_collapse(struct hist_entry *left, struct hist_entry *right)
 {
 	if (!left->branch_info->srcline_from)
 		left->branch_info->srcline_from = addr_map_symbol__srcline(&left->branch_info->from);
@@ -442,6 +448,18 @@ sort__srcline_from_cmp(struct hist_entry *left, struct hist_entry *right)
 	return strcmp(right->branch_info->srcline_from, left->branch_info->srcline_from);
 }
 
+static int64_t
+sort__srcline_from_sort(struct hist_entry *left, struct hist_entry *right)
+{
+	return sort__srcline_from_collapse(left, right);
+}
+
+static void sort__srcline_from_init(struct hist_entry *he)
+{
+	if (!he->branch_info->srcline_from)
+		he->branch_info->srcline_from = addr_map_symbol__srcline(&he->branch_info->from);
+}
+
 static int hist_entry__srcline_from_snprintf(struct hist_entry *he, char *bf,
 					size_t size, unsigned int width)
 {
@@ -451,6 +469,9 @@ static int hist_entry__srcline_from_snprintf(struct hist_entry *he, char *bf,
 struct sort_entry sort_srcline_from = {
 	.se_header	= "From Source:Line",
 	.se_cmp		= sort__srcline_from_cmp,
+	.se_collapse	= sort__srcline_from_collapse,
+	.se_sort	= sort__srcline_from_sort,
+	.se_init	= sort__srcline_from_init,
 	.se_snprintf	= hist_entry__srcline_from_snprintf,
 	.se_width_idx	= HISTC_SRCLINE_FROM,
 };
@@ -459,6 +480,12 @@ struct sort_entry sort_srcline_from = {
 
 static int64_t
 sort__srcline_to_cmp(struct hist_entry *left, struct hist_entry *right)
+{
+	return left->branch_info->to.addr - right->branch_info->to.addr;
+}
+
+static int64_t
+sort__srcline_to_collapse(struct hist_entry *left, struct hist_entry *right)
 {
 	if (!left->branch_info->srcline_to)
 		left->branch_info->srcline_to = addr_map_symbol__srcline(&left->branch_info->to);
@@ -469,6 +496,18 @@ sort__srcline_to_cmp(struct hist_entry *left, struct hist_entry *right)
 	return strcmp(right->branch_info->srcline_to, left->branch_info->srcline_to);
 }
 
+static int64_t
+sort__srcline_to_sort(struct hist_entry *left, struct hist_entry *right)
+{
+	return sort__srcline_to_collapse(left, right);
+}
+
+static void sort__srcline_to_init(struct hist_entry *he)
+{
+	if (!he->branch_info->srcline_to)
+		he->branch_info->srcline_to = addr_map_symbol__srcline(&he->branch_info->to);
+}
+
 static int hist_entry__srcline_to_snprintf(struct hist_entry *he, char *bf,
 					size_t size, unsigned int width)
 {
@@ -478,6 +517,9 @@ static int hist_entry__srcline_to_snprintf(struct hist_entry *he, char *bf,
 struct sort_entry sort_srcline_to = {
 	.se_header	= "To Source:Line",
 	.se_cmp		= sort__srcline_to_cmp,
+	.se_collapse	= sort__srcline_to_collapse,
+	.se_sort	= sort__srcline_to_sort,
+	.se_init	= sort__srcline_to_init,
 	.se_snprintf	= hist_entry__srcline_to_snprintf,
 	.se_width_idx	= HISTC_SRCLINE_TO,
 };
-- 
GitLab


From ed4c1778cc1abd18d491d0eecb7947c7cac3a598 Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:47:24 -0800
Subject: [PATCH 563/875] perf test pmu-events: Fake PMU metric workaround

We test metrics with fake events with fake values. The fake values may
yield division by zero and so we count both up and down to try to
avoid this. Unfortunately this isn't sufficient for some metrics and
so don't fail the test for them.

Add the metric name to debug output.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: http://lore.kernel.org/lkml/20221215064755.1620246-2-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/tests/pmu-events.c | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c
index e36d8b1610d4f..a9f2330f6257a 100644
--- a/tools/perf/tests/pmu-events.c
+++ b/tools/perf/tests/pmu-events.c
@@ -959,7 +959,7 @@ static struct test_metric metrics[] = {
 	{ "(imx8_ddr0@read\\-cycles@ + imx8_ddr0@write\\-cycles@)", },
 };
 
-static int metric_parse_fake(const char *str)
+static int metric_parse_fake(const char *metric_name, const char *str)
 {
 	struct expr_parse_ctx *ctx;
 	struct hashmap_entry *cur;
@@ -968,7 +968,7 @@ static int metric_parse_fake(const char *str)
 	size_t bkt;
 	int i;
 
-	pr_debug("parsing '%s'\n", str);
+	pr_debug("parsing '%s': '%s'\n", metric_name, str);
 
 	ctx = expr__ctx_new();
 	if (!ctx) {
@@ -1006,8 +1006,13 @@ static int metric_parse_fake(const char *str)
 		hashmap__for_each_entry(ctx->ids, cur, bkt)
 			expr__add_id_val(ctx, strdup(cur->pkey), i--);
 		if (expr__parse(&result, ctx, str)) {
-			pr_err("expr__parse failed\n");
-			ret = -1;
+			pr_err("expr__parse failed for %s\n", metric_name);
+			/* The following have hard to avoid divide by zero. */
+			if (!strcmp(metric_name, "tma_clears_resteers") ||
+			    !strcmp(metric_name, "tma_mispredicts_resteers"))
+				ret = 0;
+			else
+				ret = -1;
 		}
 	}
 
@@ -1023,7 +1028,7 @@ static int test__parsing_fake_callback(const struct pmu_event *pe,
 	if (!pe->metric_expr)
 		return 0;
 
-	return metric_parse_fake(pe->metric_expr);
+	return metric_parse_fake(pe->metric_name, pe->metric_expr);
 }
 
 /*
@@ -1037,7 +1042,7 @@ static int test__parsing_fake(struct test_suite *test __maybe_unused,
 	int err = 0;
 
 	for (size_t i = 0; i < ARRAY_SIZE(metrics); i++) {
-		err = metric_parse_fake(metrics[i].str);
+		err = metric_parse_fake("", metrics[i].str);
 		if (err)
 			return err;
 	}
-- 
GitLab


From 266b2ca72742269340aca6f34356bee277b59c7d Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:47:25 -0800
Subject: [PATCH 564/875] perf vendor events intel: Refresh alderlake metrics

Update the alderlake metrics using the new tooling from:

  https://github.com/intel/perfmon

The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1".

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215064755.1620246-3-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../arch/x86/alderlake/adl-metrics.json       | 116 +++++++++---------
 1 file changed, 58 insertions(+), 58 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json b/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json
index edf440e9359af..2eb3d7464d9fd 100644
--- a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json
@@ -10,7 +10,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
-        "MetricExpr": "(topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / SLOTS)",
+        "MetricExpr": "topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / SLOTS",
         "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
         "MetricName": "tma_fetch_latency",
         "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS",
@@ -46,7 +46,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage",
-        "MetricExpr": "(tma_branch_mispredicts / tma_bad_speculation) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
+        "MetricExpr": "tma_branch_mispredicts / tma_bad_speculation * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
         "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group",
         "MetricName": "tma_mispredicts_resteers",
         "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage.  Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
@@ -55,7 +55,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears",
-        "MetricExpr": "(1 - (tma_branch_mispredicts / tma_bad_speculation)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
+        "MetricExpr": "(1 - tma_branch_mispredicts / tma_bad_speculation) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
         "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group",
         "MetricName": "tma_clears_resteers",
         "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears.  Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
@@ -153,7 +153,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
-        "MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
+        "MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS",
         "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
         "MetricName": "tma_branch_mispredicts",
         "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS",
@@ -171,7 +171,7 @@
     },
     {
         "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
-        "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
+        "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS",
         "MetricGroup": "TopdownL1;tma_L1_group",
         "MetricName": "tma_backend_bound",
         "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS",
@@ -180,7 +180,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
-        "MetricExpr": "topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
+        "MetricExpr": "topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS",
         "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
         "MetricName": "tma_memory_bound",
         "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@@ -232,7 +232,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
-        "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
+        "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
         "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
         "MetricName": "tma_lock_latency",
         "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS",
@@ -277,7 +277,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
-        "MetricExpr": "((25 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + (24 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+        "MetricExpr": "(25 * Average_Frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 24 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
         "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_contested_accesses",
         "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
@@ -286,7 +286,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
-        "MetricExpr": "(24 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD)))) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+        "MetricExpr": "24 * Average_Frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
         "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_data_sharing",
         "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
@@ -295,7 +295,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
-        "MetricExpr": "(9 * Average_Frequency) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+        "MetricExpr": "9 * Average_Frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
         "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_l3_hit_latency",
         "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
@@ -313,7 +313,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
-        "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L3_MISS / CLKS)",
+        "MetricExpr": "MEMORY_ACTIVITY.STALLS_L3_MISS / CLKS",
         "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_dram_bound",
         "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS",
@@ -340,7 +340,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
-        "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CLKS",
+        "MetricExpr": "tma_st_buffer",
         "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_store_bound",
         "PublicDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS",
@@ -349,7 +349,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
-        "MetricExpr": "((MEM_STORE_RETIRED.L2_HIT * 10 * (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES))) + (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
+        "MetricExpr": "(MEM_STORE_RETIRED.L2_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
         "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
         "MetricName": "tma_store_latency",
         "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
@@ -358,7 +358,7 @@
     },
     {
         "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
-        "MetricExpr": "(28 * Average_Frequency) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
+        "MetricExpr": "28 * Average_Frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
         "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
         "MetricName": "tma_false_sharing",
         "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line.  Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
@@ -428,7 +428,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
-        "MetricExpr": "(cpu_core@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@)) / CLKS if (ARITH.DIVIDER_ACTIVE < (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS)) else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@) / CLKS",
+        "MetricExpr": "((cpu_core@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@)) / CLKS if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@) / CLKS)",
         "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
         "MetricName": "tma_ports_utilization",
         "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@@ -556,7 +556,7 @@
     },
     {
         "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
-        "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
+        "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS",
         "MetricGroup": "TopdownL1;tma_L1_group",
         "MetricName": "tma_retiring",
         "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided.  Sample with: UOPS_RETIRED.SLOTS",
@@ -704,7 +704,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
-        "MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
+        "MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS",
         "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
         "MetricName": "tma_heavy_operations",
         "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences. Sample with: UOPS_RETIRED.HEAVY",
@@ -722,7 +722,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
-        "MetricExpr": "UOPS_RETIRED.MS / SLOTS",
+        "MetricExpr": "tma_ms_uops",
         "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
         "MetricName": "tma_microcode_sequencer",
         "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS",
@@ -782,21 +782,21 @@
     },
     {
         "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) ",
+        "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))",
         "MetricGroup": "Mem;MemoryBW;Offcore",
         "MetricName": "Memory_Bandwidth",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + (tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)))",
+        "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound))",
         "MetricGroup": "Mem;MemoryLat;Offcore",
         "MetricName": "Memory_Latency",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) ",
+        "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))",
         "MetricGroup": "Mem;MemoryTLB;Offcore",
         "MetricName": "Memory_Data_TLBs",
         "Unit": "cpu_core"
@@ -831,14 +831,14 @@
     },
     {
         "BriefDescription": "Uops Per Instruction",
-        "MetricExpr": "(tma_retiring * SLOTS) / INST_RETIRED.ANY",
+        "MetricExpr": "tma_retiring * SLOTS / INST_RETIRED.ANY",
         "MetricGroup": "Pipeline;Ret;Retire",
         "MetricName": "UPI",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Instruction per taken branch",
-        "MetricExpr": "(tma_retiring * SLOTS) / BR_INST_RETIRED.NEAR_TAKEN",
+        "MetricExpr": "tma_retiring * SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
         "MetricGroup": "Branches;Fed;FetchBW",
         "MetricName": "UpTB",
         "Unit": "cpu_core"
@@ -866,7 +866,7 @@
     },
     {
         "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
-        "MetricExpr": "SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1",
+        "MetricExpr": "(SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)",
         "MetricGroup": "SMT;tma_L1_group",
         "MetricName": "Slots_Utilization",
         "Unit": "cpu_core"
@@ -888,7 +888,7 @@
     },
     {
         "BriefDescription": "Floating Point Operations Per Cycle",
-        "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
         "MetricGroup": "Flops;Ret",
         "MetricName": "FLOPc",
         "Unit": "cpu_core"
@@ -903,14 +903,14 @@
     },
     {
         "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / ((UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
         "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
         "MetricName": "ILP",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
-        "MetricExpr": "(1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0",
+        "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)",
         "MetricGroup": "Cor;SMT",
         "MetricName": "Core_Bound_Likely",
         "Unit": "cpu_core"
@@ -966,14 +966,14 @@
     },
     {
         "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
         "MetricGroup": "Flops;InsType",
         "MetricName": "IpFLOP",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
         "MetricGroup": "Flops;InsType",
         "MetricName": "IpArith",
         "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW.",
@@ -1027,7 +1027,7 @@
     },
     {
         "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
-        "MetricExpr": "(tma_retiring * SLOTS) / cpu_core@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
+        "MetricExpr": "tma_retiring * SLOTS / cpu_core@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
         "MetricGroup": "Pipeline;Ret",
         "MetricName": "Retire",
         "Unit": "cpu_core"
@@ -1104,7 +1104,7 @@
     },
     {
         "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
-        "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
+        "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
         "MetricGroup": "Bad;BrMispredicts",
         "MetricName": "Branch_Misprediction_Cost",
         "Unit": "cpu_core"
@@ -1160,63 +1160,63 @@
     },
     {
         "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L1MPKI",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L1MPKI_Load",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
         "MetricGroup": "Backend;CacheMisses;Mem",
         "MetricName": "L2MPKI",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem;Offcore",
         "MetricName": "L2MPKI_All",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L2MPKI_Load",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
-        "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L2HPKI_All",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "L2 cache hits per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L2HPKI_Load",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L3MPKI",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "FB_HPKI",
         "Unit": "cpu_core"
@@ -1231,28 +1231,28 @@
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
-        "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
+        "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L1D_Cache_Fill_BW",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
-        "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
+        "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L2_Cache_Fill_BW",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
+        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L3_Cache_Fill_BW",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time",
+        "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW;Offcore",
         "MetricName": "L3_Cache_Access_BW",
         "Unit": "cpu_core"
@@ -1294,14 +1294,14 @@
     },
     {
         "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
-        "MetricExpr": "Turbo_Utilization * TSC / 1000000000 / duration_time",
+        "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
         "MetricGroup": "Power;Summary",
         "MetricName": "Average_Frequency",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Giga Floating Point Operations Per Second",
-        "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1000000000) / duration_time",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time",
         "MetricGroup": "Cor;Flops;HPC",
         "MetricName": "GFLOPs",
         "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine.",
@@ -1316,7 +1316,7 @@
     },
     {
         "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
-        "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0",
+        "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)",
         "MetricGroup": "SMT",
         "MetricName": "SMT_2T_Utilization",
         "Unit": "cpu_core"
@@ -1337,7 +1337,7 @@
     },
     {
         "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
-        "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1000000 / duration_time / 1000",
+        "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3",
         "MetricGroup": "HPC;Mem;MemoryBW;SoC",
         "MetricName": "DRAM_BW_Use",
         "Unit": "cpu_core"
@@ -1365,7 +1365,7 @@
     },
     {
         "BriefDescription": "Uncore frequency per die [GHZ]",
-        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000",
+        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
         "MetricGroup": "SoC",
         "MetricName": "UNCORE_FREQ"
     },
@@ -1558,7 +1558,7 @@
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to stores or loads. ",
-        "MetricExpr": "min((TOPDOWN_BE_BOUND.ALL / SLOTS), (LD_HEAD.ANY_AT_RET / CLKS) + tma_store_bound)",
+        "MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / CLKS + tma_store_bound)",
         "MetricGroup": "TopdownL2;tma_backend_bound_group",
         "MetricName": "tma_load_store_bound",
         "ScaleUnit": "100%",
@@ -1566,7 +1566,7 @@
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full.",
-        "MetricExpr": "tma_mem_scheduler * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL)",
+        "MetricExpr": "tma_st_buffer",
         "MetricGroup": "TopdownL3;tma_load_store_bound_group",
         "MetricName": "tma_store_bound",
         "ScaleUnit": "100%",
@@ -1614,7 +1614,7 @@
     },
     {
         "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 Cache.",
-        "MetricExpr": "(MEM_BOUND_STALLS.LOAD_L2_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD)",
+        "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD",
         "MetricGroup": "TopdownL3;tma_load_store_bound_group",
         "MetricName": "tma_l2_bound",
         "ScaleUnit": "100%",
@@ -1622,7 +1622,7 @@
     },
     {
         "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
-        "MetricExpr": "(MEM_BOUND_STALLS.LOAD_LLC_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD)",
+        "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD",
         "MetricGroup": "TopdownL3;tma_load_store_bound_group",
         "MetricName": "tma_l3_bound",
         "ScaleUnit": "100%",
@@ -1630,7 +1630,7 @@
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
-        "MetricExpr": "(MEM_BOUND_STALLS.LOAD_DRAM_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD)",
+        "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD",
         "MetricGroup": "TopdownL3;tma_load_store_bound_group",
         "MetricName": "tma_dram_bound",
         "ScaleUnit": "100%",
@@ -1939,25 +1939,25 @@
     },
     {
         "BriefDescription": "Percent of instruction miss cost that hit in the L2",
-        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / (MEM_BOUND_STALLS.IFETCH)",
+        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / MEM_BOUND_STALLS.IFETCH",
         "MetricName": "Inst_Miss_Cost_L2Hit_Percent",
         "Unit": "cpu_atom"
     },
     {
         "BriefDescription": "Percent of instruction miss cost that hit in the L3",
-        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / (MEM_BOUND_STALLS.IFETCH)",
+        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / MEM_BOUND_STALLS.IFETCH",
         "MetricName": "Inst_Miss_Cost_L3Hit_Percent",
         "Unit": "cpu_atom"
     },
     {
         "BriefDescription": "Percent of instruction miss cost that hit in DRAM",
-        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / (MEM_BOUND_STALLS.IFETCH)",
+        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / MEM_BOUND_STALLS.IFETCH",
         "MetricName": "Inst_Miss_Cost_DRAMHit_Percent",
         "Unit": "cpu_atom"
     },
     {
         "BriefDescription": "load ops retired per 1000 instruction",
-        "MetricExpr": "1000 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
         "MetricName": "MemLoadPKI",
         "Unit": "cpu_atom"
     },
-- 
GitLab


From a5abef626f35378a7de2edc399902dc9648f69ef Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:47:26 -0800
Subject: [PATCH 565/875] perf vendor events intel: Refresh alderlake-n metrics

Update the alderlake-n metrics using the new tooling from:

  https://github.com/intel/perfmon

The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1".

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215064755.1620246-4-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../arch/x86/alderlaken/adln-metrics.json      | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json b/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json
index c57e9f325fb05..9ab1d5bcf4a21 100644
--- a/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json
@@ -165,14 +165,14 @@
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to stores or loads. ",
-        "MetricExpr": "min((TOPDOWN_BE_BOUND.ALL / SLOTS), (LD_HEAD.ANY_AT_RET / CLKS) + tma_store_bound)",
+        "MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / CLKS + tma_store_bound)",
         "MetricGroup": "TopdownL2;tma_backend_bound_group",
         "MetricName": "tma_load_store_bound",
         "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full.",
-        "MetricExpr": "tma_mem_scheduler * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL)",
+        "MetricExpr": "tma_st_buffer",
         "MetricGroup": "TopdownL3;tma_load_store_bound_group",
         "MetricName": "tma_store_bound",
         "ScaleUnit": "100%"
@@ -214,21 +214,21 @@
     },
     {
         "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 Cache.",
-        "MetricExpr": "(MEM_BOUND_STALLS.LOAD_L2_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD)",
+        "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD",
         "MetricGroup": "TopdownL3;tma_load_store_bound_group",
         "MetricName": "tma_l2_bound",
         "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
-        "MetricExpr": "(MEM_BOUND_STALLS.LOAD_LLC_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD)",
+        "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD",
         "MetricGroup": "TopdownL3;tma_load_store_bound_group",
         "MetricName": "tma_l3_bound",
         "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
-        "MetricExpr": "(MEM_BOUND_STALLS.LOAD_DRAM_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD)",
+        "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD",
         "MetricGroup": "TopdownL3;tma_load_store_bound_group",
         "MetricName": "tma_dram_bound",
         "ScaleUnit": "100%"
@@ -492,22 +492,22 @@
     },
     {
         "BriefDescription": "Percent of instruction miss cost that hit in the L2",
-        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / (MEM_BOUND_STALLS.IFETCH)",
+        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / MEM_BOUND_STALLS.IFETCH",
         "MetricName": "Inst_Miss_Cost_L2Hit_Percent"
     },
     {
         "BriefDescription": "Percent of instruction miss cost that hit in the L3",
-        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / (MEM_BOUND_STALLS.IFETCH)",
+        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / MEM_BOUND_STALLS.IFETCH",
         "MetricName": "Inst_Miss_Cost_L3Hit_Percent"
     },
     {
         "BriefDescription": "Percent of instruction miss cost that hit in DRAM",
-        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / (MEM_BOUND_STALLS.IFETCH)",
+        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / MEM_BOUND_STALLS.IFETCH",
         "MetricName": "Inst_Miss_Cost_DRAMHit_Percent"
     },
     {
         "BriefDescription": "load ops retired per 1000 instruction",
-        "MetricExpr": "1000 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
         "MetricName": "MemLoadPKI"
     },
     {
-- 
GitLab


From 6fa91f645f6f17f96f99af9e968e4109f6eb8e72 Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:47:27 -0800
Subject: [PATCH 566/875] perf vendor events intel: Refresh bonnell events

Update the bonnell events using the new tooling from:

  https://github.com/intel/perfmon

The events are unchanged but unused json values are removed and
implicit umasks of 0 are dropped. This increases consistency across
the json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215064755.1620246-5-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../pmu-events/arch/x86/bonnell/cache.json    | 93 -------------------
 .../arch/x86/bonnell/floating-point.json      | 47 +---------
 .../pmu-events/arch/x86/bonnell/frontend.json | 11 ---
 .../pmu-events/arch/x86/bonnell/memory.json   | 19 ----
 .../pmu-events/arch/x86/bonnell/other.json    | 74 ++-------------
 .../pmu-events/arch/x86/bonnell/pipeline.json | 65 ++-----------
 .../arch/x86/bonnell/virtual-memory.json      | 15 ---
 7 files changed, 18 insertions(+), 306 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/bonnell/cache.json b/tools/perf/pmu-events/arch/x86/bonnell/cache.json
index 86582bb8aa393..1ca95a70d48ae 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/cache.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/cache.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "L1 Data Cacheable reads and writes",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE.ALL_CACHE_REF",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "L1 Data reads and writes",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE.ALL_REF",
         "SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "Modified cache lines evicted from the L1 data cache",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE.EVICT",
         "SampleAfterValue": "200000",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "L1 Cacheable Data Reads",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE.LD",
         "SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "L1 Data line replacements",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE.REPL",
         "SampleAfterValue": "200000",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "Modified cache lines allocated in the L1 data cache",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE.REPLM",
         "SampleAfterValue": "200000",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "L1 Cacheable Data Writes",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE.ST",
         "SampleAfterValue": "2000000",
@@ -57,7 +50,6 @@
     },
     {
         "BriefDescription": "Cycles L2 address bus is in use.",
-        "Counter": "0,1",
         "EventCode": "0x21",
         "EventName": "L2_ADS.SELF",
         "SampleAfterValue": "200000",
@@ -65,7 +57,6 @@
     },
     {
         "BriefDescription": "All data requests from the L1 data cache",
-        "Counter": "0,1",
         "EventCode": "0x2C",
         "EventName": "L2_DATA_RQSTS.SELF.E_STATE",
         "SampleAfterValue": "200000",
@@ -73,7 +64,6 @@
     },
     {
         "BriefDescription": "All data requests from the L1 data cache",
-        "Counter": "0,1",
         "EventCode": "0x2C",
         "EventName": "L2_DATA_RQSTS.SELF.I_STATE",
         "SampleAfterValue": "200000",
@@ -81,7 +71,6 @@
     },
     {
         "BriefDescription": "All data requests from the L1 data cache",
-        "Counter": "0,1",
         "EventCode": "0x2C",
         "EventName": "L2_DATA_RQSTS.SELF.MESI",
         "SampleAfterValue": "200000",
@@ -89,7 +78,6 @@
     },
     {
         "BriefDescription": "All data requests from the L1 data cache",
-        "Counter": "0,1",
         "EventCode": "0x2C",
         "EventName": "L2_DATA_RQSTS.SELF.M_STATE",
         "SampleAfterValue": "200000",
@@ -97,7 +85,6 @@
     },
     {
         "BriefDescription": "All data requests from the L1 data cache",
-        "Counter": "0,1",
         "EventCode": "0x2C",
         "EventName": "L2_DATA_RQSTS.SELF.S_STATE",
         "SampleAfterValue": "200000",
@@ -105,7 +92,6 @@
     },
     {
         "BriefDescription": "Cycles the L2 cache data bus is busy.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "L2_DBUS_BUSY.SELF",
         "SampleAfterValue": "200000",
@@ -113,7 +99,6 @@
     },
     {
         "BriefDescription": "Cycles the L2 transfers data to the core.",
-        "Counter": "0,1",
         "EventCode": "0x23",
         "EventName": "L2_DBUS_BUSY_RD.SELF",
         "SampleAfterValue": "200000",
@@ -121,7 +106,6 @@
     },
     {
         "BriefDescription": "L2 cacheable instruction fetch requests",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "L2_IFETCH.SELF.E_STATE",
         "SampleAfterValue": "200000",
@@ -129,7 +113,6 @@
     },
     {
         "BriefDescription": "L2 cacheable instruction fetch requests",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "L2_IFETCH.SELF.I_STATE",
         "SampleAfterValue": "200000",
@@ -137,7 +120,6 @@
     },
     {
         "BriefDescription": "L2 cacheable instruction fetch requests",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "L2_IFETCH.SELF.MESI",
         "SampleAfterValue": "200000",
@@ -145,7 +127,6 @@
     },
     {
         "BriefDescription": "L2 cacheable instruction fetch requests",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "L2_IFETCH.SELF.M_STATE",
         "SampleAfterValue": "200000",
@@ -153,7 +134,6 @@
     },
     {
         "BriefDescription": "L2 cacheable instruction fetch requests",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "L2_IFETCH.SELF.S_STATE",
         "SampleAfterValue": "200000",
@@ -161,7 +141,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.ANY.E_STATE",
         "SampleAfterValue": "200000",
@@ -169,7 +148,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.ANY.I_STATE",
         "SampleAfterValue": "200000",
@@ -177,7 +155,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.ANY.MESI",
         "SampleAfterValue": "200000",
@@ -185,7 +162,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.ANY.M_STATE",
         "SampleAfterValue": "200000",
@@ -193,7 +169,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.ANY.S_STATE",
         "SampleAfterValue": "200000",
@@ -201,7 +176,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.DEMAND.E_STATE",
         "SampleAfterValue": "200000",
@@ -209,7 +183,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.DEMAND.I_STATE",
         "SampleAfterValue": "200000",
@@ -217,7 +190,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.DEMAND.MESI",
         "SampleAfterValue": "200000",
@@ -225,7 +197,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.DEMAND.M_STATE",
         "SampleAfterValue": "200000",
@@ -233,7 +204,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.DEMAND.S_STATE",
         "SampleAfterValue": "200000",
@@ -241,7 +211,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.PREFETCH.E_STATE",
         "SampleAfterValue": "200000",
@@ -249,7 +218,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.PREFETCH.I_STATE",
         "SampleAfterValue": "200000",
@@ -257,7 +225,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.PREFETCH.MESI",
         "SampleAfterValue": "200000",
@@ -265,7 +232,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.PREFETCH.M_STATE",
         "SampleAfterValue": "200000",
@@ -273,7 +239,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.PREFETCH.S_STATE",
         "SampleAfterValue": "200000",
@@ -281,7 +246,6 @@
     },
     {
         "BriefDescription": "All read requests from L1 instruction and data caches",
-        "Counter": "0,1",
         "EventCode": "0x2D",
         "EventName": "L2_LD_IFETCH.SELF.E_STATE",
         "SampleAfterValue": "200000",
@@ -289,7 +253,6 @@
     },
     {
         "BriefDescription": "All read requests from L1 instruction and data caches",
-        "Counter": "0,1",
         "EventCode": "0x2D",
         "EventName": "L2_LD_IFETCH.SELF.I_STATE",
         "SampleAfterValue": "200000",
@@ -297,7 +260,6 @@
     },
     {
         "BriefDescription": "All read requests from L1 instruction and data caches",
-        "Counter": "0,1",
         "EventCode": "0x2D",
         "EventName": "L2_LD_IFETCH.SELF.MESI",
         "SampleAfterValue": "200000",
@@ -305,7 +267,6 @@
     },
     {
         "BriefDescription": "All read requests from L1 instruction and data caches",
-        "Counter": "0,1",
         "EventCode": "0x2D",
         "EventName": "L2_LD_IFETCH.SELF.M_STATE",
         "SampleAfterValue": "200000",
@@ -313,7 +274,6 @@
     },
     {
         "BriefDescription": "All read requests from L1 instruction and data caches",
-        "Counter": "0,1",
         "EventCode": "0x2D",
         "EventName": "L2_LD_IFETCH.SELF.S_STATE",
         "SampleAfterValue": "200000",
@@ -321,7 +281,6 @@
     },
     {
         "BriefDescription": "L2 cache misses.",
-        "Counter": "0,1",
         "EventCode": "0x24",
         "EventName": "L2_LINES_IN.SELF.ANY",
         "SampleAfterValue": "200000",
@@ -329,7 +288,6 @@
     },
     {
         "BriefDescription": "L2 cache misses.",
-        "Counter": "0,1",
         "EventCode": "0x24",
         "EventName": "L2_LINES_IN.SELF.DEMAND",
         "SampleAfterValue": "200000",
@@ -337,7 +295,6 @@
     },
     {
         "BriefDescription": "L2 cache misses.",
-        "Counter": "0,1",
         "EventCode": "0x24",
         "EventName": "L2_LINES_IN.SELF.PREFETCH",
         "SampleAfterValue": "200000",
@@ -345,7 +302,6 @@
     },
     {
         "BriefDescription": "L2 cache lines evicted.",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "L2_LINES_OUT.SELF.ANY",
         "SampleAfterValue": "200000",
@@ -353,7 +309,6 @@
     },
     {
         "BriefDescription": "L2 cache lines evicted.",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "L2_LINES_OUT.SELF.DEMAND",
         "SampleAfterValue": "200000",
@@ -361,7 +316,6 @@
     },
     {
         "BriefDescription": "L2 cache lines evicted.",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "L2_LINES_OUT.SELF.PREFETCH",
         "SampleAfterValue": "200000",
@@ -369,7 +323,6 @@
     },
     {
         "BriefDescription": "L2 locked accesses",
-        "Counter": "0,1",
         "EventCode": "0x2B",
         "EventName": "L2_LOCK.SELF.E_STATE",
         "SampleAfterValue": "200000",
@@ -377,7 +330,6 @@
     },
     {
         "BriefDescription": "L2 locked accesses",
-        "Counter": "0,1",
         "EventCode": "0x2B",
         "EventName": "L2_LOCK.SELF.I_STATE",
         "SampleAfterValue": "200000",
@@ -385,7 +337,6 @@
     },
     {
         "BriefDescription": "L2 locked accesses",
-        "Counter": "0,1",
         "EventCode": "0x2B",
         "EventName": "L2_LOCK.SELF.MESI",
         "SampleAfterValue": "200000",
@@ -393,7 +344,6 @@
     },
     {
         "BriefDescription": "L2 locked accesses",
-        "Counter": "0,1",
         "EventCode": "0x2B",
         "EventName": "L2_LOCK.SELF.M_STATE",
         "SampleAfterValue": "200000",
@@ -401,7 +351,6 @@
     },
     {
         "BriefDescription": "L2 locked accesses",
-        "Counter": "0,1",
         "EventCode": "0x2B",
         "EventName": "L2_LOCK.SELF.S_STATE",
         "SampleAfterValue": "200000",
@@ -409,7 +358,6 @@
     },
     {
         "BriefDescription": "L2 cache line modifications.",
-        "Counter": "0,1",
         "EventCode": "0x25",
         "EventName": "L2_M_LINES_IN.SELF",
         "SampleAfterValue": "200000",
@@ -417,7 +365,6 @@
     },
     {
         "BriefDescription": "Modified lines evicted from the L2 cache",
-        "Counter": "0,1",
         "EventCode": "0x27",
         "EventName": "L2_M_LINES_OUT.SELF.ANY",
         "SampleAfterValue": "200000",
@@ -425,7 +372,6 @@
     },
     {
         "BriefDescription": "Modified lines evicted from the L2 cache",
-        "Counter": "0,1",
         "EventCode": "0x27",
         "EventName": "L2_M_LINES_OUT.SELF.DEMAND",
         "SampleAfterValue": "200000",
@@ -433,7 +379,6 @@
     },
     {
         "BriefDescription": "Modified lines evicted from the L2 cache",
-        "Counter": "0,1",
         "EventCode": "0x27",
         "EventName": "L2_M_LINES_OUT.SELF.PREFETCH",
         "SampleAfterValue": "200000",
@@ -441,7 +386,6 @@
     },
     {
         "BriefDescription": "Cycles no L2 cache requests are pending",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "L2_NO_REQ.SELF",
         "SampleAfterValue": "200000",
@@ -449,7 +393,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE",
         "SampleAfterValue": "200000",
@@ -457,7 +400,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE",
         "SampleAfterValue": "200000",
@@ -465,7 +407,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI",
         "SampleAfterValue": "200000",
@@ -473,7 +414,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE",
         "SampleAfterValue": "200000",
@@ -481,7 +421,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE",
         "SampleAfterValue": "200000",
@@ -489,7 +428,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE",
         "SampleAfterValue": "200000",
@@ -497,7 +435,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE",
         "SampleAfterValue": "200000",
@@ -505,7 +442,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI",
         "SampleAfterValue": "200000",
@@ -513,7 +449,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE",
         "SampleAfterValue": "200000",
@@ -521,7 +456,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE",
         "SampleAfterValue": "200000",
@@ -529,7 +463,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE",
         "SampleAfterValue": "200000",
@@ -537,7 +470,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE",
         "SampleAfterValue": "200000",
@@ -545,7 +477,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI",
         "SampleAfterValue": "200000",
@@ -553,7 +484,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE",
         "SampleAfterValue": "200000",
@@ -561,7 +491,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE",
         "SampleAfterValue": "200000",
@@ -569,7 +498,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.ANY.E_STATE",
         "SampleAfterValue": "200000",
@@ -577,7 +505,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.ANY.I_STATE",
         "SampleAfterValue": "200000",
@@ -585,7 +512,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.ANY.MESI",
         "SampleAfterValue": "200000",
@@ -593,7 +519,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.ANY.M_STATE",
         "SampleAfterValue": "200000",
@@ -601,7 +526,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.ANY.S_STATE",
         "SampleAfterValue": "200000",
@@ -609,7 +533,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.DEMAND.E_STATE",
         "SampleAfterValue": "200000",
@@ -617,7 +540,6 @@
     },
     {
         "BriefDescription": "L2 cache demand requests from this core that missed the L2",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.DEMAND.I_STATE",
         "SampleAfterValue": "200000",
@@ -625,7 +547,6 @@
     },
     {
         "BriefDescription": "L2 cache demand requests from this core",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.DEMAND.MESI",
         "SampleAfterValue": "200000",
@@ -633,7 +554,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.DEMAND.M_STATE",
         "SampleAfterValue": "200000",
@@ -641,7 +561,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.DEMAND.S_STATE",
         "SampleAfterValue": "200000",
@@ -649,7 +568,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE",
         "SampleAfterValue": "200000",
@@ -657,7 +575,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE",
         "SampleAfterValue": "200000",
@@ -665,7 +582,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.PREFETCH.MESI",
         "SampleAfterValue": "200000",
@@ -673,7 +589,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE",
         "SampleAfterValue": "200000",
@@ -681,7 +596,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE",
         "SampleAfterValue": "200000",
@@ -689,7 +603,6 @@
     },
     {
         "BriefDescription": "L2 store requests",
-        "Counter": "0,1",
         "EventCode": "0x2A",
         "EventName": "L2_ST.SELF.E_STATE",
         "SampleAfterValue": "200000",
@@ -697,7 +610,6 @@
     },
     {
         "BriefDescription": "L2 store requests",
-        "Counter": "0,1",
         "EventCode": "0x2A",
         "EventName": "L2_ST.SELF.I_STATE",
         "SampleAfterValue": "200000",
@@ -705,7 +617,6 @@
     },
     {
         "BriefDescription": "L2 store requests",
-        "Counter": "0,1",
         "EventCode": "0x2A",
         "EventName": "L2_ST.SELF.MESI",
         "SampleAfterValue": "200000",
@@ -713,7 +624,6 @@
     },
     {
         "BriefDescription": "L2 store requests",
-        "Counter": "0,1",
         "EventCode": "0x2A",
         "EventName": "L2_ST.SELF.M_STATE",
         "SampleAfterValue": "200000",
@@ -721,7 +631,6 @@
     },
     {
         "BriefDescription": "L2 store requests",
-        "Counter": "0,1",
         "EventCode": "0x2A",
         "EventName": "L2_ST.SELF.S_STATE",
         "SampleAfterValue": "200000",
@@ -729,7 +638,6 @@
     },
     {
         "BriefDescription": "Retired loads that hit the L2 cache (precise event).",
-        "Counter": "0,1",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.L2_HIT",
         "SampleAfterValue": "200000",
@@ -737,7 +645,6 @@
     },
     {
         "BriefDescription": "Retired loads that miss the L2 cache",
-        "Counter": "0,1",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.L2_MISS",
         "SampleAfterValue": "10000",
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json b/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json
index 1fa347d07c989..18bf5ec47e728 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Floating point assists for retired operations.",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "FP_ASSIST.AR",
         "SampleAfterValue": "10000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Floating point assists.",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "FP_ASSIST.S",
         "SampleAfterValue": "10000",
@@ -17,15 +15,12 @@
     },
     {
         "BriefDescription": "SIMD assists invoked.",
-        "Counter": "0,1",
         "EventCode": "0xCD",
         "EventName": "SIMD_ASSIST",
-        "SampleAfterValue": "100000",
-        "UMask": "0x0"
+        "SampleAfterValue": "100000"
     },
     {
         "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions.",
-        "Counter": "0,1",
         "EventCode": "0xCA",
         "EventName": "SIMD_COMP_INST_RETIRED.PACKED_SINGLE",
         "SampleAfterValue": "2000000",
@@ -33,7 +28,6 @@
     },
     {
         "BriefDescription": "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
-        "Counter": "0,1",
         "EventCode": "0xCA",
         "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE",
         "SampleAfterValue": "2000000",
@@ -41,7 +35,6 @@
     },
     {
         "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions.",
-        "Counter": "0,1",
         "EventCode": "0xCA",
         "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_SINGLE",
         "SampleAfterValue": "2000000",
@@ -49,15 +42,12 @@
     },
     {
         "BriefDescription": "SIMD Instructions retired.",
-        "Counter": "0,1",
         "EventCode": "0xCE",
         "EventName": "SIMD_INSTR_RETIRED",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Retired Streaming SIMD Extensions (SSE) packed-single instructions.",
-        "Counter": "0,1",
         "EventCode": "0xC7",
         "EventName": "SIMD_INST_RETIRED.PACKED_SINGLE",
         "SampleAfterValue": "2000000",
@@ -65,7 +55,6 @@
     },
     {
         "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
-        "Counter": "0,1",
         "EventCode": "0xC7",
         "EventName": "SIMD_INST_RETIRED.SCALAR_DOUBLE",
         "SampleAfterValue": "2000000",
@@ -73,7 +62,6 @@
     },
     {
         "BriefDescription": "Retired Streaming SIMD Extensions (SSE) scalar-single instructions.",
-        "Counter": "0,1",
         "EventCode": "0xC7",
         "EventName": "SIMD_INST_RETIRED.SCALAR_SINGLE",
         "SampleAfterValue": "2000000",
@@ -81,7 +69,6 @@
     },
     {
         "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions.",
-        "Counter": "0,1",
         "EventCode": "0xC7",
         "EventName": "SIMD_INST_RETIRED.VECTOR",
         "SampleAfterValue": "2000000",
@@ -89,15 +76,12 @@
     },
     {
         "BriefDescription": "Saturated arithmetic instructions retired.",
-        "Counter": "0,1",
         "EventCode": "0xCF",
         "EventName": "SIMD_SAT_INSTR_RETIRED",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "SIMD saturated arithmetic micro-ops retired.",
-        "Counter": "0,1",
         "EventCode": "0xB1",
         "EventName": "SIMD_SAT_UOP_EXEC.AR",
         "SampleAfterValue": "2000000",
@@ -105,15 +89,12 @@
     },
     {
         "BriefDescription": "SIMD saturated arithmetic micro-ops executed.",
-        "Counter": "0,1",
         "EventCode": "0xB1",
         "EventName": "SIMD_SAT_UOP_EXEC.S",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "SIMD micro-ops retired (excluding stores).",
-        "Counter": "0,1",
         "EventCode": "0xB0",
         "EventName": "SIMD_UOPS_EXEC.AR",
         "PEBS": "2",
@@ -122,15 +103,12 @@
     },
     {
         "BriefDescription": "SIMD micro-ops executed (excluding stores).",
-        "Counter": "0,1",
         "EventCode": "0xB0",
         "EventName": "SIMD_UOPS_EXEC.S",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "SIMD packed arithmetic micro-ops retired",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR",
         "SampleAfterValue": "2000000",
@@ -138,7 +116,6 @@
     },
     {
         "BriefDescription": "SIMD packed arithmetic micro-ops executed",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.S",
         "SampleAfterValue": "2000000",
@@ -146,7 +123,6 @@
     },
     {
         "BriefDescription": "SIMD packed logical micro-ops retired",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.AR",
         "SampleAfterValue": "2000000",
@@ -154,7 +130,6 @@
     },
     {
         "BriefDescription": "SIMD packed logical micro-ops executed",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.S",
         "SampleAfterValue": "2000000",
@@ -162,7 +137,6 @@
     },
     {
         "BriefDescription": "SIMD packed multiply micro-ops retired",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.MUL.AR",
         "SampleAfterValue": "2000000",
@@ -170,7 +144,6 @@
     },
     {
         "BriefDescription": "SIMD packed multiply micro-ops executed",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.MUL.S",
         "SampleAfterValue": "2000000",
@@ -178,7 +151,6 @@
     },
     {
         "BriefDescription": "SIMD packed micro-ops retired",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.PACK.AR",
         "SampleAfterValue": "2000000",
@@ -186,7 +158,6 @@
     },
     {
         "BriefDescription": "SIMD packed micro-ops executed",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.PACK.S",
         "SampleAfterValue": "2000000",
@@ -194,7 +165,6 @@
     },
     {
         "BriefDescription": "SIMD packed shift micro-ops retired",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.AR",
         "SampleAfterValue": "2000000",
@@ -202,7 +172,6 @@
     },
     {
         "BriefDescription": "SIMD packed shift micro-ops executed",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.S",
         "SampleAfterValue": "2000000",
@@ -210,7 +179,6 @@
     },
     {
         "BriefDescription": "SIMD unpacked micro-ops retired",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.AR",
         "SampleAfterValue": "2000000",
@@ -218,7 +186,6 @@
     },
     {
         "BriefDescription": "SIMD unpacked micro-ops executed",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.S",
         "SampleAfterValue": "2000000",
@@ -226,7 +193,6 @@
     },
     {
         "BriefDescription": "Floating point computational micro-ops retired.",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "X87_COMP_OPS_EXE.ANY.AR",
         "PEBS": "2",
@@ -235,7 +201,6 @@
     },
     {
         "BriefDescription": "Floating point computational micro-ops executed.",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "X87_COMP_OPS_EXE.ANY.S",
         "SampleAfterValue": "2000000",
@@ -243,7 +208,6 @@
     },
     {
         "BriefDescription": "FXCH uops retired.",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "X87_COMP_OPS_EXE.FXCH.AR",
         "PEBS": "2",
@@ -252,7 +216,6 @@
     },
     {
         "BriefDescription": "FXCH uops executed.",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "X87_COMP_OPS_EXE.FXCH.S",
         "SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json
index 21fe5fe229aa5..8d2f4edfb5976 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "BACLEARS asserted.",
-        "Counter": "0,1",
         "EventCode": "0xE6",
         "EventName": "BACLEARS.ANY",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Cycles during which instruction fetches are  stalled.",
-        "Counter": "0,1",
         "EventCode": "0x86",
         "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",
         "SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "Decode stall due to IQ full",
-        "Counter": "0,1",
         "EventCode": "0x87",
         "EventName": "DECODE_STALL.IQ_FULL",
         "SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "Decode stall due to PFB empty",
-        "Counter": "0,1",
         "EventCode": "0x87",
         "EventName": "DECODE_STALL.PFB_EMPTY",
         "SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "Instruction fetches.",
-        "Counter": "0,1",
         "EventCode": "0x80",
         "EventName": "ICACHE.ACCESSES",
         "SampleAfterValue": "200000",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "Icache hit",
-        "Counter": "0,1",
         "EventCode": "0x80",
         "EventName": "ICACHE.HIT",
         "SampleAfterValue": "200000",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "Icache miss",
-        "Counter": "0,1",
         "EventCode": "0x80",
         "EventName": "ICACHE.MISSES",
         "SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
     },
     {
         "BriefDescription": "All Instructions decoded",
-        "Counter": "0,1",
         "EventCode": "0xAA",
         "EventName": "MACRO_INSTS.ALL_DECODED",
         "SampleAfterValue": "2000000",
@@ -65,7 +57,6 @@
     },
     {
         "BriefDescription": "CISC macro instructions decoded",
-        "Counter": "0,1",
         "EventCode": "0xAA",
         "EventName": "MACRO_INSTS.CISC_DECODED",
         "SampleAfterValue": "2000000",
@@ -73,7 +64,6 @@
     },
     {
         "BriefDescription": "Non-CISC nacro instructions decoded",
-        "Counter": "0,1",
         "EventCode": "0xAA",
         "EventName": "MACRO_INSTS.NON_CISC_DECODED",
         "SampleAfterValue": "2000000",
@@ -81,7 +71,6 @@
     },
     {
         "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.",
-        "Counter": "0,1",
         "CounterMask": "1",
         "EventCode": "0xA9",
         "EventName": "UOPS.MS_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/memory.json b/tools/perf/pmu-events/arch/x86/bonnell/memory.json
index f8b45b6fb4d34..ac02dc2482c81 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/memory.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/memory.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Nonzero segbase 1 bubble",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.BUBBLE",
         "SampleAfterValue": "200000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Nonzero segbase load 1 bubble",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.LD_BUBBLE",
         "SampleAfterValue": "200000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "Load splits",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.LD_SPLIT",
         "SampleAfterValue": "200000",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "Load splits (At Retirement)",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR",
         "SampleAfterValue": "200000",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "Nonzero segbase ld-op-st 1 bubble",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.RMW_BUBBLE",
         "SampleAfterValue": "200000",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "ld-op-st splits",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.RMW_SPLIT",
         "SampleAfterValue": "200000",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "Memory references that cross an 8-byte boundary.",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.SPLIT",
         "SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
     },
     {
         "BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.SPLIT.AR",
         "SampleAfterValue": "200000",
@@ -65,7 +57,6 @@
     },
     {
         "BriefDescription": "Nonzero segbase store 1 bubble",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.ST_BUBBLE",
         "SampleAfterValue": "200000",
@@ -73,7 +64,6 @@
     },
     {
         "BriefDescription": "Store splits",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.ST_SPLIT",
         "SampleAfterValue": "200000",
@@ -81,7 +71,6 @@
     },
     {
         "BriefDescription": "Store splits (Ar Retirement)",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR",
         "SampleAfterValue": "200000",
@@ -89,7 +78,6 @@
     },
     {
         "BriefDescription": "L1 hardware prefetch request",
-        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.HW_PREFETCH",
         "SampleAfterValue": "2000000",
@@ -97,7 +85,6 @@
     },
     {
         "BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed",
-        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.PREFETCHNTA",
         "SampleAfterValue": "200000",
@@ -105,7 +92,6 @@
     },
     {
         "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.",
-        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.PREFETCHT0",
         "SampleAfterValue": "200000",
@@ -113,7 +99,6 @@
     },
     {
         "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.",
-        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.PREFETCHT1",
         "SampleAfterValue": "200000",
@@ -121,7 +106,6 @@
     },
     {
         "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.",
-        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.PREFETCHT2",
         "SampleAfterValue": "200000",
@@ -129,7 +113,6 @@
     },
     {
         "BriefDescription": "Any Software prefetch",
-        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.SOFTWARE_PREFETCH",
         "SampleAfterValue": "200000",
@@ -137,7 +120,6 @@
     },
     {
         "BriefDescription": "Any Software prefetch",
-        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.SOFTWARE_PREFETCH.AR",
         "SampleAfterValue": "200000",
@@ -145,7 +127,6 @@
     },
     {
         "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed",
-        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.SW_L2",
         "SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/other.json b/tools/perf/pmu-events/arch/x86/bonnell/other.json
index e0bdcfbfa9dcf..782594c8bda5b 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/other.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/other.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Bus queue is empty.",
-        "Counter": "0,1",
         "EventCode": "0x7D",
         "EventName": "BUSQ_EMPTY.SELF",
         "SampleAfterValue": "200000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Number of Bus Not Ready signals asserted.",
-        "Counter": "0,1",
         "EventCode": "0x61",
         "EventName": "BUS_BNR_DRV.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -17,15 +15,12 @@
     },
     {
         "BriefDescription": "Number of Bus Not Ready signals asserted.",
-        "Counter": "0,1",
         "EventCode": "0x61",
         "EventName": "BUS_BNR_DRV.THIS_AGENT",
-        "SampleAfterValue": "200000",
-        "UMask": "0x0"
+        "SampleAfterValue": "200000"
     },
     {
         "BriefDescription": "Bus cycles while processor receives data.",
-        "Counter": "0,1",
         "EventCode": "0x64",
         "EventName": "BUS_DATA_RCV.SELF",
         "SampleAfterValue": "200000",
@@ -33,7 +28,6 @@
     },
     {
         "BriefDescription": "Bus cycles when data is sent on the bus.",
-        "Counter": "0,1",
         "EventCode": "0x62",
         "EventName": "BUS_DRDY_CLOCKS.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -41,15 +35,12 @@
     },
     {
         "BriefDescription": "Bus cycles when data is sent on the bus.",
-        "Counter": "0,1",
         "EventCode": "0x62",
         "EventName": "BUS_DRDY_CLOCKS.THIS_AGENT",
-        "SampleAfterValue": "200000",
-        "UMask": "0x0"
+        "SampleAfterValue": "200000"
     },
     {
         "BriefDescription": "HITM signal asserted.",
-        "Counter": "0,1",
         "EventCode": "0x7B",
         "EventName": "BUS_HITM_DRV.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -57,15 +48,12 @@
     },
     {
         "BriefDescription": "HITM signal asserted.",
-        "Counter": "0,1",
         "EventCode": "0x7B",
         "EventName": "BUS_HITM_DRV.THIS_AGENT",
-        "SampleAfterValue": "200000",
-        "UMask": "0x0"
+        "SampleAfterValue": "200000"
     },
     {
         "BriefDescription": "HIT signal asserted.",
-        "Counter": "0,1",
         "EventCode": "0x7A",
         "EventName": "BUS_HIT_DRV.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -73,15 +61,12 @@
     },
     {
         "BriefDescription": "HIT signal asserted.",
-        "Counter": "0,1",
         "EventCode": "0x7A",
         "EventName": "BUS_HIT_DRV.THIS_AGENT",
-        "SampleAfterValue": "200000",
-        "UMask": "0x0"
+        "SampleAfterValue": "200000"
     },
     {
         "BriefDescription": "IO requests waiting in the bus queue.",
-        "Counter": "0,1",
         "EventCode": "0x7F",
         "EventName": "BUS_IO_WAIT.SELF",
         "SampleAfterValue": "200000",
@@ -89,7 +74,6 @@
     },
     {
         "BriefDescription": "Bus cycles when a LOCK signal is asserted.",
-        "Counter": "0,1",
         "EventCode": "0x63",
         "EventName": "BUS_LOCK_CLOCKS.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -97,7 +81,6 @@
     },
     {
         "BriefDescription": "Bus cycles when a LOCK signal is asserted.",
-        "Counter": "0,1",
         "EventCode": "0x63",
         "EventName": "BUS_LOCK_CLOCKS.SELF",
         "SampleAfterValue": "200000",
@@ -105,7 +88,6 @@
     },
     {
         "BriefDescription": "Outstanding cacheable data read bus requests duration.",
-        "Counter": "0,1",
         "EventCode": "0x60",
         "EventName": "BUS_REQUEST_OUTSTANDING.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -113,7 +95,6 @@
     },
     {
         "BriefDescription": "Outstanding cacheable data read bus requests duration.",
-        "Counter": "0,1",
         "EventCode": "0x60",
         "EventName": "BUS_REQUEST_OUTSTANDING.SELF",
         "SampleAfterValue": "200000",
@@ -121,7 +102,6 @@
     },
     {
         "BriefDescription": "All bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x70",
         "EventName": "BUS_TRANS_ANY.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -129,7 +109,6 @@
     },
     {
         "BriefDescription": "All bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x70",
         "EventName": "BUS_TRANS_ANY.SELF",
         "SampleAfterValue": "200000",
@@ -137,7 +116,6 @@
     },
     {
         "BriefDescription": "Burst read bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x65",
         "EventName": "BUS_TRANS_BRD.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -145,7 +123,6 @@
     },
     {
         "BriefDescription": "Burst read bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x65",
         "EventName": "BUS_TRANS_BRD.SELF",
         "SampleAfterValue": "200000",
@@ -153,7 +130,6 @@
     },
     {
         "BriefDescription": "Burst (full cache-line) bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x6E",
         "EventName": "BUS_TRANS_BURST.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -161,7 +137,6 @@
     },
     {
         "BriefDescription": "Burst (full cache-line) bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x6E",
         "EventName": "BUS_TRANS_BURST.SELF",
         "SampleAfterValue": "200000",
@@ -169,7 +144,6 @@
     },
     {
         "BriefDescription": "Deferred bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x6D",
         "EventName": "BUS_TRANS_DEF.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -177,7 +151,6 @@
     },
     {
         "BriefDescription": "Deferred bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x6D",
         "EventName": "BUS_TRANS_DEF.SELF",
         "SampleAfterValue": "200000",
@@ -185,7 +158,6 @@
     },
     {
         "BriefDescription": "Instruction-fetch bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x68",
         "EventName": "BUS_TRANS_IFETCH.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -193,7 +165,6 @@
     },
     {
         "BriefDescription": "Instruction-fetch bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x68",
         "EventName": "BUS_TRANS_IFETCH.SELF",
         "SampleAfterValue": "200000",
@@ -201,7 +172,6 @@
     },
     {
         "BriefDescription": "Invalidate bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x69",
         "EventName": "BUS_TRANS_INVAL.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -209,7 +179,6 @@
     },
     {
         "BriefDescription": "Invalidate bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x69",
         "EventName": "BUS_TRANS_INVAL.SELF",
         "SampleAfterValue": "200000",
@@ -217,7 +186,6 @@
     },
     {
         "BriefDescription": "IO bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x6C",
         "EventName": "BUS_TRANS_IO.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -225,7 +193,6 @@
     },
     {
         "BriefDescription": "IO bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x6C",
         "EventName": "BUS_TRANS_IO.SELF",
         "SampleAfterValue": "200000",
@@ -233,7 +200,6 @@
     },
     {
         "BriefDescription": "Memory bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x6F",
         "EventName": "BUS_TRANS_MEM.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -241,7 +207,6 @@
     },
     {
         "BriefDescription": "Memory bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x6F",
         "EventName": "BUS_TRANS_MEM.SELF",
         "SampleAfterValue": "200000",
@@ -249,7 +214,6 @@
     },
     {
         "BriefDescription": "Partial bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x6B",
         "EventName": "BUS_TRANS_P.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -257,7 +221,6 @@
     },
     {
         "BriefDescription": "Partial bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x6B",
         "EventName": "BUS_TRANS_P.SELF",
         "SampleAfterValue": "200000",
@@ -265,7 +228,6 @@
     },
     {
         "BriefDescription": "Partial write bus transaction.",
-        "Counter": "0,1",
         "EventCode": "0x6A",
         "EventName": "BUS_TRANS_PWR.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -273,7 +235,6 @@
     },
     {
         "BriefDescription": "Partial write bus transaction.",
-        "Counter": "0,1",
         "EventCode": "0x6A",
         "EventName": "BUS_TRANS_PWR.SELF",
         "SampleAfterValue": "200000",
@@ -281,7 +242,6 @@
     },
     {
         "BriefDescription": "RFO bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x66",
         "EventName": "BUS_TRANS_RFO.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -289,7 +249,6 @@
     },
     {
         "BriefDescription": "RFO bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x66",
         "EventName": "BUS_TRANS_RFO.SELF",
         "SampleAfterValue": "200000",
@@ -297,7 +256,6 @@
     },
     {
         "BriefDescription": "Explicit writeback bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x67",
         "EventName": "BUS_TRANS_WB.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -305,7 +263,6 @@
     },
     {
         "BriefDescription": "Explicit writeback bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x67",
         "EventName": "BUS_TRANS_WB.SELF",
         "SampleAfterValue": "200000",
@@ -313,7 +270,6 @@
     },
     {
         "BriefDescription": "Cycles during which interrupts are disabled.",
-        "Counter": "0,1",
         "EventCode": "0xC6",
         "EventName": "CYCLES_INT_MASKED.CYCLES_INT_MASKED",
         "SampleAfterValue": "2000000",
@@ -321,7 +277,6 @@
     },
     {
         "BriefDescription": "Cycles during which interrupts are pending and disabled.",
-        "Counter": "0,1",
         "EventCode": "0xC6",
         "EventName": "CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED",
         "SampleAfterValue": "2000000",
@@ -329,7 +284,6 @@
     },
     {
         "BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason",
-        "Counter": "0,1",
         "EventCode": "0x9",
         "EventName": "DISPATCH_BLOCKED.ANY",
         "SampleAfterValue": "200000",
@@ -337,15 +291,12 @@
     },
     {
         "BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
-        "Counter": "0,1",
         "EventCode": "0x3A",
         "EventName": "EIST_TRANS",
-        "SampleAfterValue": "200000",
-        "UMask": "0x0"
+        "SampleAfterValue": "200000"
     },
     {
         "BriefDescription": "External snoops.",
-        "Counter": "0,1",
         "EventCode": "0x77",
         "EventName": "EXT_SNOOP.ALL_AGENTS.ANY",
         "SampleAfterValue": "200000",
@@ -353,7 +304,6 @@
     },
     {
         "BriefDescription": "External snoops.",
-        "Counter": "0,1",
         "EventCode": "0x77",
         "EventName": "EXT_SNOOP.ALL_AGENTS.CLEAN",
         "SampleAfterValue": "200000",
@@ -361,7 +311,6 @@
     },
     {
         "BriefDescription": "External snoops.",
-        "Counter": "0,1",
         "EventCode": "0x77",
         "EventName": "EXT_SNOOP.ALL_AGENTS.HIT",
         "SampleAfterValue": "200000",
@@ -369,7 +318,6 @@
     },
     {
         "BriefDescription": "External snoops.",
-        "Counter": "0,1",
         "EventCode": "0x77",
         "EventName": "EXT_SNOOP.ALL_AGENTS.HITM",
         "SampleAfterValue": "200000",
@@ -377,7 +325,6 @@
     },
     {
         "BriefDescription": "External snoops.",
-        "Counter": "0,1",
         "EventCode": "0x77",
         "EventName": "EXT_SNOOP.THIS_AGENT.ANY",
         "SampleAfterValue": "200000",
@@ -385,7 +332,6 @@
     },
     {
         "BriefDescription": "External snoops.",
-        "Counter": "0,1",
         "EventCode": "0x77",
         "EventName": "EXT_SNOOP.THIS_AGENT.CLEAN",
         "SampleAfterValue": "200000",
@@ -393,7 +339,6 @@
     },
     {
         "BriefDescription": "External snoops.",
-        "Counter": "0,1",
         "EventCode": "0x77",
         "EventName": "EXT_SNOOP.THIS_AGENT.HIT",
         "SampleAfterValue": "200000",
@@ -401,7 +346,6 @@
     },
     {
         "BriefDescription": "External snoops.",
-        "Counter": "0,1",
         "EventCode": "0x77",
         "EventName": "EXT_SNOOP.THIS_AGENT.HITM",
         "SampleAfterValue": "200000",
@@ -409,15 +353,12 @@
     },
     {
         "BriefDescription": "Hardware interrupts received.",
-        "Counter": "0,1",
         "EventCode": "0xC8",
         "EventName": "HW_INT_RCV",
-        "SampleAfterValue": "200000",
-        "UMask": "0x0"
+        "SampleAfterValue": "200000"
     },
     {
         "BriefDescription": "Number of segment register loads.",
-        "Counter": "0,1",
         "EventCode": "0x6",
         "EventName": "SEGMENT_REG_LOADS.ANY",
         "SampleAfterValue": "200000",
@@ -425,7 +366,6 @@
     },
     {
         "BriefDescription": "Bus stalled for snoops.",
-        "Counter": "0,1",
         "EventCode": "0x7E",
         "EventName": "SNOOP_STALL_DRV.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -433,7 +373,6 @@
     },
     {
         "BriefDescription": "Bus stalled for snoops.",
-        "Counter": "0,1",
         "EventCode": "0x7E",
         "EventName": "SNOOP_STALL_DRV.SELF",
         "SampleAfterValue": "200000",
@@ -441,7 +380,6 @@
     },
     {
         "BriefDescription": "Number of thermal trips",
-        "Counter": "0,1",
         "EventCode": "0x3B",
         "EventName": "THERMAL_TRIP",
         "SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json b/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json
index f5123c99a7ba6..91b98ee8ba9a2 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Bogus branches",
-        "Counter": "0,1",
         "EventCode": "0xE4",
         "EventName": "BOGUS_BR",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Branch instructions decoded",
-        "Counter": "0,1",
         "EventCode": "0xE0",
         "EventName": "BR_INST_DECODED",
         "SampleAfterValue": "2000000",
@@ -17,15 +15,12 @@
     },
     {
         "BriefDescription": "Retired branch instructions.",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ANY",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Retired branch instructions.",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ANY1",
         "SampleAfterValue": "2000000",
@@ -33,16 +28,13 @@
     },
     {
         "BriefDescription": "Retired mispredicted branch instructions (precise event).",
-        "Counter": "0,1",
         "EventCode": "0xC5",
         "EventName": "BR_INST_RETIRED.MISPRED",
         "PEBS": "1",
-        "SampleAfterValue": "200000",
-        "UMask": "0x0"
+        "SampleAfterValue": "200000"
     },
     {
         "BriefDescription": "Retired branch instructions that were mispredicted not-taken.",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.MISPRED_NOT_TAKEN",
         "SampleAfterValue": "200000",
@@ -50,7 +42,6 @@
     },
     {
         "BriefDescription": "Retired branch instructions that were mispredicted taken.",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.MISPRED_TAKEN",
         "SampleAfterValue": "200000",
@@ -58,7 +49,6 @@
     },
     {
         "BriefDescription": "Retired branch instructions that were predicted not-taken.",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.PRED_NOT_TAKEN",
         "SampleAfterValue": "2000000",
@@ -66,7 +56,6 @@
     },
     {
         "BriefDescription": "Retired branch instructions that were predicted taken.",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.PRED_TAKEN",
         "SampleAfterValue": "2000000",
@@ -74,7 +63,6 @@
     },
     {
         "BriefDescription": "Retired taken branch instructions.",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.TAKEN",
         "SampleAfterValue": "2000000",
@@ -82,7 +70,6 @@
     },
     {
         "BriefDescription": "All macro conditional branch instructions.",
-        "Counter": "0,1",
         "EventCode": "0x88",
         "EventName": "BR_INST_TYPE_RETIRED.COND",
         "SampleAfterValue": "2000000",
@@ -90,7 +77,6 @@
     },
     {
         "BriefDescription": "Only taken macro conditional branch instructions",
-        "Counter": "0,1",
         "EventCode": "0x88",
         "EventName": "BR_INST_TYPE_RETIRED.COND_TAKEN",
         "SampleAfterValue": "2000000",
@@ -98,7 +84,6 @@
     },
     {
         "BriefDescription": "All non-indirect calls",
-        "Counter": "0,1",
         "EventCode": "0x88",
         "EventName": "BR_INST_TYPE_RETIRED.DIR_CALL",
         "SampleAfterValue": "2000000",
@@ -106,7 +91,6 @@
     },
     {
         "BriefDescription": "All indirect branches that are not calls.",
-        "Counter": "0,1",
         "EventCode": "0x88",
         "EventName": "BR_INST_TYPE_RETIRED.IND",
         "SampleAfterValue": "2000000",
@@ -114,7 +98,6 @@
     },
     {
         "BriefDescription": "All indirect calls, including both register and memory indirect.",
-        "Counter": "0,1",
         "EventCode": "0x88",
         "EventName": "BR_INST_TYPE_RETIRED.IND_CALL",
         "SampleAfterValue": "2000000",
@@ -122,7 +105,6 @@
     },
     {
         "BriefDescription": "All indirect branches that have a return mnemonic",
-        "Counter": "0,1",
         "EventCode": "0x88",
         "EventName": "BR_INST_TYPE_RETIRED.RET",
         "SampleAfterValue": "2000000",
@@ -130,7 +112,6 @@
     },
     {
         "BriefDescription": "All macro unconditional branch instructions, excluding calls and indirects",
-        "Counter": "0,1",
         "EventCode": "0x88",
         "EventName": "BR_INST_TYPE_RETIRED.UNCOND",
         "SampleAfterValue": "2000000",
@@ -138,7 +119,6 @@
     },
     {
         "BriefDescription": "Mispredicted cond branch instructions retired",
-        "Counter": "0,1",
         "EventCode": "0x89",
         "EventName": "BR_MISSP_TYPE_RETIRED.COND",
         "SampleAfterValue": "200000",
@@ -146,7 +126,6 @@
     },
     {
         "BriefDescription": "Mispredicted and taken cond branch instructions retired",
-        "Counter": "0,1",
         "EventCode": "0x89",
         "EventName": "BR_MISSP_TYPE_RETIRED.COND_TAKEN",
         "SampleAfterValue": "200000",
@@ -154,7 +133,6 @@
     },
     {
         "BriefDescription": "Mispredicted ind branches that are not calls",
-        "Counter": "0,1",
         "EventCode": "0x89",
         "EventName": "BR_MISSP_TYPE_RETIRED.IND",
         "SampleAfterValue": "200000",
@@ -162,7 +140,6 @@
     },
     {
         "BriefDescription": "Mispredicted indirect calls, including both register and memory indirect.",
-        "Counter": "0,1",
         "EventCode": "0x89",
         "EventName": "BR_MISSP_TYPE_RETIRED.IND_CALL",
         "SampleAfterValue": "200000",
@@ -170,7 +147,6 @@
     },
     {
         "BriefDescription": "Mispredicted return branches",
-        "Counter": "0,1",
         "EventCode": "0x89",
         "EventName": "BR_MISSP_TYPE_RETIRED.RETURN",
         "SampleAfterValue": "200000",
@@ -178,7 +154,6 @@
     },
     {
         "BriefDescription": "Bus cycles when core is not halted",
-        "Counter": "0,1",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.BUS",
         "SampleAfterValue": "200000",
@@ -186,31 +161,24 @@
     },
     {
         "BriefDescription": "Core cycles when core is not halted",
-        "Counter": "Fixed counter 2",
         "EventCode": "0xA",
         "EventName": "CPU_CLK_UNHALTED.CORE",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Core cycles when core is not halted",
-        "Counter": "0,1",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.CORE_P",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Reference cycles when core is not halted.",
-        "Counter": "Fixed counter 3",
         "EventCode": "0xA",
         "EventName": "CPU_CLK_UNHALTED.REF",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Cycles the divider is busy.",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "CYCLES_DIV_BUSY",
         "SampleAfterValue": "2000000",
@@ -218,7 +186,6 @@
     },
     {
         "BriefDescription": "Divide operations retired",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "DIV.AR",
         "SampleAfterValue": "2000000",
@@ -226,7 +193,6 @@
     },
     {
         "BriefDescription": "Divide operations executed.",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "DIV.S",
         "SampleAfterValue": "2000000",
@@ -234,24 +200,19 @@
     },
     {
         "BriefDescription": "Instructions retired.",
-        "Counter": "Fixed counter 1",
         "EventCode": "0xA",
         "EventName": "INST_RETIRED.ANY",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Instructions retired (precise event).",
-        "Counter": "0,1",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.ANY_P",
         "PEBS": "2",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Self-Modifying Code detected.",
-        "Counter": "0,1",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.SMC",
         "SampleAfterValue": "200000",
@@ -259,7 +220,6 @@
     },
     {
         "BriefDescription": "Multiply operations retired",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "MUL.AR",
         "SampleAfterValue": "2000000",
@@ -267,7 +227,6 @@
     },
     {
         "BriefDescription": "Multiply operations executed.",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "MUL.S",
         "SampleAfterValue": "2000000",
@@ -275,7 +234,6 @@
     },
     {
         "BriefDescription": "Micro-op reissues for any cause",
-        "Counter": "0,1",
         "EventCode": "0x3",
         "EventName": "REISSUE.ANY",
         "SampleAfterValue": "200000",
@@ -283,7 +241,6 @@
     },
     {
         "BriefDescription": "Micro-op reissues for any cause (At Retirement)",
-        "Counter": "0,1",
         "EventCode": "0x3",
         "EventName": "REISSUE.ANY.AR",
         "SampleAfterValue": "200000",
@@ -291,7 +248,6 @@
     },
     {
         "BriefDescription": "Micro-op reissues on a store-load collision",
-        "Counter": "0,1",
         "EventCode": "0x3",
         "EventName": "REISSUE.OVERLAP_STORE",
         "SampleAfterValue": "200000",
@@ -299,7 +255,6 @@
     },
     {
         "BriefDescription": "Micro-op reissues on a store-load collision (At Retirement)",
-        "Counter": "0,1",
         "EventCode": "0x3",
         "EventName": "REISSUE.OVERLAP_STORE.AR",
         "SampleAfterValue": "200000",
@@ -307,7 +262,6 @@
     },
     {
         "BriefDescription": "Cycles issue is stalled due to div busy.",
-        "Counter": "0,1",
         "EventCode": "0xDC",
         "EventName": "RESOURCE_STALLS.DIV_BUSY",
         "SampleAfterValue": "2000000",
@@ -315,7 +269,6 @@
     },
     {
         "BriefDescription": "All store forwards",
-        "Counter": "0,1",
         "EventCode": "0x2",
         "EventName": "STORE_FORWARDS.ANY",
         "SampleAfterValue": "200000",
@@ -323,7 +276,6 @@
     },
     {
         "BriefDescription": "Good store forwards",
-        "Counter": "0,1",
         "EventCode": "0x2",
         "EventName": "STORE_FORWARDS.GOOD",
         "SampleAfterValue": "200000",
@@ -331,7 +283,6 @@
     },
     {
         "BriefDescription": "Micro-ops retired.",
-        "Counter": "0,1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ANY",
         "SampleAfterValue": "2000000",
@@ -339,7 +290,6 @@
     },
     {
         "BriefDescription": "Cycles no micro-ops retired.",
-        "Counter": "0,1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.STALLED_CYCLES",
         "SampleAfterValue": "2000000",
@@ -347,7 +297,6 @@
     },
     {
         "BriefDescription": "Periods no micro-ops retired.",
-        "Counter": "0,1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.STALLS",
         "SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json b/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json
index e8512c585572e..82e07c73cff07 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Memory accesses that missed the DTLB.",
-        "Counter": "0,1",
         "EventCode": "0x8",
         "EventName": "DATA_TLB_MISSES.DTLB_MISS",
         "SampleAfterValue": "200000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "DTLB misses due to load operations.",
-        "Counter": "0,1",
         "EventCode": "0x8",
         "EventName": "DATA_TLB_MISSES.DTLB_MISS_LD",
         "SampleAfterValue": "200000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "DTLB misses due to store operations.",
-        "Counter": "0,1",
         "EventCode": "0x8",
         "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
         "SampleAfterValue": "200000",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "L0 DTLB misses due to load operations.",
-        "Counter": "0,1",
         "EventCode": "0x8",
         "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
         "SampleAfterValue": "200000",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "L0 DTLB misses due to store operations",
-        "Counter": "0,1",
         "EventCode": "0x8",
         "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST",
         "SampleAfterValue": "200000",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "ITLB flushes.",
-        "Counter": "0,1",
         "EventCode": "0x82",
         "EventName": "ITLB.FLUSH",
         "SampleAfterValue": "200000",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "ITLB hits.",
-        "Counter": "0,1",
         "EventCode": "0x82",
         "EventName": "ITLB.HIT",
         "SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
     },
     {
         "BriefDescription": "ITLB misses.",
-        "Counter": "0,1",
         "EventCode": "0x82",
         "EventName": "ITLB.MISSES",
         "PEBS": "2",
@@ -66,7 +58,6 @@
     },
     {
         "BriefDescription": "Retired loads that miss the DTLB (precise event).",
-        "Counter": "0,1",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
         "PEBS": "1",
@@ -75,7 +66,6 @@
     },
     {
         "BriefDescription": "Duration of page-walks in core cycles",
-        "Counter": "0,1",
         "EventCode": "0xC",
         "EventName": "PAGE_WALKS.CYCLES",
         "SampleAfterValue": "2000000",
@@ -83,7 +73,6 @@
     },
     {
         "BriefDescription": "Duration of D-side only page walks",
-        "Counter": "0,1",
         "EventCode": "0xC",
         "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
         "SampleAfterValue": "2000000",
@@ -91,7 +80,6 @@
     },
     {
         "BriefDescription": "Number of D-side only page walks",
-        "Counter": "0,1",
         "EventCode": "0xC",
         "EventName": "PAGE_WALKS.D_SIDE_WALKS",
         "SampleAfterValue": "200000",
@@ -99,7 +87,6 @@
     },
     {
         "BriefDescription": "Duration of I-Side page walks",
-        "Counter": "0,1",
         "EventCode": "0xC",
         "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
         "SampleAfterValue": "2000000",
@@ -107,7 +94,6 @@
     },
     {
         "BriefDescription": "Number of I-Side page walks",
-        "Counter": "0,1",
         "EventCode": "0xC",
         "EventName": "PAGE_WALKS.I_SIDE_WALKS",
         "SampleAfterValue": "200000",
@@ -115,7 +101,6 @@
     },
     {
         "BriefDescription": "Number of page-walks executed.",
-        "Counter": "0,1",
         "EventCode": "0xC",
         "EventName": "PAGE_WALKS.WALKS",
         "SampleAfterValue": "200000",
-- 
GitLab


From fec57a8e4a2cede35adbd9d70f1826ea312c49b3 Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:47:28 -0800
Subject: [PATCH 567/875] perf vendor events intel: Refresh broadwell metrics
 and events

Update the broadwell metrics and events using the new tooling from:

  https://github.com/intel/perfmon

The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1".  The
events are unchanged but unused json values are removed, implicit
umasks of 0 are dropped and duplicate short and long descriptions have
the long one dropped. This increases consistency across the json
files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215064755.1620246-6-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../arch/x86/broadwell/bdw-metrics.json       | 137 +--
 .../pmu-events/arch/x86/broadwell/cache.json  | 957 ------------------
 .../arch/x86/broadwell/floating-point.json    |  40 -
 .../arch/x86/broadwell/frontend.json          |  56 -
 .../pmu-events/arch/x86/broadwell/memory.json | 890 ----------------
 .../pmu-events/arch/x86/broadwell/other.json  |   8 -
 .../arch/x86/broadwell/pipeline.json          | 272 -----
 .../arch/x86/broadwell/uncore-cache.json      |  19 -
 .../arch/x86/broadwell/uncore-other.json      |  25 +-
 .../arch/x86/broadwell/virtual-memory.json    |  76 --
 10 files changed, 84 insertions(+), 2396 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json b/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json
index c220b1cf1740d..c3ea39d6c944b 100644
--- a/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json
@@ -110,7 +110,7 @@
     },
     {
         "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
-        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
         "MetricGroup": "TopdownL1;tma_L1_group",
         "MetricName": "tma_bad_speculation",
         "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
@@ -118,7 +118,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
-        "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
+        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
         "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
         "MetricName": "tma_branch_mispredicts",
         "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
@@ -142,7 +142,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
-        "MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB)) * tma_backend_bound",
+        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) * tma_backend_bound",
         "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
         "MetricName": "tma_memory_bound",
         "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@@ -174,7 +174,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
-        "MetricExpr": "(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
+        "MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
         "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
         "MetricName": "tma_lock_latency",
         "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS",
@@ -214,7 +214,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
-        "MetricExpr": "(MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
+        "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
         "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_l3_bound",
         "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
@@ -222,7 +222,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
-        "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / CLKS",
+        "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / CLKS",
         "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_contested_accesses",
         "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
@@ -230,7 +230,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
-        "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
+        "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
         "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_data_sharing",
         "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
@@ -238,7 +238,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
-        "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
+        "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
         "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_l3_hit_latency",
         "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
@@ -246,7 +246,7 @@
     },
     {
         "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
-        "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
+        "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
         "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_sq_full",
         "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
@@ -254,7 +254,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
-        "MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS))) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
+        "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
         "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_dram_bound",
         "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS",
@@ -286,7 +286,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
-        "MetricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES))) + (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
+        "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
         "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
         "MetricName": "tma_store_latency",
         "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
@@ -334,7 +334,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
-        "MetricExpr": "((CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS",
+        "MetricExpr": "((CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS",
         "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
         "MetricName": "tma_ports_utilization",
         "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@@ -342,7 +342,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@) / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else 0) / CORE_CLKS",
+        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) / CORE_CLKS)",
         "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
         "MetricName": "tma_ports_utilized_0",
         "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
@@ -350,7 +350,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS",
+        "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS)",
         "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
         "MetricName": "tma_ports_utilized_1",
         "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
@@ -358,7 +358,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
+        "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS)",
         "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
         "MetricName": "tma_ports_utilized_2",
         "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
@@ -366,14 +366,14 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
-        "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
+        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
         "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
         "MetricName": "tma_ports_utilized_3m",
         "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
-        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / (4 * CORE_CLKS)",
+        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS",
         "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
         "MetricName": "tma_alu_op_utilization",
         "ScaleUnit": "100%"
@@ -429,7 +429,7 @@
     },
     {
         "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
+        "MetricExpr": "tma_port_4",
         "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
         "MetricName": "tma_store_op_utilization",
         "ScaleUnit": "100%"
@@ -522,7 +522,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
-        "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
         "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
         "MetricName": "tma_microcode_sequencer",
         "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
@@ -595,26 +595,26 @@
     },
     {
         "BriefDescription": "Floating Point Operations Per Cycle",
-        "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
         "MetricGroup": "Flops;Ret",
         "MetricName": "FLOPc"
     },
     {
         "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
-        "MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
         "MetricGroup": "Cor;Flops;HPC",
         "MetricName": "FP_Arith_Utilization",
         "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
     },
     {
         "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
         "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
         "MetricName": "ILP"
     },
     {
         "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
-        "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
+        "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
         "MetricGroup": "SMT",
         "MetricName": "CORE_CLKS"
     },
@@ -656,13 +656,13 @@
     },
     {
         "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
         "MetricGroup": "Flops;InsType",
         "MetricName": "IpFLOP"
     },
     {
         "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
         "MetricGroup": "Flops;InsType",
         "MetricName": "IpArith",
         "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
@@ -715,7 +715,7 @@
     },
     {
         "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
-        "MetricExpr": "IDQ.DSB_UOPS / ((IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS))",
+        "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
         "MetricGroup": "DSB;Fed;FetchBW",
         "MetricName": "DSB_Coverage"
     },
@@ -727,13 +727,13 @@
     },
     {
         "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
-        "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
+        "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
         "MetricGroup": "Bad;BrMispredicts",
         "MetricName": "Branch_Misprediction_Cost"
     },
     {
         "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
-        "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb)",
+        "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)",
         "MetricGroup": "Mem;MemoryBound;MemoryLat",
         "MetricName": "Load_Miss_Real_Latency"
     },
@@ -745,43 +745,43 @@
     },
     {
         "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L1MPKI"
     },
     {
         "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
         "MetricGroup": "Backend;CacheMisses;Mem",
         "MetricName": "L2MPKI"
     },
     {
         "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem;Offcore",
         "MetricName": "L2MPKI_All"
     },
     {
         "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L2MPKI_Load"
     },
     {
         "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
-        "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L2HPKI_All"
     },
     {
         "BriefDescription": "L2 cache hits per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L2HPKI_Load"
     },
     {
         "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L3MPKI"
     },
@@ -794,19 +794,19 @@
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
-        "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
+        "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L1D_Cache_Fill_BW"
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
-        "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
+        "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L2_Cache_Fill_BW"
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
+        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L3_Cache_Fill_BW"
     },
@@ -836,19 +836,19 @@
     },
     {
         "BriefDescription": "Average CPU Utilization",
-        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
+        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
         "MetricGroup": "HPC;Summary",
         "MetricName": "CPU_Utilization"
     },
     {
         "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
-        "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
+        "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
         "MetricGroup": "Power;Summary",
         "MetricName": "Average_Frequency"
     },
     {
         "BriefDescription": "Giga Floating Point Operations Per Second",
-        "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1000000000) / duration_time",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time",
         "MetricGroup": "Cor;Flops;HPC",
         "MetricName": "GFLOPs",
         "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
@@ -861,7 +861,7 @@
     },
     {
         "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
-        "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
+        "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
         "MetricGroup": "SMT",
         "MetricName": "SMT_2T_Utilization"
     },
@@ -879,68 +879,87 @@
     },
     {
         "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
-        "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1000000 / duration_time / 1000",
+        "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3",
         "MetricGroup": "HPC;Mem;MemoryBW;SoC",
         "MetricName": "DRAM_BW_Use"
     },
     {
         "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)",
-        "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
+        "MetricExpr": "MEM_Parallel_Requests",
         "MetricGroup": "Mem;SoC",
         "MetricName": "MEM_Request_Latency"
     },
     {
         "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests",
-        "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
+        "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL",
         "MetricGroup": "Mem;SoC",
         "MetricName": "MEM_Parallel_Requests"
     },
+    {
+        "BriefDescription": "Socket actual clocks when any core is active on that socket",
+        "MetricExpr": "UNC_CLOCK.SOCKET",
+        "MetricGroup": "SoC",
+        "MetricName": "Socket_CLKS"
+    },
     {
         "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
         "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
         "MetricGroup": "Branches;OS",
         "MetricName": "IpFarBranch"
     },
+    {
+        "BriefDescription": "Uncore frequency per die [GHZ]",
+        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+        "MetricGroup": "SoC",
+        "MetricName": "UNCORE_FREQ"
+    },
     {
         "BriefDescription": "C3 residency percent per core",
-        "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C3_Core_Residency"
+        "MetricName": "C3_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C6 residency percent per core",
-        "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C6_Core_Residency"
+        "MetricName": "C6_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C7 residency percent per core",
-        "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C7_Core_Residency"
+        "MetricName": "C7_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C2 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C2_Pkg_Residency"
+        "MetricName": "C2_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C3 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C3_Pkg_Residency"
+        "MetricName": "C3_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C6 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C6_Pkg_Residency"
+        "MetricName": "C6_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C7 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C7_Pkg_Residency"
+        "MetricName": "C7_Pkg_Residency",
+        "ScaleUnit": "100%"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/broadwell/cache.json b/tools/perf/pmu-events/arch/x86/broadwell/cache.json
index f3d7fced28b69..26199d3ebb250 100644
--- a/tools/perf/pmu-events/arch/x86/broadwell/cache.json
+++ b/tools/perf/pmu-events/arch/x86/broadwell/cache.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "L1D data line replacements",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x51",
         "EventName": "L1D.REPLACEMENT",
         "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.FB_FULL",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "L1D miss oustandings duration in cycles",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING",
         "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Cycles with L1D load Misses outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -43,8 +35,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -53,8 +43,6 @@
     },
     {
         "BriefDescription": "Not rejected writebacks that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x27",
         "EventName": "L2_DEMAND_RQSTS.WB_HIT",
         "PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
@@ -63,8 +51,6 @@
     },
     {
         "BriefDescription": "L2 cache lines filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.ALL",
         "PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
@@ -73,8 +59,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in E state filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.E",
         "PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.",
@@ -83,8 +67,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in I state filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.I",
         "PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.",
@@ -93,8 +75,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in S state filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.S",
         "PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.",
@@ -103,8 +83,6 @@
     },
     {
         "BriefDescription": "Clean L2 cache lines evicted by demand.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
         "SampleAfterValue": "100003",
@@ -112,8 +90,6 @@
     },
     {
         "BriefDescription": "L2 code requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_CODE_RD",
         "PublicDescription": "This event counts the total number of L2 code requests.",
@@ -122,8 +98,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
         "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
@@ -132,8 +106,6 @@
     },
     {
         "BriefDescription": "Demand requests that miss L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
         "SampleAfterValue": "200003",
@@ -141,8 +113,6 @@
     },
     {
         "BriefDescription": "Demand requests to L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
         "SampleAfterValue": "200003",
@@ -150,8 +120,6 @@
     },
     {
         "BriefDescription": "Requests from L2 hardware prefetchers",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_PF",
         "PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.",
@@ -160,8 +128,6 @@
     },
     {
         "BriefDescription": "RFO requests to L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_RFO",
         "PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
@@ -170,8 +136,6 @@
     },
     {
         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_HIT",
         "SampleAfterValue": "200003",
@@ -179,8 +143,6 @@
     },
     {
         "BriefDescription": "L2 cache misses when fetching instructions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_MISS",
         "SampleAfterValue": "200003",
@@ -188,8 +150,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
         "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache.",
@@ -198,8 +158,6 @@
     },
     {
         "BriefDescription": "Demand Data Read miss L2, no rejects",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
         "PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
@@ -208,8 +166,6 @@
     },
     {
         "BriefDescription": "L2 prefetch requests that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.L2_PF_HIT",
         "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.",
@@ -218,8 +174,6 @@
     },
     {
         "BriefDescription": "L2 prefetch requests that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.L2_PF_MISS",
         "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.",
@@ -228,8 +182,6 @@
     },
     {
         "BriefDescription": "All requests that miss L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.MISS",
         "SampleAfterValue": "200003",
@@ -237,8 +189,6 @@
     },
     {
         "BriefDescription": "All L2 requests.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.REFERENCES",
         "SampleAfterValue": "200003",
@@ -246,8 +196,6 @@
     },
     {
         "BriefDescription": "RFO requests that hit L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_HIT",
         "SampleAfterValue": "200003",
@@ -255,8 +203,6 @@
     },
     {
         "BriefDescription": "RFO requests that miss L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_MISS",
         "SampleAfterValue": "200003",
@@ -264,8 +210,6 @@
     },
     {
         "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.ALL_PF",
         "PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects.",
@@ -274,8 +218,6 @@
     },
     {
         "BriefDescription": "Transactions accessing L2 pipe",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.ALL_REQUESTS",
         "PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.",
@@ -284,8 +226,6 @@
     },
     {
         "BriefDescription": "L2 cache accesses when fetching instructions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.CODE_RD",
         "PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.",
@@ -294,8 +234,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.DEMAND_DATA_RD",
         "PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.",
@@ -304,8 +242,6 @@
     },
     {
         "BriefDescription": "L1D writebacks that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L1D_WB",
         "PublicDescription": "This event counts L1D writebacks that access L2 cache.",
@@ -314,8 +250,6 @@
     },
     {
         "BriefDescription": "L2 fill requests that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L2_FILL",
         "PublicDescription": "This event counts L2 fill requests that access L2 cache.",
@@ -324,8 +258,6 @@
     },
     {
         "BriefDescription": "L2 writebacks that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L2_WB",
         "PublicDescription": "This event counts L2 writebacks that access L2 cache.",
@@ -334,8 +266,6 @@
     },
     {
         "BriefDescription": "RFO requests that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.RFO",
         "PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.",
@@ -344,8 +274,6 @@
     },
     {
         "BriefDescription": "Cycles when L1D is locked",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x63",
         "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
         "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",
@@ -354,8 +282,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests missed L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.MISS",
         "PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
@@ -364,8 +290,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
         "PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
@@ -374,8 +298,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM100",
         "EventCode": "0xD2",
@@ -387,8 +309,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM100",
         "EventCode": "0xD2",
@@ -400,8 +320,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM100",
         "EventCode": "0xD2",
@@ -413,8 +331,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM100",
         "EventCode": "0xD2",
@@ -426,8 +342,6 @@
     },
     {
         "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDE70, BDM100",
         "EventCode": "0xD3",
@@ -439,8 +353,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
@@ -451,8 +363,6 @@
     },
     {
         "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
@@ -463,8 +373,6 @@
     },
     {
         "BriefDescription": "Retired load uops misses in L1 cache as data sources.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
@@ -475,8 +383,6 @@
     },
     {
         "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM35",
         "EventCode": "0xD1",
@@ -488,8 +394,6 @@
     },
     {
         "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
@@ -500,8 +404,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM100",
         "EventCode": "0xD1",
@@ -513,8 +415,6 @@
     },
     {
         "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM100, BDE70",
         "EventCode": "0xD1",
@@ -525,8 +425,6 @@
     },
     {
         "BriefDescription": "All retired load uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
@@ -537,12 +435,9 @@
     },
     {
         "BriefDescription": "All retired store uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "PublicDescription": "This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement.",
         "SampleAfterValue": "2000003",
@@ -550,8 +445,6 @@
     },
     {
         "BriefDescription": "Retired load uops with locked access.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM35",
         "EventCode": "0xD0",
@@ -563,8 +456,6 @@
     },
     {
         "BriefDescription": "Retired load uops that split across a cacheline boundary.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
@@ -575,12 +466,9 @@
     },
     {
         "BriefDescription": "Retired store uops that split across a cacheline boundary.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
         "SampleAfterValue": "100003",
@@ -588,8 +476,6 @@
     },
     {
         "BriefDescription": "Retired load uops that miss the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
@@ -600,12 +486,9 @@
     },
     {
         "BriefDescription": "Retired store uops that miss the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "PublicDescription": "This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",
         "SampleAfterValue": "100003",
@@ -613,8 +496,6 @@
     },
     {
         "BriefDescription": "Demand and prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
         "PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
@@ -623,8 +504,6 @@
     },
     {
         "BriefDescription": "Any memory transaction that reached the SQ.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb0",
         "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
         "PublicDescription": "This event counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, and so on.",
@@ -633,8 +512,6 @@
     },
     {
         "BriefDescription": "Cacheable and noncachaeble code read requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
         "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.",
@@ -643,8 +520,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests sent to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
         "PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
@@ -653,8 +528,6 @@
     },
     {
         "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
         "PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
@@ -663,8 +536,6 @@
     },
     {
         "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb2",
         "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
         "PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.",
@@ -673,8 +544,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM76",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
@@ -684,8 +553,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "Errata": "BDM76",
         "EventCode": "0x60",
@@ -696,8 +563,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "Errata": "BDM76",
         "EventCode": "0x60",
@@ -708,8 +573,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "Errata": "BDM76",
         "EventCode": "0x60",
@@ -720,8 +583,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM76",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
@@ -731,8 +592,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM76",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
@@ -742,8 +601,6 @@
     },
     {
         "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "6",
         "Errata": "BDM76",
         "EventCode": "0x60",
@@ -753,8 +610,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM76",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
@@ -764,8 +619,6 @@
     },
     {
         "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE",
         "SampleAfterValue": "100003",
@@ -773,2634 +626,1824 @@
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads have any response type.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x04003C0091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x02003C0091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00803C0091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x01003C0091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400020091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200020091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080020091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100020091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads have any response type.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x04003C0240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x02003C0240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00803C0240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x01003C0240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400020240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200020240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080020240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100020240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads have any response type.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x04003C0090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x02003C0090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00803C0090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x01003C0090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400020090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200020090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080020090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100020090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs have any response type.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x04003C0120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x02003C0120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00803C0120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x01003C0120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400020120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200020120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080020120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100020120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs have any response type.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x04003C0122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x02003C0122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00803C0122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x01003C0122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400020122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200020122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080020122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100020122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive) have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive) have any response type.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x04003C0008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x02003C0008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00803C0008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x01003C0008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400020008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200020008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080020008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100020008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads have any response type.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x04003C0004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x02003C0004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00803C0004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x01003C0004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400020004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200020004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080020004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100020004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads have any response type.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x04003C0001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x02003C0001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00803C0001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x01003C0001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400020001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200020001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080020001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100020001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010002",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand data writes (RFOs) have any response type.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0002",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand data writes (RFOs)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0002",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand data writes (RFOs)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x04003C0002",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand data writes (RFOs)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x02003C0002",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand data writes (RFOs)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00803C0002",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand data writes (RFOs)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x01003C0002",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand data writes (RFOs)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000018000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests have any response type.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C8000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C8000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x04003C8000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x02003C8000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00803C8000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x01003C8000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80028000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000028000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400028000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200028000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080028000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100028000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads have any response type.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x04003C0040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x02003C0040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00803C0040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x01003C0040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400020040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200020040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080020040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100020040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads have any response type.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x04003C0010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x02003C0010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00803C0010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x01003C0010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400020010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200020010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080020010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100020010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs have any response type.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x04003C0020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x02003C0020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00803C0020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x01003C0020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400020020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200020020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080020020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100020020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads have any response type.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x04003C0200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x02003C0200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00803C0200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x01003C0200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400020200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200020200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080020200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100020200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x04003C0080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x02003C0080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00803C0080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x01003C0080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400020080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200020080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080020080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100020080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x04003C0100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x02003C0100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00803C0100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x01003C0100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400020100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200020100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080020100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100020100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Split locks in SQ",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xf4",
         "EventName": "SQ_MISC.SPLIT_LOCK",
         "PublicDescription": "This event counts the number of split locks in the super queue.",
diff --git a/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json b/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json
index 6322116d0d468..0de16d9a80da1 100644
--- a/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
         "SampleAfterValue": "2000003",
@@ -10,8 +8,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
         "SampleAfterValue": "2000003",
@@ -19,8 +15,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
         "SampleAfterValue": "2000003",
@@ -28,8 +22,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
         "SampleAfterValue": "2000003",
@@ -37,8 +29,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
         "SampleAfterValue": "2000006",
@@ -46,8 +36,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.PACKED",
         "SampleAfterValue": "2000004",
@@ -55,8 +43,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation.   Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.SCALAR",
         "SampleAfterValue": "2000003",
@@ -64,8 +50,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
         "SampleAfterValue": "2000003",
@@ -73,8 +57,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
         "SampleAfterValue": "2000003",
@@ -82,8 +64,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.SINGLE",
         "SampleAfterValue": "2000005",
@@ -91,8 +71,6 @@
     },
     {
         "BriefDescription": "Cycles with any input/output SSE or FP assist",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.ANY",
@@ -102,8 +80,6 @@
     },
     {
         "BriefDescription": "Number of SIMD FP assists due to input values",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.SIMD_INPUT",
         "PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",
@@ -112,8 +88,6 @@
     },
     {
         "BriefDescription": "Number of SIMD FP assists due to Output values",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.SIMD_OUTPUT",
         "PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
@@ -122,8 +96,6 @@
     },
     {
         "BriefDescription": "Number of X87 assists due to input value.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.X87_INPUT",
         "PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
@@ -132,8 +104,6 @@
     },
     {
         "BriefDescription": "Number of X87 assists due to output value.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.X87_OUTPUT",
         "PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
@@ -142,8 +112,6 @@
     },
     {
         "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
         "SampleAfterValue": "1000003",
@@ -151,8 +119,6 @@
     },
     {
         "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
         "SampleAfterValue": "1000003",
@@ -160,8 +126,6 @@
     },
     {
         "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM30",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.AVX_TO_SSE",
@@ -171,8 +135,6 @@
     },
     {
         "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM30",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.SSE_TO_AVX",
@@ -182,8 +144,6 @@
     },
     {
         "BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xA0",
         "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF",
         "PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file.  The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*.  See the Broadwell Optimization Guide for more information.",
diff --git a/tools/perf/pmu-events/arch/x86/broadwell/frontend.json b/tools/perf/pmu-events/arch/x86/broadwell/frontend.json
index 37ce8034b2ed4..d0f6678609ae6 100644
--- a/tools/perf/pmu-events/arch/x86/broadwell/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/broadwell/frontend.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xe6",
         "EventName": "BACLEARS.ANY",
         "SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
     },
     {
         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAB",
         "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
         "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
@@ -20,8 +16,6 @@
     },
     {
         "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.HIT",
         "PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.",
@@ -30,8 +24,6 @@
     },
     {
         "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.IFDATA_STALL",
         "PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).",
@@ -40,8 +32,6 @@
     },
     {
         "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.MISSES",
         "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
@@ -50,8 +40,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -61,8 +49,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -72,8 +58,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering 4 Uops",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -83,8 +67,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering any Uop",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -94,8 +76,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_CYCLES",
@@ -105,8 +85,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_UOPS",
         "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
@@ -115,8 +93,6 @@
     },
     {
         "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0x79",
         "EventName": "IDQ.EMPTY",
         "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end.  It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",
@@ -125,8 +101,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_ALL_UOPS",
         "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@@ -135,8 +109,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_CYCLES",
@@ -146,8 +118,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_UOPS",
         "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@@ -156,8 +126,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_CYCLES",
@@ -167,8 +135,6 @@
     },
     {
         "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_DSB_CYCLES",
@@ -178,8 +144,6 @@
     },
     {
         "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
@@ -190,8 +154,6 @@
     },
     {
         "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_DSB_UOPS",
         "PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
@@ -200,8 +162,6 @@
     },
     {
         "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_MITE_UOPS",
         "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.",
@@ -210,8 +170,6 @@
     },
     {
         "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
@@ -221,8 +179,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_UOPS",
         "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
@@ -231,8 +187,6 @@
     },
     {
         "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
         "PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4  x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.",
@@ -241,8 +195,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -252,8 +204,6 @@
     },
     {
         "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@@ -263,8 +213,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "3",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@@ -274,8 +222,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@@ -284,8 +230,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
diff --git a/tools/perf/pmu-events/arch/x86/broadwell/memory.json b/tools/perf/pmu-events/arch/x86/broadwell/memory.json
index 2a77977381597..394ed602fcb10 100644
--- a/tools/perf/pmu-events/arch/x86/broadwell/memory.json
+++ b/tools/perf/pmu-events/arch/x86/broadwell/memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Number of times HLE abort was triggered",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED",
         "PEBS": "1",
@@ -12,8 +10,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC1",
         "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
@@ -22,8 +18,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC2",
         "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.",
@@ -32,8 +26,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC3",
         "PublicDescription": "Number of times a disallowed operation caused an HLE abort.",
@@ -42,8 +34,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC4",
         "PublicDescription": "Number of times HLE caused a fault.",
@@ -52,8 +42,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC5",
         "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.",
@@ -62,8 +50,6 @@
     },
     {
         "BriefDescription": "Number of times HLE commit succeeded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.COMMIT",
         "PublicDescription": "Number of times HLE commit succeeded.",
@@ -72,8 +58,6 @@
     },
     {
         "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.START",
         "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.",
@@ -82,8 +66,6 @@
     },
     {
         "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
         "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",
@@ -92,8 +74,6 @@
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 128",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xcd",
@@ -103,13 +83,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads with latency value being above 128.",
         "SampleAfterValue": "1009",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 16",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xcd",
@@ -119,13 +96,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads with latency value being above 16.",
         "SampleAfterValue": "20011",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 256",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xcd",
@@ -135,13 +109,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads with latency value being above 256.",
         "SampleAfterValue": "503",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 32",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xcd",
@@ -151,13 +122,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads with latency value being above 32.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 4",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xcd",
@@ -167,13 +135,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads with latency value being above four.",
         "SampleAfterValue": "100003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 512",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xcd",
@@ -183,13 +148,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads with latency value being above 512.",
         "SampleAfterValue": "101",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 64",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xcd",
@@ -199,13 +161,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads with latency value being above 64.",
         "SampleAfterValue": "2003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 8",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xcd",
@@ -215,13 +174,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads with latency value being above eight.",
         "SampleAfterValue": "50021",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x05",
         "EventName": "MISALIGN_MEM_REF.LOADS",
         "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",
@@ -230,8 +186,6 @@
     },
     {
         "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x05",
         "EventName": "MISALIGN_MEM_REF.STORES",
         "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",
@@ -240,2621 +194,1815 @@
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x20003C0091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x043C000091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x023C000091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00BC000091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x013C000091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0404000091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0204000091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0084000091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2004000091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0104000091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000020091",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x20003C0240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x043C000240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x023C000240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00BC000240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x013C000240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0404000240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0204000240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0084000240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2004000240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0104000240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000020240",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x20003C0090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x043C000090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x023C000090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00BC000090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x013C000090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0404000090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0204000090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0084000090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2004000090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0104000090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000020090",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x20003C0120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x043C000120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x023C000120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00BC000120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x013C000120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0404000120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0204000120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0084000120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2004000120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0104000120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000020120",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x20003C0122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x043C000122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x023C000122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00BC000122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x013C000122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0404000122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0204000122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0084000122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2004000122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0104000122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000020122",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand & prefetch RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x20003C0008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x043C000008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x023C000008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00BC000008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x013C000008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0404000008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0204000008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0084000008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2004000008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0104000008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks (modified to exclusive)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000020008",
-        "Offcore": "1",
-        "PublicDescription": "Counts writebacks (modified to exclusive)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x20003C0004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x043C000004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x023C000004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00BC000004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x013C000004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0404000004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0204000004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0084000004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2004000004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0104000004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000020004",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x20003C0001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x043C000001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x023C000001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00BC000001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x013C000001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0404000001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0204000001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0084000001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2004000001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0104000001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000020001",
-        "Offcore": "1",
-        "PublicDescription": "Counts demand data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x20003C0002",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand data writes (RFOs)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x043C000002",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand data writes (RFOs)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x023C000002",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand data writes (RFOs)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00BC000002",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand data writes (RFOs)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x013C000002",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand data writes (RFOs)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000002",
-        "Offcore": "1",
-        "PublicDescription": "Counts all demand data writes (RFOs)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x20003C8000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x043C008000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x023C008000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00BC008000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x013C008000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84008000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004008000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0404008000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0204008000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0084008000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2004008000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0104008000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000028000",
-        "Offcore": "1",
-        "PublicDescription": "Counts any other requests",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x20003C0040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x043C000040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x023C000040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00BC000040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x013C000040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0404000040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0204000040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0084000040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2004000040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0104000040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000020040",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x20003C0010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x043C000010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x023C000010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00BC000010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x013C000010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0404000010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0204000010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0084000010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2004000010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0104000010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000020010",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x20003C0020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x043C000020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x023C000020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00BC000020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x013C000020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0404000020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0204000020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0084000020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2004000020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0104000020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000020020",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x20003C0200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x043C000200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x023C000200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00BC000200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x013C000200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0404000200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0204000200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0084000200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2004000200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0104000200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000020200",
-        "Offcore": "1",
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x20003C0080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x043C000080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x023C000080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00BC000080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x013C000080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0404000080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0204000080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0084000080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2004000080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0104000080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000020080",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x20003C0100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x043C000100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x023C000100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00BC000100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x013C000100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0404000100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0204000100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0084000100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2004000100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0104000100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000020100",
-        "Offcore": "1",
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of times RTM abort was triggered",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED",
         "PEBS": "1",
@@ -2864,8 +2012,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC1",
         "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
@@ -2874,8 +2020,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC2",
         "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.",
@@ -2884,8 +2028,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC3",
         "PublicDescription": "Number of times a disallowed operation caused an RTM abort.",
@@ -2894,8 +2036,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC4",
         "PublicDescription": "Number of times a RTM caused a fault.",
@@ -2904,8 +2044,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC5",
         "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.",
@@ -2914,8 +2052,6 @@
     },
     {
         "BriefDescription": "Number of times RTM commit succeeded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.COMMIT",
         "PublicDescription": "Number of times RTM commit succeeded.",
@@ -2924,8 +2060,6 @@
     },
     {
         "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.START",
         "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.",
@@ -2934,8 +2068,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC1",
         "SampleAfterValue": "2000003",
@@ -2943,8 +2075,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC2",
         "PublicDescription": "Unfriendly TSX abort triggered by  a vzeroupper instruction.",
@@ -2953,8 +2083,6 @@
     },
     {
         "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC3",
         "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
@@ -2963,8 +2091,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC4",
         "PublicDescription": "RTM region detected inside HLE.",
@@ -2973,8 +2099,6 @@
     },
     {
         "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC5",
         "SampleAfterValue": "2000003",
@@ -2982,8 +2106,6 @@
     },
     {
         "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
         "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.",
@@ -2992,8 +2114,6 @@
     },
     {
         "BriefDescription": "Number of times a TSX line had a cache conflict",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CONFLICT",
         "PublicDescription": "Number of times a TSX line had a cache conflict.",
@@ -3002,8 +2122,6 @@
     },
     {
         "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
         "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
@@ -3012,8 +2130,6 @@
     },
     {
         "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
         "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
@@ -3022,8 +2138,6 @@
     },
     {
         "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
         "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
@@ -3032,8 +2146,6 @@
     },
     {
         "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
         "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
@@ -3042,8 +2154,6 @@
     },
     {
         "BriefDescription": "Number of times we could not allocate Lock Buffer",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
         "PublicDescription": "Number of times we could not allocate Lock Buffer.",
diff --git a/tools/perf/pmu-events/arch/x86/broadwell/other.json b/tools/perf/pmu-events/arch/x86/broadwell/other.json
index 917d145d52273..1c2a5b0019496 100644
--- a/tools/perf/pmu-events/arch/x86/broadwell/other.json
+++ b/tools/perf/pmu-events/arch/x86/broadwell/other.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5C",
         "EventName": "CPL_CYCLES.RING0",
         "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5C",
@@ -23,8 +19,6 @@
     },
     {
         "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5C",
         "EventName": "CPL_CYCLES.RING123",
         "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
@@ -33,8 +27,6 @@
     },
     {
         "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x63",
         "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
         "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",
diff --git a/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json b/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json
index e9a604e2d67c6..2f0fe6b353342 100644
--- a/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Cycles when divider is busy executing divide operations",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x14",
         "EventName": "ARITH.FPU_DIV_ACTIVE",
         "PublicDescription": "This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Speculative and retired  branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_BRANCHES",
         "PublicDescription": "This event counts both taken and not taken speculative and retired branch instructions.",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Speculative and retired macro-conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
         "PublicDescription": "This event counts both taken and not taken speculative and retired macro-conditional branch instructions.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
         "PublicDescription": "This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.",
@@ -41,8 +33,6 @@
     },
     {
         "BriefDescription": "Speculative and retired direct near calls",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
         "PublicDescription": "This event counts both taken and not taken speculative and retired direct near calls.",
@@ -51,8 +41,6 @@
     },
     {
         "BriefDescription": "Speculative and retired indirect branches excluding calls and returns",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
         "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.",
@@ -61,8 +49,6 @@
     },
     {
         "BriefDescription": "Speculative and retired indirect return branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
         "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.",
@@ -71,8 +57,6 @@
     },
     {
         "BriefDescription": "Not taken macro-conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
         "PublicDescription": "This event counts not taken macro-conditional branch instructions.",
@@ -81,8 +65,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired macro-conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
         "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions.",
@@ -91,8 +73,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
         "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.",
@@ -101,8 +81,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired direct near calls",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
         "PublicDescription": "This event counts taken speculative and retired direct near calls.",
@@ -111,8 +89,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
         "PublicDescription": "This event counts taken speculative and retired indirect branches excluding calls and return branches.",
@@ -121,8 +97,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect calls",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
         "PublicDescription": "This event counts taken speculative and retired indirect calls including both register and memory indirect.",
@@ -131,8 +105,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
         "PublicDescription": "This event counts taken speculative and retired indirect branches that have a return mnemonic.",
@@ -141,8 +113,6 @@
     },
     {
         "BriefDescription": "All (macro) branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "PublicDescription": "This event counts all (macro) branch instructions retired.",
@@ -150,8 +120,6 @@
     },
     {
         "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDW98",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
@@ -162,8 +130,6 @@
     },
     {
         "BriefDescription": "Conditional branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -173,8 +139,6 @@
     },
     {
         "BriefDescription": "Far branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDW98",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.FAR_BRANCH",
@@ -184,8 +148,6 @@
     },
     {
         "BriefDescription": "Direct and indirect near call instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -195,8 +157,6 @@
     },
     {
         "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
         "PEBS": "1",
@@ -206,8 +166,6 @@
     },
     {
         "BriefDescription": "Return instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_RETURN",
         "PEBS": "1",
@@ -217,8 +175,6 @@
     },
     {
         "BriefDescription": "Taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
@@ -228,8 +184,6 @@
     },
     {
         "BriefDescription": "Not taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NOT_TAKEN",
         "PublicDescription": "This event counts not taken branch instructions retired.",
@@ -238,8 +192,6 @@
     },
     {
         "BriefDescription": "Speculative and retired mispredicted macro conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_BRANCHES",
         "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.",
@@ -248,8 +200,6 @@
     },
     {
         "BriefDescription": "Speculative and retired mispredicted macro conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
         "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.",
@@ -258,8 +208,6 @@
     },
     {
         "BriefDescription": "Mispredicted indirect branches excluding calls and returns",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
         "PublicDescription": "This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.",
@@ -268,8 +216,6 @@
     },
     {
         "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
         "PublicDescription": "This event counts not taken speculative and retired mispredicted macro conditional branch instructions.",
@@ -278,8 +224,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
         "PublicDescription": "This event counts taken speculative and retired mispredicted macro conditional branch instructions.",
@@ -288,8 +232,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
         "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.",
@@ -298,8 +240,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect calls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
         "SampleAfterValue": "200003",
@@ -307,8 +247,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
         "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.",
@@ -317,8 +255,6 @@
     },
     {
         "BriefDescription": "All mispredicted macro branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PublicDescription": "This event counts all mispredicted macro branch instructions retired.",
@@ -326,8 +262,6 @@
     },
     {
         "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
         "PEBS": "2",
@@ -337,8 +271,6 @@
     },
     {
         "BriefDescription": "Mispredicted conditional branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -348,8 +280,6 @@
     },
     {
         "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
@@ -359,8 +289,6 @@
     },
     {
         "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.RET",
         "PEBS": "1",
@@ -370,8 +298,6 @@
     },
     {
         "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "100003",
@@ -379,8 +305,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
         "PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.",
@@ -390,8 +314,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
         "SampleAfterValue": "100003",
@@ -399,8 +321,6 @@
     },
     {
         "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "100003",
@@ -408,8 +328,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the core is not in halt state.",
-        "Counter": "Fixed counter 2",
-        "CounterHTOff": "Fixed counter 2",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
         "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
         "SampleAfterValue": "2000003",
@@ -417,8 +335,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
         "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
@@ -428,8 +344,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
         "SampleAfterValue": "100003",
@@ -437,8 +351,6 @@
     },
     {
         "BriefDescription": "Core cycles when the thread is not in halt state",
-        "Counter": "Fixed counter 1",
-        "CounterHTOff": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD",
         "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
         "SampleAfterValue": "2000003",
@@ -447,16 +359,12 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
-        "Counter": "Fixed counter 1",
-        "CounterHTOff": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Thread cycles when thread is not in halt state",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
         "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
@@ -465,16 +373,12 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "8",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
@@ -483,8 +387,6 @@
     },
     {
         "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "8",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
@@ -494,8 +396,6 @@
     },
     {
         "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
@@ -504,8 +404,6 @@
     },
     {
         "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
@@ -515,8 +413,6 @@
     },
     {
         "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
@@ -526,8 +422,6 @@
     },
     {
         "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
@@ -536,8 +430,6 @@
     },
     {
         "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
@@ -547,8 +439,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "12",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
@@ -557,8 +447,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "12",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
@@ -568,8 +456,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "5",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
@@ -578,8 +464,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "5",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
@@ -589,8 +473,6 @@
     },
     {
         "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "6",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",
@@ -600,8 +482,6 @@
     },
     {
         "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "6",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
@@ -610,8 +490,6 @@
     },
     {
         "BriefDescription": "Total execution stalls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
@@ -620,8 +498,6 @@
     },
     {
         "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.LCP",
         "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.",
@@ -630,8 +506,6 @@
     },
     {
         "BriefDescription": "Instructions retired from execution.",
-        "Counter": "Fixed counter 0",
-        "CounterHTOff": "Fixed counter 0",
         "EventName": "INST_RETIRED.ANY",
         "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
         "SampleAfterValue": "2000003",
@@ -639,8 +513,6 @@
     },
     {
         "BriefDescription": "Number of instructions retired. General Counter   - architectural event",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM61",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.ANY_P",
@@ -649,8 +521,6 @@
     },
     {
         "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
-        "Counter": "1",
-        "CounterHTOff": "1",
         "Errata": "BDM11, BDM55",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.PREC_DIST",
@@ -661,8 +531,6 @@
     },
     {
         "BriefDescription": "FP operations  retired. X87 FP operations that have no exceptions:",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.X87",
         "PublicDescription": "This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.",
@@ -671,8 +539,6 @@
     },
     {
         "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RAT_STALL_CYCLES",
         "PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.",
@@ -681,8 +547,6 @@
     },
     {
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES",
@@ -693,8 +557,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
@@ -703,8 +565,6 @@
     },
     {
         "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.NO_SR",
         "SampleAfterValue": "100003",
@@ -712,8 +572,6 @@
     },
     {
         "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.STORE_FORWARD",
         "PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.",
@@ -722,8 +580,6 @@
     },
     {
         "BriefDescription": "False dependencies in MOB due to partial compare",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x07",
         "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
         "PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",
@@ -732,8 +588,6 @@
     },
     {
         "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4C",
         "EventName": "LOAD_HIT_PRE.HW_PF",
         "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.",
@@ -742,8 +596,6 @@
     },
     {
         "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4c",
         "EventName": "LOAD_HIT_PRE.SW_PF",
         "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.",
@@ -752,8 +604,6 @@
     },
     {
         "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_4_UOPS",
@@ -762,8 +612,6 @@
     },
     {
         "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_ACTIVE",
@@ -772,8 +620,6 @@
     },
     {
         "BriefDescription": "Number of Uops delivered by the LSD.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA8",
         "EventName": "LSD.UOPS",
         "SampleAfterValue": "2000003",
@@ -781,8 +627,6 @@
     },
     {
         "BriefDescription": "Number of machine clears (nukes) of any type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xC3",
@@ -792,8 +636,6 @@
     },
     {
         "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.CYCLES",
         "PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.",
@@ -802,8 +644,6 @@
     },
     {
         "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MASKMOV",
         "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",
@@ -812,8 +652,6 @@
     },
     {
         "BriefDescription": "Self-modifying code (SMC) detected.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.SMC",
         "PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.",
@@ -822,8 +660,6 @@
     },
     {
         "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.INT_ELIMINATED",
         "SampleAfterValue": "1000003",
@@ -831,8 +667,6 @@
     },
     {
         "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",
         "SampleAfterValue": "1000003",
@@ -840,8 +674,6 @@
     },
     {
         "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",
         "SampleAfterValue": "100003",
@@ -849,8 +681,6 @@
     },
     {
         "BriefDescription": "Resource-related stall cycles",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa2",
         "EventName": "RESOURCE_STALLS.ANY",
         "PublicDescription": "This event counts resource-related stall cycles.",
@@ -859,8 +689,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to re-order buffer full.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ROB",
         "PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.",
@@ -869,8 +697,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no eligible RS entry available.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.RS",
         "PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
@@ -879,8 +705,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.SB",
         "PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
@@ -889,8 +713,6 @@
     },
     {
         "BriefDescription": "Count cases of saving new LBR",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCC",
         "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
         "PublicDescription": "This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.",
@@ -899,8 +721,6 @@
     },
     {
         "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5E",
         "EventName": "RS_EVENTS.EMPTY_CYCLES",
         "PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
@@ -909,8 +729,6 @@
     },
     {
         "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5E",
@@ -921,8 +739,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_0",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
@@ -931,8 +747,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 1",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_1",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
@@ -941,8 +755,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_2",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
@@ -951,8 +763,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_3",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
@@ -961,8 +771,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 4",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_4",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
@@ -971,8 +779,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 5",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_5",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
@@ -981,8 +787,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 6",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_6",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
@@ -991,8 +795,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 7",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_7",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
@@ -1001,8 +803,6 @@
     },
     {
         "BriefDescription": "Number of uops executed on the core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE",
         "PublicDescription": "Number of uops executed from any thread.",
@@ -1011,8 +811,6 @@
     },
     {
         "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@@ -1021,8 +819,6 @@
     },
     {
         "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@@ -1031,8 +827,6 @@
     },
     {
         "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@@ -1041,8 +835,6 @@
     },
     {
         "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@@ -1051,8 +843,6 @@
     },
     {
         "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
         "Invert": "1",
@@ -1061,8 +851,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 1 uop was executed per-thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
@@ -1071,8 +859,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 2 uops were executed per-thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
@@ -1081,8 +867,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 3 uops were executed per-thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
@@ -1091,8 +875,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 4 uops were executed per-thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
@@ -1101,8 +883,6 @@
     },
     {
         "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.STALL_CYCLES",
@@ -1113,8 +893,6 @@
     },
     {
         "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.THREAD",
         "PublicDescription": "Number of uops to be executed per-thread each cycle.",
@@ -1123,8 +901,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_0",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
@@ -1134,8 +910,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are exectuted in port 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE",
         "SampleAfterValue": "2000003",
@@ -1143,8 +917,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 1",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_1",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
@@ -1154,8 +926,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are exectuted in port 1.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE",
         "SampleAfterValue": "2000003",
@@ -1163,8 +933,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_2",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
@@ -1174,8 +942,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE",
         "SampleAfterValue": "2000003",
@@ -1183,8 +949,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_3",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
@@ -1194,8 +958,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE",
         "SampleAfterValue": "2000003",
@@ -1203,8 +965,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 4",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_4",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
@@ -1214,8 +974,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are exectuted in port 4.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE",
         "SampleAfterValue": "2000003",
@@ -1223,8 +981,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 5",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_5",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
@@ -1234,8 +990,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are exectuted in port 5.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE",
         "SampleAfterValue": "2000003",
@@ -1243,8 +997,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 6",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_6",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
@@ -1254,8 +1006,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are exectuted in port 6.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE",
         "SampleAfterValue": "2000003",
@@ -1263,8 +1013,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 7",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_7",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
@@ -1274,8 +1022,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 7.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE",
         "SampleAfterValue": "2000003",
@@ -1283,8 +1029,6 @@
     },
     {
         "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.ANY",
         "PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).",
@@ -1293,8 +1037,6 @@
     },
     {
         "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.FLAGS_MERGE",
         "PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.",
@@ -1303,8 +1045,6 @@
     },
     {
         "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.SINGLE_MUL",
         "SampleAfterValue": "2000003",
@@ -1312,8 +1052,6 @@
     },
     {
         "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.SLOW_LEA",
         "SampleAfterValue": "2000003",
@@ -1321,8 +1059,6 @@
     },
     {
         "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -1333,8 +1069,6 @@
     },
     {
         "BriefDescription": "Actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ALL",
         "PEBS": "1",
@@ -1344,8 +1078,6 @@
     },
     {
         "BriefDescription": "Retirement slots used.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
         "PEBS": "1",
@@ -1355,8 +1087,6 @@
     },
     {
         "BriefDescription": "Cycles without actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -1367,8 +1097,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 10 actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "10",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json b/tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json
index d1805b3a5e3d1..fcb15b880bad2 100644
--- a/tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
         "PerPkg": "1",
@@ -11,7 +10,6 @@
     },
     {
         "BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
         "PerPkg": "1",
@@ -21,7 +19,6 @@
     },
     {
         "BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
         "PerPkg": "1",
@@ -31,7 +28,6 @@
     },
     {
         "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
         "PerPkg": "1",
@@ -41,7 +37,6 @@
     },
     {
         "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
         "PerPkg": "1",
@@ -51,7 +46,6 @@
     },
     {
         "BriefDescription": "L3 Lookup read request that access cache and found line in I-state",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
         "PerPkg": "1",
@@ -61,7 +55,6 @@
     },
     {
         "BriefDescription": "L3 Lookup read request that access cache and found line in M-state",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
         "PerPkg": "1",
@@ -71,7 +64,6 @@
     },
     {
         "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
         "PerPkg": "1",
@@ -81,7 +73,6 @@
     },
     {
         "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
         "PerPkg": "1",
@@ -91,7 +82,6 @@
     },
     {
         "BriefDescription": "L3 Lookup write request that access cache and found line in M-state",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
         "PerPkg": "1",
@@ -101,7 +91,6 @@
     },
     {
         "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
         "PerPkg": "1",
@@ -111,41 +100,33 @@
     },
     {
         "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
         "UMask": "0x48",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
         "UMask": "0x44",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
         "UMask": "0x81",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
         "UMask": "0x41",
         "Unit": "CBO"
     }
diff --git a/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json b/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json
index 73c2261e1e94c..ddcf7faa9d10d 100644
--- a/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json
@@ -1,78 +1,65 @@
 [
     {
         "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
-        "Counter": "0,1",
         "EventCode": "0x84",
         "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
         "PerPkg": "1",
-        "PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
-        "Counter": "0,",
         "EventCode": "0x80",
         "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "PublicDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;",
-        "Counter": "0,",
         "CounterMask": "1",
         "EventCode": "0x80",
         "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
         "PerPkg": "1",
-        "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",
-        "Counter": "0,",
         "EventCode": "0x80",
         "EventName": "UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT",
         "PerPkg": "1",
         "PublicDescription": "Each cycle count number of valid coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
-        "Counter": "0,1",
         "EventCode": "0x81",
         "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
         "PerPkg": "1",
-        "PublicDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode",
-        "Counter": "0,1",
         "EventCode": "0x81",
         "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
         "PerPkg": "1",
         "PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
-        "Counter": "0,1",
         "EventCode": "0x81",
         "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
         "PerPkg": "1",
-        "PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
         "UMask": "0x20",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
-        "Counter": "FIXED",
         "EventCode": "0xff",
         "EventName": "UNC_CLOCK.SOCKET",
         "PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json b/tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json
index 6a6de8790f25f..93621e004d88f 100644
--- a/tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Load misses in all DTLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
@@ -12,8 +10,6 @@
     },
     {
         "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
         "SampleAfterValue": "2000003",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (2M).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
         "SampleAfterValue": "2000003",
@@ -30,8 +24,6 @@
     },
     {
         "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (4K).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
         "SampleAfterValue": "2000003",
@@ -39,8 +31,6 @@
     },
     {
         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
@@ -49,8 +39,6 @@
     },
     {
         "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
@@ -60,8 +48,6 @@
     },
     {
         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
@@ -71,8 +57,6 @@
     },
     {
         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
@@ -82,8 +66,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
@@ -93,8 +75,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
@@ -104,8 +84,6 @@
     },
     {
         "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT",
         "SampleAfterValue": "100003",
@@ -113,8 +91,6 @@
     },
     {
         "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (2M).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
         "SampleAfterValue": "100003",
@@ -122,8 +98,6 @@
     },
     {
         "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (4K).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
         "SampleAfterValue": "100003",
@@ -131,8 +105,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
@@ -141,8 +113,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
@@ -152,8 +122,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
@@ -163,8 +131,6 @@
     },
     {
         "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
@@ -174,8 +140,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_DURATION",
@@ -185,8 +149,6 @@
     },
     {
         "BriefDescription": "Cycle count for an Extended Page table walk.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4F",
         "EventName": "EPT.WALK_CYCLES",
         "PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.",
@@ -195,8 +157,6 @@
     },
     {
         "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAE",
         "EventName": "ITLB.ITLB_FLUSH",
         "PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
@@ -205,8 +165,6 @@
     },
     {
         "BriefDescription": "Misses at all ITLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
@@ -216,8 +174,6 @@
     },
     {
         "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT",
         "SampleAfterValue": "100003",
@@ -225,8 +181,6 @@
     },
     {
         "BriefDescription": "Code misses that miss the  DTLB and hit the STLB (2M).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT_2M",
         "SampleAfterValue": "100003",
@@ -234,8 +188,6 @@
     },
     {
         "BriefDescription": "Core misses that miss the  DTLB and hit the STLB (4K).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT_4K",
         "SampleAfterValue": "100003",
@@ -243,8 +195,6 @@
     },
     {
         "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
@@ -253,8 +203,6 @@
     },
     {
         "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
@@ -264,8 +212,6 @@
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
@@ -275,8 +221,6 @@
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
@@ -286,8 +230,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_DURATION",
@@ -297,8 +239,6 @@
     },
     {
         "BriefDescription": "Number of DTLB page walker hits in the L1+FB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDM69, BDM98",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.DTLB_L1",
@@ -307,8 +247,6 @@
     },
     {
         "BriefDescription": "Number of DTLB page walker hits in the L2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDM69, BDM98",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.DTLB_L2",
@@ -317,8 +255,6 @@
     },
     {
         "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDM69, BDM98",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.DTLB_L3",
@@ -327,8 +263,6 @@
     },
     {
         "BriefDescription": "Number of DTLB page walker hits in Memory.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDM69, BDM98",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
@@ -337,8 +271,6 @@
     },
     {
         "BriefDescription": "Number of ITLB page walker hits in the L1+FB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDM69, BDM98",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.ITLB_L1",
@@ -347,8 +279,6 @@
     },
     {
         "BriefDescription": "Number of ITLB page walker hits in the L2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDM69, BDM98",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.ITLB_L2",
@@ -357,8 +287,6 @@
     },
     {
         "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDM69, BDM98",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.ITLB_L3",
@@ -367,8 +295,6 @@
     },
     {
         "BriefDescription": "DTLB flush attempts of the thread-specific entries",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.DTLB_THREAD",
         "PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.",
@@ -377,8 +303,6 @@
     },
     {
         "BriefDescription": "STLB flush attempts",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.STLB_ANY",
         "PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).",
-- 
GitLab


From f6ee944ce4e857b7ba62218caf392f3cecc90c02 Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:49:51 -0800
Subject: [PATCH 568/875] perf vendor events intel: Refresh broadwellde metrics
 and events

Update the broadwellde metrics and events using the new tooling from:

  https://github.com/intel/perfmon

The metrics vary as tma_false_sharing, MEM_Parallel_Requests and
MEM_Request_Latency are explicitly dropped from having missing events:
https://github.com/captain5050/perfmon/blob/main/scripts/create_perf_json.py#L934
The formulas also differ due to parentheses, use of exponents and
removal of redundant operations like "* 1".  The events are unchanged
but unused json values are removed and implicit umasks of 0 are
dropped. This increases consistency across the json files.

mapfile.csv's version number is set to match that in the perfmon
repository.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065017.1621020-1-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../arch/x86/broadwellde/bdwde-metrics.json   | 143 +++---
 .../arch/x86/broadwellde/cache.json           | 153 ------
 .../arch/x86/broadwellde/floating-point.json  |  40 --
 .../arch/x86/broadwellde/frontend.json        |  56 --
 .../arch/x86/broadwellde/memory.json          |  86 ----
 .../arch/x86/broadwellde/other.json           |   8 -
 .../arch/x86/broadwellde/pipeline.json        | 272 ----------
 .../arch/x86/broadwellde/uncore-cache.json    | 414 ++-------------
 .../arch/x86/broadwellde/uncore-memory.json   | 477 +++---------------
 .../arch/x86/broadwellde/uncore-other.json    | 163 ++----
 .../arch/x86/broadwellde/uncore-power.json    |  57 ---
 .../arch/x86/broadwellde/virtual-memory.json  |  76 ---
 tools/perf/pmu-events/arch/x86/mapfile.csv    |   2 +-
 13 files changed, 211 insertions(+), 1736 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json b/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json
index 5a074cf7c77da..d35d30932b682 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json
@@ -113,7 +113,7 @@
     },
     {
         "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
-        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
         "MetricGroup": "TopdownL1;tma_L1_group",
         "MetricName": "tma_bad_speculation",
         "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
@@ -121,7 +121,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
-        "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
+        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
         "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
         "MetricName": "tma_branch_mispredicts",
         "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS",
@@ -145,7 +145,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
-        "MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB)) * tma_backend_bound",
+        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) * tma_backend_bound",
         "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
         "MetricName": "tma_memory_bound",
         "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@@ -177,7 +177,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
-        "MetricExpr": "(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
+        "MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
         "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
         "MetricName": "tma_lock_latency",
         "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS",
@@ -217,7 +217,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
-        "MetricExpr": "(MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
+        "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
         "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_l3_bound",
         "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
@@ -225,7 +225,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
-        "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / CLKS",
+        "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / CLKS",
         "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_contested_accesses",
         "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
@@ -233,7 +233,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
-        "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
+        "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
         "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_data_sharing",
         "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
@@ -241,7 +241,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
-        "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
+        "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
         "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_l3_hit_latency",
         "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
@@ -249,7 +249,7 @@
     },
     {
         "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
-        "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
+        "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
         "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_sq_full",
         "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
@@ -257,7 +257,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
-        "MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS))) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
+        "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
         "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_dram_bound",
         "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS",
@@ -289,20 +289,12 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
-        "MetricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES))) + (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
+        "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
         "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
         "MetricName": "tma_store_latency",
         "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
         "ScaleUnit": "100%"
     },
-    {
-        "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
-        "MetricExpr": "60 * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
-        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_false_sharing",
-        "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line.  Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
-        "ScaleUnit": "100%"
-    },
     {
         "BriefDescription": "This metric represents rate of split store accesses",
         "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / CORE_CLKS",
@@ -337,7 +329,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
-        "MetricExpr": "((CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS",
+        "MetricExpr": "((CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS",
         "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
         "MetricName": "tma_ports_utilization",
         "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@@ -345,7 +337,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@) / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else 0) / CORE_CLKS",
+        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) / CORE_CLKS)",
         "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
         "MetricName": "tma_ports_utilized_0",
         "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
@@ -353,7 +345,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS",
+        "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS)",
         "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
         "MetricName": "tma_ports_utilized_1",
         "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL",
@@ -361,7 +353,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
+        "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS)",
         "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
         "MetricName": "tma_ports_utilized_2",
         "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL",
@@ -369,7 +361,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
+        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
         "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
         "MetricName": "tma_ports_utilized_3m",
         "PublicDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3",
@@ -377,7 +369,7 @@
     },
     {
         "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
-        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / (4 * CORE_CLKS)",
+        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS",
         "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
         "MetricName": "tma_alu_op_utilization",
         "ScaleUnit": "100%"
@@ -433,7 +425,7 @@
     },
     {
         "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations Sample with: UOPS_DISPATCHED.PORT_7_8",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
+        "MetricExpr": "tma_port_4",
         "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
         "MetricName": "tma_store_op_utilization",
         "ScaleUnit": "100%"
@@ -526,7 +518,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
-        "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
         "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
         "MetricName": "tma_microcode_sequencer",
         "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS",
@@ -599,26 +591,26 @@
     },
     {
         "BriefDescription": "Floating Point Operations Per Cycle",
-        "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
         "MetricGroup": "Flops;Ret",
         "MetricName": "FLOPc"
     },
     {
         "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
-        "MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
         "MetricGroup": "Cor;Flops;HPC",
         "MetricName": "FP_Arith_Utilization",
         "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
     },
     {
         "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
         "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
         "MetricName": "ILP"
     },
     {
         "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
-        "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
+        "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
         "MetricGroup": "SMT",
         "MetricName": "CORE_CLKS"
     },
@@ -660,13 +652,13 @@
     },
     {
         "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
         "MetricGroup": "Flops;InsType",
         "MetricName": "IpFLOP"
     },
     {
         "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
         "MetricGroup": "Flops;InsType",
         "MetricName": "IpArith",
         "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
@@ -719,7 +711,7 @@
     },
     {
         "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
-        "MetricExpr": "IDQ.DSB_UOPS / ((IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS))",
+        "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
         "MetricGroup": "DSB;Fed;FetchBW",
         "MetricName": "DSB_Coverage"
     },
@@ -731,13 +723,13 @@
     },
     {
         "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
-        "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
+        "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
         "MetricGroup": "Bad;BrMispredicts",
         "MetricName": "Branch_Misprediction_Cost"
     },
     {
         "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
-        "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb)",
+        "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)",
         "MetricGroup": "Mem;MemoryBound;MemoryLat",
         "MetricName": "Load_Miss_Real_Latency"
     },
@@ -749,68 +741,68 @@
     },
     {
         "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L1MPKI"
     },
     {
         "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
         "MetricGroup": "Backend;CacheMisses;Mem",
         "MetricName": "L2MPKI"
     },
     {
         "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem;Offcore",
         "MetricName": "L2MPKI_All"
     },
     {
         "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L2MPKI_Load"
     },
     {
         "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
-        "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L2HPKI_All"
     },
     {
         "BriefDescription": "L2 cache hits per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L2HPKI_Load"
     },
     {
         "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L3MPKI"
     },
     {
         "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
         "MetricConstraint": "NO_NMI_WATCHDOG",
-        "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) if #core_wide < 1 else ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else CPU_CLK_UNHALTED.THREAD) )",
+        "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * (DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED)) / (2 * CORE_CLKS)",
         "MetricGroup": "Mem;MemoryTLB",
         "MetricName": "Page_Walks_Utilization"
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
-        "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
+        "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L1D_Cache_Fill_BW"
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
-        "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
+        "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L2_Cache_Fill_BW"
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
+        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L3_Cache_Fill_BW"
     },
@@ -840,19 +832,19 @@
     },
     {
         "BriefDescription": "Average CPU Utilization",
-        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
+        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
         "MetricGroup": "HPC;Summary",
         "MetricName": "CPU_Utilization"
     },
     {
         "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
-        "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
+        "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
         "MetricGroup": "Power;Summary",
         "MetricName": "Average_Frequency"
     },
     {
         "BriefDescription": "Giga Floating Point Operations Per Second",
-        "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1000000000) / duration_time",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time",
         "MetricGroup": "Cor;Flops;HPC",
         "MetricName": "GFLOPs",
         "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
@@ -865,7 +857,7 @@
     },
     {
         "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
-        "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
+        "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
         "MetricGroup": "SMT",
         "MetricName": "SMT_2T_Utilization"
     },
@@ -883,22 +875,10 @@
     },
     {
         "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
-        "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1000000 / duration_time / 1000",
+        "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1e6 / duration_time / 1e3",
         "MetricGroup": "HPC;Mem;MemoryBW;SoC",
         "MetricName": "DRAM_BW_Use"
     },
-    {
-        "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)",
-        "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
-        "MetricGroup": "Mem;SoC",
-        "MetricName": "MEM_Request_Latency"
-    },
-    {
-        "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests",
-        "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
-        "MetricGroup": "Mem;SoC",
-        "MetricName": "MEM_Parallel_Requests"
-    },
     {
         "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
         "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
@@ -907,44 +887,51 @@
     },
     {
         "BriefDescription": "C3 residency percent per core",
-        "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C3_Core_Residency"
+        "MetricName": "C3_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C6 residency percent per core",
-        "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C6_Core_Residency"
+        "MetricName": "C6_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C7 residency percent per core",
-        "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C7_Core_Residency"
+        "MetricName": "C7_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C2 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C2_Pkg_Residency"
+        "MetricName": "C2_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C3 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C3_Pkg_Residency"
+        "MetricName": "C3_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C6 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C6_Pkg_Residency"
+        "MetricName": "C6_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C7 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C7_Pkg_Residency"
+        "MetricName": "C7_Pkg_Residency",
+        "ScaleUnit": "100%"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/cache.json b/tools/perf/pmu-events/arch/x86/broadwellde/cache.json
index 4b77181b2c532..fcc99fd22b0ad 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/cache.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/cache.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "L1D data line replacements",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x51",
         "EventName": "L1D.REPLACEMENT",
         "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.FB_FULL",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "L1D miss oustandings duration in cycles",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING",
         "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Cycles with L1D load Misses outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -43,8 +35,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -53,8 +43,6 @@
     },
     {
         "BriefDescription": "Not rejected writebacks that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x27",
         "EventName": "L2_DEMAND_RQSTS.WB_HIT",
         "PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
@@ -63,8 +51,6 @@
     },
     {
         "BriefDescription": "L2 cache lines filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.ALL",
         "PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
@@ -73,8 +59,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in E state filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.E",
         "PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.",
@@ -83,8 +67,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in I state filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.I",
         "PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.",
@@ -93,8 +75,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in S state filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.S",
         "PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.",
@@ -103,8 +83,6 @@
     },
     {
         "BriefDescription": "Clean L2 cache lines evicted by demand.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
         "SampleAfterValue": "100003",
@@ -112,8 +90,6 @@
     },
     {
         "BriefDescription": "L2 code requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_CODE_RD",
         "PublicDescription": "This event counts the total number of L2 code requests.",
@@ -122,8 +98,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
         "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
@@ -132,8 +106,6 @@
     },
     {
         "BriefDescription": "Demand requests that miss L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
         "SampleAfterValue": "200003",
@@ -141,8 +113,6 @@
     },
     {
         "BriefDescription": "Demand requests to L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
         "SampleAfterValue": "200003",
@@ -150,8 +120,6 @@
     },
     {
         "BriefDescription": "Requests from L2 hardware prefetchers",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_PF",
         "PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.",
@@ -160,8 +128,6 @@
     },
     {
         "BriefDescription": "RFO requests to L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_RFO",
         "PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
@@ -170,8 +136,6 @@
     },
     {
         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_HIT",
         "SampleAfterValue": "200003",
@@ -179,8 +143,6 @@
     },
     {
         "BriefDescription": "L2 cache misses when fetching instructions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_MISS",
         "SampleAfterValue": "200003",
@@ -188,8 +150,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
         "PublicDescription": "This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted.",
@@ -198,8 +158,6 @@
     },
     {
         "BriefDescription": "Demand Data Read miss L2, no rejects",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
         "PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
@@ -208,8 +166,6 @@
     },
     {
         "BriefDescription": "L2 prefetch requests that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.L2_PF_HIT",
         "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.",
@@ -218,8 +174,6 @@
     },
     {
         "BriefDescription": "L2 prefetch requests that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.L2_PF_MISS",
         "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.",
@@ -228,8 +182,6 @@
     },
     {
         "BriefDescription": "All requests that miss L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.MISS",
         "SampleAfterValue": "200003",
@@ -237,8 +189,6 @@
     },
     {
         "BriefDescription": "All L2 requests.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.REFERENCES",
         "SampleAfterValue": "200003",
@@ -246,8 +196,6 @@
     },
     {
         "BriefDescription": "RFO requests that hit L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_HIT",
         "SampleAfterValue": "200003",
@@ -255,8 +203,6 @@
     },
     {
         "BriefDescription": "RFO requests that miss L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_MISS",
         "SampleAfterValue": "200003",
@@ -264,8 +210,6 @@
     },
     {
         "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.ALL_PF",
         "PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects.",
@@ -274,8 +218,6 @@
     },
     {
         "BriefDescription": "Transactions accessing L2 pipe",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.ALL_REQUESTS",
         "PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.",
@@ -284,8 +226,6 @@
     },
     {
         "BriefDescription": "L2 cache accesses when fetching instructions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.CODE_RD",
         "PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.",
@@ -294,8 +234,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.DEMAND_DATA_RD",
         "PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.",
@@ -304,8 +242,6 @@
     },
     {
         "BriefDescription": "L1D writebacks that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L1D_WB",
         "PublicDescription": "This event counts L1D writebacks that access L2 cache.",
@@ -314,8 +250,6 @@
     },
     {
         "BriefDescription": "L2 fill requests that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L2_FILL",
         "PublicDescription": "This event counts L2 fill requests that access L2 cache.",
@@ -324,8 +258,6 @@
     },
     {
         "BriefDescription": "L2 writebacks that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L2_WB",
         "PublicDescription": "This event counts L2 writebacks that access L2 cache.",
@@ -334,8 +266,6 @@
     },
     {
         "BriefDescription": "RFO requests that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.RFO",
         "PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.",
@@ -344,8 +274,6 @@
     },
     {
         "BriefDescription": "Cycles when L1D is locked",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x63",
         "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
         "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",
@@ -354,8 +282,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests missed L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.MISS",
         "PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
@@ -364,8 +290,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
         "PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
@@ -374,8 +298,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM100",
         "EventCode": "0xD2",
@@ -387,8 +309,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM100",
         "EventCode": "0xD2",
@@ -400,8 +320,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM100",
         "EventCode": "0xD2",
@@ -413,8 +331,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM100",
         "EventCode": "0xD2",
@@ -425,8 +341,6 @@
         "UMask": "0x8"
     },
     {
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDE70, BDM100",
         "EventCode": "0xD3",
@@ -438,8 +352,6 @@
     },
     {
         "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDE70",
         "EventCode": "0xD3",
@@ -450,8 +362,6 @@
     },
     {
         "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache (Precise Event)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDE70",
         "EventCode": "0xD3",
@@ -462,8 +372,6 @@
     },
     {
         "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM (Precise Event)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDE70",
         "EventCode": "0xD3",
@@ -474,8 +382,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
@@ -486,8 +392,6 @@
     },
     {
         "BriefDescription": "Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
@@ -498,8 +402,6 @@
     },
     {
         "BriefDescription": "Retired load uops misses in L1 cache as data sources. Uses PEBS.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
@@ -510,8 +412,6 @@
     },
     {
         "BriefDescription": "Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM35",
         "EventCode": "0xD1",
@@ -523,8 +423,6 @@
     },
     {
         "BriefDescription": "Retired load uops with L2 cache misses as data sources. Uses PEBS.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
@@ -535,8 +433,6 @@
     },
     {
         "BriefDescription": "Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM100",
         "EventCode": "0xD1",
@@ -548,8 +444,6 @@
     },
     {
         "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM100, BDE70",
         "EventCode": "0xD1",
@@ -560,8 +454,6 @@
     },
     {
         "BriefDescription": "All retired load uops. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
@@ -572,12 +464,9 @@
     },
     {
         "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement.",
         "SampleAfterValue": "2000003",
@@ -585,8 +474,6 @@
     },
     {
         "BriefDescription": "Retired load uops with locked access. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM35",
         "EventCode": "0xD0",
@@ -598,8 +485,6 @@
     },
     {
         "BriefDescription": "Retired load uops that split across a cacheline boundary.(Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
@@ -610,12 +495,9 @@
     },
     {
         "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
         "SampleAfterValue": "100003",
@@ -623,8 +505,6 @@
     },
     {
         "BriefDescription": "Retired load uops that miss the STLB. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
@@ -635,12 +515,9 @@
     },
     {
         "BriefDescription": "Retired store uops that miss the STLB. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",
         "SampleAfterValue": "100003",
@@ -648,8 +525,6 @@
     },
     {
         "BriefDescription": "Demand and prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
         "PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
@@ -658,8 +533,6 @@
     },
     {
         "BriefDescription": "Cacheable and noncachaeble code read requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
         "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.",
@@ -668,8 +541,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests sent to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
         "PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
@@ -678,8 +549,6 @@
     },
     {
         "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
         "PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
@@ -688,8 +557,6 @@
     },
     {
         "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb2",
         "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
         "PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.",
@@ -698,8 +565,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM76",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
@@ -709,8 +574,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "Errata": "BDM76",
         "EventCode": "0x60",
@@ -721,8 +584,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "Errata": "BDM76",
         "EventCode": "0x60",
@@ -733,8 +594,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "Errata": "BDM76",
         "EventCode": "0x60",
@@ -745,8 +604,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM76",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
@@ -756,8 +613,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM76",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
@@ -767,8 +622,6 @@
     },
     {
         "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "6",
         "Errata": "BDM76",
         "EventCode": "0x60",
@@ -778,8 +631,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM76",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
@@ -789,8 +640,6 @@
     },
     {
         "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE",
         "SampleAfterValue": "100003",
@@ -798,8 +647,6 @@
     },
     {
         "BriefDescription": "Split locks in SQ",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xf4",
         "EventName": "SQ_MISC.SPLIT_LOCK",
         "PublicDescription": "This event counts the number of split locks in the super queue.",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json b/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json
index 46cf184901401..0b3f026158e29 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
         "SampleAfterValue": "2000003",
@@ -10,8 +8,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
         "SampleAfterValue": "2000003",
@@ -19,8 +15,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
         "SampleAfterValue": "2000003",
@@ -28,8 +22,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
         "SampleAfterValue": "2000003",
@@ -37,8 +29,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  ?.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
         "SampleAfterValue": "2000006",
@@ -46,8 +36,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.PACKED",
         "SampleAfterValue": "2000004",
@@ -55,8 +43,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.SCALAR",
         "SampleAfterValue": "2000003",
@@ -64,8 +50,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
         "SampleAfterValue": "2000003",
@@ -73,8 +57,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
         "SampleAfterValue": "2000003",
@@ -82,8 +64,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.SINGLE",
         "SampleAfterValue": "2000005",
@@ -91,8 +71,6 @@
     },
     {
         "BriefDescription": "Cycles with any input/output SSE or FP assist",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.ANY",
@@ -102,8 +80,6 @@
     },
     {
         "BriefDescription": "Number of SIMD FP assists due to input values",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.SIMD_INPUT",
         "PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",
@@ -112,8 +88,6 @@
     },
     {
         "BriefDescription": "Number of SIMD FP assists due to Output values",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.SIMD_OUTPUT",
         "PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
@@ -122,8 +96,6 @@
     },
     {
         "BriefDescription": "Number of X87 assists due to input value.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.X87_INPUT",
         "PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
@@ -132,8 +104,6 @@
     },
     {
         "BriefDescription": "Number of X87 assists due to output value.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.X87_OUTPUT",
         "PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
@@ -142,8 +112,6 @@
     },
     {
         "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
         "SampleAfterValue": "1000003",
@@ -151,8 +119,6 @@
     },
     {
         "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
         "SampleAfterValue": "1000003",
@@ -160,8 +126,6 @@
     },
     {
         "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM30",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.AVX_TO_SSE",
@@ -171,8 +135,6 @@
     },
     {
         "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM30",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.SSE_TO_AVX",
@@ -182,8 +144,6 @@
     },
     {
         "BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xA0",
         "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF",
         "PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file.  The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*.  See the Broadwell Optimization Guide for more information.",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json b/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json
index 37ce8034b2ed4..d0f6678609ae6 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xe6",
         "EventName": "BACLEARS.ANY",
         "SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
     },
     {
         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAB",
         "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
         "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
@@ -20,8 +16,6 @@
     },
     {
         "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.HIT",
         "PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.",
@@ -30,8 +24,6 @@
     },
     {
         "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.IFDATA_STALL",
         "PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).",
@@ -40,8 +32,6 @@
     },
     {
         "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.MISSES",
         "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
@@ -50,8 +40,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -61,8 +49,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -72,8 +58,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering 4 Uops",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -83,8 +67,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering any Uop",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -94,8 +76,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_CYCLES",
@@ -105,8 +85,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_UOPS",
         "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
@@ -115,8 +93,6 @@
     },
     {
         "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0x79",
         "EventName": "IDQ.EMPTY",
         "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end.  It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",
@@ -125,8 +101,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_ALL_UOPS",
         "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@@ -135,8 +109,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_CYCLES",
@@ -146,8 +118,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_UOPS",
         "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@@ -156,8 +126,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_CYCLES",
@@ -167,8 +135,6 @@
     },
     {
         "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_DSB_CYCLES",
@@ -178,8 +144,6 @@
     },
     {
         "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
@@ -190,8 +154,6 @@
     },
     {
         "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_DSB_UOPS",
         "PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
@@ -200,8 +162,6 @@
     },
     {
         "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_MITE_UOPS",
         "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.",
@@ -210,8 +170,6 @@
     },
     {
         "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
@@ -221,8 +179,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_UOPS",
         "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
@@ -231,8 +187,6 @@
     },
     {
         "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
         "PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4  x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.",
@@ -241,8 +195,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -252,8 +204,6 @@
     },
     {
         "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@@ -263,8 +213,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "3",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@@ -274,8 +222,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@@ -284,8 +230,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/memory.json b/tools/perf/pmu-events/arch/x86/broadwellde/memory.json
index a3a5cc6dab420..12cc384d7f18c 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/memory.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Number of times HLE abort was triggered (PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED",
         "PEBS": "1",
@@ -12,8 +10,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC1",
         "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
@@ -22,8 +18,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC2",
         "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.",
@@ -32,8 +26,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC3",
         "PublicDescription": "Number of times a disallowed operation caused an HLE abort.",
@@ -42,8 +34,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC4",
         "PublicDescription": "Number of times HLE caused a fault.",
@@ -52,8 +42,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC5",
         "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.",
@@ -62,8 +50,6 @@
     },
     {
         "BriefDescription": "Number of times HLE commit succeeded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.COMMIT",
         "PublicDescription": "Number of times HLE commit succeeded.",
@@ -72,8 +58,6 @@
     },
     {
         "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.START",
         "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.",
@@ -82,8 +66,6 @@
     },
     {
         "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
         "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",
@@ -92,8 +74,6 @@
     },
     {
         "BriefDescription": "Loads with latency value being above 128",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
@@ -102,13 +82,10 @@
         "PEBS": "2",
         "PublicDescription": "This event counts loads with latency value being above 128.",
         "SampleAfterValue": "1009",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 16",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
@@ -117,13 +94,10 @@
         "PEBS": "2",
         "PublicDescription": "This event counts loads with latency value being above 16.",
         "SampleAfterValue": "20011",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 256",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
@@ -132,13 +106,10 @@
         "PEBS": "2",
         "PublicDescription": "This event counts loads with latency value being above 256.",
         "SampleAfterValue": "503",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 32",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
@@ -147,13 +118,10 @@
         "PEBS": "2",
         "PublicDescription": "This event counts loads with latency value being above 32.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 4",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
@@ -162,13 +130,10 @@
         "PEBS": "2",
         "PublicDescription": "This event counts loads with latency value being above four.",
         "SampleAfterValue": "100003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 512",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
@@ -177,13 +142,10 @@
         "PEBS": "2",
         "PublicDescription": "This event counts loads with latency value being above 512.",
         "SampleAfterValue": "101",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 64",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
@@ -192,13 +154,10 @@
         "PEBS": "2",
         "PublicDescription": "This event counts loads with latency value being above 64.",
         "SampleAfterValue": "2003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 8",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
@@ -207,13 +166,10 @@
         "PEBS": "2",
         "PublicDescription": "This event counts loads with latency value being above eight.",
         "SampleAfterValue": "50021",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x05",
         "EventName": "MISALIGN_MEM_REF.LOADS",
         "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",
@@ -222,8 +178,6 @@
     },
     {
         "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x05",
         "EventName": "MISALIGN_MEM_REF.STORES",
         "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",
@@ -232,8 +186,6 @@
     },
     {
         "BriefDescription": "Number of times RTM abort was triggered (PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED",
         "PEBS": "1",
@@ -243,8 +195,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC1",
         "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
@@ -253,8 +203,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC2",
         "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.",
@@ -263,8 +211,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC3",
         "PublicDescription": "Number of times a disallowed operation caused an RTM abort.",
@@ -273,8 +219,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC4",
         "PublicDescription": "Number of times a RTM caused a fault.",
@@ -283,8 +227,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC5",
         "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.",
@@ -293,8 +235,6 @@
     },
     {
         "BriefDescription": "Number of times RTM commit succeeded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.COMMIT",
         "PublicDescription": "Number of times RTM commit succeeded.",
@@ -303,8 +243,6 @@
     },
     {
         "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.START",
         "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.",
@@ -313,8 +251,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC1",
         "SampleAfterValue": "2000003",
@@ -322,8 +258,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC2",
         "PublicDescription": "Unfriendly TSX abort triggered by  a vzeroupper instruction.",
@@ -332,8 +266,6 @@
     },
     {
         "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC3",
         "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
@@ -342,8 +274,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC4",
         "PublicDescription": "RTM region detected inside HLE.",
@@ -352,8 +282,6 @@
     },
     {
         "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC5",
         "SampleAfterValue": "2000003",
@@ -361,8 +289,6 @@
     },
     {
         "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
         "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.",
@@ -371,8 +297,6 @@
     },
     {
         "BriefDescription": "Number of times a TSX line had a cache conflict",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CONFLICT",
         "PublicDescription": "Number of times a TSX line had a cache conflict.",
@@ -381,8 +305,6 @@
     },
     {
         "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
         "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
@@ -391,8 +313,6 @@
     },
     {
         "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
         "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
@@ -401,8 +321,6 @@
     },
     {
         "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
         "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
@@ -411,8 +329,6 @@
     },
     {
         "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
         "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
@@ -421,8 +337,6 @@
     },
     {
         "BriefDescription": "Number of times we could not allocate Lock Buffer",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
         "PublicDescription": "Number of times we could not allocate Lock Buffer.",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/other.json b/tools/perf/pmu-events/arch/x86/broadwellde/other.json
index 917d145d52273..1c2a5b0019496 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/other.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/other.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5C",
         "EventName": "CPL_CYCLES.RING0",
         "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5C",
@@ -23,8 +19,6 @@
     },
     {
         "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5C",
         "EventName": "CPL_CYCLES.RING123",
         "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
@@ -33,8 +27,6 @@
     },
     {
         "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x63",
         "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
         "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json b/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json
index 85654037b768c..9e7d66b07f016 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Cycles when divider is busy executing divide operations",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x14",
         "EventName": "ARITH.FPU_DIV_ACTIVE",
         "PublicDescription": "This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Speculative and retired  branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_BRANCHES",
         "PublicDescription": "This event counts both taken and not taken speculative and retired branch instructions.",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Speculative and retired macro-conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
         "PublicDescription": "This event counts both taken and not taken speculative and retired macro-conditional branch instructions.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
         "PublicDescription": "This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.",
@@ -41,8 +33,6 @@
     },
     {
         "BriefDescription": "Speculative and retired direct near calls",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
         "PublicDescription": "This event counts both taken and not taken speculative and retired direct near calls.",
@@ -51,8 +41,6 @@
     },
     {
         "BriefDescription": "Speculative and retired indirect branches excluding calls and returns",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
         "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.",
@@ -61,8 +49,6 @@
     },
     {
         "BriefDescription": "Speculative and retired indirect return branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
         "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.",
@@ -71,8 +57,6 @@
     },
     {
         "BriefDescription": "Not taken macro-conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
         "PublicDescription": "This event counts not taken macro-conditional branch instructions.",
@@ -81,8 +65,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired macro-conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
         "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions.",
@@ -91,8 +73,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
         "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.",
@@ -101,8 +81,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired direct near calls",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
         "PublicDescription": "This event counts taken speculative and retired direct near calls.",
@@ -111,8 +89,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
         "PublicDescription": "This event counts taken speculative and retired indirect branches excluding calls and return branches.",
@@ -121,8 +97,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect calls",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
         "PublicDescription": "This event counts taken speculative and retired indirect calls including both register and memory indirect.",
@@ -131,8 +105,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
         "PublicDescription": "This event counts taken speculative and retired indirect branches that have a return mnemonic.",
@@ -141,8 +113,6 @@
     },
     {
         "BriefDescription": "All (macro) branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "PublicDescription": "This event counts all (macro) branch instructions retired.",
@@ -150,8 +120,6 @@
     },
     {
         "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDW98",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
@@ -162,8 +130,6 @@
     },
     {
         "BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -173,8 +139,6 @@
     },
     {
         "BriefDescription": "Far branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDW98",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.FAR_BRANCH",
@@ -184,8 +148,6 @@
     },
     {
         "BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -195,8 +157,6 @@
     },
     {
         "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
         "PEBS": "1",
@@ -206,8 +166,6 @@
     },
     {
         "BriefDescription": "Return instructions retired. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_RETURN",
         "PEBS": "1",
@@ -217,8 +175,6 @@
     },
     {
         "BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
@@ -228,8 +184,6 @@
     },
     {
         "BriefDescription": "Not taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NOT_TAKEN",
         "PublicDescription": "This event counts not taken branch instructions retired.",
@@ -238,8 +192,6 @@
     },
     {
         "BriefDescription": "Speculative and retired mispredicted macro conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_BRANCHES",
         "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.",
@@ -248,8 +200,6 @@
     },
     {
         "BriefDescription": "Speculative and retired mispredicted macro conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
         "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.",
@@ -258,8 +208,6 @@
     },
     {
         "BriefDescription": "Mispredicted indirect branches excluding calls and returns",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
         "PublicDescription": "This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.",
@@ -268,8 +216,6 @@
     },
     {
         "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
         "PublicDescription": "This event counts not taken speculative and retired mispredicted macro conditional branch instructions.",
@@ -278,8 +224,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
         "PublicDescription": "This event counts taken speculative and retired mispredicted macro conditional branch instructions.",
@@ -288,8 +232,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
         "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.",
@@ -298,8 +240,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect calls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
         "SampleAfterValue": "200003",
@@ -307,8 +247,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
         "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.",
@@ -317,8 +255,6 @@
     },
     {
         "BriefDescription": "All mispredicted macro branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PublicDescription": "This event counts all mispredicted macro branch instructions retired.",
@@ -326,8 +262,6 @@
     },
     {
         "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
         "PEBS": "2",
@@ -337,8 +271,6 @@
     },
     {
         "BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -348,8 +280,6 @@
     },
     {
         "BriefDescription": "number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
@@ -359,8 +289,6 @@
     },
     {
         "BriefDescription": "This event counts the number of mispredicted ret instructions retired.(Precise Event)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.RET",
         "PEBS": "1",
@@ -370,8 +298,6 @@
     },
     {
         "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "2000003",
@@ -379,8 +305,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
         "PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.",
@@ -390,8 +314,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
         "SampleAfterValue": "2000003",
@@ -399,8 +321,6 @@
     },
     {
         "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "2000003",
@@ -408,8 +328,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the core is not in halt state.",
-        "Counter": "Fixed counter 2",
-        "CounterHTOff": "Fixed counter 2",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
         "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
         "SampleAfterValue": "2000003",
@@ -417,8 +335,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
         "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
@@ -428,8 +344,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
         "SampleAfterValue": "2000003",
@@ -437,8 +351,6 @@
     },
     {
         "BriefDescription": "Core cycles when the thread is not in halt state",
-        "Counter": "Fixed counter 1",
-        "CounterHTOff": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD",
         "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
         "SampleAfterValue": "2000003",
@@ -447,16 +359,12 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
-        "Counter": "Fixed counter 1",
-        "CounterHTOff": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Thread cycles when thread is not in halt state",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
         "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
@@ -465,16 +373,12 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "8",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
@@ -483,8 +387,6 @@
     },
     {
         "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "8",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
@@ -494,8 +396,6 @@
     },
     {
         "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
@@ -504,8 +404,6 @@
     },
     {
         "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
@@ -515,8 +413,6 @@
     },
     {
         "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
@@ -526,8 +422,6 @@
     },
     {
         "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
@@ -536,8 +430,6 @@
     },
     {
         "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
@@ -547,8 +439,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "12",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
@@ -557,8 +447,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "12",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
@@ -568,8 +456,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "5",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
@@ -578,8 +464,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "5",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
@@ -589,8 +473,6 @@
     },
     {
         "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "6",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",
@@ -600,8 +482,6 @@
     },
     {
         "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "6",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
@@ -610,8 +490,6 @@
     },
     {
         "BriefDescription": "Total execution stalls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
@@ -620,8 +498,6 @@
     },
     {
         "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.LCP",
         "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.",
@@ -630,8 +506,6 @@
     },
     {
         "BriefDescription": "Instructions retired from execution.",
-        "Counter": "Fixed counter 0",
-        "CounterHTOff": "Fixed counter 0",
         "EventName": "INST_RETIRED.ANY",
         "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
         "SampleAfterValue": "2000003",
@@ -639,8 +513,6 @@
     },
     {
         "BriefDescription": "Number of instructions retired. General Counter   - architectural event",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM61",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.ANY_P",
@@ -649,8 +521,6 @@
     },
     {
         "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
-        "Counter": "1",
-        "CounterHTOff": "1",
         "Errata": "BDM11, BDM55",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.PREC_DIST",
@@ -661,8 +531,6 @@
     },
     {
         "BriefDescription": "FP operations  retired. X87 FP operations that have no exceptions:",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.X87",
         "PublicDescription": "This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.",
@@ -671,8 +539,6 @@
     },
     {
         "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RAT_STALL_CYCLES",
         "PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.",
@@ -681,8 +547,6 @@
     },
     {
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES",
@@ -693,8 +557,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
@@ -703,8 +565,6 @@
     },
     {
         "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.NO_SR",
         "SampleAfterValue": "100003",
@@ -712,8 +572,6 @@
     },
     {
         "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.STORE_FORWARD",
         "PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.",
@@ -722,8 +580,6 @@
     },
     {
         "BriefDescription": "False dependencies in MOB due to partial compare",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x07",
         "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
         "PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",
@@ -732,8 +588,6 @@
     },
     {
         "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4C",
         "EventName": "LOAD_HIT_PRE.HW_PF",
         "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.",
@@ -742,8 +596,6 @@
     },
     {
         "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4c",
         "EventName": "LOAD_HIT_PRE.SW_PF",
         "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.",
@@ -752,8 +604,6 @@
     },
     {
         "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_4_UOPS",
@@ -762,8 +612,6 @@
     },
     {
         "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_ACTIVE",
@@ -772,8 +620,6 @@
     },
     {
         "BriefDescription": "Number of Uops delivered by the LSD.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA8",
         "EventName": "LSD.UOPS",
         "SampleAfterValue": "2000003",
@@ -781,8 +627,6 @@
     },
     {
         "BriefDescription": "Number of machine clears (nukes) of any type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xC3",
@@ -792,8 +636,6 @@
     },
     {
         "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.CYCLES",
         "PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.",
@@ -802,8 +644,6 @@
     },
     {
         "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MASKMOV",
         "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",
@@ -812,8 +652,6 @@
     },
     {
         "BriefDescription": "Self-modifying code (SMC) detected.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.SMC",
         "PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.",
@@ -822,8 +660,6 @@
     },
     {
         "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.INT_ELIMINATED",
         "SampleAfterValue": "1000003",
@@ -831,8 +667,6 @@
     },
     {
         "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",
         "SampleAfterValue": "1000003",
@@ -840,8 +674,6 @@
     },
     {
         "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",
         "SampleAfterValue": "100003",
@@ -849,8 +681,6 @@
     },
     {
         "BriefDescription": "Resource-related stall cycles",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ANY",
         "PublicDescription": "This event counts resource-related stall cycles. Reasons for stalls can be as follows:\n - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots)\n - *any* u-arch structure got empty (like INT/SIMD FreeLists)\n - FPU control word (FPCW), MXCSR\nand others. This counts cycles that the pipeline backend blocked uop delivery from the front end.",
@@ -859,8 +689,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to re-order buffer full.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ROB",
         "PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.",
@@ -869,8 +697,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no eligible RS entry available.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.RS",
         "PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
@@ -879,8 +705,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.SB",
         "PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
@@ -889,8 +713,6 @@
     },
     {
         "BriefDescription": "Count cases of saving new LBR",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCC",
         "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
         "PublicDescription": "This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.",
@@ -899,8 +721,6 @@
     },
     {
         "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5E",
         "EventName": "RS_EVENTS.EMPTY_CYCLES",
         "PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
@@ -909,8 +729,6 @@
     },
     {
         "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5E",
@@ -921,8 +739,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_0",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
@@ -931,8 +747,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 1",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_1",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
@@ -941,8 +755,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_2",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
@@ -951,8 +763,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_3",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
@@ -961,8 +771,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 4",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_4",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
@@ -971,8 +779,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 5",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_5",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
@@ -981,8 +787,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 6",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_6",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
@@ -991,8 +795,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 7",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_7",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
@@ -1001,8 +803,6 @@
     },
     {
         "BriefDescription": "Number of uops executed on the core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE",
         "PublicDescription": "Number of uops executed from any thread.",
@@ -1011,8 +811,6 @@
     },
     {
         "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@@ -1021,8 +819,6 @@
     },
     {
         "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@@ -1031,8 +827,6 @@
     },
     {
         "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@@ -1041,8 +835,6 @@
     },
     {
         "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@@ -1051,8 +843,6 @@
     },
     {
         "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
         "Invert": "1",
@@ -1061,8 +851,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 1 uop was executed per-thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
@@ -1071,8 +859,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 2 uops were executed per-thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
@@ -1081,8 +867,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 3 uops were executed per-thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
@@ -1091,8 +875,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 4 uops were executed per-thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
@@ -1101,8 +883,6 @@
     },
     {
         "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.STALL_CYCLES",
@@ -1113,8 +893,6 @@
     },
     {
         "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.THREAD",
         "PublicDescription": "Number of uops to be executed per-thread each cycle.",
@@ -1123,8 +901,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_0",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
@@ -1134,8 +910,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are exectuted in port 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE",
         "SampleAfterValue": "2000003",
@@ -1143,8 +917,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 1",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_1",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
@@ -1154,8 +926,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are exectuted in port 1.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE",
         "SampleAfterValue": "2000003",
@@ -1163,8 +933,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_2",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
@@ -1174,8 +942,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE",
         "SampleAfterValue": "2000003",
@@ -1183,8 +949,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_3",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
@@ -1194,8 +958,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE",
         "SampleAfterValue": "2000003",
@@ -1203,8 +965,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 4",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_4",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
@@ -1214,8 +974,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are exectuted in port 4.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE",
         "SampleAfterValue": "2000003",
@@ -1223,8 +981,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 5",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_5",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
@@ -1234,8 +990,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are exectuted in port 5.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE",
         "SampleAfterValue": "2000003",
@@ -1243,8 +997,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 6",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_6",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
@@ -1254,8 +1006,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are exectuted in port 6.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE",
         "SampleAfterValue": "2000003",
@@ -1263,8 +1013,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 7",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_7",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
@@ -1274,8 +1022,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 7.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE",
         "SampleAfterValue": "2000003",
@@ -1283,8 +1029,6 @@
     },
     {
         "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.ANY",
         "PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).",
@@ -1293,8 +1037,6 @@
     },
     {
         "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.FLAGS_MERGE",
         "PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.",
@@ -1303,8 +1045,6 @@
     },
     {
         "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.SINGLE_MUL",
         "SampleAfterValue": "2000003",
@@ -1312,8 +1052,6 @@
     },
     {
         "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.SLOW_LEA",
         "SampleAfterValue": "2000003",
@@ -1321,8 +1059,6 @@
     },
     {
         "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -1333,8 +1069,6 @@
     },
     {
         "BriefDescription": "Actually retired uops. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ALL",
@@ -1345,8 +1079,6 @@
     },
     {
         "BriefDescription": "Retirement slots used. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
         "PEBS": "1",
@@ -1356,8 +1088,6 @@
     },
     {
         "BriefDescription": "Cycles without actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -1368,8 +1098,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 10 actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "10",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json
index c4d154944ab63..b8c9845308b25 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Bounce Control",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_C_BOUNCE_CONTROL",
         "PerPkg": "1",
@@ -9,14 +8,12 @@
     },
     {
         "BriefDescription": "Uncore Clocks",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_C_CLOCKTICKS",
         "PerPkg": "1",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Counter 0 Occupancy",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1F",
         "EventName": "UNC_C_COUNTER0_OCCUPANCY",
         "PerPkg": "1",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "FaST wire asserted",
-        "Counter": "0,1",
         "EventCode": "0x9",
         "EventName": "UNC_C_FAST_ASSERTED",
         "PerPkg": "1",
@@ -34,7 +30,6 @@
     },
     {
         "BriefDescription": "Cache Lookups; Any Request",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "UNC_C_LLC_LOOKUP.ANY",
         "PerPkg": "1",
@@ -44,7 +39,6 @@
     },
     {
         "BriefDescription": "Cache Lookups; Data Read Request",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
         "PerPkg": "1",
@@ -54,7 +48,6 @@
     },
     {
         "BriefDescription": "Cache Lookups; Lookups that Match NID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "UNC_C_LLC_LOOKUP.NID",
         "PerPkg": "1",
@@ -64,7 +57,6 @@
     },
     {
         "BriefDescription": "Cache Lookups; Any Read Request",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "UNC_C_LLC_LOOKUP.READ",
         "PerPkg": "1",
@@ -74,7 +66,6 @@
     },
     {
         "BriefDescription": "Cache Lookups; External Snoop Request",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
         "PerPkg": "1",
@@ -84,7 +75,6 @@
     },
     {
         "BriefDescription": "Cache Lookups; Write Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "UNC_C_LLC_LOOKUP.WRITE",
         "PerPkg": "1",
@@ -94,7 +84,6 @@
     },
     {
         "BriefDescription": "Lines Victimized; Lines in E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x37",
         "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
         "PerPkg": "1",
@@ -104,7 +93,6 @@
     },
     {
         "BriefDescription": "Lines Victimized",
-        "Counter": "0,1,2,3",
         "EventCode": "0x37",
         "EventName": "UNC_C_LLC_VICTIMS.F_STATE",
         "PerPkg": "1",
@@ -114,7 +102,6 @@
     },
     {
         "BriefDescription": "Lines Victimized; Lines in S State",
-        "Counter": "0,1,2,3",
         "EventCode": "0x37",
         "EventName": "UNC_C_LLC_VICTIMS.I_STATE",
         "PerPkg": "1",
@@ -124,7 +111,6 @@
     },
     {
         "BriefDescription": "Lines Victimized",
-        "Counter": "0,1,2,3",
         "EventCode": "0x37",
         "EventName": "UNC_C_LLC_VICTIMS.MISS",
         "PerPkg": "1",
@@ -134,7 +120,6 @@
     },
     {
         "BriefDescription": "Lines Victimized; Lines in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x37",
         "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
         "PerPkg": "1",
@@ -144,7 +129,6 @@
     },
     {
         "BriefDescription": "Lines Victimized; Victimized Lines that Match NID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x37",
         "EventName": "UNC_C_LLC_VICTIMS.NID",
         "PerPkg": "1",
@@ -154,7 +138,6 @@
     },
     {
         "BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_C_MISC.CVZERO_PREFETCH_MISS",
         "PerPkg": "1",
@@ -164,7 +147,6 @@
     },
     {
         "BriefDescription": "Cbo Misc; Clean Victim with raw CV=0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_C_MISC.CVZERO_PREFETCH_VICTIM",
         "PerPkg": "1",
@@ -174,7 +156,6 @@
     },
     {
         "BriefDescription": "Cbo Misc; RFO HitS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_C_MISC.RFO_HIT_S",
         "PerPkg": "1",
@@ -184,7 +165,6 @@
     },
     {
         "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_C_MISC.RSPI_WAS_FSE",
         "PerPkg": "1",
@@ -194,7 +174,6 @@
     },
     {
         "BriefDescription": "Cbo Misc",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_C_MISC.STARTED",
         "PerPkg": "1",
@@ -204,7 +183,6 @@
     },
     {
         "BriefDescription": "Cbo Misc; Write Combining Aliasing",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_C_MISC.WC_ALIASING",
         "PerPkg": "1",
@@ -214,7 +192,6 @@
     },
     {
         "BriefDescription": "LRU Queue; LRU Age 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "UNC_C_QLRU.AGE0",
         "PerPkg": "1",
@@ -224,7 +201,6 @@
     },
     {
         "BriefDescription": "LRU Queue; LRU Age 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "UNC_C_QLRU.AGE1",
         "PerPkg": "1",
@@ -234,7 +210,6 @@
     },
     {
         "BriefDescription": "LRU Queue; LRU Age 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "UNC_C_QLRU.AGE2",
         "PerPkg": "1",
@@ -244,7 +219,6 @@
     },
     {
         "BriefDescription": "LRU Queue; LRU Age 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "UNC_C_QLRU.AGE3",
         "PerPkg": "1",
@@ -254,7 +228,6 @@
     },
     {
         "BriefDescription": "LRU Queue; LRU Bits Decremented",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "UNC_C_QLRU.LRU_DECREMENT",
         "PerPkg": "1",
@@ -264,7 +237,6 @@
     },
     {
         "BriefDescription": "LRU Queue; Non-0 Aged Victim",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "UNC_C_QLRU.VICTIM_NON_ZERO",
         "PerPkg": "1",
@@ -274,27 +246,24 @@
     },
     {
         "BriefDescription": "AD Ring In Use; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_C_RING_AD_USED.ALL",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "AD Ring In Use; Down",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_C_RING_AD_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "AD Ring In Use; Up",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_C_RING_AD_USED.CW",
         "PerPkg": "1",
@@ -304,7 +273,6 @@
     },
     {
         "BriefDescription": "AD Ring In Use; Down and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_C_RING_AD_USED.DOWN_EVEN",
         "PerPkg": "1",
@@ -314,7 +282,6 @@
     },
     {
         "BriefDescription": "AD Ring In Use; Down and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_C_RING_AD_USED.DOWN_ODD",
         "PerPkg": "1",
@@ -324,7 +291,6 @@
     },
     {
         "BriefDescription": "AD Ring In Use; Up and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_C_RING_AD_USED.UP_EVEN",
         "PerPkg": "1",
@@ -334,7 +300,6 @@
     },
     {
         "BriefDescription": "AD Ring In Use; Up and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_C_RING_AD_USED.UP_ODD",
         "PerPkg": "1",
@@ -344,27 +309,24 @@
     },
     {
         "BriefDescription": "AK Ring In Use; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_C_RING_AK_USED.ALL",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "AK Ring In Use; Down",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_C_RING_AK_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "AK Ring In Use; Up",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_C_RING_AK_USED.CW",
         "PerPkg": "1",
@@ -374,7 +336,6 @@
     },
     {
         "BriefDescription": "AK Ring In Use; Down and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_C_RING_AK_USED.DOWN_EVEN",
         "PerPkg": "1",
@@ -384,7 +345,6 @@
     },
     {
         "BriefDescription": "AK Ring In Use; Down and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_C_RING_AK_USED.DOWN_ODD",
         "PerPkg": "1",
@@ -394,7 +354,6 @@
     },
     {
         "BriefDescription": "AK Ring In Use; Up and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_C_RING_AK_USED.UP_EVEN",
         "PerPkg": "1",
@@ -404,7 +363,6 @@
     },
     {
         "BriefDescription": "AK Ring In Use; Up and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_C_RING_AK_USED.UP_ODD",
         "PerPkg": "1",
@@ -414,27 +372,24 @@
     },
     {
         "BriefDescription": "BL Ring in Use; Down",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_C_RING_BL_USED.ALL",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Down",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_C_RING_BL_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Up",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_C_RING_BL_USED.CW",
         "PerPkg": "1",
@@ -444,7 +399,6 @@
     },
     {
         "BriefDescription": "BL Ring in Use; Down and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_C_RING_BL_USED.DOWN_EVEN",
         "PerPkg": "1",
@@ -454,7 +408,6 @@
     },
     {
         "BriefDescription": "BL Ring in Use; Down and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_C_RING_BL_USED.DOWN_ODD",
         "PerPkg": "1",
@@ -464,7 +417,6 @@
     },
     {
         "BriefDescription": "BL Ring in Use; Up and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_C_RING_BL_USED.UP_EVEN",
         "PerPkg": "1",
@@ -474,7 +426,6 @@
     },
     {
         "BriefDescription": "BL Ring in Use; Up and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_C_RING_BL_USED.UP_ODD",
         "PerPkg": "1",
@@ -484,7 +435,6 @@
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.; AD",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_C_RING_BOUNCES.AD",
         "PerPkg": "1",
@@ -493,7 +443,6 @@
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.; AK",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_C_RING_BOUNCES.AK",
         "PerPkg": "1",
@@ -502,7 +451,6 @@
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.; BL",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_C_RING_BOUNCES.BL",
         "PerPkg": "1",
@@ -511,7 +459,6 @@
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_C_RING_BOUNCES.IV",
         "PerPkg": "1",
@@ -520,37 +467,33 @@
     },
     {
         "BriefDescription": "BL Ring in Use; Any",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
         "EventName": "UNC_C_RING_IV_USED.ANY",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in BDX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Any",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
         "EventName": "UNC_C_RING_IV_USED.DN",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in BDX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Down",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
         "EventName": "UNC_C_RING_IV_USED.DOWN",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in BDX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters for Down polarity",
-        "UMask": "0xCC",
+        "UMask": "0xcc",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Any",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
         "EventName": "UNC_C_RING_IV_USED.UP",
         "PerPkg": "1",
@@ -560,7 +503,6 @@
     },
     {
         "BriefDescription": "AD",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_C_RING_SINK_STARVED.AD",
         "PerPkg": "1",
@@ -569,7 +511,6 @@
     },
     {
         "BriefDescription": "AK",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_C_RING_SINK_STARVED.AK",
         "PerPkg": "1",
@@ -578,7 +519,6 @@
     },
     {
         "BriefDescription": "BL",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_C_RING_SINK_STARVED.BL",
         "PerPkg": "1",
@@ -587,7 +527,6 @@
     },
     {
         "BriefDescription": "IV",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_C_RING_SINK_STARVED.IV",
         "PerPkg": "1",
@@ -596,7 +535,6 @@
     },
     {
         "BriefDescription": "Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_C_RING_SRC_THRTL",
         "PerPkg": "1",
@@ -604,7 +542,6 @@
     },
     {
         "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_C_RxR_EXT_STARVED.IPQ",
         "PerPkg": "1",
@@ -614,7 +551,6 @@
     },
     {
         "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_C_RxR_EXT_STARVED.IRQ",
         "PerPkg": "1",
@@ -624,7 +560,6 @@
     },
     {
         "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
         "PerPkg": "1",
@@ -634,7 +569,6 @@
     },
     {
         "BriefDescription": "Ingress Arbiter Blocking Cycles; PRQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_C_RxR_EXT_STARVED.PRQ",
         "PerPkg": "1",
@@ -644,7 +578,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; IPQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_C_RxR_INSERTS.IPQ",
         "PerPkg": "1",
@@ -654,7 +587,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; IRQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_C_RxR_INSERTS.IRQ",
         "PerPkg": "1",
@@ -664,7 +596,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; IRQ Rejected",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_C_RxR_INSERTS.IRQ_REJ",
         "PerPkg": "1",
@@ -674,7 +605,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; PRQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_C_RxR_INSERTS.PRQ",
         "PerPkg": "1",
@@ -684,7 +614,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; PRQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_C_RxR_INSERTS.PRQ_REJ",
         "PerPkg": "1",
@@ -694,7 +623,6 @@
     },
     {
         "BriefDescription": "Ingress Internal Starvation Cycles; IPQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_C_RxR_INT_STARVED.IPQ",
         "PerPkg": "1",
@@ -704,7 +632,6 @@
     },
     {
         "BriefDescription": "Ingress Internal Starvation Cycles; IRQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_C_RxR_INT_STARVED.IRQ",
         "PerPkg": "1",
@@ -714,7 +641,6 @@
     },
     {
         "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_C_RxR_INT_STARVED.ISMQ",
         "PerPkg": "1",
@@ -724,7 +650,6 @@
     },
     {
         "BriefDescription": "Ingress Internal Starvation Cycles; PRQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_C_RxR_INT_STARVED.PRQ",
         "PerPkg": "1",
@@ -734,7 +659,6 @@
     },
     {
         "BriefDescription": "Probe Queue Retries; Address Conflict",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
         "PerPkg": "1",
@@ -744,7 +668,6 @@
     },
     {
         "BriefDescription": "Probe Queue Retries; Any Reject",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_C_RxR_IPQ_RETRY.ANY",
         "PerPkg": "1",
@@ -754,7 +677,6 @@
     },
     {
         "BriefDescription": "Probe Queue Retries; No Egress Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_C_RxR_IPQ_RETRY.FULL",
         "PerPkg": "1",
@@ -764,7 +686,6 @@
     },
     {
         "BriefDescription": "Probe Queue Retries; No QPI Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS",
         "PerPkg": "1",
@@ -774,7 +695,6 @@
     },
     {
         "BriefDescription": "Probe Queue Retries; No AD Sbo Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "UNC_C_RxR_IPQ_RETRY2.AD_SBO",
         "PerPkg": "1",
@@ -784,7 +704,6 @@
     },
     {
         "BriefDescription": "Probe Queue Retries; Target Node Filter",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "UNC_C_RxR_IPQ_RETRY2.TARGET",
         "PerPkg": "1",
@@ -794,7 +713,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; Address Conflict",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
         "PerPkg": "1",
@@ -804,7 +722,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; Any Reject",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.ANY",
         "PerPkg": "1",
@@ -814,7 +731,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; No Egress Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.FULL",
         "PerPkg": "1",
@@ -824,7 +740,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS",
         "PerPkg": "1",
@@ -834,7 +749,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.NID",
         "PerPkg": "1",
@@ -844,7 +758,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS",
         "PerPkg": "1",
@@ -854,7 +767,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; No RTIDs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.RTID",
         "PerPkg": "1",
@@ -864,7 +776,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; No AD Sbo Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_C_RxR_IRQ_RETRY2.AD_SBO",
         "PerPkg": "1",
@@ -874,7 +785,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; No BL Sbo Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_C_RxR_IRQ_RETRY2.BL_SBO",
         "PerPkg": "1",
@@ -884,7 +794,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; Target Node Filter",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_C_RxR_IRQ_RETRY2.TARGET",
         "PerPkg": "1",
@@ -894,7 +803,6 @@
     },
     {
         "BriefDescription": "ISMQ Retries; Any Reject",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_C_RxR_ISMQ_RETRY.ANY",
         "PerPkg": "1",
@@ -904,7 +812,6 @@
     },
     {
         "BriefDescription": "ISMQ Retries; No Egress Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_C_RxR_ISMQ_RETRY.FULL",
         "PerPkg": "1",
@@ -914,7 +821,6 @@
     },
     {
         "BriefDescription": "ISMQ Retries; No IIO Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
         "PerPkg": "1",
@@ -924,7 +830,6 @@
     },
     {
         "BriefDescription": "ISMQ Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_C_RxR_ISMQ_RETRY.NID",
         "PerPkg": "1",
@@ -934,7 +839,6 @@
     },
     {
         "BriefDescription": "ISMQ Retries; No QPI Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
         "PerPkg": "1",
@@ -944,7 +848,6 @@
     },
     {
         "BriefDescription": "ISMQ Retries; No RTIDs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID",
         "PerPkg": "1",
@@ -954,7 +857,6 @@
     },
     {
         "BriefDescription": "ISMQ Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS",
         "PerPkg": "1",
@@ -964,7 +866,6 @@
     },
     {
         "BriefDescription": "ISMQ Request Queue Rejects; No AD Sbo Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_C_RxR_ISMQ_RETRY2.AD_SBO",
         "PerPkg": "1",
@@ -974,7 +875,6 @@
     },
     {
         "BriefDescription": "ISMQ Request Queue Rejects; No BL Sbo Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_C_RxR_ISMQ_RETRY2.BL_SBO",
         "PerPkg": "1",
@@ -984,7 +884,6 @@
     },
     {
         "BriefDescription": "ISMQ Request Queue Rejects; Target Node Filter",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_C_RxR_ISMQ_RETRY2.TARGET",
         "PerPkg": "1",
@@ -1030,7 +929,6 @@
     },
     {
         "BriefDescription": "SBo Credits Acquired; For AD Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3D",
         "EventName": "UNC_C_SBO_CREDITS_ACQUIRED.AD",
         "PerPkg": "1",
@@ -1040,7 +938,6 @@
     },
     {
         "BriefDescription": "SBo Credits Acquired; For BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3D",
         "EventName": "UNC_C_SBO_CREDITS_ACQUIRED.BL",
         "PerPkg": "1",
@@ -1068,7 +965,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.ALL",
         "PerPkg": "1",
@@ -1078,7 +974,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; Evictions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.EVICTION",
         "PerPkg": "1",
@@ -1088,7 +983,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; Local Memory",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.LOCAL",
         "PerPkg": "1",
@@ -1098,7 +992,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE",
         "PerPkg": "1",
@@ -1108,17 +1001,15 @@
     },
     {
         "BriefDescription": "TOR Inserts; Misses to Local Memory",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by locally HOMed memory.",
-        "UMask": "0x2A",
+        "UMask": "0x2a",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE",
         "PerPkg": "1",
@@ -1128,7 +1019,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; Miss Opcode Match",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE",
         "PerPkg": "1",
@@ -1138,17 +1028,15 @@
     },
     {
         "BriefDescription": "TOR Inserts; Misses to Remote Memory",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by remote caches or remote memory.",
-        "UMask": "0x8A",
+        "UMask": "0x8a",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE",
         "PerPkg": "1",
@@ -1158,7 +1046,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; NID Matched",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.NID_ALL",
         "PerPkg": "1",
@@ -1168,7 +1055,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; NID Matched Evictions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION",
         "PerPkg": "1",
@@ -1178,17 +1064,15 @@
     },
     {
         "BriefDescription": "TOR Inserts; NID Matched Miss All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.",
-        "UMask": "0x4A",
+        "UMask": "0x4a",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
         "PerPkg": "1",
@@ -1198,7 +1082,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; NID and Opcode Matched",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE",
         "PerPkg": "1",
@@ -1208,7 +1091,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; NID Matched Writebacks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.NID_WB",
         "PerPkg": "1",
@@ -1218,7 +1100,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; Opcode Match",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.OPCODE",
         "PerPkg": "1",
@@ -1228,7 +1109,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; Remote Memory",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.REMOTE",
         "PerPkg": "1",
@@ -1238,7 +1118,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE",
         "PerPkg": "1",
@@ -1248,7 +1127,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; Writebacks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.WB",
         "PerPkg": "1",
@@ -1298,7 +1176,7 @@
         "EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL",
         "PerPkg": "1",
         "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR.  'Miss' means the allocation requires an RTID.  This generally means that the request was sent to memory or MMIO.",
-        "UMask": "0xA",
+        "UMask": "0xa",
         "Unit": "CBO"
     },
     {
@@ -1307,7 +1185,7 @@
         "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL",
         "PerPkg": "1",
         "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
-        "UMask": "0x2A",
+        "UMask": "0x2a",
         "Unit": "CBO"
     },
     {
@@ -1334,7 +1212,7 @@
         "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE",
         "PerPkg": "1",
         "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
-        "UMask": "0x8A",
+        "UMask": "0x8a",
         "Unit": "CBO"
     },
     {
@@ -1370,7 +1248,7 @@
         "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
         "PerPkg": "1",
         "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID.",
-        "UMask": "0x4A",
+        "UMask": "0x4a",
         "Unit": "CBO"
     },
     {
@@ -1438,7 +1316,6 @@
     },
     {
         "BriefDescription": "Onto AD Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_C_TxR_ADS_USED.AD",
         "PerPkg": "1",
@@ -1447,7 +1324,6 @@
     },
     {
         "BriefDescription": "Onto AK Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_C_TxR_ADS_USED.AK",
         "PerPkg": "1",
@@ -1456,7 +1332,6 @@
     },
     {
         "BriefDescription": "Onto BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_C_TxR_ADS_USED.BL",
         "PerPkg": "1",
@@ -1465,7 +1340,6 @@
     },
     {
         "BriefDescription": "Egress Allocations; AD - Cachebo",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.AD_CACHE",
         "PerPkg": "1",
@@ -1475,7 +1349,6 @@
     },
     {
         "BriefDescription": "Egress Allocations; AD - Corebo",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.AD_CORE",
         "PerPkg": "1",
@@ -1485,7 +1358,6 @@
     },
     {
         "BriefDescription": "Egress Allocations; AK - Cachebo",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.AK_CACHE",
         "PerPkg": "1",
@@ -1495,7 +1367,6 @@
     },
     {
         "BriefDescription": "Egress Allocations; AK - Corebo",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.AK_CORE",
         "PerPkg": "1",
@@ -1505,7 +1376,6 @@
     },
     {
         "BriefDescription": "Egress Allocations; BL - Cacheno",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.BL_CACHE",
         "PerPkg": "1",
@@ -1515,7 +1385,6 @@
     },
     {
         "BriefDescription": "Egress Allocations; BL - Corebo",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.BL_CORE",
         "PerPkg": "1",
@@ -1525,7 +1394,6 @@
     },
     {
         "BriefDescription": "Egress Allocations; IV - Cachebo",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.IV_CACHE",
         "PerPkg": "1",
@@ -1535,7 +1403,6 @@
     },
     {
         "BriefDescription": "Injection Starvation; Onto AD Ring (to core)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_C_TxR_STARVED.AD_CORE",
         "PerPkg": "1",
@@ -1545,7 +1412,6 @@
     },
     {
         "BriefDescription": "Injection Starvation; Onto AK Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_C_TxR_STARVED.AK_BOTH",
         "PerPkg": "1",
@@ -1555,7 +1421,6 @@
     },
     {
         "BriefDescription": "Injection Starvation; Onto BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_C_TxR_STARVED.BL_BOTH",
         "PerPkg": "1",
@@ -1565,7 +1430,6 @@
     },
     {
         "BriefDescription": "Injection Starvation; Onto IV Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_C_TxR_STARVED.IV",
         "PerPkg": "1",
@@ -1575,7 +1439,6 @@
     },
     {
         "BriefDescription": "BT Cycles Not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0x42",
         "EventName": "UNC_H_BT_CYCLES_NE",
         "PerPkg": "1",
@@ -1584,7 +1447,6 @@
     },
     {
         "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
-        "Counter": "0,1,2,3",
         "EventCode": "0x51",
         "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD",
         "PerPkg": "1",
@@ -1594,7 +1456,6 @@
     },
     {
         "BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard",
-        "Counter": "0,1,2,3",
         "EventCode": "0x51",
         "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD",
         "PerPkg": "1",
@@ -1604,7 +1465,6 @@
     },
     {
         "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
-        "Counter": "0,1,2,3",
         "EventCode": "0x51",
         "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD",
         "PerPkg": "1",
@@ -1614,7 +1474,6 @@
     },
     {
         "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
-        "Counter": "0,1,2,3",
         "EventCode": "0x51",
         "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD",
         "PerPkg": "1",
@@ -1624,7 +1483,6 @@
     },
     {
         "BriefDescription": "HA to iMC Bypass; Not Taken",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN",
         "PerPkg": "1",
@@ -1634,7 +1492,6 @@
     },
     {
         "BriefDescription": "HA to iMC Bypass; Taken",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_H_BYPASS_IMC.TAKEN",
         "PerPkg": "1",
@@ -1644,7 +1501,6 @@
     },
     {
         "BriefDescription": "uclks",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_H_CLOCKTICKS",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of uclks in the HA.  This will be slightly different than the count in the Ubox because of enable/freeze delays.  The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.",
@@ -1652,7 +1508,6 @@
     },
     {
         "BriefDescription": "Direct2Core Messages Sent",
-        "Counter": "0,1,2,3",
         "EventCode": "0x11",
         "EventName": "UNC_H_DIRECT2CORE_COUNT",
         "PerPkg": "1",
@@ -1661,7 +1516,6 @@
     },
     {
         "BriefDescription": "Cycles when Direct2Core was Disabled",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED",
         "PerPkg": "1",
@@ -1670,7 +1524,6 @@
     },
     {
         "BriefDescription": "Number of Reads that had Direct2Core Overridden",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE",
         "PerPkg": "1",
@@ -1679,7 +1532,6 @@
     },
     {
         "BriefDescription": "Directory Lat Opt Return",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_H_DIRECTORY_LAT_OPT",
         "PerPkg": "1",
@@ -1688,7 +1540,6 @@
     },
     {
         "BriefDescription": "Directory Lookups; Snoop Not Needed",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC",
         "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP",
         "PerPkg": "1",
@@ -1698,7 +1549,6 @@
     },
     {
         "BriefDescription": "Directory Lookups; Snoop Needed",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC",
         "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP",
         "PerPkg": "1",
@@ -1708,7 +1558,6 @@
     },
     {
         "BriefDescription": "Directory Updates; Any Directory Update",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD",
         "EventName": "UNC_H_DIRECTORY_UPDATE.ANY",
         "PerPkg": "1",
@@ -1718,7 +1567,6 @@
     },
     {
         "BriefDescription": "Directory Updates; Directory Clear",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD",
         "EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR",
         "PerPkg": "1",
@@ -1728,7 +1576,6 @@
     },
     {
         "BriefDescription": "Directory Updates; Directory Set",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD",
         "EventName": "UNC_H_DIRECTORY_UPDATE.SET",
         "PerPkg": "1",
@@ -1738,7 +1585,6 @@
     },
     {
         "BriefDescription": "Counts Number of Hits in HitMe Cache; op is AckCnfltWbI",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "UNC_H_HITME_HIT.ACKCNFLTWBI",
         "PerPkg": "1",
@@ -1747,16 +1593,14 @@
     },
     {
         "BriefDescription": "Counts Number of Hits in HitMe Cache; All Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "UNC_H_HITME_HIT.ALL",
         "PerPkg": "1",
-        "UMask": "0xFF",
+        "UMask": "0xff",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "UNC_H_HITME_HIT.ALLOCS",
         "PerPkg": "1",
@@ -1765,7 +1609,6 @@
     },
     {
         "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "UNC_H_HITME_HIT.EVICTS",
         "PerPkg": "1",
@@ -1774,16 +1617,14 @@
     },
     {
         "BriefDescription": "Counts Number of Hits in HitMe Cache; HOM Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "UNC_H_HITME_HIT.HOM",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Counts Number of Hits in HitMe Cache; Invalidations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "UNC_H_HITME_HIT.INVALS",
         "PerPkg": "1",
@@ -1792,7 +1633,6 @@
     },
     {
         "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "UNC_H_HITME_HIT.READ_OR_INVITOE",
         "PerPkg": "1",
@@ -1801,7 +1641,6 @@
     },
     {
         "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "UNC_H_HITME_HIT.RSP",
         "PerPkg": "1",
@@ -1810,7 +1649,6 @@
     },
     {
         "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "UNC_H_HITME_HIT.RSPFWDI_LOCAL",
         "PerPkg": "1",
@@ -1819,7 +1657,6 @@
     },
     {
         "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "UNC_H_HITME_HIT.RSPFWDI_REMOTE",
         "PerPkg": "1",
@@ -1828,7 +1665,6 @@
     },
     {
         "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "UNC_H_HITME_HIT.RSPFWDS",
         "PerPkg": "1",
@@ -1837,7 +1673,6 @@
     },
     {
         "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "UNC_H_HITME_HIT.WBMTOE_OR_S",
         "PerPkg": "1",
@@ -1846,7 +1681,6 @@
     },
     {
         "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "UNC_H_HITME_HIT.WBMTOI",
         "PerPkg": "1",
@@ -1855,7 +1689,6 @@
     },
     {
         "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI",
-        "Counter": "0,1,2,3",
         "EventCode": "0x72",
         "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI",
         "PerPkg": "1",
@@ -1864,25 +1697,22 @@
     },
     {
         "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; All Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x72",
         "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ALL",
         "PerPkg": "1",
-        "UMask": "0xFF",
+        "UMask": "0xff",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x72",
         "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.HOM",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
-        "Counter": "0,1,2,3",
         "EventCode": "0x72",
         "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE",
         "PerPkg": "1",
@@ -1891,7 +1721,6 @@
     },
     {
         "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
-        "Counter": "0,1,2,3",
         "EventCode": "0x72",
         "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSP",
         "PerPkg": "1",
@@ -1900,7 +1729,6 @@
     },
     {
         "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a local request",
-        "Counter": "0,1,2,3",
         "EventCode": "0x72",
         "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL",
         "PerPkg": "1",
@@ -1909,7 +1737,6 @@
     },
     {
         "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request",
-        "Counter": "0,1,2,3",
         "EventCode": "0x72",
         "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE",
         "PerPkg": "1",
@@ -1918,7 +1745,6 @@
     },
     {
         "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb",
-        "Counter": "0,1,2,3",
         "EventCode": "0x72",
         "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS",
         "PerPkg": "1",
@@ -1927,7 +1753,6 @@
     },
     {
         "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x72",
         "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S",
         "PerPkg": "1",
@@ -1936,7 +1761,6 @@
     },
     {
         "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI",
-        "Counter": "0,1,2,3",
         "EventCode": "0x72",
         "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI",
         "PerPkg": "1",
@@ -1945,7 +1769,6 @@
     },
     {
         "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI",
-        "Counter": "0,1,2,3",
         "EventCode": "0x70",
         "EventName": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI",
         "PerPkg": "1",
@@ -1954,16 +1777,14 @@
     },
     {
         "BriefDescription": "Counts Number of times HitMe Cache is accessed; All Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x70",
         "EventName": "UNC_H_HITME_LOOKUP.ALL",
         "PerPkg": "1",
-        "UMask": "0xFF",
+        "UMask": "0xff",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Counts Number of times HitMe Cache is accessed; Allocations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x70",
         "EventName": "UNC_H_HITME_LOOKUP.ALLOCS",
         "PerPkg": "1",
@@ -1972,16 +1793,14 @@
     },
     {
         "BriefDescription": "Counts Number of times HitMe Cache is accessed; HOM Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x70",
         "EventName": "UNC_H_HITME_LOOKUP.HOM",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Counts Number of times HitMe Cache is accessed; Invalidations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x70",
         "EventName": "UNC_H_HITME_LOOKUP.INVALS",
         "PerPkg": "1",
@@ -1990,7 +1809,6 @@
     },
     {
         "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
-        "Counter": "0,1,2,3",
         "EventCode": "0x70",
         "EventName": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE",
         "PerPkg": "1",
@@ -1999,7 +1817,6 @@
     },
     {
         "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
-        "Counter": "0,1,2,3",
         "EventCode": "0x70",
         "EventName": "UNC_H_HITME_LOOKUP.RSP",
         "PerPkg": "1",
@@ -2008,7 +1825,6 @@
     },
     {
         "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request",
-        "Counter": "0,1,2,3",
         "EventCode": "0x70",
         "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL",
         "PerPkg": "1",
@@ -2017,7 +1833,6 @@
     },
     {
         "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request",
-        "Counter": "0,1,2,3",
         "EventCode": "0x70",
         "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE",
         "PerPkg": "1",
@@ -2026,7 +1841,6 @@
     },
     {
         "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb",
-        "Counter": "0,1,2,3",
         "EventCode": "0x70",
         "EventName": "UNC_H_HITME_LOOKUP.RSPFWDS",
         "PerPkg": "1",
@@ -2035,7 +1849,6 @@
     },
     {
         "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x70",
         "EventName": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S",
         "PerPkg": "1",
@@ -2044,7 +1857,6 @@
     },
     {
         "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoI",
-        "Counter": "0,1,2,3",
         "EventCode": "0x70",
         "EventName": "UNC_H_HITME_LOOKUP.WBMTOI",
         "PerPkg": "1",
@@ -2053,7 +1865,6 @@
     },
     {
         "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
         "PerPkg": "1",
@@ -2063,7 +1874,6 @@
     },
     {
         "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
         "PerPkg": "1",
@@ -2073,7 +1883,6 @@
     },
     {
         "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2",
         "PerPkg": "1",
@@ -2083,7 +1892,6 @@
     },
     {
         "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
         "PerPkg": "1",
@@ -2093,7 +1901,6 @@
     },
     {
         "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
         "PerPkg": "1",
@@ -2103,7 +1910,6 @@
     },
     {
         "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2",
         "PerPkg": "1",
@@ -2113,7 +1919,6 @@
     },
     {
         "BriefDescription": "HA to iMC Normal Priority Reads Issued; Normal Priority",
-        "Counter": "0,1,2,3",
         "EventCode": "0x17",
         "EventName": "UNC_H_IMC_READS.NORMAL",
         "PerPkg": "1",
@@ -2123,7 +1928,6 @@
     },
     {
         "BriefDescription": "Retry Events",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
         "EventName": "UNC_H_IMC_RETRY",
         "PerPkg": "1",
@@ -2131,17 +1935,15 @@
     },
     {
         "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1A",
         "EventName": "UNC_H_IMC_WRITES.ALL",
         "PerPkg": "1",
         "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1A",
         "EventName": "UNC_H_IMC_WRITES.FULL",
         "PerPkg": "1",
@@ -2151,7 +1953,6 @@
     },
     {
         "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full Line",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1A",
         "EventName": "UNC_H_IMC_WRITES.FULL_ISOCH",
         "PerPkg": "1",
@@ -2161,7 +1962,6 @@
     },
     {
         "BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1A",
         "EventName": "UNC_H_IMC_WRITES.PARTIAL",
         "PerPkg": "1",
@@ -2171,7 +1971,6 @@
     },
     {
         "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1A",
         "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH",
         "PerPkg": "1",
@@ -2181,7 +1980,6 @@
     },
     {
         "BriefDescription": "IOT Backpressure",
-        "Counter": "0,1,2",
         "EventCode": "0x61",
         "EventName": "UNC_H_IOT_BACKPRESSURE.HUB",
         "PerPkg": "1",
@@ -2190,7 +1988,6 @@
     },
     {
         "BriefDescription": "IOT Backpressure",
-        "Counter": "0,1,2",
         "EventCode": "0x61",
         "EventName": "UNC_H_IOT_BACKPRESSURE.SAT",
         "PerPkg": "1",
@@ -2199,7 +1996,6 @@
     },
     {
         "BriefDescription": "IOT Common Trigger Sequencer - Lo",
-        "Counter": "0,1,2",
         "EventCode": "0x64",
         "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS0",
         "PerPkg": "1",
@@ -2209,7 +2005,6 @@
     },
     {
         "BriefDescription": "IOT Common Trigger Sequencer - Lo",
-        "Counter": "0,1,2",
         "EventCode": "0x64",
         "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS1",
         "PerPkg": "1",
@@ -2219,7 +2014,6 @@
     },
     {
         "BriefDescription": "IOT Common Trigger Sequencer - Hi",
-        "Counter": "0,1,2",
         "EventCode": "0x65",
         "EventName": "UNC_H_IOT_CTS_HI.CTS2",
         "PerPkg": "1",
@@ -2229,7 +2023,6 @@
     },
     {
         "BriefDescription": "IOT Common Trigger Sequencer - Hi",
-        "Counter": "0,1,2",
         "EventCode": "0x65",
         "EventName": "UNC_H_IOT_CTS_HI.CTS3",
         "PerPkg": "1",
@@ -2239,7 +2032,6 @@
     },
     {
         "BriefDescription": "IOT Common Trigger Sequencer - Lo",
-        "Counter": "0,1,2",
         "EventCode": "0x62",
         "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS0",
         "PerPkg": "1",
@@ -2249,7 +2041,6 @@
     },
     {
         "BriefDescription": "IOT Common Trigger Sequencer - Lo",
-        "Counter": "0,1,2",
         "EventCode": "0x62",
         "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS1",
         "PerPkg": "1",
@@ -2259,7 +2050,6 @@
     },
     {
         "BriefDescription": "OSB Snoop Broadcast; Cancelled",
-        "Counter": "0,1,2,3",
         "EventCode": "0x53",
         "EventName": "UNC_H_OSB.CANCELLED",
         "PerPkg": "1",
@@ -2269,7 +2059,6 @@
     },
     {
         "BriefDescription": "OSB Snoop Broadcast; Local InvItoE",
-        "Counter": "0,1,2,3",
         "EventCode": "0x53",
         "EventName": "UNC_H_OSB.INVITOE_LOCAL",
         "PerPkg": "1",
@@ -2279,7 +2068,6 @@
     },
     {
         "BriefDescription": "OSB Snoop Broadcast; Local Reads",
-        "Counter": "0,1,2,3",
         "EventCode": "0x53",
         "EventName": "UNC_H_OSB.READS_LOCAL",
         "PerPkg": "1",
@@ -2289,7 +2077,6 @@
     },
     {
         "BriefDescription": "OSB Snoop Broadcast; Reads Local -  Useful",
-        "Counter": "0,1,2,3",
         "EventCode": "0x53",
         "EventName": "UNC_H_OSB.READS_LOCAL_USEFUL",
         "PerPkg": "1",
@@ -2299,7 +2086,6 @@
     },
     {
         "BriefDescription": "OSB Snoop Broadcast; Remote",
-        "Counter": "0,1,2,3",
         "EventCode": "0x53",
         "EventName": "UNC_H_OSB.REMOTE",
         "PerPkg": "1",
@@ -2309,7 +2095,6 @@
     },
     {
         "BriefDescription": "OSB Snoop Broadcast; Remote - Useful",
-        "Counter": "0,1,2,3",
         "EventCode": "0x53",
         "EventName": "UNC_H_OSB.REMOTE_USEFUL",
         "PerPkg": "1",
@@ -2319,7 +2104,6 @@
     },
     {
         "BriefDescription": "OSB Early Data Return; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "UNC_H_OSB_EDR.ALL",
         "PerPkg": "1",
@@ -2329,7 +2113,6 @@
     },
     {
         "BriefDescription": "OSB Early Data Return; Reads to Local  I",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "UNC_H_OSB_EDR.READS_LOCAL_I",
         "PerPkg": "1",
@@ -2339,7 +2122,6 @@
     },
     {
         "BriefDescription": "OSB Early Data Return; Reads to Local S",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "UNC_H_OSB_EDR.READS_LOCAL_S",
         "PerPkg": "1",
@@ -2349,7 +2131,6 @@
     },
     {
         "BriefDescription": "OSB Early Data Return; Reads to Remote I",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "UNC_H_OSB_EDR.READS_REMOTE_I",
         "PerPkg": "1",
@@ -2359,7 +2140,6 @@
     },
     {
         "BriefDescription": "OSB Early Data Return; Reads to Remote S",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "UNC_H_OSB_EDR.READS_REMOTE_S",
         "PerPkg": "1",
@@ -2369,7 +2149,6 @@
     },
     {
         "BriefDescription": "Read and Write Requests; Local InvItoEs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
         "PerPkg": "1",
@@ -2379,7 +2158,6 @@
     },
     {
         "BriefDescription": "Read and Write Requests; Remote InvItoEs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
         "PerPkg": "1",
@@ -2389,7 +2167,6 @@
     },
     {
         "BriefDescription": "Read and Write Requests; Reads",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_H_REQUESTS.READS",
         "PerPkg": "1",
@@ -2399,7 +2176,6 @@
     },
     {
         "BriefDescription": "Read and Write Requests; Local Reads",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_H_REQUESTS.READS_LOCAL",
         "PerPkg": "1",
@@ -2409,7 +2185,6 @@
     },
     {
         "BriefDescription": "Read and Write Requests; Remote Reads",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_H_REQUESTS.READS_REMOTE",
         "PerPkg": "1",
@@ -2419,17 +2194,15 @@
     },
     {
         "BriefDescription": "Read and Write Requests; Writes",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_H_REQUESTS.WRITES",
         "PerPkg": "1",
         "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; Incoming write requests.",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Read and Write Requests; Local Writes",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
         "PerPkg": "1",
@@ -2439,7 +2212,6 @@
     },
     {
         "BriefDescription": "Read and Write Requests; Remote Writes",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_H_REQUESTS.WRITES_REMOTE",
         "PerPkg": "1",
@@ -2449,17 +2221,15 @@
     },
     {
         "BriefDescription": "HA AD Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3E",
         "EventName": "UNC_H_RING_AD_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3E",
         "EventName": "UNC_H_RING_AD_USED.CCW_EVEN",
         "PerPkg": "1",
@@ -2469,7 +2239,6 @@
     },
     {
         "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3E",
         "EventName": "UNC_H_RING_AD_USED.CCW_ODD",
         "PerPkg": "1",
@@ -2479,7 +2248,6 @@
     },
     {
         "BriefDescription": "HA AD Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3E",
         "EventName": "UNC_H_RING_AD_USED.CW",
         "PerPkg": "1",
@@ -2489,7 +2257,6 @@
     },
     {
         "BriefDescription": "HA AD Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3E",
         "EventName": "UNC_H_RING_AD_USED.CW_EVEN",
         "PerPkg": "1",
@@ -2499,7 +2266,6 @@
     },
     {
         "BriefDescription": "HA AD Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3E",
         "EventName": "UNC_H_RING_AD_USED.CW_ODD",
         "PerPkg": "1",
@@ -2509,27 +2275,24 @@
     },
     {
         "BriefDescription": "HA AK Ring in Use; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3F",
         "EventName": "UNC_H_RING_AK_USED.ALL",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA AK Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3F",
         "EventName": "UNC_H_RING_AK_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3F",
         "EventName": "UNC_H_RING_AK_USED.CCW_EVEN",
         "PerPkg": "1",
@@ -2539,7 +2302,6 @@
     },
     {
         "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3F",
         "EventName": "UNC_H_RING_AK_USED.CCW_ODD",
         "PerPkg": "1",
@@ -2549,7 +2311,6 @@
     },
     {
         "BriefDescription": "HA AK Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3F",
         "EventName": "UNC_H_RING_AK_USED.CW",
         "PerPkg": "1",
@@ -2559,7 +2320,6 @@
     },
     {
         "BriefDescription": "HA AK Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3F",
         "EventName": "UNC_H_RING_AK_USED.CW_EVEN",
         "PerPkg": "1",
@@ -2569,7 +2329,6 @@
     },
     {
         "BriefDescription": "HA AK Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3F",
         "EventName": "UNC_H_RING_AK_USED.CW_ODD",
         "PerPkg": "1",
@@ -2579,27 +2338,24 @@
     },
     {
         "BriefDescription": "HA BL Ring in Use; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.ALL",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA BL Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.CCW_EVEN",
         "PerPkg": "1",
@@ -2609,7 +2365,6 @@
     },
     {
         "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.CCW_ODD",
         "PerPkg": "1",
@@ -2619,7 +2374,6 @@
     },
     {
         "BriefDescription": "HA BL Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.CW",
         "PerPkg": "1",
@@ -2629,7 +2383,6 @@
     },
     {
         "BriefDescription": "HA BL Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.CW_EVEN",
         "PerPkg": "1",
@@ -2639,7 +2392,6 @@
     },
     {
         "BriefDescription": "HA BL Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.CW_ODD",
         "PerPkg": "1",
@@ -2649,7 +2401,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
         "PerPkg": "1",
@@ -2659,7 +2410,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
         "PerPkg": "1",
@@ -2669,7 +2419,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
         "PerPkg": "1",
@@ -2679,7 +2428,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
         "PerPkg": "1",
@@ -2689,7 +2437,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
         "PerPkg": "1",
@@ -2699,7 +2446,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
         "PerPkg": "1",
@@ -2709,7 +2455,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
         "PerPkg": "1",
@@ -2719,7 +2464,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
         "PerPkg": "1",
@@ -2729,7 +2473,6 @@
     },
     {
         "BriefDescription": "SBo0 Credits Acquired; For AD Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x68",
         "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.AD",
         "PerPkg": "1",
@@ -2739,7 +2482,6 @@
     },
     {
         "BriefDescription": "SBo0 Credits Acquired; For BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x68",
         "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.BL",
         "PerPkg": "1",
@@ -2749,7 +2491,6 @@
     },
     {
         "BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6A",
         "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.AD",
         "PerPkg": "1",
@@ -2759,7 +2500,6 @@
     },
     {
         "BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6A",
         "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.BL",
         "PerPkg": "1",
@@ -2769,7 +2509,6 @@
     },
     {
         "BriefDescription": "SBo1 Credits Acquired; For AD Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x69",
         "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.AD",
         "PerPkg": "1",
@@ -2779,7 +2518,6 @@
     },
     {
         "BriefDescription": "SBo1 Credits Acquired; For BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x69",
         "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.BL",
         "PerPkg": "1",
@@ -2789,7 +2527,6 @@
     },
     {
         "BriefDescription": "SBo1 Credits Occupancy; For AD Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6B",
         "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.AD",
         "PerPkg": "1",
@@ -2799,7 +2536,6 @@
     },
     {
         "BriefDescription": "SBo1 Credits Occupancy; For BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6B",
         "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.BL",
         "PerPkg": "1",
@@ -2809,7 +2545,6 @@
     },
     {
         "BriefDescription": "Data beat the Snoop Responses; Local Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL",
         "PerPkg": "1",
@@ -2819,7 +2554,6 @@
     },
     {
         "BriefDescription": "Data beat the Snoop Responses; Remote Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE",
         "PerPkg": "1",
@@ -2829,7 +2563,6 @@
     },
     {
         "BriefDescription": "Cycles with Snoops Outstanding; All Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_H_SNOOP_CYCLES_NE.ALL",
         "PerPkg": "1",
@@ -2839,7 +2572,6 @@
     },
     {
         "BriefDescription": "Cycles with Snoops Outstanding; Local Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_H_SNOOP_CYCLES_NE.LOCAL",
         "PerPkg": "1",
@@ -2849,7 +2581,6 @@
     },
     {
         "BriefDescription": "Cycles with Snoops Outstanding; Remote Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_H_SNOOP_CYCLES_NE.REMOTE",
         "PerPkg": "1",
@@ -2859,7 +2590,6 @@
     },
     {
         "BriefDescription": "Tracker Snoops Outstanding Accumulator; Local Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_H_SNOOP_OCCUPANCY.LOCAL",
         "PerPkg": "1",
@@ -2869,7 +2599,6 @@
     },
     {
         "BriefDescription": "Tracker Snoops Outstanding Accumulator; Remote Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_H_SNOOP_OCCUPANCY.REMOTE",
         "PerPkg": "1",
@@ -2879,7 +2608,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received; RSPCNFLCT*",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
         "PerPkg": "1",
@@ -2889,7 +2617,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received; RspI",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_H_SNOOP_RESP.RSPI",
         "PerPkg": "1",
@@ -2899,7 +2626,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received; RspIFwd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
         "PerPkg": "1",
@@ -2909,7 +2635,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received; RspS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_H_SNOOP_RESP.RSPS",
         "PerPkg": "1",
@@ -2919,7 +2644,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received; RspSFwd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
         "PerPkg": "1",
@@ -2929,7 +2653,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received; Rsp*Fwd*WB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
         "PerPkg": "1",
@@ -2939,7 +2662,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received; Rsp*WB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_H_SNOOP_RESP.RSP_WB",
         "PerPkg": "1",
@@ -2949,7 +2671,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received Local; Other",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER",
         "PerPkg": "1",
@@ -2959,7 +2680,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received Local; RspCnflct",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT",
         "PerPkg": "1",
@@ -2969,7 +2689,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received Local; RspI",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPI",
         "PerPkg": "1",
@@ -2979,7 +2698,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received Local; RspIFwd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD",
         "PerPkg": "1",
@@ -2989,7 +2707,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received Local; RspS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS",
         "PerPkg": "1",
@@ -2999,7 +2716,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received Local; RspSFwd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD",
         "PerPkg": "1",
@@ -3009,7 +2725,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB",
         "PerPkg": "1",
@@ -3019,7 +2734,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB",
         "PerPkg": "1",
@@ -3029,7 +2743,6 @@
     },
     {
         "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6C",
         "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD",
         "PerPkg": "1",
@@ -3039,7 +2752,6 @@
     },
     {
         "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6C",
         "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL",
         "PerPkg": "1",
@@ -3049,7 +2761,6 @@
     },
     {
         "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6C",
         "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD",
         "PerPkg": "1",
@@ -3059,7 +2770,6 @@
     },
     {
         "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6C",
         "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL",
         "PerPkg": "1",
@@ -3069,7 +2779,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION0",
         "PerPkg": "1",
@@ -3079,7 +2788,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION1",
         "PerPkg": "1",
@@ -3089,7 +2797,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION2",
         "PerPkg": "1",
@@ -3099,7 +2806,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION3",
         "PerPkg": "1",
@@ -3109,7 +2815,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION4",
         "PerPkg": "1",
@@ -3119,7 +2824,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION5",
         "PerPkg": "1",
@@ -3129,7 +2833,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION6",
         "PerPkg": "1",
@@ -3139,7 +2842,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION7",
         "PerPkg": "1",
@@ -3149,7 +2851,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10",
         "PerPkg": "1",
@@ -3159,7 +2860,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11",
         "PerPkg": "1",
@@ -3169,7 +2869,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_H_TAD_REQUESTS_G1.REGION8",
         "PerPkg": "1",
@@ -3179,7 +2878,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_H_TAD_REQUESTS_G1.REGION9",
         "PerPkg": "1",
@@ -3189,7 +2887,6 @@
     },
     {
         "BriefDescription": "Tracker Cycles Full; Cycles Completely Used",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_H_TRACKER_CYCLES_FULL.ALL",
         "PerPkg": "1",
@@ -3199,7 +2896,6 @@
     },
     {
         "BriefDescription": "Tracker Cycles Full; Cycles GP Completely Used",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_H_TRACKER_CYCLES_FULL.GP",
         "PerPkg": "1",
@@ -3209,7 +2905,6 @@
     },
     {
         "BriefDescription": "Tracker Cycles Not Empty; All Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_H_TRACKER_CYCLES_NE.ALL",
         "PerPkg": "1",
@@ -3219,7 +2914,6 @@
     },
     {
         "BriefDescription": "Tracker Cycles Not Empty; Local Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL",
         "PerPkg": "1",
@@ -3229,7 +2923,6 @@
     },
     {
         "BriefDescription": "Tracker Cycles Not Empty; Remote Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE",
         "PerPkg": "1",
@@ -3239,7 +2932,6 @@
     },
     {
         "BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL",
         "PerPkg": "1",
@@ -3249,7 +2941,6 @@
     },
     {
         "BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE",
         "PerPkg": "1",
@@ -3259,7 +2950,6 @@
     },
     {
         "BriefDescription": "Tracker Occupancy Accumultor; Local Read Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL",
         "PerPkg": "1",
@@ -3269,7 +2959,6 @@
     },
     {
         "BriefDescription": "Tracker Occupancy Accumultor; Remote Read Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE",
         "PerPkg": "1",
@@ -3279,7 +2968,6 @@
     },
     {
         "BriefDescription": "Tracker Occupancy Accumultor; Local Write Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL",
         "PerPkg": "1",
@@ -3289,7 +2977,6 @@
     },
     {
         "BriefDescription": "Tracker Occupancy Accumultor; Remote Write Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE",
         "PerPkg": "1",
@@ -3299,7 +2986,6 @@
     },
     {
         "BriefDescription": "Data Pending Occupancy Accumultor; Local Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL",
         "PerPkg": "1",
@@ -3309,7 +2995,6 @@
     },
     {
         "BriefDescription": "Data Pending Occupancy Accumultor; Remote Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE",
         "PerPkg": "1",
@@ -3319,7 +3004,6 @@
     },
     {
         "BriefDescription": "Outbound NDR Ring Transactions; Non-data Responses",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "UNC_H_TxR_AD.HOM",
         "PerPkg": "1",
@@ -3329,7 +3013,6 @@
     },
     {
         "BriefDescription": "AD Egress Full; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL",
         "PerPkg": "1",
@@ -3339,7 +3022,6 @@
     },
     {
         "BriefDescription": "AD Egress Full; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
         "PerPkg": "1",
@@ -3349,7 +3031,6 @@
     },
     {
         "BriefDescription": "AD Egress Full; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
         "PerPkg": "1",
@@ -3359,7 +3040,6 @@
     },
     {
         "BriefDescription": "AD Egress Not Empty; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL",
         "PerPkg": "1",
@@ -3369,7 +3049,6 @@
     },
     {
         "BriefDescription": "AD Egress Not Empty; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0",
         "PerPkg": "1",
@@ -3379,7 +3058,6 @@
     },
     {
         "BriefDescription": "AD Egress Not Empty; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1",
         "PerPkg": "1",
@@ -3389,7 +3067,6 @@
     },
     {
         "BriefDescription": "AD Egress Allocations; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "UNC_H_TxR_AD_INSERTS.ALL",
         "PerPkg": "1",
@@ -3399,7 +3076,6 @@
     },
     {
         "BriefDescription": "AD Egress Allocations; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "UNC_H_TxR_AD_INSERTS.SCHED0",
         "PerPkg": "1",
@@ -3409,7 +3085,6 @@
     },
     {
         "BriefDescription": "AD Egress Allocations; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "UNC_H_TxR_AD_INSERTS.SCHED1",
         "PerPkg": "1",
@@ -3419,7 +3094,6 @@
     },
     {
         "BriefDescription": "AK Egress Full; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL",
         "PerPkg": "1",
@@ -3429,7 +3103,6 @@
     },
     {
         "BriefDescription": "AK Egress Full; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
         "PerPkg": "1",
@@ -3439,7 +3112,6 @@
     },
     {
         "BriefDescription": "AK Egress Full; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
         "PerPkg": "1",
@@ -3449,7 +3121,6 @@
     },
     {
         "BriefDescription": "AK Egress Not Empty; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL",
         "PerPkg": "1",
@@ -3459,7 +3130,6 @@
     },
     {
         "BriefDescription": "AK Egress Not Empty; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0",
         "PerPkg": "1",
@@ -3469,7 +3139,6 @@
     },
     {
         "BriefDescription": "AK Egress Not Empty; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1",
         "PerPkg": "1",
@@ -3479,7 +3148,6 @@
     },
     {
         "BriefDescription": "AK Egress Allocations; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2F",
         "EventName": "UNC_H_TxR_AK_INSERTS.ALL",
         "PerPkg": "1",
@@ -3489,7 +3157,6 @@
     },
     {
         "BriefDescription": "AK Egress Allocations; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2F",
         "EventName": "UNC_H_TxR_AK_INSERTS.SCHED0",
         "PerPkg": "1",
@@ -3499,7 +3166,6 @@
     },
     {
         "BriefDescription": "AK Egress Allocations; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2F",
         "EventName": "UNC_H_TxR_AK_INSERTS.SCHED1",
         "PerPkg": "1",
@@ -3509,7 +3175,6 @@
     },
     {
         "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_H_TxR_BL.DRS_CACHE",
         "PerPkg": "1",
@@ -3519,7 +3184,6 @@
     },
     {
         "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_H_TxR_BL.DRS_CORE",
         "PerPkg": "1",
@@ -3529,7 +3193,6 @@
     },
     {
         "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_H_TxR_BL.DRS_QPI",
         "PerPkg": "1",
@@ -3539,7 +3202,6 @@
     },
     {
         "BriefDescription": "BL Egress Full; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x36",
         "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL",
         "PerPkg": "1",
@@ -3549,7 +3211,6 @@
     },
     {
         "BriefDescription": "BL Egress Full; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x36",
         "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
         "PerPkg": "1",
@@ -3559,7 +3220,6 @@
     },
     {
         "BriefDescription": "BL Egress Full; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x36",
         "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
         "PerPkg": "1",
@@ -3569,7 +3229,6 @@
     },
     {
         "BriefDescription": "BL Egress Not Empty; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL",
         "PerPkg": "1",
@@ -3579,7 +3238,6 @@
     },
     {
         "BriefDescription": "BL Egress Not Empty; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0",
         "PerPkg": "1",
@@ -3589,7 +3247,6 @@
     },
     {
         "BriefDescription": "BL Egress Not Empty; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1",
         "PerPkg": "1",
@@ -3599,7 +3256,6 @@
     },
     {
         "BriefDescription": "BL Egress Allocations; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_H_TxR_BL_INSERTS.ALL",
         "PerPkg": "1",
@@ -3609,7 +3265,6 @@
     },
     {
         "BriefDescription": "BL Egress Allocations; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_H_TxR_BL_INSERTS.SCHED0",
         "PerPkg": "1",
@@ -3619,7 +3274,6 @@
     },
     {
         "BriefDescription": "BL Egress Allocations; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_H_TxR_BL_INSERTS.SCHED1",
         "PerPkg": "1",
@@ -3629,7 +3283,6 @@
     },
     {
         "BriefDescription": "Injection Starvation; For AK Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6D",
         "EventName": "UNC_H_TxR_STARVED.AK",
         "PerPkg": "1",
@@ -3639,7 +3292,6 @@
     },
     {
         "BriefDescription": "Injection Starvation; For BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6D",
         "EventName": "UNC_H_TxR_STARVED.BL",
         "PerPkg": "1",
@@ -3649,7 +3301,6 @@
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
         "PerPkg": "1",
@@ -3659,7 +3310,6 @@
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
         "PerPkg": "1",
@@ -3669,7 +3319,6 @@
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
         "PerPkg": "1",
@@ -3679,7 +3328,6 @@
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
         "PerPkg": "1",
@@ -3689,7 +3337,6 @@
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
         "PerPkg": "1",
@@ -3699,7 +3346,6 @@
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
         "PerPkg": "1",
@@ -3709,7 +3355,6 @@
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
         "PerPkg": "1",
@@ -3719,7 +3364,6 @@
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
         "PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json
index 83ff0542dbc01..c3f2f6c2ac74c 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "DRAM Activate Count; Activate due to Write",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_M_ACT_COUNT.BYP",
         "PerPkg": "1",
@@ -11,7 +10,6 @@
     },
     {
         "BriefDescription": "DRAM Activate Count; Activate due to Read",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_M_ACT_COUNT.RD",
         "PerPkg": "1",
@@ -21,7 +19,6 @@
     },
     {
         "BriefDescription": "DRAM Activate Count; Activate due to Write",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_M_ACT_COUNT.WR",
         "PerPkg": "1",
@@ -31,7 +28,6 @@
     },
     {
         "BriefDescription": "ACT command issued by 2 cycle bypass",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA1",
         "EventName": "UNC_M_BYP_CMDS.ACT",
         "PerPkg": "1",
@@ -40,7 +36,6 @@
     },
     {
         "BriefDescription": "CAS command issued by 2 cycle bypass",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA1",
         "EventName": "UNC_M_BYP_CMDS.CAS",
         "PerPkg": "1",
@@ -49,7 +44,6 @@
     },
     {
         "BriefDescription": "PRE command issued by 2 cycle bypass",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA1",
         "EventName": "UNC_M_BYP_CMDS.PRE",
         "PerPkg": "1",
@@ -58,17 +52,15 @@
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.ALL",
         "PerPkg": "1",
         "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS commands issued on this channel.",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.RD",
         "PerPkg": "1",
@@ -78,7 +70,6 @@
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.RD_REG",
         "PerPkg": "1",
@@ -88,17 +79,14 @@
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.RD_RMM",
         "PerPkg": "1",
-        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
         "UMask": "0x20",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
         "PerPkg": "1",
@@ -108,27 +96,23 @@
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.RD_WMM",
         "PerPkg": "1",
-        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
         "UMask": "0x10",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.WR",
         "PerPkg": "1",
         "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel.",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.WR_RMM",
         "PerPkg": "1",
@@ -138,7 +122,6 @@
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.WR_WMM",
         "PerPkg": "1",
@@ -148,14 +131,12 @@
     },
     {
         "BriefDescription": "DRAM Clockticks",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_M_DCLOCKTICKS",
         "PerPkg": "1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM Precharge All Commands",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_M_DRAM_PRE_ALL",
         "PerPkg": "1",
@@ -164,7 +145,6 @@
     },
     {
         "BriefDescription": "Number of DRAM Refreshes Issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_M_DRAM_REFRESH.HIGH",
         "PerPkg": "1",
@@ -174,7 +154,6 @@
     },
     {
         "BriefDescription": "Number of DRAM Refreshes Issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_M_DRAM_REFRESH.PANIC",
         "PerPkg": "1",
@@ -184,7 +163,6 @@
     },
     {
         "BriefDescription": "ECC Correctable Errors",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
         "PerPkg": "1",
@@ -193,7 +171,6 @@
     },
     {
         "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_M_MAJOR_MODES.ISOCH",
         "PerPkg": "1",
@@ -203,7 +180,6 @@
     },
     {
         "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
         "PerPkg": "1",
@@ -213,7 +189,6 @@
     },
     {
         "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_M_MAJOR_MODES.READ",
         "PerPkg": "1",
@@ -223,7 +198,6 @@
     },
     {
         "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_M_MAJOR_MODES.WRITE",
         "PerPkg": "1",
@@ -233,7 +207,6 @@
     },
     {
         "BriefDescription": "Channel DLLOFF Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x84",
         "EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
         "PerPkg": "1",
@@ -242,7 +215,6 @@
     },
     {
         "BriefDescription": "Channel PPD Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "UNC_M_POWER_CHANNEL_PPD",
         "PerPkg": "1",
@@ -251,7 +223,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
         "PerPkg": "1",
@@ -261,7 +232,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
         "PerPkg": "1",
@@ -271,7 +241,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
         "PerPkg": "1",
@@ -281,7 +250,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
         "PerPkg": "1",
@@ -291,7 +259,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
         "PerPkg": "1",
@@ -301,7 +268,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
         "PerPkg": "1",
@@ -311,7 +277,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
         "PerPkg": "1",
@@ -321,7 +286,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
         "PerPkg": "1",
@@ -331,16 +295,20 @@
     },
     {
         "BriefDescription": "Critical Throttle Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x86",
         "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles when the iMC is in critical thermal throttling.  When this happens, all traffic is blocked.  This should be rare unless something bad is going on in the platform.  There is no filtering by rank for this event.",
         "Unit": "iMC"
     },
+    {
+        "EventCode": "0x42",
+        "EventName": "UNC_M_POWER_PCU_THROTTLING",
+        "PerPkg": "1",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "Clock-Enabled Self-Refresh",
-        "Counter": "0,1,2,3",
         "EventCode": "0x43",
         "EventName": "UNC_M_POWER_SELF_REFRESH",
         "PerPkg": "1",
@@ -349,7 +317,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
         "PerPkg": "1",
@@ -359,7 +326,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
         "PerPkg": "1",
@@ -369,7 +335,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
         "PerPkg": "1",
@@ -379,7 +344,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
         "PerPkg": "1",
@@ -389,7 +353,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
         "PerPkg": "1",
@@ -399,7 +362,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
         "PerPkg": "1",
@@ -409,7 +371,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
         "PerPkg": "1",
@@ -419,7 +380,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
         "PerPkg": "1",
@@ -429,7 +389,6 @@
     },
     {
         "BriefDescription": "Read Preemption Count; Read over Read Preemption",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
         "PerPkg": "1",
@@ -439,7 +398,6 @@
     },
     {
         "BriefDescription": "Read Preemption Count; Read over Write Preemption",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
         "PerPkg": "1",
@@ -449,7 +407,6 @@
     },
     {
         "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_M_PRE_COUNT.BYP",
         "PerPkg": "1",
@@ -459,7 +416,6 @@
     },
     {
         "BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
         "PerPkg": "1",
@@ -469,7 +425,6 @@
     },
     {
         "BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
         "PerPkg": "1",
@@ -479,7 +434,6 @@
     },
     {
         "BriefDescription": "DRAM Precharge commands.; Precharge due to read",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_M_PRE_COUNT.RD",
         "PerPkg": "1",
@@ -489,7 +443,6 @@
     },
     {
         "BriefDescription": "DRAM Precharge commands.; Precharge due to write",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_M_PRE_COUNT.WR",
         "PerPkg": "1",
@@ -499,7 +452,6 @@
     },
     {
         "BriefDescription": "Read CAS issued with HIGH priority",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA0",
         "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
         "PerPkg": "1",
@@ -508,7 +460,6 @@
     },
     {
         "BriefDescription": "Read CAS issued with LOW priority",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA0",
         "EventName": "UNC_M_RD_CAS_PRIO.LOW",
         "PerPkg": "1",
@@ -517,7 +468,6 @@
     },
     {
         "BriefDescription": "Read CAS issued with MEDIUM priority",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA0",
         "EventName": "UNC_M_RD_CAS_PRIO.MED",
         "PerPkg": "1",
@@ -526,7 +476,6 @@
     },
     {
         "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA0",
         "EventName": "UNC_M_RD_CAS_PRIO.PANIC",
         "PerPkg": "1",
@@ -535,7 +484,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
         "PerPkg": "1",
@@ -544,7 +492,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK0",
         "PerPkg": "1",
@@ -552,7 +499,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK1",
         "PerPkg": "1",
@@ -561,61 +507,54 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK10",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK11",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK12",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK13",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 14",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK14",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 15",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK15",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK2",
         "PerPkg": "1",
@@ -624,7 +563,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK3",
         "PerPkg": "1",
@@ -633,7 +571,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK4",
         "PerPkg": "1",
@@ -642,7 +579,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK5",
         "PerPkg": "1",
@@ -651,7 +587,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK6",
         "PerPkg": "1",
@@ -660,7 +595,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK7",
         "PerPkg": "1",
@@ -669,7 +603,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK8",
         "PerPkg": "1",
@@ -678,7 +611,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK9",
         "PerPkg": "1",
@@ -687,7 +619,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANKG0",
         "PerPkg": "1",
@@ -696,7 +627,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANKG1",
         "PerPkg": "1",
@@ -705,7 +635,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANKG2",
         "PerPkg": "1",
@@ -714,7 +643,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANKG3",
         "PerPkg": "1",
@@ -723,7 +651,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; All Banks",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS",
         "PerPkg": "1",
@@ -732,7 +659,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK0",
         "PerPkg": "1",
@@ -740,7 +666,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK1",
         "PerPkg": "1",
@@ -749,61 +674,54 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 10",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK10",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 11",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK11",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 12",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK12",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 13",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK13",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 14",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK14",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 15",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK15",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK2",
         "PerPkg": "1",
@@ -812,7 +730,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK3",
         "PerPkg": "1",
@@ -821,7 +738,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK4",
         "PerPkg": "1",
@@ -830,7 +746,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK5",
         "PerPkg": "1",
@@ -839,7 +754,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK6",
         "PerPkg": "1",
@@ -848,7 +762,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK7",
         "PerPkg": "1",
@@ -857,7 +770,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK8",
         "PerPkg": "1",
@@ -866,7 +778,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK9",
         "PerPkg": "1",
@@ -875,7 +786,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANKG0",
         "PerPkg": "1",
@@ -884,7 +794,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANKG1",
         "PerPkg": "1",
@@ -893,7 +802,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANKG2",
         "PerPkg": "1",
@@ -902,7 +810,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANKG3",
         "PerPkg": "1",
@@ -911,7 +818,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 2; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_M_RD_CAS_RANK2.BANK0",
         "PerPkg": "1",
@@ -919,7 +825,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; All Banks",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS",
         "PerPkg": "1",
@@ -928,7 +833,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK0",
         "PerPkg": "1",
@@ -936,7 +840,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK1",
         "PerPkg": "1",
@@ -945,61 +848,54 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 10",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK10",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 11",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK11",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 12",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK12",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 13",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK13",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 14",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK14",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 15",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK15",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK2",
         "PerPkg": "1",
@@ -1008,7 +904,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK3",
         "PerPkg": "1",
@@ -1017,7 +912,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK4",
         "PerPkg": "1",
@@ -1026,7 +920,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK5",
         "PerPkg": "1",
@@ -1035,7 +928,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK6",
         "PerPkg": "1",
@@ -1044,7 +936,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK7",
         "PerPkg": "1",
@@ -1053,7 +944,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK8",
         "PerPkg": "1",
@@ -1062,7 +952,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK9",
         "PerPkg": "1",
@@ -1071,7 +960,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANKG0",
         "PerPkg": "1",
@@ -1080,7 +968,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANKG1",
         "PerPkg": "1",
@@ -1089,7 +976,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANKG2",
         "PerPkg": "1",
@@ -1098,7 +984,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANKG3",
         "PerPkg": "1",
@@ -1107,7 +992,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; All Banks",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS",
         "PerPkg": "1",
@@ -1116,7 +1000,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK0",
         "PerPkg": "1",
@@ -1124,7 +1007,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK1",
         "PerPkg": "1",
@@ -1133,61 +1015,54 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 10",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK10",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 11",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK11",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 12",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK12",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 13",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK13",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 14",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK14",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 15",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK15",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK2",
         "PerPkg": "1",
@@ -1196,7 +1071,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK3",
         "PerPkg": "1",
@@ -1205,7 +1079,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK4",
         "PerPkg": "1",
@@ -1214,7 +1087,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK5",
         "PerPkg": "1",
@@ -1223,7 +1095,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK6",
         "PerPkg": "1",
@@ -1232,7 +1103,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK7",
         "PerPkg": "1",
@@ -1241,7 +1111,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK8",
         "PerPkg": "1",
@@ -1250,7 +1119,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK9",
         "PerPkg": "1",
@@ -1259,7 +1127,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANKG0",
         "PerPkg": "1",
@@ -1268,7 +1135,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANKG1",
         "PerPkg": "1",
@@ -1277,7 +1143,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANKG2",
         "PerPkg": "1",
@@ -1286,7 +1151,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANKG3",
         "PerPkg": "1",
@@ -1295,7 +1159,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; All Banks",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS",
         "PerPkg": "1",
@@ -1304,7 +1167,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK0",
         "PerPkg": "1",
@@ -1312,7 +1174,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK1",
         "PerPkg": "1",
@@ -1321,61 +1182,54 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 10",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK10",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 11",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK11",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 12",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK12",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 13",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK13",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 14",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK14",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 15",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK15",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK2",
         "PerPkg": "1",
@@ -1384,7 +1238,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK3",
         "PerPkg": "1",
@@ -1393,7 +1246,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK4",
         "PerPkg": "1",
@@ -1402,7 +1254,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK5",
         "PerPkg": "1",
@@ -1411,7 +1262,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK6",
         "PerPkg": "1",
@@ -1420,7 +1270,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK7",
         "PerPkg": "1",
@@ -1429,7 +1278,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK8",
         "PerPkg": "1",
@@ -1438,7 +1286,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK9",
         "PerPkg": "1",
@@ -1447,7 +1294,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANKG0",
         "PerPkg": "1",
@@ -1456,7 +1302,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANKG1",
         "PerPkg": "1",
@@ -1465,7 +1310,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANKG2",
         "PerPkg": "1",
@@ -1474,7 +1318,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANKG3",
         "PerPkg": "1",
@@ -1483,7 +1326,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; All Banks",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS",
         "PerPkg": "1",
@@ -1492,7 +1334,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK0",
         "PerPkg": "1",
@@ -1500,7 +1341,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK1",
         "PerPkg": "1",
@@ -1509,61 +1349,54 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 10",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK10",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK11",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK12",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK13",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK14",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK15",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK2",
         "PerPkg": "1",
@@ -1572,7 +1405,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK3",
         "PerPkg": "1",
@@ -1581,7 +1413,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK4",
         "PerPkg": "1",
@@ -1590,7 +1421,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK5",
         "PerPkg": "1",
@@ -1599,7 +1429,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK6",
         "PerPkg": "1",
@@ -1608,7 +1437,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK7",
         "PerPkg": "1",
@@ -1617,7 +1445,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK8",
         "PerPkg": "1",
@@ -1626,7 +1453,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK9",
         "PerPkg": "1",
@@ -1635,7 +1461,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANKG0",
         "PerPkg": "1",
@@ -1644,7 +1469,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANKG1",
         "PerPkg": "1",
@@ -1653,7 +1477,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANKG2",
         "PerPkg": "1",
@@ -1662,7 +1485,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANKG3",
         "PerPkg": "1",
@@ -1671,7 +1493,6 @@
     },
     {
         "BriefDescription": "Read Pending Queue Not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0x11",
         "EventName": "UNC_M_RPQ_CYCLES_NE",
         "PerPkg": "1",
@@ -1680,7 +1501,6 @@
     },
     {
         "BriefDescription": "Read Pending Queue Allocations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_M_RPQ_INSERTS",
         "PerPkg": "1",
@@ -1689,7 +1509,6 @@
     },
     {
         "BriefDescription": "VMSE MXB write buffer occupancy",
-        "Counter": "0,1,2,3",
         "EventCode": "0x91",
         "EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY",
         "PerPkg": "1",
@@ -1697,7 +1516,6 @@
     },
     {
         "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in RMM",
-        "Counter": "0,1,2,3",
         "EventCode": "0x90",
         "EventName": "UNC_M_VMSE_WR_PUSH.RMM",
         "PerPkg": "1",
@@ -1706,7 +1524,6 @@
     },
     {
         "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in WMM",
-        "Counter": "0,1,2,3",
         "EventCode": "0x90",
         "EventName": "UNC_M_VMSE_WR_PUSH.WMM",
         "PerPkg": "1",
@@ -1715,7 +1532,6 @@
     },
     {
         "BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH",
         "PerPkg": "1",
@@ -1724,7 +1540,6 @@
     },
     {
         "BriefDescription": "Transition from WMM to RMM because of low threshold",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "UNC_M_WMM_TO_RMM.STARVE",
         "PerPkg": "1",
@@ -1733,7 +1548,6 @@
     },
     {
         "BriefDescription": "Transition from WMM to RMM because of low threshold",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY",
         "PerPkg": "1",
@@ -1742,7 +1556,6 @@
     },
     {
         "BriefDescription": "Write Pending Queue Full Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_M_WPQ_CYCLES_FULL",
         "PerPkg": "1",
@@ -1751,7 +1564,6 @@
     },
     {
         "BriefDescription": "Write Pending Queue Not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_M_WPQ_CYCLES_NE",
         "PerPkg": "1",
@@ -1760,7 +1572,6 @@
     },
     {
         "BriefDescription": "Write Pending Queue CAM Match",
-        "Counter": "0,1,2,3",
         "EventCode": "0x23",
         "EventName": "UNC_M_WPQ_READ_HIT",
         "PerPkg": "1",
@@ -1769,7 +1580,6 @@
     },
     {
         "BriefDescription": "Write Pending Queue CAM Match",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_M_WPQ_WRITE_HIT",
         "PerPkg": "1",
@@ -1778,7 +1588,6 @@
     },
     {
         "BriefDescription": "Not getting the requested Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC1",
         "EventName": "UNC_M_WRONG_MM",
         "PerPkg": "1",
@@ -1786,7 +1595,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; All Banks",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
         "PerPkg": "1",
@@ -1795,7 +1603,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK0",
         "PerPkg": "1",
@@ -1803,7 +1610,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK1",
         "PerPkg": "1",
@@ -1812,61 +1618,54 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK10",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK11",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK12",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK13",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 14",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK14",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 15",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK15",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK2",
         "PerPkg": "1",
@@ -1875,7 +1674,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK3",
         "PerPkg": "1",
@@ -1884,7 +1682,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK4",
         "PerPkg": "1",
@@ -1893,7 +1690,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK5",
         "PerPkg": "1",
@@ -1902,7 +1698,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK6",
         "PerPkg": "1",
@@ -1911,7 +1706,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK7",
         "PerPkg": "1",
@@ -1920,7 +1714,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK8",
         "PerPkg": "1",
@@ -1929,7 +1722,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK9",
         "PerPkg": "1",
@@ -1938,7 +1730,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANKG0",
         "PerPkg": "1",
@@ -1947,7 +1738,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANKG1",
         "PerPkg": "1",
@@ -1956,7 +1746,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANKG2",
         "PerPkg": "1",
@@ -1965,7 +1754,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANKG3",
         "PerPkg": "1",
@@ -1974,7 +1762,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; All Banks",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS",
         "PerPkg": "1",
@@ -1983,7 +1770,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK0",
         "PerPkg": "1",
@@ -1991,7 +1777,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK1",
         "PerPkg": "1",
@@ -2000,61 +1785,54 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 10",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK10",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 11",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK11",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 12",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK12",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 13",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK13",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 14",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK14",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 15",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK15",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK2",
         "PerPkg": "1",
@@ -2063,7 +1841,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK3",
         "PerPkg": "1",
@@ -2072,7 +1849,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK4",
         "PerPkg": "1",
@@ -2081,7 +1857,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK5",
         "PerPkg": "1",
@@ -2090,7 +1865,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK6",
         "PerPkg": "1",
@@ -2099,7 +1873,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK7",
         "PerPkg": "1",
@@ -2108,7 +1881,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK8",
         "PerPkg": "1",
@@ -2117,7 +1889,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK9",
         "PerPkg": "1",
@@ -2126,7 +1897,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANKG0",
         "PerPkg": "1",
@@ -2135,7 +1905,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANKG1",
         "PerPkg": "1",
@@ -2144,7 +1913,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANKG2",
         "PerPkg": "1",
@@ -2153,7 +1921,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANKG3",
         "PerPkg": "1",
@@ -2162,7 +1929,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; All Banks",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS",
         "PerPkg": "1",
@@ -2171,7 +1937,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK0",
         "PerPkg": "1",
@@ -2179,7 +1944,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK1",
         "PerPkg": "1",
@@ -2188,61 +1952,54 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 10",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK10",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 11",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK11",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 12",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK12",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 13",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK13",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 14",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK14",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 15",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK15",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK2",
         "PerPkg": "1",
@@ -2251,7 +2008,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK3",
         "PerPkg": "1",
@@ -2260,7 +2016,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK4",
         "PerPkg": "1",
@@ -2269,7 +2024,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK5",
         "PerPkg": "1",
@@ -2278,7 +2032,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK6",
         "PerPkg": "1",
@@ -2287,7 +2040,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK7",
         "PerPkg": "1",
@@ -2296,7 +2048,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK8",
         "PerPkg": "1",
@@ -2305,7 +2056,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK9",
         "PerPkg": "1",
@@ -2314,7 +2064,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANKG0",
         "PerPkg": "1",
@@ -2323,7 +2072,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANKG1",
         "PerPkg": "1",
@@ -2332,7 +2080,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANKG2",
         "PerPkg": "1",
@@ -2341,7 +2088,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANKG3",
         "PerPkg": "1",
@@ -2350,7 +2096,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; All Banks",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS",
         "PerPkg": "1",
@@ -2359,7 +2104,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK0",
         "PerPkg": "1",
@@ -2367,7 +2111,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK1",
         "PerPkg": "1",
@@ -2376,61 +2119,54 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 10",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK10",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 11",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK11",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 12",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK12",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 13",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK13",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 14",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK14",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 15",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK15",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK2",
         "PerPkg": "1",
@@ -2439,7 +2175,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK3",
         "PerPkg": "1",
@@ -2448,7 +2183,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK4",
         "PerPkg": "1",
@@ -2457,7 +2191,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK5",
         "PerPkg": "1",
@@ -2466,7 +2199,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK6",
         "PerPkg": "1",
@@ -2475,7 +2207,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK7",
         "PerPkg": "1",
@@ -2484,7 +2215,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK8",
         "PerPkg": "1",
@@ -2493,7 +2223,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK9",
         "PerPkg": "1",
@@ -2502,7 +2231,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANKG0",
         "PerPkg": "1",
@@ -2511,7 +2239,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANKG1",
         "PerPkg": "1",
@@ -2520,7 +2247,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANKG2",
         "PerPkg": "1",
@@ -2529,7 +2255,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANKG3",
         "PerPkg": "1",
@@ -2538,7 +2263,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; All Banks",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS",
         "PerPkg": "1",
@@ -2547,7 +2271,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK0",
         "PerPkg": "1",
@@ -2555,7 +2278,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK1",
         "PerPkg": "1",
@@ -2564,61 +2286,54 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 10",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK10",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 11",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK11",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 12",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK12",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 13",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK13",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 14",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK14",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 15",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK15",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK2",
         "PerPkg": "1",
@@ -2627,7 +2342,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK3",
         "PerPkg": "1",
@@ -2636,7 +2350,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK4",
         "PerPkg": "1",
@@ -2645,7 +2358,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK5",
         "PerPkg": "1",
@@ -2654,7 +2366,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK6",
         "PerPkg": "1",
@@ -2663,7 +2374,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK7",
         "PerPkg": "1",
@@ -2672,7 +2382,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK8",
         "PerPkg": "1",
@@ -2681,7 +2390,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK9",
         "PerPkg": "1",
@@ -2690,7 +2398,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANKG0",
         "PerPkg": "1",
@@ -2699,7 +2406,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANKG1",
         "PerPkg": "1",
@@ -2708,7 +2414,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANKG2",
         "PerPkg": "1",
@@ -2717,7 +2422,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANKG3",
         "PerPkg": "1",
@@ -2726,7 +2430,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; All Banks",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS",
         "PerPkg": "1",
@@ -2735,7 +2438,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK0",
         "PerPkg": "1",
@@ -2743,7 +2445,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK1",
         "PerPkg": "1",
@@ -2752,61 +2453,54 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 10",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK10",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 11",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK11",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK12",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK13",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK14",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK15",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK2",
         "PerPkg": "1",
@@ -2815,7 +2509,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK3",
         "PerPkg": "1",
@@ -2824,7 +2517,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK4",
         "PerPkg": "1",
@@ -2833,7 +2525,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK5",
         "PerPkg": "1",
@@ -2842,7 +2533,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK6",
         "PerPkg": "1",
@@ -2851,7 +2541,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK7",
         "PerPkg": "1",
@@ -2860,7 +2549,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK8",
         "PerPkg": "1",
@@ -2869,7 +2557,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK9",
         "PerPkg": "1",
@@ -2878,7 +2565,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANKG0",
         "PerPkg": "1",
@@ -2887,7 +2573,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANKG1",
         "PerPkg": "1",
@@ -2896,7 +2581,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANKG2",
         "PerPkg": "1",
@@ -2905,7 +2589,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANKG3",
         "PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json
index fc7e0867fcc5a..753b381b77fe1 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Total Write Cache Occupancy; Any Source",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
         "PerPkg": "1",
@@ -11,7 +10,6 @@
     },
     {
         "BriefDescription": "Total Write Cache Occupancy; Select Source",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
         "PerPkg": "1",
@@ -21,7 +19,6 @@
     },
     {
         "BriefDescription": "Clocks in the IRP",
-        "Counter": "0,1",
         "EventName": "UNC_I_CLOCKTICKS",
         "PerPkg": "1",
         "PublicDescription": "Number of clocks in the IRP.",
@@ -29,7 +26,6 @@
     },
     {
         "BriefDescription": "Coherent Ops; CLFlush",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
         "PerPkg": "1",
@@ -39,7 +35,6 @@
     },
     {
         "BriefDescription": "Coherent Ops; CRd",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_I_COHERENT_OPS.CRD",
         "PerPkg": "1",
@@ -49,7 +44,6 @@
     },
     {
         "BriefDescription": "Coherent Ops; DRd",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_I_COHERENT_OPS.DRD",
         "PerPkg": "1",
@@ -59,7 +53,6 @@
     },
     {
         "BriefDescription": "Coherent Ops; PCIDCAHin5t",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
         "PerPkg": "1",
@@ -69,7 +62,6 @@
     },
     {
         "BriefDescription": "Coherent Ops; PCIRdCur",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
         "PerPkg": "1",
@@ -79,7 +71,6 @@
     },
     {
         "BriefDescription": "Coherent Ops; PCIItoM",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_I_COHERENT_OPS.PCITOM",
         "PerPkg": "1",
@@ -89,7 +80,6 @@
     },
     {
         "BriefDescription": "Coherent Ops; RFO",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_I_COHERENT_OPS.RFO",
         "PerPkg": "1",
@@ -99,7 +89,6 @@
     },
     {
         "BriefDescription": "Coherent Ops; WbMtoI",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
         "PerPkg": "1",
@@ -109,7 +98,6 @@
     },
     {
         "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
         "PerPkg": "1",
@@ -118,7 +106,6 @@
     },
     {
         "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
         "PerPkg": "1",
@@ -127,7 +114,6 @@
     },
     {
         "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
         "PerPkg": "1",
@@ -136,7 +122,6 @@
     },
     {
         "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_I_MISC0.FAST_REJ",
         "PerPkg": "1",
@@ -145,7 +130,6 @@
     },
     {
         "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_I_MISC0.FAST_REQ",
         "PerPkg": "1",
@@ -154,7 +138,6 @@
     },
     {
         "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_I_MISC0.FAST_XFER",
         "PerPkg": "1",
@@ -163,7 +146,6 @@
     },
     {
         "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_I_MISC0.PF_ACK_HINT",
         "PerPkg": "1",
@@ -172,7 +154,6 @@
     },
     {
         "BriefDescription": "Misc Events - Set 0; Prefetch TimeOut",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_I_MISC0.PF_TIMEOUT",
         "PerPkg": "1",
@@ -182,7 +163,6 @@
     },
     {
         "BriefDescription": "Misc Events - Set 1; Data Throttled",
-        "Counter": "0,1",
         "EventCode": "0x15",
         "EventName": "UNC_I_MISC1.DATA_THROTTLE",
         "PerPkg": "1",
@@ -192,7 +172,6 @@
     },
     {
         "BriefDescription": "Misc Events - Set 1",
-        "Counter": "0,1",
         "EventCode": "0x15",
         "EventName": "UNC_I_MISC1.LOST_FWD",
         "PerPkg": "1",
@@ -201,7 +180,6 @@
     },
     {
         "BriefDescription": "Misc Events - Set 1; Received Invalid",
-        "Counter": "0,1",
         "EventCode": "0x15",
         "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
         "PerPkg": "1",
@@ -211,7 +189,6 @@
     },
     {
         "BriefDescription": "Misc Events - Set 1; Received Valid",
-        "Counter": "0,1",
         "EventCode": "0x15",
         "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
         "PerPkg": "1",
@@ -221,7 +198,6 @@
     },
     {
         "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
-        "Counter": "0,1",
         "EventCode": "0x15",
         "EventName": "UNC_I_MISC1.SLOW_E",
         "PerPkg": "1",
@@ -231,7 +207,6 @@
     },
     {
         "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
-        "Counter": "0,1",
         "EventCode": "0x15",
         "EventName": "UNC_I_MISC1.SLOW_I",
         "PerPkg": "1",
@@ -241,7 +216,6 @@
     },
     {
         "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
-        "Counter": "0,1",
         "EventCode": "0x15",
         "EventName": "UNC_I_MISC1.SLOW_M",
         "PerPkg": "1",
@@ -251,7 +225,6 @@
     },
     {
         "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
-        "Counter": "0,1",
         "EventCode": "0x15",
         "EventName": "UNC_I_MISC1.SLOW_S",
         "PerPkg": "1",
@@ -261,7 +234,6 @@
     },
     {
         "BriefDescription": "AK Ingress Occupancy",
-        "Counter": "0,1",
         "EventCode": "0xA",
         "EventName": "UNC_I_RxR_AK_INSERTS",
         "PerPkg": "1",
@@ -269,7 +241,6 @@
         "Unit": "IRP"
     },
     {
-        "Counter": "0,1",
         "EventCode": "0x4",
         "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
         "PerPkg": "1",
@@ -278,7 +249,6 @@
     },
     {
         "BriefDescription": "BL Ingress Occupancy - DRS",
-        "Counter": "0,1",
         "EventCode": "0x1",
         "EventName": "UNC_I_RxR_BL_DRS_INSERTS",
         "PerPkg": "1",
@@ -286,7 +256,6 @@
         "Unit": "IRP"
     },
     {
-        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY",
         "PerPkg": "1",
@@ -294,7 +263,6 @@
         "Unit": "IRP"
     },
     {
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
         "PerPkg": "1",
@@ -303,7 +271,6 @@
     },
     {
         "BriefDescription": "BL Ingress Occupancy - NCB",
-        "Counter": "0,1",
         "EventCode": "0x2",
         "EventName": "UNC_I_RxR_BL_NCB_INSERTS",
         "PerPkg": "1",
@@ -311,7 +278,6 @@
         "Unit": "IRP"
     },
     {
-        "Counter": "0,1",
         "EventCode": "0x8",
         "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY",
         "PerPkg": "1",
@@ -319,7 +285,6 @@
         "Unit": "IRP"
     },
     {
-        "Counter": "0,1",
         "EventCode": "0x6",
         "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
         "PerPkg": "1",
@@ -328,7 +293,6 @@
     },
     {
         "BriefDescription": "BL Ingress Occupancy - NCS",
-        "Counter": "0,1",
         "EventCode": "0x3",
         "EventName": "UNC_I_RxR_BL_NCS_INSERTS",
         "PerPkg": "1",
@@ -336,7 +300,6 @@
         "Unit": "IRP"
     },
     {
-        "Counter": "0,1",
         "EventCode": "0x9",
         "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY",
         "PerPkg": "1",
@@ -345,7 +308,6 @@
     },
     {
         "BriefDescription": "Snoop Responses; Hit E or S",
-        "Counter": "0,1",
         "EventCode": "0x17",
         "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
         "PerPkg": "1",
@@ -354,7 +316,6 @@
     },
     {
         "BriefDescription": "Snoop Responses; Hit I",
-        "Counter": "0,1",
         "EventCode": "0x17",
         "EventName": "UNC_I_SNOOP_RESP.HIT_I",
         "PerPkg": "1",
@@ -363,7 +324,6 @@
     },
     {
         "BriefDescription": "Snoop Responses; Hit M",
-        "Counter": "0,1",
         "EventCode": "0x17",
         "EventName": "UNC_I_SNOOP_RESP.HIT_M",
         "PerPkg": "1",
@@ -372,7 +332,6 @@
     },
     {
         "BriefDescription": "Snoop Responses; Miss",
-        "Counter": "0,1",
         "EventCode": "0x17",
         "EventName": "UNC_I_SNOOP_RESP.MISS",
         "PerPkg": "1",
@@ -381,7 +340,6 @@
     },
     {
         "BriefDescription": "Snoop Responses; SnpCode",
-        "Counter": "0,1",
         "EventCode": "0x17",
         "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
         "PerPkg": "1",
@@ -390,7 +348,6 @@
     },
     {
         "BriefDescription": "Snoop Responses; SnpData",
-        "Counter": "0,1",
         "EventCode": "0x17",
         "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
         "PerPkg": "1",
@@ -399,7 +356,6 @@
     },
     {
         "BriefDescription": "Snoop Responses; SnpInv",
-        "Counter": "0,1",
         "EventCode": "0x17",
         "EventName": "UNC_I_SNOOP_RESP.SNPINV",
         "PerPkg": "1",
@@ -408,7 +364,6 @@
     },
     {
         "BriefDescription": "Inbound Transaction Count; Atomic",
-        "Counter": "0,1",
         "EventCode": "0x16",
         "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
         "PerPkg": "1",
@@ -418,7 +373,6 @@
     },
     {
         "BriefDescription": "Inbound Transaction Count; Other",
-        "Counter": "0,1",
         "EventCode": "0x16",
         "EventName": "UNC_I_TRANSACTIONS.OTHER",
         "PerPkg": "1",
@@ -428,7 +382,6 @@
     },
     {
         "BriefDescription": "Inbound Transaction Count; Read Prefetches",
-        "Counter": "0,1",
         "EventCode": "0x16",
         "EventName": "UNC_I_TRANSACTIONS.RD_PREF",
         "PerPkg": "1",
@@ -438,7 +391,6 @@
     },
     {
         "BriefDescription": "Inbound Transaction Count; Reads",
-        "Counter": "0,1",
         "EventCode": "0x16",
         "EventName": "UNC_I_TRANSACTIONS.READS",
         "PerPkg": "1",
@@ -448,7 +400,6 @@
     },
     {
         "BriefDescription": "Inbound Transaction Count; Writes",
-        "Counter": "0,1",
         "EventCode": "0x16",
         "EventName": "UNC_I_TRANSACTIONS.WRITES",
         "PerPkg": "1",
@@ -458,7 +409,6 @@
     },
     {
         "BriefDescription": "Inbound Transaction Count; Write Prefetches",
-        "Counter": "0,1",
         "EventCode": "0x16",
         "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
         "PerPkg": "1",
@@ -468,7 +418,6 @@
     },
     {
         "BriefDescription": "No AD Egress Credit Stalls",
-        "Counter": "0,1",
         "EventCode": "0x18",
         "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
         "PerPkg": "1",
@@ -477,7 +426,6 @@
     },
     {
         "BriefDescription": "No BL Egress Credit Stalls",
-        "Counter": "0,1",
         "EventCode": "0x19",
         "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
         "PerPkg": "1",
@@ -486,7 +434,6 @@
     },
     {
         "BriefDescription": "Outbound Read Requests",
-        "Counter": "0,1",
         "EventCode": "0xE",
         "EventName": "UNC_I_TxR_DATA_INSERTS_NCB",
         "PerPkg": "1",
@@ -495,7 +442,6 @@
     },
     {
         "BriefDescription": "Outbound Read Requests",
-        "Counter": "0,1",
         "EventCode": "0xF",
         "EventName": "UNC_I_TxR_DATA_INSERTS_NCS",
         "PerPkg": "1",
@@ -504,7 +450,6 @@
     },
     {
         "BriefDescription": "Outbound Request Queue Occupancy",
-        "Counter": "0,1",
         "EventCode": "0xD",
         "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY",
         "PerPkg": "1",
@@ -513,16 +458,42 @@
     },
     {
         "BriefDescription": "Number of uclks in domain",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_R2_CLOCKTICKS",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of uclks in the R2PCIe uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
         "Unit": "R2PCIe"
     },
+    {
+        "EventCode": "0x2D",
+        "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "R2PCIe"
+    },
+    {
+        "EventCode": "0x2D",
+        "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "R2PCIe"
+    },
+    {
+        "EventCode": "0x2D",
+        "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "R2PCIe"
+    },
+    {
+        "EventCode": "0x2D",
+        "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "R2PCIe"
+    },
     {
         "BriefDescription": "R2PCIe IIO Credit Acquired; DRS",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
         "PerPkg": "1",
@@ -532,7 +503,6 @@
     },
     {
         "BriefDescription": "R2PCIe IIO Credit Acquired; NCB",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
         "PerPkg": "1",
@@ -542,7 +512,6 @@
     },
     {
         "BriefDescription": "R2PCIe IIO Credit Acquired; NCS",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
         "PerPkg": "1",
@@ -552,7 +521,6 @@
     },
     {
         "BriefDescription": "R2PCIe IIO Credits in Use; DRS",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_R2_IIO_CREDITS_USED.DRS",
         "PerPkg": "1",
@@ -562,7 +530,6 @@
     },
     {
         "BriefDescription": "R2PCIe IIO Credits in Use; NCB",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_R2_IIO_CREDITS_USED.NCB",
         "PerPkg": "1",
@@ -572,7 +539,6 @@
     },
     {
         "BriefDescription": "R2PCIe IIO Credits in Use; NCS",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_R2_IIO_CREDITS_USED.NCS",
         "PerPkg": "1",
@@ -582,27 +548,24 @@
     },
     {
         "BriefDescription": "R2 AD Ring in Use; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.ALL",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CCW_EVEN",
         "PerPkg": "1",
@@ -612,7 +575,6 @@
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CCW_ODD",
         "PerPkg": "1",
@@ -622,7 +584,6 @@
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CW",
         "PerPkg": "1",
@@ -632,7 +593,6 @@
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CW_EVEN",
         "PerPkg": "1",
@@ -642,7 +602,6 @@
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CW_ODD",
         "PerPkg": "1",
@@ -652,7 +611,6 @@
     },
     {
         "BriefDescription": "AK Ingress Bounced; Dn",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_R2_RING_AK_BOUNCES.DN",
         "PerPkg": "1",
@@ -662,7 +620,6 @@
     },
     {
         "BriefDescription": "AK Ingress Bounced; Up",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_R2_RING_AK_BOUNCES.UP",
         "PerPkg": "1",
@@ -672,27 +629,24 @@
     },
     {
         "BriefDescription": "R2 AK Ring in Use; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.ALL",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CCW_EVEN",
         "PerPkg": "1",
@@ -702,7 +656,6 @@
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CCW_ODD",
         "PerPkg": "1",
@@ -712,7 +665,6 @@
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CW",
         "PerPkg": "1",
@@ -722,7 +674,6 @@
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CW_EVEN",
         "PerPkg": "1",
@@ -732,7 +683,6 @@
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CW_ODD",
         "PerPkg": "1",
@@ -742,27 +692,24 @@
     },
     {
         "BriefDescription": "R2 BL Ring in Use; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.ALL",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CCW_EVEN",
         "PerPkg": "1",
@@ -772,7 +719,6 @@
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CCW_ODD",
         "PerPkg": "1",
@@ -782,7 +728,6 @@
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CW",
         "PerPkg": "1",
@@ -792,7 +737,6 @@
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CW_EVEN",
         "PerPkg": "1",
@@ -802,7 +746,6 @@
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CW_ODD",
         "PerPkg": "1",
@@ -812,27 +755,24 @@
     },
     {
         "BriefDescription": "R2 IV Ring in Use; Any",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_R2_RING_IV_USED.ANY",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 IV Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_R2_RING_IV_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 IV Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_R2_RING_IV_USED.CW",
         "PerPkg": "1",
@@ -842,7 +782,6 @@
     },
     {
         "BriefDescription": "Ingress Cycles Not Empty; NCB",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R2_RxR_CYCLES_NE.NCB",
         "PerPkg": "1",
@@ -852,7 +791,6 @@
     },
     {
         "BriefDescription": "Ingress Cycles Not Empty; NCS",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R2_RxR_CYCLES_NE.NCS",
         "PerPkg": "1",
@@ -862,7 +800,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; NCB",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R2_RxR_INSERTS.NCB",
         "PerPkg": "1",
@@ -872,7 +809,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; NCS",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R2_RxR_INSERTS.NCS",
         "PerPkg": "1",
@@ -891,7 +827,6 @@
     },
     {
         "BriefDescription": "SBo0 Credits Acquired; For AD Ring",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.AD",
         "PerPkg": "1",
@@ -901,7 +836,6 @@
     },
     {
         "BriefDescription": "SBo0 Credits Acquired; For BL Ring",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.BL",
         "PerPkg": "1",
@@ -929,7 +863,6 @@
     },
     {
         "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
-        "Counter": "0,1",
         "EventCode": "0x2C",
         "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD",
         "PerPkg": "1",
@@ -939,7 +872,6 @@
     },
     {
         "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
-        "Counter": "0,1",
         "EventCode": "0x2C",
         "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL",
         "PerPkg": "1",
@@ -949,7 +881,6 @@
     },
     {
         "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
-        "Counter": "0,1",
         "EventCode": "0x2C",
         "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD",
         "PerPkg": "1",
@@ -959,7 +890,6 @@
     },
     {
         "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
-        "Counter": "0,1",
         "EventCode": "0x2C",
         "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL",
         "PerPkg": "1",
@@ -1023,7 +953,6 @@
     },
     {
         "BriefDescription": "Egress CCW NACK; AD CCW",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R2_TxR_NACK_CW.DN_AD",
         "PerPkg": "1",
@@ -1033,7 +962,6 @@
     },
     {
         "BriefDescription": "Egress CCW NACK; AK CCW",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R2_TxR_NACK_CW.DN_AK",
         "PerPkg": "1",
@@ -1043,7 +971,6 @@
     },
     {
         "BriefDescription": "Egress CCW NACK; BL CCW",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R2_TxR_NACK_CW.DN_BL",
         "PerPkg": "1",
@@ -1053,7 +980,6 @@
     },
     {
         "BriefDescription": "Egress CCW NACK; AK CCW",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R2_TxR_NACK_CW.UP_AD",
         "PerPkg": "1",
@@ -1063,7 +989,6 @@
     },
     {
         "BriefDescription": "Egress CCW NACK; BL CW",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R2_TxR_NACK_CW.UP_AK",
         "PerPkg": "1",
@@ -1073,7 +998,6 @@
     },
     {
         "BriefDescription": "Egress CCW NACK; BL CCW",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R2_TxR_NACK_CW.UP_BL",
         "PerPkg": "1",
@@ -1083,7 +1007,6 @@
     },
     {
         "BriefDescription": "VLW Received",
-        "Counter": "0,1",
         "EventCode": "0x42",
         "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
         "PerPkg": "1",
@@ -1093,7 +1016,6 @@
     },
     {
         "BriefDescription": "Filter Match",
-        "Counter": "0,1",
         "EventCode": "0x41",
         "EventName": "UNC_U_FILTER_MATCH.DISABLE",
         "PerPkg": "1",
@@ -1103,7 +1025,6 @@
     },
     {
         "BriefDescription": "Filter Match",
-        "Counter": "0,1",
         "EventCode": "0x41",
         "EventName": "UNC_U_FILTER_MATCH.ENABLE",
         "PerPkg": "1",
@@ -1113,7 +1034,6 @@
     },
     {
         "BriefDescription": "Filter Match",
-        "Counter": "0,1",
         "EventCode": "0x41",
         "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
         "PerPkg": "1",
@@ -1123,7 +1043,6 @@
     },
     {
         "BriefDescription": "Filter Match",
-        "Counter": "0,1",
         "EventCode": "0x41",
         "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE",
         "PerPkg": "1",
@@ -1133,7 +1052,6 @@
     },
     {
         "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
-        "Counter": "0,1",
         "EventCode": "0x45",
         "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
         "PerPkg": "1",
@@ -1143,7 +1061,6 @@
     },
     {
         "BriefDescription": "RACU Request",
-        "Counter": "0,1",
         "EventCode": "0x46",
         "EventName": "UNC_U_RACU_REQUESTS",
         "PerPkg": "1",
@@ -1152,7 +1069,6 @@
     },
     {
         "BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.CMC",
         "PerPkg": "1",
@@ -1162,7 +1078,6 @@
     },
     {
         "BriefDescription": "Monitor Sent to T0; Livelock",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.LIVELOCK",
         "PerPkg": "1",
@@ -1172,7 +1087,6 @@
     },
     {
         "BriefDescription": "Monitor Sent to T0; LTError",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.LTERROR",
         "PerPkg": "1",
@@ -1182,7 +1096,6 @@
     },
     {
         "BriefDescription": "Monitor Sent to T0; Monitor T0",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
         "PerPkg": "1",
@@ -1192,7 +1105,6 @@
     },
     {
         "BriefDescription": "Monitor Sent to T0; Monitor T1",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
         "PerPkg": "1",
@@ -1202,7 +1114,6 @@
     },
     {
         "BriefDescription": "Monitor Sent to T0; Other",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.OTHER",
         "PerPkg": "1",
@@ -1212,7 +1123,6 @@
     },
     {
         "BriefDescription": "Monitor Sent to T0; Trap",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.TRAP",
         "PerPkg": "1",
@@ -1222,7 +1132,6 @@
     },
     {
         "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.UMC",
         "PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json
index c3325dd612020..124b3fe2e0e13 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "pclk Cycles",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_P_CLOCKTICKS",
         "PerPkg": "1",
         "PublicDescription": "The PCU runs off a fixed 1 GHz clock.  This event counts the number of pclk cycles measured while the counter was enabled.  The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_P_CORE0_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -18,7 +16,6 @@
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6A",
         "EventName": "UNC_P_CORE10_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -27,7 +24,6 @@
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6B",
         "EventName": "UNC_P_CORE11_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -36,7 +32,6 @@
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6C",
         "EventName": "UNC_P_CORE12_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -45,7 +40,6 @@
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6D",
         "EventName": "UNC_P_CORE13_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -54,7 +48,6 @@
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6E",
         "EventName": "UNC_P_CORE14_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -63,7 +56,6 @@
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6F",
         "EventName": "UNC_P_CORE15_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -72,7 +64,6 @@
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x70",
         "EventName": "UNC_P_CORE16_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -81,7 +72,6 @@
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "UNC_P_CORE17_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -90,7 +80,6 @@
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x61",
         "EventName": "UNC_P_CORE1_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -99,7 +88,6 @@
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x62",
         "EventName": "UNC_P_CORE2_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -108,7 +96,6 @@
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x63",
         "EventName": "UNC_P_CORE3_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -117,7 +104,6 @@
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x64",
         "EventName": "UNC_P_CORE4_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -126,7 +112,6 @@
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x65",
         "EventName": "UNC_P_CORE5_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -135,7 +120,6 @@
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x66",
         "EventName": "UNC_P_CORE6_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -144,7 +128,6 @@
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x67",
         "EventName": "UNC_P_CORE7_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -153,7 +136,6 @@
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x68",
         "EventName": "UNC_P_CORE8_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -162,7 +144,6 @@
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x69",
         "EventName": "UNC_P_CORE9_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -171,7 +152,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x30",
         "EventName": "UNC_P_DEMOTIONS_CORE0",
         "PerPkg": "1",
@@ -180,7 +160,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_P_DEMOTIONS_CORE1",
         "PerPkg": "1",
@@ -189,7 +168,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3A",
         "EventName": "UNC_P_DEMOTIONS_CORE10",
         "PerPkg": "1",
@@ -198,7 +176,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3B",
         "EventName": "UNC_P_DEMOTIONS_CORE11",
         "PerPkg": "1",
@@ -207,7 +184,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "UNC_P_DEMOTIONS_CORE12",
         "PerPkg": "1",
@@ -216,7 +192,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3D",
         "EventName": "UNC_P_DEMOTIONS_CORE13",
         "PerPkg": "1",
@@ -225,7 +200,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3E",
         "EventName": "UNC_P_DEMOTIONS_CORE14",
         "PerPkg": "1",
@@ -234,7 +208,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3F",
         "EventName": "UNC_P_DEMOTIONS_CORE15",
         "PerPkg": "1",
@@ -243,7 +216,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_P_DEMOTIONS_CORE16",
         "PerPkg": "1",
@@ -252,7 +224,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_P_DEMOTIONS_CORE17",
         "PerPkg": "1",
@@ -261,7 +232,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_P_DEMOTIONS_CORE2",
         "PerPkg": "1",
@@ -270,7 +240,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_P_DEMOTIONS_CORE3",
         "PerPkg": "1",
@@ -279,7 +248,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "UNC_P_DEMOTIONS_CORE4",
         "PerPkg": "1",
@@ -288,7 +256,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_P_DEMOTIONS_CORE5",
         "PerPkg": "1",
@@ -297,7 +264,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x36",
         "EventName": "UNC_P_DEMOTIONS_CORE6",
         "PerPkg": "1",
@@ -306,7 +272,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x37",
         "EventName": "UNC_P_DEMOTIONS_CORE7",
         "PerPkg": "1",
@@ -315,7 +280,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x38",
         "EventName": "UNC_P_DEMOTIONS_CORE8",
         "PerPkg": "1",
@@ -324,7 +288,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_P_DEMOTIONS_CORE9",
         "PerPkg": "1",
@@ -333,7 +296,6 @@
     },
     {
         "BriefDescription": "Thermal Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
         "PerPkg": "1",
@@ -342,7 +304,6 @@
     },
     {
         "BriefDescription": "OS Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_P_FREQ_MAX_OS_CYCLES",
         "PerPkg": "1",
@@ -351,7 +312,6 @@
     },
     {
         "BriefDescription": "Power Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
         "PerPkg": "1",
@@ -360,7 +320,6 @@
     },
     {
         "BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x73",
         "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
         "PerPkg": "1",
@@ -369,7 +328,6 @@
     },
     {
         "BriefDescription": "Cycles spent changing Frequency",
-        "Counter": "0,1,2,3",
         "EventCode": "0x74",
         "EventName": "UNC_P_FREQ_TRANS_CYCLES",
         "PerPkg": "1",
@@ -378,7 +336,6 @@
     },
     {
         "BriefDescription": "Memory Phase Shedding Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2F",
         "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
         "PerPkg": "1",
@@ -387,7 +344,6 @@
     },
     {
         "BriefDescription": "Package C State Residency - C0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
         "PerPkg": "1",
@@ -396,7 +352,6 @@
     },
     {
         "BriefDescription": "Package C State Residency - C1E",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4E",
         "EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES",
         "PerPkg": "1",
@@ -405,7 +360,6 @@
     },
     {
         "BriefDescription": "Package C State Residency - C2E",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2B",
         "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
         "PerPkg": "1",
@@ -414,7 +368,6 @@
     },
     {
         "BriefDescription": "Package C State Residency - C3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2C",
         "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
         "PerPkg": "1",
@@ -423,7 +376,6 @@
     },
     {
         "BriefDescription": "Package C State Residency - C6",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2D",
         "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
         "PerPkg": "1",
@@ -432,7 +384,6 @@
     },
     {
         "BriefDescription": "Package C7 State Residency",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES",
         "PerPkg": "1",
@@ -441,7 +392,6 @@
     },
     {
         "BriefDescription": "Number of cores in C-State; C0 and C1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
         "PerPkg": "1",
@@ -450,7 +400,6 @@
     },
     {
         "BriefDescription": "Number of cores in C-State; C3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
         "PerPkg": "1",
@@ -459,7 +408,6 @@
     },
     {
         "BriefDescription": "Number of cores in C-State; C6 and C7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
         "PerPkg": "1",
@@ -468,7 +416,6 @@
     },
     {
         "BriefDescription": "External Prochot",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
         "PerPkg": "1",
@@ -477,7 +424,6 @@
     },
     {
         "BriefDescription": "Internal Prochot",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
         "PerPkg": "1",
@@ -486,7 +432,6 @@
     },
     {
         "BriefDescription": "Total Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x72",
         "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -494,7 +439,6 @@
         "Unit": "PCU"
     },
     {
-        "Counter": "0,1,2,3",
         "EventCode": "0x79",
         "EventName": "UNC_P_UFS_TRANSITIONS_RING_GV",
         "PerPkg": "1",
@@ -503,7 +447,6 @@
     },
     {
         "BriefDescription": "VR Hot",
-        "Counter": "0,1,2,3",
         "EventCode": "0x42",
         "EventName": "UNC_P_VR_HOT_CYCLES",
         "PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json b/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json
index 6a6de8790f25f..93621e004d88f 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Load misses in all DTLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
@@ -12,8 +10,6 @@
     },
     {
         "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
         "SampleAfterValue": "2000003",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (2M).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
         "SampleAfterValue": "2000003",
@@ -30,8 +24,6 @@
     },
     {
         "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (4K).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
         "SampleAfterValue": "2000003",
@@ -39,8 +31,6 @@
     },
     {
         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
@@ -49,8 +39,6 @@
     },
     {
         "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
@@ -60,8 +48,6 @@
     },
     {
         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
@@ -71,8 +57,6 @@
     },
     {
         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
@@ -82,8 +66,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
@@ -93,8 +75,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
@@ -104,8 +84,6 @@
     },
     {
         "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT",
         "SampleAfterValue": "100003",
@@ -113,8 +91,6 @@
     },
     {
         "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (2M).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
         "SampleAfterValue": "100003",
@@ -122,8 +98,6 @@
     },
     {
         "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (4K).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
         "SampleAfterValue": "100003",
@@ -131,8 +105,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
@@ -141,8 +113,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
@@ -152,8 +122,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
@@ -163,8 +131,6 @@
     },
     {
         "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
@@ -174,8 +140,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_DURATION",
@@ -185,8 +149,6 @@
     },
     {
         "BriefDescription": "Cycle count for an Extended Page table walk.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4F",
         "EventName": "EPT.WALK_CYCLES",
         "PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.",
@@ -195,8 +157,6 @@
     },
     {
         "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAE",
         "EventName": "ITLB.ITLB_FLUSH",
         "PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
@@ -205,8 +165,6 @@
     },
     {
         "BriefDescription": "Misses at all ITLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
@@ -216,8 +174,6 @@
     },
     {
         "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT",
         "SampleAfterValue": "100003",
@@ -225,8 +181,6 @@
     },
     {
         "BriefDescription": "Code misses that miss the  DTLB and hit the STLB (2M).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT_2M",
         "SampleAfterValue": "100003",
@@ -234,8 +188,6 @@
     },
     {
         "BriefDescription": "Core misses that miss the  DTLB and hit the STLB (4K).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT_4K",
         "SampleAfterValue": "100003",
@@ -243,8 +195,6 @@
     },
     {
         "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
@@ -253,8 +203,6 @@
     },
     {
         "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
@@ -264,8 +212,6 @@
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
@@ -275,8 +221,6 @@
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
@@ -286,8 +230,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_DURATION",
@@ -297,8 +239,6 @@
     },
     {
         "BriefDescription": "Number of DTLB page walker hits in the L1+FB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDM69, BDM98",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.DTLB_L1",
@@ -307,8 +247,6 @@
     },
     {
         "BriefDescription": "Number of DTLB page walker hits in the L2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDM69, BDM98",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.DTLB_L2",
@@ -317,8 +255,6 @@
     },
     {
         "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDM69, BDM98",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.DTLB_L3",
@@ -327,8 +263,6 @@
     },
     {
         "BriefDescription": "Number of DTLB page walker hits in Memory.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDM69, BDM98",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
@@ -337,8 +271,6 @@
     },
     {
         "BriefDescription": "Number of ITLB page walker hits in the L1+FB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDM69, BDM98",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.ITLB_L1",
@@ -347,8 +279,6 @@
     },
     {
         "BriefDescription": "Number of ITLB page walker hits in the L2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDM69, BDM98",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.ITLB_L2",
@@ -357,8 +287,6 @@
     },
     {
         "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDM69, BDM98",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.ITLB_L3",
@@ -367,8 +295,6 @@
     },
     {
         "BriefDescription": "DTLB flush attempts of the thread-specific entries",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.DTLB_THREAD",
         "PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.",
@@ -377,8 +303,6 @@
     },
     {
         "BriefDescription": "STLB flush attempts",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.STLB_ANY",
         "PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).",
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index df47462a125ff..8949b58f89be9 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -3,7 +3,7 @@ GenuineIntel-6-(97|9A|B7|BA|BF),v1.16,alderlake,core
 GenuineIntel-6-BE,v1.16,alderlaken,core
 GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core
 GenuineIntel-6-(3D|47),v26,broadwell,core
-GenuineIntel-6-56,v23,broadwellde,core
+GenuineIntel-6-56,v7,broadwellde,core
 GenuineIntel-6-4F,v19,broadwellx,core
 GenuineIntel-6-55-[56789ABCDEF],v1.16,cascadelakex,core
 GenuineIntel-6-9[6C],v1.03,elkhartlake,core
-- 
GitLab


From 5e241aad62057b5b3a4fe8bd6ed2fdd906d38a90 Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:49:52 -0800
Subject: [PATCH 569/875] perf vendor events intel: Refresh broadwellx metrics
 and events

Update the broadwellx metrics and events using the new tooling from:

  https://github.com/intel/perfmon

The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
order of metrics varies as TMA metrics are first converted and then
removed if perfmon versions are found. The events are updated with
fixes to uncore events and improved descriptions. The formatting
changes increase consistency across the json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065017.1621020-2-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../arch/x86/broadwellx/bdx-metrics.json      | 1703 ++++----
 .../pmu-events/arch/x86/broadwellx/cache.json |  191 -
 .../arch/x86/broadwellx/floating-point.json   |   40 -
 .../arch/x86/broadwellx/frontend.json         |   56 -
 .../arch/x86/broadwellx/memory.json           |  143 -
 .../pmu-events/arch/x86/broadwellx/other.json |    8 -
 .../arch/x86/broadwellx/pipeline.json         |  272 --
 .../arch/x86/broadwellx/uncore-cache.json     | 3740 ++++++++---------
 .../x86/broadwellx/uncore-interconnect.json   | 1225 +++---
 .../arch/x86/broadwellx/uncore-memory.json    | 2052 +++++----
 .../arch/x86/broadwellx/uncore-other.json     | 2410 ++++++-----
 .../arch/x86/broadwellx/uncore-power.json     |  198 +-
 .../arch/x86/broadwellx/virtual-memory.json   |   76 -
 13 files changed, 5577 insertions(+), 6537 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json b/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json
index e89fa536ca030..f5c8f707c6924 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json
@@ -1,1206 +1,1189 @@
 [
     {
-        "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
-        "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS",
-        "MetricGroup": "PGO;TopdownL1;tma_L1_group",
-        "MetricName": "tma_frontend_bound",
-        "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
+        "MetricExpr": "INST_RETIRED.ANY / CLKS",
+        "MetricGroup": "Ret;Summary",
+        "MetricName": "IPC"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
-        "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS",
-        "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
-        "MetricName": "tma_fetch_latency",
-        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Uops Per Instruction",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
+        "MetricGroup": "Pipeline;Ret;Retire",
+        "MetricName": "UPI"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.",
-        "MetricExpr": "ICACHE.IFDATA_STALL / CLKS",
-        "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_icache_misses",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instruction per taken branch",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
+        "MetricGroup": "Branches;Fed;FetchBW",
+        "MetricName": "UpTB"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses",
-        "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * ITLB_MISSES.WALK_COMPLETED) / CLKS",
-        "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_itlb_misses",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
+        "MetricExpr": "1 / IPC",
+        "MetricGroup": "Mem;Pipeline",
+        "MetricName": "CPI"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
-        "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / CLKS",
-        "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_branch_resteers",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "Pipeline",
+        "MetricName": "CLKS"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ",
-        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)",
-        "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group",
-        "MetricName": "tma_mispredicts_resteers",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
+        "MetricExpr": "4 * CORE_CLKS",
+        "MetricGroup": "tma_L1_group",
+        "MetricName": "SLOTS"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ",
-        "MetricExpr": "MACHINE_CLEARS.COUNT * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)",
-        "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group",
-        "MetricName": "tma_clears_resteers",
-        "ScaleUnit": "100%"
+        "BriefDescription": "The ratio of Executed- by Issued-Uops",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
+        "MetricGroup": "Cor;Pipeline",
+        "MetricName": "Execute_per_Issue",
+        "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
-        "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers",
-        "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_branch_resteers_group",
-        "MetricName": "tma_unknown_branches",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: BACLEARS.ANY",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
+        "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
+        "MetricGroup": "Ret;SMT;tma_L1_group",
+        "MetricName": "CoreIPC"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
-        "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS",
-        "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_dsb_switches",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Floating Point Operations Per Cycle",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
+        "MetricGroup": "Flops;Ret",
+        "MetricName": "FLOPc"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
-        "MetricExpr": "ILD_STALL.LCP / CLKS",
-        "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_lcp",
-        "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
+        "MetricGroup": "Cor;Flops;HPC",
+        "MetricName": "FP_Arith_Utilization",
+        "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
     },
     {
-        "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
-        "MetricExpr": "2 * IDQ.MS_SWITCHES / CLKS",
-        "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_ms_switches",
-        "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
+        "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
+        "MetricName": "ILP"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
-        "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
-        "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
-        "MetricName": "tma_fetch_bandwidth",
-        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues.  For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
+        "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
+        "MetricGroup": "SMT",
+        "MetricName": "CORE_CLKS"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
-        "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
-        "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
-        "MetricName": "tma_mite",
-        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
+        "MetricGroup": "InsType",
+        "MetricName": "IpLoad"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
-        "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2",
-        "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
-        "MetricName": "tma_dsb",
-        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline.  For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
+        "MetricGroup": "InsType",
+        "MetricName": "IpStore"
     },
     {
-        "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
-        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
-        "MetricGroup": "TopdownL1;tma_L1_group",
-        "MetricName": "tma_bad_speculation",
-        "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Branches;Fed;InsType",
+        "MetricName": "IpBranch"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
-        "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
-        "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
-        "MetricName": "tma_branch_mispredicts",
-        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
+        "MetricGroup": "Branches;Fed;PGO",
+        "MetricName": "IpCall"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
-        "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
-        "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group",
-        "MetricName": "tma_machine_clears",
-        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears.  These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instruction per taken branch",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
+        "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
+        "MetricName": "IpTB"
     },
     {
-        "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
-        "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)",
-        "MetricGroup": "TopdownL1;tma_L1_group",
-        "MetricName": "tma_backend_bound",
-        "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Branch instructions per taken branch. ",
+        "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
+        "MetricGroup": "Branches;Fed;PGO",
+        "MetricName": "BpTkBranch"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
-        "MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB)) * tma_backend_bound",
-        "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
-        "MetricName": "tma_memory_bound",
-        "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
+        "MetricGroup": "Flops;InsType",
+        "MetricName": "IpFLOP"
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
-        "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CLKS, 0)",
-        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_l1_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache.  The L1 data cache typically has the shortest latency.  However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT_PS;MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
+        "MetricGroup": "Flops;InsType",
+        "MetricName": "IpArith",
+        "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
     },
     {
-        "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
-        "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * DTLB_LOAD_MISSES.WALK_COMPLETED) / CLKS",
-        "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_dtlb_load",
-        "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
+        "MetricGroup": "Flops;FpScalar;InsType",
+        "MetricName": "IpArith_Scalar_SP",
+        "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
-        "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS",
-        "MetricGroup": "TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_store_fwd_blk",
-        "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
+        "MetricGroup": "Flops;FpScalar;InsType",
+        "MetricName": "IpArith_Scalar_DP",
+        "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
-        "MetricExpr": "(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
-        "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_lock_latency",
-        "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)",
+        "MetricGroup": "Flops;FpVector;InsType",
+        "MetricName": "IpArith_AVX128",
+        "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary",
-        "MetricExpr": "Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS",
-        "MetricGroup": "TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_split_loads",
-        "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary.  Sample with: MEM_UOPS_RETIRED.SPLIT_LOADS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
+        "MetricGroup": "Flops;FpVector;InsType",
+        "MetricName": "IpArith_AVX256",
+        "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
-        "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CLKS",
-        "MetricGroup": "TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_4k_aliasing",
-        "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
+        "MetricExpr": "INST_RETIRED.ANY",
+        "MetricGroup": "Summary;tma_L1_group",
+        "MetricName": "Instructions"
     },
     {
-        "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
-        "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / CLKS",
-        "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_fb_full",
-        "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
+        "MetricGroup": "Pipeline;Ret",
+        "MetricName": "Retire"
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
-        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS",
-        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_l2_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
+        "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
+        "MetricName": "Execute"
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
-        "MetricExpr": "(MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
-        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_l3_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
+        "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
+        "MetricGroup": "DSB;Fed;FetchBW",
+        "MetricName": "DSB_Coverage"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
-        "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CLKS",
-        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_contested_accesses",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;BadSpec;BrMispredicts",
+        "MetricName": "IpMispredict"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
-        "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS",
-        "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_data_sharing",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
+        "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;BrMispredicts",
+        "MetricName": "Branch_Misprediction_Cost"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
-        "MetricExpr": "41 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS",
-        "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_l3_hit_latency",
-        "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
+        "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)",
+        "MetricGroup": "Mem;MemoryBound;MemoryLat",
+        "MetricName": "Load_Miss_Real_Latency"
     },
     {
-        "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
-        "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
-        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_sq_full",
-        "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
+        "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
+        "MetricGroup": "Mem;MemoryBW;MemoryBound",
+        "MetricName": "MLP"
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
-        "MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS))) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
-        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_dram_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
+        "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L1MPKI"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
-        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / CLKS",
-        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group",
-        "MetricName": "tma_mem_bandwidth",
-        "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM).  The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
+        "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
+        "MetricGroup": "Backend;CacheMisses;Mem",
+        "MetricName": "L2MPKI"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
-        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth",
-        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group",
-        "MetricName": "tma_mem_latency",
-        "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM).  This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
+        "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem;Offcore",
+        "MetricName": "L2MPKI_All"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
-        "MetricExpr": "200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS",
-        "MetricGroup": "Server;TopdownL5;tma_mem_latency_group",
-        "MetricName": "tma_local_dram",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (including speculative)",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L2MPKI_Load"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
-        "MetricExpr": "310 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS",
-        "MetricGroup": "Server;Snoop;TopdownL5;tma_mem_latency_group",
-        "MetricName": "tma_remote_dram",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
+        "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L2HPKI_All"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
-        "MetricExpr": "(200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CLKS",
-        "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_mem_latency_group",
-        "MetricName": "tma_remote_cache",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache hits per kilo instruction for all demand loads  (including speculative)",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L2HPKI_Load"
     },
     {
-        "BriefDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
-        "MetricExpr": "RESOURCE_STALLS.SB / CLKS",
-        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_store_bound",
-        "PublicDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
+        "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L3MPKI"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
-        "MetricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES))) + (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
-        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_store_latency",
-        "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
+        "MetricConstraint": "NO_NMI_WATCHDOG",
+        "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * (DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED)) / (2 * CORE_CLKS)",
+        "MetricGroup": "Mem;MemoryTLB",
+        "MetricName": "Page_Walks_Utilization"
     },
     {
-        "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
-        "MetricExpr": "(200 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE) / CLKS",
-        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_false_sharing",
-        "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line.  Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
+        "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L1D_Cache_Fill_BW"
     },
     {
-        "BriefDescription": "This metric represents rate of split store accesses",
-        "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / CORE_CLKS",
-        "MetricGroup": "TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_split_stores",
-        "PublicDescription": "This metric represents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_UOPS_RETIRED.SPLIT_STORES_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
+        "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L2_Cache_Fill_BW"
     },
     {
-        "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
-        "MetricExpr": "(8 * DTLB_STORE_MISSES.STLB_HIT + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * DTLB_STORE_MISSES.WALK_COMPLETED) / CLKS",
-        "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_dtlb_store",
-        "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead.  Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page.  Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
+        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L3_Cache_Fill_BW"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
-        "MetricExpr": "tma_backend_bound - tma_memory_bound",
-        "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group",
-        "MetricName": "tma_core_bound",
-        "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
+        "MetricExpr": "L1D_Cache_Fill_BW",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L1D_Cache_Fill_BW_1T"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
-        "MetricExpr": "ARITH.FPU_DIV_ACTIVE / CORE_CLKS",
-        "MetricGroup": "TopdownL3;tma_core_bound_group",
-        "MetricName": "tma_divider",
-        "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
+        "MetricExpr": "L2_Cache_Fill_BW",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L2_Cache_Fill_BW_1T"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
-        "MetricExpr": "((CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS",
-        "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
-        "MetricName": "tma_ports_utilization",
-        "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
+        "MetricExpr": "L3_Cache_Fill_BW",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L3_Cache_Fill_BW_1T"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@) / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else 0) / CORE_CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_0",
-        "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
+        "MetricExpr": "0",
+        "MetricGroup": "Mem;MemoryBW;Offcore",
+        "MetricName": "L3_Cache_Access_BW_1T"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_1",
-        "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average CPU Utilization",
+        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+        "MetricGroup": "HPC;Summary",
+        "MetricName": "CPU_Utilization"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_2",
-        "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
+        "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
+        "MetricGroup": "Power;Summary",
+        "MetricName": "Average_Frequency"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
-        "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_3m",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Giga Floating Point Operations Per Second",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time",
+        "MetricGroup": "Cor;Flops;HPC",
+        "MetricName": "GFLOPs",
+        "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
-        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / (4 * CORE_CLKS)",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
-        "MetricName": "tma_alu_op_utilization",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average Frequency Utilization relative nominal frequency",
+        "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
+        "MetricGroup": "Power",
+        "MetricName": "Turbo_Utilization"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED_PORT.PORT_0",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS",
-        "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group",
-        "MetricName": "tma_port_0",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
+        "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
+        "MetricGroup": "SMT",
+        "MetricName": "SMT_2T_Utilization"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_1",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
-        "MetricName": "tma_port_1",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "OS",
+        "MetricName": "Kernel_Utilization"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) Sample with: UOPS_DISPATCHED.PORT_5",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
-        "MetricName": "tma_port_5",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
+        "MetricGroup": "OS",
+        "MetricName": "Kernel_CPI"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_6",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
-        "MetricName": "tma_port_6",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
+        "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time",
+        "MetricGroup": "HPC;Mem;MemoryBW;SoC",
+        "MetricName": "DRAM_BW_Use"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3",
-        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
-        "MetricName": "tma_load_op_utilization",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
+        "MetricExpr": "1e9 * (UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_INSERTS.MISS_OPCODE@filter_opc\\=0x182@) / (Socket_CLKS / duration_time)",
+        "MetricGroup": "Mem;MemoryLat;SoC",
+        "MetricName": "MEM_Read_Latency"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_2",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_load_op_utilization_group",
-        "MetricName": "tma_port_2",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
+        "MetricExpr": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182\\,thresh\\=1@",
+        "MetricGroup": "Mem;MemoryBW;SoC",
+        "MetricName": "MEM_Parallel_Reads"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_3",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_load_op_utilization_group",
-        "MetricName": "tma_port_3",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Socket actual clocks when any core is active on that socket",
+        "MetricExpr": "cbox_0@event\\=0x0@",
+        "MetricGroup": "SoC",
+        "MetricName": "Socket_CLKS"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
-        "MetricName": "tma_store_op_utilization",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
+        "MetricGroup": "Branches;OS",
+        "MetricName": "IpFarBranch"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data) Sample with: UOPS_DISPATCHED_PORT.PORT_4",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_store_op_utilization_group",
-        "MetricName": "tma_port_4",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Uncore frequency per die [GHZ]",
+        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+        "MetricGroup": "SoC",
+        "MetricName": "UNCORE_FREQ"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address) Sample with: UOPS_DISPATCHED_PORT.PORT_7",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_store_op_utilization_group",
-        "MetricName": "tma_port_7",
-        "ScaleUnit": "100%"
+        "BriefDescription": "CPU operating frequency (in GHz)",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / duration_time",
+        "MetricName": "cpu_operating_frequency",
+        "ScaleUnit": "1GHz"
+    },
+    {
+        "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY",
+        "MetricName": "cpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
-        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS",
-        "MetricGroup": "TopdownL1;tma_L1_group",
-        "MetricName": "tma_retiring",
-        "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided.  Sample with: UOPS_RETIRED.RETIRE_SLOTS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
+        "MetricExpr": "MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
+        "MetricName": "loads_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
-        "MetricExpr": "tma_retiring - tma_heavy_operations",
-        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
-        "MetricName": "tma_light_operations",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST",
-        "ScaleUnit": "100%"
+        "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
+        "MetricExpr": "MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY",
+        "MetricName": "stores_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
-        "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector",
-        "MetricGroup": "HPC;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_fp_arith",
-        "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
+        "MetricName": "l1d_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
-        "MetricExpr": "INST_RETIRED.X87 * UPI / UOPS_RETIRED.RETIRE_SLOTS",
-        "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group",
-        "MetricName": "tma_x87_use",
-        "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions",
+        "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L1_HIT / INST_RETIRED.ANY",
+        "MetricName": "l1d_demand_data_read_hits_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / UOPS_RETIRED.RETIRE_SLOTS",
-        "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group",
-        "MetricName": "tma_fp_scalar",
-        "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
+        "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
+        "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS",
-        "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group",
-        "MetricName": "tma_fp_vector",
-        "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions",
+        "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_HIT / INST_RETIRED.ANY",
+        "MetricName": "l2_demand_data_read_hits_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS",
-        "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
-        "MetricName": "tma_fp_vector_128b",
-        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
+        "MetricName": "l2_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS",
-        "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
-        "MetricName": "tma_fp_vector_256b",
-        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
+        "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
+        "MetricName": "l2_demand_data_read_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
-        "MetricExpr": "tma_microcode_sequencer",
-        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
-        "MetricName": "tma_heavy_operations",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
+        "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
+        "MetricName": "l2_demand_code_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
-        "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
-        "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
-        "MetricName": "tma_microcode_sequencer",
-        "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "(cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x192@) / INST_RETIRED.ANY",
+        "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
-        "MetricExpr": "100 * OTHER_ASSISTS.ANY_WB_ASSIST / SLOTS",
-        "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
-        "MetricName": "tma_assists",
-        "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "(cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x181@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x191@) / INST_RETIRED.ANY",
+        "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
-        "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
-        "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
-        "MetricName": "tma_cisc",
-        "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds",
+        "MetricExpr": "1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time",
+        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency",
+        "ScaleUnit": "1ns"
     },
     {
-        "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
-        "MetricExpr": "INST_RETIRED.ANY / CLKS",
-        "MetricGroup": "Ret;Summary",
-        "MetricName": "IPC"
+        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds",
+        "MetricExpr": "1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time",
+        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests",
+        "ScaleUnit": "1ns"
     },
     {
-        "BriefDescription": "Uops Per Instruction",
-        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
-        "MetricGroup": "Pipeline;Ret;Retire",
-        "MetricName": "UPI"
+        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds",
+        "MetricExpr": "1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time",
+        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests",
+        "ScaleUnit": "1ns"
     },
     {
-        "BriefDescription": "Instruction per taken branch",
-        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
-        "MetricGroup": "Branches;Fed;FetchBW",
-        "MetricName": "UpTB"
+        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions",
+        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+        "MetricName": "itlb_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
-        "MetricExpr": "1 / IPC",
-        "MetricGroup": "Mem;Pipeline",
-        "MetricName": "CPI"
+        "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions",
+        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+        "MetricName": "itlb_large_page_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
-        "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
-        "MetricGroup": "Pipeline",
-        "MetricName": "CLKS"
+        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions",
+        "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+        "MetricName": "dtlb_load_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
-        "MetricExpr": "4 * CORE_CLKS",
-        "MetricGroup": "tma_L1_group",
-        "MetricName": "SLOTS"
+        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions",
+        "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+        "MetricName": "dtlb_store_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "The ratio of Executed- by Issued-Uops",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
-        "MetricGroup": "Cor;Pipeline",
-        "MetricName": "Execute_per_Issue",
-        "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
+        "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+        "MetricExpr": "cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / (cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@)",
+        "MetricName": "numa_reads_addressed_to_local_dram",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
-        "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
-        "MetricGroup": "Ret;SMT;tma_L1_group",
-        "MetricName": "CoreIPC"
+        "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+        "MetricExpr": "cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / (cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@)",
+        "MetricName": "numa_reads_addressed_to_remote_dram",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Floating Point Operations Per Cycle",
-        "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
-        "MetricGroup": "Flops;Ret",
-        "MetricName": "FLOPc"
+        "BriefDescription": "Uncore operating frequency in GHz",
+        "MetricExpr": "UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages) / 1e9 / duration_time",
+        "MetricName": "uncore_frequency",
+        "ScaleUnit": "1GHz"
     },
     {
-        "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
-        "MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
-        "MetricGroup": "Cor;Flops;HPC",
-        "MetricName": "FP_Arith_Utilization",
-        "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
+        "BriefDescription": "Intel(R) Quick Path Interconnect (QPI) data transmit bandwidth (MB/sec)",
+        "MetricExpr": "UNC_Q_TxL_FLITS_G0.DATA * 8 / 1e6 / duration_time",
+        "MetricName": "qpi_data_transmit_bw",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
-        "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
-        "MetricName": "ILP"
+        "BriefDescription": "DDR memory read bandwidth (MB/sec)",
+        "MetricExpr": "UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time",
+        "MetricName": "memory_bandwidth_read",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
-        "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
-        "MetricGroup": "SMT",
-        "MetricName": "CORE_CLKS"
+        "BriefDescription": "DDR memory write bandwidth (MB/sec)",
+        "MetricExpr": "UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time",
+        "MetricName": "memory_bandwidth_write",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
-        "MetricGroup": "InsType",
-        "MetricName": "IpLoad"
+        "BriefDescription": "DDR memory bandwidth (MB/sec)",
+        "MetricExpr": "(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time",
+        "MetricName": "memory_bandwidth_total",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
-        "MetricGroup": "InsType",
-        "MetricName": "IpStore"
+        "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
+        "MetricExpr": "cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x19e@ * 64 / 1e6 / duration_time",
+        "MetricName": "io_bandwidth_disk_or_network_writes",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Branches;Fed;InsType",
-        "MetricName": "IpBranch"
+        "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
+        "MetricExpr": "(cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x1c8\\,filter_tid\\=0x3e@ + cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x180\\,filter_tid\\=0x3e@) * 64 / 1e6 / duration_time",
+        "MetricName": "io_bandwidth_disk_or_network_reads",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
-        "MetricGroup": "Branches;Fed;PGO",
-        "MetricName": "IpCall"
+        "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
+        "MetricExpr": "IDQ.DSB_UOPS / UOPS_ISSUED.ANY",
+        "MetricName": "percent_uops_delivered_from_decoded_icache",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instruction per taken branch",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
-        "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
-        "MetricName": "IpTB"
+        "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
+        "MetricExpr": "IDQ.MITE_UOPS / UOPS_ISSUED.ANY",
+        "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Branch instructions per taken branch. ",
-        "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
-        "MetricGroup": "Branches;Fed;PGO",
-        "MetricName": "BpTkBranch"
+        "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
+        "MetricExpr": "IDQ.MS_UOPS / UOPS_ISSUED.ANY",
+        "MetricName": "percent_uops_delivered_from_microcode_sequencer",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
-        "MetricGroup": "Flops;InsType",
-        "MetricName": "IpFLOP"
+        "BriefDescription": "Uops delivered from loop stream detector(LSD) as a percent of total uops delivered to Instruction Decode Queue",
+        "MetricExpr": "LSD.UOPS / UOPS_ISSUED.ANY",
+        "MetricName": "percent_uops_delivered_from_loop_stream_detector",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
-        "MetricGroup": "Flops;InsType",
-        "MetricName": "IpArith",
-        "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
+        "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
+        "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS",
+        "MetricGroup": "PGO;TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_frontend_bound",
+        "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
-        "MetricGroup": "Flops;FpScalar;InsType",
-        "MetricName": "IpArith_Scalar_SP",
-        "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
+        "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS",
+        "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+        "MetricName": "tma_fetch_latency",
+        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
-        "MetricGroup": "Flops;FpScalar;InsType",
-        "MetricName": "IpArith_Scalar_DP",
-        "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.",
+        "MetricExpr": "ICACHE.IFDATA_STALL / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_icache_misses",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)",
-        "MetricGroup": "Flops;FpVector;InsType",
-        "MetricName": "IpArith_AVX128",
-        "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.",
+        "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=0x1@ + 7 * ITLB_MISSES.WALK_COMPLETED) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_itlb_misses",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
-        "MetricGroup": "Flops;FpVector;InsType",
-        "MetricName": "IpArith_AVX256",
-        "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
+        "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_branch_resteers",
+        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
-        "MetricExpr": "INST_RETIRED.ANY",
-        "MetricGroup": "Summary;tma_L1_group",
-        "MetricName": "Instructions"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ",
+        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)",
+        "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+        "MetricName": "tma_mispredicts_resteers",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
-        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
-        "MetricGroup": "Pipeline;Ret",
-        "MetricName": "Retire"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ",
+        "MetricExpr": "MACHINE_CLEARS.COUNT * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)",
+        "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+        "MetricName": "tma_clears_resteers",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
-        "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
-        "MetricName": "Execute"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
+        "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers",
+        "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+        "MetricName": "tma_unknown_branches",
+        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
-        "MetricExpr": "IDQ.DSB_UOPS / ((IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS))",
-        "MetricGroup": "DSB;Fed;FetchBW",
-        "MetricName": "DSB_Coverage"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
+        "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_dsb_switches",
+        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;BadSpec;BrMispredicts",
-        "MetricName": "IpMispredict"
+        "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
+        "MetricExpr": "ILD_STALL.LCP / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_lcp",
+        "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
-        "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;BrMispredicts",
-        "MetricName": "Branch_Misprediction_Cost"
+        "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
+        "MetricExpr": "2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_ms_switches",
+        "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
-        "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb)",
-        "MetricGroup": "Mem;MemoryBound;MemoryLat",
-        "MetricName": "Load_Miss_Real_Latency"
+        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
+        "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
+        "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+        "MetricName": "tma_fetch_bandwidth",
+        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues.  For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
-        "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
-        "MetricGroup": "Mem;MemoryBW;MemoryBound",
-        "MetricName": "MLP"
+        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
+        "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
+        "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+        "MetricName": "tma_mite",
+        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L1MPKI"
+        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
+        "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2",
+        "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+        "MetricName": "tma_dsb",
+        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline.  For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "Backend;CacheMisses;Mem",
-        "MetricName": "L2MPKI"
+        "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
+        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+        "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_bad_speculation",
+        "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem;Offcore",
-        "MetricName": "L2MPKI_All"
+        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
+        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
+        "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+        "MetricName": "tma_branch_mispredicts",
+        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L2MPKI_Load"
+        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
+        "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
+        "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+        "MetricName": "tma_machine_clears",
+        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears.  These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
-        "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L2HPKI_All"
+        "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
+        "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + UOPS_RETIRED.RETIRE_SLOTS / SLOTS)",
+        "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_backend_bound",
+        "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache hits per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L2HPKI_Load"
+        "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
+        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound",
+        "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+        "MetricName": "tma_memory_bound",
+        "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L3MPKI"
+        "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
+        "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CPU_CLK_UNHALTED.THREAD, 0)",
+        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_l1_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache.  The L1 data cache typically has the shortest latency.  However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
-        "MetricConstraint": "NO_NMI_WATCHDOG",
-        "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * (DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED)) / (2 * CORE_CLKS)",
-        "MetricGroup": "Mem;MemoryTLB",
-        "MetricName": "Page_Walks_Utilization"
+        "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
+        "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=0x1@ + 7 * DTLB_LOAD_MISSES.WALK_COMPLETED) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_dtlb_load",
+        "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
-        "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L1D_Cache_Fill_BW"
+        "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
+        "MetricExpr": "min(13 * LD_BLOCKS.STORE_FORWARD / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_store_fwd_blk",
+        "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
-        "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L2_Cache_Fill_BW"
+        "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
+        "MetricExpr": "min(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_lock_latency",
+        "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L3_Cache_Fill_BW"
+        "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ",
+        "MetricExpr": "min(Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_split_loads",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
-        "MetricExpr": "L1D_Cache_Fill_BW",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L1D_Cache_Fill_BW_1T"
+        "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
+        "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_4k_aliasing",
+        "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
-        "MetricExpr": "L2_Cache_Fill_BW",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L2_Cache_Fill_BW_1T"
+        "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
+        "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_fb_full",
+        "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "L3_Cache_Fill_BW",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L3_Cache_Fill_BW_1T"
+        "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
+        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_l2_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "0",
-        "MetricGroup": "Mem;MemoryBW;Offcore",
-        "MetricName": "L3_Cache_Access_BW_1T"
+        "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
+        "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_MISS / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_l3_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average CPU Utilization",
-        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
-        "MetricGroup": "HPC;Summary",
-        "MetricName": "CPU_Utilization"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
+        "MetricExpr": "min((60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_contested_accesses",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
-        "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
-        "MetricGroup": "Power;Summary",
-        "MetricName": "Average_Frequency"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
+        "MetricExpr": "min(43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_data_sharing",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Giga Floating Point Operations Per Second",
-        "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1000000000) / duration_time",
-        "MetricGroup": "Cor;Flops;HPC",
-        "MetricName": "GFLOPs",
-        "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
+        "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
+        "MetricExpr": "min(41 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_l3_hit_latency",
+        "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average Frequency Utilization relative nominal frequency",
-        "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
-        "MetricGroup": "Power",
-        "MetricName": "Turbo_Utilization"
+        "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
+        "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
+        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_sq_full",
+        "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
-        "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
-        "MetricGroup": "SMT",
-        "MetricName": "SMT_2T_Utilization"
+        "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
+        "MetricExpr": "min((1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_dram_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
-        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
-        "MetricGroup": "OS",
-        "MetricName": "Kernel_Utilization"
+        "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
+        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+        "MetricName": "tma_mem_bandwidth",
+        "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM).  The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
-        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
-        "MetricGroup": "OS",
-        "MetricName": "Kernel_CPI"
+        "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
+        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CPU_CLK_UNHALTED.THREAD - tma_mem_bandwidth",
+        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+        "MetricName": "tma_mem_latency",
+        "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM).  This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
-        "MetricExpr": "(64 * (uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@) / 1000000000) / duration_time",
-        "MetricGroup": "HPC;Mem;MemoryBW;SoC",
-        "MetricName": "DRAM_BW_Use"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
+        "MetricExpr": "min(200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group",
+        "MetricName": "tma_local_dram",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
-        "MetricExpr": "1000000000 * (cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x35\\,umask\\=0x3\\,filter_opc\\=0x182@) / (Socket_CLKS / duration_time)",
-        "MetricGroup": "Mem;MemoryLat;SoC",
-        "MetricName": "MEM_Read_Latency"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
+        "MetricExpr": "min(310 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+        "MetricName": "tma_remote_dram",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
-        "MetricExpr": "cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182\\,thresh\\=1@",
-        "MetricGroup": "Mem;MemoryBW;SoC",
-        "MetricName": "MEM_Parallel_Reads"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
+        "MetricExpr": "min((200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+        "MetricName": "tma_remote_cache",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Socket actual clocks when any core is active on that socket",
-        "MetricExpr": "cbox_0@event\\=0x0@",
-        "MetricGroup": "SoC",
-        "MetricName": "Socket_CLKS"
+        "BriefDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
+        "MetricExpr": "RESOURCE_STALLS.SB / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_store_bound",
+        "PublicDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
-        "MetricGroup": "Branches;OS",
-        "MetricName": "IpFarBranch"
+        "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
+        "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_store_latency",
+        "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C3 residency percent per core",
-        "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C3_Core_Residency"
+        "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
+        "MetricExpr": "min((200 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_false_sharing",
+        "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C6 residency percent per core",
-        "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C6_Core_Residency"
+        "BriefDescription": "This metric represents rate of split store accesses",
+        "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / CORE_CLKS",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_split_stores",
+        "PublicDescription": "This metric represents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granularity.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C7 residency percent per core",
-        "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C7_Core_Residency"
+        "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
+        "MetricExpr": "min((8 * DTLB_STORE_MISSES.STLB_HIT + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=0x1@ + 7 * DTLB_STORE_MISSES.WALK_COMPLETED) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_dtlb_store",
+        "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead.  Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page.  Try using larger page sizes for large amounts of frequently-used data.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C2 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C2_Pkg_Residency"
+        "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
+        "MetricExpr": "tma_backend_bound - tma_memory_bound",
+        "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+        "MetricName": "tma_core_bound",
+        "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C3 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C3_Pkg_Residency"
+        "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
+        "MetricExpr": "ARITH.FPU_DIV_ACTIVE / CORE_CLKS",
+        "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group",
+        "MetricName": "tma_divider",
+        "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C6 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C6_Pkg_Residency"
+        "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
+        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group",
+        "MetricName": "tma_ports_utilization",
+        "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C7 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C7_Pkg_Residency"
+        "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\=0x1\\,cmask\\=0x1@ / 2 if #SMT_on else CYCLE_ACTIVITY.STALLS_TOTAL - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0)) / CORE_CLKS",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_0",
+        "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uncore frequency per die [GHZ]",
-        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000",
-        "MetricGroup": "SoC",
-        "MetricName": "UNCORE_FREQ"
+        "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+        "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@) / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_1",
+        "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "CPU operating frequency (in GHz)",
-        "MetricExpr": "(( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ ) / 1000000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "cpu_operating_frequency",
-        "ScaleUnit": "1GHz"
+        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+        "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@) / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_2",
+        "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
-        "MetricExpr": "MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "loads_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
+        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_3m",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
-        "MetricExpr": "MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "stores_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
+        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+        "MetricName": "tma_alu_op_utilization",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l1d_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS",
+        "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+        "MetricName": "tma_port_0",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions",
-        "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L1_HIT / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l1d_demand_data_read_hits_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+        "MetricName": "tma_port_1",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
-        "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+        "MetricName": "tma_port_5",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions",
-        "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_HIT / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_demand_data_read_hits_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+        "MetricName": "tma_port_6",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations",
+        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+        "MetricName": "tma_load_op_utilization",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
-        "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_demand_data_read_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group",
+        "MetricName": "tma_port_2",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
-        "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_demand_code_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group",
+        "MetricName": "tma_port_3",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x192@ ) / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+        "MetricName": "tma_store_op_utilization",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x181@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x191@ ) / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)",
+        "MetricExpr": "tma_store_op_utilization",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group",
+        "MetricName": "tma_port_4",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds",
-        "MetricExpr": "( 1000000000 * ( cbox@UNC_C_TOR_OCCUPANCY.MISS_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ ) / ( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency",
-        "ScaleUnit": "1ns"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group",
+        "MetricName": "tma_port_7",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds",
-        "MetricExpr": "( 1000000000 * ( cbox@UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ ) / ( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests",
-        "ScaleUnit": "1ns"
+        "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS",
+        "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_retiring",
+        "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds",
-        "MetricExpr": "( 1000000000 * ( cbox@UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ ) / ( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests",
-        "ScaleUnit": "1ns"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
+        "MetricExpr": "tma_retiring - UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
+        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+        "MetricName": "tma_light_operations",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
-        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "itlb_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
+        "MetricExpr": "INST_RETIRED.X87 * UPI / UOPS_RETIRED.RETIRE_SLOTS + tma_fp_scalar + tma_fp_vector",
+        "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_fp_arith",
+        "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
-        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "itlb_large_page_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
+        "MetricExpr": "INST_RETIRED.X87 * UPI / UOPS_RETIRED.RETIRE_SLOTS",
+        "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group",
+        "MetricName": "tma_x87_use",
+        "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
-        "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "dtlb_load_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / UOPS_RETIRED.RETIRE_SLOTS",
+        "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group",
+        "MetricName": "tma_fp_scalar",
+        "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
-        "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "dtlb_store_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
+        "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)",
+        "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group",
+        "MetricName": "tma_fp_vector",
+        "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
-        "MetricExpr": "100 * cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / ( cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ )",
-        "MetricGroup": "",
-        "MetricName": "numa_reads_addressed_to_local_dram",
-        "ScaleUnit": "1%"
+        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
+        "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)",
+        "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+        "MetricName": "tma_fp_vector_128b",
+        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
-        "MetricExpr": "100 * cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / ( cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ )",
-        "MetricGroup": "",
-        "MetricName": "numa_reads_addressed_to_remote_dram",
-        "ScaleUnit": "1%"
+        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
+        "MetricExpr": "min((FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)",
+        "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+        "MetricName": "tma_fp_vector_256b",
+        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uncore operating frequency in GHz",
-        "MetricExpr": "( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) / 1000000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "uncore_frequency",
-        "ScaleUnit": "1GHz"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
+        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+        "MetricName": "tma_heavy_operations",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Intel(R) Quick Path Interconnect (QPI) data transmit bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_Q_TxL_FLITS_G0.DATA * 8 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "qpi_data_transmit_bw",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
+        "MetricExpr": "tma_heavy_operations",
+        "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group",
+        "MetricName": "tma_microcode_sequencer",
+        "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "DDR memory read bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "memory_bandwidth_read",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
+        "MetricExpr": "min(100 * OTHER_ASSISTS.ANY_WB_ASSIST / SLOTS, 1)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+        "MetricName": "tma_assists",
+        "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "DDR memory write bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "memory_bandwidth_write",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
+        "MetricExpr": "max(0, tma_heavy_operations - tma_assists)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+        "MetricName": "tma_cisc",
+        "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "DDR memory bandwidth (MB/sec)",
-        "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "memory_bandwidth_total",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "C3 residency percent per core",
+        "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C3_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
-        "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x19e@ * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "io_bandwidth_disk_or_network_writes",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "C6 residency percent per core",
+        "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C6_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
-        "MetricExpr": "(( cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x1c8\\,filter_tid\\=0x3e@ + cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x180\\,filter_tid\\=0x3e@ ) * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "io_bandwidth_disk_or_network_reads",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "C7 residency percent per core",
+        "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C7_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
-        "MetricExpr": "100 * ( IDQ.DSB_UOPS / UOPS_ISSUED.ANY )",
-        "MetricGroup": "",
-        "MetricName": "percent_uops_delivered_from_decoded_icache",
-        "ScaleUnit": "1%"
+        "BriefDescription": "C2 residency percent per package",
+        "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C2_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
-        "MetricExpr": "100 * ( IDQ.MITE_UOPS / UOPS_ISSUED.ANY )",
-        "MetricGroup": "",
-        "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
-        "ScaleUnit": "1%"
+        "BriefDescription": "C3 residency percent per package",
+        "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C3_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
-        "MetricExpr": "100 * ( IDQ.MS_UOPS / UOPS_ISSUED.ANY )",
-        "MetricGroup": "",
-        "MetricName": "percent_uops_delivered_from_microcode_sequencer",
-        "ScaleUnit": "1%"
+        "BriefDescription": "C6 residency percent per package",
+        "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C6_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uops delivered from loop stream detector(LSD) as a percent of total uops delivered to Instruction Decode Queue",
-        "MetricExpr": "100 * ( LSD.UOPS / UOPS_ISSUED.ANY )",
-        "MetricGroup": "",
-        "MetricName": "percent_uops_delivered_from_loop_stream_detector",
-        "ScaleUnit": "1%"
+        "BriefDescription": "C7 residency percent per package",
+        "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C7_Pkg_Residency",
+        "ScaleUnit": "100%"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/cache.json b/tools/perf/pmu-events/arch/x86/broadwellx/cache.json
index 2efc4c0ee740d..6a134928b3f09 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/cache.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/cache.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "L1D data line replacements",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x51",
         "EventName": "L1D.REPLACEMENT",
         "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.FB_FULL",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "L1D miss oustandings duration in cycles",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING",
         "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Cycles with L1D load Misses outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -43,8 +35,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -53,8 +43,6 @@
     },
     {
         "BriefDescription": "Not rejected writebacks that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x27",
         "EventName": "L2_DEMAND_RQSTS.WB_HIT",
         "PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
@@ -63,8 +51,6 @@
     },
     {
         "BriefDescription": "L2 cache lines filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.ALL",
         "PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
@@ -73,8 +59,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in E state filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.E",
         "PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.",
@@ -83,8 +67,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in I state filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.I",
         "PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.",
@@ -93,8 +75,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in S state filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.S",
         "PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.",
@@ -103,8 +83,6 @@
     },
     {
         "BriefDescription": "Clean L2 cache lines evicted by demand.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
         "SampleAfterValue": "100003",
@@ -112,8 +90,6 @@
     },
     {
         "BriefDescription": "L2 code requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_CODE_RD",
         "PublicDescription": "This event counts the total number of L2 code requests.",
@@ -122,8 +98,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
         "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
@@ -132,8 +106,6 @@
     },
     {
         "BriefDescription": "Demand requests that miss L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
         "SampleAfterValue": "200003",
@@ -141,8 +113,6 @@
     },
     {
         "BriefDescription": "Demand requests to L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
         "SampleAfterValue": "200003",
@@ -150,8 +120,6 @@
     },
     {
         "BriefDescription": "Requests from L2 hardware prefetchers",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_PF",
         "PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.",
@@ -160,8 +128,6 @@
     },
     {
         "BriefDescription": "RFO requests to L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_RFO",
         "PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
@@ -170,8 +136,6 @@
     },
     {
         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_HIT",
         "SampleAfterValue": "200003",
@@ -179,8 +143,6 @@
     },
     {
         "BriefDescription": "L2 cache misses when fetching instructions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_MISS",
         "SampleAfterValue": "200003",
@@ -188,8 +150,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
         "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache.",
@@ -198,8 +158,6 @@
     },
     {
         "BriefDescription": "Demand Data Read miss L2, no rejects",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
         "PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
@@ -208,8 +166,6 @@
     },
     {
         "BriefDescription": "L2 prefetch requests that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.L2_PF_HIT",
         "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.",
@@ -218,8 +174,6 @@
     },
     {
         "BriefDescription": "L2 prefetch requests that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.L2_PF_MISS",
         "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.",
@@ -228,8 +182,6 @@
     },
     {
         "BriefDescription": "All requests that miss L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.MISS",
         "SampleAfterValue": "200003",
@@ -237,8 +189,6 @@
     },
     {
         "BriefDescription": "All L2 requests.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.REFERENCES",
         "SampleAfterValue": "200003",
@@ -246,8 +196,6 @@
     },
     {
         "BriefDescription": "RFO requests that hit L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_HIT",
         "SampleAfterValue": "200003",
@@ -255,8 +203,6 @@
     },
     {
         "BriefDescription": "RFO requests that miss L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_MISS",
         "SampleAfterValue": "200003",
@@ -264,8 +210,6 @@
     },
     {
         "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.ALL_PF",
         "PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects.",
@@ -274,8 +218,6 @@
     },
     {
         "BriefDescription": "Transactions accessing L2 pipe",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.ALL_REQUESTS",
         "PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.",
@@ -284,8 +226,6 @@
     },
     {
         "BriefDescription": "L2 cache accesses when fetching instructions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.CODE_RD",
         "PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.",
@@ -294,8 +234,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.DEMAND_DATA_RD",
         "PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.",
@@ -304,8 +242,6 @@
     },
     {
         "BriefDescription": "L1D writebacks that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L1D_WB",
         "PublicDescription": "This event counts L1D writebacks that access L2 cache.",
@@ -314,8 +250,6 @@
     },
     {
         "BriefDescription": "L2 fill requests that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L2_FILL",
         "PublicDescription": "This event counts L2 fill requests that access L2 cache.",
@@ -324,8 +258,6 @@
     },
     {
         "BriefDescription": "L2 writebacks that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L2_WB",
         "PublicDescription": "This event counts L2 writebacks that access L2 cache.",
@@ -334,8 +266,6 @@
     },
     {
         "BriefDescription": "RFO requests that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.RFO",
         "PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.",
@@ -344,8 +274,6 @@
     },
     {
         "BriefDescription": "Cycles when L1D is locked",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x63",
         "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
         "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",
@@ -354,8 +282,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests missed L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.MISS",
         "PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
@@ -364,8 +290,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
         "PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
@@ -374,8 +298,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM100",
         "EventCode": "0xD2",
@@ -387,8 +309,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM100",
         "EventCode": "0xD2",
@@ -400,8 +320,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM100",
         "EventCode": "0xD2",
@@ -413,8 +331,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM100",
         "EventCode": "0xD2",
@@ -426,8 +342,6 @@
     },
     {
         "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDE70, BDM100",
         "EventCode": "0xD3",
@@ -439,8 +353,6 @@
     },
     {
         "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDE70",
         "EventCode": "0xD3",
@@ -451,8 +363,6 @@
     },
     {
         "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDE70",
         "EventCode": "0xD3",
@@ -463,8 +373,6 @@
     },
     {
         "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDE70",
         "EventCode": "0xD3",
@@ -475,8 +383,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
@@ -487,8 +393,6 @@
     },
     {
         "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
@@ -499,8 +403,6 @@
     },
     {
         "BriefDescription": "Retired load uops misses in L1 cache as data sources.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
@@ -511,8 +413,6 @@
     },
     {
         "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM35",
         "EventCode": "0xD1",
@@ -524,8 +424,6 @@
     },
     {
         "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
@@ -536,8 +434,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM100",
         "EventCode": "0xD1",
@@ -549,8 +445,6 @@
     },
     {
         "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM100, BDE70",
         "EventCode": "0xD1",
@@ -561,8 +455,6 @@
     },
     {
         "BriefDescription": "All retired load uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
@@ -573,12 +465,9 @@
     },
     {
         "BriefDescription": "All retired store uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "PublicDescription": "This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement.",
         "SampleAfterValue": "2000003",
@@ -586,8 +475,6 @@
     },
     {
         "BriefDescription": "Retired load uops with locked access.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "BDM35",
         "EventCode": "0xD0",
@@ -599,8 +486,6 @@
     },
     {
         "BriefDescription": "Retired load uops that split across a cacheline boundary.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
@@ -611,12 +496,9 @@
     },
     {
         "BriefDescription": "Retired store uops that split across a cacheline boundary.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
         "SampleAfterValue": "100003",
@@ -624,8 +506,6 @@
     },
     {
         "BriefDescription": "Retired load uops that miss the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
@@ -636,12 +516,9 @@
     },
     {
         "BriefDescription": "Retired store uops that miss the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "PublicDescription": "This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",
         "SampleAfterValue": "100003",
@@ -649,8 +526,6 @@
     },
     {
         "BriefDescription": "Demand and prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
         "PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
@@ -659,8 +534,6 @@
     },
     {
         "BriefDescription": "Any memory transaction that reached the SQ.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb0",
         "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
         "PublicDescription": "This event counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, and so on.",
@@ -669,8 +542,6 @@
     },
     {
         "BriefDescription": "Cacheable and noncachaeble code read requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
         "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.",
@@ -679,8 +550,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests sent to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
         "PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
@@ -689,8 +558,6 @@
     },
     {
         "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
         "PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
@@ -699,8 +566,6 @@
     },
     {
         "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb2",
         "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
         "PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.",
@@ -709,8 +574,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM76",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
@@ -720,8 +583,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "Errata": "BDM76",
         "EventCode": "0x60",
@@ -732,8 +593,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "Errata": "BDM76",
         "EventCode": "0x60",
@@ -744,8 +603,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "Errata": "BDM76",
         "EventCode": "0x60",
@@ -756,8 +613,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM76",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
@@ -767,8 +622,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM76",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
@@ -778,8 +631,6 @@
     },
     {
         "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "6",
         "Errata": "BDM76",
         "EventCode": "0x60",
@@ -789,8 +640,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM76",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
@@ -800,8 +649,6 @@
     },
     {
         "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE",
         "SampleAfterValue": "100003",
@@ -809,152 +656,114 @@
     },
     {
         "BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0244",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C07F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C07F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all requests hit in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C8FFF",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0200",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Split locks in SQ",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xf4",
         "EventName": "SQ_MISC.SPLIT_LOCK",
         "PublicDescription": "This event counts the number of split locks in the super queue.",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json b/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json
index 93bbc86003218..e4826dc7f7978 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
         "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
         "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
         "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
         "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -41,8 +33,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
         "SampleAfterValue": "2000006",
@@ -50,8 +40,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.PACKED",
         "SampleAfterValue": "2000004",
@@ -59,8 +47,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation.   Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.SCALAR",
         "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -69,8 +55,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
         "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -79,8 +63,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
         "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -89,8 +71,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.SINGLE",
         "SampleAfterValue": "2000005",
@@ -98,8 +78,6 @@
     },
     {
         "BriefDescription": "Cycles with any input/output SSE or FP assist",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.ANY",
@@ -109,8 +87,6 @@
     },
     {
         "BriefDescription": "Number of SIMD FP assists due to input values",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.SIMD_INPUT",
         "PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",
@@ -119,8 +95,6 @@
     },
     {
         "BriefDescription": "Number of SIMD FP assists due to Output values",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.SIMD_OUTPUT",
         "PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
@@ -129,8 +103,6 @@
     },
     {
         "BriefDescription": "Number of X87 assists due to input value.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.X87_INPUT",
         "PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
@@ -139,8 +111,6 @@
     },
     {
         "BriefDescription": "Number of X87 assists due to output value.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.X87_OUTPUT",
         "PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
@@ -149,8 +119,6 @@
     },
     {
         "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
         "SampleAfterValue": "1000003",
@@ -158,8 +126,6 @@
     },
     {
         "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
         "SampleAfterValue": "1000003",
@@ -167,8 +133,6 @@
     },
     {
         "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM30",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.AVX_TO_SSE",
@@ -178,8 +142,6 @@
     },
     {
         "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM30",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.SSE_TO_AVX",
@@ -189,8 +151,6 @@
     },
     {
         "BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xA0",
         "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF",
         "PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file.  The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*.  See the Broadwell Optimization Guide for more information.",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json b/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json
index 37ce8034b2ed4..d0f6678609ae6 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xe6",
         "EventName": "BACLEARS.ANY",
         "SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
     },
     {
         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAB",
         "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
         "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
@@ -20,8 +16,6 @@
     },
     {
         "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.HIT",
         "PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.",
@@ -30,8 +24,6 @@
     },
     {
         "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.IFDATA_STALL",
         "PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).",
@@ -40,8 +32,6 @@
     },
     {
         "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.MISSES",
         "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
@@ -50,8 +40,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -61,8 +49,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -72,8 +58,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering 4 Uops",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -83,8 +67,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering any Uop",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -94,8 +76,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_CYCLES",
@@ -105,8 +85,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_UOPS",
         "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
@@ -115,8 +93,6 @@
     },
     {
         "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0x79",
         "EventName": "IDQ.EMPTY",
         "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end.  It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",
@@ -125,8 +101,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_ALL_UOPS",
         "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@@ -135,8 +109,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_CYCLES",
@@ -146,8 +118,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_UOPS",
         "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@@ -156,8 +126,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_CYCLES",
@@ -167,8 +135,6 @@
     },
     {
         "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_DSB_CYCLES",
@@ -178,8 +144,6 @@
     },
     {
         "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
@@ -190,8 +154,6 @@
     },
     {
         "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_DSB_UOPS",
         "PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
@@ -200,8 +162,6 @@
     },
     {
         "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_MITE_UOPS",
         "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.",
@@ -210,8 +170,6 @@
     },
     {
         "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
@@ -221,8 +179,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_UOPS",
         "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
@@ -231,8 +187,6 @@
     },
     {
         "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
         "PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4  x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.",
@@ -241,8 +195,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -252,8 +204,6 @@
     },
     {
         "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@@ -263,8 +213,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "3",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@@ -274,8 +222,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@@ -284,8 +230,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/memory.json b/tools/perf/pmu-events/arch/x86/broadwellx/memory.json
index 545f61f691b99..a7449e5b68dc3 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/memory.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Number of times HLE abort was triggered",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED",
         "PEBS": "1",
@@ -12,8 +10,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC1",
         "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
@@ -22,8 +18,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC2",
         "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.",
@@ -32,8 +26,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC3",
         "PublicDescription": "Number of times a disallowed operation caused an HLE abort.",
@@ -42,8 +34,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC4",
         "PublicDescription": "Number of times HLE caused a fault.",
@@ -52,8 +42,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC5",
         "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.",
@@ -62,8 +50,6 @@
     },
     {
         "BriefDescription": "Number of times HLE commit succeeded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.COMMIT",
         "PublicDescription": "Number of times HLE commit succeeded.",
@@ -72,8 +58,6 @@
     },
     {
         "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.START",
         "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.",
@@ -82,8 +66,6 @@
     },
     {
         "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
         "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",
@@ -92,8 +74,6 @@
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 128",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xcd",
@@ -103,13 +83,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads with latency value being above 128.",
         "SampleAfterValue": "1009",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 16",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xcd",
@@ -119,13 +96,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads with latency value being above 16.",
         "SampleAfterValue": "20011",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 256",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xcd",
@@ -135,13 +109,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads with latency value being above 256.",
         "SampleAfterValue": "503",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 32",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xcd",
@@ -151,13 +122,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads with latency value being above 32.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 4",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xcd",
@@ -167,13 +135,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads with latency value being above four.",
         "SampleAfterValue": "100003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 512",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xcd",
@@ -183,13 +148,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads with latency value being above 512.",
         "SampleAfterValue": "101",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 64",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xcd",
@@ -199,13 +161,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads with latency value being above 64.",
         "SampleAfterValue": "2003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 8",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "BDM100, BDM35",
         "EventCode": "0xcd",
@@ -215,13 +174,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads with latency value being above eight.",
         "SampleAfterValue": "50021",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x05",
         "EventName": "MISALIGN_MEM_REF.LOADS",
         "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",
@@ -230,8 +186,6 @@
     },
     {
         "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x05",
         "EventName": "MISALIGN_MEM_REF.STORES",
         "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",
@@ -240,236 +194,177 @@
     },
     {
         "BriefDescription": "Counts all demand & prefetch code reads miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC00244",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000244",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC00091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63BC00091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x87FC00091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x6040007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63BC007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x87FC007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all requests miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC08FFF",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC00122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC00002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC00200",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC00100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of times RTM abort was triggered",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED",
         "PEBS": "1",
@@ -479,8 +374,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC1",
         "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
@@ -489,8 +382,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC2",
         "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.",
@@ -499,8 +390,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC3",
         "PublicDescription": "Number of times a disallowed operation caused an RTM abort.",
@@ -509,8 +398,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC4",
         "PublicDescription": "Number of times a RTM caused a fault.",
@@ -519,8 +406,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC5",
         "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.",
@@ -529,8 +414,6 @@
     },
     {
         "BriefDescription": "Number of times RTM commit succeeded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.COMMIT",
         "PublicDescription": "Number of times RTM commit succeeded.",
@@ -539,8 +422,6 @@
     },
     {
         "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.START",
         "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.",
@@ -549,8 +430,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC1",
         "SampleAfterValue": "2000003",
@@ -558,8 +437,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC2",
         "PublicDescription": "Unfriendly TSX abort triggered by  a vzeroupper instruction.",
@@ -568,8 +445,6 @@
     },
     {
         "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC3",
         "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
@@ -578,8 +453,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC4",
         "PublicDescription": "RTM region detected inside HLE.",
@@ -588,8 +461,6 @@
     },
     {
         "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC5",
         "SampleAfterValue": "2000003",
@@ -597,8 +468,6 @@
     },
     {
         "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
         "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.",
@@ -607,8 +476,6 @@
     },
     {
         "BriefDescription": "Number of times a TSX line had a cache conflict",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CONFLICT",
         "PublicDescription": "Number of times a TSX line had a cache conflict.",
@@ -617,8 +484,6 @@
     },
     {
         "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
         "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
@@ -627,8 +492,6 @@
     },
     {
         "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
         "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
@@ -637,8 +500,6 @@
     },
     {
         "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
         "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
@@ -647,8 +508,6 @@
     },
     {
         "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
         "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
@@ -657,8 +516,6 @@
     },
     {
         "BriefDescription": "Number of times we could not allocate Lock Buffer",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
         "PublicDescription": "Number of times we could not allocate Lock Buffer.",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/other.json b/tools/perf/pmu-events/arch/x86/broadwellx/other.json
index 917d145d52273..1c2a5b0019496 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/other.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/other.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5C",
         "EventName": "CPL_CYCLES.RING0",
         "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5C",
@@ -23,8 +19,6 @@
     },
     {
         "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5C",
         "EventName": "CPL_CYCLES.RING123",
         "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
@@ -33,8 +27,6 @@
     },
     {
         "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x63",
         "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
         "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json b/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json
index f0f30081d6831..75233316640b8 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Cycles when divider is busy executing divide operations",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x14",
         "EventName": "ARITH.FPU_DIV_ACTIVE",
         "PublicDescription": "This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Speculative and retired  branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_BRANCHES",
         "PublicDescription": "This event counts both taken and not taken speculative and retired branch instructions.",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Speculative and retired macro-conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
         "PublicDescription": "This event counts both taken and not taken speculative and retired macro-conditional branch instructions.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
         "PublicDescription": "This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.",
@@ -41,8 +33,6 @@
     },
     {
         "BriefDescription": "Speculative and retired direct near calls",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
         "PublicDescription": "This event counts both taken and not taken speculative and retired direct near calls.",
@@ -51,8 +41,6 @@
     },
     {
         "BriefDescription": "Speculative and retired indirect branches excluding calls and returns",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
         "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.",
@@ -61,8 +49,6 @@
     },
     {
         "BriefDescription": "Speculative and retired indirect return branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
         "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.",
@@ -71,8 +57,6 @@
     },
     {
         "BriefDescription": "Not taken macro-conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
         "PublicDescription": "This event counts not taken macro-conditional branch instructions.",
@@ -81,8 +65,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired macro-conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
         "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions.",
@@ -91,8 +73,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
         "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.",
@@ -101,8 +81,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired direct near calls",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
         "PublicDescription": "This event counts taken speculative and retired direct near calls.",
@@ -111,8 +89,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
         "PublicDescription": "This event counts taken speculative and retired indirect branches excluding calls and return branches.",
@@ -121,8 +97,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect calls",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
         "PublicDescription": "This event counts taken speculative and retired indirect calls including both register and memory indirect.",
@@ -131,8 +105,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
         "PublicDescription": "This event counts taken speculative and retired indirect branches that have a return mnemonic.",
@@ -141,8 +113,6 @@
     },
     {
         "BriefDescription": "All (macro) branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "PublicDescription": "This event counts all (macro) branch instructions retired.",
@@ -150,8 +120,6 @@
     },
     {
         "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDW98",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
@@ -162,8 +130,6 @@
     },
     {
         "BriefDescription": "Conditional branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -173,8 +139,6 @@
     },
     {
         "BriefDescription": "Far branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDW98",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.FAR_BRANCH",
@@ -184,8 +148,6 @@
     },
     {
         "BriefDescription": "Direct and indirect near call instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -195,8 +157,6 @@
     },
     {
         "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
         "PEBS": "1",
@@ -206,8 +166,6 @@
     },
     {
         "BriefDescription": "Return instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_RETURN",
         "PEBS": "1",
@@ -217,8 +175,6 @@
     },
     {
         "BriefDescription": "Taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
@@ -228,8 +184,6 @@
     },
     {
         "BriefDescription": "Not taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NOT_TAKEN",
         "PublicDescription": "This event counts not taken branch instructions retired.",
@@ -238,8 +192,6 @@
     },
     {
         "BriefDescription": "Speculative and retired mispredicted macro conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_BRANCHES",
         "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.",
@@ -248,8 +200,6 @@
     },
     {
         "BriefDescription": "Speculative and retired mispredicted macro conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
         "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.",
@@ -258,8 +208,6 @@
     },
     {
         "BriefDescription": "Mispredicted indirect branches excluding calls and returns",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
         "PublicDescription": "This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.",
@@ -268,8 +216,6 @@
     },
     {
         "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
         "PublicDescription": "This event counts not taken speculative and retired mispredicted macro conditional branch instructions.",
@@ -278,8 +224,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
         "PublicDescription": "This event counts taken speculative and retired mispredicted macro conditional branch instructions.",
@@ -288,8 +232,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
         "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.",
@@ -298,8 +240,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect calls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
         "SampleAfterValue": "200003",
@@ -307,8 +247,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
         "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.",
@@ -317,8 +255,6 @@
     },
     {
         "BriefDescription": "All mispredicted macro branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PublicDescription": "This event counts all mispredicted macro branch instructions retired.",
@@ -326,8 +262,6 @@
     },
     {
         "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
         "PEBS": "2",
@@ -337,8 +271,6 @@
     },
     {
         "BriefDescription": "Mispredicted conditional branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -348,8 +280,6 @@
     },
     {
         "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
@@ -359,8 +289,6 @@
     },
     {
         "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.RET",
         "PEBS": "1",
@@ -370,8 +298,6 @@
     },
     {
         "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "100003",
@@ -379,8 +305,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
         "PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.",
@@ -390,8 +314,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
         "SampleAfterValue": "100003",
@@ -399,8 +321,6 @@
     },
     {
         "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "100003",
@@ -408,8 +328,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the core is not in halt state.",
-        "Counter": "Fixed counter 2",
-        "CounterHTOff": "Fixed counter 2",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
         "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
         "SampleAfterValue": "2000003",
@@ -417,8 +335,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
         "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
@@ -428,8 +344,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
         "SampleAfterValue": "100003",
@@ -437,8 +351,6 @@
     },
     {
         "BriefDescription": "Core cycles when the thread is not in halt state",
-        "Counter": "Fixed counter 1",
-        "CounterHTOff": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD",
         "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
         "SampleAfterValue": "2000003",
@@ -447,16 +359,12 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
-        "Counter": "Fixed counter 1",
-        "CounterHTOff": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Thread cycles when thread is not in halt state",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
         "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
@@ -465,16 +373,12 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "8",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
@@ -483,8 +387,6 @@
     },
     {
         "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "8",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
@@ -494,8 +396,6 @@
     },
     {
         "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
@@ -504,8 +404,6 @@
     },
     {
         "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
@@ -515,8 +413,6 @@
     },
     {
         "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
@@ -526,8 +422,6 @@
     },
     {
         "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
@@ -536,8 +430,6 @@
     },
     {
         "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
@@ -547,8 +439,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "12",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
@@ -557,8 +447,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "12",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
@@ -568,8 +456,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "5",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
@@ -578,8 +464,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "5",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
@@ -589,8 +473,6 @@
     },
     {
         "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "6",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",
@@ -600,8 +482,6 @@
     },
     {
         "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "6",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
@@ -610,8 +490,6 @@
     },
     {
         "BriefDescription": "Total execution stalls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
@@ -620,8 +498,6 @@
     },
     {
         "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.LCP",
         "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.",
@@ -630,8 +506,6 @@
     },
     {
         "BriefDescription": "Instructions retired from execution.",
-        "Counter": "Fixed counter 0",
-        "CounterHTOff": "Fixed counter 0",
         "EventName": "INST_RETIRED.ANY",
         "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
         "SampleAfterValue": "2000003",
@@ -639,8 +513,6 @@
     },
     {
         "BriefDescription": "Number of instructions retired. General Counter   - architectural event",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM61",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.ANY_P",
@@ -649,8 +521,6 @@
     },
     {
         "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
-        "Counter": "1",
-        "CounterHTOff": "1",
         "Errata": "BDM11, BDM55",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.PREC_DIST",
@@ -661,8 +531,6 @@
     },
     {
         "BriefDescription": "FP operations  retired. X87 FP operations that have no exceptions:",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.X87",
         "PublicDescription": "This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.",
@@ -671,8 +539,6 @@
     },
     {
         "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RAT_STALL_CYCLES",
         "PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.",
@@ -681,8 +547,6 @@
     },
     {
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES",
@@ -693,8 +557,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
@@ -703,8 +565,6 @@
     },
     {
         "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.NO_SR",
         "SampleAfterValue": "100003",
@@ -712,8 +572,6 @@
     },
     {
         "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.STORE_FORWARD",
         "PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.",
@@ -722,8 +580,6 @@
     },
     {
         "BriefDescription": "False dependencies in MOB due to partial compare",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x07",
         "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
         "PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",
@@ -732,8 +588,6 @@
     },
     {
         "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4C",
         "EventName": "LOAD_HIT_PRE.HW_PF",
         "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.",
@@ -742,8 +596,6 @@
     },
     {
         "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4c",
         "EventName": "LOAD_HIT_PRE.SW_PF",
         "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.",
@@ -752,8 +604,6 @@
     },
     {
         "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_4_UOPS",
@@ -762,8 +612,6 @@
     },
     {
         "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_ACTIVE",
@@ -772,8 +620,6 @@
     },
     {
         "BriefDescription": "Number of Uops delivered by the LSD.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA8",
         "EventName": "LSD.UOPS",
         "SampleAfterValue": "2000003",
@@ -781,8 +627,6 @@
     },
     {
         "BriefDescription": "Number of machine clears (nukes) of any type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xC3",
@@ -792,8 +636,6 @@
     },
     {
         "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.CYCLES",
         "PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.",
@@ -802,8 +644,6 @@
     },
     {
         "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MASKMOV",
         "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",
@@ -812,8 +652,6 @@
     },
     {
         "BriefDescription": "Self-modifying code (SMC) detected.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.SMC",
         "PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.",
@@ -822,8 +660,6 @@
     },
     {
         "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.INT_ELIMINATED",
         "SampleAfterValue": "1000003",
@@ -831,8 +667,6 @@
     },
     {
         "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",
         "SampleAfterValue": "1000003",
@@ -840,8 +674,6 @@
     },
     {
         "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",
         "SampleAfterValue": "100003",
@@ -849,8 +681,6 @@
     },
     {
         "BriefDescription": "Resource-related stall cycles",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa2",
         "EventName": "RESOURCE_STALLS.ANY",
         "PublicDescription": "This event counts resource-related stall cycles.",
@@ -859,8 +689,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to re-order buffer full.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ROB",
         "PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.",
@@ -869,8 +697,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no eligible RS entry available.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.RS",
         "PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
@@ -879,8 +705,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.SB",
         "PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
@@ -889,8 +713,6 @@
     },
     {
         "BriefDescription": "Count cases of saving new LBR",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCC",
         "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
         "PublicDescription": "This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.",
@@ -899,8 +721,6 @@
     },
     {
         "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5E",
         "EventName": "RS_EVENTS.EMPTY_CYCLES",
         "PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
@@ -909,8 +729,6 @@
     },
     {
         "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5E",
@@ -921,8 +739,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_0",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
@@ -931,8 +747,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 1",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_1",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
@@ -941,8 +755,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_2",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
@@ -951,8 +763,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_3",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
@@ -961,8 +771,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 4",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_4",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
@@ -971,8 +779,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 5",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_5",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
@@ -981,8 +787,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 6",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_6",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
@@ -991,8 +795,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 7",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_7",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
@@ -1001,8 +803,6 @@
     },
     {
         "BriefDescription": "Number of uops executed on the core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE",
         "PublicDescription": "Number of uops executed from any thread.",
@@ -1011,8 +811,6 @@
     },
     {
         "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@@ -1021,8 +819,6 @@
     },
     {
         "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@@ -1031,8 +827,6 @@
     },
     {
         "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@@ -1041,8 +835,6 @@
     },
     {
         "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@@ -1051,8 +843,6 @@
     },
     {
         "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
         "Invert": "1",
@@ -1061,8 +851,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 1 uop was executed per-thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
@@ -1071,8 +859,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 2 uops were executed per-thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
@@ -1081,8 +867,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 3 uops were executed per-thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
@@ -1091,8 +875,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 4 uops were executed per-thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
@@ -1101,8 +883,6 @@
     },
     {
         "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.STALL_CYCLES",
@@ -1113,8 +893,6 @@
     },
     {
         "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.THREAD",
         "PublicDescription": "Number of uops to be executed per-thread each cycle.",
@@ -1123,8 +901,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_0",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
@@ -1134,8 +910,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are exectuted in port 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE",
         "SampleAfterValue": "2000003",
@@ -1143,8 +917,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 1",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_1",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
@@ -1154,8 +926,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are exectuted in port 1.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE",
         "SampleAfterValue": "2000003",
@@ -1163,8 +933,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_2",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
@@ -1174,8 +942,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE",
         "SampleAfterValue": "2000003",
@@ -1183,8 +949,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_3",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
@@ -1194,8 +958,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE",
         "SampleAfterValue": "2000003",
@@ -1203,8 +965,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 4",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_4",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
@@ -1214,8 +974,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are exectuted in port 4.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE",
         "SampleAfterValue": "2000003",
@@ -1223,8 +981,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 5",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_5",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
@@ -1234,8 +990,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are exectuted in port 5.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE",
         "SampleAfterValue": "2000003",
@@ -1243,8 +997,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 6",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_6",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
@@ -1254,8 +1006,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are exectuted in port 6.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE",
         "SampleAfterValue": "2000003",
@@ -1263,8 +1013,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 7",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_7",
         "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
@@ -1274,8 +1022,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 7.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE",
         "SampleAfterValue": "2000003",
@@ -1283,8 +1029,6 @@
     },
     {
         "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.ANY",
         "PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).",
@@ -1293,8 +1037,6 @@
     },
     {
         "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.FLAGS_MERGE",
         "PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.",
@@ -1303,8 +1045,6 @@
     },
     {
         "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.SINGLE_MUL",
         "SampleAfterValue": "2000003",
@@ -1312,8 +1052,6 @@
     },
     {
         "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.SLOW_LEA",
         "SampleAfterValue": "2000003",
@@ -1321,8 +1059,6 @@
     },
     {
         "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -1333,8 +1069,6 @@
     },
     {
         "BriefDescription": "Actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ALL",
         "PEBS": "1",
@@ -1344,8 +1078,6 @@
     },
     {
         "BriefDescription": "Retirement slots used.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
         "PEBS": "1",
@@ -1355,8 +1087,6 @@
     },
     {
         "BriefDescription": "Cycles without actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -1367,8 +1097,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 10 actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "16",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json
index 449fa723d0aa7..38eaac5afd4b9 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json
@@ -1,789 +1,1100 @@
 [
     {
-        "BriefDescription": "Bounce Control",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA",
-        "EventName": "UNC_C_BOUNCE_CONTROL",
+        "BriefDescription": "LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.CODE_LLC_PREFETCH",
+        "Filter": "filter_opc=0x191",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Uncore Clocks",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_C_CLOCKTICKS",
+        "BriefDescription": "LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.DATA_LLC_PREFETCH",
+        "Filter": "filter_opc=0x192",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Counter 0 Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1F",
-        "EventName": "UNC_C_COUNTER0_OCCUPANCY",
+        "BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.DATA_READ",
+        "Filter": "filter_opc=0x182",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "FaST wire asserted",
-        "Counter": "0,1",
-        "EventCode": "0x9",
-        "EventName": "UNC_C_FAST_ASSERTED",
+        "BriefDescription": "MMIO reads. Derived from unc_c_tor_inserts.miss_opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.MMIO_READ",
+        "Filter": "filter_opc=0x187,filter_nc=1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Cache Lookups; Data Read Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x34",
-        "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
+        "BriefDescription": "MMIO writes. Derived from unc_c_tor_inserts.miss_opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.MMIO_WRITE",
+        "Filter": "filter_opc=0x18f,filter_nc=1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+        "ScaleUnit": "64Bytes",
         "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Cache Lookups; Write Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x34",
-        "EventName": "UNC_C_LLC_LOOKUP.WRITE",
+        "BriefDescription": "PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.PCIE_NON_SNOOP_WRITE",
+        "Filter": "filter_opc=0x1c8,filter_tid=0x3e",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Cache Lookups; External Snoop Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x34",
-        "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
+        "BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.PCIE_READ",
+        "Filter": "filter_opc=0x19e",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x34",
-        "EventName": "UNC_C_LLC_LOOKUP.ANY",
-        "Filter": "filter_state=0x1",
+        "BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.PCIE_WRITE",
+        "Filter": "filter_opc=0x1c8",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
         "ScaleUnit": "64Bytes",
-        "UMask": "0x11",
+        "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Cache Lookups; Lookups that Match NID",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x34",
-        "EventName": "UNC_C_LLC_LOOKUP.NID",
+        "BriefDescription": "LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.RFO_LLC_PREFETCH",
+        "Filter": "filter_opc=0x190",
         "PerPkg": "1",
-        "UMask": "0x41",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Cache Lookups; Any Read Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x34",
-        "EventName": "UNC_C_LLC_LOOKUP.READ",
+        "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.miss_opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.UNCACHEABLE",
+        "Filter": "filter_opc=0x187",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "M line evictions from LLC (writebacks to memory)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
+        "BriefDescription": "L2 demand and L2 prefetch code references to LLC. Derived from unc_c_tor_inserts.opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_REFERENCES.CODE_LLC_PREFETCH",
+        "Filter": "filter_opc=0x181",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
         "ScaleUnit": "64Bytes",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Lines Victimized; Lines in E state",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
+        "BriefDescription": "PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE",
+        "Filter": "filter_opc=0x180,filter_tid=0x3e",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+        "UMask": "0x1",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Lines Victimized; Lines in S State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_C_LLC_VICTIMS.I_STATE",
+        "BriefDescription": "PCIe read current. Derived from unc_c_tor_inserts.opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_REFERENCES.PCIE_READ",
+        "Filter": "filter_opc=0x19e",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x1",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Lines Victimized",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_C_LLC_VICTIMS.F_STATE",
+        "BriefDescription": "PCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_REFERENCES.PCIE_WRITE",
+        "Filter": "filter_opc=0x1c8,filter_tid=0x3e",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x1",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Lines Victimized; Victimized Lines that Match NID",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_C_LLC_VICTIMS.NID",
+        "BriefDescription": "Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_REFERENCES.STREAMING_FULL",
+        "Filter": "filter_opc=0x18c",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x1",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Lines Victimized",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_C_LLC_VICTIMS.MISS",
+        "BriefDescription": "Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_REFERENCES.STREAMING_PARTIAL",
+        "Filter": "filter_opc=0x18d",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x1",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_C_MISC.RSPI_WAS_FSE",
+        "BriefDescription": "Bounce Control",
+        "EventCode": "0xA",
+        "EventName": "UNC_C_BOUNCE_CONTROL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "UNC_C_BOUNCE_CONTROL",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Cbo Misc; Write Combining Aliasing",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_C_MISC.WC_ALIASING",
+        "BriefDescription": "Uncore Clocks",
+        "EventName": "UNC_C_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "UNC_C_CLOCKTICKS",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Cbo Misc",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_C_MISC.STARTED",
+        "BriefDescription": "Counter 0 Occupancy",
+        "EventCode": "0x1F",
+        "EventName": "UNC_C_COUNTER0_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0.   The filtering available is found in the control register - threshold, invert and edge detect.   E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Cbo Misc; RFO HitS",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_C_MISC.RFO_HIT_S",
+        "BriefDescription": "FaST wire asserted",
+        "EventCode": "0x9",
+        "EventName": "UNC_C_FAST_ASSERTED",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of cycles either the local distress or incoming distress signals are asserted.  Incoming distress includes both up and dn.",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Cbo Misc; Clean Victim with raw CV=0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_C_MISC.CVZERO_PREFETCH_VICTIM",
+        "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
+        "EventCode": "0x34",
+        "EventName": "UNC_C_LLC_LOOKUP.ANY",
+        "Filter": "filter_state=0x1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ.  This does not include lookups originating from the ISMQ.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x11",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_C_MISC.CVZERO_PREFETCH_MISS",
+        "BriefDescription": "Cache Lookups; Data Read Request",
+        "EventCode": "0x34",
+        "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions",
+        "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "AD Ring In Use; Up and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1B",
-        "EventName": "UNC_C_RING_AD_USED.UP_EVEN",
+        "BriefDescription": "Cache Lookups; Lookups that Match NID",
+        "EventCode": "0x34",
+        "EventName": "UNC_C_LLC_LOOKUP.NID",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Qualify one of the other subevents by the Target NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.   In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+        "UMask": "0x41",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "AD Ring In Use; Up and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1B",
-        "EventName": "UNC_C_RING_AD_USED.UP_ODD",
+        "BriefDescription": "Cache Lookups; Any Read Request",
+        "EventCode": "0x34",
+        "EventName": "UNC_C_LLC_LOOKUP.READ",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions",
+        "UMask": "0x21",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "AD Ring In Use; Down and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1B",
-        "EventName": "UNC_C_RING_AD_USED.DOWN_EVEN",
+        "BriefDescription": "Cache Lookups; External Snoop Request",
+        "EventCode": "0x34",
+        "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.",
+        "UMask": "0x9",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "AD Ring In Use; Down and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1B",
-        "EventName": "UNC_C_RING_AD_USED.DOWN_ODD",
+        "BriefDescription": "Cache Lookups; Write Requests",
+        "EventCode": "0x34",
+        "EventName": "UNC_C_LLC_LOOKUP.WRITE",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC  This includes all write transactions -- both Cachable and UC.",
+        "UMask": "0x5",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "AD Ring In Use; Up",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1B",
-        "EventName": "UNC_C_RING_AD_USED.UP",
+        "BriefDescription": "Lines Victimized; Lines in E state",
+        "EventCode": "0x37",
+        "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x2",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "AD Ring In Use; Down",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1B",
-        "EventName": "UNC_C_RING_AD_USED.DOWN",
+        "BriefDescription": "Lines Victimized",
+        "EventCode": "0x37",
+        "EventName": "UNC_C_LLC_VICTIMS.F_STATE",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x8",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "AD Ring In Use; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1B",
-        "EventName": "UNC_C_RING_AD_USED.ALL",
+        "BriefDescription": "Lines Victimized; Lines in S State",
+        "EventCode": "0x37",
+        "EventName": "UNC_C_LLC_VICTIMS.I_STATE",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x4",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "AK Ring In Use; Up and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1C",
-        "EventName": "UNC_C_RING_AK_USED.UP_EVEN",
+        "BriefDescription": "Lines Victimized",
+        "EventCode": "0x37",
+        "EventName": "UNC_C_LLC_VICTIMS.MISS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x10",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "AK Ring In Use; Up and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1C",
-        "EventName": "UNC_C_RING_AK_USED.UP_ODD",
+        "BriefDescription": "M line evictions from LLC (writebacks to memory)",
+        "EventCode": "0x37",
+        "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x1",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "Lines Victimized; Victimized Lines that Match NID",
+        "EventCode": "0x37",
+        "EventName": "UNC_C_LLC_VICTIMS.NID",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.; Qualify one of the other subevents by the Target NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.   In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+        "UMask": "0x40",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=0",
+        "EventCode": "0x39",
+        "EventName": "UNC_C_MISC.CVZERO_PREFETCH_MISS",
+        "PerPkg": "1",
+        "PublicDescription": "Miscellaneous events in the Cbo.",
+        "UMask": "0x20",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "Cbo Misc; Clean Victim with raw CV=0",
+        "EventCode": "0x39",
+        "EventName": "UNC_C_MISC.CVZERO_PREFETCH_VICTIM",
+        "PerPkg": "1",
+        "PublicDescription": "Miscellaneous events in the Cbo.",
+        "UMask": "0x10",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "Cbo Misc; RFO HitS",
+        "EventCode": "0x39",
+        "EventName": "UNC_C_MISC.RFO_HIT_S",
+        "PerPkg": "1",
+        "PublicDescription": "Miscellaneous events in the Cbo.; Number of times that an RFO hit in S state.  This is useful for determining if it might be good for a workload to use RspIWB instead of RspSWB.",
+        "UMask": "0x8",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
+        "EventCode": "0x39",
+        "EventName": "UNC_C_MISC.RSPI_WAS_FSE",
+        "PerPkg": "1",
+        "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction.  This is useful because this information is lost in the PRE encodings.",
+        "UMask": "0x1",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "Cbo Misc",
+        "EventCode": "0x39",
+        "EventName": "UNC_C_MISC.STARTED",
+        "PerPkg": "1",
+        "PublicDescription": "Miscellaneous events in the Cbo.",
+        "UMask": "0x4",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "Cbo Misc; Write Combining Aliasing",
+        "EventCode": "0x39",
+        "EventName": "UNC_C_MISC.WC_ALIASING",
+        "PerPkg": "1",
+        "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write.  This occurs when there is WC aliasing.",
+        "UMask": "0x2",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "LRU Queue; LRU Age 0",
+        "EventCode": "0x3C",
+        "EventName": "UNC_C_QLRU.AGE0",
+        "PerPkg": "1",
+        "PublicDescription": "How often age was set to 0",
+        "UMask": "0x1",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "LRU Queue; LRU Age 1",
+        "EventCode": "0x3C",
+        "EventName": "UNC_C_QLRU.AGE1",
+        "PerPkg": "1",
+        "PublicDescription": "How often age was set to 1",
+        "UMask": "0x2",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "LRU Queue; LRU Age 2",
+        "EventCode": "0x3C",
+        "EventName": "UNC_C_QLRU.AGE2",
+        "PerPkg": "1",
+        "PublicDescription": "How often age was set to 2",
+        "UMask": "0x4",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "LRU Queue; LRU Age 3",
+        "EventCode": "0x3C",
+        "EventName": "UNC_C_QLRU.AGE3",
+        "PerPkg": "1",
+        "PublicDescription": "How often age was set to 3",
+        "UMask": "0x8",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "LRU Queue; LRU Bits Decremented",
+        "EventCode": "0x3C",
+        "EventName": "UNC_C_QLRU.LRU_DECREMENT",
+        "PerPkg": "1",
+        "PublicDescription": "How often all LRU bits were decremented by 1",
+        "UMask": "0x10",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "LRU Queue; Non-0 Aged Victim",
+        "EventCode": "0x3C",
+        "EventName": "UNC_C_QLRU.VICTIM_NON_ZERO",
+        "PerPkg": "1",
+        "PublicDescription": "How often we picked a victim that had a non-zero age",
+        "UMask": "0x20",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "AD Ring In Use; All",
+        "EventCode": "0x1B",
+        "EventName": "UNC_C_RING_AD_USED.ALL",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0xf",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "AD Ring In Use; Down",
+        "EventCode": "0x1B",
+        "EventName": "UNC_C_RING_AD_USED.DOWN",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX-- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0xc",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "AD Ring In Use; Down and Even",
+        "EventCode": "0x1B",
+        "EventName": "UNC_C_RING_AD_USED.DOWN_EVEN",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
+        "UMask": "0x4",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "AD Ring In Use; Down and Odd",
+        "EventCode": "0x1B",
+        "EventName": "UNC_C_RING_AD_USED.DOWN_ODD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
+        "UMask": "0x8",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "AD Ring In Use; Up",
+        "EventCode": "0x1B",
+        "EventName": "UNC_C_RING_AD_USED.UP",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x3",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "AD Ring In Use; Up and Even",
+        "EventCode": "0x1B",
+        "EventName": "UNC_C_RING_AD_USED.UP_EVEN",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+        "UMask": "0x1",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "AD Ring In Use; Up and Odd",
+        "EventCode": "0x1B",
+        "EventName": "UNC_C_RING_AD_USED.UP_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
         "UMask": "0x2",
         "Unit": "CBO"
     },
+    {
+        "BriefDescription": "AK Ring In Use; All",
+        "EventCode": "0x1C",
+        "EventName": "UNC_C_RING_AK_USED.ALL",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0xf",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "AK Ring In Use; Down",
+        "EventCode": "0x1C",
+        "EventName": "UNC_C_RING_AK_USED.DOWN",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0xc",
+        "Unit": "CBO"
+    },
     {
         "BriefDescription": "AK Ring In Use; Down and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_C_RING_AK_USED.DOWN_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
         "UMask": "0x4",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "AK Ring In Use; Down and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_C_RING_AK_USED.DOWN_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "AK Ring In Use; Up",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_C_RING_AK_USED.UP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
         "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "AK Ring In Use; Down",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "AK Ring In Use; Up and Even",
         "EventCode": "0x1C",
-        "EventName": "UNC_C_RING_AK_USED.DOWN",
+        "EventName": "UNC_C_RING_AK_USED.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "AK Ring In Use; All",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "AK Ring In Use; Up and Odd",
         "EventCode": "0x1C",
-        "EventName": "UNC_C_RING_AK_USED.ALL",
+        "EventName": "UNC_C_RING_AK_USED.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+        "UMask": "0x2",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "BL Ring in Use; Up and Even",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "BL Ring in Use; Down",
         "EventCode": "0x1D",
-        "EventName": "UNC_C_RING_BL_USED.UP_EVEN",
+        "EventName": "UNC_C_RING_BL_USED.ALL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0xf",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "BL Ring in Use; Up and Odd",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "BL Ring in Use; Down",
         "EventCode": "0x1D",
-        "EventName": "UNC_C_RING_BL_USED.UP_ODD",
+        "EventName": "UNC_C_RING_BL_USED.DOWN",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0xc",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Down and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_C_RING_BL_USED.DOWN_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
         "UMask": "0x4",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Down and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_C_RING_BL_USED.DOWN_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Up",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_C_RING_BL_USED.UP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
         "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "BL Ring in Use; Down",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "BL Ring in Use; Up and Even",
         "EventCode": "0x1D",
-        "EventName": "UNC_C_RING_BL_USED.DOWN",
+        "EventName": "UNC_C_RING_BL_USED.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "BL Ring in Use; Down",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "BL Ring in Use; Up and Odd",
         "EventCode": "0x1D",
-        "EventName": "UNC_C_RING_BL_USED.ALL",
+        "EventName": "UNC_C_RING_BL_USED.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+        "UMask": "0x2",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.; AD",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_C_RING_BOUNCES.AD",
         "PerPkg": "1",
+        "PublicDescription": "UNC_C_RING_BOUNCES.AD",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.; AK",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_C_RING_BOUNCES.AK",
         "PerPkg": "1",
+        "PublicDescription": "UNC_C_RING_BOUNCES.AK",
         "UMask": "0x2",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.; BL",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_C_RING_BOUNCES.BL",
         "PerPkg": "1",
+        "PublicDescription": "UNC_C_RING_BOUNCES.BL",
         "UMask": "0x4",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
         "EventCode": "0x5",
         "EventName": "UNC_C_RING_BOUNCES.IV",
         "PerPkg": "1",
+        "PublicDescription": "UNC_C_RING_BOUNCES.IV",
         "UMask": "0x10",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Any",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
         "EventName": "UNC_C_RING_IV_USED.ANY",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in BDX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+        "UMask": "0xf",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Any",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
-        "EventName": "UNC_C_RING_IV_USED.UP",
+        "EventName": "UNC_C_RING_IV_USED.DN",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in BDX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+        "UMask": "0xc",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Down",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
         "EventName": "UNC_C_RING_IV_USED.DOWN",
         "PerPkg": "1",
-        "UMask": "0xCC",
+        "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in BDX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters for Down polarity",
+        "UMask": "0xcc",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Any",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
-        "EventName": "UNC_C_RING_IV_USED.DN",
-        "PerPkg": "1",
-        "UMask": "0xC",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x7",
-        "EventName": "UNC_C_RING_SRC_THRTL",
+        "EventName": "UNC_C_RING_IV_USED.UP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in BDX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+        "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_C_RxR_EXT_STARVED.IRQ",
+        "BriefDescription": "AD",
+        "EventCode": "0x6",
+        "EventName": "UNC_C_RING_SINK_STARVED.AD",
         "PerPkg": "1",
+        "PublicDescription": "UNC_C_RING_SINK_STARVED.AD",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_C_RxR_EXT_STARVED.IPQ",
+        "BriefDescription": "AK",
+        "EventCode": "0x6",
+        "EventName": "UNC_C_RING_SINK_STARVED.AK",
         "PerPkg": "1",
+        "PublicDescription": "UNC_C_RING_SINK_STARVED.AK",
         "UMask": "0x2",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Ingress Arbiter Blocking Cycles; PRQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_C_RxR_EXT_STARVED.PRQ",
+        "BriefDescription": "BL",
+        "EventCode": "0x6",
+        "EventName": "UNC_C_RING_SINK_STARVED.BL",
         "PerPkg": "1",
+        "PublicDescription": "UNC_C_RING_SINK_STARVED.BL",
         "UMask": "0x4",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
+        "BriefDescription": "IV",
+        "EventCode": "0x6",
+        "EventName": "UNC_C_RING_SINK_STARVED.IV",
         "PerPkg": "1",
+        "PublicDescription": "UNC_C_RING_SINK_STARVED.IV",
         "UMask": "0x8",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Ingress Allocations; IRQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_C_RxR_INSERTS.IRQ",
+        "BriefDescription": "Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic.",
+        "EventCode": "0x7",
+        "EventName": "UNC_C_RING_SRC_THRTL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "UNC_C_RING_SRC_THRTL",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Ingress Allocations; IRQ Rejected",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_C_RxR_INSERTS.IRQ_REJ",
-        "PerPkg": "1",
-        "UMask": "0x2",
+        "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ",
+        "EventCode": "0x12",
+        "EventName": "UNC_C_RxR_EXT_STARVED.IPQ",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally startved and therefore we are blocking the IRQ.",
+        "UMask": "0x2",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ",
+        "EventCode": "0x12",
+        "EventName": "UNC_C_RxR_EXT_STARVED.IRQ",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; IRQ is externally starved and therefore we are blocking the IPQ.",
+        "UMask": "0x1",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID",
+        "EventCode": "0x12",
+        "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; Number of times that the ISMQ Bid.",
+        "UMask": "0x8",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "Ingress Arbiter Blocking Cycles; PRQ",
+        "EventCode": "0x12",
+        "EventName": "UNC_C_RxR_EXT_STARVED.PRQ",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.",
+        "UMask": "0x4",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Ingress Allocations; IPQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_C_RxR_INSERTS.IPQ",
         "PerPkg": "1",
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
         "UMask": "0x4",
         "Unit": "CBO"
     },
+    {
+        "BriefDescription": "Ingress Allocations; IRQ",
+        "EventCode": "0x13",
+        "EventName": "UNC_C_RxR_INSERTS.IRQ",
+        "PerPkg": "1",
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x1",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "Ingress Allocations; IRQ Rejected",
+        "EventCode": "0x13",
+        "EventName": "UNC_C_RxR_INSERTS.IRQ_REJ",
+        "PerPkg": "1",
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x2",
+        "Unit": "CBO"
+    },
     {
         "BriefDescription": "Ingress Allocations; PRQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_C_RxR_INSERTS.PRQ",
         "PerPkg": "1",
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
         "UMask": "0x10",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Ingress Allocations; PRQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_C_RxR_INSERTS.PRQ_REJ",
         "PerPkg": "1",
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
         "UMask": "0x20",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Probe Queue Retries; Any Reject",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x31",
-        "EventName": "UNC_C_RxR_IPQ_RETRY.ANY",
+        "BriefDescription": "Ingress Internal Starvation Cycles; IPQ",
+        "EventCode": "0x14",
+        "EventName": "UNC_C_RxR_INT_STARVED.IPQ",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IPQ in Internal Starvation.",
+        "UMask": "0x4",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "Ingress Internal Starvation Cycles; IRQ",
+        "EventCode": "0x14",
+        "EventName": "UNC_C_RxR_INT_STARVED.IRQ",
         "PerPkg": "1",
+        "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IRQ in Internal Starvation.",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Probe Queue Retries; No Egress Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x31",
-        "EventName": "UNC_C_RxR_IPQ_RETRY.FULL",
+        "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ",
+        "EventCode": "0x14",
+        "EventName": "UNC_C_RxR_INT_STARVED.ISMQ",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the ISMQ in Internal Starvation.",
+        "UMask": "0x8",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "Ingress Internal Starvation Cycles; PRQ",
+        "EventCode": "0x14",
+        "EventName": "UNC_C_RxR_INT_STARVED.PRQ",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.",
+        "UMask": "0x10",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Probe Queue Retries; Address Conflict",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from an address conflicts.  Address conflicts out of the IPQ should be rare.  They will generally only occur if two different sockets are sending requests to the same address at the same time.  This is a true conflict case, unlike the IPQ Address Conflict which is commonly caused by prefetching characteristics.",
         "UMask": "0x4",
         "Unit": "CBO"
     },
+    {
+        "BriefDescription": "Probe Queue Retries; Any Reject",
+        "EventCode": "0x31",
+        "EventName": "UNC_C_RxR_IPQ_RETRY.ANY",
+        "PerPkg": "1",
+        "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject.  TOR rejects from the IPQ can be caused by the Egress being full or Address Conflicts.",
+        "UMask": "0x1",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "Probe Queue Retries; No Egress Credits",
+        "EventCode": "0x31",
+        "EventName": "UNC_C_RxR_IPQ_RETRY.FULL",
+        "PerPkg": "1",
+        "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from the Egress being full.  IPQ requests make use of the AD Egress for regular responses, the BL egress to forward data, and the AK egress to return credits.",
+        "UMask": "0x2",
+        "Unit": "CBO"
+    },
     {
         "BriefDescription": "Probe Queue Retries; No QPI Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.",
         "UMask": "0x10",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Probe Queue Retries; No AD Sbo Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "UNC_C_RxR_IPQ_RETRY2.AD_SBO",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo.",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Probe Queue Retries; Target Node Filter",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "UNC_C_RxR_IPQ_RETRY2.TARGET",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
         "UMask": "0x40",
         "Unit": "CBO"
     },
+    {
+        "BriefDescription": "Ingress Request Queue Rejects; Address Conflict",
+        "EventCode": "0x32",
+        "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that a request from the IRQ was retried because of an address match in the TOR.  In order to maintain coherency, requests to the same address are not allowed to pass each other up in the Cbo.  Therefore, if there is an outstanding request to a given address, one cannot issue another request to that address until it is complete.  This comes up most commonly with prefetches.  Outstanding prefetches occasionally will not complete their memory fetch and a demand request to the same address will then sit in the IRQ and get retried until the prefetch fills the data into the LLC.  Therefore, it will not be uncommon to see this case in high bandwidth streaming workloads when the LLC Prefetcher in the core is enabled.",
+        "UMask": "0x4",
+        "Unit": "CBO"
+    },
     {
         "BriefDescription": "Ingress Request Queue Rejects; Any Reject",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.ANY",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of IRQ retries that occur.  Requests from the IRQ are retried if they are rejected from the TOR pipeline for a variety of reasons.  Some of the most common reasons include if the Egress is full, there are no RTIDs, or there is a Physical Address match to another outstanding request.",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; No Egress Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.FULL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that a request from the IRQ was retried because it failed to acquire an entry in the Egress.  The egress is the buffer that queues up for allocating onto the ring.  IRQ requests can make use of all four rings and all four Egresses.  If any of the queues that a given request needs to make use of are full, the request will be retried.",
         "UMask": "0x2",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Ingress Request Queue Rejects; Address Conflict",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits",
         "EventCode": "0x32",
-        "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
+        "EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO.  There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.",
+        "UMask": "0x20",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Ingress Request Queue Rejects; No RTIDs",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Ingress Request Queue Rejects",
         "EventCode": "0x32",
-        "EventName": "UNC_C_RxR_IRQ_RETRY.RTID",
+        "EventName": "UNC_C_RxR_IRQ_RETRY.NID",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Qualify one of the other subevents by a given RTID destination NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
+        "UMask": "0x40",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS",
         "PerPkg": "1",
+        "PublicDescription": "Number of requests rejects because of lack of QPI Ingress credits.  These credits are required in order to send transactions to the QPI agent.  Please see the QPI_IGR_CREDITS events for more information.",
         "UMask": "0x10",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Ingress Request Queue Rejects; No RTIDs",
         "EventCode": "0x32",
-        "EventName": "UNC_C_RxR_IRQ_RETRY.NID",
+        "EventName": "UNC_C_RxR_IRQ_RETRY.RTID",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of times that requests from the IRQ were retried because there were no RTIDs available.  RTIDs are required after a request misses the LLC and needs to send snoops and/or requests to memory.  If there are no RTIDs available, requests will queue up in the IRQ and retry until one becomes available.  Note that there are multiple RTID pools for the different sockets.  There may be cases where the local RTIDs are all used, but requests destined for remote memory can still acquire an RTID because there are remote RTIDs available.  This event does not provide any filtering for this case.",
+        "UMask": "0x8",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; No AD Sbo Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_C_RxR_IRQ_RETRY2.AD_SBO",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo.",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; No BL Sbo Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_C_RxR_IRQ_RETRY2.BL_SBO",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an BL packet to the Sbo.",
         "UMask": "0x2",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; Target Node Filter",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_C_RxR_IRQ_RETRY2.TARGET",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
         "UMask": "0x40",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "ISMQ Retries; Any Reject",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_C_RxR_ISMQ_RETRY.ANY",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the total number of times that a request from the ISMQ retried because of a TOR reject.  ISMQ requests generally will not need to retry (or at least ISMQ retries are less common than IRQ retries).  ISMQ requests will retry if they are not able to acquire a needed Egress credit to get onto the ring, or for cache evictions that need to acquire an RTID.  Most ISMQ requests already have an RTID, so eviction retries will be less common here.",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "ISMQ Retries; No Egress Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_C_RxR_ISMQ_RETRY.FULL",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by a lack of Egress credits. The egress is the buffer that queues up for allocating onto the ring.  If any of the Egress queues that a given request needs to make use of are full, the request will be retried.",
         "UMask": "0x2",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "ISMQ Retries; No RTIDs",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "ISMQ Retries; No IIO Credits",
         "EventCode": "0x33",
-        "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID",
+        "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO.  There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.",
+        "UMask": "0x20",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "ISMQ Retries; No QPI Credits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "ISMQ Retries",
         "EventCode": "0x33",
-        "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
+        "EventName": "UNC_C_RxR_ISMQ_RETRY.NID",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
+        "UMask": "0x40",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "ISMQ Retries; No IIO Credits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "ISMQ Retries; No QPI Credits",
         "EventCode": "0x33",
-        "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
+        "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x10",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "ISMQ Retries",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "ISMQ Retries; No RTIDs",
         "EventCode": "0x33",
-        "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS",
+        "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by no RTIDs.  M-state cache evictions are serviced through the ISMQ, and must acquire an RTID in order to write back to memory.  If no RTIDs are available, they will be retried.",
+        "UMask": "0x8",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "ISMQ Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
-        "EventName": "UNC_C_RxR_ISMQ_RETRY.NID",
+        "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
+        "UMask": "0x80",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "ISMQ Request Queue Rejects; No AD Sbo Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_C_RxR_ISMQ_RETRY2.AD_SBO",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an AD packet to the Sbo.",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "ISMQ Request Queue Rejects; No BL Sbo Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_C_RxR_ISMQ_RETRY2.BL_SBO",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an BL packet to the Sbo.",
         "UMask": "0x2",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "ISMQ Request Queue Rejects; Target Node Filter",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_C_RxR_ISMQ_RETRY2.TARGET",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that a request from the ISMQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
         "UMask": "0x40",
         "Unit": "CBO"
     },
+    {
+        "BriefDescription": "Ingress Occupancy; IPQ",
+        "EventCode": "0x11",
+        "EventName": "UNC_C_RxR_OCCUPANCY.IPQ",
+        "PerPkg": "1",
+        "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+        "UMask": "0x4",
+        "Unit": "CBO"
+    },
     {
         "BriefDescription": "Ingress Occupancy; IRQ",
         "EventCode": "0x11",
         "EventName": "UNC_C_RxR_OCCUPANCY.IRQ",
         "PerPkg": "1",
+        "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
         "UMask": "0x1",
         "Unit": "CBO"
     },
@@ -792,40 +1103,34 @@
         "EventCode": "0x11",
         "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJ",
         "PerPkg": "1",
+        "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
         "UMask": "0x2",
         "Unit": "CBO"
     },
-    {
-        "BriefDescription": "Ingress Occupancy; IPQ",
-        "EventCode": "0x11",
-        "EventName": "UNC_C_RxR_OCCUPANCY.IPQ",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "CBO"
-    },
     {
         "BriefDescription": "Ingress Occupancy; PRQ Rejects",
         "EventCode": "0x11",
         "EventName": "UNC_C_RxR_OCCUPANCY.PRQ_REJ",
         "PerPkg": "1",
+        "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
         "UMask": "0x20",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "SBo Credits Acquired; For AD Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3D",
         "EventName": "UNC_C_SBO_CREDITS_ACQUIRED.AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo credits acquired in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "SBo Credits Acquired; For BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3D",
         "EventName": "UNC_C_SBO_CREDITS_ACQUIRED.BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo credits acquired in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
         "UMask": "0x2",
         "Unit": "CBO"
     },
@@ -834,6 +1139,7 @@
         "EventCode": "0x3E",
         "EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo credits in use in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
         "UMask": "0x1",
         "Unit": "CBO"
     },
@@ -842,411 +1148,288 @@
         "EventCode": "0x3E",
         "EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo credits in use in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
         "UMask": "0x2",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; Opcode Match",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; All",
         "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.OPCODE",
+        "EventName": "UNC_C_TOR_INSERTS.ALL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR.    This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues.  The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger.  Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20.  Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.",
+        "UMask": "0x8",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; Evictions",
         "EventCode": "0x35",
-        "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE",
-        "Filter": "filter_opc=0x180,filter_tid=0x3e",
+        "EventName": "UNC_C_TOR_INSERTS.EVICTION",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Eviction transactions inserted into the TOR.  Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set.  They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).",
+        "UMask": "0x4",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "L2 demand and L2 prefetch code references to LLC. Derived from unc_c_tor_inserts.opcode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; Local Memory",
         "EventCode": "0x35",
-        "EventName": "LLC_REFERENCES.CODE_LLC_PREFETCH",
-        "Filter": "filter_opc=0x181",
+        "EventName": "UNC_C_TOR_INSERTS.LOCAL",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR that are satisifed by locally HOMed memory.",
+        "UMask": "0x28",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched",
         "EventCode": "0x35",
-        "EventName": "LLC_REFERENCES.STREAMING_FULL",
-        "Filter": "filter_opc=0x18c",
+        "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions, satisifed by an opcode,  inserted into the TOR that are satisifed by locally HOMed memory.",
+        "UMask": "0x21",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; Misses to Local Memory",
         "EventCode": "0x35",
-        "EventName": "LLC_REFERENCES.STREAMING_PARTIAL",
-        "Filter": "filter_opc=0x18d",
+        "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by locally HOMed memory.",
+        "UMask": "0x2a",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "PCIe read current. Derived from unc_c_tor_inserts.opcode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched",
         "EventCode": "0x35",
-        "EventName": "LLC_REFERENCES.PCIE_READ",
-        "Filter": "filter_opc=0x19e",
+        "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory.",
+        "UMask": "0x23",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "PCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; Miss Opcode Match",
         "EventCode": "0x35",
-        "EventName": "LLC_REFERENCES.PCIE_WRITE",
-        "Filter": "filter_opc=0x1c8,filter_tid=0x3e",
+        "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+        "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; Evictions",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; Misses to Remote Memory",
         "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.EVICTION",
+        "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by remote caches or remote memory.",
+        "UMask": "0x8a",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; All",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched",
         "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.ALL",
+        "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions, satisifed by an opcode,  inserted into the TOR that are satisifed by remote caches or remote memory.",
+        "UMask": "0x83",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; Writebacks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; NID Matched",
         "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.WB",
+        "EventName": "UNC_C_TOR_INSERTS.NID_ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.  In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+        "UMask": "0x48",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; Miss Opcode Match",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; NID Matched Evictions",
         "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE",
+        "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; NID matched eviction transactions inserted into the TOR.",
+        "UMask": "0x44",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; NID Matched Miss All",
         "EventCode": "0x35",
-        "EventName": "LLC_MISSES.DATA_READ",
-        "Filter": "filter_opc=0x182",
+        "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.",
+        "UMask": "0x4a",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.miss_opcode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss",
         "EventCode": "0x35",
-        "EventName": "LLC_MISSES.UNCACHEABLE",
-        "Filter": "filter_opc=0x187",
+        "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x3",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "MMIO reads. Derived from unc_c_tor_inserts.miss_opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "LLC_MISSES.MMIO_READ",
-        "Filter": "filter_opc=0x187,filter_nc=1",
-        "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x3",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "MMIO writes. Derived from unc_c_tor_inserts.miss_opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "LLC_MISSES.MMIO_WRITE",
-        "Filter": "filter_opc=0x18f,filter_nc=1",
-        "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x3",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "LLC_MISSES.RFO_LLC_PREFETCH",
-        "Filter": "filter_opc=0x190",
-        "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x3",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "LLC_MISSES.CODE_LLC_PREFETCH",
-        "Filter": "filter_opc=0x191",
-        "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x3",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "LLC_MISSES.DATA_LLC_PREFETCH",
-        "Filter": "filter_opc=0x192",
-        "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x3",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "LLC_MISSES.PCIE_READ",
-        "Filter": "filter_opc=0x19e",
-        "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x3",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "LLC_MISSES.PCIE_WRITE",
-        "Filter": "filter_opc=0x1c8",
-        "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x3",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "LLC_MISSES.PCIE_NON_SNOOP_WRITE",
-        "Filter": "filter_opc=0x1c8,filter_tid=0x3e",
-        "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode.",
+        "UMask": "0x43",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "TOR Inserts; NID and Opcode Matched",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode.",
         "UMask": "0x41",
         "Unit": "CBO"
     },
-    {
-        "BriefDescription": "TOR Inserts; NID Matched Evictions",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION",
-        "PerPkg": "1",
-        "UMask": "0x44",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "TOR Inserts; NID Matched",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.NID_ALL",
-        "PerPkg": "1",
-        "UMask": "0x48",
-        "Unit": "CBO"
-    },
     {
         "BriefDescription": "TOR Inserts; NID Matched Writebacks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.NID_WB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; NID matched write transactions inserted into the TOR.",
         "UMask": "0x50",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; Opcode Match",
         "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
+        "EventName": "UNC_C_TOR_INSERTS.OPCODE",
         "PerPkg": "1",
-        "UMask": "0x43",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+        "UMask": "0x1",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; NID Matched Miss All",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; Remote Memory",
         "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL",
+        "EventName": "UNC_C_TOR_INSERTS.REMOTE",
         "PerPkg": "1",
-        "UMask": "0x4A",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR that are satisifed by remote caches or remote memory.",
+        "UMask": "0x88",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; Misses to Local Memory",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched",
         "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL",
+        "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE",
         "PerPkg": "1",
-        "UMask": "0x2A",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions, satisifed by an opcode,  inserted into the TOR that are satisifed by remote caches or remote memory.",
+        "UMask": "0x81",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; Misses to Remote Memory",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; Writebacks",
         "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE",
+        "EventName": "UNC_C_TOR_INSERTS.WB",
         "PerPkg": "1",
-        "UMask": "0x8A",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Write transactions inserted into the TOR.   This does not include RFO, but actual operations that contain data being sent from the core.",
+        "UMask": "0x10",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; Local Memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.LOCAL",
+        "BriefDescription": "TOR Occupancy; Any",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "UMask": "0x28",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All valid TOR entries.  This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues.  The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger.  Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20.  Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.",
+        "UMask": "0x8",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; Remote Memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.REMOTE",
+        "BriefDescription": "TOR Occupancy; Evictions",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.EVICTION",
         "PerPkg": "1",
-        "UMask": "0x88",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding eviction transactions in the TOR.  Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set.  They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).",
+        "UMask": "0x4",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE",
+        "BriefDescription": "Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.LLC_DATA_READ",
+        "Filter": "filter_opc=0x182",
         "PerPkg": "1",
-        "UMask": "0x23",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO.",
+        "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE",
+        "BriefDescription": "TOR Occupancy",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL",
         "PerPkg": "1",
-        "UMask": "0x83",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+        "UMask": "0x28",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE",
+        "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE",
         "PerPkg": "1",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding  transactions, satisifed by an opcode,  in the TOR that are satisifed by locally HOMed memory.",
         "UMask": "0x21",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE",
-        "PerPkg": "1",
-        "UMask": "0x81",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "TOR Occupancy; Opcode Match",
+        "BriefDescription": "TOR Occupancy; Miss All",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE",
+        "EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR.  'Miss' means the allocation requires an RTID.  This generally means that the request was sent to memory or MMIO.",
+        "UMask": "0xa",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Occupancy; Evictions",
+        "BriefDescription": "TOR Occupancy",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.EVICTION",
+        "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+        "UMask": "0x2a",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Occupancy; Any",
+        "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcode Matched",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.ALL",
+        "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by locally HOMed memory.",
+        "UMask": "0x23",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode",
+        "BriefDescription": "TOR Occupancy; Miss Opcode Match",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.LLC_DATA_READ",
-        "Filter": "filter_opc=0x182",
+        "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE",
         "PerPkg": "1",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO.",
         "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Occupancy counter for LLC data reads (demand and L2 prefetch)",
+        "BriefDescription": "TOR Occupancy",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE",
-        "Filter": "filter_opc=0x182",
+        "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+        "UMask": "0x8a",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Occupancy; Miss All",
+        "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opcode Matched",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL",
+        "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by remote caches or remote memory.",
+        "UMask": "0x83",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Occupancy; NID and Opcode Matched",
+        "BriefDescription": "TOR Occupancy; NID Matched",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE",
+        "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL",
         "PerPkg": "1",
-        "UMask": "0x41",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of NID matched outstanding requests in the TOR.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+        "UMask": "0x48",
         "Unit": "CBO"
     },
     {
@@ -1254,15 +1437,17 @@
         "EventCode": "0x36",
         "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION",
         "PerPkg": "1",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding NID matched eviction transactions in the TOR .",
         "UMask": "0x44",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "TOR Occupancy; NID Matched",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL",
+        "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
         "PerPkg": "1",
-        "UMask": "0x48",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID.",
+        "UMask": "0x4a",
         "Unit": "CBO"
     },
     {
@@ -1270,39 +1455,35 @@
         "EventCode": "0x36",
         "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE",
         "PerPkg": "1",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID and an opcode.",
         "UMask": "0x43",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Occupancy; NID Matched",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
-        "PerPkg": "1",
-        "UMask": "0x4A",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "TOR Occupancy",
+        "BriefDescription": "TOR Occupancy; NID and Opcode Matched",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL",
+        "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE",
         "PerPkg": "1",
-        "UMask": "0x2A",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match a NID and an opcode.",
+        "UMask": "0x41",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Occupancy",
+        "BriefDescription": "TOR Occupancy; NID Matched Writebacks",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE",
+        "EventName": "UNC_C_TOR_OCCUPANCY.NID_WB",
         "PerPkg": "1",
-        "UMask": "0x8A",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); NID matched write transactions int the TOR.",
+        "UMask": "0x50",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Occupancy",
+        "BriefDescription": "TOR Occupancy; Opcode Match",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL",
+        "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE",
         "PerPkg": "1",
-        "UMask": "0x28",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc).",
+        "UMask": "0x1",
         "Unit": "CBO"
     },
     {
@@ -1310,38 +1491,16 @@
         "EventCode": "0x36",
         "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE",
         "PerPkg": "1",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
         "UMask": "0x88",
         "Unit": "CBO"
     },
-    {
-        "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcode Matched",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE",
-        "PerPkg": "1",
-        "UMask": "0x23",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opcode Matched",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE",
-        "PerPkg": "1",
-        "UMask": "0x83",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE",
-        "PerPkg": "1",
-        "UMask": "0x21",
-        "Unit": "CBO"
-    },
     {
         "BriefDescription": "TOR Occupancy; Remote Memory - Opcode Matched",
         "EventCode": "0x36",
         "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE",
         "PerPkg": "1",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding  transactions, satisifed by an opcode,  in the TOR that are satisifed by remote caches or remote memory.",
         "UMask": "0x81",
         "Unit": "CBO"
     },
@@ -1350,2297 +1509,2110 @@
         "EventCode": "0x36",
         "EventName": "UNC_C_TOR_OCCUPANCY.WB",
         "PerPkg": "1",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Write transactions in the TOR.   This does not include RFO, but actual operations that contain data being sent from the core.",
         "UMask": "0x10",
         "Unit": "CBO"
     },
-    {
-        "BriefDescription": "TOR Occupancy; NID Matched Writebacks",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.NID_WB",
-        "PerPkg": "1",
-        "UMask": "0x50",
-        "Unit": "CBO"
-    },
     {
         "BriefDescription": "Onto AD Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_C_TxR_ADS_USED.AD",
         "PerPkg": "1",
+        "PublicDescription": "UNC_C_TxR_ADS_USED.AD",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Onto AK Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_C_TxR_ADS_USED.AK",
         "PerPkg": "1",
+        "PublicDescription": "UNC_C_TxR_ADS_USED.AK",
         "UMask": "0x2",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Onto BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_C_TxR_ADS_USED.BL",
         "PerPkg": "1",
+        "PublicDescription": "UNC_C_TxR_ADS_USED.BL",
         "UMask": "0x4",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Egress Allocations; AD - Cachebo",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.AD_CACHE",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
         "UMask": "0x1",
         "Unit": "CBO"
     },
-    {
-        "BriefDescription": "Egress Allocations; AK - Cachebo",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_C_TxR_INSERTS.AK_CACHE",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "Egress Allocations; BL - Cacheno",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_C_TxR_INSERTS.BL_CACHE",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "Egress Allocations; IV - Cachebo",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_C_TxR_INSERTS.IV_CACHE",
-        "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "CBO"
-    },
     {
         "BriefDescription": "Egress Allocations; AD - Corebo",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.AD_CORE",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AD ring.  This is commonly used for outbound requests.",
         "UMask": "0x10",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Egress Allocations; AK - Corebo",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_C_TxR_INSERTS.AK_CORE",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "Egress Allocations; BL - Corebo",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Egress Allocations; AK - Cachebo",
         "EventCode": "0x2",
-        "EventName": "UNC_C_TxR_INSERTS.BL_CORE",
-        "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "LRU Queue; LRU Age 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3C",
-        "EventName": "UNC_C_QLRU.AGE0",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "LRU Queue; LRU Age 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3C",
-        "EventName": "UNC_C_QLRU.AGE1",
+        "EventName": "UNC_C_TxR_INSERTS.AK_CACHE",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AK ring.  This is commonly used for credit returns and GO responses.",
         "UMask": "0x2",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "LRU Queue; LRU Age 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3C",
-        "EventName": "UNC_C_QLRU.AGE2",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "LRU Queue; LRU Age 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3C",
-        "EventName": "UNC_C_QLRU.AGE3",
-        "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "LRU Queue; LRU Bits Decremented",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3C",
-        "EventName": "UNC_C_QLRU.LRU_DECREMENT",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "LRU Queue; Non-0 Aged Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3C",
-        "EventName": "UNC_C_QLRU.VICTIM_NON_ZERO",
+        "BriefDescription": "Egress Allocations; AK - Corebo",
+        "EventCode": "0x2",
+        "EventName": "UNC_C_TxR_INSERTS.AK_CORE",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AK ring.  This is commonly used for snoop responses coming from the core and destined for a Cachebo.",
         "UMask": "0x20",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "AD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6",
-        "EventName": "UNC_C_RING_SINK_STARVED.AD",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "AK",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6",
-        "EventName": "UNC_C_RING_SINK_STARVED.AK",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6",
-        "EventName": "UNC_C_RING_SINK_STARVED.IV",
-        "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "BL",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6",
-        "EventName": "UNC_C_RING_SINK_STARVED.BL",
+        "BriefDescription": "Egress Allocations; BL - Cacheno",
+        "EventCode": "0x2",
+        "EventName": "UNC_C_TxR_INSERTS.BL_CACHE",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
         "UMask": "0x4",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Ingress Internal Starvation Cycles; IRQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_C_RxR_INT_STARVED.IRQ",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "Ingress Internal Starvation Cycles; IPQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_C_RxR_INT_STARVED.IPQ",
+        "BriefDescription": "Egress Allocations; BL - Corebo",
+        "EventCode": "0x2",
+        "EventName": "UNC_C_TxR_INSERTS.BL_CORE",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_C_RxR_INT_STARVED.ISMQ",
+        "BriefDescription": "Egress Allocations; IV - Cachebo",
+        "EventCode": "0x2",
+        "EventName": "UNC_C_TxR_INSERTS.IV_CACHE",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the IV ring.  This is commonly used for snoops to the cores.",
         "UMask": "0x8",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Ingress Internal Starvation Cycles; PRQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_C_RxR_INT_STARVED.PRQ",
+        "BriefDescription": "Injection Starvation; Onto AD Ring (to core)",
+        "EventCode": "0x3",
+        "EventName": "UNC_C_TxR_STARVED.AD_CORE",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the core AD egress spent in starvation",
         "UMask": "0x10",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Injection Starvation; Onto AK Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_C_TxR_STARVED.AK_BOTH",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both AK egresses spent in starvation",
         "UMask": "0x2",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Injection Starvation; Onto BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_C_TxR_STARVED.BL_BOTH",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both BL egresses spent in starvation",
         "UMask": "0x4",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Injection Starvation; Onto IV Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_C_TxR_STARVED.IV",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the cachebo IV egress spent in starvation",
         "UMask": "0x8",
         "Unit": "CBO"
     },
-    {
-        "BriefDescription": "Injection Starvation; Onto AD Ring (to core)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_C_TxR_STARVED.AD_CORE",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "QPI Address/Opcode Match; Address & Opcode Match",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_H_ADDR_OPC_MATCH.FILT",
-        "PerPkg": "1",
-        "UMask": "0x3",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "QPI Address/Opcode Match; Address",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_H_ADDR_OPC_MATCH.ADDR",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "QPI Address/Opcode Match; Opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_H_ADDR_OPC_MATCH.OPC",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "QPI Address/Opcode Match; AD Opcodes",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_H_ADDR_OPC_MATCH.AD",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "QPI Address/Opcode Match; BL Opcodes",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_H_ADDR_OPC_MATCH.BL",
-        "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "QPI Address/Opcode Match; AK Opcodes",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_H_ADDR_OPC_MATCH.AK",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "HA"
-    },
     {
         "BriefDescription": "BT Cycles Not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0x42",
-        "EventName": "UNC_H_BT_CYCLES_NE",
-        "PerPkg": "1",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "HA to iMC Bypass; Taken",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_H_BYPASS_IMC.TAKEN",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "HA to iMC Bypass; Not Taken",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "uclks",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_H_CLOCKTICKS",
-        "PerPkg": "1",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "Direct2Core Messages Sent",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x11",
-        "EventName": "UNC_H_DIRECT2CORE_COUNT",
-        "PerPkg": "1",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "Cycles when Direct2Core was Disabled",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED",
-        "PerPkg": "1",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "Number of Reads that had Direct2Core Overridden",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE",
-        "PerPkg": "1",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "Directory Lat Opt Return",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x41",
-        "EventName": "UNC_H_DIRECTORY_LAT_OPT",
-        "PerPkg": "1",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "Directory Lookups; Snoop Needed",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC",
-        "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "Directory Lookups; Snoop Not Needed",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC",
-        "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "Directory Updates; Directory Set",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD",
-        "EventName": "UNC_H_DIRECTORY_UPDATE.SET",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "Directory Updates; Directory Clear",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD",
-        "EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "Directory Updates; Any Directory Update",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD",
-        "EventName": "UNC_H_DIRECTORY_UPDATE.ANY",
-        "PerPkg": "1",
-        "UMask": "0x3",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.READ_OR_INVITOE",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.WBMTOI",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is AckCnfltWbI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.ACKCNFLTWBI",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.WBMTOE_OR_S",
-        "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.RSPFWDI_REMOTE",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.RSPFWDI_LOCAL",
+        "EventName": "UNC_H_BT_CYCLES_NE",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT.",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.RSPFWDS",
+        "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
+        "EventCode": "0x51",
+        "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.RSP",
+        "BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard",
+        "EventCode": "0x51",
+        "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming snoop hazard",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.ALLOCS",
+        "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
+        "EventCode": "0x51",
+        "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD",
         "PerPkg": "1",
-        "UMask": "0x70",
+        "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.EVICTS",
+        "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
+        "EventCode": "0x51",
+        "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD",
         "PerPkg": "1",
-        "UMask": "0x42",
+        "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
+        "UMask": "0x10",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; Invalidations",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.INVALS",
+        "BriefDescription": "HA to iMC Bypass; Not Taken",
+        "EventCode": "0x14",
+        "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN",
         "PerPkg": "1",
-        "UMask": "0x26",
+        "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass.",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; All Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.ALL",
+        "BriefDescription": "HA to iMC Bypass; Taken",
+        "EventCode": "0x14",
+        "EventName": "UNC_H_BYPASS_IMC.TAKEN",
         "PerPkg": "1",
-        "UMask": "0xFF",
+        "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass.",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; HOM Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.HOM",
+        "BriefDescription": "uclks",
+        "EventName": "UNC_H_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "Counts the number of uclks in the HA.  This will be slightly different than the count in the Ubox because of enable/freeze delays.  The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x72",
-        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE",
+        "BriefDescription": "Direct2Core Messages Sent",
+        "EventCode": "0x11",
+        "EventName": "UNC_H_DIRECT2CORE_COUNT",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Number of Direct2Core messages sent",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x72",
-        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI",
+        "BriefDescription": "Cycles when Direct2Core was Disabled",
+        "EventCode": "0x12",
+        "EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Number of cycles in which Direct2Core was disabled",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x72",
-        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI",
+        "BriefDescription": "Number of Reads that had Direct2Core Overridden",
+        "EventCode": "0x13",
+        "EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of Reads where Direct2Core overridden",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x72",
-        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S",
+        "BriefDescription": "Directory Lat Opt Return",
+        "EventCode": "0x41",
+        "EventName": "UNC_H_DIRECTORY_LAT_OPT",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Directory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory returned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc).",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x72",
-        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE",
+        "BriefDescription": "Directory Lookups; Snoop Not Needed",
+        "EventCode": "0xC",
+        "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that did not have to send any snoops because the directory bit was clear.",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a local request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x72",
-        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL",
+        "BriefDescription": "Directory Lookups; Snoop Needed",
+        "EventCode": "0xC",
+        "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that had to send one or more snoops because the directory bit was set.",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x72",
-        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS",
+        "BriefDescription": "Directory Updates; Any Directory Update",
+        "EventCode": "0xD",
+        "EventName": "UNC_H_DIRECTORY_UPDATE.ANY",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.",
+        "UMask": "0x3",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x72",
-        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSP",
+        "BriefDescription": "Directory Updates; Directory Clear",
+        "EventCode": "0xD",
+        "EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.; Filter for directory clears.  This occurs when snoops were sent and all returned with RspI.",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; All Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x72",
-        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ALL",
+        "BriefDescription": "Directory Updates; Directory Set",
+        "EventCode": "0xD",
+        "EventName": "UNC_H_DIRECTORY_UPDATE.SET",
         "PerPkg": "1",
-        "UMask": "0xFF",
+        "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.; Filter for directory sets.  This occurs when a remote read transaction requests memory, bringing it to a remote cache.",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x72",
-        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.HOM",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is AckCnfltWbI",
+        "EventCode": "0x71",
+        "EventName": "UNC_H_HITME_HIT.ACKCNFLTWBI",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "UNC_H_HITME_HIT.ACKCNFLTWBI",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x70",
-        "EventName": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; All Requests",
+        "EventCode": "0x71",
+        "EventName": "UNC_H_HITME_HIT.ALL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "UNC_H_HITME_HIT.ALL",
+        "UMask": "0xff",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x70",
-        "EventName": "UNC_H_HITME_LOOKUP.WBMTOI",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
+        "EventCode": "0x71",
+        "EventName": "UNC_H_HITME_HIT.ALLOCS",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "UNC_H_HITME_HIT.ALLOCS",
+        "UMask": "0x70",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x70",
-        "EventName": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
+        "EventCode": "0x71",
+        "EventName": "UNC_H_HITME_HIT.EVICTS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "UNC_H_HITME_HIT.EVICTS",
+        "UMask": "0x42",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x70",
-        "EventName": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; HOM Requests",
+        "EventCode": "0x71",
+        "EventName": "UNC_H_HITME_HIT.HOM",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "UNC_H_HITME_HIT.HOM",
+        "UMask": "0xf",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x70",
-        "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; Invalidations",
+        "EventCode": "0x71",
+        "EventName": "UNC_H_HITME_HIT.INVALS",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "UNC_H_HITME_HIT.INVALS",
+        "UMask": "0x26",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x70",
-        "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
+        "EventCode": "0x71",
+        "EventName": "UNC_H_HITME_HIT.READ_OR_INVITOE",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "UNC_H_HITME_HIT.READ_OR_INVITOE",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x70",
-        "EventName": "UNC_H_HITME_LOOKUP.RSPFWDS",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
+        "EventCode": "0x71",
+        "EventName": "UNC_H_HITME_HIT.RSP",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "UNC_H_HITME_HIT.RSP",
+        "UMask": "0x80",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x70",
-        "EventName": "UNC_H_HITME_LOOKUP.RSP",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
+        "EventCode": "0x71",
+        "EventName": "UNC_H_HITME_HIT.RSPFWDI_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "UNC_H_HITME_HIT.RSPFWDI_LOCAL",
+        "UMask": "0x20",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; Allocations",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x70",
-        "EventName": "UNC_H_HITME_LOOKUP.ALLOCS",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
+        "EventCode": "0x71",
+        "EventName": "UNC_H_HITME_HIT.RSPFWDI_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x70",
+        "PublicDescription": "UNC_H_HITME_HIT.RSPFWDI_REMOTE",
+        "UMask": "0x10",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; Invalidations",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x70",
-        "EventName": "UNC_H_HITME_LOOKUP.INVALS",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb",
+        "EventCode": "0x71",
+        "EventName": "UNC_H_HITME_HIT.RSPFWDS",
         "PerPkg": "1",
-        "UMask": "0x26",
+        "PublicDescription": "UNC_H_HITME_HIT.RSPFWDS",
+        "UMask": "0x40",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; All Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x70",
-        "EventName": "UNC_H_HITME_LOOKUP.ALL",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS",
+        "EventCode": "0x71",
+        "EventName": "UNC_H_HITME_HIT.WBMTOE_OR_S",
         "PerPkg": "1",
-        "UMask": "0xFF",
+        "PublicDescription": "UNC_H_HITME_HIT.WBMTOE_OR_S",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; HOM Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x70",
-        "EventName": "UNC_H_HITME_LOOKUP.HOM",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI",
+        "EventCode": "0x71",
+        "EventName": "UNC_H_HITME_HIT.WBMTOI",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "UNC_H_HITME_HIT.WBMTOI",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x22",
-        "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
+        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI",
+        "EventCode": "0x72",
+        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x22",
-        "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
+        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; All Requests",
+        "EventCode": "0x72",
+        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ALL",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.ALL",
+        "UMask": "0xff",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x22",
-        "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
+        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests",
+        "EventCode": "0x72",
+        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.HOM",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.HOM",
+        "UMask": "0xf",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x22",
-        "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
+        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
+        "EventCode": "0x72",
+        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x22",
-        "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2",
+        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
+        "EventCode": "0x72",
+        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.RSP",
+        "UMask": "0x80",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x22",
-        "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2",
+        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a local request",
+        "EventCode": "0x72",
+        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL",
         "PerPkg": "1",
+        "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL",
         "UMask": "0x20",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA to iMC Normal Priority Reads Issued; Normal Priority",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x17",
-        "EventName": "UNC_H_IMC_READS.NORMAL",
+        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request",
+        "EventCode": "0x72",
+        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE",
+        "UMask": "0x10",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Retry Events",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1E",
-        "EventName": "UNC_H_IMC_RETRY",
+        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb",
+        "EventCode": "0x72",
+        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS",
         "PerPkg": "1",
+        "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS",
+        "UMask": "0x40",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1A",
-        "EventName": "UNC_H_IMC_WRITES.FULL",
+        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS",
+        "EventCode": "0x72",
+        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1A",
-        "EventName": "UNC_H_IMC_WRITES.PARTIAL",
+        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI",
+        "EventCode": "0x72",
+        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI",
         "PerPkg": "1",
+        "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full Line",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1A",
-        "EventName": "UNC_H_IMC_WRITES.FULL_ISOCH",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI",
+        "EventCode": "0x70",
+        "EventName": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI",
         "PerPkg": "1",
+        "PublicDescription": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI",
         "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1A",
-        "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; All Requests",
+        "EventCode": "0x70",
+        "EventName": "UNC_H_HITME_LOOKUP.ALL",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "UNC_H_HITME_LOOKUP.ALL",
+        "UMask": "0xff",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1A",
-        "EventName": "UNC_H_IMC_WRITES.ALL",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; Allocations",
+        "EventCode": "0x70",
+        "EventName": "UNC_H_HITME_LOOKUP.ALLOCS",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "UNC_H_HITME_LOOKUP.ALLOCS",
+        "UMask": "0x70",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "OSB Snoop Broadcast; Local Reads",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x53",
-        "EventName": "UNC_H_OSB.READS_LOCAL",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; HOM Requests",
+        "EventCode": "0x70",
+        "EventName": "UNC_H_HITME_LOOKUP.HOM",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "UNC_H_HITME_LOOKUP.HOM",
+        "UMask": "0xf",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "OSB Snoop Broadcast; Local InvItoE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x53",
-        "EventName": "UNC_H_OSB.INVITOE_LOCAL",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; Invalidations",
+        "EventCode": "0x70",
+        "EventName": "UNC_H_HITME_LOOKUP.INVALS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "UNC_H_HITME_LOOKUP.INVALS",
+        "UMask": "0x26",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "OSB Snoop Broadcast; Remote",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x53",
-        "EventName": "UNC_H_OSB.REMOTE",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
+        "EventCode": "0x70",
+        "EventName": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "OSB Snoop Broadcast; Cancelled",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x53",
-        "EventName": "UNC_H_OSB.CANCELLED",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
+        "EventCode": "0x70",
+        "EventName": "UNC_H_HITME_LOOKUP.RSP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "UNC_H_HITME_LOOKUP.RSP",
+        "UMask": "0x80",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "OSB Snoop Broadcast; Reads Local -  Useful",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x53",
-        "EventName": "UNC_H_OSB.READS_LOCAL_USEFUL",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request",
+        "EventCode": "0x70",
+        "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL",
         "PerPkg": "1",
+        "PublicDescription": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL",
         "UMask": "0x20",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "OSB Snoop Broadcast; Remote - Useful",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x53",
-        "EventName": "UNC_H_OSB.REMOTE_USEFUL",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request",
+        "EventCode": "0x70",
+        "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE",
+        "PerPkg": "1",
+        "PublicDescription": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE",
+        "UMask": "0x10",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb",
+        "EventCode": "0x70",
+        "EventName": "UNC_H_HITME_LOOKUP.RSPFWDS",
         "PerPkg": "1",
+        "PublicDescription": "UNC_H_HITME_LOOKUP.RSPFWDS",
         "UMask": "0x40",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "OSB Early Data Return; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x54",
-        "EventName": "UNC_H_OSB_EDR.ALL",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS",
+        "EventCode": "0x70",
+        "EventName": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "OSB Early Data Return; Reads to Local  I",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x54",
-        "EventName": "UNC_H_OSB_EDR.READS_LOCAL_I",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoI",
+        "EventCode": "0x70",
+        "EventName": "UNC_H_HITME_LOOKUP.WBMTOI",
         "PerPkg": "1",
+        "PublicDescription": "UNC_H_HITME_LOOKUP.WBMTOI",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "OSB Early Data Return; Reads to Remote I",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x54",
-        "EventName": "UNC_H_OSB_EDR.READS_REMOTE_I",
+        "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 0",
+        "EventCode": "0x22",
+        "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "OSB Early Data Return; Reads to Local S",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x54",
-        "EventName": "UNC_H_OSB_EDR.READS_LOCAL_S",
+        "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 1",
+        "EventCode": "0x22",
+        "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "OSB Early Data Return; Reads to Remote S",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x54",
-        "EventName": "UNC_H_OSB_EDR.READS_REMOTE_S",
+        "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
+        "EventCode": "0x22",
+        "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
         "UMask": "0x10",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Read and Write Requests; Reads",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_H_REQUESTS.READS",
+        "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
+        "EventCode": "0x22",
+        "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Read and Write Requests; Writes",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_H_REQUESTS.WRITES",
+        "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
+        "EventCode": "0x22",
+        "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Read and Write Requests; Local Reads",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_H_REQUESTS.READS_LOCAL",
+        "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
+        "EventCode": "0x22",
+        "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+        "UMask": "0x20",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Read and Write Requests; Remote Reads",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_H_REQUESTS.READS_REMOTE",
+        "BriefDescription": "HA to iMC Normal Priority Reads Issued; Normal Priority",
+        "EventCode": "0x17",
+        "EventName": "UNC_H_IMC_READS.NORMAL",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Count of the number of reads issued to any of the memory controller channels.  This can be filtered by the priority of the reads.",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Read and Write Requests; Local Writes",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
+        "BriefDescription": "Retry Events",
+        "EventCode": "0x1E",
+        "EventName": "UNC_H_IMC_RETRY",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "UNC_H_IMC_RETRY",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Read and Write Requests; Remote Writes",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_H_REQUESTS.WRITES_REMOTE",
+        "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes",
+        "EventCode": "0x1A",
+        "EventName": "UNC_H_IMC_WRITES.ALL",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+        "UMask": "0xf",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Read and Write Requests; Local InvItoEs",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
+        "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
+        "EventCode": "0x1A",
+        "EventName": "UNC_H_IMC_WRITES.FULL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Read and Write Requests; Remote InvItoEs",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
+        "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full Line",
+        "EventCode": "0x1A",
+        "EventName": "UNC_H_IMC_WRITES.FULL_ISOCH",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA AD Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3E",
-        "EventName": "UNC_H_RING_AD_USED.CW_EVEN",
+        "BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
+        "EventCode": "0x1A",
+        "EventName": "UNC_H_IMC_WRITES.PARTIAL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA AD Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3E",
-        "EventName": "UNC_H_RING_AD_USED.CW_ODD",
+        "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial",
+        "EventCode": "0x1A",
+        "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3E",
-        "EventName": "UNC_H_RING_AD_USED.CCW_EVEN",
+        "BriefDescription": "IOT Backpressure",
+        "EventCode": "0x61",
+        "EventName": "UNC_H_IOT_BACKPRESSURE.HUB",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "UNC_H_IOT_BACKPRESSURE.HUB",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3E",
-        "EventName": "UNC_H_RING_AD_USED.CCW_ODD",
+        "BriefDescription": "IOT Backpressure",
+        "EventCode": "0x61",
+        "EventName": "UNC_H_IOT_BACKPRESSURE.SAT",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "UNC_H_IOT_BACKPRESSURE.SAT",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA AD Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3E",
-        "EventName": "UNC_H_RING_AD_USED.CW",
+        "BriefDescription": "IOT Common Trigger Sequencer - Lo",
+        "EventCode": "0x64",
+        "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS0",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Debug Mask/Match Tie-Ins",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA AD Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3E",
-        "EventName": "UNC_H_RING_AD_USED.CCW",
+        "BriefDescription": "IOT Common Trigger Sequencer - Lo",
+        "EventCode": "0x64",
+        "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS1",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Debug Mask/Match Tie-Ins",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA AK Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3F",
-        "EventName": "UNC_H_RING_AK_USED.CW_EVEN",
+        "BriefDescription": "IOT Common Trigger Sequencer - Hi",
+        "EventCode": "0x65",
+        "EventName": "UNC_H_IOT_CTS_HI.CTS2",
         "PerPkg": "1",
+        "PublicDescription": "Debug Mask/Match Tie-Ins",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA AK Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3F",
-        "EventName": "UNC_H_RING_AK_USED.CW_ODD",
+        "BriefDescription": "IOT Common Trigger Sequencer - Hi",
+        "EventCode": "0x65",
+        "EventName": "UNC_H_IOT_CTS_HI.CTS3",
         "PerPkg": "1",
+        "PublicDescription": "Debug Mask/Match Tie-Ins",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3F",
-        "EventName": "UNC_H_RING_AK_USED.CCW_EVEN",
+        "BriefDescription": "IOT Common Trigger Sequencer - Lo",
+        "EventCode": "0x62",
+        "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS0",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Debug Mask/Match Tie-Ins",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3F",
-        "EventName": "UNC_H_RING_AK_USED.CCW_ODD",
+        "BriefDescription": "IOT Common Trigger Sequencer - Lo",
+        "EventCode": "0x62",
+        "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS1",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Debug Mask/Match Tie-Ins",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA AK Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3F",
-        "EventName": "UNC_H_RING_AK_USED.CW",
+        "BriefDescription": "OSB Snoop Broadcast; Cancelled",
+        "EventCode": "0x53",
+        "EventName": "UNC_H_OSB.CANCELLED",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.; OSB Snoop broadcast cancelled due to D2C or Other. OSB cancel is counted when OSB local read is not allowed even when the transaction in local InItoE. It also counts D2C OSB cancel, but also includes the cases were D2C was not set in the first place for the transaction coming from the ring.",
+        "UMask": "0x10",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA AK Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3F",
-        "EventName": "UNC_H_RING_AK_USED.CCW",
+        "BriefDescription": "OSB Snoop Broadcast; Local InvItoE",
+        "EventCode": "0x53",
+        "EventName": "UNC_H_OSB.INVITOE_LOCAL",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA BL Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x40",
-        "EventName": "UNC_H_RING_BL_USED.CW_EVEN",
+        "BriefDescription": "OSB Snoop Broadcast; Local Reads",
+        "EventCode": "0x53",
+        "EventName": "UNC_H_OSB.READS_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA BL Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x40",
-        "EventName": "UNC_H_RING_BL_USED.CW_ODD",
+        "BriefDescription": "OSB Snoop Broadcast; Reads Local -  Useful",
+        "EventCode": "0x53",
+        "EventName": "UNC_H_OSB.READS_LOCAL_USEFUL",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+        "UMask": "0x20",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x40",
-        "EventName": "UNC_H_RING_BL_USED.CCW_EVEN",
+        "BriefDescription": "OSB Snoop Broadcast; Remote",
+        "EventCode": "0x53",
+        "EventName": "UNC_H_OSB.REMOTE",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x40",
-        "EventName": "UNC_H_RING_BL_USED.CCW_ODD",
+        "BriefDescription": "OSB Snoop Broadcast; Remote - Useful",
+        "EventCode": "0x53",
+        "EventName": "UNC_H_OSB.REMOTE_USEFUL",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+        "UMask": "0x40",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA BL Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x40",
-        "EventName": "UNC_H_RING_BL_USED.CW",
+        "BriefDescription": "OSB Early Data Return; All",
+        "EventCode": "0x54",
+        "EventName": "UNC_H_OSB_EDR.ALL",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA BL Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x40",
-        "EventName": "UNC_H_RING_BL_USED.CCW",
+        "BriefDescription": "OSB Early Data Return; Reads to Local  I",
+        "EventCode": "0x54",
+        "EventName": "UNC_H_OSB_EDR.READS_LOCAL_I",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
+        "BriefDescription": "OSB Early Data Return; Reads to Local S",
+        "EventCode": "0x54",
+        "EventName": "UNC_H_OSB_EDR.READS_LOCAL_S",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
+        "BriefDescription": "OSB Early Data Return; Reads to Remote I",
+        "EventCode": "0x54",
+        "EventName": "UNC_H_OSB_EDR.READS_REMOTE_I",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
+        "BriefDescription": "OSB Early Data Return; Reads to Remote S",
+        "EventCode": "0x54",
+        "EventName": "UNC_H_OSB_EDR.READS_REMOTE_S",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+        "UMask": "0x10",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
+        "BriefDescription": "Read and Write Requests; Local InvItoEs",
+        "EventCode": "0x1",
+        "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from the local socket.",
+        "UMask": "0x10",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "SBo0 Credits Acquired; For AD Ring",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x68",
-        "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.AD",
+        "BriefDescription": "Read and Write Requests; Remote InvItoEs",
+        "EventCode": "0x1",
+        "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from remote sockets.",
+        "UMask": "0x20",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "SBo0 Credits Acquired; For BL Ring",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x68",
-        "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.BL",
+        "BriefDescription": "Read and Write Requests; Reads",
+        "EventCode": "0x1",
+        "EventName": "UNC_H_REQUESTS.READS",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; Incoming ead requests.  This is a good proxy for LLC Read Misses (including RFOs).",
+        "UMask": "0x3",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6A",
-        "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.AD",
+        "BriefDescription": "Read and Write Requests; Local Reads",
+        "EventCode": "0x1",
+        "EventName": "UNC_H_REQUESTS.READS_LOCAL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the local socket.  This is a good proxy for LLC Read Misses (including RFOs) from the local socket.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6A",
-        "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.BL",
+        "BriefDescription": "Read and Write Requests; Remote Reads",
+        "EventCode": "0x1",
+        "EventName": "UNC_H_REQUESTS.READS_REMOTE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the remote socket.  This is a good proxy for LLC Read Misses (including RFOs) from the remote socket.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "SBo1 Credits Acquired; For AD Ring",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x69",
-        "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.AD",
+        "BriefDescription": "Read and Write Requests; Writes",
+        "EventCode": "0x1",
+        "EventName": "UNC_H_REQUESTS.WRITES",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; Incoming write requests.",
+        "UMask": "0xc",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "SBo1 Credits Acquired; For BL Ring",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x69",
-        "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.BL",
+        "BriefDescription": "Read and Write Requests; Local Writes",
+        "EventCode": "0x1",
+        "EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from the local socket.",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "SBo1 Credits Occupancy; For AD Ring",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6B",
-        "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.AD",
+        "BriefDescription": "Read and Write Requests; Remote Writes",
+        "EventCode": "0x1",
+        "EventName": "UNC_H_REQUESTS.WRITES_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from remote sockets.",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "SBo1 Credits Occupancy; For BL Ring",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6B",
-        "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.BL",
+        "BriefDescription": "HA AD Ring in Use; Counterclockwise",
+        "EventCode": "0x3E",
+        "EventName": "UNC_H_RING_AD_USED.CCW",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xc",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Data beat the Snoop Responses; Local Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA",
-        "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL",
+        "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even",
+        "EventCode": "0x3E",
+        "EventName": "UNC_H_RING_AD_USED.CCW_EVEN",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Data beat the Snoop Responses; Remote Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA",
-        "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE",
+        "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd",
+        "EventCode": "0x3E",
+        "EventName": "UNC_H_RING_AD_USED.CCW_ODD",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Cycles with Snoops Outstanding; Local Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8",
-        "EventName": "UNC_H_SNOOP_CYCLES_NE.LOCAL",
+        "BriefDescription": "HA AD Ring in Use; Clockwise",
+        "EventCode": "0x3E",
+        "EventName": "UNC_H_RING_AD_USED.CW",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0x3",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "HA AD Ring in Use; Clockwise and Even",
+        "EventCode": "0x3E",
+        "EventName": "UNC_H_RING_AD_USED.CW_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Cycles with Snoops Outstanding; Remote Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8",
-        "EventName": "UNC_H_SNOOP_CYCLES_NE.REMOTE",
+        "BriefDescription": "HA AD Ring in Use; Clockwise and Odd",
+        "EventCode": "0x3E",
+        "EventName": "UNC_H_RING_AD_USED.CW_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Cycles with Snoops Outstanding; All Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8",
-        "EventName": "UNC_H_SNOOP_CYCLES_NE.ALL",
+        "BriefDescription": "HA AK Ring in Use; All",
+        "EventCode": "0x3F",
+        "EventName": "UNC_H_RING_AK_USED.ALL",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xf",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Tracker Snoops Outstanding Accumulator; Local Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9",
-        "EventName": "UNC_H_SNOOP_OCCUPANCY.LOCAL",
+        "BriefDescription": "HA AK Ring in Use; Counterclockwise",
+        "EventCode": "0x3F",
+        "EventName": "UNC_H_RING_AK_USED.CCW",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xc",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Tracker Snoops Outstanding Accumulator; Remote Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9",
-        "EventName": "UNC_H_SNOOP_OCCUPANCY.REMOTE",
+        "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even",
+        "EventCode": "0x3F",
+        "EventName": "UNC_H_RING_AK_USED.CCW_EVEN",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Snoop Responses Received; RspI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_H_SNOOP_RESP.RSPI",
+        "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd",
+        "EventCode": "0x3F",
+        "EventName": "UNC_H_RING_AK_USED.CCW_ODD",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Shared line response from remote cache",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_H_SNOOP_RESP.RSPS",
+        "BriefDescription": "HA AK Ring in Use; Clockwise",
+        "EventCode": "0x3F",
+        "EventName": "UNC_H_RING_AK_USED.CW",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0x3",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "M line forwarded from remote cache with no writeback to memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
+        "BriefDescription": "HA AK Ring in Use; Clockwise and Even",
+        "EventCode": "0x3F",
+        "EventName": "UNC_H_RING_AK_USED.CW_EVEN",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Shared line forwarded from remote cache",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
+        "BriefDescription": "HA AK Ring in Use; Clockwise and Odd",
+        "EventCode": "0x3F",
+        "EventName": "UNC_H_RING_AK_USED.CW_ODD",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Snoop Responses Received; Rsp*WB",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_H_SNOOP_RESP.RSP_WB",
+        "BriefDescription": "HA BL Ring in Use; All",
+        "EventCode": "0x40",
+        "EventName": "UNC_H_RING_BL_USED.ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xf",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "M line forwarded from remote cache along with writeback to memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
+        "BriefDescription": "HA BL Ring in Use; Counterclockwise",
+        "EventCode": "0x40",
+        "EventName": "UNC_H_RING_BL_USED.CCW",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xc",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Snoop Responses Received; RSPCNFLCT*",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
+        "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even",
+        "EventCode": "0x40",
+        "EventName": "UNC_H_RING_BL_USED.CCW_EVEN",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; RspI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x60",
-        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPI",
+        "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd",
+        "EventCode": "0x40",
+        "EventName": "UNC_H_RING_BL_USED.CCW_ODD",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; RspS",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x60",
-        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS",
+        "BriefDescription": "HA BL Ring in Use; Clockwise",
+        "EventCode": "0x40",
+        "EventName": "UNC_H_RING_BL_USED.CW",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0x3",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; RspIFwd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x60",
-        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD",
+        "BriefDescription": "HA BL Ring in Use; Clockwise and Even",
+        "EventCode": "0x40",
+        "EventName": "UNC_H_RING_BL_USED.CW_EVEN",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; RspSFwd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x60",
-        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD",
+        "BriefDescription": "HA BL Ring in Use; Clockwise and Odd",
+        "EventCode": "0x40",
+        "EventName": "UNC_H_RING_BL_USED.CW_ODD",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x60",
-        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB",
+        "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0",
+        "EventCode": "0x15",
+        "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x60",
-        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB",
+        "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1",
+        "EventCode": "0x15",
+        "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; RspCnflct",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x60",
-        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT",
+        "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2",
+        "EventCode": "0x15",
+        "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; Other",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x60",
-        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER",
+        "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3",
+        "EventCode": "0x15",
+        "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6C",
-        "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD",
+        "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0",
+        "EventCode": "0x16",
+        "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6C",
-        "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD",
+        "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1",
+        "EventCode": "0x16",
+        "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6C",
-        "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL",
+        "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2",
+        "EventCode": "0x16",
+        "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
         "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6C",
-        "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL",
+        "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3",
+        "EventCode": "0x16",
+        "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
         "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1B",
-        "EventName": "UNC_H_TAD_REQUESTS_G0.REGION0",
+        "BriefDescription": "SBo0 Credits Acquired; For AD Ring",
+        "EventCode": "0x68",
+        "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1B",
-        "EventName": "UNC_H_TAD_REQUESTS_G0.REGION1",
+        "BriefDescription": "SBo0 Credits Acquired; For BL Ring",
+        "EventCode": "0x68",
+        "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1B",
-        "EventName": "UNC_H_TAD_REQUESTS_G0.REGION2",
+        "BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
+        "EventCode": "0x6A",
+        "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.AD",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1B",
-        "EventName": "UNC_H_TAD_REQUESTS_G0.REGION3",
+        "BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
+        "EventCode": "0x6A",
+        "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.BL",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1B",
-        "EventName": "UNC_H_TAD_REQUESTS_G0.REGION4",
+        "BriefDescription": "SBo1 Credits Acquired; For AD Ring",
+        "EventCode": "0x69",
+        "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.AD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1B",
-        "EventName": "UNC_H_TAD_REQUESTS_G0.REGION5",
+        "BriefDescription": "SBo1 Credits Acquired; For BL Ring",
+        "EventCode": "0x69",
+        "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.BL",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 6",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1B",
-        "EventName": "UNC_H_TAD_REQUESTS_G0.REGION6",
+        "BriefDescription": "SBo1 Credits Occupancy; For AD Ring",
+        "EventCode": "0x6B",
+        "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.AD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 7",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1B",
-        "EventName": "UNC_H_TAD_REQUESTS_G0.REGION7",
+        "BriefDescription": "SBo1 Credits Occupancy; For BL Ring",
+        "EventCode": "0x6B",
+        "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.BL",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 8",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1C",
-        "EventName": "UNC_H_TAD_REQUESTS_G1.REGION8",
+        "BriefDescription": "Data beat the Snoop Responses; Local Requests",
+        "EventCode": "0xA",
+        "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from the local socket.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 9",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1C",
-        "EventName": "UNC_H_TAD_REQUESTS_G1.REGION9",
+        "BriefDescription": "Data beat the Snoop Responses; Remote Requests",
+        "EventCode": "0xA",
+        "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from remote sockets.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1C",
-        "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10",
+        "BriefDescription": "Cycles with Snoops Outstanding; All Requests",
+        "EventCode": "0x8",
+        "EventName": "UNC_H_SNOOP_CYCLES_NE.ALL",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts cycles when one or more snoops are outstanding.; Tracked for snoops from both local and remote sockets.",
+        "UMask": "0x3",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1C",
-        "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11",
+        "BriefDescription": "Cycles with Snoops Outstanding; Local Requests",
+        "EventCode": "0x8",
+        "EventName": "UNC_H_SNOOP_CYCLES_NE.LOCAL",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from the local socket.",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Tracker Cycles Full; Cycles GP Completely Used",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_H_TRACKER_CYCLES_FULL.GP",
+        "BriefDescription": "Cycles with Snoops Outstanding; Remote Requests",
+        "EventCode": "0x8",
+        "EventName": "UNC_H_SNOOP_CYCLES_NE.REMOTE",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from remote sockets.",
+        "UMask": "0x2",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "Tracker Snoops Outstanding Accumulator; Local Requests",
+        "EventCode": "0x9",
+        "EventName": "UNC_H_SNOOP_OCCUPANCY.LOCAL",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle.    This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from the local socket.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Tracker Cycles Full; Cycles Completely Used",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_H_TRACKER_CYCLES_FULL.ALL",
+        "BriefDescription": "Tracker Snoops Outstanding Accumulator; Remote Requests",
+        "EventCode": "0x9",
+        "EventName": "UNC_H_SNOOP_OCCUPANCY.REMOTE",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle.    This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from remote sockets.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Tracker Cycles Not Empty; Local Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL",
+        "BriefDescription": "Snoop Responses Received; RSPCNFLCT*",
+        "EventCode": "0x21",
+        "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspConflict.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI.",
+        "UMask": "0x40",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Tracker Cycles Not Empty; Remote Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE",
+        "BriefDescription": "Snoop Responses Received; RspI",
+        "EventCode": "0x21",
+        "EventName": "UNC_H_SNOOP_RESP.RSPI",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspI.  RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Tracker Cycles Not Empty; All Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_H_TRACKER_CYCLES_NE.ALL",
+        "BriefDescription": "M line forwarded from remote cache with no writeback to memory",
+        "EventCode": "0x21",
+        "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspIFwd.  This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states.  This is commonly returned with RFO transactions.  It can be either a HitM or a HitFE.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Tracker Occupancy Accumultor; Local Read Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL",
+        "BriefDescription": "Shared line response from remote cache",
+        "EventCode": "0x21",
+        "EventName": "UNC_H_SNOOP_RESP.RSPS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspS.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Tracker Occupancy Accumultor; Remote Read Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE",
+        "BriefDescription": "Shared line forwarded from remote cache",
+        "EventCode": "0x21",
+        "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd.  This is returned when a remote caching agent forwards data but holds on to its currentl copy.  This is common for data and code reads that hit in a remote socket in E or F state.",
+        "ScaleUnit": "64Bytes",
         "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Tracker Occupancy Accumultor; Local Write Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL",
+        "BriefDescription": "M line forwarded from remote cache along with writeback to memory",
+        "EventCode": "0x21",
+        "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of Rsp*Fwd*WB.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x20",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "Snoop Responses Received; Rsp*WB",
+        "EventCode": "0x21",
+        "EventName": "UNC_H_SNOOP_RESP.RSP_WB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspIWB or RspSWB.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership.",
         "UMask": "0x10",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Tracker Occupancy Accumultor; Remote Write Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE",
+        "BriefDescription": "Snoop Responses Received Local; Other",
+        "EventCode": "0x60",
+        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for all other snoop responses.",
+        "UMask": "0x80",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL",
+        "BriefDescription": "Snoop Responses Received Local; RspCnflct",
+        "EventCode": "0x60",
+        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT",
         "PerPkg": "1",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoops responses of RspConflict.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI.",
         "UMask": "0x40",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE",
+        "BriefDescription": "Snoop Responses Received Local; RspI",
+        "EventCode": "0x60",
+        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPI",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoops responses of RspI.  RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Data Pending Occupancy Accumultor; Local Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL",
+        "BriefDescription": "Snoop Responses Received Local; RspIFwd",
+        "EventCode": "0x60",
+        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoop responses of RspIFwd.  This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states.  This is commonly returned with RFO transactions.  It can be either a HitM or a HitFE.",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Data Pending Occupancy Accumultor; Remote Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE",
+        "BriefDescription": "Snoop Responses Received Local; RspS",
+        "EventCode": "0x60",
+        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS",
         "PerPkg": "1",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoop responses of RspS.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "AD Egress Full; Scheduler 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
+        "BriefDescription": "Snoop Responses Received Local; RspSFwd",
+        "EventCode": "0x60",
+        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of RspSFwd.  This is returned when a remote caching agent forwards data but holds on to its currentl copy.  This is common for data and code reads that hit in a remote socket in E or F state.",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "AD Egress Full; Scheduler 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
+        "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
+        "EventCode": "0x60",
+        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of Rsp*Fwd*WB.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
+        "UMask": "0x20",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "AD Egress Full; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL",
+        "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
+        "EventCode": "0x60",
+        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of RspIWB or RspSWB.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership.",
+        "UMask": "0x10",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "AK Egress Full; Scheduler 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
+        "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
+        "EventCode": "0x6C",
+        "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "AK Egress Full; Scheduler 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
+        "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
+        "EventCode": "0x6C",
+        "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+        "UMask": "0x4",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
+        "EventCode": "0x6C",
+        "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "AK Egress Full; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL",
+        "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
+        "EventCode": "0x6C",
+        "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x10",
-        "EventName": "UNC_H_TxR_BL.DRS_CACHE",
+        "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 0",
+        "EventCode": "0x1B",
+        "EventName": "UNC_H_TAD_REQUESTS_G0.REGION0",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 0",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x10",
-        "EventName": "UNC_H_TxR_BL.DRS_CORE",
+        "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 1",
+        "EventCode": "0x1B",
+        "EventName": "UNC_H_TAD_REQUESTS_G0.REGION1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 1",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x10",
-        "EventName": "UNC_H_TxR_BL.DRS_QPI",
+        "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 2",
+        "EventCode": "0x1B",
+        "EventName": "UNC_H_TAD_REQUESTS_G0.REGION2",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 2",
         "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "BL Egress Full; Scheduler 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x36",
-        "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
+        "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 3",
+        "EventCode": "0x1B",
+        "EventName": "UNC_H_TAD_REQUESTS_G0.REGION3",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 3",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "BL Egress Full; Scheduler 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x36",
-        "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
+        "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 4",
+        "EventCode": "0x1B",
+        "EventName": "UNC_H_TAD_REQUESTS_G0.REGION4",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 4",
+        "UMask": "0x10",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "BL Egress Full; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x36",
-        "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL",
+        "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 5",
+        "EventCode": "0x1B",
+        "EventName": "UNC_H_TAD_REQUESTS_G0.REGION5",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 5",
+        "UMask": "0x20",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Injection Starvation; For AK Ring",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6D",
-        "EventName": "UNC_H_TxR_STARVED.AK",
+        "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 6",
+        "EventCode": "0x1B",
+        "EventName": "UNC_H_TAD_REQUESTS_G0.REGION6",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 6",
+        "UMask": "0x40",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Injection Starvation; For BL Ring",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6D",
-        "EventName": "UNC_H_TxR_STARVED.BL",
+        "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 7",
+        "EventCode": "0x1B",
+        "EventName": "UNC_H_TAD_REQUESTS_G0.REGION7",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 7",
+        "UMask": "0x80",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
+        "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10",
+        "EventCode": "0x1C",
+        "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 10",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
+        "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11",
+        "EventCode": "0x1C",
+        "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 11",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
+        "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 8",
+        "EventCode": "0x1C",
+        "EventName": "UNC_H_TAD_REQUESTS_G1.REGION8",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 8",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
+        "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 9",
+        "EventCode": "0x1C",
+        "EventName": "UNC_H_TAD_REQUESTS_G1.REGION9",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 9",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x51",
-        "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD",
+        "BriefDescription": "Tracker Cycles Full; Cycles Completely Used",
+        "EventCode": "0x2",
+        "EventName": "UNC_H_TRACKER_CYCLES_FULL.ALL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the local HA tracker pool is completely used.  This can be used with edge detect to identify the number of situations when the pool became fully utilized.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, the system could be starved for RTIDs but not fill up the HA trackers.  HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the HA tracker pool (HT) is completely used including reserved HT entries.  It will not return valid count when BT is disabled.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x51",
-        "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD",
+        "BriefDescription": "Tracker Cycles Full; Cycles GP Completely Used",
+        "EventCode": "0x2",
+        "EventName": "UNC_H_TRACKER_CYCLES_FULL.GP",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of cycles when the local HA tracker pool is completely used.  This can be used with edge detect to identify the number of situations when the pool became fully utilized.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, the system could be starved for RTIDs but not fill up the HA trackers.  HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the general purpose (GP) HA tracker pool (HT) is completely used.  It will not return valid count when BT is disabled.",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x51",
-        "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD",
+        "BriefDescription": "Tracker Cycles Not Empty; All Requests",
+        "EventCode": "0x3",
+        "EventName": "UNC_H_TRACKER_CYCLES_NE.ALL",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Requests coming from both local and remote sockets.",
+        "UMask": "0x3",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x51",
-        "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD",
+        "BriefDescription": "Tracker Cycles Not Empty; Local Requests",
+        "EventCode": "0x3",
+        "EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from the local socket.",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "IOT Backpressure",
-        "Counter": "0,1,2",
-        "EventCode": "0x61",
-        "EventName": "UNC_H_IOT_BACKPRESSURE.SAT",
+        "BriefDescription": "Tracker Cycles Not Empty; Remote Requests",
+        "EventCode": "0x3",
+        "EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from remote sockets.",
+        "UMask": "0x2",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE Requests",
+        "EventCode": "0x4",
+        "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL",
+        "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+        "UMask": "0x40",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "IOT Backpressure",
-        "Counter": "0,1,2",
-        "EventCode": "0x61",
-        "EventName": "UNC_H_IOT_BACKPRESSURE.HUB",
+        "BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE Requests",
+        "EventCode": "0x4",
+        "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+        "UMask": "0x80",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "IOT Common Trigger Sequencer - Lo",
-        "Counter": "0,1,2",
-        "EventCode": "0x64",
-        "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS0",
+        "BriefDescription": "Tracker Occupancy Accumultor; Local Read Requests",
+        "EventCode": "0x4",
+        "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "IOT Common Trigger Sequencer - Lo",
-        "Counter": "0,1,2",
-        "EventCode": "0x64",
-        "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS1",
+        "BriefDescription": "Tracker Occupancy Accumultor; Remote Read Requests",
+        "EventCode": "0x4",
+        "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "IOT Common Trigger Sequencer - Hi",
-        "Counter": "0,1,2",
-        "EventCode": "0x65",
-        "EventName": "UNC_H_IOT_CTS_HI.CTS2",
+        "BriefDescription": "Tracker Occupancy Accumultor; Local Write Requests",
+        "EventCode": "0x4",
+        "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+        "UMask": "0x10",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "IOT Common Trigger Sequencer - Hi",
-        "Counter": "0,1,2",
-        "EventCode": "0x65",
-        "EventName": "UNC_H_IOT_CTS_HI.CTS3",
+        "BriefDescription": "Tracker Occupancy Accumultor; Remote Write Requests",
+        "EventCode": "0x4",
+        "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+        "UMask": "0x20",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "IOT Common Trigger Sequencer - Lo",
-        "Counter": "0,1,2",
-        "EventCode": "0x62",
-        "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS0",
+        "BriefDescription": "Data Pending Occupancy Accumultor; Local Requests",
+        "EventCode": "0x5",
+        "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress.  This can be used to calculate the queuing latency for two things.  (1) If the system is waiting for snoops, this will increase.  (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from the local socket.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "IOT Common Trigger Sequencer - Lo",
-        "Counter": "0,1,2",
-        "EventCode": "0x62",
-        "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS1",
+        "BriefDescription": "Data Pending Occupancy Accumultor; Remote Requests",
+        "EventCode": "0x5",
+        "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress.  This can be used to calculate the queuing latency for two things.  (1) If the system is waiting for snoops, this will increase.  (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from remote sockets.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x16",
-        "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
+        "BriefDescription": "Outbound NDR Ring Transactions; Non-data Responses",
+        "EventCode": "0xF",
+        "EventName": "UNC_H_TxR_AD.HOM",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of outbound transactions on the AD ring.  This can be filtered by the NDR and SNP message classes.  See the filter descriptions for more details.; Filter for outbound NDR transactions sent on the AD ring.  NDR stands for non-data response and is generally used for completions that do not include data.  AD NDR is used for transactions to remote sockets.",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x16",
-        "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
+        "BriefDescription": "AD Egress Full; All",
+        "EventCode": "0x2A",
+        "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "AD Egress Full; Cycles full from both schedulers",
+        "UMask": "0x3",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x16",
-        "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
+        "BriefDescription": "AD Egress Full; Scheduler 0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "AD Egress Full; Filter for cycles full  from scheduler bank 0",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x16",
-        "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
+        "BriefDescription": "AD Egress Full; Scheduler 1",
+        "EventCode": "0x2A",
+        "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "AD Egress Full; Filter for cycles full  from scheduler bank 1",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Outbound NDR Ring Transactions; Non-data Responses",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xF",
-        "EventName": "UNC_H_TxR_AD.HOM",
+        "BriefDescription": "AD Egress Not Empty; All",
+        "EventCode": "0x29",
+        "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "AD Egress Not Empty; Cycles full from both schedulers",
+        "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AD Egress Not Empty; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0",
         "PerPkg": "1",
+        "PublicDescription": "AD Egress Not Empty; Filter for cycles not empty  from scheduler bank 0",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AD Egress Not Empty; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1",
         "PerPkg": "1",
+        "PublicDescription": "AD Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "AD Egress Not Empty; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x29",
-        "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL",
+        "BriefDescription": "AD Egress Allocations; All",
+        "EventCode": "0x27",
+        "EventName": "UNC_H_TxR_AD_INSERTS.ALL",
         "PerPkg": "1",
+        "PublicDescription": "AD Egress Allocations; Allocations from both schedulers",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AD Egress Allocations; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "UNC_H_TxR_AD_INSERTS.SCHED0",
         "PerPkg": "1",
+        "PublicDescription": "AD Egress Allocations; Filter for allocations from scheduler bank 0",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AD Egress Allocations; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "UNC_H_TxR_AD_INSERTS.SCHED1",
         "PerPkg": "1",
+        "PublicDescription": "AD Egress Allocations; Filter for allocations from scheduler bank 1",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "AD Egress Allocations; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x27",
-        "EventName": "UNC_H_TxR_AD_INSERTS.ALL",
+        "BriefDescription": "AK Egress Full; All",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL",
+        "PerPkg": "1",
+        "PublicDescription": "AK Egress Full; Cycles full from both schedulers",
+        "UMask": "0x3",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "AK Egress Full; Scheduler 0",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
+        "PerPkg": "1",
+        "PublicDescription": "AK Egress Full; Filter for cycles full  from scheduler bank 0",
+        "UMask": "0x1",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "AK Egress Full; Scheduler 1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
+        "PerPkg": "1",
+        "PublicDescription": "AK Egress Full; Filter for cycles full  from scheduler bank 1",
+        "UMask": "0x2",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "AK Egress Not Empty; All",
+        "EventCode": "0x31",
+        "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL",
         "PerPkg": "1",
+        "PublicDescription": "AK Egress Not Empty; Cycles full from both schedulers",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AK Egress Not Empty; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0",
         "PerPkg": "1",
+        "PublicDescription": "AK Egress Not Empty; Filter for cycles not empty  from scheduler bank 0",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AK Egress Not Empty; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1",
         "PerPkg": "1",
+        "PublicDescription": "AK Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "AK Egress Not Empty; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x31",
-        "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL",
+        "BriefDescription": "AK Egress Allocations; All",
+        "EventCode": "0x2F",
+        "EventName": "UNC_H_TxR_AK_INSERTS.ALL",
         "PerPkg": "1",
+        "PublicDescription": "AK Egress Allocations; Allocations from both schedulers",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AK Egress Allocations; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2F",
         "EventName": "UNC_H_TxR_AK_INSERTS.SCHED0",
         "PerPkg": "1",
+        "PublicDescription": "AK Egress Allocations; Filter for allocations from scheduler bank 0",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AK Egress Allocations; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2F",
         "EventName": "UNC_H_TxR_AK_INSERTS.SCHED1",
         "PerPkg": "1",
+        "PublicDescription": "AK Egress Allocations; Filter for allocations from scheduler bank 1",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "AK Egress Allocations; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2F",
-        "EventName": "UNC_H_TxR_AK_INSERTS.ALL",
+        "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
+        "EventCode": "0x10",
+        "EventName": "UNC_H_TxR_BL.DRS_CACHE",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent to the cache.",
+        "UMask": "0x1",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
+        "EventCode": "0x10",
+        "EventName": "UNC_H_TxR_BL.DRS_CORE",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent directly to the requesting core.",
+        "UMask": "0x2",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
+        "EventCode": "0x10",
+        "EventName": "UNC_H_TxR_BL.DRS_QPI",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent to a remote socket over QPI.",
+        "UMask": "0x4",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "BL Egress Full; All",
+        "EventCode": "0x36",
+        "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL",
+        "PerPkg": "1",
+        "PublicDescription": "BL Egress Full; Cycles full from both schedulers",
+        "UMask": "0x3",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "BL Egress Full; Scheduler 0",
+        "EventCode": "0x36",
+        "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
+        "PerPkg": "1",
+        "PublicDescription": "BL Egress Full; Filter for cycles full  from scheduler bank 0",
+        "UMask": "0x1",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "BL Egress Full; Scheduler 1",
+        "EventCode": "0x36",
+        "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
+        "PerPkg": "1",
+        "PublicDescription": "BL Egress Full; Filter for cycles full  from scheduler bank 1",
+        "UMask": "0x2",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "BL Egress Not Empty; All",
+        "EventCode": "0x35",
+        "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL",
         "PerPkg": "1",
+        "PublicDescription": "BL Egress Not Empty; Cycles full from both schedulers",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "BL Egress Not Empty; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0",
         "PerPkg": "1",
+        "PublicDescription": "BL Egress Not Empty; Filter for cycles not empty  from scheduler bank 0",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "BL Egress Not Empty; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1",
         "PerPkg": "1",
+        "PublicDescription": "BL Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "BL Egress Not Empty; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL",
+        "BriefDescription": "BL Egress Allocations; All",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_TxR_BL_INSERTS.ALL",
         "PerPkg": "1",
+        "PublicDescription": "BL Egress Allocations; Allocations from both schedulers",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "BL Egress Allocations; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_H_TxR_BL_INSERTS.SCHED0",
         "PerPkg": "1",
+        "PublicDescription": "BL Egress Allocations; Filter for allocations from scheduler bank 0",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "BL Egress Allocations; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_H_TxR_BL_INSERTS.SCHED1",
         "PerPkg": "1",
+        "PublicDescription": "BL Egress Allocations; Filter for allocations from scheduler bank 1",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "BL Egress Allocations; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_H_TxR_BL_INSERTS.ALL",
+        "BriefDescription": "Injection Starvation; For AK Ring",
+        "EventCode": "0x6D",
+        "EventName": "UNC_H_TxR_STARVED.AK",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
+        "UMask": "0x1",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "Injection Starvation; For BL Ring",
+        "EventCode": "0x6D",
+        "EventName": "UNC_H_TxR_STARVED.BL",
+        "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
+        "UMask": "0x2",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0",
+        "EventCode": "0x18",
+        "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
+        "UMask": "0x1",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1",
+        "EventCode": "0x18",
+        "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
+        "UMask": "0x2",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2",
+        "EventCode": "0x18",
+        "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
+        "UMask": "0x4",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3",
+        "EventCode": "0x18",
+        "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
         "UMask": "0x4",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
         "UMask": "0x8",
         "Unit": "HA"
-    },
-    {
-        "BriefDescription": "HA AK Ring in Use; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3F",
-        "EventName": "UNC_H_RING_AK_USED.ALL",
-        "PerPkg": "1",
-        "UMask": "0xF",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "HA BL Ring in Use; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x40",
-        "EventName": "UNC_H_RING_BL_USED.ALL",
-        "PerPkg": "1",
-        "UMask": "0xF",
-        "Unit": "HA"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json
index cb1916f526074..a5457c7ba58b1 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json
@@ -1,1452 +1,1331 @@
 [
+    {
+        "BriefDescription": "Number of non data (control) flits transmitted . Derived from unc_q_txl_flits_g0.non_data",
+        "EventName": "QPI_CTL_BANDWIDTH_TX",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI.  This basically tracks the protocol overhead on the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This includes the header flits for data packets.",
+        "ScaleUnit": "8Bytes",
+        "UMask": "0x4",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data",
+        "EventName": "QPI_DATA_BANDWIDTH_TX",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI.  Each flit contains 64b of data.  This includes both DRS and NCB data flits (coherent and non-coherent).  This can be used to calculate the data bandwidth of the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This does not include the header flits that go in data packets.",
+        "ScaleUnit": "8Bytes",
+        "UMask": "0x2",
+        "Unit": "QPI LL"
+    },
     {
         "BriefDescription": "Number of qfclks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_Q_CLOCKTICKS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of clocks in the QPI LL.  This clock runs at 1/4th the GT/s speed of the QPI link.  For example, a 4GT/s link will have qfclk or 1GHz.  BDX does not support dynamic link speeds, so this frequency is fixed.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Count of CTO Events",
-        "Counter": "0,1,2,3",
         "EventCode": "0x38",
         "EventName": "UNC_Q_CTO_COUNT",
-        "ExtSel": "1",
         "PerPkg": "1",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "Direct 2 Core Spawning; Spawn Success",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT",
-        "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots.  If both slots trigger in a given cycle, the event will increment by 2.  You can use edge detect to count the number of cases when both events triggered.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits.  Had there been enough credits, the spawn would have worked as the RBT bit was set and the RBT tag matched.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Invalid",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss",
         "EventCode": "0x13",
-        "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT",
+        "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and there weren't enough Egress credits.   The valid bit was set.",
+        "UMask": "0x20",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Invalid",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits AND the RBT bit was not set, but the RBT tag matched.",
         "UMask": "0x8",
         "Unit": "QPI LL"
     },
+    {
+        "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid",
+        "EventCode": "0x13",
+        "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match, the valid bit was not set and there weren't enough Egress credits.",
+        "UMask": "0x80",
+        "Unit": "QPI LL"
+    },
     {
         "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_DIRECT2CORE.FAILURE_MISS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match although the valid bit was set and there were enough Egress credits.",
         "UMask": "0x10",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Invalid",
         "EventCode": "0x13",
-        "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS",
+        "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the route-back table (RBT) specified that the transaction should not trigger a direct2core tranaction.  This is common for IO transactions.  There were enough Egress credits and the RBT tag matched but the valid bit was not set.",
+        "UMask": "0x4",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss and Invalid",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and the valid bit was not set although there were enough Egress credits.",
         "UMask": "0x40",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Direct 2 Core Spawning; Spawn Success",
         "EventCode": "0x13",
-        "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS",
+        "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exlusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn was successful.  There were sufficient credits, the RBT valid bit was set and there was an RBT tag match.  The message was marked to spawn direct2core.",
+        "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Cycles in L1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_Q_L1_POWER_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of QPI qfclk cycles spent in L1 power mode.  L1 is a mode that totally shuts down a QPI link.  Use edge detect to count the number of instances when the QPI link entered L1.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Cycles in L0p",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_Q_RxL0P_POWER_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses.  Use edge detect to count the number of instances when the QPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Cycles in L0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "UNC_Q_RxL0_POWER_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Bypassed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_Q_RxL_BYPASSED",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "CRC Errors Detected; LinkInit",
+        "EventCode": "0x3",
+        "EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CRC errors detected in the QPI Agent.  Each QPI flit incorporates 8 bits of CRC for error detection.  This counts the number of flits where the CRC was able to detect an error.  After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during link initialization.",
+        "UMask": "0x1",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
+        "EventCode": "0x3",
+        "EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
+        "PerPkg": "1",
+        "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "VN0 Credit Consumed; DRS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the DRS message class.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
+    {
+        "BriefDescription": "VN0 Credit Consumed; HOM",
+        "EventCode": "0x1E",
+        "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the HOM message class.",
+        "UMask": "0x8",
+        "Unit": "QPI LL"
+    },
     {
         "BriefDescription": "VN0 Credit Consumed; NCB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCB message class.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "VN0 Credit Consumed; NCS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCS message class.",
         "UMask": "0x4",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "VN0 Credit Consumed; HOM",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "VN0 Credit Consumed; NDR",
         "EventCode": "0x1E",
-        "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NDR message class.",
+        "UMask": "0x20",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "VN0 Credit Consumed; SNP",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the SNP message class.",
         "UMask": "0x10",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "VN0 Credit Consumed; NDR",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1E",
-        "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR",
-        "ExtSel": "1",
+        "BriefDescription": "VN1 Credit Consumed; DRS",
+        "EventCode": "0x39",
+        "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the DRS message class.",
+        "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "VN1 Credit Consumed; DRS",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "VN1 Credit Consumed; HOM",
         "EventCode": "0x39",
-        "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the HOM message class.",
+        "UMask": "0x8",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "VN1 Credit Consumed; NCB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCB message class.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "VN1 Credit Consumed; NCS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCS message class.",
         "UMask": "0x4",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "VN1 Credit Consumed; HOM",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "VN1 Credit Consumed; NDR",
         "EventCode": "0x39",
-        "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NDR message class.",
+        "UMask": "0x20",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "VN1 Credit Consumed; SNP",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the SNP message class.",
         "UMask": "0x10",
         "Unit": "QPI LL"
     },
-    {
-        "BriefDescription": "VN1 Credit Consumed; NDR",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "QPI LL"
-    },
     {
         "BriefDescription": "VNA Credit Consumed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_Q_RxL_CYCLES_NE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Received - Group 0; Idle and Null Flits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_Q_RxL_FLITS_G0.IDLE",
+        "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN0",
+        "EventCode": "0xF",
+        "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN0",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors DRS flits only.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Received - Group 1; SNP Flits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_Q_RxL_FLITS_G1.SNP",
-        "ExtSel": "1",
+        "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN1",
+        "EventCode": "0xF",
+        "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN1",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors DRS flits only.",
+        "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Received - Group 1; HOM Request Flits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ",
-        "ExtSel": "1",
+        "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN0",
+        "EventCode": "0x12",
+        "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors HOM flits only.",
+        "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ",
-        "ExtSel": "1",
+        "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN1",
+        "EventCode": "0x12",
+        "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors HOM flits only.",
+        "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Received - Group 1; HOM Flits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_Q_RxL_FLITS_G1.HOM",
-        "ExtSel": "1",
+        "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN0",
+        "EventCode": "0x10",
+        "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN0",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCB flits only.",
+        "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Received - Group 1; DRS Data Flits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA",
-        "ExtSel": "1",
+        "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN1",
+        "EventCode": "0x10",
+        "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN1",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCB flits only.",
+        "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Received - Group 1; DRS Header Flits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA",
-        "ExtSel": "1",
+        "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN0",
+        "EventCode": "0x11",
+        "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCS flits only.",
+        "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_Q_RxL_FLITS_G1.DRS",
-        "ExtSel": "1",
+        "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN1",
+        "EventCode": "0x11",
+        "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN1",
         "PerPkg": "1",
-        "UMask": "0x18",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCS flits only.",
+        "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD",
-        "ExtSel": "1",
+        "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN0",
+        "EventCode": "0x14",
+        "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN0",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NDR flits only.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK",
-        "ExtSel": "1",
+        "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN1",
+        "EventCode": "0x14",
+        "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NDR flits only.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Received - Group 2; Non-Coherent data Rx Flits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA",
-        "ExtSel": "1",
+        "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN0",
+        "EventCode": "0x13",
+        "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN0",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors SNP flits only.",
+        "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Received - Group 2; Non-Coherent non-data Rx Flits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA",
-        "ExtSel": "1",
+        "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN1",
+        "EventCode": "0x13",
+        "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN1",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors SNP flits only.",
+        "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_Q_RxL_FLITS_G2.NCB",
-        "ExtSel": "1",
+        "BriefDescription": "Flits Received - Group 0; Idle and Null Flits",
+        "EventCode": "0x1",
+        "EventName": "UNC_Q_RxL_FLITS_G0.IDLE",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received over QPI that do not hold protocol payload.  When QPI is not in a power saving state, it continuously transmits flits across the link.  When there are no protocol flits to send, it will send IDLE and NULL flits  across.  These flits sometimes do carry a payload, such as credit returns, but are generall not considered part of the QPI bandwidth.",
+        "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_Q_RxL_FLITS_G2.NCS",
-        "ExtSel": "1",
+        "BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)",
+        "EventCode": "0x2",
+        "EventName": "UNC_Q_RxL_FLITS_G1.DRS",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits received over the NCB channel which transmits non-coherent data.",
+        "UMask": "0x18",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Rx Flit Buffer Allocations",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8",
-        "EventName": "UNC_Q_RxL_INSERTS",
+        "BriefDescription": "Flits Received - Group 1; DRS Data Flits",
+        "EventCode": "0x2",
+        "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits received over the NCB channel which transmits non-coherent data.  This includes only the data flits (not the header).",
+        "UMask": "0x8",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9",
-        "EventName": "UNC_Q_RxL_INSERTS_DRS.VN0",
-        "ExtSel": "1",
+        "BriefDescription": "Flits Received - Group 1; DRS Header Flits",
+        "EventCode": "0x2",
+        "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits received over the NCB channel which transmits non-coherent data.  This includes only the header flits (not the data).  This includes extended headers.",
+        "UMask": "0x10",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9",
-        "EventName": "UNC_Q_RxL_INSERTS_DRS.VN1",
-        "ExtSel": "1",
+        "BriefDescription": "Flits Received - Group 1; HOM Flits",
+        "EventCode": "0x2",
+        "EventName": "UNC_Q_RxL_FLITS_G1.HOM",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel.",
+        "UMask": "0x6",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC",
-        "EventName": "UNC_Q_RxL_INSERTS_HOM.VN0",
-        "ExtSel": "1",
+        "BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits",
+        "EventCode": "0x2",
+        "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel.  These are most commonly snoop responses, and this event can be used as a proxy for that.",
+        "UMask": "0x4",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC",
-        "EventName": "UNC_Q_RxL_INSERTS_HOM.VN1",
-        "ExtSel": "1",
+        "BriefDescription": "Flits Received - Group 1; HOM Request Flits",
+        "EventCode": "0x2",
+        "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel.  This basically counts the number of remote memory requests received over QPI.  In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA",
-        "EventName": "UNC_Q_RxL_INSERTS_NCB.VN0",
-        "ExtSel": "1",
+        "BriefDescription": "Flits Received - Group 1; SNP Flits",
+        "EventCode": "0x2",
+        "EventName": "UNC_Q_RxL_FLITS_G1.SNP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI.  These requests are contained in the snoop channel.  This does not include snoop responses, which are received on the home channel.",
+        "UMask": "0x1",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits",
+        "EventCode": "0x3",
+        "EventName": "UNC_Q_RxL_FLITS_G2.NCB",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits.  These packets are generally used to transmit non-coherent data across QPI.",
+        "UMask": "0xc",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Flits Received - Group 2; Non-Coherent data Rx Flits",
+        "EventCode": "0x3",
+        "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits.  These flits are generally used to transmit non-coherent data across QPI.  This does not include a count of the DRS (coherent) data flits.  This only counts the data flits, not the NCB headers.",
+        "UMask": "0x4",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Flits Received - Group 2; Non-Coherent non-data Rx Flits",
+        "EventCode": "0x3",
+        "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits.  These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits.  This includes extended headers.",
+        "UMask": "0x8",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits",
+        "EventCode": "0x3",
+        "EventName": "UNC_Q_RxL_FLITS_G2.NCS",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI.    This includes extended headers.",
+        "UMask": "0x10",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD",
+        "EventCode": "0x3",
+        "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets to the local socket which use the AK ring.",
+        "UMask": "0x1",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK",
+        "EventCode": "0x3",
+        "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets destined for Route-thru to a remote socket.",
+        "UMask": "0x2",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Rx Flit Buffer Allocations",
+        "EventCode": "0x8",
+        "EventName": "UNC_Q_RxL_INSERTS",
+        "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN0",
+        "EventCode": "0x9",
+        "EventName": "UNC_Q_RxL_INSERTS_DRS.VN0",
+        "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only DRS flits.",
+        "UMask": "0x1",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN1",
+        "EventCode": "0x9",
+        "EventName": "UNC_Q_RxL_INSERTS_DRS.VN1",
+        "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only DRS flits.",
+        "UMask": "0x2",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN0",
+        "EventCode": "0xC",
+        "EventName": "UNC_Q_RxL_INSERTS_HOM.VN0",
+        "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only HOM flits.",
+        "UMask": "0x1",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN1",
+        "EventCode": "0xC",
+        "EventName": "UNC_Q_RxL_INSERTS_HOM.VN1",
+        "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only HOM flits.",
+        "UMask": "0x2",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN0",
+        "EventCode": "0xA",
+        "EventName": "UNC_Q_RxL_INSERTS_NCB.VN0",
+        "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCB flits.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_Q_RxL_INSERTS_NCB.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCB flits.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB",
         "EventName": "UNC_Q_RxL_INSERTS_NCS.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCS flits.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB",
         "EventName": "UNC_Q_RxL_INSERTS_NCS.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCS flits.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE",
         "EventName": "UNC_Q_RxL_INSERTS_NDR.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NDR flits.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE",
         "EventName": "UNC_Q_RxL_INSERTS_NDR.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NDR flits.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD",
         "EventName": "UNC_Q_RxL_INSERTS_SNP.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only SNP flits.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD",
         "EventName": "UNC_Q_RxL_INSERTS_SNP.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only SNP flits.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - All Packets",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB",
         "EventName": "UNC_Q_RxL_OCCUPANCY",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - DRS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors DRS flits only.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - DRS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors DRS flits only.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - HOM; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors HOM flits only.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - HOM; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors HOM flits only.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - NCB; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCB flits only.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - NCB; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCB flits only.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - NCS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x17",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCS flits only.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - NCS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x17",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCS flits only.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - NDR; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1A",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NDR flits only.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - NDR; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1A",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NDR flits only.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - SNP; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors SNP flits only.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - SNP; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors SNP flits only.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Cycles in L0p",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD",
-        "EventName": "UNC_Q_TxL0P_POWER_CYCLES",
+        "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - HOM",
+        "EventCode": "0x35",
+        "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_DRS",
         "PerPkg": "1",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the HOM message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+        "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Cycles in L0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC",
-        "EventName": "UNC_Q_TxL0_POWER_CYCLES",
+        "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - DRS",
+        "EventCode": "0x35",
+        "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM",
+        "PerPkg": "1",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the DRS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+        "UMask": "0x8",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - SNP",
+        "EventCode": "0x35",
+        "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCB",
         "PerPkg": "1",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the SNP message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+        "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Tx Flit Buffer Bypassed",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_Q_TxL_BYPASSED",
+        "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NDR",
+        "EventCode": "0x35",
+        "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCS",
         "PerPkg": "1",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NDR message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+        "UMask": "0x4",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Tx Flit Buffer Cycles not Empty",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6",
-        "EventName": "UNC_Q_TxL_CYCLES_NE",
+        "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCS",
+        "EventCode": "0x35",
+        "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR",
         "PerPkg": "1",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+        "UMask": "0x20",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_Q_TxL_FLITS_G0.DATA",
+        "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCB",
+        "EventCode": "0x35",
+        "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_SNP",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCB message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+        "UMask": "0x10",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data",
-        "Counter": "0,1,2,3",
-        "EventName": "QPI_DATA_BANDWIDTH_TX",
+        "BriefDescription": "Stalls Sending to R3QPI on VN0; Egress Credits",
+        "EventCode": "0x35",
+        "EventName": "UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS",
         "PerPkg": "1",
-        "ScaleUnit": "8Bytes",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet because there were insufficient BGF credits.  For details on a message class granularity, use the Egress Credit Occupancy events.",
+        "UMask": "0x40",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Stalls Sending to R3QPI on VN0; GV",
+        "EventCode": "0x35",
+        "EventName": "UNC_Q_RxL_STALLS_VN0.GV",
+        "PerPkg": "1",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled because a GV transition (frequency transition) was taking place.",
+        "UMask": "0x80",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - HOM",
+        "EventCode": "0x3A",
+        "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_DRS",
+        "PerPkg": "1",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the HOM message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+        "UMask": "0x1",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - DRS",
+        "EventCode": "0x3A",
+        "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM",
+        "PerPkg": "1",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the DRS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+        "UMask": "0x8",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - SNP",
+        "EventCode": "0x3A",
+        "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCB",
+        "PerPkg": "1",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the SNP message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA",
+        "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NDR",
+        "EventCode": "0x3A",
+        "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCS",
         "PerPkg": "1",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NDR message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
         "UMask": "0x4",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Number of non data (control) flits transmitted . Derived from unc_q_txl_flits_g0.non_data",
-        "Counter": "0,1,2,3",
-        "EventName": "QPI_CTL_BANDWIDTH_TX",
+        "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCS",
+        "EventCode": "0x3A",
+        "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR",
         "PerPkg": "1",
-        "ScaleUnit": "8Bytes",
-        "UMask": "0x4",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+        "UMask": "0x20",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Transferred - Group 1; SNP Flits",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_Q_TxL_FLITS_G1.SNP",
-        "ExtSel": "1",
+        "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCB",
+        "EventCode": "0x3A",
+        "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_SNP",
+        "PerPkg": "1",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCB message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+        "UMask": "0x10",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Cycles in L0p",
+        "EventCode": "0xD",
+        "EventName": "UNC_Q_TxL0P_POWER_CYCLES",
+        "PerPkg": "1",
+        "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses.  Use edge detect to count the number of instances when the QPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Cycles in L0",
+        "EventCode": "0xC",
+        "EventName": "UNC_Q_TxL0_POWER_CYCLES",
+        "PerPkg": "1",
+        "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Tx Flit Buffer Bypassed",
+        "EventCode": "0x5",
+        "EventName": "UNC_Q_TxL_BYPASSED",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full",
+        "EventCode": "0x2",
+        "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is almost full, we block some but not all packets.",
+        "UMask": "0x2",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full",
+        "EventCode": "0x2",
+        "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is totally full, we are not allowed to send any packets.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ",
-        "ExtSel": "1",
+        "BriefDescription": "Tx Flit Buffer Cycles not Empty",
+        "EventCode": "0x6",
+        "EventName": "UNC_Q_TxL_CYCLES_NE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits",
+        "EventName": "UNC_Q_TxL_FLITS_G0.DATA",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI.  Each flit contains 64b of data.  This includes both DRS and NCB data flits (coherent and non-coherent).  This can be used to calculate the data bandwidth of the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This does not include the header flits that go in data packets.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ",
-        "ExtSel": "1",
+        "BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits",
+        "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI.  This basically tracks the protocol overhead on the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This includes the header flits for data packets.",
         "UMask": "0x4",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Transferred - Group 1; HOM Flits",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_Q_TxL_FLITS_G1.HOM",
-        "ExtSel": "1",
+        "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)",
+        "EventName": "UNC_Q_TxL_FLITS_G1.DRS",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.",
+        "UMask": "0x18",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits transmitted over the NCB channel which transmits non-coherent data.  This includes only the data flits (not the header).",
         "UMask": "0x8",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits transmitted over the NCB channel which transmits non-coherent data.  This includes only the header flits (not the data).  This includes extended headers.",
         "UMask": "0x10",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_Q_TxL_FLITS_G1.DRS",
-        "ExtSel": "1",
+        "BriefDescription": "Flits Transferred - Group 1; HOM Flits",
+        "EventName": "UNC_Q_TxL_FLITS_G1.HOM",
         "PerPkg": "1",
-        "UMask": "0x18",
+        "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel.",
+        "UMask": "0x6",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD",
-        "ExtSel": "1",
+        "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits",
+        "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel.  These are most commonly snoop responses, and this event can be used as a proxy for that.",
+        "UMask": "0x4",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits",
+        "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel.  This basically counts the number of remote memory requests transmitted over QPI.  In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.",
+        "UMask": "0x2",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Flits Transferred - Group 1; SNP Flits",
+        "EventName": "UNC_Q_TxL_FLITS_G1.SNP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI.  These requests are contained in the snoop channel.  This does not include snoop responses, which are transmitted on the home channel.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits",
         "EventCode": "0x1",
-        "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_TxL_FLITS_G2.NCB",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits.  These packets are generally used to transmit non-coherent data across QPI.",
+        "UMask": "0xc",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Flits Transferred - Group 2; Non-Coherent data Tx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits.  These flits are generally used to transmit non-coherent data across QPI.  This does not include a count of the DRS (coherent) data flits.  This only counts the data flits, not te NCB headers.",
         "UMask": "0x4",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Flits Transferred - Group 2; Non-Coherent non-data Tx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
-        "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits.  These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits.  This includes extended headers.",
+        "UMask": "0x8",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits",
+        "EventCode": "0x1",
+        "EventName": "UNC_Q_TxL_FLITS_G2.NCS",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI.    This includes extended headers.",
+        "UMask": "0x10",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD",
         "EventCode": "0x1",
-        "EventName": "UNC_Q_TxL_FLITS_G2.NCB",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets to the local socket which use the AK ring.",
+        "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK",
         "EventCode": "0x1",
-        "EventName": "UNC_Q_TxL_FLITS_G2.NCS",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets destined for Route-thru to a remote socket.",
+        "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Tx Flit Buffer Allocations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_Q_TxL_INSERTS",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Tx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Tx Flit Buffer Occupancy",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_Q_TxL_OCCUPANCY",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of flits in the TxQ.  Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO for HOM messages on AD.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO for HOM messages on AD.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for NDR messages on AD.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for NDR messages on AD.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO  for NDR messages on AD.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO  for NDR messages on AD.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for Snoop messages on AD.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for Snoop messages on AD.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x23",
         "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO fro Snoop messages on AD.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x23",
         "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO fro Snoop messages on AD.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR",
-        "Counter": "0,1,2,3",
         "EventCode": "0x25",
         "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  Local NDR message class to AK Egress.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for Shared VN",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
         "UMask": "0x4",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1F",
         "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  DRS message class to BL Egress.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1F",
         "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  DRS message class to BL Egress.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for Shared VN",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1F",
         "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  DRS message class to BL Egress.",
         "UMask": "0x4",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2B",
         "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2B",
         "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCB message class to BL Egress.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCB message class to BL Egress.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2C",
         "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2C",
         "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCS message class to BL Egress.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCS message class to BL Egress.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "VNA Credits Returned",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_Q_VNA_CREDIT_RETURNS",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of VNA credits returned.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "VNA Credits Pending Return - Occupancy",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "CRC Errors Detected; LinkInit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xF",
-        "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN0",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xF",
-        "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN1",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN0",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN1",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x10",
-        "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN0",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x10",
-        "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN1",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x11",
-        "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN0",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x11",
-        "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN1",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN0",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN1",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN0",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN1",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - HOM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_DRS",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - SNP",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCB",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NDR",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCS",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - DRS",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCB",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_SNP",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCS",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "Stalls Sending to R3QPI on VN0; Egress Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "Stalls Sending to R3QPI on VN0; GV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_Q_RxL_STALLS_VN0.GV",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - HOM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3A",
-        "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_DRS",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - SNP",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3A",
-        "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCB",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NDR",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3A",
-        "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCS",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - DRS",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3A",
-        "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCB",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3A",
-        "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_SNP",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCS",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3A",
-        "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.",
         "Unit": "QPI LL"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json
index 05fab7d2723ea..34dfc3cf22efe 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json
@@ -1,335 +1,344 @@
 [
     {
-        "BriefDescription": "DRAM Activate Count; Activate due to Read",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_M_ACT_COUNT.RD",
+        "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
+        "EventCode": "0x4",
+        "EventName": "LLC_MISSES.MEM_READ",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills).",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Activate Count; Activate due to Write",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_M_ACT_COUNT.WR",
+        "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
+        "EventCode": "0x4",
+        "EventName": "LLC_MISSES.MEM_WRITE",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM Activate Count; Activate due to Write",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_M_ACT_COUNT.BYP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
         "UMask": "0x8",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "DRAM Activate Count; Activate due to Read",
+        "EventCode": "0x1",
+        "EventName": "UNC_M_ACT_COUNT.RD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+        "UMask": "0x1",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "DRAM Activate Count; Activate due to Write",
+        "EventCode": "0x1",
+        "EventName": "UNC_M_ACT_COUNT.WR",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+        "UMask": "0x2",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "ACT command issued by 2 cycle bypass",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA1",
         "EventName": "UNC_M_BYP_CMDS.ACT",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_BYP_CMDS.ACT",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CAS command issued by 2 cycle bypass",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA1",
         "EventName": "UNC_M_BYP_CMDS.CAS",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_BYP_CMDS.CAS",
         "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "PRE command issued by 2 cycle bypass",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA1",
         "EventName": "UNC_M_BYP_CMDS.PRE",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_BYP_CMDS.PRE",
         "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
         "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.RD_REG",
+        "EventName": "UNC_M_CAS_COUNT.ALL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS commands issued on this channel.",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
         "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
+        "EventName": "UNC_M_CAS_COUNT.RD",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills).",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
         "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.RD",
+        "EventName": "UNC_M_CAS_COUNT.RD_REG",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Read CAS commands issued on this channel.  This includes both regular RD CAS commands as well as those with implicit Precharge.  AutoPre is only used in systems that are using closed page policy.  We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM",
         "EventCode": "0x4",
-        "EventName": "LLC_MISSES.MEM_READ",
+        "EventName": "UNC_M_CAS_COUNT.RD_RMM",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x3",
+        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
         "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.WR_WMM",
+        "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the number of underfill reads that are issued by the memory controller.  This will generally be about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ.  While it is possible for underfills to be issed in both WMM and RMM, this event counts both.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM",
         "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.WR_RMM",
+        "EventName": "UNC_M_CAS_COUNT.RD_WMM",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.WR",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel.",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
         "EventCode": "0x4",
-        "EventName": "LLC_MISSES.MEM_WRITE",
+        "EventName": "UNC_M_CAS_COUNT.WR_RMM",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0xC",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of Opportunistic DRAM Write CAS commands issued on this channel while in Read-Major-Mode.",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
         "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.ALL",
+        "EventName": "UNC_M_CAS_COUNT.WR_WMM",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode.",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.RD_WMM",
+        "BriefDescription": "Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter",
+        "EventCode": "0xff",
+        "EventName": "UNC_M_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.RD_RMM",
+        "BriefDescription": "Clockticks in the Memory Controller using one of the programmable counters",
+        "EventName": "UNC_M_CLOCKTICKS_P",
         "PerPkg": "1",
-        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_M_CLOCKTICKS_P",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_M_DCLOCKTICKS",
         "PerPkg": "1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM Precharge All Commands",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_M_DRAM_PRE_ALL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that the precharge all command was sent.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Number of DRAM Refreshes Issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
-        "EventName": "UNC_M_DRAM_REFRESH.PANIC",
+        "EventName": "UNC_M_DRAM_REFRESH.HIGH",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of refreshes issued.",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Number of DRAM Refreshes Issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
-        "EventName": "UNC_M_DRAM_REFRESH.HIGH",
+        "EventName": "UNC_M_DRAM_REFRESH.PANIC",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of refreshes issued.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "ECC Correctable Errors",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of ECC errors detected and corrected by the iMC on this channel.  This counter is only useful with ECC DRAM devices.  This count will increment one time for each correction regardless of the number of bits corrected.  The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
         "EventCode": "0x7",
-        "EventName": "UNC_M_MAJOR_MODES.READ",
+        "EventName": "UNC_M_MAJOR_MODES.ISOCH",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group these two modes together so that we can use four counters to track each of the major modes at one time.  These major modes are used whenever there is an ISOCH txn in the memory controller.  In these mode, only ISOCH transactions are processed.",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
         "EventCode": "0x7",
-        "EventName": "UNC_M_MAJOR_MODES.WRITE",
+        "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode is used to drain starved underfill reads.  Regular reads and writes are blocked and only underfill reads will be processed.",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
         "EventCode": "0x7",
-        "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
+        "EventName": "UNC_M_MAJOR_MODES.READ",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode is the default mode for the iMC, as reads are generally more critical to forward progress than writes.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
         "EventCode": "0x7",
-        "EventName": "UNC_M_MAJOR_MODES.ISOCH",
+        "EventName": "UNC_M_MAJOR_MODES.WRITE",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is triggered when the WPQ hits high occupancy and causes writes to be higher priority than reads.  This can cause blips in the available read bandwidth in the system and temporarily increase read latencies in order to achieve better bus utilizations and higher bandwidth.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Channel DLLOFF Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x84",
         "EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Channel PPD Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "UNC_M_POWER_CHANNEL_PPD",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles when all the ranks in the channel are in PPD mode.  If IBT=off is enabled, then this can be used to count those cycles.  If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x4",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x8",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x10",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x20",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x40",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x80",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Critical Throttle Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x86",
         "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the iMC is in critical thermal throttling.  When this happens, all traffic is blocked.  This should be rare unless something bad is going on in the platform.  There is no filtering by rank for this event.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "UNC_M_POWER_PCU_THROTTLING",
-        "Counter": "0,1,2,3",
         "EventCode": "0x42",
         "EventName": "UNC_M_POWER_PCU_THROTTLING",
         "PerPkg": "1",
@@ -337,2569 +346,2554 @@
     },
     {
         "BriefDescription": "Clock-Enabled Self-Refresh",
-        "Counter": "0,1,2,3",
         "EventCode": "0x43",
         "EventName": "UNC_M_POWER_SELF_REFRESH",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock.  This happens in some package C-states.  For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing.  One use of this is for Monroe technology.  Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.; Thermal throttling is performed per DIMM.  We support 3 DIMMs per channel.  This ID allows us to filter by ID.",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x4",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x8",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x10",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x20",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x40",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x80",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Read Preemption Count; Read over Read Preemption",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts another read.",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Read Preemption Count; Read over Write Preemption",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts a write.",
         "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
         "EventCode": "0x2",
-        "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+        "EventName": "UNC_M_PRE_COUNT.BYP",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of the page close counter expiring.  This does not include implicit precharge commands sent in auto-precharge mode.",
         "UMask": "0x2",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
+        "EventCode": "0x2",
+        "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of page misses.  This does not include explicit precharge commands sent with CAS commands in Auto-Precharge mode.  This does not include PRE commands sent as a result of the page close counter expiration.",
+        "UMask": "0x1",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "DRAM Precharge commands.; Precharge due to read",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_M_PRE_COUNT.RD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
         "UMask": "0x4",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM Precharge commands.; Precharge due to write",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_M_PRE_COUNT.WR",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
         "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_M_PRE_COUNT.BYP",
+        "BriefDescription": "Read CAS issued with HIGH priority",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "UNC_M_RD_CAS_PRIO.HIGH",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Read CAS issued with LOW priority",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA0",
         "EventName": "UNC_M_RD_CAS_PRIO.LOW",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_PRIO.LOW",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Read CAS issued with MEDIUM priority",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA0",
         "EventName": "UNC_M_RD_CAS_PRIO.MED",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_PRIO.MED",
         "UMask": "0x2",
         "Unit": "iMC"
     },
-    {
-        "BriefDescription": "Read CAS issued with HIGH priority",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "iMC"
-    },
     {
         "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA0",
         "EventName": "UNC_M_RD_CAS_PRIO.PANIC",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_PRIO.PANIC",
         "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK1",
+        "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK0.ALLBANKS",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK2",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK4",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK8",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK10",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK11",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK0",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK12",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK3",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK13",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 14",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK5",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK14",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK14",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 15",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK6",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK15",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK15",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK7",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK2",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK9",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK3",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK3",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK4",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK4",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK5",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK5",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK6",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK6",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK7",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK7",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK14",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK8",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK8",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK15",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK9",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK9",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK0.BANKG0",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK0.BANKG1",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK0.BANKG2",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK0.BANKG3",
         "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; All Banks",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK1",
+        "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK1.ALLBANKS",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK2",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK4",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 10",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK8",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK10",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 11",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK11",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 12",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK0",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK12",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 13",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK3",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK13",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 14",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK5",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK14",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK14",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 15",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK6",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK15",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK15",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 2",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK7",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK2",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 3",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK9",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK3",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK3",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 4",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK4",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK4",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 5",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK5",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK5",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 6",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK6",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK6",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 7",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK7",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK7",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 8",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK14",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK8",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK8",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 9",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK15",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK9",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK9",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK1.BANKG0",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK1.BANKG1",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK1.BANKG2",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK1.BANKG3",
         "UMask": "0x14",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 2; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_M_RD_CAS_RANK2.BANK0",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK2.BANK0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; All Banks",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK1",
+        "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK4.ALLBANKS",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 0",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK2",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 1",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK4",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 10",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK8",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK10",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 11",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK11",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 12",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK0",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK12",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 13",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK3",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK13",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 14",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK5",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK14",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK14",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 15",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK6",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK15",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK15",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 2",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK7",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK2",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 3",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK9",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK3",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK3",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 4",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK4",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK4",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 5",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK5",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK5",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 6",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK6",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK6",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 7",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK7",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK7",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 8",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK14",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK8",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK8",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 9",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK15",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK9",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK9",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK4.BANKG0",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK4.BANKG1",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK4.BANKG2",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK4.BANKG3",
         "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; All Banks",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK1",
+        "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK5.ALLBANKS",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 0",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK2",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 1",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK4",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 10",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK8",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK10",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 11",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK11",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 12",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK0",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK12",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 13",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK3",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK13",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 14",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK5",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK14",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK14",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 15",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK6",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK15",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK15",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 2",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK7",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK2",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 3",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK9",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK3",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK3",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 4",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK4",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK4",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 5",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK5",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK5",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 6",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK6",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK6",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 7",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK7",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK7",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 8",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK14",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK8",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK8",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 9",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK15",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK9",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK9",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK5.BANKG0",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK5.BANKG1",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK5.BANKG2",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK5.BANKG3",
         "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; All Banks",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK1",
+        "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK6.ALLBANKS",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 0",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK2",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 1",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK4",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 10",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK8",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK10",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 11",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK11",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 12",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK0",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK12",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 13",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK3",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK13",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 14",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK5",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK14",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK14",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 15",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK6",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK15",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK15",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 2",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK7",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK2",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 3",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK9",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK3",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK3",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 4",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK4",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK4",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 5",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK5",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK5",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 6",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK6",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK6",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 7",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK7",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK7",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 8",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK14",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK8",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK8",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 9",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK15",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK9",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK9",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK6.BANKG0",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK6.BANKG1",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK6.BANKG2",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK6.BANKG3",
         "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; All Banks",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK1",
+        "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK7.ALLBANKS",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK2",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 1",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK4",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 10",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK8",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK10",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK11",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK0",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK12",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK3",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK13",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK5",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK14",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK14",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK6",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK15",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK15",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 2",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK7",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK2",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 3",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK9",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK3",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK3",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 4",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK4",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK4",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 5",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK5",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK5",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 6",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK6",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK6",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 7",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK7",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK7",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 8",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK14",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK8",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK8",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 9",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK15",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK9",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK9",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK7.BANKG0",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK7.BANKG1",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK7.BANKG2",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_RD_CAS_RANK7.BANKG3",
         "UMask": "0x14",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Read Pending Queue Not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0x11",
         "EventName": "UNC_M_RPQ_CYCLES_NE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Read Pending Queue is not empty.  This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Read Pending Queue Allocations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_M_RPQ_INSERTS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "VMSE MXB write buffer occupancy",
-        "Counter": "0,1,2,3",
         "EventCode": "0x91",
         "EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_VMSE_MXB_WR_OCCUPANCY",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in WMM",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in RMM",
         "EventCode": "0x90",
-        "EventName": "UNC_M_VMSE_WR_PUSH.WMM",
+        "EventName": "UNC_M_VMSE_WR_PUSH.RMM",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "UNC_M_VMSE_WR_PUSH.RMM",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in RMM",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in WMM",
         "EventCode": "0x90",
-        "EventName": "UNC_M_VMSE_WR_PUSH.RMM",
+        "EventName": "UNC_M_VMSE_WR_PUSH.WMM",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "UNC_M_VMSE_WR_PUSH.WMM",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WMM_TO_RMM.LOW_THRESH",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Transition from WMM to RMM because of low threshold",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "UNC_M_WMM_TO_RMM.STARVE",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WMM_TO_RMM.STARVE",
         "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Transition from WMM to RMM because of low threshold",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WMM_TO_RMM.VMSE_RETRY",
         "UMask": "0x4",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Write Pending Queue Full Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_M_WPQ_CYCLES_FULL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Write Pending Queue Not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_M_WPQ_CYCLES_NE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Write Pending Queue CAM Match",
-        "Counter": "0,1,2,3",
         "EventCode": "0x23",
         "EventName": "UNC_M_WPQ_READ_HIT",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Write Pending Queue CAM Match",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_M_WPQ_WRITE_HIT",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Not getting the requested Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC1",
         "EventName": "UNC_M_WRONG_MM",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WRONG_MM",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 0; All Banks",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
+        "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK0.ALLBANKS",
+        "UMask": "0x10",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK0",
+        "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK0",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK1",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK1",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK2",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK10",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK4",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK11",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK8",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK12",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK13",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 14",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK14",
+        "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK14",
+        "UMask": "0xe",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 15",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK15",
+        "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK15",
+        "UMask": "0xf",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK2",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK3",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK3",
         "UMask": "0x3",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK4",
+        "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK4",
+        "UMask": "0x4",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK5",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK5",
         "UMask": "0x5",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK6",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK6",
         "UMask": "0x6",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK7",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK7",
         "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 8",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK9",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK8",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK8",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 9",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK9",
         "PerPkg": "1",
-        "UMask": "0xA",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK11",
-        "PerPkg": "1",
-        "UMask": "0xB",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK12",
-        "PerPkg": "1",
-        "UMask": "0xC",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK13",
-        "PerPkg": "1",
-        "UMask": "0xD",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 14",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK14",
-        "PerPkg": "1",
-        "UMask": "0xE",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 15",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK15",
-        "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK9",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK0.BANKG0",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK0.BANKG1",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK0.BANKG2",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK0.BANKG3",
         "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; All Banks",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK1.ALLBANKS",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 0",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK2",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 1",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK4",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 10",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK8",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK10",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 11",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK11",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 12",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK12",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 13",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK3",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK13",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 14",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK5",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK14",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK14",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 15",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK6",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK15",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK15",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 2",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK7",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK2",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 3",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK9",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK3",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK3",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 4",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK4",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK4",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 5",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK5",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK5",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 6",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK6",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK6",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 7",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK7",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK7",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 8",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK14",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK8",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK8",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 9",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK15",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK9",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK9",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK1.BANKG0",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK1.BANKG1",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK1.BANKG2",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK1.BANKG3",
         "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; All Banks",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK4.ALLBANKS",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 0",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK2",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 1",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK4",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 10",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK8",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK10",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 11",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK11",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 12",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK12",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 13",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK3",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK13",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 14",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK5",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK14",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK14",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 15",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK6",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK15",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK15",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 2",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK7",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK2",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 3",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK9",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK3",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK3",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 4",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK4",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK4",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 5",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK5",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK5",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 6",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK6",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK6",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 7",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK7",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK7",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 8",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK14",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK8",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK8",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 9",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK15",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK9",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK9",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK4.BANKG0",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK4.BANKG1",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK4.BANKG2",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK4.BANKG3",
         "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; All Banks",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK5.ALLBANKS",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 0",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK2",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 1",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK4",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 10",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK8",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK10",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 11",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK11",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 12",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK12",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 13",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK3",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK13",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 14",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK5",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK14",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK14",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 15",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK6",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK15",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK15",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 2",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK7",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK2",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 3",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK9",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK3",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK3",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 4",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK4",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK4",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 5",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK5",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK5",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 6",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK6",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK6",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 7",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK7",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK7",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 8",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK14",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK8",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK8",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 9",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK15",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK9",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK9",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK5.BANKG0",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK5.BANKG1",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK5.BANKG2",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK5.BANKG3",
         "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; All Banks",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK6.ALLBANKS",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 0",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK2",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 1",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK4",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 10",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK8",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK10",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 11",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK11",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 12",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK12",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 13",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK3",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK13",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 14",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK5",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK14",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK14",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 15",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK6",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK15",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK15",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 2",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK7",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK2",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 3",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK9",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK3",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK3",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 4",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK4",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK4",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 5",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK5",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK5",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 6",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK6",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK6",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 7",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK7",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK7",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 8",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK14",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK8",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK8",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 9",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK15",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK9",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK9",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK6.BANKG0",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK6.BANKG1",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK6.BANKG2",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK6.BANKG3",
         "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; All Banks",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK7.ALLBANKS",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK2",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK4",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 10",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK8",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK10",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 11",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK11",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK12",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK3",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK13",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK5",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK14",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK14",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK6",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK15",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK15",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 2",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK7",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK2",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 3",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK9",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK3",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK3",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 4",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK4",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK4",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 5",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK5",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK5",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 6",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK6",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK6",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK7",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK7",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 8",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK14",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK8",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK8",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 9",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK15",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK9",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK9",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK7.BANKG0",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK7.BANKG1",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK7.BANKG2",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_WR_CAS_RANK7.BANKG3",
         "UMask": "0x14",
         "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "Clockticks in the Memory Controller using one of the programmable counters",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_M_CLOCKTICKS_P",
-        "PerPkg": "1",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter",
-        "Counter": "FIXED",
-        "EventCode": "0xff",
-        "EventName": "UNC_M_CLOCKTICKS",
-        "PerPkg": "1",
-        "Unit": "iMC"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json
index 289a726c9ac37..495e34ee5bfba 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json
@@ -1,502 +1,508 @@
 [
     {
         "BriefDescription": "Total Write Cache Occupancy; Any Source",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.",
         "UMask": "0x1",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Total Write Cache Occupancy; Select Source",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time.",
         "UMask": "0x2",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Clocks in the IRP",
-        "Counter": "0,1",
         "EventName": "UNC_I_CLOCKTICKS",
         "PerPkg": "1",
+        "PublicDescription": "Number of clocks in the IRP.",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Coherent Ops; PCIRdCur",
-        "Counter": "0,1",
+        "BriefDescription": "Coherent Ops; CLFlush",
         "EventCode": "0x13",
-        "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
+        "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+        "UMask": "0x80",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Coherent Ops; CRd",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_I_COHERENT_OPS.CRD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
         "UMask": "0x2",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Coherent Ops; DRd",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_I_COHERENT_OPS.DRD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
         "UMask": "0x4",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Coherent Ops; RFO",
-        "Counter": "0,1",
+        "BriefDescription": "Coherent Ops; PCIDCAHin5t",
         "EventCode": "0x13",
-        "EventName": "UNC_I_COHERENT_OPS.RFO",
+        "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+        "UMask": "0x20",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Coherent Ops; PCIRdCur",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+        "UMask": "0x1",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Coherent Ops; PCIItoM",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_I_COHERENT_OPS.PCITOM",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
         "UMask": "0x10",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Coherent Ops; PCIDCAHin5t",
-        "Counter": "0,1",
+        "BriefDescription": "Coherent Ops; RFO",
         "EventCode": "0x13",
-        "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
+        "EventName": "UNC_I_COHERENT_OPS.RFO",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+        "UMask": "0x8",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Coherent Ops; WbMtoI",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
         "UMask": "0x40",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Coherent Ops; CLFlush",
-        "Counter": "0,1",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
-        "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "IRP"
-    },
-    {
-        "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
-        "Counter": "0,1",
-        "EventCode": "0x14",
-        "EventName": "UNC_I_MISC0.FAST_REQ",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "IRP"
-    },
-    {
-        "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
-        "Counter": "0,1",
+        "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
         "EventCode": "0x14",
-        "EventName": "UNC_I_MISC0.FAST_REJ",
+        "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
+        "UMask": "0x10",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
         "PerPkg": "1",
+        "PublicDescription": "UNC_I_MISC0.2ND_RD_INSERT",
         "UMask": "0x4",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
         "PerPkg": "1",
+        "PublicDescription": "UNC_I_MISC0.2ND_WR_INSERT",
         "UMask": "0x8",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
-        "Counter": "0,1",
+        "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
         "EventCode": "0x14",
-        "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
+        "EventName": "UNC_I_MISC0.FAST_REJ",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "UNC_I_MISC0.FAST_REJ",
+        "UMask": "0x2",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
+        "EventCode": "0x14",
+        "EventName": "UNC_I_MISC0.FAST_REQ",
+        "PerPkg": "1",
+        "PublicDescription": "UNC_I_MISC0.FAST_REQ",
+        "UMask": "0x1",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_I_MISC0.FAST_XFER",
         "PerPkg": "1",
+        "PublicDescription": "UNC_I_MISC0.FAST_XFER",
         "UMask": "0x20",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_I_MISC0.PF_ACK_HINT",
         "PerPkg": "1",
+        "PublicDescription": "UNC_I_MISC0.PF_ACK_HINT",
         "UMask": "0x40",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Misc Events - Set 0; Prefetch TimeOut",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_I_MISC0.PF_TIMEOUT",
         "PerPkg": "1",
+        "PublicDescription": "Indicates the fetch for a previous prefetch wasn't accepted by the prefetch.   This happens in the case of a prefetch TimeOut",
         "UMask": "0x80",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
-        "Counter": "0,1",
+        "BriefDescription": "Misc Events - Set 1; Data Throttled",
         "EventCode": "0x15",
-        "EventName": "UNC_I_MISC1.SLOW_I",
+        "EventName": "UNC_I_MISC1.DATA_THROTTLE",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "IRP throttled switch data",
+        "UMask": "0x80",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
-        "Counter": "0,1",
+        "BriefDescription": "Misc Events - Set 1",
         "EventCode": "0x15",
-        "EventName": "UNC_I_MISC1.SLOW_S",
+        "EventName": "UNC_I_MISC1.LOST_FWD",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "UNC_I_MISC1.LOST_FWD",
+        "UMask": "0x10",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
-        "Counter": "0,1",
+        "BriefDescription": "Misc Events - Set 1; Received Invalid",
         "EventCode": "0x15",
-        "EventName": "UNC_I_MISC1.SLOW_E",
+        "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
+        "UMask": "0x20",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
-        "Counter": "0,1",
+        "BriefDescription": "Misc Events - Set 1; Received Valid",
         "EventCode": "0x15",
-        "EventName": "UNC_I_MISC1.SLOW_M",
+        "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
+        "UMask": "0x40",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 1",
-        "Counter": "0,1",
+        "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
         "EventCode": "0x15",
-        "EventName": "UNC_I_MISC1.LOST_FWD",
+        "EventName": "UNC_I_MISC1.SLOW_E",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
+        "UMask": "0x4",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Received Invalid",
-        "Counter": "0,1",
+        "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
         "EventCode": "0x15",
-        "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
+        "EventName": "UNC_I_MISC1.SLOW_I",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
+        "UMask": "0x1",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Received Valid",
-        "Counter": "0,1",
+        "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
         "EventCode": "0x15",
-        "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
+        "EventName": "UNC_I_MISC1.SLOW_M",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
+        "UMask": "0x8",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Data Throttled",
-        "Counter": "0,1",
+        "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
         "EventCode": "0x15",
-        "EventName": "UNC_I_MISC1.DATA_THROTTLE",
+        "EventName": "UNC_I_MISC1.SLOW_S",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
+        "UMask": "0x2",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "AK Ingress Occupancy",
-        "Counter": "0,1",
         "EventCode": "0xA",
         "EventName": "UNC_I_RxR_AK_INSERTS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the AK Ingress.  This queue is where the IRP receives responses from R2PCIe (the ring).",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
-        "Counter": "0,1",
         "EventCode": "0x4",
         "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "BL Ingress Occupancy - DRS",
-        "Counter": "0,1",
         "EventCode": "0x1",
         "EventName": "UNC_I_RxR_BL_DRS_INSERTS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "UNC_I_RxR_BL_DRS_OCCUPANCY",
-        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "BL Ingress Occupancy - NCB",
-        "Counter": "0,1",
         "EventCode": "0x2",
         "EventName": "UNC_I_RxR_BL_NCB_INSERTS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "UNC_I_RxR_BL_NCB_OCCUPANCY",
-        "Counter": "0,1",
         "EventCode": "0x8",
         "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
-        "Counter": "0,1",
         "EventCode": "0x6",
         "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "BL Ingress Occupancy - NCS",
-        "Counter": "0,1",
         "EventCode": "0x3",
         "EventName": "UNC_I_RxR_BL_NCS_INSERTS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "UNC_I_RxR_BL_NCS_OCCUPANCY",
-        "Counter": "0,1",
         "EventCode": "0x9",
         "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Snoop Responses; Miss",
-        "Counter": "0,1",
+        "BriefDescription": "Snoop Responses; Hit E or S",
         "EventCode": "0x17",
-        "EventName": "UNC_I_SNOOP_RESP.MISS",
+        "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "UNC_I_SNOOP_RESP.HIT_ES",
+        "UMask": "0x4",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Snoop Responses; Hit I",
-        "Counter": "0,1",
         "EventCode": "0x17",
         "EventName": "UNC_I_SNOOP_RESP.HIT_I",
         "PerPkg": "1",
+        "PublicDescription": "UNC_I_SNOOP_RESP.HIT_I",
         "UMask": "0x2",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Snoop Responses; Hit E or S",
-        "Counter": "0,1",
+        "BriefDescription": "Snoop Responses; Hit M",
         "EventCode": "0x17",
-        "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
+        "EventName": "UNC_I_SNOOP_RESP.HIT_M",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "UNC_I_SNOOP_RESP.HIT_M",
+        "UMask": "0x8",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Snoop Responses; Hit M",
-        "Counter": "0,1",
+        "BriefDescription": "Snoop Responses; Miss",
         "EventCode": "0x17",
-        "EventName": "UNC_I_SNOOP_RESP.HIT_M",
+        "EventName": "UNC_I_SNOOP_RESP.MISS",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "UNC_I_SNOOP_RESP.MISS",
+        "UMask": "0x1",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Snoop Responses; SnpCode",
-        "Counter": "0,1",
         "EventCode": "0x17",
         "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
         "PerPkg": "1",
+        "PublicDescription": "UNC_I_SNOOP_RESP.SNPCODE",
         "UMask": "0x10",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Snoop Responses; SnpData",
-        "Counter": "0,1",
         "EventCode": "0x17",
         "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
         "PerPkg": "1",
+        "PublicDescription": "UNC_I_SNOOP_RESP.SNPDATA",
         "UMask": "0x20",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Snoop Responses; SnpInv",
-        "Counter": "0,1",
         "EventCode": "0x17",
         "EventName": "UNC_I_SNOOP_RESP.SNPINV",
         "PerPkg": "1",
+        "PublicDescription": "UNC_I_SNOOP_RESP.SNPINV",
         "UMask": "0x40",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Inbound Transaction Count; Reads",
-        "Counter": "0,1",
+        "BriefDescription": "Inbound Transaction Count; Atomic",
         "EventCode": "0x16",
-        "EventName": "UNC_I_TRANSACTIONS.READS",
+        "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions",
+        "UMask": "0x10",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Inbound Transaction Count; Writes",
-        "Counter": "0,1",
+        "BriefDescription": "Inbound Transaction Count; Other",
         "EventCode": "0x16",
-        "EventName": "UNC_I_TRANSACTIONS.WRITES",
+        "EventName": "UNC_I_TRANSACTIONS.OTHER",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions.",
+        "UMask": "0x20",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Inbound Transaction Count; Read Prefetches",
-        "Counter": "0,1",
         "EventCode": "0x16",
         "EventName": "UNC_I_TRANSACTIONS.RD_PREF",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.",
         "UMask": "0x4",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Inbound Transaction Count; Write Prefetches",
-        "Counter": "0,1",
-        "EventCode": "0x16",
-        "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
-        "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "IRP"
-    },
-    {
-        "BriefDescription": "Inbound Transaction Count; Atomic",
-        "Counter": "0,1",
+        "BriefDescription": "Inbound Transaction Count; Reads",
         "EventCode": "0x16",
-        "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
+        "EventName": "UNC_I_TRANSACTIONS.READS",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).",
+        "UMask": "0x1",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Inbound Transaction Count; Other",
-        "Counter": "0,1",
+        "BriefDescription": "Inbound Transaction Count; Writes",
         "EventCode": "0x16",
-        "EventName": "UNC_I_TRANSACTIONS.OTHER",
+        "EventName": "UNC_I_TRANSACTIONS.WRITES",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only write requests.  Each write request should have a prefetch, so there is no need to explicitly track these requests.",
+        "UMask": "0x2",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Inbound Transaction Count; Select Source",
-        "Counter": "0,1",
+        "BriefDescription": "Inbound Transaction Count; Write Prefetches",
         "EventCode": "0x16",
-        "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ",
+        "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of write prefetches.",
+        "UMask": "0x8",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "No AD Egress Credit Stalls",
-        "Counter": "0,1",
         "EventCode": "0x18",
         "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "No BL Egress Credit Stalls",
-        "Counter": "0,1",
         "EventCode": "0x19",
         "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Outbound Read Requests",
-        "Counter": "0,1",
         "EventCode": "0xE",
         "EventName": "UNC_I_TxR_DATA_INSERTS_NCB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Outbound Read Requests",
-        "Counter": "0,1",
         "EventCode": "0xF",
         "EventName": "UNC_I_TxR_DATA_INSERTS_NCS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Outbound Request Queue Occupancy",
-        "Counter": "0,1",
         "EventCode": "0xD",
         "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY",
         "PerPkg": "1",
+        "PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices).  This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Number of uclks in domain",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_R2_CLOCKTICKS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of uclks in the R2PCIe uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
+        "Unit": "R2PCIe"
+    },
+    {
+        "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
+        "EventCode": "0x2D",
+        "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "R2PCIe"
+    },
+    {
+        "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
+        "EventCode": "0x2D",
+        "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
+        "PerPkg": "1",
+        "UMask": "0x8",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
-        "Counter": "0,1",
         "EventCode": "0x2D",
         "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
         "PerPkg": "1",
@@ -505,7 +511,6 @@
     },
     {
         "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
-        "Counter": "0,1",
         "EventCode": "0x2D",
         "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
         "PerPkg": "1",
@@ -513,263 +518,326 @@
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
-        "Counter": "0,1",
-        "EventCode": "0x2D",
-        "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
+        "BriefDescription": "R2PCIe IIO Credit Acquired; DRS",
+        "EventCode": "0x33",
+        "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.",
+        "UMask": "0x8",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
-        "Counter": "0,1",
-        "EventCode": "0x2D",
-        "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
+        "BriefDescription": "R2PCIe IIO Credit Acquired; NCB",
+        "EventCode": "0x33",
+        "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.",
+        "UMask": "0x10",
+        "Unit": "R2PCIe"
+    },
+    {
+        "BriefDescription": "R2PCIe IIO Credit Acquired; NCS",
+        "EventCode": "0x33",
+        "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.",
+        "UMask": "0x20",
+        "Unit": "R2PCIe"
+    },
+    {
+        "BriefDescription": "R2PCIe IIO Credits in Use; DRS",
+        "EventCode": "0x32",
+        "EventName": "UNC_R2_IIO_CREDITS_USED.DRS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.",
         "UMask": "0x8",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "R2 AD Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "R2PCIe IIO Credits in Use; NCB",
+        "EventCode": "0x32",
+        "EventName": "UNC_R2_IIO_CREDITS_USED.NCB",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.",
+        "UMask": "0x10",
+        "Unit": "R2PCIe"
+    },
+    {
+        "BriefDescription": "R2PCIe IIO Credits in Use; NCS",
+        "EventCode": "0x32",
+        "EventName": "UNC_R2_IIO_CREDITS_USED.NCS",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.",
+        "UMask": "0x20",
+        "Unit": "R2PCIe"
+    },
+    {
+        "BriefDescription": "R2 AD Ring in Use; All",
         "EventCode": "0x7",
-        "EventName": "UNC_R2_RING_AD_USED.CW_EVEN",
+        "EventName": "UNC_R2_RING_AD_USED.ALL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xf",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "R2 AD Ring in Use; Counterclockwise",
         "EventCode": "0x7",
-        "EventName": "UNC_R2_RING_AD_USED.CW_ODD",
+        "EventName": "UNC_R2_RING_AD_USED.CCW",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xc",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CCW_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
         "UMask": "0x4",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CCW_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CW",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
         "UMask": "0x3",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "R2 AD Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "R2 AD Ring in Use; Clockwise and Even",
         "EventCode": "0x7",
-        "EventName": "UNC_R2_RING_AD_USED.CCW",
+        "EventName": "UNC_R2_RING_AD_USED.CW_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "AK Ingress Bounced; Up",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_R2_RING_AK_BOUNCES.UP",
+        "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd",
+        "EventCode": "0x7",
+        "EventName": "UNC_R2_RING_AD_USED.CW_ODD",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+        "UMask": "0x2",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "AK Ingress Bounced; Dn",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_R2_RING_AK_BOUNCES.DN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.",
         "UMask": "0x2",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "R2 AK Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8",
-        "EventName": "UNC_R2_RING_AK_USED.CW_EVEN",
+        "BriefDescription": "AK Ingress Bounced; Up",
+        "EventCode": "0x12",
+        "EventName": "UNC_R2_RING_AK_BOUNCES.UP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.",
         "UMask": "0x1",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "R2 AK Ring in Use; All",
         "EventCode": "0x8",
-        "EventName": "UNC_R2_RING_AK_USED.CW_ODD",
+        "EventName": "UNC_R2_RING_AK_USED.ALL",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xf",
+        "Unit": "R2PCIe"
+    },
+    {
+        "BriefDescription": "R2 AK Ring in Use; Counterclockwise",
+        "EventCode": "0x8",
+        "EventName": "UNC_R2_RING_AK_USED.CCW",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xc",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CCW_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
         "UMask": "0x4",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CCW_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CW",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
         "UMask": "0x3",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "R2 AK Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "R2 AK Ring in Use; Clockwise and Even",
         "EventCode": "0x8",
-        "EventName": "UNC_R2_RING_AK_USED.CCW",
+        "EventName": "UNC_R2_RING_AK_USED.CW_EVEN",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+        "UMask": "0x1",
+        "Unit": "R2PCIe"
+    },
+    {
+        "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd",
+        "EventCode": "0x8",
+        "EventName": "UNC_R2_RING_AK_USED.CW_ODD",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+        "UMask": "0x2",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "R2 BL Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "R2 BL Ring in Use; All",
         "EventCode": "0x9",
-        "EventName": "UNC_R2_RING_BL_USED.CW_EVEN",
+        "EventName": "UNC_R2_RING_BL_USED.ALL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xf",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "R2 BL Ring in Use; Counterclockwise",
         "EventCode": "0x9",
-        "EventName": "UNC_R2_RING_BL_USED.CW_ODD",
+        "EventName": "UNC_R2_RING_BL_USED.CCW",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xc",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CCW_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
         "UMask": "0x4",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CCW_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CW",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
         "UMask": "0x3",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "R2 BL Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "R2 BL Ring in Use; Clockwise and Even",
         "EventCode": "0x9",
-        "EventName": "UNC_R2_RING_BL_USED.CCW",
+        "EventName": "UNC_R2_RING_BL_USED.CW_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "R2 IV Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd",
+        "EventCode": "0x9",
+        "EventName": "UNC_R2_RING_BL_USED.CW_ODD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+        "UMask": "0x2",
+        "Unit": "R2PCIe"
+    },
+    {
+        "BriefDescription": "R2 IV Ring in Use; Any",
         "EventCode": "0xA",
-        "EventName": "UNC_R2_RING_IV_USED.CW",
+        "EventName": "UNC_R2_RING_IV_USED.ANY",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+        "UMask": "0xf",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 IV Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_R2_RING_IV_USED.CCW",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+        "UMask": "0xc",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "R2 IV Ring in Use; Any",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "R2 IV Ring in Use; Clockwise",
         "EventCode": "0xA",
-        "EventName": "UNC_R2_RING_IV_USED.ANY",
+        "EventName": "UNC_R2_RING_IV_USED.CW",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+        "UMask": "0x3",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "Ingress Cycles Not Empty; NCB",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R2_RxR_CYCLES_NE.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
         "UMask": "0x10",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "Ingress Cycles Not Empty; NCS",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R2_RxR_CYCLES_NE.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
         "UMask": "0x20",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "Ingress Allocations; NCB",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R2_RxR_INSERTS.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
         "UMask": "0x10",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "Ingress Allocations; NCS",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R2_RxR_INSERTS.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
         "UMask": "0x20",
         "Unit": "R2PCIe"
     },
@@ -778,60 +846,79 @@
         "EventCode": "0x13",
         "EventName": "UNC_R2_RxR_OCCUPANCY.DRS",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue",
         "UMask": "0x8",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "SBo0 Credits Acquired; For AD Ring",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
         "UMask": "0x1",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "SBo0 Credits Acquired; For BL Ring",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
         "UMask": "0x2",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
-        "Counter": "0,1",
-        "EventCode": "0x2C",
-        "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD",
+        "BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
+        "EventCode": "0x2A",
+        "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
         "UMask": "0x1",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
-        "Counter": "0,1",
-        "EventCode": "0x2C",
-        "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD",
+        "BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
+        "EventCode": "0x2A",
+        "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
         "UMask": "0x2",
         "Unit": "R2PCIe"
     },
+    {
+        "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
+        "EventCode": "0x2C",
+        "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+        "UMask": "0x1",
+        "Unit": "R2PCIe"
+    },
     {
         "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
-        "Counter": "0,1",
         "EventCode": "0x2C",
         "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
         "UMask": "0x4",
         "Unit": "R2PCIe"
     },
+    {
+        "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
+        "EventCode": "0x2C",
+        "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+        "UMask": "0x2",
+        "Unit": "R2PCIe"
+    },
     {
         "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
-        "Counter": "0,1",
         "EventCode": "0x2C",
         "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
         "UMask": "0x8",
         "Unit": "R2PCIe"
     },
@@ -840,6 +927,7 @@
         "EventCode": "0x25",
         "EventName": "UNC_R2_TxR_CYCLES_FULL.AD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AD Egress Queue",
         "UMask": "0x1",
         "Unit": "R2PCIe"
     },
@@ -848,6 +936,7 @@
         "EventCode": "0x25",
         "EventName": "UNC_R2_TxR_CYCLES_FULL.AK",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AK Egress Queue",
         "UMask": "0x2",
         "Unit": "R2PCIe"
     },
@@ -856,6 +945,7 @@
         "EventCode": "0x25",
         "EventName": "UNC_R2_TxR_CYCLES_FULL.BL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; BL Egress Queue",
         "UMask": "0x4",
         "Unit": "R2PCIe"
     },
@@ -864,6 +954,7 @@
         "EventCode": "0x23",
         "EventName": "UNC_R2_TxR_CYCLES_NE.AD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.; AD Egress Queue",
         "UMask": "0x1",
         "Unit": "R2PCIe"
     },
@@ -872,6 +963,7 @@
         "EventCode": "0x23",
         "EventName": "UNC_R2_TxR_CYCLES_NE.AK",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.; AK Egress Queue",
         "UMask": "0x2",
         "Unit": "R2PCIe"
     },
@@ -880,954 +972,925 @@
         "EventCode": "0x23",
         "EventName": "UNC_R2_TxR_CYCLES_NE.BL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.; BL Egress Queue",
         "UMask": "0x4",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "Egress CCW NACK; AD CCW",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R2_TxR_NACK_CW.DN_AD",
         "PerPkg": "1",
+        "PublicDescription": "AD CounterClockwise Egress Queue",
         "UMask": "0x1",
         "Unit": "R2PCIe"
     },
-    {
-        "BriefDescription": "Egress CCW NACK; BL CCW",
-        "Counter": "0,1",
-        "EventCode": "0x26",
-        "EventName": "UNC_R2_TxR_NACK_CW.DN_BL",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "R2PCIe"
-    },
     {
         "BriefDescription": "Egress CCW NACK; AK CCW",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R2_TxR_NACK_CW.DN_AK",
         "PerPkg": "1",
+        "PublicDescription": "AK CounterClockwise Egress Queue",
         "UMask": "0x4",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "Egress CCW NACK; AK CCW",
-        "Counter": "0,1",
+        "BriefDescription": "Egress CCW NACK; BL CCW",
         "EventCode": "0x26",
-        "EventName": "UNC_R2_TxR_NACK_CW.UP_AD",
+        "EventName": "UNC_R2_TxR_NACK_CW.DN_BL",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "BL CounterClockwise Egress Queue",
+        "UMask": "0x2",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "Egress CCW NACK; BL CCW",
-        "Counter": "0,1",
+        "BriefDescription": "Egress CCW NACK; AK CCW",
         "EventCode": "0x26",
-        "EventName": "UNC_R2_TxR_NACK_CW.UP_BL",
+        "EventName": "UNC_R2_TxR_NACK_CW.UP_AD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "BL CounterClockwise Egress Queue",
+        "UMask": "0x8",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "Egress CCW NACK; BL CW",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R2_TxR_NACK_CW.UP_AK",
         "PerPkg": "1",
+        "PublicDescription": "AD Clockwise Egress Queue",
         "UMask": "0x20",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "R2PCIe IIO Credit Acquired; DRS",
-        "Counter": "0,1",
-        "EventCode": "0x33",
-        "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
-        "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "R2PCIe"
-    },
-    {
-        "BriefDescription": "R2PCIe IIO Credit Acquired; NCB",
-        "Counter": "0,1",
-        "EventCode": "0x33",
-        "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "R2PCIe"
-    },
-    {
-        "BriefDescription": "R2PCIe IIO Credit Acquired; NCS",
-        "Counter": "0,1",
-        "EventCode": "0x33",
-        "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "R2PCIe"
-    },
-    {
-        "BriefDescription": "R2PCIe IIO Credits in Use; DRS",
-        "Counter": "0,1",
-        "EventCode": "0x32",
-        "EventName": "UNC_R2_IIO_CREDITS_USED.DRS",
-        "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "R2PCIe"
-    },
-    {
-        "BriefDescription": "R2PCIe IIO Credits in Use; NCB",
-        "Counter": "0,1",
-        "EventCode": "0x32",
-        "EventName": "UNC_R2_IIO_CREDITS_USED.NCB",
+        "BriefDescription": "Egress CCW NACK; BL CCW",
+        "EventCode": "0x26",
+        "EventName": "UNC_R2_TxR_NACK_CW.UP_BL",
         "PerPkg": "1",
+        "PublicDescription": "AD CounterClockwise Egress Queue",
         "UMask": "0x10",
         "Unit": "R2PCIe"
     },
-    {
-        "BriefDescription": "R2PCIe IIO Credits in Use; NCS",
-        "Counter": "0,1",
-        "EventCode": "0x32",
-        "EventName": "UNC_R2_IIO_CREDITS_USED.NCS",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "R2PCIe"
-    },
-    {
-        "BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
-        "EventCode": "0x2A",
-        "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.AD",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "R2PCIe"
-    },
-    {
-        "BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
-        "EventCode": "0x2A",
-        "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.BL",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "R2PCIe"
-    },
-    {
-        "BriefDescription": "R2 AD Ring in Use; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x7",
-        "EventName": "UNC_R2_RING_AD_USED.ALL",
-        "PerPkg": "1",
-        "UMask": "0xF",
-        "Unit": "R2PCIe"
-    },
-    {
-        "BriefDescription": "R2 AK Ring in Use; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8",
-        "EventName": "UNC_R2_RING_AK_USED.ALL",
-        "PerPkg": "1",
-        "UMask": "0xF",
-        "Unit": "R2PCIe"
-    },
-    {
-        "BriefDescription": "R2 BL Ring in Use; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9",
-        "EventName": "UNC_R2_RING_BL_USED.ALL",
-        "PerPkg": "1",
-        "UMask": "0xF",
-        "Unit": "R2PCIe"
-    },
     {
         "BriefDescription": "Number of uclks in domain",
-        "Counter": "0,1,2",
         "EventCode": "0x1",
         "EventName": "UNC_R3_CLOCKTICKS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of uclks in the QPI uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x1F",
-        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8",
+        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 10",
+        "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x1F",
-        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9",
+        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 11",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x1F",
-        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10",
+        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 12",
+        "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x1F",
-        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11",
+        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 13",
+        "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x1F",
-        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12",
+        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 14&16",
+        "UMask": "0x40",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x1F",
-        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13",
+        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 8",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x1F",
-        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16",
+        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 9",
+        "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x1F",
         "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO_15_17",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 15&17",
         "UMask": "0x80",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 0",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 1",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 2",
         "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 3",
         "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 4",
         "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 5",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 6",
         "UMask": "0x40",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 7",
         "UMask": "0x80",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "HA/R2 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2D",
         "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA0",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "HA/R2 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2D",
         "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA1",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "HA/R2 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2D",
         "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCB Messages",
         "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "HA/R2 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2D",
         "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCS Messages",
         "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "QPI0 AD Credits Empty",
-        "Counter": "0,1",
-        "EventCode": "0x20",
-        "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA",
+        "BriefDescription": "IOT Backpressure",
+        "EventCode": "0xB",
+        "EventName": "UNC_R3_IOT_BACKPRESSURE.HUB",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "UNC_R3_IOT_BACKPRESSURE.HUB",
+        "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "QPI0 AD Credits Empty",
-        "Counter": "0,1",
-        "EventCode": "0x20",
-        "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM",
+        "BriefDescription": "IOT Backpressure",
+        "EventCode": "0xB",
+        "EventName": "UNC_R3_IOT_BACKPRESSURE.SAT",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "UNC_R3_IOT_BACKPRESSURE.SAT",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "QPI0 AD Credits Empty",
-        "Counter": "0,1",
-        "EventCode": "0x20",
-        "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP",
+        "BriefDescription": "IOT Common Trigger Sequencer - Hi",
+        "EventCode": "0xD",
+        "EventName": "UNC_R3_IOT_CTS_HI.CTS2",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Debug Mask/Match Tie-Ins",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "QPI0 AD Credits Empty",
-        "Counter": "0,1",
-        "EventCode": "0x20",
-        "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR",
+        "BriefDescription": "IOT Common Trigger Sequencer - Hi",
+        "EventCode": "0xD",
+        "EventName": "UNC_R3_IOT_CTS_HI.CTS3",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Debug Mask/Match Tie-Ins",
+        "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "QPI0 AD Credits Empty",
-        "Counter": "0,1",
-        "EventCode": "0x20",
-        "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM",
+        "BriefDescription": "IOT Common Trigger Sequencer - Lo",
+        "EventCode": "0xC",
+        "EventName": "UNC_R3_IOT_CTS_LO.CTS0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Debug Mask/Match Tie-Ins",
+        "UMask": "0x1",
+        "Unit": "R3QPI"
+    },
+    {
+        "BriefDescription": "IOT Common Trigger Sequencer - Lo",
+        "EventCode": "0xC",
+        "EventName": "UNC_R3_IOT_CTS_LO.CTS1",
+        "PerPkg": "1",
+        "PublicDescription": "Debug Mask/Match Tie-Ins",
+        "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI0 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x20",
-        "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP",
+        "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 HOM Messages",
+        "UMask": "0x2",
+        "Unit": "R3QPI"
+    },
+    {
+        "BriefDescription": "QPI0 AD Credits Empty",
+        "EventCode": "0x20",
+        "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR",
+        "PerPkg": "1",
+        "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 NDR Messages",
+        "UMask": "0x8",
+        "Unit": "R3QPI"
+    },
+    {
+        "BriefDescription": "QPI0 AD Credits Empty",
+        "EventCode": "0x20",
+        "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP",
+        "PerPkg": "1",
+        "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 SNP Messages",
+        "UMask": "0x4",
+        "Unit": "R3QPI"
+    },
+    {
+        "BriefDescription": "QPI0 AD Credits Empty",
+        "EventCode": "0x20",
+        "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM",
+        "PerPkg": "1",
+        "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 HOM Messages",
+        "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI0 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x20",
         "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 NDR Messages",
         "UMask": "0x40",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "QPI0 BL Credits Empty",
-        "Counter": "0,1",
-        "EventCode": "0x21",
-        "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA",
+        "BriefDescription": "QPI0 AD Credits Empty",
+        "EventCode": "0x20",
+        "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP",
+        "PerPkg": "1",
+        "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 SNP Messages",
+        "UMask": "0x20",
+        "Unit": "R3QPI"
+    },
+    {
+        "BriefDescription": "QPI0 AD Credits Empty",
+        "EventCode": "0x20",
+        "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VNA",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI0 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x21",
         "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 HOM Messages",
         "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI0 BL Credits Empty",
-        "Counter": "0,1",
+        "EventCode": "0x21",
+        "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR",
+        "PerPkg": "1",
+        "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 NDR Messages",
+        "UMask": "0x40",
+        "Unit": "R3QPI"
+    },
+    {
+        "BriefDescription": "QPI0 BL Credits Empty",
         "EventCode": "0x21",
         "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 SNP Messages",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI0 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x21",
-        "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR",
+        "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VNA",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI1 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2E",
-        "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA",
+        "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 HOM Messages",
+        "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI1 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2E",
-        "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM",
+        "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 NDR Messages",
+        "UMask": "0x40",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI1 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 SNP Messages",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI1 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2E",
-        "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR",
+        "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VNA",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI1 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2F",
-        "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA",
+        "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 HOM Messages",
+        "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI1 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2F",
-        "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM",
+        "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 NDR Messages",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI1 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2F",
         "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 SNP Messages",
         "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI1 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2F",
-        "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR",
+        "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 HOM Messages",
+        "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI1 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2F",
-        "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM",
+        "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 NDR Messages",
+        "UMask": "0x40",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI1 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2F",
         "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 SNP Messages",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI1 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2F",
-        "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR",
+        "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VNA",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "R3 AD Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2",
+        "BriefDescription": "R3 AD Ring in Use; All",
         "EventCode": "0x7",
-        "EventName": "UNC_R3_RING_AD_USED.CW_EVEN",
+        "EventName": "UNC_R3_RING_AD_USED.ALL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xf",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2",
+        "BriefDescription": "R3 AD Ring in Use; Counterclockwise",
         "EventCode": "0x7",
-        "EventName": "UNC_R3_RING_AD_USED.CW_ODD",
+        "EventName": "UNC_R3_RING_AD_USED.CCW",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xc",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2",
         "EventCode": "0x7",
         "EventName": "UNC_R3_RING_AD_USED.CCW_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
         "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2",
         "EventCode": "0x7",
         "EventName": "UNC_R3_RING_AD_USED.CCW_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R3 AD Ring in Use; Clockwise",
-        "Counter": "0,1,2",
         "EventCode": "0x7",
         "EventName": "UNC_R3_RING_AD_USED.CW",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
         "UMask": "0x3",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "R3 AD Ring in Use; Counterclockwise",
-        "Counter": "0,1,2",
+        "BriefDescription": "R3 AD Ring in Use; Clockwise and Even",
         "EventCode": "0x7",
-        "EventName": "UNC_R3_RING_AD_USED.CCW",
+        "EventName": "UNC_R3_RING_AD_USED.CW_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "R3 AK Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2",
+        "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd",
+        "EventCode": "0x7",
+        "EventName": "UNC_R3_RING_AD_USED.CW_ODD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+        "UMask": "0x2",
+        "Unit": "R3QPI"
+    },
+    {
+        "BriefDescription": "R3 AK Ring in Use; All",
         "EventCode": "0x8",
-        "EventName": "UNC_R3_RING_AK_USED.CW_EVEN",
+        "EventName": "UNC_R3_RING_AK_USED.ALL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xf",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2",
+        "BriefDescription": "R3 AK Ring in Use; Counterclockwise",
         "EventCode": "0x8",
-        "EventName": "UNC_R3_RING_AK_USED.CW_ODD",
+        "EventName": "UNC_R3_RING_AK_USED.CCW",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xc",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2",
         "EventCode": "0x8",
         "EventName": "UNC_R3_RING_AK_USED.CCW_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
         "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2",
         "EventCode": "0x8",
         "EventName": "UNC_R3_RING_AK_USED.CCW_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R3 AK Ring in Use; Clockwise",
-        "Counter": "0,1,2",
         "EventCode": "0x8",
         "EventName": "UNC_R3_RING_AK_USED.CW",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
         "UMask": "0x3",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "R3 AK Ring in Use; Counterclockwise",
-        "Counter": "0,1,2",
+        "BriefDescription": "R3 AK Ring in Use; Clockwise and Even",
         "EventCode": "0x8",
-        "EventName": "UNC_R3_RING_AK_USED.CCW",
+        "EventName": "UNC_R3_RING_AK_USED.CW_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "R3 BL Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2",
+        "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd",
+        "EventCode": "0x8",
+        "EventName": "UNC_R3_RING_AK_USED.CW_ODD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+        "UMask": "0x2",
+        "Unit": "R3QPI"
+    },
+    {
+        "BriefDescription": "R3 BL Ring in Use; All",
         "EventCode": "0x9",
-        "EventName": "UNC_R3_RING_BL_USED.CW_EVEN",
+        "EventName": "UNC_R3_RING_BL_USED.ALL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xf",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2",
+        "BriefDescription": "R3 BL Ring in Use; Counterclockwise",
         "EventCode": "0x9",
-        "EventName": "UNC_R3_RING_BL_USED.CW_ODD",
+        "EventName": "UNC_R3_RING_BL_USED.CCW",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xc",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2",
         "EventCode": "0x9",
         "EventName": "UNC_R3_RING_BL_USED.CCW_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
         "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2",
         "EventCode": "0x9",
         "EventName": "UNC_R3_RING_BL_USED.CCW_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R3 BL Ring in Use; Clockwise",
-        "Counter": "0,1,2",
         "EventCode": "0x9",
         "EventName": "UNC_R3_RING_BL_USED.CW",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
         "UMask": "0x3",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "R3 BL Ring in Use; Counterclockwise",
-        "Counter": "0,1,2",
+        "BriefDescription": "R3 BL Ring in Use; Clockwise and Even",
         "EventCode": "0x9",
-        "EventName": "UNC_R3_RING_BL_USED.CCW",
+        "EventName": "UNC_R3_RING_BL_USED.CW_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "R3 IV Ring in Use; Clockwise",
-        "Counter": "0,1,2",
-        "EventCode": "0xA",
-        "EventName": "UNC_R3_RING_IV_USED.CW",
+        "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd",
+        "EventCode": "0x9",
+        "EventName": "UNC_R3_RING_BL_USED.CW_ODD",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+        "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R3 IV Ring in Use; Any",
-        "Counter": "0,1,2",
         "EventCode": "0xA",
         "EventName": "UNC_R3_RING_IV_USED.ANY",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+        "UMask": "0xf",
+        "Unit": "R3QPI"
+    },
+    {
+        "BriefDescription": "R3 IV Ring in Use; Clockwise",
+        "EventCode": "0xA",
+        "EventName": "UNC_R3_RING_IV_USED.CW",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+        "UMask": "0x3",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "Ring Stop Starved; AK",
-        "Counter": "0,1,2",
         "EventCode": "0xE",
         "EventName": "UNC_R3_RING_SINK_STARVED.AK",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the ringstop is in starvation (per ring)",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "Ingress Cycles Not Empty; HOM",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R3_RxR_CYCLES_NE.HOM",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
-    {
-        "BriefDescription": "Ingress Cycles Not Empty; SNP",
-        "Counter": "0,1",
-        "EventCode": "0x10",
-        "EventName": "UNC_R3_RxR_CYCLES_NE.SNP",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "R3QPI"
-    },
     {
         "BriefDescription": "Ingress Cycles Not Empty; NDR",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R3_RxR_CYCLES_NE.NDR",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
         "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Ingress Cycles Not Empty; HOM",
-        "Counter": "0,1",
-        "EventCode": "0x14",
-        "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.HOM",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "R3QPI"
-    },
-    {
-        "BriefDescription": "VN1 Ingress Cycles Not Empty; SNP",
-        "Counter": "0,1",
-        "EventCode": "0x14",
-        "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.SNP",
+        "BriefDescription": "Ingress Cycles Not Empty; SNP",
+        "EventCode": "0x10",
+        "EventName": "UNC_R3_RxR_CYCLES_NE.SNP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Ingress Cycles Not Empty; NDR",
-        "Counter": "0,1",
+        "BriefDescription": "VN1 Ingress Cycles Not Empty; DRS",
         "EventCode": "0x14",
-        "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NDR",
+        "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.DRS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Ingress Cycles Not Empty; DRS",
-        "Counter": "0,1",
+        "BriefDescription": "VN1 Ingress Cycles Not Empty; HOM",
         "EventCode": "0x14",
-        "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.DRS",
+        "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.HOM",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VN1 Ingress Cycles Not Empty; NCB",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
         "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VN1 Ingress Cycles Not Empty; NCS",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "Ingress Allocations; HOM",
-        "Counter": "0,1",
-        "EventCode": "0x11",
-        "EventName": "UNC_R3_RxR_INSERTS.HOM",
+        "BriefDescription": "VN1 Ingress Cycles Not Empty; NDR",
+        "EventCode": "0x14",
+        "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NDR",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+        "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "Ingress Allocations; SNP",
-        "Counter": "0,1",
-        "EventCode": "0x11",
-        "EventName": "UNC_R3_RxR_INSERTS.SNP",
+        "BriefDescription": "VN1 Ingress Cycles Not Empty; SNP",
+        "EventCode": "0x14",
+        "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.SNP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "Ingress Allocations; NDR",
-        "Counter": "0,1",
+        "BriefDescription": "Ingress Allocations; DRS",
         "EventCode": "0x11",
-        "EventName": "UNC_R3_RxR_INSERTS.NDR",
+        "EventName": "UNC_R3_RxR_INSERTS.DRS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "Ingress Allocations; DRS",
-        "Counter": "0,1",
+        "BriefDescription": "Ingress Allocations; HOM",
         "EventCode": "0x11",
-        "EventName": "UNC_R3_RxR_INSERTS.DRS",
+        "EventName": "UNC_R3_RxR_INSERTS.HOM",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "Ingress Allocations; NCB",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R3_RxR_INSERTS.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
         "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "Ingress Allocations; NCS",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R3_RxR_INSERTS.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Ingress Allocations; HOM",
-        "Counter": "0,1",
-        "EventCode": "0x15",
-        "EventName": "UNC_R3_RxR_INSERTS_VN1.HOM",
+        "BriefDescription": "Ingress Allocations; NDR",
+        "EventCode": "0x11",
+        "EventName": "UNC_R3_RxR_INSERTS.NDR",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+        "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Ingress Allocations; SNP",
-        "Counter": "0,1",
-        "EventCode": "0x15",
-        "EventName": "UNC_R3_RxR_INSERTS_VN1.SNP",
+        "BriefDescription": "Ingress Allocations; SNP",
+        "EventCode": "0x11",
+        "EventName": "UNC_R3_RxR_INSERTS.SNP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
-    {
-        "BriefDescription": "VN1 Ingress Allocations; NDR",
-        "Counter": "0,1",
-        "EventCode": "0x15",
-        "EventName": "UNC_R3_RxR_INSERTS_VN1.NDR",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "R3QPI"
-    },
     {
         "BriefDescription": "VN1 Ingress Allocations; DRS",
-        "Counter": "0,1",
         "EventCode": "0x15",
         "EventName": "UNC_R3_RxR_INSERTS_VN1.DRS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue",
         "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Ingress Allocations; NCB",
-        "Counter": "0,1",
+        "BriefDescription": "VN1 Ingress Allocations; HOM",
         "EventCode": "0x15",
-        "EventName": "UNC_R3_RxR_INSERTS_VN1.NCB",
+        "EventName": "UNC_R3_RxR_INSERTS_VN1.HOM",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
+        "UMask": "0x1",
+        "Unit": "R3QPI"
+    },
+    {
+        "BriefDescription": "VN1 Ingress Allocations; NCB",
+        "EventCode": "0x15",
+        "EventName": "UNC_R3_RxR_INSERTS_VN1.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
         "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VN1 Ingress Allocations; NCS",
-        "Counter": "0,1",
         "EventCode": "0x15",
         "EventName": "UNC_R3_RxR_INSERTS_VN1.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Ingress Occupancy Accumulator; HOM",
-        "EventCode": "0x13",
-        "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.HOM",
+        "BriefDescription": "VN1 Ingress Allocations; NDR",
+        "EventCode": "0x15",
+        "EventName": "UNC_R3_RxR_INSERTS_VN1.NDR",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+        "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Ingress Occupancy Accumulator; SNP",
-        "EventCode": "0x13",
-        "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.SNP",
+        "BriefDescription": "VN1 Ingress Allocations; SNP",
+        "EventCode": "0x15",
+        "EventName": "UNC_R3_RxR_INSERTS_VN1.SNP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Ingress Occupancy Accumulator; NDR",
+        "BriefDescription": "VN1 Ingress Occupancy Accumulator; DRS",
         "EventCode": "0x13",
-        "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NDR",
+        "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.DRS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Ingress Occupancy Accumulator; DRS",
+        "BriefDescription": "VN1 Ingress Occupancy Accumulator; HOM",
         "EventCode": "0x13",
-        "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.DRS",
+        "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.HOM",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; HOM Ingress Queue",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
@@ -1835,6 +1898,7 @@
         "EventCode": "0x13",
         "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; NCB Ingress Queue",
         "UMask": "0x10",
         "Unit": "R3QPI"
     },
@@ -1843,1410 +1907,1344 @@
         "EventCode": "0x13",
         "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; NCS Ingress Queue",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
+    {
+        "BriefDescription": "VN1 Ingress Occupancy Accumulator; NDR",
+        "EventCode": "0x13",
+        "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NDR",
+        "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; NDR Ingress Queue",
+        "UMask": "0x4",
+        "Unit": "R3QPI"
+    },
+    {
+        "BriefDescription": "VN1 Ingress Occupancy Accumulator; SNP",
+        "EventCode": "0x13",
+        "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.SNP",
+        "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; SNP Ingress Queue",
+        "UMask": "0x2",
+        "Unit": "R3QPI"
+    },
     {
         "BriefDescription": "SBo0 Credits Acquired; For AD Ring",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "SBo0 Credits Acquired; For BL Ring",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
+        "UMask": "0x2",
+        "Unit": "R3QPI"
+    },
+    {
+        "BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
+        "EventCode": "0x2A",
+        "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.AD",
+        "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
+        "UMask": "0x1",
+        "Unit": "R3QPI"
+    },
+    {
+        "BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
+        "EventCode": "0x2A",
+        "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.BL",
+        "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "SBo1 Credits Acquired; For AD Ring",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "SBo1 Credits Acquired; For BL Ring",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
-        "Counter": "0,1",
-        "EventCode": "0x2C",
-        "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_AD",
+        "BriefDescription": "SBo1 Credits Occupancy; For AD Ring",
+        "EventCode": "0x2B",
+        "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
-        "Counter": "0,1",
-        "EventCode": "0x2C",
-        "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD",
+        "BriefDescription": "SBo1 Credits Occupancy; For BL Ring",
+        "EventCode": "0x2B",
+        "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
+    {
+        "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
+        "EventCode": "0x2C",
+        "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_AD",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+        "UMask": "0x1",
+        "Unit": "R3QPI"
+    },
     {
         "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
-        "Counter": "0,1",
         "EventCode": "0x2C",
         "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
         "UMask": "0x4",
         "Unit": "R3QPI"
     },
+    {
+        "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
+        "EventCode": "0x2C",
+        "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+        "UMask": "0x2",
+        "Unit": "R3QPI"
+    },
     {
         "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
-        "Counter": "0,1",
         "EventCode": "0x2C",
         "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
         "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "Egress CCW NACK; AD CCW",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R3_TxR_NACK.DN_AD",
         "PerPkg": "1",
+        "PublicDescription": "AD CounterClockwise Egress Queue",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
-    {
-        "BriefDescription": "Egress CCW NACK; BL CCW",
-        "Counter": "0,1",
-        "EventCode": "0x26",
-        "EventName": "UNC_R3_TxR_NACK.DN_BL",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "R3QPI"
-    },
     {
         "BriefDescription": "Egress CCW NACK; AK CCW",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R3_TxR_NACK.DN_AK",
         "PerPkg": "1",
+        "PublicDescription": "AK CounterClockwise Egress Queue",
         "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "Egress CCW NACK; AK CCW",
-        "Counter": "0,1",
+        "BriefDescription": "Egress CCW NACK; BL CCW",
         "EventCode": "0x26",
-        "EventName": "UNC_R3_TxR_NACK.UP_AD",
+        "EventName": "UNC_R3_TxR_NACK.DN_BL",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "BL CounterClockwise Egress Queue",
+        "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "Egress CCW NACK; BL CCW",
-        "Counter": "0,1",
+        "BriefDescription": "Egress CCW NACK; AK CCW",
         "EventCode": "0x26",
-        "EventName": "UNC_R3_TxR_NACK.UP_BL",
+        "EventName": "UNC_R3_TxR_NACK.UP_AD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "BL CounterClockwise Egress Queue",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "Egress CCW NACK; BL CW",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R3_TxR_NACK.UP_AK",
         "PerPkg": "1",
+        "PublicDescription": "AD Clockwise Egress Queue",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class",
-        "Counter": "0,1",
-        "EventCode": "0x37",
-        "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "R3QPI"
-    },
-    {
-        "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class",
-        "Counter": "0,1",
-        "EventCode": "0x37",
-        "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP",
+        "BriefDescription": "Egress CCW NACK; BL CCW",
+        "EventCode": "0x26",
+        "EventName": "UNC_R3_TxR_NACK.UP_BL",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "AD CounterClockwise Egress Queue",
+        "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class",
         "EventCode": "0x37",
-        "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR",
+        "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class",
         "EventCode": "0x37",
-        "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS",
+        "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Message Class",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ?",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN0 Credit Used; HOM Message Class",
-        "Counter": "0,1",
-        "EventCode": "0x36",
-        "EventName": "UNC_R3_VN0_CREDITS_USED.HOM",
+        "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class",
+        "EventCode": "0x37",
+        "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN0 Credit Used; SNP Message Class",
-        "Counter": "0,1",
-        "EventCode": "0x36",
-        "EventName": "UNC_R3_VN0_CREDITS_USED.SNP",
+        "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class",
+        "EventCode": "0x37",
+        "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN0 Credit Used; NDR Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VN0 Credit Used; DRS Message Class",
         "EventCode": "0x36",
-        "EventName": "UNC_R3_VN0_CREDITS_USED.NDR",
+        "EventName": "UNC_R3_VN0_CREDITS_USED.DRS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN0 Credit Used; DRS Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VN0 Credit Used; HOM Message Class",
         "EventCode": "0x36",
-        "EventName": "UNC_R3_VN0_CREDITS_USED.DRS",
+        "EventName": "UNC_R3_VN0_CREDITS_USED.HOM",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VN0 Credit Used; NCB Message Class",
-        "Counter": "0,1",
         "EventCode": "0x36",
         "EventName": "UNC_R3_VN0_CREDITS_USED.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VN0 Credit Used; NCS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x36",
         "EventName": "UNC_R3_VN0_CREDITS_USED.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ?",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Message Class",
-        "Counter": "0,1",
-        "EventCode": "0x39",
-        "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM",
+        "BriefDescription": "VN0 Credit Used; NDR Message Class",
+        "EventCode": "0x36",
+        "EventName": "UNC_R3_VN0_CREDITS_USED.NDR",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Message Class",
-        "Counter": "0,1",
-        "EventCode": "0x39",
-        "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP",
+        "BriefDescription": "VN0 Credit Used; SNP Message Class",
+        "EventCode": "0x36",
+        "EventName": "UNC_R3_VN0_CREDITS_USED.SNP",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Message Class",
         "EventCode": "0x39",
-        "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR",
+        "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Message Class",
         "EventCode": "0x39",
-        "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS",
+        "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCB Message Class",
-        "Counter": "0,1",
         "EventCode": "0x39",
         "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x39",
         "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ?",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Credit Used; HOM Message Class",
-        "Counter": "0,1",
-        "EventCode": "0x38",
-        "EventName": "UNC_R3_VN1_CREDITS_USED.HOM",
+        "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Message Class",
+        "EventCode": "0x39",
+        "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Credit Used; SNP Message Class",
-        "Counter": "0,1",
-        "EventCode": "0x38",
-        "EventName": "UNC_R3_VN1_CREDITS_USED.SNP",
+        "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Message Class",
+        "EventCode": "0x39",
+        "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Credit Used; NDR Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VN1 Credit Used; DRS Message Class",
         "EventCode": "0x38",
-        "EventName": "UNC_R3_VN1_CREDITS_USED.NDR",
+        "EventName": "UNC_R3_VN1_CREDITS_USED.DRS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Credit Used; DRS Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VN1 Credit Used; HOM Message Class",
         "EventCode": "0x38",
-        "EventName": "UNC_R3_VN1_CREDITS_USED.DRS",
+        "EventName": "UNC_R3_VN1_CREDITS_USED.HOM",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VN1 Credit Used; NCB Message Class",
-        "Counter": "0,1",
         "EventCode": "0x38",
         "EventName": "UNC_R3_VN1_CREDITS_USED.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VN1 Credit Used; NCS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x38",
         "EventName": "UNC_R3_VN1_CREDITS_USED.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ?",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
+    {
+        "BriefDescription": "VN1 Credit Used; NDR Message Class",
+        "EventCode": "0x38",
+        "EventName": "UNC_R3_VN1_CREDITS_USED.NDR",
+        "PerPkg": "1",
+        "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
+        "Unit": "R3QPI"
+    },
+    {
+        "BriefDescription": "VN1 Credit Used; SNP Message Class",
+        "EventCode": "0x38",
+        "EventName": "UNC_R3_VN1_CREDITS_USED.SNP",
+        "PerPkg": "1",
+        "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.",
+        "UMask": "0x2",
+        "Unit": "R3QPI"
+    },
     {
         "BriefDescription": "VNA credit Acquisitions; HOM Message Class",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of QPI VNA Credit acquisitions.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder.  VNA credits are used by all message classes in order to communicate across QPI.  If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool.  Note that a single packet may require multiple flit buffers (i.e. when data is being transferred).  Therefore, this event will increment by the number of credits acquired in each cycle.  Filtering based on message class is not provided.  One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VNA credit Acquisitions; HOM Message Class",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of QPI VNA Credit acquisitions.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder.  VNA credits are used by all message classes in order to communicate across QPI.  If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool.  Note that a single packet may require multiple flit buffers (i.e. when data is being transferred).  Therefore, this event will increment by the number of credits acquired in each cycle.  Filtering based on message class is not provided.  One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
         "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VNA Credit Reject; HOM Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VNA Credit Reject; DRS Message Class",
         "EventCode": "0x34",
-        "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM",
+        "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VNA Credit Reject; SNP Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VNA Credit Reject; HOM Message Class",
         "EventCode": "0x34",
-        "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP",
+        "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VNA Credit Reject; NDR Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VNA Credit Reject; NCB Message Class",
         "EventCode": "0x34",
-        "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR",
+        "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "R3QPI"
-    },
-    {
-        "BriefDescription": "VNA Credit Reject; DRS Message Class",
-        "Counter": "0,1",
-        "EventCode": "0x34",
-        "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS",
-        "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "R3QPI"
-    },
-    {
-        "BriefDescription": "VNA Credit Reject; NCB Message Class",
-        "Counter": "0,1",
-        "EventCode": "0x34",
-        "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB",
-        "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VNA Credit Reject; NCS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Standard (NCS).",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "IOT Backpressure",
-        "Counter": "0,1,2",
-        "EventCode": "0xB",
-        "EventName": "UNC_R3_IOT_BACKPRESSURE.SAT",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "R3QPI"
-    },
-    {
-        "BriefDescription": "IOT Backpressure",
-        "Counter": "0,1,2",
-        "EventCode": "0xB",
-        "EventName": "UNC_R3_IOT_BACKPRESSURE.HUB",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "R3QPI"
-    },
-    {
-        "BriefDescription": "IOT Common Trigger Sequencer - Hi",
-        "Counter": "0,1,2",
-        "EventCode": "0xD",
-        "EventName": "UNC_R3_IOT_CTS_HI.CTS2",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "R3QPI"
-    },
-    {
-        "BriefDescription": "IOT Common Trigger Sequencer - Hi",
-        "Counter": "0,1,2",
-        "EventCode": "0xD",
-        "EventName": "UNC_R3_IOT_CTS_HI.CTS3",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "R3QPI"
-    },
-    {
-        "BriefDescription": "IOT Common Trigger Sequencer - Lo",
-        "Counter": "0,1,2",
-        "EventCode": "0xC",
-        "EventName": "UNC_R3_IOT_CTS_LO.CTS0",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "R3QPI"
-    },
-    {
-        "BriefDescription": "IOT Common Trigger Sequencer - Lo",
-        "Counter": "0,1,2",
-        "EventCode": "0xC",
-        "EventName": "UNC_R3_IOT_CTS_LO.CTS1",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "R3QPI"
-    },
-    {
-        "BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
-        "EventCode": "0x2A",
-        "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.AD",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "R3QPI"
-    },
-    {
-        "BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
-        "EventCode": "0x2A",
-        "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.BL",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "R3QPI"
-    },
-    {
-        "BriefDescription": "SBo1 Credits Occupancy; For AD Ring",
-        "EventCode": "0x2B",
-        "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.AD",
+        "BriefDescription": "VNA Credit Reject; NDR Message Class",
+        "EventCode": "0x34",
+        "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "SBo1 Credits Occupancy; For BL Ring",
-        "EventCode": "0x2B",
-        "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.BL",
+        "BriefDescription": "VNA Credit Reject; SNP Message Class",
+        "EventCode": "0x34",
+        "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP",
         "PerPkg": "1",
+        "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
-    {
-        "BriefDescription": "R3 AD Ring in Use; All",
-        "Counter": "0,1,2",
-        "EventCode": "0x7",
-        "EventName": "UNC_R3_RING_AD_USED.ALL",
-        "PerPkg": "1",
-        "UMask": "0xF",
-        "Unit": "R3QPI"
-    },
-    {
-        "BriefDescription": "R3 AK Ring in Use; All",
-        "Counter": "0,1,2",
-        "EventCode": "0x8",
-        "EventName": "UNC_R3_RING_AK_USED.ALL",
-        "PerPkg": "1",
-        "UMask": "0xF",
-        "Unit": "R3QPI"
-    },
-    {
-        "BriefDescription": "R3 BL Ring in Use; All",
-        "Counter": "0,1,2",
-        "EventCode": "0x9",
-        "EventName": "UNC_R3_RING_BL_USED.ALL",
-        "PerPkg": "1",
-        "UMask": "0xF",
-        "Unit": "R3QPI"
-    },
     {
         "BriefDescription": "Bounce Control",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_S_BOUNCE_CONTROL",
         "PerPkg": "1",
+        "PublicDescription": "UNC_S_BOUNCE_CONTROL",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Uncore Clocks",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_S_CLOCKTICKS",
         "PerPkg": "1",
+        "PublicDescription": "UNC_S_CLOCKTICKS",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "FaST wire asserted",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_S_FAST_ASSERTED",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "AD Ring In Use; Up and Even",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "AD Ring In Use; All",
         "EventCode": "0x1B",
-        "EventName": "UNC_S_RING_AD_USED.UP_EVEN",
+        "EventName": "UNC_S_RING_AD_USED.ALL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0xf",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "AD Ring In Use; Up and Odd",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "AD Ring In Use; Down",
         "EventCode": "0x1B",
-        "EventName": "UNC_S_RING_AD_USED.UP_ODD",
+        "EventName": "UNC_S_RING_AD_USED.DOWN",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0xc",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "AD Ring In Use; Down and Event",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_S_RING_AD_USED.DOWN_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.",
         "UMask": "0x4",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "AD Ring In Use; Down and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_S_RING_AD_USED.DOWN_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "AD Ring In Use; Up",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_S_RING_AD_USED.UP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
         "UMask": "0x3",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "AD Ring In Use; Down",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "AD Ring In Use; Up and Even",
         "EventCode": "0x1B",
-        "EventName": "UNC_S_RING_AD_USED.DOWN",
+        "EventName": "UNC_S_RING_AD_USED.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "AK Ring In Use; Up and Even",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "AD Ring In Use; Up and Odd",
+        "EventCode": "0x1B",
+        "EventName": "UNC_S_RING_AD_USED.UP_ODD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+        "UMask": "0x2",
+        "Unit": "SBO"
+    },
+    {
+        "BriefDescription": "AK Ring In Use; All",
         "EventCode": "0x1C",
-        "EventName": "UNC_S_RING_AK_USED.UP_EVEN",
+        "EventName": "UNC_S_RING_AK_USED.ALL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0xf",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "AK Ring In Use; Up and Odd",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "AK Ring In Use; Down",
         "EventCode": "0x1C",
-        "EventName": "UNC_S_RING_AK_USED.UP_ODD",
+        "EventName": "UNC_S_RING_AK_USED.DOWN",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0xc",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "AK Ring In Use; Down and Event",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_S_RING_AK_USED.DOWN_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.",
         "UMask": "0x4",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "AK Ring In Use; Down and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_S_RING_AK_USED.DOWN_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "AK Ring In Use; Up",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_S_RING_AK_USED.UP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
         "UMask": "0x3",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "AK Ring In Use; Down",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "AK Ring In Use; Up and Even",
         "EventCode": "0x1C",
-        "EventName": "UNC_S_RING_AK_USED.DOWN",
+        "EventName": "UNC_S_RING_AK_USED.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "BL Ring in Use; Up and Even",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "AK Ring In Use; Up and Odd",
+        "EventCode": "0x1C",
+        "EventName": "UNC_S_RING_AK_USED.UP_ODD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+        "UMask": "0x2",
+        "Unit": "SBO"
+    },
+    {
+        "BriefDescription": "BL Ring in Use; All",
         "EventCode": "0x1D",
-        "EventName": "UNC_S_RING_BL_USED.UP_EVEN",
+        "EventName": "UNC_S_RING_BL_USED.ALL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0xf",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "BL Ring in Use; Up and Odd",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "BL Ring in Use; Down",
         "EventCode": "0x1D",
-        "EventName": "UNC_S_RING_BL_USED.UP_ODD",
+        "EventName": "UNC_S_RING_BL_USED.DOWN",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0xc",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Down and Event",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_S_RING_BL_USED.DOWN_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.",
         "UMask": "0x4",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Down and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_S_RING_BL_USED.DOWN_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Up",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_S_RING_BL_USED.UP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
         "UMask": "0x3",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "BL Ring in Use; Down",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "BL Ring in Use; Up and Even",
         "EventCode": "0x1D",
-        "EventName": "UNC_S_RING_BL_USED.DOWN",
+        "EventName": "UNC_S_RING_BL_USED.UP_EVEN",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+        "UMask": "0x1",
+        "Unit": "SBO"
+    },
+    {
+        "BriefDescription": "BL Ring in Use; Up and Odd",
+        "EventCode": "0x1D",
+        "EventName": "UNC_S_RING_BL_USED.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+        "UMask": "0x2",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Number of LLC responses that bounced on the Ring",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Number of LLC responses that bounced on the Ring.",
         "EventCode": "0x5",
         "EventName": "UNC_S_RING_BOUNCES.AD_CACHE",
         "PerPkg": "1",
+        "PublicDescription": "UNC_S_RING_BOUNCES.AD_CACHE",
         "UMask": "0x1",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.; Acknowledgements to core",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_S_RING_BOUNCES.AK_CORE",
         "PerPkg": "1",
+        "PublicDescription": "UNC_S_RING_BOUNCES.AK_CORE",
         "UMask": "0x2",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.; Data Responses to core",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_S_RING_BOUNCES.BL_CORE",
         "PerPkg": "1",
+        "PublicDescription": "UNC_S_RING_BOUNCES.BL_CORE",
         "UMask": "0x4",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
         "EventCode": "0x5",
         "EventName": "UNC_S_RING_BOUNCES.IV_CORE",
         "PerPkg": "1",
+        "PublicDescription": "UNC_S_RING_BOUNCES.IV_CORE",
         "UMask": "0x8",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Any",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
-        "EventName": "UNC_S_RING_IV_USED.UP",
+        "EventName": "UNC_S_RING_IV_USED.DN",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  There is only 1 IV ring in HSX.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+        "UMask": "0xc",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Any",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
-        "EventName": "UNC_S_RING_IV_USED.DN",
+        "EventName": "UNC_S_RING_IV_USED.UP",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  There is only 1 IV ring in HSX.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+        "UMask": "0x3",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Bypass; AD - Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_S_RxR_BYPASS.AD_CRD",
+        "BriefDescription": "UNC_S_RING_SINK_STARVED.AD_CACHE",
+        "EventCode": "0x6",
+        "EventName": "UNC_S_RING_SINK_STARVED.AD_CACHE",
         "PerPkg": "1",
         "UMask": "0x1",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Bypass; AD - Bounces",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_S_RxR_BYPASS.AD_BNC",
+        "BriefDescription": "UNC_S_RING_SINK_STARVED.AK_CORE",
+        "EventCode": "0x6",
+        "EventName": "UNC_S_RING_SINK_STARVED.AK_CORE",
         "PerPkg": "1",
         "UMask": "0x2",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Bypass; BL - Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_S_RxR_BYPASS.BL_CRD",
+        "BriefDescription": "UNC_S_RING_SINK_STARVED.BL_CORE",
+        "EventCode": "0x6",
+        "EventName": "UNC_S_RING_SINK_STARVED.BL_CORE",
         "PerPkg": "1",
         "UMask": "0x4",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Bypass; BL - Bounces",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_S_RxR_BYPASS.BL_BNC",
+        "BriefDescription": "UNC_S_RING_SINK_STARVED.IV_CORE",
+        "EventCode": "0x6",
+        "EventName": "UNC_S_RING_SINK_STARVED.IV_CORE",
         "PerPkg": "1",
         "UMask": "0x8",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Bypass; AK",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_S_RxR_BYPASS.AK",
+        "BriefDescription": "Injection Starvation; AD - Bounces",
+        "EventCode": "0x15",
+        "EventName": "UNC_S_RxR_BUSY_STARVED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is  being sent.",
+        "UMask": "0x2",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Bypass; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_S_RxR_BYPASS.IV",
+        "BriefDescription": "Injection Starvation; AD - Credits",
+        "EventCode": "0x15",
+        "EventName": "UNC_S_RxR_BUSY_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is  being sent.",
+        "UMask": "0x1",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Ingress Allocations; AD - Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_S_RxR_INSERTS.AD_CRD",
+        "BriefDescription": "Injection Starvation; BL - Bounces",
+        "EventCode": "0x15",
+        "EventName": "UNC_S_RxR_BUSY_STARVED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is  being sent.",
+        "UMask": "0x8",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Ingress Allocations; AD - Bounces",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_S_RxR_INSERTS.AD_BNC",
+        "BriefDescription": "Injection Starvation; BL - Credits",
+        "EventCode": "0x15",
+        "EventName": "UNC_S_RxR_BUSY_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is  being sent.",
+        "UMask": "0x4",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Ingress Allocations; BL - Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_S_RxR_INSERTS.BL_CRD",
+        "BriefDescription": "Bypass; AD - Bounces",
+        "EventCode": "0x12",
+        "EventName": "UNC_S_RxR_BYPASS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Bypass the Sbo Ingress.",
+        "UMask": "0x2",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Ingress Allocations; BL - Bounces",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_S_RxR_INSERTS.BL_BNC",
+        "BriefDescription": "Bypass; AD - Credits",
+        "EventCode": "0x12",
+        "EventName": "UNC_S_RxR_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Bypass the Sbo Ingress.",
+        "UMask": "0x1",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Ingress Allocations; AK",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_S_RxR_INSERTS.AK",
+        "BriefDescription": "Bypass; AK",
+        "EventCode": "0x12",
+        "EventName": "UNC_S_RxR_BYPASS.AK",
         "PerPkg": "1",
+        "PublicDescription": "Bypass the Sbo Ingress.",
         "UMask": "0x10",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Ingress Allocations; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_S_RxR_INSERTS.IV",
+        "BriefDescription": "Bypass; BL - Bounces",
+        "EventCode": "0x12",
+        "EventName": "UNC_S_RxR_BYPASS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Bypass the Sbo Ingress.",
+        "UMask": "0x8",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Ingress Occupancy; AD - Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x11",
-        "EventName": "UNC_S_RxR_OCCUPANCY.AD_CRD",
+        "BriefDescription": "Bypass; BL - Credits",
+        "EventCode": "0x12",
+        "EventName": "UNC_S_RxR_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Bypass the Sbo Ingress.",
+        "UMask": "0x4",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Ingress Occupancy; AD - Bounces",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x11",
-        "EventName": "UNC_S_RxR_OCCUPANCY.AD_BNC",
+        "BriefDescription": "Bypass; IV",
+        "EventCode": "0x12",
+        "EventName": "UNC_S_RxR_BYPASS.IV",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Bypass the Sbo Ingress.",
+        "UMask": "0x20",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Ingress Occupancy; BL - Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x11",
-        "EventName": "UNC_S_RxR_OCCUPANCY.BL_CRD",
+        "BriefDescription": "Injection Starvation; AD - Bounces",
+        "EventCode": "0x14",
+        "EventName": "UNC_S_RxR_CRD_STARVED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+        "UMask": "0x2",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Ingress Occupancy; BL - Bounces",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x11",
-        "EventName": "UNC_S_RxR_OCCUPANCY.BL_BNC",
+        "BriefDescription": "Injection Starvation; AD - Credits",
+        "EventCode": "0x14",
+        "EventName": "UNC_S_RxR_CRD_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+        "UMask": "0x1",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Ingress Occupancy; AK",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x11",
-        "EventName": "UNC_S_RxR_OCCUPANCY.AK",
+        "BriefDescription": "Injection Starvation; AK",
+        "EventCode": "0x14",
+        "EventName": "UNC_S_RxR_CRD_STARVED.AK",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit.",
         "UMask": "0x10",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Ingress Occupancy; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x11",
-        "EventName": "UNC_S_RxR_OCCUPANCY.IV",
+        "BriefDescription": "Injection Starvation; BL - Bounces",
+        "EventCode": "0x14",
+        "EventName": "UNC_S_RxR_CRD_STARVED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+        "UMask": "0x8",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "UNC_S_TxR_ADS_USED.AD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_S_TxR_ADS_USED.AD",
+        "BriefDescription": "Injection Starvation; BL - Credits",
+        "EventCode": "0x14",
+        "EventName": "UNC_S_RxR_CRD_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+        "UMask": "0x4",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "UNC_S_TxR_ADS_USED.AK",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_S_TxR_ADS_USED.AK",
+        "BriefDescription": "Injection Starvation; IVF Credit",
+        "EventCode": "0x14",
+        "EventName": "UNC_S_RxR_CRD_STARVED.IFV",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+        "UMask": "0x40",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "UNC_S_TxR_ADS_USED.BL",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_S_TxR_ADS_USED.BL",
+        "BriefDescription": "Injection Starvation; IV",
+        "EventCode": "0x14",
+        "EventName": "UNC_S_RxR_CRD_STARVED.IV",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+        "UMask": "0x20",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Egress Allocations; AD - Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_S_TxR_INSERTS.AD_CRD",
+        "BriefDescription": "Ingress Allocations; AD - Bounces",
+        "EventCode": "0x13",
+        "EventName": "UNC_S_RxR_INSERTS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring.",
+        "UMask": "0x2",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Egress Allocations; AD - Bounces",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_S_TxR_INSERTS.AD_BNC",
+        "BriefDescription": "Ingress Allocations; AD - Credits",
+        "EventCode": "0x13",
+        "EventName": "UNC_S_RxR_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring.",
+        "UMask": "0x1",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Egress Allocations; BL - Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_S_TxR_INSERTS.BL_CRD",
+        "BriefDescription": "Ingress Allocations; AK",
+        "EventCode": "0x13",
+        "EventName": "UNC_S_RxR_INSERTS.AK",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring.",
+        "UMask": "0x10",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Egress Allocations; BL - Bounces",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_S_TxR_INSERTS.BL_BNC",
+        "BriefDescription": "Ingress Allocations; BL - Bounces",
+        "EventCode": "0x13",
+        "EventName": "UNC_S_RxR_INSERTS.BL_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring.",
         "UMask": "0x8",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Egress Allocations; AK",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_S_TxR_INSERTS.AK",
+        "BriefDescription": "Ingress Allocations; BL - Credits",
+        "EventCode": "0x13",
+        "EventName": "UNC_S_RxR_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring.",
+        "UMask": "0x4",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Egress Allocations; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_S_TxR_INSERTS.IV",
+        "BriefDescription": "Ingress Allocations; IV",
+        "EventCode": "0x13",
+        "EventName": "UNC_S_RxR_INSERTS.IV",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring.",
         "UMask": "0x20",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Egress Occupancy; AD - Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_S_TxR_OCCUPANCY.AD_CRD",
+        "BriefDescription": "Ingress Occupancy; AD - Bounces",
+        "EventCode": "0x11",
+        "EventName": "UNC_S_RxR_OCCUPANCY.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring.",
+        "UMask": "0x2",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Egress Occupancy; AD - Bounces",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_S_TxR_OCCUPANCY.AD_BNC",
+        "BriefDescription": "Ingress Occupancy; AD - Credits",
+        "EventCode": "0x11",
+        "EventName": "UNC_S_RxR_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring.",
+        "UMask": "0x1",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Egress Occupancy; BL - Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_S_TxR_OCCUPANCY.BL_CRD",
+        "BriefDescription": "Ingress Occupancy; AK",
+        "EventCode": "0x11",
+        "EventName": "UNC_S_RxR_OCCUPANCY.AK",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring.",
+        "UMask": "0x10",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Egress Occupancy; BL - Bounces",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_S_TxR_OCCUPANCY.BL_BNC",
+        "BriefDescription": "Ingress Occupancy; BL - Bounces",
+        "EventCode": "0x11",
+        "EventName": "UNC_S_RxR_OCCUPANCY.BL_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring.",
         "UMask": "0x8",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Egress Occupancy; AK",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_S_TxR_OCCUPANCY.AK",
+        "BriefDescription": "Ingress Occupancy; BL - Credits",
+        "EventCode": "0x11",
+        "EventName": "UNC_S_RxR_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring.",
+        "UMask": "0x4",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Egress Occupancy; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_S_TxR_OCCUPANCY.IV",
+        "BriefDescription": "Ingress Occupancy; IV",
+        "EventCode": "0x11",
+        "EventName": "UNC_S_RxR_OCCUPANCY.IV",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring.",
         "UMask": "0x20",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "UNC_S_RING_SINK_STARVED.AD_CACHE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6",
-        "EventName": "UNC_S_RING_SINK_STARVED.AD_CACHE",
+        "BriefDescription": "UNC_S_TxR_ADS_USED.AD",
+        "EventCode": "0x4",
+        "EventName": "UNC_S_TxR_ADS_USED.AD",
         "PerPkg": "1",
         "UMask": "0x1",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "UNC_S_RING_SINK_STARVED.AK_CORE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6",
-        "EventName": "UNC_S_RING_SINK_STARVED.AK_CORE",
+        "BriefDescription": "UNC_S_TxR_ADS_USED.AK",
+        "EventCode": "0x4",
+        "EventName": "UNC_S_TxR_ADS_USED.AK",
         "PerPkg": "1",
         "UMask": "0x2",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "UNC_S_RING_SINK_STARVED.BL_CORE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6",
-        "EventName": "UNC_S_RING_SINK_STARVED.BL_CORE",
+        "BriefDescription": "UNC_S_TxR_ADS_USED.BL",
+        "EventCode": "0x4",
+        "EventName": "UNC_S_TxR_ADS_USED.BL",
         "PerPkg": "1",
         "UMask": "0x4",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "UNC_S_RING_SINK_STARVED.IV_CORE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6",
-        "EventName": "UNC_S_RING_SINK_STARVED.IV_CORE",
+        "BriefDescription": "Egress Allocations; AD - Bounces",
+        "EventCode": "0x2",
+        "EventName": "UNC_S_TxR_INSERTS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring.",
+        "UMask": "0x2",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Injection Starvation; AD - Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_S_RxR_BUSY_STARVED.AD_CRD",
+        "BriefDescription": "Egress Allocations; AD - Credits",
+        "EventCode": "0x2",
+        "EventName": "UNC_S_TxR_INSERTS.AD_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring.",
         "UMask": "0x1",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Injection Starvation; AD - Bounces",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_S_RxR_BUSY_STARVED.AD_BNC",
+        "BriefDescription": "Egress Allocations; AK",
+        "EventCode": "0x2",
+        "EventName": "UNC_S_TxR_INSERTS.AK",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring.",
+        "UMask": "0x10",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Injection Starvation; BL - Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_S_RxR_BUSY_STARVED.BL_CRD",
+        "BriefDescription": "Egress Allocations; BL - Bounces",
+        "EventCode": "0x2",
+        "EventName": "UNC_S_TxR_INSERTS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring.",
+        "UMask": "0x8",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Injection Starvation; BL - Bounces",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_S_RxR_BUSY_STARVED.BL_BNC",
+        "BriefDescription": "Egress Allocations; BL - Credits",
+        "EventCode": "0x2",
+        "EventName": "UNC_S_TxR_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring.",
+        "UMask": "0x4",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Injection Starvation; AD - Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_S_RxR_CRD_STARVED.AD_CRD",
+        "BriefDescription": "Egress Allocations; IV",
+        "EventCode": "0x2",
+        "EventName": "UNC_S_TxR_INSERTS.IV",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring.",
+        "UMask": "0x20",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Injection Starvation; AD - Bounces",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_S_RxR_CRD_STARVED.AD_BNC",
+        "BriefDescription": "Egress Occupancy; AD - Bounces",
+        "EventCode": "0x1",
+        "EventName": "UNC_S_TxR_OCCUPANCY.AD_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring.",
         "UMask": "0x2",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Injection Starvation; BL - Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_S_RxR_CRD_STARVED.BL_CRD",
+        "BriefDescription": "Egress Occupancy; AD - Credits",
+        "EventCode": "0x1",
+        "EventName": "UNC_S_TxR_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring.",
+        "UMask": "0x1",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Injection Starvation; BL - Bounces",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_S_RxR_CRD_STARVED.BL_BNC",
+        "BriefDescription": "Egress Occupancy; AK",
+        "EventCode": "0x1",
+        "EventName": "UNC_S_TxR_OCCUPANCY.AK",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring.",
+        "UMask": "0x10",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Injection Starvation; AK",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_S_RxR_CRD_STARVED.AK",
+        "BriefDescription": "Egress Occupancy; BL - Bounces",
+        "EventCode": "0x1",
+        "EventName": "UNC_S_TxR_OCCUPANCY.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring.",
+        "UMask": "0x8",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Injection Starvation; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_S_RxR_CRD_STARVED.IV",
+        "BriefDescription": "Egress Occupancy; BL - Credits",
+        "EventCode": "0x1",
+        "EventName": "UNC_S_TxR_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring.",
+        "UMask": "0x4",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Injection Starvation; IVF Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_S_RxR_CRD_STARVED.IFV",
+        "BriefDescription": "Egress Occupancy; IV",
+        "EventCode": "0x1",
+        "EventName": "UNC_S_TxR_OCCUPANCY.IV",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring.",
+        "UMask": "0x20",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Injection Starvation; Onto AD Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_S_TxR_STARVED.AD",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
         "UMask": "0x1",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Injection Starvation; Onto AK Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_S_TxR_STARVED.AK",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
         "UMask": "0x2",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Injection Starvation; Onto BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_S_TxR_STARVED.BL",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
         "UMask": "0x4",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Injection Starvation; Onto IV Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_S_TxR_STARVED.IV",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
         "UMask": "0x8",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "AD Ring In Use; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1B",
-        "EventName": "UNC_S_RING_AD_USED.ALL",
-        "PerPkg": "1",
-        "UMask": "0xF",
-        "Unit": "SBO"
-    },
-    {
-        "BriefDescription": "AK Ring In Use; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1C",
-        "EventName": "UNC_S_RING_AK_USED.ALL",
-        "PerPkg": "1",
-        "UMask": "0xF",
-        "Unit": "SBO"
-    },
-    {
-        "BriefDescription": "BL Ring in Use; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1D",
-        "EventName": "UNC_S_RING_BL_USED.ALL",
+        "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
+        "EventCode": "0xff",
+        "EventName": "UNC_U_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0xF",
-        "Unit": "SBO"
+        "Unit": "UBOX"
     },
     {
         "BriefDescription": "VLW Received",
-        "Counter": "0,1",
         "EventCode": "0x42",
         "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
         "PerPkg": "1",
+        "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
         "UMask": "0x8",
         "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
-        "Counter": "0,1",
-        "EventCode": "0x45",
-        "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "UBOX"
-    },
-    {
-        "BriefDescription": "RACU Request",
-        "Counter": "0,1",
-        "EventCode": "0x46",
-        "EventName": "UNC_U_RACU_REQUESTS",
+        "BriefDescription": "Filter Match",
+        "EventCode": "0x41",
+        "EventName": "UNC_U_FILTER_MATCH.DISABLE",
         "PerPkg": "1",
+        "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+        "UMask": "0x2",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "Filter Match",
-        "Counter": "0,1",
         "EventCode": "0x41",
         "EventName": "UNC_U_FILTER_MATCH.ENABLE",
         "PerPkg": "1",
+        "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
         "UMask": "0x1",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "Filter Match",
-        "Counter": "0,1",
         "EventCode": "0x41",
-        "EventName": "UNC_U_FILTER_MATCH.DISABLE",
+        "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+        "UMask": "0x8",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "Filter Match",
-        "Counter": "0,1",
         "EventCode": "0x41",
         "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE",
         "PerPkg": "1",
+        "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
         "UMask": "0x4",
         "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Filter Match",
-        "Counter": "0,1",
-        "EventCode": "0x41",
-        "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
+        "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
+        "EventCode": "0x45",
+        "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "PHOLD cycles.  Filter from source CoreID.",
+        "UMask": "0x1",
         "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Monitor Sent to T0; Monitor T0",
-        "Counter": "0,1",
-        "EventCode": "0x43",
-        "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
+        "BriefDescription": "RACU Request",
+        "EventCode": "0x46",
+        "EventName": "UNC_U_RACU_REQUESTS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Number outstanding register requests within message channel tracker",
         "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Monitor Sent to T0; Monitor T1",
-        "Counter": "0,1",
+        "BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
         "EventCode": "0x43",
-        "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
+        "EventName": "UNC_U_U2C_EVENTS.CMC",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+        "UMask": "0x10",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "Monitor Sent to T0; Livelock",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.LIVELOCK",
         "PerPkg": "1",
+        "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
         "UMask": "0x4",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "Monitor Sent to T0; LTError",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.LTERROR",
         "PerPkg": "1",
+        "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
         "UMask": "0x8",
         "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
-        "Counter": "0,1",
+        "BriefDescription": "Monitor Sent to T0; Monitor T0",
         "EventCode": "0x43",
-        "EventName": "UNC_U_U2C_EVENTS.CMC",
+        "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
+        "UMask": "0x1",
         "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
-        "Counter": "0,1",
+        "BriefDescription": "Monitor Sent to T0; Monitor T1",
         "EventCode": "0x43",
-        "EventName": "UNC_U_U2C_EVENTS.UMC",
+        "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
+        "UMask": "0x2",
         "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Monitor Sent to T0; Trap",
-        "Counter": "0,1",
+        "BriefDescription": "Monitor Sent to T0; Other",
         "EventCode": "0x43",
-        "EventName": "UNC_U_U2C_EVENTS.TRAP",
+        "EventName": "UNC_U_U2C_EVENTS.OTHER",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Events coming from Uncore can be sent to one or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI",
+        "UMask": "0x80",
         "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Monitor Sent to T0; Other",
-        "Counter": "0,1",
+        "BriefDescription": "Monitor Sent to T0; Trap",
         "EventCode": "0x43",
-        "EventName": "UNC_U_U2C_EVENTS.OTHER",
+        "EventName": "UNC_U_U2C_EVENTS.TRAP",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+        "UMask": "0x40",
         "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
-        "Counter": "FIXED",
-        "EventCode": "0xff",
-        "EventName": "UNC_U_CLOCKTICKS",
+        "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
+        "EventCode": "0x43",
+        "EventName": "UNC_U_U2C_EVENTS.UMC",
         "PerPkg": "1",
+        "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+        "UMask": "0x20",
         "Unit": "UBOX"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json
index 3ffb70ff573df..e682eedf644a4 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json
@@ -1,457 +1,457 @@
 [
     {
         "BriefDescription": "pclk Cycles",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_P_CLOCKTICKS",
         "PerPkg": "1",
+        "PublicDescription": "The PCU runs off a fixed 1 GHz clock.  This event counts the number of pclk cycles measured while the counter was enabled.  The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_P_CORE0_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6A",
         "EventName": "UNC_P_CORE10_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6B",
         "EventName": "UNC_P_CORE11_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6C",
         "EventName": "UNC_P_CORE12_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6D",
         "EventName": "UNC_P_CORE13_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6E",
         "EventName": "UNC_P_CORE14_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6F",
         "EventName": "UNC_P_CORE15_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x70",
         "EventName": "UNC_P_CORE16_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "UNC_P_CORE17_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x61",
         "EventName": "UNC_P_CORE1_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x62",
         "EventName": "UNC_P_CORE2_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x63",
         "EventName": "UNC_P_CORE3_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x64",
         "EventName": "UNC_P_CORE4_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x65",
         "EventName": "UNC_P_CORE5_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x66",
         "EventName": "UNC_P_CORE6_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x67",
         "EventName": "UNC_P_CORE7_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x68",
         "EventName": "UNC_P_CORE8_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x69",
         "EventName": "UNC_P_CORE9_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x30",
         "EventName": "UNC_P_DEMOTIONS_CORE0",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_P_DEMOTIONS_CORE1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3A",
         "EventName": "UNC_P_DEMOTIONS_CORE10",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3B",
         "EventName": "UNC_P_DEMOTIONS_CORE11",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "UNC_P_DEMOTIONS_CORE12",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3D",
         "EventName": "UNC_P_DEMOTIONS_CORE13",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3E",
         "EventName": "UNC_P_DEMOTIONS_CORE14",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3F",
         "EventName": "UNC_P_DEMOTIONS_CORE15",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_P_DEMOTIONS_CORE16",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_P_DEMOTIONS_CORE17",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_P_DEMOTIONS_CORE2",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_P_DEMOTIONS_CORE3",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "UNC_P_DEMOTIONS_CORE4",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_P_DEMOTIONS_CORE5",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x36",
         "EventName": "UNC_P_DEMOTIONS_CORE6",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x37",
         "EventName": "UNC_P_DEMOTIONS_CORE7",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x38",
         "EventName": "UNC_P_DEMOTIONS_CORE8",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_P_DEMOTIONS_CORE9",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Thermal Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when thermal conditions are the upper limit on frequency.  This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature.  This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "OS Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_P_FREQ_MAX_OS_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the OS is the upper limit on frequency.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Power Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when power is the upper limit on frequency.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x73",
         "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower.  This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW.  This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Cycles spent changing Frequency",
-        "Counter": "0,1,2,3",
         "EventCode": "0x74",
         "EventName": "UNC_P_FREQ_TRANS_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the system is changing frequency.  This can not be filtered by thread ID.  One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Memory Phase Shedding Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2F",
         "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the PCU has triggered memory phase shedding.  This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "Number of cores in C-State; C0 and C1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
+        "BriefDescription": "Package C State Residency - C0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the package was in C0.  This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "Number of cores in C-State; C3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
+        "BriefDescription": "Package C State Residency - C1E",
+        "EventCode": "0x4E",
+        "EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the package was in C1E.  This event can be used in conjunction with edge detect to count C1E entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "Number of cores in C-State; C6 and C7",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
+        "BriefDescription": "Package C State Residency - C2E",
+        "EventCode": "0x2B",
+        "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the package was in C2E.  This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "External Prochot",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA",
-        "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
+        "BriefDescription": "Package C State Residency - C3",
+        "EventCode": "0x2C",
+        "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the package was in C3.  This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "Internal Prochot",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9",
-        "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
+        "BriefDescription": "Package C State Residency - C6",
+        "EventCode": "0x2D",
+        "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the package was in C6.  This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "Total Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x72",
-        "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
+        "BriefDescription": "Package C7 State Residency",
+        "EventCode": "0x2E",
+        "EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the package was in C7.  This event can be used in conjunction with edge detect to count C7 entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "UNC_P_UFS_TRANSITIONS_RING_GV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x79",
-        "EventName": "UNC_P_UFS_TRANSITIONS_RING_GV",
+        "BriefDescription": "Number of cores in C-State; C0 and C1",
+        "EventCode": "0x80",
+        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
         "PerPkg": "1",
+        "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "VR Hot",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x42",
-        "EventName": "UNC_P_VR_HOT_CYCLES",
+        "BriefDescription": "Number of cores in C-State; C3",
+        "EventCode": "0x80",
+        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
         "PerPkg": "1",
+        "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "Package C State Residency - C0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
+        "BriefDescription": "Number of cores in C-State; C6 and C7",
+        "EventCode": "0x80",
+        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
         "PerPkg": "1",
+        "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "Package C State Residency - C2E",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
+        "BriefDescription": "External Prochot",
+        "EventCode": "0xA",
+        "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that we are in external PROCHOT mode.  This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "Package C State Residency - C3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2C",
-        "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
+        "BriefDescription": "Internal Prochot",
+        "EventCode": "0x9",
+        "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that we are in Interal PROCHOT mode.  This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "Package C State Residency - C6",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2D",
-        "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
+        "BriefDescription": "Total Core C State Transition Cycles",
+        "EventCode": "0x72",
+        "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions across all cores.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "Package C7 State Residency",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES",
+        "BriefDescription": "UNC_P_UFS_TRANSITIONS_RING_GV",
+        "EventCode": "0x79",
+        "EventName": "UNC_P_UFS_TRANSITIONS_RING_GV",
         "PerPkg": "1",
+        "PublicDescription": "Ring GV with same final and initial frequency",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "Package C State Residency - C1E",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4E",
-        "EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES",
+        "BriefDescription": "VR Hot",
+        "EventCode": "0x42",
+        "EventName": "UNC_P_VR_HOT_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "UNC_P_VR_HOT_CYCLES",
         "Unit": "PCU"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json b/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json
index 6a6de8790f25f..93621e004d88f 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Load misses in all DTLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
@@ -12,8 +10,6 @@
     },
     {
         "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
         "SampleAfterValue": "2000003",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (2M).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
         "SampleAfterValue": "2000003",
@@ -30,8 +24,6 @@
     },
     {
         "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (4K).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
         "SampleAfterValue": "2000003",
@@ -39,8 +31,6 @@
     },
     {
         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
@@ -49,8 +39,6 @@
     },
     {
         "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
@@ -60,8 +48,6 @@
     },
     {
         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
@@ -71,8 +57,6 @@
     },
     {
         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
@@ -82,8 +66,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
@@ -93,8 +75,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
@@ -104,8 +84,6 @@
     },
     {
         "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT",
         "SampleAfterValue": "100003",
@@ -113,8 +91,6 @@
     },
     {
         "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (2M).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
         "SampleAfterValue": "100003",
@@ -122,8 +98,6 @@
     },
     {
         "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (4K).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
         "SampleAfterValue": "100003",
@@ -131,8 +105,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
@@ -141,8 +113,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
@@ -152,8 +122,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
@@ -163,8 +131,6 @@
     },
     {
         "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
@@ -174,8 +140,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_DURATION",
@@ -185,8 +149,6 @@
     },
     {
         "BriefDescription": "Cycle count for an Extended Page table walk.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4F",
         "EventName": "EPT.WALK_CYCLES",
         "PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.",
@@ -195,8 +157,6 @@
     },
     {
         "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAE",
         "EventName": "ITLB.ITLB_FLUSH",
         "PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
@@ -205,8 +165,6 @@
     },
     {
         "BriefDescription": "Misses at all ITLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
@@ -216,8 +174,6 @@
     },
     {
         "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT",
         "SampleAfterValue": "100003",
@@ -225,8 +181,6 @@
     },
     {
         "BriefDescription": "Code misses that miss the  DTLB and hit the STLB (2M).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT_2M",
         "SampleAfterValue": "100003",
@@ -234,8 +188,6 @@
     },
     {
         "BriefDescription": "Core misses that miss the  DTLB and hit the STLB (4K).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT_4K",
         "SampleAfterValue": "100003",
@@ -243,8 +195,6 @@
     },
     {
         "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
@@ -253,8 +203,6 @@
     },
     {
         "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
@@ -264,8 +212,6 @@
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
@@ -275,8 +221,6 @@
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
@@ -286,8 +230,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "BDM69",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_DURATION",
@@ -297,8 +239,6 @@
     },
     {
         "BriefDescription": "Number of DTLB page walker hits in the L1+FB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDM69, BDM98",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.DTLB_L1",
@@ -307,8 +247,6 @@
     },
     {
         "BriefDescription": "Number of DTLB page walker hits in the L2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDM69, BDM98",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.DTLB_L2",
@@ -317,8 +255,6 @@
     },
     {
         "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDM69, BDM98",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.DTLB_L3",
@@ -327,8 +263,6 @@
     },
     {
         "BriefDescription": "Number of DTLB page walker hits in Memory.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDM69, BDM98",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
@@ -337,8 +271,6 @@
     },
     {
         "BriefDescription": "Number of ITLB page walker hits in the L1+FB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDM69, BDM98",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.ITLB_L1",
@@ -347,8 +279,6 @@
     },
     {
         "BriefDescription": "Number of ITLB page walker hits in the L2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDM69, BDM98",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.ITLB_L2",
@@ -357,8 +287,6 @@
     },
     {
         "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "BDM69, BDM98",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.ITLB_L3",
@@ -367,8 +295,6 @@
     },
     {
         "BriefDescription": "DTLB flush attempts of the thread-specific entries",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.DTLB_THREAD",
         "PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.",
@@ -377,8 +303,6 @@
     },
     {
         "BriefDescription": "STLB flush attempts",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.STLB_ANY",
         "PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).",
-- 
GitLab


From 8358b1222798f1eaec057d770ea43ad9d059abf9 Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:49:53 -0800
Subject: [PATCH 570/875] perf vendor events intel: Refresh cascadelakex
 metrics and events

Update the cascadelakex metrics and events using the new tooling from:

  https://github.com/intel/perfmon

The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
order of metrics varies as TMA metrics are first converted and then
removed if perfmon versions are found. The events are updated with
fixes to uncore events and improved descriptions. The formatting
changes increase consistency across the json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065017.1621020-3-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../arch/x86/cascadelakex/cache.json          |  3644 --
 .../arch/x86/cascadelakex/clx-metrics.json    |  2217 +-
 .../arch/x86/cascadelakex/floating-point.json |    24 -
 .../arch/x86/cascadelakex/frontend.json       |   109 -
 .../arch/x86/cascadelakex/memory.json         |  2194 --
 .../arch/x86/cascadelakex/other.json          |   490 -
 .../arch/x86/cascadelakex/pipeline.json       |   194 -
 .../arch/x86/cascadelakex/uncore-memory.json  |  3185 +-
 .../arch/x86/cascadelakex/uncore-other.json   | 29770 +++++++++-------
 .../arch/x86/cascadelakex/uncore-power.json   |    45 +-
 .../arch/x86/cascadelakex/virtual-memory.json |    56 -
 11 files changed, 19060 insertions(+), 22868 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json b/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json
index 716c1b5074965..1070ad317ec91 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "L1D data line replacements",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x51",
         "EventName": "L1D.REPLACEMENT",
         "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.FB_FULL",
         "PublicDescription": "Number of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructions.",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "L1D miss outstandings duration in cycles",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING",
         "PublicDescription": "Counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch.Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Cycles with L1D load Misses outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -43,8 +35,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -53,8 +43,6 @@
     },
     {
         "BriefDescription": "L2 cache lines filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.ALL",
         "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
@@ -63,8 +51,6 @@
     },
     {
         "BriefDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3.  Clean lines may either be allocated in L3 or dropped",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.NON_SILENT",
         "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3.  Clean lines may either be allocated in L3 or dropped.",
@@ -73,8 +59,6 @@
     },
     {
         "BriefDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded event.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.SILENT",
         "SampleAfterValue": "200003",
@@ -82,8 +66,6 @@
     },
     {
         "BriefDescription": "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.USELESS_HWPF",
         "SampleAfterValue": "200003",
@@ -91,8 +73,6 @@
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Deprecated": "1",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.USELESS_PREF",
@@ -101,8 +81,6 @@
     },
     {
         "BriefDescription": "L2 code requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_CODE_RD",
         "PublicDescription": "Counts the total number of L2 code requests.",
@@ -111,8 +89,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
         "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
@@ -121,8 +97,6 @@
     },
     {
         "BriefDescription": "Demand requests that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
         "PublicDescription": "Demand requests that miss L2 cache.",
@@ -131,8 +105,6 @@
     },
     {
         "BriefDescription": "Demand requests to L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
         "PublicDescription": "Demand requests to L2 cache.",
@@ -141,8 +113,6 @@
     },
     {
         "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_PF",
         "PublicDescription": "Counts the total number of requests from the L2 hardware prefetchers.",
@@ -151,8 +121,6 @@
     },
     {
         "BriefDescription": "RFO requests to L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_RFO",
         "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
@@ -161,8 +129,6 @@
     },
     {
         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_HIT",
         "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
@@ -171,8 +137,6 @@
     },
     {
         "BriefDescription": "L2 cache misses when fetching instructions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_MISS",
         "PublicDescription": "Counts L2 cache misses when fetching instructions.",
@@ -181,8 +145,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
         "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",
@@ -191,8 +153,6 @@
     },
     {
         "BriefDescription": "Demand Data Read miss L2, no rejects",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
         "PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
@@ -201,8 +161,6 @@
     },
     {
         "BriefDescription": "All requests that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.MISS",
         "PublicDescription": "All requests that miss L2 cache.",
@@ -211,8 +169,6 @@
     },
     {
         "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PF_HIT",
         "PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache.",
@@ -221,8 +177,6 @@
     },
     {
         "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PF_MISS",
         "PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache.",
@@ -231,8 +185,6 @@
     },
     {
         "BriefDescription": "All L2 requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.REFERENCES",
         "PublicDescription": "All L2 requests.",
@@ -241,8 +193,6 @@
     },
     {
         "BriefDescription": "RFO requests that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_HIT",
         "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
@@ -251,8 +201,6 @@
     },
     {
         "BriefDescription": "RFO requests that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_MISS",
         "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
@@ -261,8 +209,6 @@
     },
     {
         "BriefDescription": "L2 writebacks that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L2_WB",
         "PublicDescription": "Counts L2 writebacks that access L2 cache.",
@@ -271,8 +217,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests missed L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL057",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.MISS",
@@ -282,8 +226,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL057",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
@@ -293,8 +235,6 @@
     },
     {
         "BriefDescription": "All retired load instructions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.ALL_LOADS",
@@ -304,24 +244,18 @@
     },
     {
         "BriefDescription": "All retired store instructions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.ALL_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "SampleAfterValue": "2000003",
         "UMask": "0x82"
     },
     {
         "BriefDescription": "All retired memory instructions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.ANY",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "PublicDescription": "Counts all retired memory instructions - loads and stores.",
         "SampleAfterValue": "2000003",
@@ -329,8 +263,6 @@
     },
     {
         "BriefDescription": "Retired load instructions with locked access.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.LOCK_LOADS",
@@ -340,8 +272,6 @@
     },
     {
         "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
@@ -352,12 +282,9 @@
     },
     {
         "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.SPLIT_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
         "SampleAfterValue": "100003",
@@ -365,8 +292,6 @@
     },
     {
         "BriefDescription": "Retired load instructions that miss the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
@@ -377,12 +302,9 @@
     },
     {
         "BriefDescription": "Retired store instructions that miss the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).",
         "SampleAfterValue": "100003",
@@ -390,8 +312,6 @@
     },
     {
         "BriefDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
@@ -402,8 +322,6 @@
     },
     {
         "BriefDescription": "Retired load instructions which data sources were HitM responses from shared L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
@@ -414,8 +332,6 @@
     },
     {
         "BriefDescription": "Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
@@ -425,8 +341,6 @@
     },
     {
         "BriefDescription": "Retired load instructions which data sources were hits in L3 without snoops required",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
@@ -437,8 +351,6 @@
     },
     {
         "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD3",
         "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
@@ -449,8 +361,6 @@
     },
     {
         "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from remote dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD3",
         "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM",
@@ -460,8 +370,6 @@
     },
     {
         "BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD3",
         "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD",
@@ -471,8 +379,6 @@
     },
     {
         "BriefDescription": "Retired load instructions whose data sources was remote HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD3",
         "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM",
@@ -483,10 +389,7 @@
     },
     {
         "BriefDescription": "Retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches. Precise event.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
-        "ELLC": "1",
         "EventCode": "0xD3",
         "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM",
         "PEBS": "1",
@@ -496,8 +399,6 @@
     },
     {
         "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD4",
         "EventName": "MEM_LOAD_MISC_RETIRED.UC",
@@ -507,8 +408,6 @@
     },
     {
         "BriefDescription": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_RETIRED.FB_HIT",
@@ -519,8 +418,6 @@
     },
     {
         "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_RETIRED.L1_HIT",
@@ -531,8 +428,6 @@
     },
     {
         "BriefDescription": "Retired load instructions missed L1 cache as data sources",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_RETIRED.L1_MISS",
@@ -543,8 +438,6 @@
     },
     {
         "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_RETIRED.L2_HIT",
@@ -555,8 +448,6 @@
     },
     {
         "BriefDescription": "Retired load instructions missed L2 cache as data sources",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_RETIRED.L2_MISS",
@@ -567,8 +458,6 @@
     },
     {
         "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_RETIRED.L3_HIT",
@@ -579,8 +468,6 @@
     },
     {
         "BriefDescription": "Retired load instructions missed L3 cache as data sources",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_RETIRED.L3_MISS",
@@ -591,10 +478,7 @@
     },
     {
         "BriefDescription": "Retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches. Precise event.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
-        "ELLC": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_RETIRED.LOCAL_PMM",
         "PEBS": "1",
@@ -604,6056 +488,4542 @@
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP  OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP  OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP  OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP  OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP  OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP  OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP  OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP  OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C07F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C07F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C07F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C07F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C07F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C07F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_MISS OCR.ALL_READS.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C07F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_NONE OCR.ALL_READS.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C07F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP  OCR.ALL_READS.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F800807F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE  OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10000807F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8000807F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4000807F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000807F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000807F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800807F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP  OCR.ALL_READS.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F802007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE  OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10002007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8002007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4002007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1002007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2002007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x802007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP  OCR.ALL_READS.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F800407F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE  OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10000407F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8000407F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4000407F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000407F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000407F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800407F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP  OCR.ALL_READS.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F801007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE  OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10001007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8001007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4001007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1001007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2001007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x801007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS OCR.ALL_RFO.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE OCR.ALL_RFO.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP  OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE  OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP  OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE  OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP  OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE  OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP  OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE  OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.ANY_SNOOP OCR.OTHER.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HITM_OTHER_CORE OCR.OTHER.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80088000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000088000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800088000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400088000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100088000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200088000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80088000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80208000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000208000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800208000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400208000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100208000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200208000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80208000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80048000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000048000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800048000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400048000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100048000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200048000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80048000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80108000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000108000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800108000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400108000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100108000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200108000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80108000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Demand and prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
         "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
@@ -6662,8 +5032,6 @@
     },
     {
         "BriefDescription": "Any memory transaction that reached the SQ.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
         "PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..",
@@ -6672,8 +5040,6 @@
     },
     {
         "BriefDescription": "Cacheable and noncachaeble code read requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
         "PublicDescription": "Counts both cacheable and non-cacheable code read requests.",
@@ -6682,8 +5048,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests sent to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
         "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
@@ -6692,8 +5056,6 @@
     },
     {
         "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
         "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
@@ -6702,8 +5064,6 @@
     },
     {
         "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB2",
         "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
         "PublicDescription": "Counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entries.",
@@ -6712,8 +5072,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
         "PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
@@ -6722,8 +5080,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
@@ -6733,8 +5089,6 @@
     },
     {
         "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
@@ -6744,8 +5098,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
@@ -6755,8 +5107,6 @@
     },
     {
         "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
@@ -6766,8 +5116,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
         "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
@@ -6776,8 +5124,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
         "PublicDescription": "Counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the promotion point.",
@@ -6786,8 +5132,6 @@
     },
     {
         "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "6",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
@@ -6796,8 +5140,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
         "PublicDescription": "Counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
@@ -6806,8 +5148,6 @@
     },
     {
         "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
@@ -6816,8562 +5156,6586 @@
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.ANY_RESPONSE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.ANY_RESPONSE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.ANY_RESPONSE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.ANY_RESPONSE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x107F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C07F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C07F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C07F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C07F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C07F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C07F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C07F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C07F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F800807F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10000807F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8000807F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4000807F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000807F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000807F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800807F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F802007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10002007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8002007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4002007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1002007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2002007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x802007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F800407F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10000407F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8000407F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4000407F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000407F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000407F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800407F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F801007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10001007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8001007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4001007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1001007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2001007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x801007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F804007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F800207F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10000207F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8000207F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4000207F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000207F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000207F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800207F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.ANY_RESPONSE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.ANY_RESPONSE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.ANY_RESPONSE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.ANY_RESPONSE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.ANY_RESPONSE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x18000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80088000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000088000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800088000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400088000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100088000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200088000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80088000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80208000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000208000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800208000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400208000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100208000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200208000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80208000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80048000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000048000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800048000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400048000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100048000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200048000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80048000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80108000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000108000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800108000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400108000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100108000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200108000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80108000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80028000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000028000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800028000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400028000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100028000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200028000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80028000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.ANY_RESPONSE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.ANY_RESPONSE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.ANY_RESPONSE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.ANY_RESPONSE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.ANY_RESPONSE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8007C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80080100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800080100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80200100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000200100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800200100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400200100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100200100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200200100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80200100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80040100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800040100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80100100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800100100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of cache line split locks sent to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF4",
         "EventName": "SQ_MISC.SPLIT_LOCK",
         "PublicDescription": "Counts the number of cache line split locks sent to the uncore.",
@@ -15380,8 +11744,6 @@
     },
     {
         "BriefDescription": "Number of PREFETCHNTA instructions executed.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.NTA",
         "SampleAfterValue": "2000003",
@@ -15389,8 +11751,6 @@
     },
     {
         "BriefDescription": "Number of PREFETCHW instructions executed.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
         "SampleAfterValue": "2000003",
@@ -15398,8 +11758,6 @@
     },
     {
         "BriefDescription": "Number of PREFETCHT0 instructions executed.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.T0",
         "SampleAfterValue": "2000003",
@@ -15407,8 +11765,6 @@
     },
     {
         "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.T1_T2",
         "SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json b/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json
index 81de1149297da..356cf6603b69c 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json
@@ -1,1575 +1,1548 @@
 [
     {
-        "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
-        "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS",
-        "MetricGroup": "PGO;TopdownL1;tma_L1_group",
-        "MetricName": "tma_frontend_bound",
-        "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS",
-        "ScaleUnit": "100%"
-    },
-    {
-        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
-        "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS",
-        "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
-        "MetricName": "tma_fetch_latency",
-        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
+        "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
+        "MetricGroup": "Bad;BadSpec;BrMispredicts",
+        "MetricName": "Mispredictions"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses",
-        "MetricExpr": "(ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@) / CLKS",
-        "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_icache_misses",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
+        "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))",
+        "MetricGroup": "Mem;MemoryBW;Offcore",
+        "MetricName": "Memory_Bandwidth"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses",
-        "MetricExpr": "ICACHE_64B.IFTAG_STALL / CLKS",
-        "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_itlb_misses",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
+        "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound))",
+        "MetricGroup": "Mem;MemoryLat;Offcore",
+        "MetricName": "Memory_Latency"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
-        "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CLKS + tma_unknown_branches",
-        "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_branch_resteers",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
+        "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)))",
+        "MetricGroup": "Mem;MemoryTLB;Offcore",
+        "MetricName": "Memory_Data_TLBs"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage",
-        "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
-        "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group",
-        "MetricName": "tma_mispredicts_resteers",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage.  Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)",
+        "MetricExpr": "100 * ((BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)",
+        "MetricGroup": "Ret",
+        "MetricName": "Branching_Overhead"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears",
-        "MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT))) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
-        "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group",
-        "MetricName": "tma_clears_resteers",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears.  Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)",
+        "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)",
+        "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB",
+        "MetricName": "Big_Code"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
-        "MetricExpr": "9 * BACLEARS.ANY / CLKS",
-        "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_branch_resteers_group",
-        "MetricName": "tma_unknown_branches",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: BACLEARS.ANY",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks",
+        "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code",
+        "MetricGroup": "Fed;FetchBW;Frontend",
+        "MetricName": "Instruction_Fetch_BW"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
-        "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS",
-        "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_dsb_switches",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
+        "MetricExpr": "INST_RETIRED.ANY / CLKS",
+        "MetricGroup": "Ret;Summary",
+        "MetricName": "IPC"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
-        "MetricExpr": "ILD_STALL.LCP / CLKS",
-        "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_lcp",
-        "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Uops Per Instruction",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
+        "MetricGroup": "Pipeline;Ret;Retire",
+        "MetricName": "UPI"
     },
     {
-        "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
-        "MetricExpr": "2 * IDQ.MS_SWITCHES / CLKS",
-        "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_ms_switches",
-        "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instruction per taken branch",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
+        "MetricGroup": "Branches;Fed;FetchBW",
+        "MetricName": "UpTB"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
-        "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
-        "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
-        "MetricName": "tma_fetch_bandwidth",
-        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues.  For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
+        "MetricExpr": "1 / IPC",
+        "MetricGroup": "Mem;Pipeline",
+        "MetricName": "CPI"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
-        "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
-        "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
-        "MetricName": "tma_mite",
-        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "Pipeline",
+        "MetricName": "CLKS"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder",
-        "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) / CORE_CLKS",
-        "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_mite_group",
-        "MetricName": "tma_decoder0_alone",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
+        "MetricExpr": "4 * CORE_CLKS",
+        "MetricGroup": "tma_L1_group",
+        "MetricName": "SLOTS"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
-        "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2",
-        "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
-        "MetricName": "tma_dsb",
-        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline.  For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "The ratio of Executed- by Issued-Uops",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
+        "MetricGroup": "Cor;Pipeline",
+        "MetricName": "Execute_per_Issue",
+        "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
     },
     {
-        "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
-        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
-        "MetricGroup": "TopdownL1;tma_L1_group",
-        "MetricName": "tma_bad_speculation",
-        "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
+        "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
+        "MetricGroup": "Ret;SMT;tma_L1_group",
+        "MetricName": "CoreIPC"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
-        "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
-        "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
-        "MetricName": "tma_branch_mispredicts",
-        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Floating Point Operations Per Cycle",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS",
+        "MetricGroup": "Flops;Ret",
+        "MetricName": "FLOPc"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
-        "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
-        "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group",
-        "MetricName": "tma_machine_clears",
-        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears.  These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
+        "MetricGroup": "Cor;Flops;HPC",
+        "MetricName": "FP_Arith_Utilization",
+        "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
     },
     {
-        "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
-        "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
-        "MetricGroup": "TopdownL1;tma_L1_group",
-        "MetricName": "tma_backend_bound",
-        "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
+        "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
+        "MetricName": "ILP"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
-        "MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * tma_backend_bound",
-        "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
-        "MetricName": "tma_memory_bound",
-        "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
+        "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)",
+        "MetricGroup": "Cor;SMT",
+        "MetricName": "Core_Bound_Likely"
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
-        "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CLKS, 0)",
-        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_l1_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache.  The L1 data cache typically has the shortest latency.  However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
+        "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
+        "MetricGroup": "SMT",
+        "MetricName": "CORE_CLKS"
     },
     {
-        "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
-        "MetricExpr": "min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / CLKS",
-        "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_dtlb_load",
-        "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS",
+        "MetricGroup": "InsType",
+        "MetricName": "IpLoad"
     },
     {
-        "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
-        "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
-        "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group",
-        "MetricName": "tma_load_stlb_hit",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES",
+        "MetricGroup": "InsType",
+        "MetricName": "IpStore"
     },
     {
-        "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk",
-        "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CLKS",
-        "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group",
-        "MetricName": "tma_load_stlb_miss",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Branches;Fed;InsType",
+        "MetricName": "IpBranch"
     },
     {
-        "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
-        "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS",
-        "MetricGroup": "TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_store_fwd_blk",
-        "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
+        "MetricGroup": "Branches;Fed;PGO",
+        "MetricName": "IpCall"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
-        "MetricExpr": "(12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * (11 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
-        "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_lock_latency",
-        "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instruction per taken branch",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
+        "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
+        "MetricName": "IpTB"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary",
-        "MetricExpr": "Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS",
-        "MetricGroup": "TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_split_loads",
-        "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary.  Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Branch instructions per taken branch. ",
+        "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
+        "MetricGroup": "Branches;Fed;PGO",
+        "MetricName": "BpTkBranch"
     },
     {
-        "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
-        "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CLKS",
-        "MetricGroup": "TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_4k_aliasing",
-        "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
+        "MetricGroup": "Flops;InsType",
+        "MetricName": "IpFLOP"
     },
     {
-        "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
-        "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / CLKS",
-        "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_fb_full",
-        "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))",
+        "MetricGroup": "Flops;InsType",
+        "MetricName": "IpArith",
+        "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
-        "MetricExpr": "((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / ((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@)) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS)",
-        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_l2_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
+        "MetricGroup": "Flops;FpScalar;InsType",
+        "MetricName": "IpArith_Scalar_SP",
+        "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
-        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / CLKS",
-        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_l3_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
+        "MetricGroup": "Flops;FpScalar;InsType",
+        "MetricName": "IpArith_Scalar_DP",
+        "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
-        "MetricExpr": "((44 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD))) + (44 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_contested_accesses",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)",
+        "MetricGroup": "Flops;FpVector;InsType",
+        "MetricName": "IpArith_AVX128",
+        "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
-        "MetricExpr": "(44 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD)))) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_data_sharing",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
+        "MetricGroup": "Flops;FpVector;InsType",
+        "MetricName": "IpArith_AVX256",
+        "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
-        "MetricExpr": "(17 * Average_Frequency) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_l3_hit_latency",
-        "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
+        "MetricGroup": "Flops;FpVector;InsType",
+        "MetricName": "IpArith_AVX512",
+        "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
-        "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
-        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_sq_full",
-        "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@",
+        "MetricGroup": "Prefetches",
+        "MetricName": "IpSWPF"
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
-        "MetricExpr": "((CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS) - tma_l2_bound) - tma_pmm_bound)",
-        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_dram_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
+        "MetricExpr": "INST_RETIRED.ANY",
+        "MetricGroup": "Summary;tma_L1_group",
+        "MetricName": "Instructions"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
-        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / CLKS",
-        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group",
-        "MetricName": "tma_mem_bandwidth",
-        "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM).  The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
+        "MetricGroup": "Pipeline;Ret",
+        "MetricName": "Retire"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
-        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth",
-        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group",
-        "MetricName": "tma_mem_latency",
-        "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM).  This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
+        "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
+        "MetricName": "Execute"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
-        "MetricExpr": "(59.5 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "Server;TopdownL5;tma_mem_latency_group",
-        "MetricName": "tma_local_dram",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average number of Uops issued by front-end when it issued something",
+        "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@",
+        "MetricGroup": "Fed;FetchBW",
+        "MetricName": "Fetch_UpC"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
-        "MetricExpr": "(127 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "Server;Snoop;TopdownL5;tma_mem_latency_group",
-        "MetricName": "tma_remote_dram",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
+        "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
+        "MetricGroup": "DSB;Fed;FetchBW",
+        "MetricName": "DSB_Coverage"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
-        "MetricExpr": "((89.5 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + (89.5 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_mem_latency_group",
-        "MetricName": "tma_remote_cache",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
+        "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHES.COUNT",
+        "MetricGroup": "DSBmiss",
+        "MetricName": "DSB_Switch_Cost"
     },
     {
-        "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a",
-        "MetricExpr": "(((1 - ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + 10 * ((MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) / ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + 10 * ((MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS) - tma_l2_bound)) if (1000000 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS) else 0)",
-        "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_pmm_bound",
-        "PublicDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
+        "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))",
+        "MetricGroup": "DSBmiss;Fed",
+        "MetricName": "DSB_Misses"
     },
     {
-        "BriefDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
-        "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CLKS",
-        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_store_bound",
-        "PublicDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS",
+        "MetricGroup": "DSBmiss;Fed",
+        "MetricName": "IpDSB_Miss_Ret"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
-        "MetricExpr": "((L2_RQSTS.RFO_HIT * 11 * (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES))) + (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
-        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_store_latency",
-        "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;BadSpec;BrMispredicts",
+        "MetricName": "IpMispredict"
     },
     {
-        "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
-        "MetricExpr": "((110 * Average_Frequency) * (OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM + OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM) + (47.5 * Average_Frequency) * (OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE)) / CLKS",
-        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_false_sharing",
-        "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line.  Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
+        "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;BrMispredicts",
+        "MetricName": "Branch_Misprediction_Cost"
     },
     {
-        "BriefDescription": "This metric represents rate of split store accesses",
-        "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CORE_CLKS",
-        "MetricGroup": "TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_split_stores",
-        "PublicDescription": "This metric represents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of branches that are non-taken conditionals",
+        "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;Branches;CodeGen;PGO",
+        "MetricName": "Cond_NT"
     },
     {
-        "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
-        "MetricExpr": "(9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CORE_CLKS",
-        "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_dtlb_store",
-        "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead.  Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page.  Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of branches that are taken conditionals",
+        "MetricExpr": "(BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) / BR_INST_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;Branches;CodeGen;PGO",
+        "MetricName": "Cond_TK"
     },
     {
-        "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
-        "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
-        "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group",
-        "MetricName": "tma_store_stlb_hit",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of branches that are CALL or RET",
+        "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;Branches",
+        "MetricName": "CallRet"
     },
     {
-        "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk",
-        "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS",
-        "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group",
-        "MetricName": "tma_store_stlb_miss",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps",
+        "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;Branches",
+        "MetricName": "Jump"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
-        "MetricExpr": "tma_backend_bound - tma_memory_bound",
-        "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group",
-        "MetricName": "tma_core_bound",
-        "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
+        "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)",
+        "MetricGroup": "Mem;MemoryBound;MemoryLat",
+        "MetricName": "Load_Miss_Real_Latency"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
-        "MetricExpr": "ARITH.DIVIDER_ACTIVE / CLKS",
-        "MetricGroup": "TopdownL3;tma_core_bound_group",
-        "MetricName": "tma_divider",
-        "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
+        "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
+        "MetricGroup": "Mem;MemoryBW;MemoryBound",
+        "MetricName": "MLP"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
-        "MetricExpr": "(EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if (ARITH.DIVIDER_ACTIVE < (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY)) else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CLKS",
-        "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
-        "MetricName": "tma_ports_utilization",
-        "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L1MPKI"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_NONE / 2 if #SMT_on else CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CORE_CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_0",
-        "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
+        "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L1MPKI_Load"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations",
-        "MetricExpr": "PARTIAL_RAT_STALLS.SCOREBOARD / CLKS",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_0_group",
-        "MetricName": "tma_serializing_operation",
-        "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: PARTIAL_RAT_STALLS.SCOREBOARD",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+        "MetricGroup": "Backend;CacheMisses;Mem",
+        "MetricName": "L2MPKI"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions",
-        "MetricExpr": "40 * ROB_MISC_EVENTS.PAUSE_INST / CLKS",
-        "MetricGroup": "TopdownL6;tma_serializing_operation_group",
-        "MetricName": "tma_slow_pause",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: MISC_RETIRED.PAUSE_INST",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
+        "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem;Offcore",
+        "MetricName": "L2MPKI_All"
     },
     {
-        "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued",
-        "MetricExpr": "CLKS * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_0_group",
-        "MetricName": "tma_mixing_vectors",
-        "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (including speculative)",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L2MPKI_Load"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2) / 2 if #SMT_on else EXE_ACTIVITY.1_PORTS_UTIL) / CORE_CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_1",
-        "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
+        "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L2HPKI_All"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3) / 2 if #SMT_on else EXE_ACTIVITY.2_PORTS_UTIL) / CORE_CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_2",
-        "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache hits per kilo instruction for all demand loads  (including speculative)",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L2HPKI_Load"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
-        "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_3) / CORE_CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_3m",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L3MPKI"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
-        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / (4 * CORE_CLKS)",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
-        "MetricName": "tma_alu_op_utilization",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "FB_HPKI"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED_PORT.PORT_0",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS",
-        "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group",
-        "MetricName": "tma_port_0",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
+        "MetricConstraint": "NO_NMI_WATCHDOG",
+        "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING) / (2 * CORE_CLKS)",
+        "MetricGroup": "Mem;MemoryTLB",
+        "MetricName": "Page_Walks_Utilization"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_1",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
-        "MetricName": "tma_port_1",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
+        "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L1D_Cache_Fill_BW"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) Sample with: UOPS_DISPATCHED.PORT_5",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
-        "MetricName": "tma_port_5",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
+        "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L2_Cache_Fill_BW"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_6",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
-        "MetricName": "tma_port_6",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
+        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L3_Cache_Fill_BW"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3",
-        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
-        "MetricName": "tma_load_op_utilization",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
+        "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW;Offcore",
+        "MetricName": "L3_Cache_Access_BW"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_2",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_load_op_utilization_group",
-        "MetricName": "tma_port_2",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
+        "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / Instructions",
+        "MetricGroup": "L2Evicts;Mem;Server",
+        "MetricName": "L2_Evictions_Silent_PKI"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_3",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_load_op_utilization_group",
-        "MetricName": "tma_port_3",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
+        "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / Instructions",
+        "MetricGroup": "L2Evicts;Mem;Server",
+        "MetricName": "L2_Evictions_NonSilent_PKI"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
-        "MetricName": "tma_store_op_utilization",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
+        "MetricExpr": "L1D_Cache_Fill_BW",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L1D_Cache_Fill_BW_1T"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data) Sample with: UOPS_DISPATCHED_PORT.PORT_4",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_store_op_utilization_group",
-        "MetricName": "tma_port_4",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
+        "MetricExpr": "L2_Cache_Fill_BW",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L2_Cache_Fill_BW_1T"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address) Sample with: UOPS_DISPATCHED_PORT.PORT_7",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_store_op_utilization_group",
-        "MetricName": "tma_port_7",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
+        "MetricExpr": "L3_Cache_Fill_BW",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L3_Cache_Fill_BW_1T"
     },
     {
-        "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
-        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS",
-        "MetricGroup": "TopdownL1;tma_L1_group",
-        "MetricName": "tma_retiring",
-        "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided.  Sample with: UOPS_RETIRED.RETIRE_SLOTS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
+        "MetricExpr": "L3_Cache_Access_BW",
+        "MetricGroup": "Mem;MemoryBW;Offcore",
+        "MetricName": "L3_Cache_Access_BW_1T"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
-        "MetricExpr": "tma_retiring - tma_heavy_operations",
-        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
-        "MetricName": "tma_light_operations",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average CPU Utilization",
+        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+        "MetricGroup": "HPC;Summary",
+        "MetricName": "CPU_Utilization"
     },
     {
-        "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
-        "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector",
-        "MetricGroup": "HPC;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_fp_arith",
-        "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
+        "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
+        "MetricGroup": "Power;Summary",
+        "MetricName": "Average_Frequency"
     },
     {
-        "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
-        "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD",
-        "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group",
-        "MetricName": "tma_x87_use",
-        "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Giga Floating Point Operations Per Second",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time",
+        "MetricGroup": "Cor;Flops;HPC",
+        "MetricName": "GFLOPs",
+        "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
     },
     {
-        "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / UOPS_RETIRED.RETIRE_SLOTS",
-        "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group",
-        "MetricName": "tma_fp_scalar",
-        "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average Frequency Utilization relative nominal frequency",
+        "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
+        "MetricGroup": "Power",
+        "MetricName": "Turbo_Utilization"
     },
     {
-        "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS",
-        "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group",
-        "MetricName": "tma_fp_vector",
-        "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0",
+        "MetricExpr": "(CORE_POWER.LVL0_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL0_TURBO_LICENSE / CORE_CLKS)",
+        "MetricGroup": "Power",
+        "MetricName": "Power_License0_Utilization",
+        "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes."
     },
     {
-        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS",
-        "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
-        "MetricName": "tma_fp_vector_128b",
-        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1",
+        "MetricExpr": "(CORE_POWER.LVL1_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL1_TURBO_LICENSE / CORE_CLKS)",
+        "MetricGroup": "Power",
+        "MetricName": "Power_License1_Utilization",
+        "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions."
     },
     {
-        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS",
-        "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
-        "MetricName": "tma_fp_vector_256b",
-        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)",
+        "MetricExpr": "(CORE_POWER.LVL2_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL2_TURBO_LICENSE / CORE_CLKS)",
+        "MetricGroup": "Power",
+        "MetricName": "Power_License2_Utilization",
+        "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX).  This includes high current AVX 512-bit instructions."
     },
     {
-        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS",
-        "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
-        "MetricName": "tma_fp_vector_512b",
-        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
+        "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
+        "MetricGroup": "SMT",
+        "MetricName": "SMT_2T_Utilization"
+    },
+    {
+        "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "OS",
+        "MetricName": "Kernel_Utilization"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.",
-        "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY",
-        "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_memory_operations",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
+        "MetricGroup": "OS",
+        "MetricName": "Kernel_CPI"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions",
-        "MetricExpr": "tma_light_operations * UOPS_RETIRED.MACRO_FUSED / UOPS_RETIRED.RETIRE_SLOTS",
-        "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_fused_instructions",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
+        "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time",
+        "MetricGroup": "HPC;Mem;MemoryBW;SoC",
+        "MetricName": "DRAM_BW_Use"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused",
-        "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS",
-        "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_non_fused_branches",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
+        "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (Socket_CLKS / duration_time)",
+        "MetricGroup": "Mem;MemoryLat;SoC",
+        "MetricName": "MEM_Read_Latency"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions",
-        "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / UOPS_RETIRED.RETIRE_SLOTS",
-        "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_nop_instructions",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
+        "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@thresh\\=1@",
+        "MetricGroup": "Mem;MemoryBW;SoC",
+        "MetricName": "MEM_Parallel_Reads"
     },
     {
-        "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting",
-        "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions))",
-        "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_other_light_ops",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
+        "MetricExpr": "1e9 * (UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS) / imc_0@event\\=0x0@",
+        "MetricGroup": "Mem;MemoryLat;Server;SoC",
+        "MetricName": "MEM_PMM_Read_Latency"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
-        "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / SLOTS",
-        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
-        "MetricName": "tma_heavy_operations",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
+        "MetricExpr": "1e9 * (UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSERTS) / imc_0@event\\=0x0@",
+        "MetricGroup": "Mem;MemoryLat;Server;SoC",
+        "MetricName": "MEM_DRAM_Read_Latency"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops",
-        "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer",
-        "MetricGroup": "TopdownL3;tma_heavy_operations_group",
-        "MetricName": "tma_few_uops_instructions",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]",
+        "MetricExpr": "64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW;Server;SoC",
+        "MetricName": "PMM_Read_BW"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
-        "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
-        "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
-        "MetricName": "tma_microcode_sequencer",
-        "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]",
+        "MetricExpr": "64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW;Server;SoC",
+        "MetricName": "PMM_Write_BW"
     },
     {
-        "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
-        "MetricExpr": "100 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / SLOTS",
-        "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
-        "MetricName": "tma_assists",
-        "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]",
+        "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1e9 / duration_time",
+        "MetricGroup": "IoBW;Mem;Server;SoC",
+        "MetricName": "IO_Write_BW"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
-        "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
-        "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
-        "MetricName": "tma_cisc",
-        "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]",
+        "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3) * 4 / 1e9 / duration_time",
+        "MetricGroup": "IoBW;Mem;Server;SoC",
+        "MetricName": "IO_Read_BW"
     },
     {
-        "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
-        "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
-        "MetricGroup": "Bad;BadSpec;BrMispredicts",
-        "MetricName": "Mispredictions"
+        "BriefDescription": "Socket actual clocks when any core is active on that socket",
+        "MetricExpr": "cha_0@event\\=0x0@",
+        "MetricGroup": "SoC",
+        "MetricName": "Socket_CLKS"
     },
     {
-        "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) ",
-        "MetricGroup": "Mem;MemoryBW;Offcore",
-        "MetricName": "Memory_Bandwidth"
+        "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
+        "MetricGroup": "Branches;OS",
+        "MetricName": "IpFarBranch"
     },
     {
-        "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + (tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)))",
-        "MetricGroup": "Mem;MemoryLat;Offcore",
-        "MetricName": "Memory_Latency"
+        "BriefDescription": "Uncore frequency per die [GHZ]",
+        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+        "MetricGroup": "SoC",
+        "MetricName": "UNCORE_FREQ"
     },
     {
-        "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency))) ",
-        "MetricGroup": "Mem;MemoryTLB;Offcore",
-        "MetricName": "Memory_Data_TLBs"
+        "BriefDescription": "Percentage of time spent in the active CPU power state C0",
+        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+        "MetricName": "cpu_utilization",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)",
-        "MetricExpr": "100 * ((BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)",
-        "MetricGroup": "Ret",
-        "MetricName": "Branching_Overhead"
+        "BriefDescription": "CPU operating frequency (in GHz)",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / duration_time",
+        "MetricName": "cpu_operating_frequency",
+        "ScaleUnit": "1GHz"
     },
     {
-        "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)",
-        "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)",
-        "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB",
-        "MetricName": "Big_Code"
+        "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY",
+        "MetricName": "cpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks",
-        "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code",
-        "MetricGroup": "Fed;FetchBW;Frontend",
-        "MetricName": "Instruction_Fetch_BW"
+        "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
+        "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
+        "MetricName": "loads_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
-        "MetricExpr": "INST_RETIRED.ANY / CLKS",
-        "MetricGroup": "Ret;Summary",
-        "MetricName": "IPC"
+        "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
+        "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY",
+        "MetricName": "stores_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Uops Per Instruction",
-        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
-        "MetricGroup": "Pipeline;Ret;Retire",
-        "MetricName": "UPI"
+        "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
+        "MetricName": "l1d_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instruction per taken branch",
-        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
-        "MetricGroup": "Branches;Fed;FetchBW",
-        "MetricName": "UpTB"
+        "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ",
+        "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY",
+        "MetricName": "l1d_demand_data_read_hits_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
-        "MetricExpr": "1 / IPC",
-        "MetricGroup": "Mem;Pipeline",
-        "MetricName": "CPI"
+        "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
+        "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
+        "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
-        "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
-        "MetricGroup": "Pipeline",
-        "MetricName": "CLKS"
+        "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ",
+        "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY",
+        "MetricName": "l2_demand_data_read_hits_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
-        "MetricExpr": "4 * CORE_CLKS",
-        "MetricGroup": "tma_L1_group",
-        "MetricName": "SLOTS"
+        "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
+        "MetricName": "l2_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "The ratio of Executed- by Issued-Uops",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
-        "MetricGroup": "Cor;Pipeline",
-        "MetricName": "Execute_per_Issue",
-        "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
+        "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
+        "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+        "MetricName": "l2_demand_data_read_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
-        "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
-        "MetricGroup": "Ret;SMT;tma_L1_group",
-        "MetricName": "CoreIPC"
+        "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
+        "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
+        "MetricName": "l2_demand_code_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Floating Point Operations Per Cycle",
-        "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS",
-        "MetricGroup": "Flops;Ret",
-        "MetricName": "FLOPc"
+        "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x12D4043300000000@ / INST_RETIRED.ANY",
+        "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
-        "MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
-        "MetricGroup": "Cor;Flops;HPC",
-        "MetricName": "FP_Arith_Utilization",
-        "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
+        "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x12CC023300000000@ / INST_RETIRED.ANY",
+        "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / ((UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
-        "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
-        "MetricName": "ILP"
+        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds",
+        "MetricExpr": "1e9 * (cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043300000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043300000000@) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages)) * duration_time",
+        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency",
+        "ScaleUnit": "1ns"
     },
     {
-        "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
-        "MetricExpr": "(1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0",
-        "MetricGroup": "Cor;SMT",
-        "MetricName": "Core_Bound_Likely"
+        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds",
+        "MetricExpr": "1e9 * (cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043200000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages)) * duration_time",
+        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests",
+        "ScaleUnit": "1ns"
     },
     {
-        "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
-        "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
-        "MetricGroup": "SMT",
-        "MetricName": "CORE_CLKS"
+        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds",
+        "MetricExpr": "1e9 * (cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043100000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages)) * duration_time",
+        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests",
+        "ScaleUnit": "1ns"
     },
     {
-        "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS",
-        "MetricGroup": "InsType",
-        "MetricName": "IpLoad"
+        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions",
+        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+        "MetricName": "itlb_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES",
-        "MetricGroup": "InsType",
-        "MetricName": "IpStore"
+        "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions",
+        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+        "MetricName": "itlb_large_page_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Branches;Fed;InsType",
-        "MetricName": "IpBranch"
+        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions",
+        "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+        "MetricName": "dtlb_load_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
-        "MetricGroup": "Branches;Fed;PGO",
-        "MetricName": "IpCall"
+        "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions",
+        "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+        "MetricName": "dtlb_2mb_large_page_load_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instruction per taken branch",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
-        "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
-        "MetricName": "IpTB"
+        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions",
+        "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+        "MetricName": "dtlb_store_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
+    },
+    {
+        "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+        "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ / (cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@)",
+        "MetricName": "numa_reads_addressed_to_local_dram",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Branch instructions per taken branch. ",
-        "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
-        "MetricGroup": "Branches;Fed;PGO",
-        "MetricName": "BpTkBranch"
+        "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+        "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@ / (cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@)",
+        "MetricName": "numa_reads_addressed_to_remote_dram",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
-        "MetricGroup": "Flops;InsType",
-        "MetricName": "IpFLOP"
+        "BriefDescription": "Uncore operating frequency in GHz",
+        "MetricExpr": "UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages) / 1e9 / duration_time",
+        "MetricName": "uncore_frequency",
+        "ScaleUnit": "1GHz"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))",
-        "MetricGroup": "Flops;InsType",
-        "MetricName": "IpArith",
-        "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
+        "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)",
+        "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 7.111111111111111 / 1e6 / duration_time",
+        "MetricName": "upi_data_transmit_bw",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
-        "MetricGroup": "Flops;FpScalar;InsType",
-        "MetricName": "IpArith_Scalar_SP",
-        "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "DDR memory read bandwidth (MB/sec)",
+        "MetricExpr": "UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time",
+        "MetricName": "memory_bandwidth_read",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
-        "MetricGroup": "Flops;FpScalar;InsType",
-        "MetricName": "IpArith_Scalar_DP",
-        "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "DDR memory write bandwidth (MB/sec)",
+        "MetricExpr": "UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time",
+        "MetricName": "memory_bandwidth_write",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)",
-        "MetricGroup": "Flops;FpVector;InsType",
-        "MetricName": "IpArith_AVX128",
-        "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "DDR memory bandwidth (MB/sec)",
+        "MetricExpr": "(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time",
+        "MetricName": "memory_bandwidth_total",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
-        "MetricGroup": "Flops;FpVector;InsType",
-        "MetricName": "IpArith_AVX256",
-        "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)",
+        "MetricExpr": "UNC_M_PMM_RPQ_INSERTS * 64 / 1e6 / duration_time",
+        "MetricName": "pmem_memory_bandwidth_read",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
-        "MetricGroup": "Flops;FpVector;InsType",
-        "MetricName": "IpArith_AVX512",
-        "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)",
+        "MetricExpr": "UNC_M_PMM_WPQ_INSERTS * 64 / 1e6 / duration_time",
+        "MetricName": "pmem_memory_bandwidth_write",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@",
-        "MetricGroup": "Prefetches",
-        "MetricName": "IpSWPF"
+        "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)",
+        "MetricExpr": "(UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS) * 64 / 1e6 / duration_time",
+        "MetricName": "pmem_memory_bandwidth_total",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
-        "MetricExpr": "INST_RETIRED.ANY",
-        "MetricGroup": "Summary;tma_L1_group",
-        "MetricName": "Instructions"
+        "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
+        "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1e6 / duration_time",
+        "MetricName": "io_bandwidth_disk_or_network_writes",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
-        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
-        "MetricGroup": "Pipeline;Ret",
-        "MetricName": "Retire"
+        "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
+        "MetricExpr": "(UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3) * 4 / 1e6 / duration_time",
+        "MetricName": "io_bandwidth_disk_or_network_reads",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
-        "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
-        "MetricName": "Execute"
+        "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
+        "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+        "MetricName": "percent_uops_delivered_from_decoded_icache",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average number of Uops issued by front-end when it issued something",
-        "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@",
-        "MetricGroup": "Fed;FetchBW",
-        "MetricName": "Fetch_UpC"
+        "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
+        "MetricExpr": "IDQ.MITE_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+        "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
-        "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
-        "MetricGroup": "DSB;Fed;FetchBW",
-        "MetricName": "DSB_Coverage"
+        "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
+        "MetricExpr": "IDQ.MS_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+        "MetricName": "percent_uops_delivered_from_microcode_sequencer",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
-        "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHES.COUNT",
-        "MetricGroup": "DSBmiss",
-        "MetricName": "DSB_Switch_Cost"
+        "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.",
+        "MetricExpr": "UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1e6 / duration_time",
+        "MetricName": "llc_miss_local_memory_bandwidth_read",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
-        "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))",
-        "MetricGroup": "DSBmiss;Fed",
-        "MetricName": "DSB_Misses"
+        "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.",
+        "MetricExpr": "UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1e6 / duration_time",
+        "MetricName": "llc_miss_local_memory_bandwidth_write",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS",
-        "MetricGroup": "DSBmiss;Fed",
-        "MetricName": "IpDSB_Miss_Ret"
+        "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.",
+        "MetricExpr": "UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1e6 / duration_time",
+        "MetricName": "llc_miss_remote_memory_bandwidth_read",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;BadSpec;BrMispredicts",
-        "MetricName": "IpMispredict"
+        "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
+        "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS",
+        "MetricGroup": "PGO;TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_frontend_bound",
+        "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
-        "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;BrMispredicts",
-        "MetricName": "Branch_Misprediction_Cost"
+        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
+        "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS",
+        "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+        "MetricName": "tma_fetch_latency",
+        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of branches that are non-taken conditionals",
-        "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;Branches;CodeGen;PGO",
-        "MetricName": "Cond_NT"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.",
+        "MetricExpr": "(ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_icache_misses",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of branches that are taken conditionals",
-        "MetricExpr": "(BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) / BR_INST_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;Branches;CodeGen;PGO",
-        "MetricName": "Cond_TK"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.",
+        "MetricExpr": "ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_itlb_misses",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of branches that are CALL or RET",
-        "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;Branches",
-        "MetricName": "CallRet"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
+        "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + tma_unknown_branches",
+        "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_branch_resteers",
+        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps",
-        "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;Branches",
-        "MetricName": "Jump"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ",
+        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+        "MetricName": "tma_mispredicts_resteers",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
-        "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)",
-        "MetricGroup": "Mem;MemoryBound;MemoryLat",
-        "MetricName": "Load_Miss_Real_Latency"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ",
+        "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+        "MetricName": "tma_clears_resteers",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
-        "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
-        "MetricGroup": "Mem;MemoryBW;MemoryBound",
-        "MetricName": "MLP"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
+        "MetricExpr": "9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+        "MetricName": "tma_unknown_branches",
+        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L1MPKI"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
+        "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_dsb_switches",
+        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L1MPKI_Load"
+        "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
+        "MetricExpr": "ILD_STALL.LCP / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_lcp",
+        "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "Backend;CacheMisses;Mem",
-        "MetricName": "L2MPKI"
+        "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
+        "MetricExpr": "2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_ms_switches",
+        "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem;Offcore",
-        "MetricName": "L2MPKI_All"
+        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
+        "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
+        "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+        "MetricName": "tma_fetch_bandwidth",
+        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues.  For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L2MPKI_Load"
+        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
+        "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
+        "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+        "MetricName": "tma_mite",
+        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
-        "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L2HPKI_All"
+        "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder",
+        "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=0x1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=0x2@) / CORE_CLKS",
+        "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group",
+        "MetricName": "tma_decoder0_alone",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache hits per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L2HPKI_Load"
+        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
+        "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2",
+        "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+        "MetricName": "tma_dsb",
+        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline.  For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L3MPKI"
+        "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
+        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+        "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_bad_speculation",
+        "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "FB_HPKI"
+        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
+        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
+        "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+        "MetricName": "tma_branch_mispredicts",
+        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
-        "MetricConstraint": "NO_NMI_WATCHDOG",
-        "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING) / (2 * CORE_CLKS)",
-        "MetricGroup": "Mem;MemoryTLB",
-        "MetricName": "Page_Walks_Utilization"
+        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
+        "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
+        "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+        "MetricName": "tma_machine_clears",
+        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears.  These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
-        "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L1D_Cache_Fill_BW"
+        "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
+        "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+        "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_backend_bound",
+        "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
+        "ScaleUnit": "100%"
     },
-    {
-        "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
-        "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L2_Cache_Fill_BW"
+    {
+        "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
+        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + UOPS_RETIRED.RETIRE_SLOTS / SLOTS * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound",
+        "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+        "MetricName": "tma_memory_bound",
+        "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L3_Cache_Fill_BW"
+        "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
+        "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CPU_CLK_UNHALTED.THREAD, 0)",
+        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_l1_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache.  The L1 data cache typically has the shortest latency.  However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time",
-        "MetricGroup": "Mem;MemoryBW;Offcore",
-        "MetricName": "L3_Cache_Access_BW"
+        "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
+        "MetricExpr": "min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_dtlb_load",
+        "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
-        "MetricExpr": "1000 * L2_LINES_OUT.SILENT / Instructions",
-        "MetricGroup": "L2Evicts;Mem;Server",
-        "MetricName": "L2_Evictions_Silent_PKI"
+        "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
+        "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
+        "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group",
+        "MetricName": "tma_load_stlb_hit",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
-        "MetricExpr": "1000 * L2_LINES_OUT.NON_SILENT / Instructions",
-        "MetricGroup": "L2Evicts;Mem;Server",
-        "MetricName": "L2_Evictions_NonSilent_PKI"
+        "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk",
+        "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group",
+        "MetricName": "tma_load_stlb_miss",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
-        "MetricExpr": "L1D_Cache_Fill_BW",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L1D_Cache_Fill_BW_1T"
+        "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
+        "MetricExpr": "min(13 * LD_BLOCKS.STORE_FORWARD / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_store_fwd_blk",
+        "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
-        "MetricExpr": "L2_Cache_Fill_BW",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L2_Cache_Fill_BW_1T"
+        "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
+        "MetricExpr": "min((12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (11 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_lock_latency",
+        "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "L3_Cache_Fill_BW",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L3_Cache_Fill_BW_1T"
+        "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ",
+        "MetricExpr": "min(Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_split_loads",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "L3_Cache_Access_BW",
-        "MetricGroup": "Mem;MemoryBW;Offcore",
-        "MetricName": "L3_Cache_Access_BW_1T"
+        "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
+        "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_4k_aliasing",
+        "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average CPU Utilization",
-        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
-        "MetricGroup": "HPC;Summary",
-        "MetricName": "CPU_Utilization"
+        "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
+        "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_fb_full",
+        "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
-        "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
-        "MetricGroup": "Power;Summary",
-        "MetricName": "Average_Frequency"
+        "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
+        "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD)",
+        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_l2_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Giga Floating Point Operations Per Second",
-        "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1000000000) / duration_time",
-        "MetricGroup": "Cor;Flops;HPC",
-        "MetricName": "GFLOPs",
-        "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
+        "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
+        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_l3_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average Frequency Utilization relative nominal frequency",
-        "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
-        "MetricGroup": "Power",
-        "MetricName": "Turbo_Utilization"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
+        "MetricExpr": "min(((47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD))) + (47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_contested_accesses",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0",
-        "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL0_TURBO_LICENSE / CORE_CLKS",
-        "MetricGroup": "Power",
-        "MetricName": "Power_License0_Utilization",
-        "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes."
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
+        "MetricExpr": "min((47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_data_sharing",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1",
-        "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL1_TURBO_LICENSE / CORE_CLKS",
-        "MetricGroup": "Power",
-        "MetricName": "Power_License1_Utilization",
-        "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions."
+        "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
+        "MetricExpr": "min((20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_l3_hit_latency",
+        "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)",
-        "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL2_TURBO_LICENSE / CORE_CLKS",
-        "MetricGroup": "Power",
-        "MetricName": "Power_License2_Utilization",
-        "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX).  This includes high current AVX 512-bit instructions."
+        "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
+        "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
+        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_sq_full",
+        "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
-        "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
-        "MetricGroup": "SMT",
-        "MetricName": "SMT_2T_Utilization"
+        "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
+        "MetricExpr": "min(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound - min(((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0), 1), 1)",
+        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_dram_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
-        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
-        "MetricGroup": "OS",
-        "MetricName": "Kernel_Utilization"
+        "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
+        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+        "MetricName": "tma_mem_bandwidth",
+        "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM).  The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
-        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
-        "MetricGroup": "OS",
-        "MetricName": "Kernel_CPI"
+        "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
+        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CPU_CLK_UNHALTED.THREAD - tma_mem_bandwidth",
+        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+        "MetricName": "tma_mem_latency",
+        "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM).  This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
-        "MetricExpr": "(64 * (uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@) / 1000000000) / duration_time",
-        "MetricGroup": "HPC;Mem;MemoryBW;SoC",
-        "MetricName": "DRAM_BW_Use"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
+        "MetricExpr": "min((80 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group",
+        "MetricName": "tma_local_dram",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
-        "MetricExpr": "1000000000 * (cha@event\\=0x36\\,umask\\=0x21\\,config\\=0x40433@ / cha@event\\=0x35\\,umask\\=0x21\\,config\\=0x40433@) / (Socket_CLKS / duration_time)",
-        "MetricGroup": "Mem;MemoryLat;SoC",
-        "MetricName": "MEM_Read_Latency"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
+        "MetricExpr": "min((147.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+        "MetricName": "tma_remote_dram",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
-        "MetricExpr": "cha@event\\=0x36\\,umask\\=0x21\\,config\\=0x40433@ / cha@event\\=0x36\\,umask\\=0x21\\,config\\=0x40433\\,thresh\\=1@",
-        "MetricGroup": "Mem;MemoryBW;SoC",
-        "MetricName": "MEM_Parallel_Reads"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
+        "MetricExpr": "min(((110 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + (110 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+        "MetricName": "tma_remote_cache",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
-        "MetricExpr": "(1000000000 * (imc@event\\=0xe0\\,umask\\=0x1@ / imc@event\\=0xe3@) / imc_0@event\\=0x0@)",
-        "MetricGroup": "Mem;MemoryLat;Server;SoC",
-        "MetricName": "MEM_PMM_Read_Latency"
+        "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a",
+        "MetricExpr": "min(((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0), 1)",
+        "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_pmm_bound",
+        "PublicDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
-        "MetricExpr": "1000000000 * (UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSERTS) / imc_0@event\\=0x0@",
-        "MetricGroup": "Mem;MemoryLat;Server;SoC",
-        "MetricName": "MEM_DRAM_Read_Latency"
+        "BriefDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
+        "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_store_bound",
+        "PublicDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]",
-        "MetricExpr": "((64 * imc@event\\=0xe3@ / 1000000000) / duration_time)",
-        "MetricGroup": "Mem;MemoryBW;Server;SoC",
-        "MetricName": "PMM_Read_BW"
+        "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
+        "MetricExpr": "(L2_RQSTS.RFO_HIT * 11 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_store_latency",
+        "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]",
-        "MetricExpr": "((64 * imc@event\\=0xe7@ / 1000000000) / duration_time)",
-        "MetricGroup": "Mem;MemoryBW;Server;SoC",
-        "MetricName": "PMM_Write_BW"
+        "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
+        "MetricExpr": "min((110 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) * (OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM + OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM) + 47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) * (OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE)) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_false_sharing",
+        "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]",
-        "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1000000000 / duration_time",
-        "MetricGroup": "IoBW;Mem;Server;SoC",
-        "MetricName": "IO_Write_BW"
+        "BriefDescription": "This metric represents rate of split store accesses",
+        "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CORE_CLKS",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_split_stores",
+        "PublicDescription": "This metric represents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granularity.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]",
-        "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3) * 4 / 1000000000 / duration_time",
-        "MetricGroup": "IoBW;Mem;Server;SoC",
-        "MetricName": "IO_Read_BW"
+        "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
+        "MetricExpr": "min((9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CORE_CLKS, 1)",
+        "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_dtlb_store",
+        "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead.  Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page.  Try using larger page sizes for large amounts of frequently-used data.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Socket actual clocks when any core is active on that socket",
-        "MetricExpr": "cha_0@event\\=0x0@",
-        "MetricGroup": "SoC",
-        "MetricName": "Socket_CLKS"
+        "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
+        "MetricExpr": "tma_dtlb_store - DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS",
+        "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group",
+        "MetricName": "tma_store_stlb_hit",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
-        "MetricGroup": "Branches;OS",
-        "MetricName": "IpFarBranch"
+        "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk",
+        "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS",
+        "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group",
+        "MetricName": "tma_store_stlb_miss",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C3 residency percent per core",
-        "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C3_Core_Residency"
+        "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
+        "MetricExpr": "tma_backend_bound - tma_memory_bound",
+        "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+        "MetricName": "tma_core_bound",
+        "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C6 residency percent per core",
-        "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C6_Core_Residency"
+        "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
+        "MetricExpr": "ARITH.DIVIDER_ACTIVE / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group",
+        "MetricName": "tma_divider",
+        "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C7 residency percent per core",
-        "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C7_Core_Residency"
+        "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
+        "MetricExpr": "((EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + UOPS_RETIRED.RETIRE_SLOTS / SLOTS * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + UOPS_RETIRED.RETIRE_SLOTS / SLOTS * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD)",
+        "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group",
+        "MetricName": "tma_ports_utilization",
+        "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C2 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C2_Pkg_Residency"
+        "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+        "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_NONE / 2 if #SMT_on else CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CORE_CLKS",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_0",
+        "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C3 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C3_Pkg_Residency"
+        "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations",
+        "MetricExpr": "PARTIAL_RAT_STALLS.SCOREBOARD / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group",
+        "MetricName": "tma_serializing_operation",
+        "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C6 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C6_Pkg_Residency"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.",
+        "MetricExpr": "40 * ROB_MISC_EVENTS.PAUSE_INST / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group",
+        "MetricName": "tma_slow_pause",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C7 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C7_Pkg_Residency"
+        "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued",
+        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY, 1)",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group",
+        "MetricName": "tma_mixing_vectors",
+        "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uncore frequency per die [GHZ]",
-        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000",
-        "MetricGroup": "SoC",
-        "MetricName": "UNCORE_FREQ"
+        "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+        "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2) / 2 if #SMT_on else EXE_ACTIVITY.1_PORTS_UTIL) / CORE_CLKS",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_1",
+        "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "CPU operating frequency (in GHz)",
-        "MetricExpr": "(( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ ) / 1000000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "cpu_operating_frequency",
-        "ScaleUnit": "1GHz"
+        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+        "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3) / 2 if #SMT_on else EXE_ACTIVITY.2_PORTS_UTIL) / CORE_CLKS",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_2",
+        "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
-        "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "loads_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
+        "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_3) / CORE_CLKS",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_3m",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
-        "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "stores_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
+        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+        "MetricName": "tma_alu_op_utilization",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l1d_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS",
+        "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+        "MetricName": "tma_port_0",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ",
-        "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l1d_demand_data_read_hits_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+        "MetricName": "tma_port_1",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
-        "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+        "MetricName": "tma_port_5",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ",
-        "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_demand_data_read_hits_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+        "MetricName": "tma_port_6",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations",
+        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+        "MetricName": "tma_load_op_utilization",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
-        "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_demand_data_read_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group",
+        "MetricName": "tma_port_2",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
-        "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_demand_code_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group",
+        "MetricName": "tma_port_3",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x12D4043300000000@ / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+        "MetricName": "tma_store_op_utilization",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x12CC023300000000@ / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)",
+        "MetricExpr": "tma_store_op_utilization",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group",
+        "MetricName": "tma_port_4",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds",
-        "MetricExpr": "( 1000000000 * ( cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043300000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043300000000@ ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_CLOCKTICKS) * #num_packages ) ) ) * duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency",
-        "ScaleUnit": "1ns"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group",
+        "MetricName": "tma_port_7",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds",
-        "MetricExpr": "( 1000000000 * ( cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043200000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_CLOCKTICKS) * #num_packages ) ) ) * duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests",
-        "ScaleUnit": "1ns"
+        "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS",
+        "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_retiring",
+        "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds",
-        "MetricExpr": "( 1000000000 * ( cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043100000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@ ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_CLOCKTICKS) * #num_packages ) ) ) * duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests",
-        "ScaleUnit": "1ns"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
+        "MetricExpr": "tma_retiring - (UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / SLOTS",
+        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+        "MetricName": "tma_light_operations",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
-        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "itlb_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
+        "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD + tma_fp_scalar + tma_fp_vector",
+        "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_fp_arith",
+        "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
-        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "itlb_large_page_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
+        "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD",
+        "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group",
+        "MetricName": "tma_x87_use",
+        "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
-        "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "dtlb_load_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / UOPS_RETIRED.RETIRE_SLOTS",
+        "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group",
+        "MetricName": "tma_fp_scalar",
+        "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.",
-        "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "dtlb_2mb_large_page_load_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
+        "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)",
+        "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group",
+        "MetricName": "tma_fp_vector",
+        "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
-        "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "dtlb_store_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
+        "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)",
+        "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+        "MetricName": "tma_fp_vector_128b",
+        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
-        "MetricExpr": "100 * cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ / ( cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@ )",
-        "MetricGroup": "",
-        "MetricName": "numa_reads_addressed_to_local_dram",
-        "ScaleUnit": "1%"
+        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
+        "MetricExpr": "min((FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)",
+        "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+        "MetricName": "tma_fp_vector_256b",
+        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
-        "MetricExpr": "100 * cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@ / ( cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@ )",
-        "MetricGroup": "",
-        "MetricName": "numa_reads_addressed_to_remote_dram",
-        "ScaleUnit": "1%"
+        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
+        "MetricExpr": "min((FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)",
+        "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+        "MetricName": "tma_fp_vector_512b",
+        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uncore operating frequency in GHz",
-        "MetricExpr": "( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_CLOCKTICKS) * #num_packages ) / 1000000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "uncore_frequency",
-        "ScaleUnit": "1GHz"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.",
+        "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY",
+        "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_memory_operations",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_UPI_TxL_FLITS.ALL_DATA * (64 / 9.0) / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "upi_data_transmit_bw",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions",
+        "MetricExpr": "tma_light_operations * UOPS_RETIRED.MACRO_FUSED / UOPS_RETIRED.RETIRE_SLOTS",
+        "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_fused_instructions",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "DDR memory read bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "memory_bandwidth_read",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused",
+        "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS",
+        "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_non_fused_branches",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "DDR memory write bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "memory_bandwidth_write",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions",
+        "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / UOPS_RETIRED.RETIRE_SLOTS",
+        "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_nop_instructions",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "DDR memory bandwidth (MB/sec)",
-        "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "memory_bandwidth_total",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting",
+        "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions))",
+        "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_other_light_ops",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_M_PMM_RPQ_INSERTS * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "pmem_memory_bandwidth_read",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
+        "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / SLOTS",
+        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+        "MetricName": "tma_heavy_operations",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_M_PMM_WPQ_INSERTS * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "pmem_memory_bandwidth_write",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops",
+        "MetricExpr": "tma_heavy_operations - UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
+        "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group",
+        "MetricName": "tma_few_uops_instructions",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)",
-        "MetricExpr": "(( UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS ) * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "pmem_memory_bandwidth_total",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
+        "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group",
+        "MetricName": "tma_microcode_sequencer",
+        "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
-        "MetricExpr": "(( UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 ) * 4 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "io_bandwidth_disk_or_network_writes",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
+        "MetricExpr": "min(100 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / SLOTS, 1)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+        "MetricName": "tma_assists",
+        "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
-        "MetricExpr": "(( UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3 ) * 4 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "io_bandwidth_disk_or_network_reads",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
+        "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+        "MetricName": "tma_cisc",
+        "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
-        "MetricExpr": "100 * ( IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )",
-        "MetricGroup": "",
-        "MetricName": "percent_uops_delivered_from_decoded_icache",
-        "ScaleUnit": "1%"
+        "BriefDescription": "C3 residency percent per core",
+        "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C3_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
-        "MetricExpr": "100 * ( IDQ.MITE_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )",
-        "MetricGroup": "",
-        "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
-        "ScaleUnit": "1%"
+        "BriefDescription": "C6 residency percent per core",
+        "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C6_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
-        "MetricExpr": "100 * ( IDQ.MS_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )",
-        "MetricGroup": "",
-        "MetricName": "percent_uops_delivered_from_microcode_sequencer",
-        "ScaleUnit": "1%"
+        "BriefDescription": "C7 residency percent per core",
+        "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C7_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.",
-        "MetricExpr": "( UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_miss_local_memory_bandwidth_read",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "C2 residency percent per package",
+        "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C2_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.",
-        "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_miss_local_memory_bandwidth_write",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "C3 residency percent per package",
+        "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C3_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.",
-        "MetricExpr": "( UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_miss_remote_memory_bandwidth_read",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "C6 residency percent per package",
+        "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C6_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit.  LSD typically does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be reached for small loops whose size (in terms of number of uops) does not suit well the LSD structure.",
-        "MetricExpr": "100 * ( ( LSD.CYCLES_ACTIVE - LSD.CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )",
-        "MetricGroup": "FetchBW;LSD;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
-        "MetricName": "tma_lsd",
-        "ScaleUnit": "1%"
+        "BriefDescription": "C7 residency percent per package",
+        "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C7_Pkg_Residency",
+        "ScaleUnit": "100%"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.json b/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.json
index 48bb1b38dde66..1f46e6b338565 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
         "PublicDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
         "PublicDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
         "PublicDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
         "PublicDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -41,8 +33,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
         "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.  The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -51,8 +41,6 @@
     },
     {
         "BriefDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
         "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -61,8 +49,6 @@
     },
     {
         "BriefDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
         "PublicDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -71,8 +57,6 @@
     },
     {
         "BriefDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
         "PublicDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -81,8 +65,6 @@
     },
     {
         "BriefDescription": "Intel AVX-512 computational 512-bit packed BFloat16 instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCF",
         "EventName": "FP_ARITH_INST_RETIRED2.128BIT_PACKED_BF16",
         "PublicDescription": "Counts once for each Intel AVX-512 computational 512-bit packed BFloat16 floating-point instruction retired. Applies to the ZMM based VDPBF16PS instruction.  Each count represents 64 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake.",
@@ -91,8 +73,6 @@
     },
     {
         "BriefDescription": "Intel AVX-512 computational 128-bit packed BFloat16 instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCF",
         "EventName": "FP_ARITH_INST_RETIRED2.256BIT_PACKED_BF16",
         "PublicDescription": "Counts once for each Intel AVX-512 computational 128-bit packed BFloat16 floating-point instruction retired. Applies to the XMM based VDPBF16PS instruction. Each count represents 16 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake.",
@@ -101,8 +81,6 @@
     },
     {
         "BriefDescription": "Intel AVX-512 computational 256-bit packed BFloat16 instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCF",
         "EventName": "FP_ARITH_INST_RETIRED2.512BIT_PACKED_BF16",
         "PublicDescription": "Counts once for each Intel AVX-512 computational 256-bit packed BFloat16 floating-point instruction retired. Applies to the YMM based VDPBF16PS instruction.  Each count represents 32 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake.",
@@ -111,8 +89,6 @@
     },
     {
         "BriefDescription": "Cycles with any input/output SSE or FP assist",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.ANY",
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json b/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json
index 8633ee406813a..13ccf50db43df 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xE6",
         "EventName": "BACLEARS.ANY",
         "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAB",
         "EventName": "DSB2MITE_SWITCHES.COUNT",
         "PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAB",
         "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
         "PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Retired Instructions who experienced DSB miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
         "MSRIndex": "0x3F7",
@@ -40,13 +32,10 @@
         "PEBS": "1",
         "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.DSB_MISS",
         "MSRIndex": "0x3F7",
@@ -54,13 +43,10 @@
         "PEBS": "1",
         "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.ITLB_MISS",
         "MSRIndex": "0x3F7",
@@ -68,39 +54,30 @@
         "PEBS": "1",
         "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.L1I_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x12",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.L2_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x13",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
         "MSRIndex": "0x3F7",
@@ -108,26 +85,20 @@
         "PEBS": "2",
         "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x408006",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
         "MSRIndex": "0x3F7",
@@ -135,39 +106,30 @@
         "PEBS": "1",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x400206",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x410006",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
         "MSRIndex": "0x3F7",
@@ -175,39 +137,30 @@
         "PEBS": "1",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x200206",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x300206",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
         "MSRIndex": "0x3F7",
@@ -215,52 +168,40 @@
         "PEBS": "1",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x400406",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x420006",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x404006",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
         "MSRIndex": "0x3F7",
@@ -268,13 +209,10 @@
         "PEBS": "1",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.STLB_MISS",
         "MSRIndex": "0x3F7",
@@ -282,13 +220,10 @@
         "PEBS": "1",
         "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE_16B.IFDATA_STALL",
         "PublicDescription": "Cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.",
@@ -297,8 +232,6 @@
     },
     {
         "BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x83",
         "EventName": "ICACHE_64B.IFTAG_HIT",
         "SampleAfterValue": "200003",
@@ -306,8 +239,6 @@
     },
     {
         "BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x83",
         "EventName": "ICACHE_64B.IFTAG_MISS",
         "SampleAfterValue": "200003",
@@ -315,8 +246,6 @@
     },
     {
         "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x83",
         "EventName": "ICACHE_64B.IFTAG_STALL",
         "SampleAfterValue": "200003",
@@ -324,8 +253,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -335,8 +262,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -346,8 +271,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering 4 Uops",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -357,8 +280,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering any Uop",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -368,8 +289,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_CYCLES",
@@ -379,8 +298,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_UOPS",
         "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.",
@@ -389,8 +306,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_CYCLES",
@@ -400,8 +315,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_UOPS",
         "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@@ -410,8 +323,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_CYCLES",
@@ -421,8 +332,6 @@
     },
     {
         "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_DSB_CYCLES",
@@ -432,8 +341,6 @@
     },
     {
         "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_MITE_UOPS",
         "PublicDescription": "Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.",
@@ -442,8 +349,6 @@
     },
     {
         "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
@@ -454,8 +359,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_UOPS",
         "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
@@ -464,8 +367,6 @@
     },
     {
         "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
         "PublicDescription": "Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4  x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions).  c. Instruction Decode Queue (IDQ) delivers four uops.",
@@ -474,8 +375,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -485,8 +384,6 @@
     },
     {
         "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@@ -496,8 +393,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@@ -507,8 +402,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@@ -518,8 +411,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/memory.json b/tools/perf/pmu-events/arch/x86/cascadelakex/memory.json
index 36042010d7682..a00ad0aaf1bad 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/memory.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "6",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.ABORTED",
         "PEBS": "1",
@@ -32,8 +26,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.ABORTED_EVENTS",
         "SampleAfterValue": "2000003",
@@ -41,8 +33,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.ABORTED_MEM",
         "SampleAfterValue": "2000003",
@@ -50,8 +40,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.ABORTED_MEMTYPE",
         "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.",
@@ -60,8 +48,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.ABORTED_TIMER",
         "SampleAfterValue": "2000003",
@@ -69,8 +55,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
         "SampleAfterValue": "2000003",
@@ -78,8 +62,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution successfully committed",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.COMMIT",
         "PublicDescription": "Number of times HLE commit succeeded.",
@@ -88,8 +70,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution started.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.START",
         "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.",
@@ -98,8 +78,6 @@
     },
     {
         "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL089",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
@@ -109,8 +87,6 @@
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
@@ -119,13 +95,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "1009",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
@@ -134,13 +107,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "20011",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
@@ -149,13 +119,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "503",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
@@ -164,13 +131,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
@@ -179,13 +143,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "100003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
@@ -194,13 +155,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "101",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
@@ -209,13 +167,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "2003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
@@ -224,4213 +179,3160 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "50021",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP  OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP  OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP  OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP  OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS.ANY_SNOOP OCR.ALL_READS.L3_MISS.ANY_SNOOP OCR.ALL_READS.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC0007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C0007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C0007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C0007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C0007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS.REMOTE_HITM OCR.ALL_READS.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS.SNOOP_MISS OCR.ALL_READS.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C0007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS.SNOOP_NONE OCR.ALL_READS.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC0007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP  OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F840007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE  OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10040007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8040007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4040007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1040007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2040007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x6040007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x840007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B8007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP  OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F900007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE  OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10100007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8100007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4100007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1100007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2100007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x900007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS.ANY_SNOOP OCR.ALL_RFO.L3_MISS.ANY_SNOOP OCR.ALL_RFO.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS.REMOTE_HITM OCR.ALL_RFO.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS.SNOOP_MISS OCR.ALL_RFO.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS.SNOOP_NONE OCR.ALL_RFO.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP  OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE  OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP  OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE  OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.ANY_SNOOP OCR.OTHER.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.HITM_OTHER_CORE OCR.OTHER.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC08000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC08000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B808000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Demand Data Read requests who miss L3 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
         "PublicDescription": "Demand Data Read requests who miss L3 cache.",
@@ -4439,8 +3341,6 @@
     },
     {
         "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
@@ -4449,8 +3349,6 @@
     },
     {
         "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
         "SampleAfterValue": "2000003",
@@ -4458,8 +3356,6 @@
     },
     {
         "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "6",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
@@ -4468,4558 +3364,3506 @@
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC0007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C0007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C0007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C0007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C0007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C0007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC0007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F840007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10040007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8040007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4040007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1040007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2040007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x6040007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x840007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B8007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F900007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10100007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8100007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4100007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1100007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2100007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x900007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC08000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC08000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B808000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83C000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F90000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.ABORTED",
         "PEBS": "1",
@@ -9029,8 +6873,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.ABORTED_EVENTS",
         "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
@@ -9039,8 +6881,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.ABORTED_MEM",
         "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
@@ -9049,8 +6889,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
         "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.",
@@ -9059,8 +6897,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.ABORTED_TIMER",
         "SampleAfterValue": "2000003",
@@ -9068,8 +6904,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
         "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.",
@@ -9078,8 +6912,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution successfully committed",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.COMMIT",
         "PublicDescription": "Number of times RTM commit succeeded.",
@@ -9088,8 +6920,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution started.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.START",
         "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.",
@@ -9098,8 +6928,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC1",
         "SampleAfterValue": "2000003",
@@ -9107,8 +6935,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC2",
         "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
@@ -9117,8 +6943,6 @@
     },
     {
         "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC3",
         "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
@@ -9127,8 +6951,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC4",
         "PublicDescription": "RTM region detected inside HLE.",
@@ -9137,8 +6959,6 @@
     },
     {
         "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC5",
         "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
@@ -9147,8 +6967,6 @@
     },
     {
         "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CAPACITY",
         "SampleAfterValue": "2000003",
@@ -9156,8 +6974,6 @@
     },
     {
         "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CONFLICT",
         "PublicDescription": "Number of times a TSX line had a cache conflict.",
@@ -9166,8 +6982,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
         "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
@@ -9176,8 +6990,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
         "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
@@ -9186,8 +6998,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
         "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
@@ -9196,8 +7006,6 @@
     },
     {
         "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
         "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
@@ -9206,8 +7014,6 @@
     },
     {
         "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
         "PublicDescription": "Number of times we could not allocate Lock Buffer.",
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/other.json b/tools/perf/pmu-events/arch/x86/cascadelakex/other.json
index 6baa338e72f1a..3ab5e91a4c1c7 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/other.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/other.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
         "PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
         "PublicDescription": "Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
         "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture).  This includes high current AVX 512-bit instructions.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Core cycles the core was throttled due to a pending power level request.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "CORE_POWER.THROTTLE",
         "PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.",
@@ -41,8 +33,6 @@
     },
     {
         "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDFE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xEF",
         "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE",
         "SampleAfterValue": "2000003",
@@ -50,8 +40,6 @@
     },
     {
         "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xEF",
         "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM",
         "SampleAfterValue": "2000003",
@@ -59,8 +47,6 @@
     },
     {
         "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITFSE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xEF",
         "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE",
         "SampleAfterValue": "2000003",
@@ -68,8 +54,6 @@
     },
     {
         "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITI",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xEF",
         "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI",
         "SampleAfterValue": "2000003",
@@ -77,8 +61,6 @@
     },
     {
         "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDFE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xEF",
         "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE",
         "SampleAfterValue": "2000003",
@@ -86,8 +68,6 @@
     },
     {
         "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xEF",
         "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM",
         "SampleAfterValue": "2000003",
@@ -95,8 +75,6 @@
     },
     {
         "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SHITFSE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xEF",
         "EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE",
         "SampleAfterValue": "2000003",
@@ -104,8 +82,6 @@
     },
     {
         "BriefDescription": "Number of hardware interrupts received by the processor.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCB",
         "EventName": "HW_INTERRUPTS.RECEIVED",
         "PublicDescription": "Counts the number of hardware interruptions received by the processor.",
@@ -114,8 +90,6 @@
     },
     {
         "BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xFE",
         "EventName": "IDI_MISC.WB_DOWNGRADE",
         "PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.",
@@ -124,8 +98,6 @@
     },
     {
         "BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xFE",
         "EventName": "IDI_MISC.WB_UPGRADE",
         "PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.",
@@ -134,1849 +106,1387 @@
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.ANY_RESPONSE have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP  OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE  OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP  OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.ANY_RESPONSE have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP  OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE  OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.ANY_RESPONSE have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x107F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F804007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP  OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F800207F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE  OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10000207F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD  OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8000207F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4000207F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED  OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000207F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000207F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800207F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.ANY_RESPONSE have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP  OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE  OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED  OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads  OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads  OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x18000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80028000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000028000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800028000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400028000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests  OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100028000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200028000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80028000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80400100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F80020100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800020100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     }
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json b/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json
index f085b9145952c..64e1fe3513331 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x14",
         "EventName": "ARITH.DIVIDER_ACTIVE",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "All (macro) branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "All (macro) branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
@@ -33,8 +27,6 @@
     },
     {
         "BriefDescription": "Conditional branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.CONDITIONAL",
@@ -45,8 +37,6 @@
     },
     {
         "BriefDescription": "Not taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.COND_NTAKEN",
@@ -56,8 +46,6 @@
     },
     {
         "BriefDescription": "Far branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.FAR_BRANCH",
@@ -68,8 +56,6 @@
     },
     {
         "BriefDescription": "Direct and indirect near call instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL",
@@ -80,8 +66,6 @@
     },
     {
         "BriefDescription": "Return instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_RETURN",
@@ -92,8 +76,6 @@
     },
     {
         "BriefDescription": "Taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
@@ -104,8 +86,6 @@
     },
     {
         "BriefDescription": "Not taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NOT_TAKEN",
@@ -115,8 +95,6 @@
     },
     {
         "BriefDescription": "All mispredicted macro branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch.  When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
@@ -124,8 +102,6 @@
     },
     {
         "BriefDescription": "Mispredicted macro branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
         "PEBS": "2",
@@ -135,8 +111,6 @@
     },
     {
         "BriefDescription": "Mispredicted conditional branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -146,8 +120,6 @@
     },
     {
         "BriefDescription": "Mispredicted direct and indirect near call instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -157,8 +129,6 @@
     },
     {
         "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
@@ -167,8 +137,6 @@
     },
     {
         "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.RET",
         "PEBS": "1",
@@ -178,8 +146,6 @@
     },
     {
         "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "25003",
@@ -187,8 +153,6 @@
     },
     {
         "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
         "SampleAfterValue": "25003",
@@ -197,8 +161,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
         "SampleAfterValue": "25003",
@@ -206,8 +168,6 @@
     },
     {
         "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "25003",
@@ -215,8 +175,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the core is not in halt state.",
-        "Counter": "Fixed counter 2",
-        "CounterHTOff": "Fixed counter 2",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
         "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
         "SampleAfterValue": "2000003",
@@ -224,8 +182,6 @@
     },
     {
         "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
         "SampleAfterValue": "25003",
@@ -234,8 +190,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
         "SampleAfterValue": "25003",
@@ -243,8 +197,6 @@
     },
     {
         "BriefDescription": "Counts when there is a transition from ring 1, 2 or 3 to ring 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x3C",
@@ -254,8 +206,6 @@
     },
     {
         "BriefDescription": "Core cycles when the thread is not in halt state",
-        "Counter": "Fixed counter 1",
-        "CounterHTOff": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD",
         "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
         "SampleAfterValue": "2000003",
@@ -264,16 +214,12 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
-        "Counter": "Fixed counter 1",
-        "CounterHTOff": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Thread cycles when thread is not in halt state",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
         "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
@@ -282,16 +228,12 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "8",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
@@ -300,8 +242,6 @@
     },
     {
         "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
@@ -310,8 +250,6 @@
     },
     {
         "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "16",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
@@ -320,8 +258,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "12",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
@@ -330,8 +266,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "5",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
@@ -340,8 +274,6 @@
     },
     {
         "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "20",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
@@ -350,8 +282,6 @@
     },
     {
         "BriefDescription": "Total execution stalls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
@@ -360,8 +290,6 @@
     },
     {
         "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA6",
         "EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
         "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
@@ -370,8 +298,6 @@
     },
     {
         "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA6",
         "EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
         "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
@@ -380,8 +306,6 @@
     },
     {
         "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA6",
         "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
         "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
@@ -390,8 +314,6 @@
     },
     {
         "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA6",
         "EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
         "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
@@ -400,8 +322,6 @@
     },
     {
         "BriefDescription": "Cycles where the Store Buffer was full and no outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA6",
         "EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
         "SampleAfterValue": "2000003",
@@ -409,8 +329,6 @@
     },
     {
         "BriefDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA6",
         "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS",
         "PublicDescription": "Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty.",
@@ -419,8 +337,6 @@
     },
     {
         "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.LCP",
         "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
@@ -429,8 +345,6 @@
     },
     {
         "BriefDescription": "Instruction decoders utilized in a cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x55",
         "EventName": "INST_DECODED.DECODERS",
         "PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
@@ -439,8 +353,6 @@
     },
     {
         "BriefDescription": "Instructions retired from execution.",
-        "Counter": "Fixed counter 0",
-        "CounterHTOff": "Fixed counter 0",
         "EventName": "INST_RETIRED.ANY",
         "PublicDescription": "Counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
         "SampleAfterValue": "2000003",
@@ -448,8 +360,6 @@
     },
     {
         "BriefDescription": "Number of instructions retired. General Counter - architectural event",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091, SKL044",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.ANY_P",
@@ -458,8 +368,6 @@
     },
     {
         "BriefDescription": "Number of all retired NOP instructions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091, SKL044",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.NOP",
@@ -469,8 +377,6 @@
     },
     {
         "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
-        "Counter": "1",
-        "CounterHTOff": "1",
         "Errata": "SKL091, SKL044",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.PREC_DIST",
@@ -481,8 +387,6 @@
     },
     {
         "BriefDescription": "Number of cycles using always true condition applied to  PEBS instructions retired event.",
-        "Counter": "0,2,3",
-        "CounterHTOff": "0,2,3",
         "CounterMask": "10",
         "Errata": "SKL091, SKL044",
         "EventCode": "0xC0",
@@ -495,8 +399,6 @@
     },
     {
         "BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
         "SampleAfterValue": "2000003",
@@ -504,8 +406,6 @@
     },
     {
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES",
         "PublicDescription": "Core cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
@@ -515,8 +415,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
         "SampleAfterValue": "2000003",
@@ -524,8 +422,6 @@
     },
     {
         "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.NO_SR",
         "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
@@ -534,8 +430,6 @@
     },
     {
         "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.STORE_FORWARD",
         "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
@@ -544,8 +438,6 @@
     },
     {
         "BriefDescription": "False dependencies in MOB due to partial compare on address.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x07",
         "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
         "PublicDescription": "Counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",
@@ -554,8 +446,6 @@
     },
     {
         "BriefDescription": "Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4C",
         "EventName": "LOAD_HIT_PRE.SW_PF",
         "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
@@ -564,8 +454,6 @@
     },
     {
         "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_4_UOPS",
@@ -575,8 +463,6 @@
     },
     {
         "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_ACTIVE",
@@ -586,8 +472,6 @@
     },
     {
         "BriefDescription": "Number of Uops delivered by the LSD.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA8",
         "EventName": "LSD.UOPS",
         "PublicDescription": "Number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
@@ -596,8 +480,6 @@
     },
     {
         "BriefDescription": "Number of machine clears (nukes) of any type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xC3",
@@ -607,8 +489,6 @@
     },
     {
         "BriefDescription": "Self-modifying code (SMC) detected.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.SMC",
         "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
@@ -617,8 +497,6 @@
     },
     {
         "BriefDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.ANY",
         "SampleAfterValue": "100003",
@@ -626,8 +504,6 @@
     },
     {
         "BriefDescription": "Cycles where the pipeline is stalled due to serializing operations.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x59",
         "EventName": "PARTIAL_RAT_STALLS.SCOREBOARD",
         "PublicDescription": "This event counts cycles during which the microcode scoreboard stalls happen.",
@@ -636,8 +512,6 @@
     },
     {
         "BriefDescription": "Resource-related stall cycles",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa2",
         "EventName": "RESOURCE_STALLS.ANY",
         "PublicDescription": "Counts resource-related stall cycles.",
@@ -646,8 +520,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.SB",
         "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
@@ -656,8 +528,6 @@
     },
     {
         "BriefDescription": "Increments whenever there is an update to the LBR array.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCC",
         "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
         "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.",
@@ -666,8 +536,6 @@
     },
     {
         "BriefDescription": "Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL products.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCC",
         "EventName": "ROB_MISC_EVENTS.PAUSE_INST",
         "SampleAfterValue": "2000003",
@@ -675,8 +543,6 @@
     },
     {
         "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5E",
         "EventName": "RS_EVENTS.EMPTY_CYCLES",
         "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
@@ -685,8 +551,6 @@
     },
     {
         "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5E",
@@ -698,8 +562,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_0",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.",
@@ -708,8 +570,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 1",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_1",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.",
@@ -718,8 +578,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_2",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 2.",
@@ -728,8 +586,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_3",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 3.",
@@ -738,8 +594,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 4",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_4",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 4.",
@@ -748,8 +602,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 5",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_5",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.",
@@ -758,8 +610,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 6",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_6",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
@@ -768,8 +618,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 7",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 7.",
@@ -778,8 +626,6 @@
     },
     {
         "BriefDescription": "Number of uops executed on the core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE",
         "PublicDescription": "Number of uops executed from any thread.",
@@ -788,8 +634,6 @@
     },
     {
         "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@@ -798,8 +642,6 @@
     },
     {
         "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@@ -808,8 +650,6 @@
     },
     {
         "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@@ -818,8 +658,6 @@
     },
     {
         "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@@ -828,8 +666,6 @@
     },
     {
         "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
@@ -839,8 +675,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
@@ -850,8 +684,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
@@ -861,8 +693,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
@@ -872,8 +702,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
@@ -883,8 +711,6 @@
     },
     {
         "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.STALL_CYCLES",
@@ -895,8 +721,6 @@
     },
     {
         "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.THREAD",
         "PublicDescription": "Number of uops to be executed per-thread each cycle.",
@@ -905,8 +729,6 @@
     },
     {
         "BriefDescription": "Counts the number of x87 uops dispatched.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.X87",
         "PublicDescription": "Counts the number of x87 uops executed.",
@@ -915,8 +737,6 @@
     },
     {
         "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.ANY",
         "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
@@ -925,8 +745,6 @@
     },
     {
         "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.SLOW_LEA",
         "SampleAfterValue": "2000003",
@@ -934,8 +752,6 @@
     },
     {
         "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -946,8 +762,6 @@
     },
     {
         "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
         "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.",
@@ -956,8 +770,6 @@
     },
     {
         "BriefDescription": "Number of macro-fused uops retired. (non precise)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.MACRO_FUSED",
         "PublicDescription": "Counts the number of macro-fused uops retired. (non precise)",
@@ -966,8 +778,6 @@
     },
     {
         "BriefDescription": "Retirement slots used.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
         "PublicDescription": "Counts the retirement slots used.",
@@ -976,8 +786,6 @@
     },
     {
         "BriefDescription": "Cycles without actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -988,8 +796,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 10 actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "16",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json
index 326b674045c68..70a2c0ff8dfde 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json
@@ -1,223 +1,270 @@
 [
+    {
+        "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
+        "EventCode": "0x4",
+        "EventName": "LLC_MISSES.MEM_READ",
+        "PerPkg": "1",
+        "PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per channel basis.  CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every read.  This event includes underfill reads due to partial write requests.  This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write)  is enabled or not.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x3",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
+        "EventCode": "0x4",
+        "EventName": "LLC_MISSES.MEM_WRITE",
+        "PerPkg": "1",
+        "PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory channel.  CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0xc",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "DRAM Activate Count; Activate due to Bypass",
+        "EventCode": "0x1",
+        "EventName": "UNC_M_ACT_COUNT.BYP",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+        "UMask": "0x8",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "DRAM Activate Count; Activate due to Read",
+        "EventCode": "0x1",
+        "EventName": "UNC_M_ACT_COUNT.RD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+        "UMask": "0x1",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "DRAM Page Activate commands sent due to a write request",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_M_ACT_COUNT.WR",
         "PerPkg": "1",
+        "PublicDescription": "Counts DRAM Page Activate commands sent on this channel due to a write request to the iMC (Memory Controller).  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS (Column Access Select) command.",
         "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "All DRAM Read CAS Commands issued (does not include underfills)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.RD_REG",
+        "BriefDescription": "ACT command issued by 2 cycle bypass",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M_BYP_CMDS.ACT",
         "PerPkg": "1",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Underfill Read CAS Commands issued",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
+        "BriefDescription": "CAS command issued by 2 cycle bypass",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M_BYP_CMDS.CAS",
         "PerPkg": "1",
         "UMask": "0x2",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "PRE command issued by 2 cycle bypass",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M_BYP_CMDS.PRE",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "All DRAM CAS Commands issued",
+        "EventCode": "0x4",
+        "EventName": "UNC_M_CAS_COUNT.ALL",
+        "PerPkg": "1",
+        "PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory channel.  CAS commands are issued to specify the address to read or write on DRAM, so this event increments for every read and write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.",
+        "UMask": "0xf",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "All DRAM Read CAS Commands issued (including underfills)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.RD",
         "PerPkg": "1",
+        "PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per channel basis.  CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every read.  This event includes underfill reads due to partial write requests.  This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write)  is enabled or not.",
         "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Read ISOCH Mode",
         "EventCode": "0x4",
-        "EventName": "LLC_MISSES.MEM_READ",
+        "EventName": "UNC_M_CAS_COUNT.RD_ISOCH",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x3",
+        "UMask": "0x40",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "All DRAM Read CAS Commands issued (does not include underfills)",
         "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.WR_WMM",
+        "EventName": "UNC_M_CAS_COUNT.RD_REG",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts CAS (Column Access Select) regular read commands issued to DRAM on a per channel basis.  CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every regular read.  This event only counts regular reads and does not includes underfill reads due to partial write requests.  This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write)  is enabled or not.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "All DRAM Write CAS commands issued",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in RMM",
         "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.WR",
+        "EventName": "UNC_M_CAS_COUNT.RD_RMM",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "DRAM Underfill Read CAS Commands issued",
         "EventCode": "0x4",
-        "EventName": "LLC_MISSES.MEM_WRITE",
+        "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0xC",
+        "PublicDescription": "Counts CAS (Column Access Select) underfill read commands issued to DRAM due to a partial write, on a per channel basis.  CAS commands are issued to specify the address to read or write on DRAM, and this command counts underfill reads.  Partial writes must be completed by first reading in the underfill from DRAM and then merging in the partial write data before writing the full line back to DRAM. This event will generally count about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ (due to a previous write request).",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "All DRAM CAS Commands issued",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in WMM",
         "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.ALL",
+        "EventName": "UNC_M_CAS_COUNT.RD_WMM",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Memory controller clock ticks",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_M_CLOCKTICKS",
+        "BriefDescription": "All DRAM Write CAS commands issued",
+        "EventCode": "0x4",
+        "EventName": "UNC_M_CAS_COUNT.WR",
         "PerPkg": "1",
+        "PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory channel.  CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode+C37",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x85",
-        "EventName": "UNC_M_POWER_CHANNEL_PPD",
-        "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.",
-        "MetricName": "power_channel_ppd %",
+        "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Write ISOCH Mode",
+        "EventCode": "0x4",
+        "EventName": "UNC_M_CAS_COUNT.WR_ISOCH",
         "PerPkg": "1",
+        "UMask": "0x80",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Cycles Memory is in self refresh power mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x43",
-        "EventName": "UNC_M_POWER_SELF_REFRESH",
-        "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100.",
-        "MetricName": "power_self_refresh %",
+        "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
+        "EventCode": "0x4",
+        "EventName": "UNC_M_CAS_COUNT.WR_RMM",
         "PerPkg": "1",
+        "PublicDescription": "Counts the total number of Opportunistic DRAM Write CAS commands issued on this channel while in Read-Major-Mode.",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Pre-charges due to page misses",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+        "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
+        "EventCode": "0x4",
+        "EventName": "UNC_M_CAS_COUNT.WR_WMM",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode.",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Pre-charge for reads",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_M_PRE_COUNT.RD",
+        "BriefDescription": "Memory controller clock ticks",
+        "EventName": "UNC_M_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts clockticks of the fixed frequency clock of the memory controller using one of the programmable counters.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Pending Queue Allocations",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x10",
-        "EventName": "UNC_M_RPQ_INSERTS",
+        "BriefDescription": "Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter",
+        "EventCode": "0xff",
+        "EventName": "UNC_M_CLOCKTICKS_F",
         "PerPkg": "1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_M_RPQ_OCCUPANCY",
+        "BriefDescription": "DRAM Precharge All Commands",
+        "EventCode": "0x6",
+        "EventName": "UNC_M_DRAM_PRE_ALL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that the precharge all command was sent.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "All hits to Near Memory(DRAM cache) in Memory Mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD3",
-        "EventName": "UNC_M_TAGCHK.HIT",
+        "BriefDescription": "ECC Correctable Errors",
+        "EventCode": "0x9",
+        "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of ECC errors detected and corrected by the iMC on this channel.  This counter is only useful with ECC DRAM devices.  This count will increment one time for each correction regardless of the number of bits corrected.  The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "All Clean line misses to Near Memory(DRAM cache) in Memory Mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD3",
-        "EventName": "UNC_M_TAGCHK.MISS_CLEAN",
+        "BriefDescription": "UNC_M_MAJMODE2.DRAM_CYC",
+        "EventCode": "0xED",
+        "EventName": "UNC_M_MAJMODE2.DRAM_CYC",
         "PerPkg": "1",
         "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "All dirty line misses to Near Memory(DRAM cache) in Memory Mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD3",
-        "EventName": "UNC_M_TAGCHK.MISS_DIRTY",
+        "BriefDescription": "UNC_M_MAJMODE2.DRAM_ENTER",
+        "EventCode": "0xED",
+        "EventName": "UNC_M_MAJMODE2.DRAM_ENTER",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Allocations",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_M_WPQ_INSERTS",
+        "BriefDescription": "UNC_M_MAJMODE2.PMM_CYC",
+        "EventCode": "0xED",
+        "EventName": "UNC_M_MAJMODE2.PMM_CYC",
         "PerPkg": "1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x81",
-        "EventName": "UNC_M_WPQ_OCCUPANCY",
+        "BriefDescription": "UNC_M_MAJMODE2.PMM_ENTER",
+        "EventCode": "0xED",
+        "EventName": "UNC_M_MAJMODE2.PMM_ENTER",
         "PerPkg": "1",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL",
+        "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
+        "EventCode": "0x7",
+        "EventName": "UNC_M_MAJOR_MODES.ISOCH",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group these two modes together so that we can use four counters to track each of the major modes at one time.  These major modes are used whenever there is an ISOCH txn in the memory controller.  In these mode, only ISOCH transactions are processed.",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Intel Optane DC persistent memory read latency (ns). Derived from unc_m_pmm_rpq_occupancy.all",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M_PMM_READ_LATENCY",
-        "MetricExpr": "UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS / UNC_M_CLOCKTICKS",
-        "MetricName": "UNC_M_PMM_READ_LATENCY",
+        "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
+        "EventCode": "0x7",
+        "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
         "PerPkg": "1",
-        "ScaleUnit": "6000000000ns",
+        "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode is used to drain starved underfill reads.  Regular reads and writes are blocked and only underfill reads will be processed.",
+        "UMask": "0x4",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
+        "EventCode": "0x7",
+        "EventName": "UNC_M_MAJOR_MODES.READ",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode is the default mode for the iMC, as reads are generally more critical to forward progress than writes.",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xE3",
-        "EventName": "UNC_M_PMM_RPQ_INSERTS",
+        "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
+        "EventCode": "0x7",
+        "EventName": "UNC_M_MAJOR_MODES.WRITE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is triggered when the WPQ hits high occupancy and causes writes to be higher priority than reads.  This can cause blips in the available read bandwidth in the system and temporarily increase read latencies in order to achieve better bus utilizations and higher bandwidth.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Intel Optane DC persistent memory bandwidth read (MB/sec). Derived from unc_m_pmm_rpq_inserts",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE3",
         "EventName": "UNC_M_PMM_BANDWIDTH.READ",
         "PerPkg": "1",
@@ -226,7 +273,6 @@
     },
     {
         "BriefDescription": "Intel Optane DC persistent memory bandwidth total (MB/sec). Derived from unc_m_pmm_rpq_inserts",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE3",
         "EventName": "UNC_M_PMM_BANDWIDTH.TOTAL",
         "MetricExpr": "UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS",
@@ -235,426 +281,544 @@
         "ScaleUnit": "6.103515625E-5MB/sec",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "Intel Optane DC persistent memory bandwidth write (MB/sec). Derived from unc_m_pmm_wpq_inserts",
+        "EventCode": "0xE7",
+        "EventName": "UNC_M_PMM_BANDWIDTH.WRITE",
+        "PerPkg": "1",
+        "ScaleUnit": "6.103515625E-5MB/sec",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "All commands for Intel Optane DC persistent memory",
-        "Counter": "0,1,2,3",
         "EventCode": "0xEA",
         "EventName": "UNC_M_PMM_CMD1.ALL",
         "PerPkg": "1",
         "UMask": "0x1",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "Misc Commands (error, flow ACKs)",
+        "EventCode": "0xEA",
+        "EventName": "UNC_M_PMM_CMD1.MISC",
+        "PerPkg": "1",
+        "UMask": "0x80",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Misc GNTs",
+        "EventCode": "0xEA",
+        "EventName": "UNC_M_PMM_CMD1.MISC_GNT",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "Regular reads(RPQ) commands for Intel Optane DC persistent memory",
-        "Counter": "0,1,2,3",
         "EventCode": "0xEA",
         "EventName": "UNC_M_PMM_CMD1.RD",
         "PerPkg": "1",
+        "PublicDescription": "All Reads - RPQ or Ufill",
         "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write commands for Intel Optane DC persistent memory",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RPQ GNTs",
         "EventCode": "0xEA",
-        "EventName": "UNC_M_PMM_CMD1.WR",
+        "EventName": "UNC_M_PMM_CMD1.RPQ_GNTS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Underfill read commands for Intel Optane DC persistent memory",
-        "Counter": "0,1,2,3",
         "EventCode": "0xEA",
         "EventName": "UNC_M_PMM_CMD1.UFILL_RD",
         "PerPkg": "1",
+        "PublicDescription": "Underfill reads",
         "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xE7",
-        "EventName": "UNC_M_PMM_WPQ_INSERTS",
+        "BriefDescription": "Underfill GNTs",
+        "EventCode": "0xEA",
+        "EventName": "UNC_M_PMM_CMD1.WPQ_GNTS",
         "PerPkg": "1",
+        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Intel Optane DC persistent memory bandwidth write (MB/sec). Derived from unc_m_pmm_wpq_inserts",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xE7",
-        "EventName": "UNC_M_PMM_BANDWIDTH.WRITE",
+        "BriefDescription": "Write commands for Intel Optane DC persistent memory",
+        "EventCode": "0xEA",
+        "EventName": "UNC_M_PMM_CMD1.WR",
         "PerPkg": "1",
-        "ScaleUnit": "6.103515625E-5MB/sec",
+        "PublicDescription": "Writes",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xE4",
-        "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL",
+        "BriefDescription": "Expected No data packet (ERID matched NDP encoding)",
+        "EventCode": "0xEB",
+        "EventName": "UNC_M_PMM_CMD2.NODATA_EXP",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Activate Count; Activate due to Read",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_M_ACT_COUNT.RD",
+        "BriefDescription": "Unexpected No data packet (ERID matched a Read, but data was a NDP)",
+        "EventCode": "0xEB",
+        "EventName": "UNC_M_PMM_CMD2.NODATA_UNEXP",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Opportunistic Reads",
+        "EventCode": "0xEB",
+        "EventName": "UNC_M_PMM_CMD2.OPP_RD",
         "PerPkg": "1",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Activate Count; Activate due to Bypass",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_M_ACT_COUNT.BYP",
+        "BriefDescription": "PMM ECC Errors",
+        "EventCode": "0xEB",
+        "EventName": "UNC_M_PMM_CMD2.PMM_ECC_ERROR",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "PMM ERID detectable parity error",
+        "EventCode": "0xEB",
+        "EventName": "UNC_M_PMM_CMD2.PMM_ERID_ERROR",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Read Requests - Slot 0",
+        "EventCode": "0xEB",
+        "EventName": "UNC_M_PMM_CMD2.REQS_SLOT0",
         "PerPkg": "1",
         "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "ACT command issued by 2 cycle bypass",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M_BYP_CMDS.ACT",
+        "BriefDescription": "Read Requests - Slot 1",
+        "EventCode": "0xEB",
+        "EventName": "UNC_M_PMM_CMD2.REQS_SLOT1",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "PMM Major Mode; Cycles PMM is in Partial Write Major Mode",
+        "EventCode": "0xEC",
+        "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_CYC",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "PMM Major Mode",
+        "EventCode": "0xEC",
+        "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_ENTER",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "PMM Major Mode",
+        "EventCode": "0xEC",
+        "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_EXIT",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "PMM Major Mode; Cycles PMM is in Read Major Mode",
+        "EventCode": "0xEC",
+        "EventName": "UNC_M_PMM_MAJMODE1.RD_CYC",
         "PerPkg": "1",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "CAS command issued by 2 cycle bypass",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M_BYP_CMDS.CAS",
+        "BriefDescription": "PMM Major Mode; Cycles PMM is in Write Major Mode",
+        "EventCode": "0xEC",
+        "EventName": "UNC_M_PMM_MAJMODE1.WR_CYC",
         "PerPkg": "1",
         "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PRE command issued by 2 cycle bypass",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M_BYP_CMDS.PRE",
+        "BriefDescription": "Intel Optane DC persistent memory read latency (ns). Derived from unc_m_pmm_rpq_occupancy.all",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M_PMM_READ_LATENCY",
+        "MetricExpr": "UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS / UNC_M_CLOCKTICKS",
+        "MetricName": "UNC_M_PMM_READ_LATENCY",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "ScaleUnit": "6000000000ns",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.WR_RMM",
+        "BriefDescription": "PMM Read Queue Cycles Full",
+        "EventCode": "0xE2",
+        "EventName": "UNC_M_PMM_RPQ_CYCLES_FULL",
         "PerPkg": "1",
-        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in WMM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.RD_WMM",
+        "BriefDescription": "PMM Read Queue Cycles Not Empty",
+        "EventCode": "0xE1",
+        "EventName": "UNC_M_PMM_RPQ_CYCLES_NE",
         "PerPkg": "1",
-        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in RMM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.RD_RMM",
+        "BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory",
+        "EventCode": "0xE3",
+        "EventName": "UNC_M_PMM_RPQ_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Read ISOCH Mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.RD_ISOCH",
+        "BriefDescription": "Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Write ISOCH Mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.WR_ISOCH",
+        "BriefDescription": "PMM Occupancy",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge All Commands",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6",
-        "EventName": "UNC_M_DRAM_PRE_ALL",
+        "BriefDescription": "PMM Write Queue Cycles Full",
+        "EventCode": "0xE6",
+        "EventName": "UNC_M_PMM_WPQ_CYCLES_FULL",
         "PerPkg": "1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "ECC Correctable Errors",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9",
-        "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
+        "BriefDescription": "PMM Write Queue Cycles Not Empty",
+        "EventCode": "0xE5",
+        "EventName": "UNC_M_PMM_WPQ_CYCLES_NE",
         "PerPkg": "1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x7",
-        "EventName": "UNC_M_MAJOR_MODES.READ",
+        "BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory",
+        "EventCode": "0xE7",
+        "EventName": "UNC_M_PMM_WPQ_INSERTS",
+        "PerPkg": "1",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory",
+        "EventCode": "0xE4",
+        "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL",
         "PerPkg": "1",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x7",
-        "EventName": "UNC_M_MAJOR_MODES.WRITE",
+        "BriefDescription": "PMM Occupancy",
+        "EventCode": "0xE4",
+        "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.CAS",
         "PerPkg": "1",
         "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x7",
-        "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
+        "BriefDescription": "PMM Occupancy",
+        "EventCode": "0xE4",
+        "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.PWR",
         "PerPkg": "1",
         "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x7",
-        "EventName": "UNC_M_MAJOR_MODES.ISOCH",
+        "BriefDescription": "UNC_M_PMM_WPQ_PCOMMIT",
+        "EventCode": "0xE8",
+        "EventName": "UNC_M_PMM_WPQ_PCOMMIT",
+        "PerPkg": "1",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "UNC_M_PMM_WPQ_PCOMMIT_CYC",
+        "EventCode": "0xE9",
+        "EventName": "UNC_M_PMM_WPQ_PCOMMIT_CYC",
         "PerPkg": "1",
-        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Channel DLLOFF Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x84",
         "EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode+C37",
+        "EventCode": "0x85",
+        "EventName": "UNC_M_POWER_CHANNEL_PPD",
+        "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100",
+        "MetricName": "power_channel_ppd",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles when all the ranks in the channel are in PPD (PreCharge Power Down) mode. If IBT (Input Buffer Terminators)=off is enabled, then this event counts the cycles in PPD mode. If IBT=off is not enabled, then this event counts the number of cycles when being in PPD mode could have been taken advantage of.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x4",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x8",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x10",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x20",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x40",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x80",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Critical Throttle Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x86",
         "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the iMC is in critical thermal throttling.  When this happens, all traffic is blocked.  This should be rare unless something bad is going on in the platform.  There is no filtering by rank for this event.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "UNC_M_POWER_PCU_THROTTLING",
-        "Counter": "0,1,2,3",
         "EventCode": "0x42",
         "EventName": "UNC_M_POWER_PCU_THROTTLING",
         "PerPkg": "1",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "Cycles Memory is in self refresh power mode",
+        "EventCode": "0x43",
+        "EventName": "UNC_M_POWER_SELF_REFRESH",
+        "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100",
+        "MetricName": "power_self_refresh",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the iMC (memory controller) is in self-refresh and has a clock. This happens in some ACPI CPU package C-states for the sleep levels. For example, the PCU (Power Control Unit) may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Intel? Dynamic Power Technology.  Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.; Thermal throttling is performed per DIMM.  We support 3 DIMMs per channel.  This ID allows us to filter by ID.",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x4",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x8",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x10",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x20",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x40",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x80",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Read Preemption Count; Read over Read Preemption",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts another read.",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Read Preemption Count; Read over Write Preemption",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts a write.",
         "UMask": "0x2",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
+        "EventCode": "0x2",
+        "EventName": "UNC_M_PRE_COUNT.BYP",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
+        "UMask": "0x10",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of the page close counter expiring.  This does not include implicit precharge commands sent in auto-precharge mode.",
         "UMask": "0x2",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "Pre-charges due to page misses",
+        "EventCode": "0x2",
+        "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of explicit DRAM Precharge commands sent on this channel as a result of a DRAM page miss. This does not include the implicit precharge commands sent with CAS commands in Auto-Precharge mode. This does not include Precharge commands sent as a result of a page close counter expiration.",
+        "UMask": "0x1",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Pre-charge for reads",
+        "EventCode": "0x2",
+        "EventName": "UNC_M_PRE_COUNT.RD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of explicit DRAM Precharge commands issued on a per channel basis due to a read, so as to close the previous DRAM page, before opening the requested page.",
+        "UMask": "0x4",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "Pre-charge for writes",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_M_PRE_COUNT.WR",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
         "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_M_PRE_COUNT.BYP",
+        "BriefDescription": "Read CAS issued with HIGH priority",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Read CAS issued with LOW priority",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA0",
         "EventName": "UNC_M_RD_CAS_PRIO.LOW",
         "PerPkg": "1",
@@ -663,7 +827,6 @@
     },
     {
         "BriefDescription": "Read CAS issued with MEDIUM priority",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA0",
         "EventName": "UNC_M_RD_CAS_PRIO.MED",
         "PerPkg": "1",
@@ -671,26 +834,23 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read CAS issued with HIGH priority",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
         "EventCode": "0xA0",
-        "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
+        "EventName": "UNC_M_RD_CAS_PRIO.PANIC",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M_RD_CAS_PRIO.PANIC",
+        "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK0",
         "PerPkg": "1",
@@ -698,7 +858,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK1",
         "PerPkg": "1",
@@ -706,143 +865,119 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK2",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK10",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK3",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK11",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK4",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK12",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK5",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK13",
         "PerPkg": "1",
-        "UMask": "0x5",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK6",
-        "PerPkg": "1",
-        "UMask": "0x6",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 14",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK7",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK14",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 15",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK8",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK15",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK9",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK2",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK3",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK4",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK5",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK6",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK14",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK7",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK15",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK8",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK9",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANKG0",
         "PerPkg": "1",
@@ -851,7 +986,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANKG1",
         "PerPkg": "1",
@@ -860,7 +994,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANKG2",
         "PerPkg": "1",
@@ -869,7 +1002,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANKG3",
         "PerPkg": "1",
@@ -877,160 +1009,142 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; All Banks",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK0",
+        "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS",
         "PerPkg": "1",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK1",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK0",
         "PerPkg": "1",
-        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK2",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK1",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 10",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK3",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK10",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 11",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK4",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK11",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 12",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK5",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK12",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 13",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK6",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK13",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 14",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK7",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK14",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 15",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK8",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK15",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 2",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK9",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK2",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 3",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK3",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 4",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK4",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 5",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK5",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 6",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK6",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 7",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK14",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK7",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 8",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK15",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK8",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 9",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK9",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANKG0",
         "PerPkg": "1",
@@ -1039,7 +1153,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANKG1",
         "PerPkg": "1",
@@ -1048,7 +1161,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANKG2",
         "PerPkg": "1",
@@ -1057,7 +1169,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANKG3",
         "PerPkg": "1",
@@ -1065,160 +1176,142 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 2; All Banks",
         "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK0",
+        "EventName": "UNC_M_RD_CAS_RANK2.ALLBANKS",
         "PerPkg": "1",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 0",
         "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK1",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK0",
         "PerPkg": "1",
-        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 1",
         "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK2",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK1",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 10",
         "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK3",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK10",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 11",
         "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK4",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK11",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 12",
         "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK5",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK12",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 13",
         "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK6",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK13",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 14",
         "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK7",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK14",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 15",
         "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK8",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK15",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 2",
         "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK9",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK2",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 3",
         "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK3",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 4",
         "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK4",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 5",
         "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK5",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 6",
         "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK6",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 7",
         "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK14",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK7",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 8",
         "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK15",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK8",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 9",
         "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.ALLBANKS",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK9",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_M_RD_CAS_RANK2.BANKG0",
         "PerPkg": "1",
@@ -1227,7 +1320,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_M_RD_CAS_RANK2.BANKG1",
         "PerPkg": "1",
@@ -1236,7 +1328,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_M_RD_CAS_RANK2.BANKG2",
         "PerPkg": "1",
@@ -1245,16 +1336,22 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_M_RD_CAS_RANK2.BANKG3",
         "PerPkg": "1",
         "UMask": "0x14",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "RD_CAS Access to Rank 3; All Banks",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M_RD_CAS_RANK3.ALLBANKS",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "RD_CAS Access to Rank 3; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_M_RD_CAS_RANK3.BANK0",
         "PerPkg": "1",
@@ -1262,7 +1359,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 3; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_M_RD_CAS_RANK3.BANK1",
         "PerPkg": "1",
@@ -1270,143 +1366,119 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank 10",
         "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANK2",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANK10",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank 11",
         "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANK3",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANK11",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANK4",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank 12",
         "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANK5",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANK12",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank 13",
         "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANK6",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANK13",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank 14",
         "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANK7",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANK14",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank 15",
         "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANK8",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANK15",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank 2",
         "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANK9",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANK2",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank 3",
         "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANK3",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank 4",
         "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANK4",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank 5",
         "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANK5",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank 6",
         "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANK6",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank 7",
         "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANK14",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANK7",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank 8",
         "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANK15",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANK8",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank 9",
         "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.ALLBANKS",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANK9",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_M_RD_CAS_RANK3.BANKG0",
         "PerPkg": "1",
@@ -1415,7 +1487,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_M_RD_CAS_RANK3.BANKG1",
         "PerPkg": "1",
@@ -1424,7 +1495,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_M_RD_CAS_RANK3.BANKG2",
         "PerPkg": "1",
@@ -1433,7 +1503,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_M_RD_CAS_RANK3.BANKG3",
         "PerPkg": "1",
@@ -1441,160 +1510,142 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; All Banks",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK0",
+        "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS",
         "PerPkg": "1",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 0",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK1",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK0",
         "PerPkg": "1",
-        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 1",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK2",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK1",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 10",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK3",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK10",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 11",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK4",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK11",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 12",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK5",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK12",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 13",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK6",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK13",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 14",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK7",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK14",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 15",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK8",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK15",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 2",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK9",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK2",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 3",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK3",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 4",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK4",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 5",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK5",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 6",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK6",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 7",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK14",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK7",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 8",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK15",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK8",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 9",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK9",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANKG0",
         "PerPkg": "1",
@@ -1603,7 +1654,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANKG1",
         "PerPkg": "1",
@@ -1612,7 +1662,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANKG2",
         "PerPkg": "1",
@@ -1621,7 +1670,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANKG3",
         "PerPkg": "1",
@@ -1629,160 +1677,142 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; All Banks",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK0",
+        "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS",
         "PerPkg": "1",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 0",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK1",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK0",
         "PerPkg": "1",
-        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 1",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK2",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK1",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 10",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK3",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK10",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 11",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK4",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK11",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 12",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK5",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK12",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 13",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK6",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK13",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 14",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK7",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK14",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 15",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK8",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK15",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 2",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK9",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK2",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 3",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK3",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 4",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK4",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 5",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK5",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 6",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK6",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 7",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK14",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK7",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 8",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK15",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK8",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 9",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK9",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANKG0",
         "PerPkg": "1",
@@ -1791,7 +1821,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANKG1",
         "PerPkg": "1",
@@ -1800,7 +1829,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANKG2",
         "PerPkg": "1",
@@ -1809,16 +1837,22 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANKG3",
         "PerPkg": "1",
         "UMask": "0x14",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "RD_CAS Access to Rank 6; All Banks",
+        "EventCode": "0xB6",
+        "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK0",
         "PerPkg": "1",
@@ -1826,7 +1860,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK1",
         "PerPkg": "1",
@@ -1834,143 +1867,119 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 10",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK2",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK3",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK10",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 11",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK4",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK11",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 12",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK5",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK12",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 13",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK6",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK13",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 14",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK7",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK14",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 15",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK8",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK15",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 2",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK9",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK2",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 3",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK3",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 4",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK4",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 5",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK5",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 6",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK6",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 7",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK14",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK7",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 8",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK15",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK8",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 9",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK9",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANKG0",
         "PerPkg": "1",
@@ -1979,7 +1988,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANKG1",
         "PerPkg": "1",
@@ -1988,7 +1996,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANKG2",
         "PerPkg": "1",
@@ -1997,7 +2004,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANKG3",
         "PerPkg": "1",
@@ -2005,160 +2011,142 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; All Banks",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK0",
+        "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS",
         "PerPkg": "1",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK1",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK0",
         "PerPkg": "1",
-        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 1",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK2",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK1",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 10",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK3",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK10",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK4",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK11",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK5",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK12",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK6",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK13",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK7",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK14",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK8",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK15",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 2",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK9",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK2",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 3",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK3",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 4",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK4",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 5",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK5",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 6",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK6",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 7",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK14",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK7",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 8",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK15",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK8",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 9",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK9",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANKG0",
         "PerPkg": "1",
@@ -2167,7 +2155,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANKG1",
         "PerPkg": "1",
@@ -2176,7 +2163,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANKG2",
         "PerPkg": "1",
@@ -2185,7 +2171,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANKG3",
         "PerPkg": "1",
@@ -2194,59 +2179,54 @@
     },
     {
         "BriefDescription": "Read Pending Queue Full Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_M_RPQ_CYCLES_FULL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the Read Pending Queue is full.  When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead.  We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM.  This event only tracks non-ISOC queue entries.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Read Pending Queue Not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0x11",
         "EventName": "UNC_M_RPQ_CYCLES_NE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Read Pending Queue is not empty.  This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Accesses; Read Accepts",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M_SB_ACCESSES.RD_ACCEPTS",
+        "BriefDescription": "Read Pending Queue Allocations",
+        "EventCode": "0x10",
+        "EventName": "UNC_M_RPQ_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of read requests allocated into the Read Pending Queue (RPQ).  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  The requests deallocate after the read CAS command has been issued to DRAM.  This event counts both Isochronous and non-Isochronous requests which were issued to the RPQ.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Accesses; Read Rejects",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M_SB_ACCESSES.RD_REJECTS",
+        "BriefDescription": "Read Pending Queue Occupancy",
+        "EventCode": "0x80",
+        "EventName": "UNC_M_RPQ_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of entries in the Read Pending Queue (RPQ) at each cycle.  This can then be used to calculate both the average occupancy of the queue (in conjunction with the number of cycles not empty) and the average latency in the queue (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate from the RPQ after the CAS command has been issued to memory.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Accesses; NM read completions",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Scoreboard Accesses; Write Accepts",
         "EventCode": "0xD2",
-        "EventName": "UNC_M_SB_ACCESSES.WR_ACCEPTS",
+        "EventName": "UNC_M_SB_ACCESSES.FM_RD_CMPS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0x40",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Accesses; NM write completions",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Scoreboard Accesses; Write Rejects",
         "EventCode": "0xD2",
-        "EventName": "UNC_M_SB_ACCESSES.WR_REJECTS",
+        "EventName": "UNC_M_SB_ACCESSES.FM_WR_CMPS",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0x80",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Scoreboard Accesses; FM read completions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "UNC_M_SB_ACCESSES.NM_RD_CMPS",
         "PerPkg": "1",
@@ -2255,7 +2235,6 @@
     },
     {
         "BriefDescription": "Scoreboard Accesses; FM write completions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "UNC_M_SB_ACCESSES.NM_WR_CMPS",
         "PerPkg": "1",
@@ -2263,26 +2242,39 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Accesses; Write Accepts",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Scoreboard Accesses; Read Accepts",
         "EventCode": "0xD2",
-        "EventName": "UNC_M_SB_ACCESSES.FM_RD_CMPS",
+        "EventName": "UNC_M_SB_ACCESSES.RD_ACCEPTS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Accesses; Write Rejects",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Scoreboard Accesses; Read Rejects",
         "EventCode": "0xD2",
-        "EventName": "UNC_M_SB_ACCESSES.FM_WR_CMPS",
+        "EventName": "UNC_M_SB_ACCESSES.RD_REJECTS",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x2",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Scoreboard Accesses; NM read completions",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M_SB_ACCESSES.WR_ACCEPTS",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Scoreboard Accesses; NM write completions",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M_SB_ACCESSES.WR_REJECTS",
+        "PerPkg": "1",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Alloc",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD9",
         "EventName": "UNC_M_SB_CANARY.ALLOC",
         "PerPkg": "1",
@@ -2291,7 +2283,6 @@
     },
     {
         "BriefDescription": "Dealloc",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD9",
         "EventName": "UNC_M_SB_CANARY.DEALLOC",
         "PerPkg": "1",
@@ -2299,26 +2290,23 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Reject",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Far Mem Read Starved",
         "EventCode": "0xD9",
-        "EventName": "UNC_M_SB_CANARY.REJ",
+        "EventName": "UNC_M_SB_CANARY.FMRD_STARVED",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0x40",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Valid",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Far Mem Write Starved",
         "EventCode": "0xD9",
-        "EventName": "UNC_M_SB_CANARY.VLD",
+        "EventName": "UNC_M_SB_CANARY.FMWR_STARVED",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0x80",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Near Mem Read Starved",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD9",
         "EventName": "UNC_M_SB_CANARY.NMRD_STARVED",
         "PerPkg": "1",
@@ -2327,7 +2315,6 @@
     },
     {
         "BriefDescription": "Near Mem Write Starved",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD9",
         "EventName": "UNC_M_SB_CANARY.NMWR_STARVED",
         "PerPkg": "1",
@@ -2335,26 +2322,23 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Far Mem Read Starved",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Reject",
         "EventCode": "0xD9",
-        "EventName": "UNC_M_SB_CANARY.FMRD_STARVED",
+        "EventName": "UNC_M_SB_CANARY.REJ",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Far Mem Write Starved",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Valid",
         "EventCode": "0xD9",
-        "EventName": "UNC_M_SB_CANARY.FMWR_STARVED",
+        "EventName": "UNC_M_SB_CANARY.VLD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Scoreboard Cycles Full",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "UNC_M_SB_CYCLES_FULL",
         "PerPkg": "1",
@@ -2362,87 +2346,77 @@
     },
     {
         "BriefDescription": "Scoreboard Cycles Not-Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "UNC_M_SB_CYCLES_NE",
         "PerPkg": "1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Inserts; Reads",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Scoreboard Inserts; Block region reads",
         "EventCode": "0xD6",
-        "EventName": "UNC_M_SB_INSERTS.RDS",
+        "EventName": "UNC_M_SB_INSERTS.BLOCK_RDS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Inserts; Writes",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Scoreboard Inserts; Block region writes",
         "EventCode": "0xD6",
-        "EventName": "UNC_M_SB_INSERTS.WRS",
+        "EventName": "UNC_M_SB_INSERTS.BLOCK_WRS",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Inserts; Block region reads",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Scoreboard Inserts; Dealloc all commands (for error flows)",
         "EventCode": "0xD6",
-        "EventName": "UNC_M_SB_INSERTS.BLOCK_RDS",
+        "EventName": "UNC_M_SB_INSERTS.DEALLOC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x40",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Inserts; Block region writes",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Scoreboard Inserts; Patrol inserts",
         "EventCode": "0xD6",
-        "EventName": "UNC_M_SB_INSERTS.BLOCK_WRS",
+        "EventName": "UNC_M_SB_INSERTS.PATROL",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x80",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Inserts; Dealloc all commands (for error flows)",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Scoreboard Inserts; Persistent Mem reads",
         "EventCode": "0xD6",
-        "EventName": "UNC_M_SB_INSERTS.DEALLOC",
+        "EventName": "UNC_M_SB_INSERTS.PMM_RDS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Inserts; Patrol inserts",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Scoreboard Inserts; Persistent Mem writes",
         "EventCode": "0xD6",
-        "EventName": "UNC_M_SB_INSERTS.PATROL",
+        "EventName": "UNC_M_SB_INSERTS.PMM_WRS",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Occupancy; Reads",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD5",
-        "EventName": "UNC_M_SB_OCCUPANCY.RDS",
+        "BriefDescription": "Scoreboard Inserts; Reads",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M_SB_INSERTS.RDS",
         "PerPkg": "1",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Occupancy; Writes",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD5",
-        "EventName": "UNC_M_SB_OCCUPANCY.WRS",
+        "BriefDescription": "Scoreboard Inserts; Writes",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M_SB_INSERTS.WRS",
         "PerPkg": "1",
         "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Scoreboard Occupancy; Block region reads",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD5",
         "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_RDS",
         "PerPkg": "1",
@@ -2451,7 +2425,6 @@
     },
     {
         "BriefDescription": "Scoreboard Occupancy; Block region writes",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD5",
         "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_WRS",
         "PerPkg": "1",
@@ -2460,7 +2433,6 @@
     },
     {
         "BriefDescription": "Scoreboard Occupancy; Patrol",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD5",
         "EventName": "UNC_M_SB_OCCUPANCY.PATROL",
         "PerPkg": "1",
@@ -2468,26 +2440,55 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Number of Scoreboard Requests Rejected; NM requests rejected due to set conflict",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M_SB_REJECT.NM_SET_CNFLT",
+        "BriefDescription": "Scoreboard Occupancy; Persistent Mem reads",
+        "EventCode": "0xD5",
+        "EventName": "UNC_M_SB_OCCUPANCY.PMM_RDS",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Scoreboard Occupancy; Persistent Mem writes",
+        "EventCode": "0xD5",
+        "EventName": "UNC_M_SB_OCCUPANCY.PMM_WRS",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Scoreboard Occupancy; Reads",
+        "EventCode": "0xD5",
+        "EventName": "UNC_M_SB_OCCUPANCY.RDS",
         "PerPkg": "1",
         "UMask": "0x1",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "Scoreboard Occupancy; Writes",
+        "EventCode": "0xD5",
+        "EventName": "UNC_M_SB_OCCUPANCY.WRS",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "Number of Scoreboard Requests Rejected; FM requests rejected due to full address conflict",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD4",
         "EventName": "UNC_M_SB_REJECT.FM_ADDR_CNFLT",
         "PerPkg": "1",
         "UMask": "0x2",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "Number of Scoreboard Requests Rejected; NM requests rejected due to set conflict",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M_SB_REJECT.NM_SET_CNFLT",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "Number of Scoreboard Requests Rejected; Patrol requests rejected due to set conflict",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD4",
         "EventName": "UNC_M_SB_REJECT.PATROL_SET_CNFLT",
         "PerPkg": "1",
@@ -2495,17 +2496,15 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Near Mem Read - Set",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Far Mem Read - Clear",
         "EventCode": "0xD7",
-        "EventName": "UNC_M_SB_STRV_ALLOC.NMRD_SET",
+        "EventName": "UNC_M_SB_STRV_ALLOC.FMRD_CLR",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Far Mem Read - Set",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD7",
         "EventName": "UNC_M_SB_STRV_ALLOC.FMRD_SET",
         "PerPkg": "1",
@@ -2513,17 +2512,15 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Near Mem Write - Set",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Far Mem Write - Clear",
         "EventCode": "0xD7",
-        "EventName": "UNC_M_SB_STRV_ALLOC.NMWR_SET",
+        "EventName": "UNC_M_SB_STRV_ALLOC.FMWR_CLR",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0x80",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Far Mem Write - Set",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD7",
         "EventName": "UNC_M_SB_STRV_ALLOC.FMWR_SET",
         "PerPkg": "1",
@@ -2532,7 +2529,6 @@
     },
     {
         "BriefDescription": "Near Mem Read - Clear",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD7",
         "EventName": "UNC_M_SB_STRV_ALLOC.NMRD_CLR",
         "PerPkg": "1",
@@ -2540,17 +2536,15 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Far Mem Read - Clear",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Near Mem Read - Set",
         "EventCode": "0xD7",
-        "EventName": "UNC_M_SB_STRV_ALLOC.FMRD_CLR",
+        "EventName": "UNC_M_SB_STRV_ALLOC.NMRD_SET",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Near Mem Write - Clear",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD7",
         "EventName": "UNC_M_SB_STRV_ALLOC.NMWR_CLR",
         "PerPkg": "1",
@@ -2558,35 +2552,39 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Far Mem Write - Clear",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Near Mem Write - Set",
         "EventCode": "0xD7",
-        "EventName": "UNC_M_SB_STRV_ALLOC.FMWR_CLR",
+        "EventName": "UNC_M_SB_STRV_ALLOC.NMWR_SET",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Near Mem Read",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Far Mem Read",
         "EventCode": "0xD8",
-        "EventName": "UNC_M_SB_STRV_OCC.NMRD",
+        "EventName": "UNC_M_SB_STRV_OCC.FMRD",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Far Mem Read",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Far Mem Write",
         "EventCode": "0xD8",
-        "EventName": "UNC_M_SB_STRV_OCC.FMRD",
+        "EventName": "UNC_M_SB_STRV_OCC.FMWR",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "UMask": "0x8",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Near Mem Read",
+        "EventCode": "0xD8",
+        "EventName": "UNC_M_SB_STRV_OCC.NMRD",
+        "PerPkg": "1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Near Mem Write",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD8",
         "EventName": "UNC_M_SB_STRV_OCC.NMWR",
         "PerPkg": "1",
@@ -2594,26 +2592,55 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Far Mem Write",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD8",
-        "EventName": "UNC_M_SB_STRV_OCC.FMWR",
+        "BriefDescription": "UNC_M_SB_TAGGED.DDR4_CMP",
+        "EventCode": "0xDD",
+        "EventName": "UNC_M_SB_TAGGED.DDR4_CMP",
         "PerPkg": "1",
         "UMask": "0x8",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "UNC_M_SB_TAGGED.NEW",
-        "Counter": "0,1,2,3",
         "EventCode": "0xDD",
         "EventName": "UNC_M_SB_TAGGED.NEW",
         "PerPkg": "1",
         "UMask": "0x1",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "UNC_M_SB_TAGGED.OCC",
+        "EventCode": "0xDD",
+        "EventName": "UNC_M_SB_TAGGED.OCC",
+        "PerPkg": "1",
+        "UMask": "0x80",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "UNC_M_SB_TAGGED.PMM0_CMP",
+        "EventCode": "0xDD",
+        "EventName": "UNC_M_SB_TAGGED.PMM0_CMP",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "UNC_M_SB_TAGGED.PMM1_CMP",
+        "EventCode": "0xDD",
+        "EventName": "UNC_M_SB_TAGGED.PMM1_CMP",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "UNC_M_SB_TAGGED.PMM2_CMP",
+        "EventCode": "0xDD",
+        "EventName": "UNC_M_SB_TAGGED.PMM2_CMP",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "UNC_M_SB_TAGGED.RD_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xDD",
         "EventName": "UNC_M_SB_TAGGED.RD_HIT",
         "PerPkg": "1",
@@ -2622,7 +2649,6 @@
     },
     {
         "BriefDescription": "UNC_M_SB_TAGGED.RD_MISS",
-        "Counter": "0,1,2,3",
         "EventCode": "0xDD",
         "EventName": "UNC_M_SB_TAGGED.RD_MISS",
         "PerPkg": "1",
@@ -2630,26 +2656,34 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "UNC_M_SB_TAGGED.DDR4_CMP",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xDD",
-        "EventName": "UNC_M_SB_TAGGED.DDR4_CMP",
+        "BriefDescription": "All hits to Near Memory(DRAM cache) in Memory Mode",
+        "EventCode": "0xD3",
+        "EventName": "UNC_M_TAGCHK.HIT",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Tag Check; Hit",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "UNC_M_SB_TAGGED.OCC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xDD",
-        "EventName": "UNC_M_SB_TAGGED.OCC",
+        "BriefDescription": "All Clean line misses to Near Memory(DRAM cache) in Memory Mode",
+        "EventCode": "0xD3",
+        "EventName": "UNC_M_TAGCHK.MISS_CLEAN",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Tag Check; Clean",
+        "UMask": "0x2",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "All dirty line misses to Near Memory(DRAM cache) in Memory Mode",
+        "EventCode": "0xD3",
+        "EventName": "UNC_M_TAGCHK.MISS_DIRTY",
+        "PerPkg": "1",
+        "PublicDescription": "Tag Check; Dirty",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH",
         "PerPkg": "1",
@@ -2658,7 +2692,6 @@
     },
     {
         "BriefDescription": "Transition from WMM to RMM because of low threshold",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "UNC_M_WMM_TO_RMM.STARVE",
         "PerPkg": "1",
@@ -2667,7 +2700,6 @@
     },
     {
         "BriefDescription": "Transition from WMM to RMM because of low threshold",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY",
         "PerPkg": "1",
@@ -2676,47 +2708,69 @@
     },
     {
         "BriefDescription": "Write Pending Queue Full Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_M_WPQ_CYCLES_FULL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC.  This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Write Pending Queue Not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_M_WPQ_CYCLES_NE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Write Pending Queue Allocations",
+        "EventCode": "0x20",
+        "EventName": "UNC_M_WPQ_INSERTS",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of writes requests allocated into the Write Pending Queue (WPQ).  The WPQ is used to schedule writes out to the memory controller and to track the requests.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (Memory Controller).  The write requests deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Write Pending Queue Occupancy",
+        "EventCode": "0x81",
+        "EventName": "UNC_M_WPQ_OCCUPANCY",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries in the Write Pending Queue (WPQ) at each cycle.  This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The WPQ is used to schedule writes out to the memory controller and to track the requests.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller).  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.  So, we provide filtering based on if the request has posted or not.  By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA.  The 'posted' filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory.  High average occupancies will generally coincide with high write major mode counts. Is there a filter of sorts???",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Write Pending Queue CAM Match",
-        "Counter": "0,1,2,3",
         "EventCode": "0x23",
         "EventName": "UNC_M_WPQ_READ_HIT",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Write Pending Queue CAM Match",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_M_WPQ_WRITE_HIT",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Not getting the requested Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC1",
         "EventName": "UNC_M_WRONG_MM",
         "PerPkg": "1",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 0; All Banks",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK0",
         "PerPkg": "1",
@@ -2724,16 +2778,62 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK1",
         "PerPkg": "1",
         "UMask": "0x1",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK10",
+        "PerPkg": "1",
+        "UMask": "0xa",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK11",
+        "PerPkg": "1",
+        "UMask": "0xb",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK12",
+        "PerPkg": "1",
+        "UMask": "0xc",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK13",
+        "PerPkg": "1",
+        "UMask": "0xd",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 14",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK14",
+        "PerPkg": "1",
+        "UMask": "0xe",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 15",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK15",
+        "PerPkg": "1",
+        "UMask": "0xf",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK2",
         "PerPkg": "1",
@@ -2742,7 +2842,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK3",
         "PerPkg": "1",
@@ -2751,7 +2850,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK4",
         "PerPkg": "1",
@@ -2760,7 +2858,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK5",
         "PerPkg": "1",
@@ -2769,7 +2866,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK6",
         "PerPkg": "1",
@@ -2778,7 +2874,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK7",
         "PerPkg": "1",
@@ -2787,7 +2882,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK8",
         "PerPkg": "1",
@@ -2796,7 +2890,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK9",
         "PerPkg": "1",
@@ -2804,124 +2897,110 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANKG0",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x11",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANKG1",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x12",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANKG2",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x13",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANKG3",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 14",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK14",
+        "BriefDescription": "WR_CAS Access to Rank 1; All Banks",
+        "EventCode": "0xB9",
+        "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 15",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK15",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 0",
+        "EventCode": "0xB9",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK0",
         "PerPkg": "1",
-        "UMask": "0xF",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; All Banks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 1",
+        "EventCode": "0xB9",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANKG0",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 10",
+        "EventCode": "0xB9",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK10",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANKG1",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 11",
+        "EventCode": "0xB9",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK11",
         "PerPkg": "1",
-        "UMask": "0x12",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANKG2",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 12",
+        "EventCode": "0xB9",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK12",
         "PerPkg": "1",
-        "UMask": "0x13",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANKG3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 13",
+        "EventCode": "0xB9",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK13",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 14",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK14",
         "PerPkg": "1",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 15",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK15",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK2",
         "PerPkg": "1",
@@ -2930,7 +3009,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK3",
         "PerPkg": "1",
@@ -2939,7 +3017,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK4",
         "PerPkg": "1",
@@ -2948,7 +3025,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK5",
         "PerPkg": "1",
@@ -2957,7 +3033,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK6",
         "PerPkg": "1",
@@ -2966,7 +3041,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK7",
         "PerPkg": "1",
@@ -2975,7 +3049,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK8",
         "PerPkg": "1",
@@ -2984,7 +3057,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK9",
         "PerPkg": "1",
@@ -2992,124 +3064,110 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANKG0",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x11",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANKG1",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x12",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANKG2",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x13",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANKG3",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 14",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK14",
+        "BriefDescription": "WR_CAS Access to Rank 2; All Banks",
+        "EventCode": "0xBA",
+        "EventName": "UNC_M_WR_CAS_RANK2.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 15",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK15",
+        "BriefDescription": "WR_CAS Access to Rank 2; Bank 0",
+        "EventCode": "0xBA",
+        "EventName": "UNC_M_WR_CAS_RANK2.BANK0",
         "PerPkg": "1",
-        "UMask": "0xF",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; All Banks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS",
+        "BriefDescription": "WR_CAS Access to Rank 2; Bank 1",
+        "EventCode": "0xBA",
+        "EventName": "UNC_M_WR_CAS_RANK2.BANK1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANKG0",
+        "BriefDescription": "WR_CAS Access to Rank 2; Bank 10",
+        "EventCode": "0xBA",
+        "EventName": "UNC_M_WR_CAS_RANK2.BANK10",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANKG1",
+        "BriefDescription": "WR_CAS Access to Rank 2; Bank 11",
+        "EventCode": "0xBA",
+        "EventName": "UNC_M_WR_CAS_RANK2.BANK11",
         "PerPkg": "1",
-        "UMask": "0x12",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANKG2",
+        "BriefDescription": "WR_CAS Access to Rank 2; Bank 12",
+        "EventCode": "0xBA",
+        "EventName": "UNC_M_WR_CAS_RANK2.BANK12",
         "PerPkg": "1",
-        "UMask": "0x13",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANKG3",
+        "BriefDescription": "WR_CAS Access to Rank 2; Bank 13",
+        "EventCode": "0xBA",
+        "EventName": "UNC_M_WR_CAS_RANK2.BANK13",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 2; Bank 14",
         "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK2.BANK14",
         "PerPkg": "1",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 2; Bank 15",
         "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK2.BANK15",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK2",
         "PerPkg": "1",
@@ -3118,7 +3176,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK3",
         "PerPkg": "1",
@@ -3127,7 +3184,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK4",
         "PerPkg": "1",
@@ -3136,7 +3192,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK5",
         "PerPkg": "1",
@@ -3145,7 +3200,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK6",
         "PerPkg": "1",
@@ -3154,7 +3208,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK7",
         "PerPkg": "1",
@@ -3163,7 +3216,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK8",
         "PerPkg": "1",
@@ -3172,7 +3224,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK9",
         "PerPkg": "1",
@@ -3180,124 +3231,110 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 0 (Banks 0-3)",
         "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK2.BANKG0",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x11",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 1 (Banks 4-7)",
         "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK2.BANKG1",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x12",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 2 (Banks 8-11)",
         "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK2.BANKG2",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x13",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 3 (Banks 12-15)",
         "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK2.BANKG3",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; Bank 14",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.BANK14",
+        "BriefDescription": "WR_CAS Access to Rank 3; All Banks",
+        "EventCode": "0xBB",
+        "EventName": "UNC_M_WR_CAS_RANK3.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; Bank 15",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.BANK15",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank 0",
+        "EventCode": "0xBB",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANK0",
         "PerPkg": "1",
-        "UMask": "0xF",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; All Banks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.ALLBANKS",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank 1",
+        "EventCode": "0xBB",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANK1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.BANKG0",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank 10",
+        "EventCode": "0xBB",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANK10",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.BANKG1",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank 11",
+        "EventCode": "0xBB",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANK11",
         "PerPkg": "1",
-        "UMask": "0x12",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.BANKG2",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank 12",
+        "EventCode": "0xBB",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANK12",
         "PerPkg": "1",
-        "UMask": "0x13",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.BANKG3",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank 13",
+        "EventCode": "0xBB",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANK13",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank 14",
         "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANK14",
         "PerPkg": "1",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank 15",
         "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANK15",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK2",
         "PerPkg": "1",
@@ -3306,7 +3343,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK3",
         "PerPkg": "1",
@@ -3315,7 +3351,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK4",
         "PerPkg": "1",
@@ -3324,7 +3359,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK5",
         "PerPkg": "1",
@@ -3333,7 +3367,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK6",
         "PerPkg": "1",
@@ -3342,7 +3375,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK7",
         "PerPkg": "1",
@@ -3351,7 +3383,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK8",
         "PerPkg": "1",
@@ -3360,7 +3391,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK9",
         "PerPkg": "1",
@@ -3368,124 +3398,110 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 0 (Banks 0-3)",
         "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANKG0",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x11",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 1 (Banks 4-7)",
         "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANKG1",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x12",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 2 (Banks 8-11)",
         "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANKG2",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x13",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 3 (Banks 12-15)",
         "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANKG3",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank 14",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANK14",
+        "BriefDescription": "WR_CAS Access to Rank 4; All Banks",
+        "EventCode": "0xBC",
+        "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank 15",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANK15",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 0",
+        "EventCode": "0xBC",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK0",
         "PerPkg": "1",
-        "UMask": "0xF",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; All Banks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.ALLBANKS",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 1",
+        "EventCode": "0xBC",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANKG0",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 10",
+        "EventCode": "0xBC",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK10",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANKG1",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 11",
+        "EventCode": "0xBC",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK11",
         "PerPkg": "1",
-        "UMask": "0x12",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANKG2",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 12",
+        "EventCode": "0xBC",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK12",
         "PerPkg": "1",
-        "UMask": "0x13",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANKG3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 13",
+        "EventCode": "0xBC",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK13",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 14",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK14",
         "PerPkg": "1",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 15",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK15",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK2",
         "PerPkg": "1",
@@ -3494,7 +3510,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK3",
         "PerPkg": "1",
@@ -3503,7 +3518,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK4",
         "PerPkg": "1",
@@ -3512,7 +3526,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK5",
         "PerPkg": "1",
@@ -3521,7 +3534,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK6",
         "PerPkg": "1",
@@ -3530,7 +3542,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK7",
         "PerPkg": "1",
@@ -3539,7 +3550,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK8",
         "PerPkg": "1",
@@ -3548,7 +3558,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK9",
         "PerPkg": "1",
@@ -3556,124 +3565,110 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANKG0",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x11",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANKG1",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x12",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANKG2",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x13",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANKG3",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 14",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK14",
+        "BriefDescription": "WR_CAS Access to Rank 5; All Banks",
+        "EventCode": "0xBD",
+        "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 15",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK15",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 0",
+        "EventCode": "0xBD",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK0",
         "PerPkg": "1",
-        "UMask": "0xF",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; All Banks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 1",
+        "EventCode": "0xBD",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANKG0",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 10",
+        "EventCode": "0xBD",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK10",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANKG1",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 11",
+        "EventCode": "0xBD",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK11",
         "PerPkg": "1",
-        "UMask": "0x12",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANKG2",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 12",
+        "EventCode": "0xBD",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK12",
         "PerPkg": "1",
-        "UMask": "0x13",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANKG3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 13",
+        "EventCode": "0xBD",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK13",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 14",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK14",
         "PerPkg": "1",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 15",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK15",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK2",
         "PerPkg": "1",
@@ -3682,7 +3677,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK3",
         "PerPkg": "1",
@@ -3691,7 +3685,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK4",
         "PerPkg": "1",
@@ -3700,7 +3693,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK5",
         "PerPkg": "1",
@@ -3709,7 +3701,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK6",
         "PerPkg": "1",
@@ -3718,7 +3709,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK7",
         "PerPkg": "1",
@@ -3727,7 +3717,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK8",
         "PerPkg": "1",
@@ -3736,7 +3725,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK9",
         "PerPkg": "1",
@@ -3744,124 +3732,110 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANKG0",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x11",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANKG1",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x12",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANKG2",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x13",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANKG3",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 14",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK14",
+        "BriefDescription": "WR_CAS Access to Rank 6; All Banks",
+        "EventCode": "0xBE",
+        "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 15",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK15",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 0",
+        "EventCode": "0xBE",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK0",
         "PerPkg": "1",
-        "UMask": "0xF",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; All Banks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 1",
+        "EventCode": "0xBE",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANKG0",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 10",
+        "EventCode": "0xBE",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK10",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANKG1",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 11",
+        "EventCode": "0xBE",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK11",
         "PerPkg": "1",
-        "UMask": "0x12",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANKG2",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 12",
+        "EventCode": "0xBE",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK12",
         "PerPkg": "1",
-        "UMask": "0x13",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANKG3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 13",
+        "EventCode": "0xBE",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK13",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 14",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK14",
         "PerPkg": "1",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 15",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK15",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK2",
         "PerPkg": "1",
@@ -3870,7 +3844,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK3",
         "PerPkg": "1",
@@ -3879,7 +3852,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK4",
         "PerPkg": "1",
@@ -3888,7 +3860,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK5",
         "PerPkg": "1",
@@ -3897,7 +3868,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK6",
         "PerPkg": "1",
@@ -3906,7 +3876,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK7",
         "PerPkg": "1",
@@ -3915,7 +3884,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK8",
         "PerPkg": "1",
@@ -3924,7 +3892,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK9",
         "PerPkg": "1",
@@ -3932,124 +3899,110 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANKG0",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x11",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANKG1",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x12",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANKG2",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x13",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANKG3",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 14",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK14",
+        "BriefDescription": "WR_CAS Access to Rank 7; All Banks",
+        "EventCode": "0xBF",
+        "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 15",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK15",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
+        "EventCode": "0xBF",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK0",
         "PerPkg": "1",
-        "UMask": "0xF",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; All Banks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
+        "EventCode": "0xBF",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANKG0",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 10",
+        "EventCode": "0xBF",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK10",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANKG1",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 11",
+        "EventCode": "0xBF",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK11",
         "PerPkg": "1",
-        "UMask": "0x12",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANKG2",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
+        "EventCode": "0xBF",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK12",
         "PerPkg": "1",
-        "UMask": "0x13",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANKG3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
+        "EventCode": "0xBF",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK13",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK14",
         "PerPkg": "1",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK15",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK2",
         "PerPkg": "1",
@@ -4058,7 +4011,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK3",
         "PerPkg": "1",
@@ -4067,7 +4019,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK4",
         "PerPkg": "1",
@@ -4076,7 +4027,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK5",
         "PerPkg": "1",
@@ -4085,7 +4035,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK6",
         "PerPkg": "1",
@@ -4094,7 +4043,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK7",
         "PerPkg": "1",
@@ -4103,7 +4051,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK8",
         "PerPkg": "1",
@@ -4112,79 +4059,14 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK9",
         "PerPkg": "1",
         "UMask": "0x9",
         "Unit": "iMC"
     },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 10",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK10",
-        "PerPkg": "1",
-        "UMask": "0xA",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 11",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK11",
-        "PerPkg": "1",
-        "UMask": "0xB",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK12",
-        "PerPkg": "1",
-        "UMask": "0xC",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK13",
-        "PerPkg": "1",
-        "UMask": "0xD",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK14",
-        "PerPkg": "1",
-        "UMask": "0xE",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK15",
-        "PerPkg": "1",
-        "UMask": "0xF",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 7; All Banks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "iMC"
-    },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANKG0",
         "PerPkg": "1",
@@ -4193,7 +4075,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANKG1",
         "PerPkg": "1",
@@ -4202,7 +4083,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANKG2",
         "PerPkg": "1",
@@ -4211,337 +4091,10 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANKG3",
         "PerPkg": "1",
         "UMask": "0x14",
         "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter",
-        "Counter": "FIXED",
-        "EventCode": "0xff",
-        "EventName": "UNC_M_CLOCKTICKS_F",
-        "PerPkg": "1",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "PMM Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "PMM Read Queue Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xE1",
-        "EventName": "UNC_M_PMM_RPQ_CYCLES_NE",
-        "PerPkg": "1",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "PMM Read Queue Cycles Full",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xE2",
-        "EventName": "UNC_M_PMM_RPQ_CYCLES_FULL",
-        "PerPkg": "1",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "RPQ GNTs",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xEA",
-        "EventName": "UNC_M_PMM_CMD1.RPQ_GNTS",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "Underfill GNTs",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xEA",
-        "EventName": "UNC_M_PMM_CMD1.WPQ_GNTS",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "Misc GNTs",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xEA",
-        "EventName": "UNC_M_PMM_CMD1.MISC_GNT",
-        "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "Misc Commands (error, flow ACKs)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xEA",
-        "EventName": "UNC_M_PMM_CMD1.MISC",
-        "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "Opportunistic Reads",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xEB",
-        "EventName": "UNC_M_PMM_CMD2.OPP_RD",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "Expected No data packet (ERID matched NDP encoding)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xEB",
-        "EventName": "UNC_M_PMM_CMD2.NODATA_EXP",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "Unexpected No data packet (ERID matched a Read, but data was a NDP)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xEB",
-        "EventName": "UNC_M_PMM_CMD2.NODATA_UNEXP",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "Read Requests - Slot 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xEB",
-        "EventName": "UNC_M_PMM_CMD2.REQS_SLOT0",
-        "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "Read Requests - Slot 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xEB",
-        "EventName": "UNC_M_PMM_CMD2.REQS_SLOT1",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "PMM ECC Errors",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xEB",
-        "EventName": "UNC_M_PMM_CMD2.PMM_ECC_ERROR",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "PMM ERID detectable parity error",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xEB",
-        "EventName": "UNC_M_PMM_CMD2.PMM_ERID_ERROR",
-        "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "PMM Major Mode; Cycles PMM is in Read Major Mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xEC",
-        "EventName": "UNC_M_PMM_MAJMODE1.RD_CYC",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "PMM Major Mode; Cycles PMM is in Partial Write Major Mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xEC",
-        "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_CYC",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "PMM Major Mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xEC",
-        "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_ENTER",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "PMM Major Mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xEC",
-        "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_EXIT",
-        "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "UNC_M_MAJMODE2.DRAM_CYC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xED",
-        "EventName": "UNC_M_MAJMODE2.DRAM_CYC",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "UNC_M_MAJMODE2.DRAM_ENTER",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xED",
-        "EventName": "UNC_M_MAJMODE2.DRAM_ENTER",
-        "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "UNC_M_MAJMODE2.PMM_ENTER",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xED",
-        "EventName": "UNC_M_MAJMODE2.PMM_ENTER",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "PMM Write Queue Cycles Full",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xE6",
-        "EventName": "UNC_M_PMM_WPQ_CYCLES_FULL",
-        "PerPkg": "1",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "PMM Write Queue Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xE5",
-        "EventName": "UNC_M_PMM_WPQ_CYCLES_NE",
-        "PerPkg": "1",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "PMM Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xE4",
-        "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.CAS",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "PMM Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xE4",
-        "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.PWR",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "UNC_M_PMM_WPQ_PCOMMIT",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xE8",
-        "EventName": "UNC_M_PMM_WPQ_PCOMMIT",
-        "PerPkg": "1",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "UNC_M_PMM_WPQ_PCOMMIT_CYC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xE9",
-        "EventName": "UNC_M_PMM_WPQ_PCOMMIT_CYC",
-        "PerPkg": "1",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "PMM Major Mode; Cycles PMM is in Write Major Mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xEC",
-        "EventName": "UNC_M_PMM_MAJMODE1.WR_CYC",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "UNC_M_MAJMODE2.PMM_CYC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xED",
-        "EventName": "UNC_M_MAJMODE2.PMM_CYC",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "UNC_M_SB_TAGGED.PMM0_CMP",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xDD",
-        "EventName": "UNC_M_SB_TAGGED.PMM0_CMP",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "UNC_M_SB_TAGGED.PMM1_CMP",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xDD",
-        "EventName": "UNC_M_SB_TAGGED.PMM1_CMP",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "UNC_M_SB_TAGGED.PMM2_CMP",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xDD",
-        "EventName": "UNC_M_SB_TAGGED.PMM2_CMP",
-        "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "Scoreboard Inserts; Persistent Mem writes",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M_SB_INSERTS.PMM_WRS",
-        "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "Scoreboard Occupancy; Persistent Mem writes",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD5",
-        "EventName": "UNC_M_SB_OCCUPANCY.PMM_WRS",
-        "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "Scoreboard Occupancy; Persistent Mem reads",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD5",
-        "EventName": "UNC_M_SB_OCCUPANCY.PMM_RDS",
-        "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "Scoreboard Inserts; Persistent Mem reads",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M_SB_INSERTS.PMM_RDS",
-        "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "iMC"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json
index e10530c21ef8b..ef4767feb4e2f 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json
@@ -1,8010 +1,7928 @@
 [
     {
-        "BriefDescription": "Traffic in which the M2M to iMC Bypass was not taken",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x22",
-        "EventName": "UNC_M2M_BYPASS_M2M_Egress.NOT_TAKEN",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x24",
-        "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
+        "BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.ia_miss",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.MMIO_READ",
+        "Filter": "config1=0x40040e33",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages sent direct to core (bypassing the CHA)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x23",
-        "EventName": "UNC_M2M_DIRECT2CORE_TAKEN",
+        "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.MMIO_WRITE",
+        "Filter": "config1=0x40041e33",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number of reads in which direct to core transaction were overridden",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x25",
-        "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
+        "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0",
+        "EventCode": "0x83",
+        "EventName": "LLC_MISSES.PCIE_READ",
+        "FCMask": "0x07",
+        "Filter": "ch_mask=0x1f",
+        "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
+        "MetricName": "LLC_MISSES.PCIE_READ",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "ScaleUnit": "4Bytes",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY",
+        "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0",
+        "EventCode": "0x83",
+        "EventName": "LLC_MISSES.PCIE_WRITE",
+        "FCMask": "0x07",
+        "Filter": "ch_mask=0x1f",
+        "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
+        "MetricName": "LLC_MISSES.PCIE_WRITE",
         "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part0 to a unit onthe main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "ScaleUnit": "4Bytes",
         "UMask": "0x1",
-        "Unit": "M2M"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I",
+        "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.UNCACHEABLE",
+        "Filter": "config1=0x40e33",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S",
+        "BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss",
+        "EventCode": "0x35",
+        "EventName": "LLC_REFERENCES.STREAMING_FULL",
+        "Filter": "config1=0x41833",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A",
+        "BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss",
+        "EventCode": "0x35",
+        "EventName": "LLC_REFERENCES.STREAMING_PARTIAL",
+        "Filter": "config1=0x41a33",
         "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory update from/to Any state",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x1",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory update from I to S",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x2",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory update from I to A",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x4",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory update from S to I",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x8",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory update from S to A",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory update from A to I",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x20",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory update from A to S",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Reads to iMC issued at Normal Priority (Non-Isochronous)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.NORMAL",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Reads to iMC issued",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.ALL",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x4",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Partial Non-Isochronous writes to the iMC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.PARTIAL",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Writes to iMC issued",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.ALL",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.NI",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Prefecth requests that got turn into a demand request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x56",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_PROMOTIONS",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Inserts into the Memory Controller Prefetch Queue",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x57",
-        "EventName": "UNC_M2M_PREFCAM_INSERTS",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AD Ingress (from CMS) Queue Inserts",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_M2M_RxC_AD_INSERTS",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AD Ingress (from CMS) Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Ingress (from CMS) Allocations",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_M2M_RxC_BL_INSERTS",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Ingress (from CMS) Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6",
-        "EventName": "UNC_M2M_RxC_BL_OCCUPANCY",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Allocations",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9",
-        "EventName": "UNC_M2M_TxC_AD_INSERTS",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA",
-        "EventName": "UNC_M2M_TxC_AD_OCCUPANCY",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Allocations; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Occupancy; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x16",
-        "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.ALL",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x28",
-        "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles when direct to Intel UPI was disabled",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x27",
-        "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages sent direct to the Intel UPI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x26",
-        "EventName": "UNC_M2M_DIRECT2UPI_TAKEN",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x29",
-        "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Dirty line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2C",
-        "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Clean line underfill read hits to Near Memory(DRAM cache) in Memory Mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2C",
-        "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Dirty line underfill read hits to Near Memory(DRAM cache) in Memory Mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2C",
-        "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read requests to Intel Optane DC persistent memory issued to the iMC from M2M",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.TO_PMM",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write requests to Intel Optane DC persistent memory issued to the iMC from M2M",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.TO_PMM",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CLOCKTICKS",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventName": "UNC_C_CLOCKTICKS",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued; Multiple Core Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0x42",
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued; Multiple Eviction",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0x82",
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x53",
-        "EventName": "UNC_CHA_DIR_LOOKUP.SNP",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x53",
-        "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x54",
-        "EventName": "UNC_CHA_DIR_UPDATE.HA",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x54",
-        "EventName": "UNC_CHA_DIR_UPDATE.TOR",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5F",
-        "EventName": "UNC_CHA_HITME_HIT.EX_RDS",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_C_LLC_VICTIMS.S_STATE",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_C_LLC_VICTIMS.F_STATE",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number of times that an RFO hit in S state",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_CHA_MISC.RFO_HIT_S",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "read requests from home agent",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.READS",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5",
         "PerPkg": "1",
-        "UMask": "0x03",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "write requests from home agent",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.WRITES",
+        "BriefDescription": "CHA to iMC Bypass; Intermediate bypass Taken",
+        "EventCode": "0x57",
+        "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
         "PerPkg": "1",
-        "UMask": "0x0C",
+        "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the intermediate bypass.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "read requests from local home agent",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.READS_LOCAL",
+        "BriefDescription": "CHA to iMC Bypass; Not Taken",
+        "EventCode": "0x57",
+        "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "write requests from local home agent",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL",
-        "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Local requests for exclusive ownership of a cache line  without receiving data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL",
+        "BriefDescription": "CHA to iMC Bypass; Taken",
+        "EventCode": "0x57",
+        "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the full bypass.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE",
+        "BriefDescription": "Uncore cache clock ticks",
+        "EventName": "UNC_CHA_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts clockticks of the clock controlling the uncore caching and home agent (CHA).",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RspIFwd Snoop Responses Received",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5C",
-        "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD",
+        "BriefDescription": "CMS Clockticks",
+        "EventCode": "0xC0",
+        "EventName": "UNC_CHA_CMS_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RspSFwd Snoop Responses Received",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5C",
-        "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD",
+        "BriefDescription": "Core PMA Events; C1  State",
+        "EventCode": "0x17",
+        "EventName": "UNC_CHA_CORE_PMA.C1_STATE",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Rsp*Fwd*WB Snoop Responses Received",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5C",
-        "EventName": "UNC_CHA_SNOOP_RESP.RSP_FWD_WB",
+        "BriefDescription": "Core PMA Events; C1 Transition",
+        "EventCode": "0x17",
+        "EventName": "UNC_CHA_CORE_PMA.C1_TRANSITION",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPCNFLCTS",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5C",
-        "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
+        "BriefDescription": "Core PMA Events; C6 State",
+        "EventCode": "0x17",
+        "EventName": "UNC_CHA_CORE_PMA.C6_STATE",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.IRQ",
+        "BriefDescription": "Core PMA Events; C6 Transition",
+        "EventCode": "0x17",
+        "EventName": "UNC_CHA_CORE_PMA.C6_TRANSITION",
         "PerPkg": "1",
-        "UMask": "0x31",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA",
-        "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.IRQ",
+        "BriefDescription": "Core PMA Events; GV",
+        "EventCode": "0x17",
+        "EventName": "UNC_CHA_CORE_PMA.GV",
         "PerPkg": "1",
-        "UMask": "0x31",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.REM_ALL",
+        "BriefDescription": "Core Cross Snoops Issued; Any Cycle with Multiple Snoops",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE",
         "PerPkg": "1",
-        "UMask": "0x30",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0xe2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_FAST_ASSERTED.HORZ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0xA5",
-        "EventName": "UNC_C_FAST_ASSERTED",
+        "BriefDescription": "Core Cross Snoops Issued; Any Single Snoop",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.ANY_ONE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0xe1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations; IRQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.IRQ",
+        "BriefDescription": "Core Cross Snoops Issued; Any Snoop to Remote Node",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.ANY_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0xe4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
+        "BriefDescription": "Core Cross Snoops Issued; Multiple Core Requests",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x42",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Occupancy; IRQ",
-        "EventCode": "0x11",
-        "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ",
+        "BriefDescription": "Core Cross Snoops Issued; Single Core Requests",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.CORE_ONE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x41",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.IRQ_HIT",
+        "BriefDescription": "Core Cross Snoops Issued; Core Request to Remote Node",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.CORE_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x44",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.IRQ_MISS",
+        "BriefDescription": "Core Cross Snoops Issued; Multiple Eviction",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x82",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_HIT",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.PRQ_HIT",
+        "BriefDescription": "Core Cross Snoops Issued; Single Eviction",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x81",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_MISS",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.PRQ_MISS",
+        "BriefDescription": "Core Cross Snoops Issued; Eviction to Remote Node",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.EVICT_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x24",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x84",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_HIT",
-        "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_HIT",
+        "BriefDescription": "Core Cross Snoops Issued; Multiple External Snoops",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x22",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_MISS",
-        "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_MISS",
+        "BriefDescription": "Core Cross Snoops Issued; Single External Snoops",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.EXT_ONE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
         "UMask": "0x21",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; Hits from Local IO",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
+        "BriefDescription": "Core Cross Snoops Issued; External Snoop to Remote Node",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.EXT_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x24",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; Misses from Local IO",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
+        "BriefDescription": "Counter 0 Occupancy",
+        "EventCode": "0x1F",
+        "EventName": "UNC_CHA_COUNTER0_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x24",
+        "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0.   The filtering available is found in the control register - threshold, invert and edge detect.   E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; All from Local iA",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA",
+        "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed",
+        "EventCode": "0x53",
+        "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP",
         "PerPkg": "1",
-        "UMask": "0x31",
+        "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; Hits from Local iA",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
+        "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed",
+        "EventCode": "0x53",
+        "EventName": "UNC_CHA_DIR_LOOKUP.SNP",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts  transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+        "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe",
+        "EventCode": "0x54",
+        "EventName": "UNC_CHA_DIR_UPDATE.HA",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "LLC_MISSES.UNCACHEABLE",
-        "Filter": "config1=0x40e33",
+        "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe",
+        "EventCode": "0x54",
+        "EventName": "UNC_CHA_DIR_UPDATE.TOR",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.ia_miss",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "LLC_MISSES.MMIO_READ",
-        "Filter": "config1=0x40040e33",
+        "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
+        "EventCode": "0xAE",
+        "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "LLC_MISSES.MMIO_WRITE",
-        "Filter": "config1=0x40041e33",
+        "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
+        "EventCode": "0xAE",
+        "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "LLC_REFERENCES.STREAMING_FULL",
-        "Filter": "config1=0x41833",
+        "BriefDescription": "FaST wire asserted; Horizontal",
+        "EventCode": "0xA5",
+        "EventName": "UNC_CHA_FAST_ASSERTED.HORZ",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x21",
+        "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "LLC_REFERENCES.STREAMING_PARTIAL",
-        "Filter": "config1=0x41a33",
+        "BriefDescription": "FaST wire asserted; Vertical",
+        "EventCode": "0xA5",
+        "EventName": "UNC_CHA_FAST_ASSERTED.VERT",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x21",
+        "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; All from Local iA",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
+        "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state",
+        "EventCode": "0x5F",
+        "EventName": "UNC_CHA_HITME_HIT.EX_RDS",
         "PerPkg": "1",
-        "UMask": "0x31",
+        "PublicDescription": "Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state.  This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*)",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; Hits from Local iA",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; Shared hit and op is RdInvOwn, RdInv, Inv*",
+        "EventCode": "0x5F",
+        "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; Misses from Local iA",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE",
+        "EventCode": "0x5F",
+        "EventName": "UNC_CHA_HITME_HIT.WBMTOE",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCS VN0 Credits",
-        "EventCode": "0x3B",
-        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCS",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
+        "EventCode": "0x5F",
+        "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "FaST wire asserted; Horizontal",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA5",
-        "EventName": "UNC_CHA_FAST_ASSERTED.HORZ",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*",
+        "EventCode": "0x5E",
+        "EventName": "UNC_CHA_HITME_LOOKUP.READ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Uncore cache clock ticks",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_CHA_CLOCKTICKS",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
+        "EventCode": "0x5E",
+        "EventName": "UNC_CHA_HITME_LOOKUP.WRITE",
         "PerPkg": "1",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Normal priority reads issued to the memory controller from the CHA",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x59",
-        "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL",
+        "BriefDescription": "Counts Number of Misses in HitMe Cache; No SF/LLC HitS/F and op is RdInvOwn",
+        "EventCode": "0x60",
+        "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5B",
-        "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL",
+        "BriefDescription": "Counts Number of Misses in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*",
+        "EventCode": "0x60",
+        "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read requests from a remote socket",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.READS_REMOTE",
+        "BriefDescription": "Counts Number of Misses in HitMe Cache; SF/LLC HitS/F and op is RdInvOwn",
+        "EventCode": "0x60",
+        "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RspI Snoop Responses Received",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5C",
-        "EventName": "UNC_CHA_SNOOP_RESP.RSPI",
+        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Deallocate HtiME$ on Reads without RspFwdI*",
+        "EventCode": "0x61",
+        "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Rsp*WB Snoop Responses Received",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5C",
-        "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB",
+        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
+        "EventCode": "0x61",
+        "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Received RspFwdI* for a local request, but converted HitME$ to SF entry",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RspCnflct* Snoop Responses Received",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5C",
-        "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCTS",
+        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache on RdInvOwn even if not RspFwdI*",
+        "EventCode": "0x61",
+        "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop filter capacity evictions for M-state entries",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3D",
-        "EventName": "UNC_CHA_SF_EVICTION.M_STATE",
+        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
+        "EventCode": "0x61",
+        "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Updated HitME$ on RspFwdI* or local HitM/E received for a remote request",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop filter capacity evictions for E-state entries",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3D",
-        "EventName": "UNC_CHA_SF_EVICTION.E_STATE",
+        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache to SHARed",
+        "EventCode": "0x61",
+        "EventName": "UNC_CHA_HITME_UPDATE.SHARED",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop filter capacity evictions for S-state entries",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3D",
-        "EventName": "UNC_CHA_SF_EVICTION.S_STATE",
+        "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
+        "EventCode": "0xA7",
+        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL",
+        "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
+        "EventCode": "0xA7",
+        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x30",
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized; Lines in M state",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M",
+        "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
+        "EventCode": "0xA7",
+        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized; Lines in E state",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E",
+        "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
+        "EventCode": "0xA7",
+        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized; Lines in S State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S",
+        "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
+        "EventCode": "0xA9",
+        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized; Lines in F State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_F",
+        "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
+        "EventCode": "0xA9",
+        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD",
-        "Filter": "config1=0x40433",
+        "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
+        "EventCode": "0xA9",
+        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
-        "Filter": "config1=0x40233",
+        "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
+        "EventCode": "0xA9",
+        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
-        "Filter": "config1=0x40033",
+        "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
+        "EventCode": "0xAB",
+        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD",
-        "Filter": "config1=0x4b433",
+        "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
+        "EventCode": "0xAB",
+        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD",
-        "Filter": "config1=0x4b233",
+        "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
+        "EventCode": "0xAB",
+        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefRFO",
-        "Filter": "config1=0x4b033",
+        "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
+        "EventCode": "0xAB",
+        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD",
-        "Filter": "config1=0x40433",
+        "BriefDescription": "Horizontal IV Ring in Use; Left",
+        "EventCode": "0xAD",
+        "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
-        "Filter": "config1=0x40233",
+        "BriefDescription": "Horizontal IV Ring in Use; Right",
+        "EventCode": "0xAD",
+        "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
-        "Filter": "config1=0x40033",
+        "BriefDescription": "Normal priority reads issued to the memory controller from the CHA",
+        "EventCode": "0x59",
+        "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD",
-        "Filter": "config1=0x4b433",
+        "BriefDescription": "HA to iMC Reads Issued; ISOCH",
+        "EventCode": "0x59",
+        "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Count of the number of reads issued to any of the memory controller channels.  This can be filtered by the priority of the reads.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD",
-        "Filter": "config1=0x4b233",
+        "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
+        "EventCode": "0x5B",
+        "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefRFO",
-        "Filter": "config1=0x4b033",
+        "BriefDescription": "Writes Issued to the iMC by the HA; Full Line MIG",
+        "EventCode": "0x5B",
+        "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_MIG",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
-        "Filter": "config1=0x40433",
+        "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Full Line",
+        "EventCode": "0x5B",
+        "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
-        "Filter": "config1=0x40233",
+        "BriefDescription": "Writes Issued to the iMC by the HA; Partial Non-ISOCH",
+        "EventCode": "0x5B",
+        "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
-        "Filter": "config1=0x40033",
-        "PerPkg": "1",
-        "UMask": "0x11",
+        "BriefDescription": "Writes Issued to the iMC by the HA; Partial MIG",
+        "EventCode": "0x5B",
+        "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.; Filter for memory controller 5 only.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD",
-        "Filter": "config1=0x4b433",
+        "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Partial",
+        "EventCode": "0x5B",
+        "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD",
-        "Filter": "config1=0x4b233",
+        "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations",
+        "EventCode": "0x62",
+        "EventName": "UNC_CHA_IODC_ALLOC.INVITOM",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO",
-        "Filter": "config1=0x4b033",
+        "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations dropped due to IODC Full",
+        "EventCode": "0x62",
+        "EventName": "UNC_CHA_IODC_ALLOC.IODCFULL",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
-        "Filter": "config1=0x40433",
+        "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IDOC allocation dropped due to OSB gate",
+        "EventCode": "0x62",
+        "EventName": "UNC_CHA_IODC_ALLOC.OSBGATED",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
-        "Filter": "config1=0x40233",
+        "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to any reason",
+        "EventCode": "0x63",
+        "EventName": "UNC_CHA_IODC_DEALLOC.ALL",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
-        "Filter": "config1=0x40033",
+        "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to conflicting transaction",
+        "EventCode": "0x63",
+        "EventName": "UNC_CHA_IODC_DEALLOC.SNPOUT",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD",
-        "Filter": "config1=0x4b433",
+        "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoE",
+        "EventCode": "0x63",
+        "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOE",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD",
-        "Filter": "config1=0x4b233",
+        "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoI",
+        "EventCode": "0x63",
+        "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOI",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO",
-        "Filter": "config1=0x4b033",
+        "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbPushMtoI",
+        "EventCode": "0x63",
+        "EventName": "UNC_CHA_IODC_DEALLOC.WBPUSHMTOI",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Moved to Cbo section",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Clockticks of the IIO Traffic Controller",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_IIO_CLOCKTICKS",
+        "BriefDescription": "Cache and Snoop Filter Lookups; Any Request",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.ANY",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ.  This does not include lookups originating from the ISMQ.",
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
-        "Counter": "0,1",
-        "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0",
-        "FCMask": "0x7",
+        "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x1",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Read transactions",
+        "UMask": "0x3",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
-        "Counter": "0,1",
-        "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1",
-        "FCMask": "0x7",
+        "BriefDescription": "Cache and Snoop Filter Lookups; Local",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x1",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.",
+        "UMask": "0x31",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
-        "Counter": "0,1",
-        "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2",
-        "FCMask": "0x7",
+        "BriefDescription": "Cache and Snoop Filter Lookups; Remote",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x1",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.",
+        "UMask": "0x91",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
-        "Counter": "0,1",
-        "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3",
-        "FCMask": "0x7",
+        "BriefDescription": "Cache and Snoop Filter Lookups; External Snoop Request",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x1",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.",
+        "UMask": "0x9",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
-        "Counter": "0,1",
-        "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART0",
-        "FCMask": "0x7",
+        "BriefDescription": "Cache and Snoop Filter Lookups; Write Requests",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.WRITE",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x4",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC  This includes all write transactions -- both Cachable and UC.",
+        "UMask": "0x5",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART1",
-        "FCMask": "0x7",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x4",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2",
-        "FCMask": "0x7",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.F_STATE",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x4",
-        "Unit": "IIO"
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3",
-        "FCMask": "0x7",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x4",
-        "Unit": "IIO"
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Local - All Lines",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x2f",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Local - Lines in E State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x22",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Local - Lines in F State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_F",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x28",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Local - Lines in M State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Local - Lines in S State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x24",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M",
+        "Deprecated": "1",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
+        "Deprecated": "1",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Remote - All Lines",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x8f",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Remote - Lines in E State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x82",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Remote - Lines in F State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_F",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x88",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part2",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Remote - Lines in M State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x81",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part3",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Remote - Lines in S State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x84",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S",
+        "Deprecated": "1",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Lines in E state",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Lines in F State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_F",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Lines in M state",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCI Express bandwidth writing at IIO, part 0",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Lines in S State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCI Express bandwidth writing at IIO, part 1",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Cbo Misc; CV0 Prefetch Miss",
+        "EventCode": "0x39",
+        "EventName": "UNC_CHA_MISC.CV0_PREF_MISS",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Miscellaneous events in the Cbo.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCI Express bandwidth writing at IIO, part 2",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Cbo Misc; CV0 Prefetch Victim",
+        "EventCode": "0x39",
+        "EventName": "UNC_CHA_MISC.CV0_PREF_VIC",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Miscellaneous events in the Cbo.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCI Express bandwidth writing at IIO, part 3",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Number of times that an RFO hit in S state.",
+        "EventCode": "0x39",
+        "EventName": "UNC_CHA_MISC.RFO_HIT_S",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts when a RFO (the Read for Ownership issued before a  write) request hit a cacheline in the S (Shared) state.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "LLC_MISSES.PCIE_WRITE",
-        "FCMask": "0x07",
-        "Filter": "ch_mask=0x1f",
-        "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
-        "MetricName": "LLC_MISSES.PCIE_WRITE",
+        "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
+        "EventCode": "0x39",
+        "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "ScaleUnit": "4Bytes",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction.  This is useful because this information is lost in the PRE encodings.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Cbo Misc; Write Combining Aliasing",
+        "EventCode": "0x39",
+        "EventName": "UNC_CHA_MISC.WC_ALIASING",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write.  This occurs when there is WC aliasing.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "OSB Snoop Broadcast",
+        "EventCode": "0x55",
+        "EventName": "UNC_CHA_OSB",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in IODC",
+        "EventCode": "0x64",
+        "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.IODC",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "2LM related events; Counts the number of times CHA saw NM Set conflict in IODC",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in SF/LLC",
+        "EventCode": "0x64",
+        "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "NM evictions due to another read to the same near memory set in the LLC.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCI Express bandwidth reading at IIO, part 0",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in SF/LLC",
+        "EventCode": "0x64",
+        "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "NM evictions due to another read to the same near memory set in the SF.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCI Express bandwidth reading at IIO, part 1",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in TOR",
+        "EventCode": "0x64",
+        "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "No Reject in the CHA due to a pending read to the same near memory set in the TOR.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCI Express bandwidth reading at IIO, part 2",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Memory mode related events; Counts the number of times CHA saw NM Set conflict in TOR and the transaction was rejected",
+        "EventCode": "0x64",
+        "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR_REJECT",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Rejects in the CHA due to a pending read to the same near memory set in the TOR.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCI Express bandwidth reading at IIO, part 3",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC0_SMI2",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.EDC0_SMI2",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 2 only.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "LLC_MISSES.PCIE_READ",
-        "FCMask": "0x07",
-        "Filter": "ch_mask=0x1f",
-        "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
-        "MetricName": "LLC_MISSES.PCIE_READ",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC1_SMI3",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.EDC1_SMI3",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "ScaleUnit": "4Bytes",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 3 only.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC2_SMI4",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.EDC2_SMI4",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 4 only.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC3_SMI5",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.EDC3_SMI5",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 5 only.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC0_SMI0",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC0_SMI0",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 0 only.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC1_SMI1",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC1_SMI1",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 1 only.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Local requests for exclusive ownership of a cache line  without receiving data",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Read requests",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.READS",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a  write) .",
+        "UMask": "0x3",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Read requests from a unit on this socket",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.READS_LOCAL",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a  write).",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Read requests from a remote socket",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.READS_REMOTE",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a  write).",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Write requests",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.WRITES",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
+        "UMask": "0xc",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Write Requests from a unit on this socket",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Counts  write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Read and Write Requests; Writes Remote",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
+        "EventCode": "0xA1",
+        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
+        "EventCode": "0xA1",
+        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
+        "EventCode": "0xA1",
+        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
+        "EventCode": "0xA1",
+        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
+        "EventCode": "0xA0",
+        "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
+        "EventCode": "0xA0",
+        "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
+        "EventCode": "0xA0",
+        "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.",
+        "EventCode": "0xA0",
+        "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
+        "EventCode": "0xA3",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
+        "EventCode": "0xA3",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
+        "EventCode": "0xA3",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
+        "EventCode": "0xA3",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
+        "EventCode": "0xA3",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Sink Starvation on Vertical Ring; AD",
+        "EventCode": "0xA2",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
+        "EventCode": "0xA2",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
+        "EventCode": "0xA2",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.",
+        "EventCode": "0xA2",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is  made by IIO Part1 to Memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Source Throttle",
+        "EventCode": "0xA4",
+        "EventName": "UNC_CHA_RING_SRC_THRTL",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Ingress (from CMS) Allocations; IPQ",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.IPQ",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Ingress (from CMS) Allocations; IRQ",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.IRQ",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Ingress (from CMS) Allocations; IRQ Rejected",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Ingress (from CMS) Allocations; PRQ",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.PRQ",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Ingress (from CMS) Allocations; PRQ",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Ingress (from CMS) Allocations; RRQ",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.RRQ",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
-        "FCMask": "0x4",
+        "BriefDescription": "Ingress (from CMS) Allocations; WBQ",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.WBQ",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
-        "FCMask": "0x4",
+        "BriefDescription": "Ingress Probe Queue Rejects; AD REQ on VN0",
+        "EventCode": "0x22",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
-        "FCMask": "0x4",
+        "BriefDescription": "Ingress Probe Queue Rejects; AD RSP on VN0",
+        "EventCode": "0x22",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
-        "FCMask": "0x4",
+        "BriefDescription": "Ingress Probe Queue Rejects; Non UPI AK Request",
+        "EventCode": "0x22",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0",
-        "Counter": "2,3",
-        "EventCode": "0xD5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
-        "FCMask": "0x04",
+        "BriefDescription": "Ingress Probe Queue Rejects; BL NCB on VN0",
+        "EventCode": "0x22",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1",
-        "Counter": "2,3",
-        "EventCode": "0xD5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
-        "FCMask": "0x04",
+        "BriefDescription": "Ingress Probe Queue Rejects; BL NCS on VN0",
+        "EventCode": "0x22",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2",
-        "Counter": "2,3",
-        "EventCode": "0xD5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
-        "FCMask": "0x04",
+        "BriefDescription": "Ingress Probe Queue Rejects; BL RSP on VN0",
+        "EventCode": "0x22",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3",
-        "Counter": "2,3",
-        "EventCode": "0xD5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
-        "FCMask": "0x04",
+        "BriefDescription": "Ingress Probe Queue Rejects; BL WB on VN0",
+        "EventCode": "0x22",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",
-        "FCMask": "0x4",
+        "BriefDescription": "Ingress Probe Queue Rejects; Non UPI IV Request",
+        "EventCode": "0x22",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
-        "PortMask": "0x0f",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3",
-        "Counter": "2,3",
-        "EventCode": "0xD5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
-        "FCMask": "0x04",
+        "BriefDescription": "Ingress Probe Queue Rejects; Allow Snoop",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x0f",
-        "Unit": "IIO"
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Total IRP occupancy of inbound read and write requests",
-        "Counter": "0,1",
-        "EventCode": "0xF",
-        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
+        "BriefDescription": "Ingress Probe Queue Rejects; ANY0",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "IRP"
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline",
-        "Counter": "0,1",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.RFO",
+        "BriefDescription": "Ingress Probe Queue Rejects; HA",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA",
         "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "IRP"
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline",
-        "Counter": "0,1",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.PCITOM",
+        "BriefDescription": "Ingress Probe Queue Rejects; Merging these two together to make room for ANY_REJECT_*0",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IRP"
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue",
-        "Counter": "0,1",
-        "EventCode": "0x18",
-        "EventName": "UNC_I_FAF_INSERTS",
+        "BriefDescription": "Ingress Probe Queue Rejects; LLC Victim",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Occupancy of the IRP FAF queue",
-        "Counter": "0,1",
-        "EventCode": "0x19",
-        "EventName": "UNC_I_FAF_OCCUPANCY",
+        "BriefDescription": "Ingress Probe Queue Rejects; PhyAddr Match",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Inbound write (fast path) requests received by the IRP",
-        "Counter": "0,1",
-        "EventCode": "0x11",
-        "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
+        "BriefDescription": "Ingress Probe Queue Rejects; SF Victim",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
         "UMask": "0x8",
-        "Unit": "IRP"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Clocks of the Intel Ultra Path Interconnect (UPI)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_UPI_CLOCKTICKS",
+        "BriefDescription": "Ingress Probe Queue Rejects; Victim",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data Response packets that go direct to core",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
         "UMask": "0x1",
-        "Unit": "UPI LL"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_DIRECT_ATTEMPTS.D2U",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x12",
-        "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
         "UMask": "0x2",
-        "Unit": "UPI LL"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles Intel UPI is in L1 power mode (shutdown)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_UPI_L1_POWER_CYCLES",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles the Rx of the Intel UPI is in L0p power mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x25",
-        "EventName": "UNC_UPI_RxL0P_POWER_CYCLES",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x31",
-        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "UPI LL"
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x31",
-        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "UPI LL"
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "FLITs received which bypassed the Slot0 Recieve Buffer",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x31",
-        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "UPI LL"
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.ALL_NULL",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.NULL",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "UPI LL"
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles in which the Tx of the Intel Ultra Path Interconnect (UPI) is in L0p power mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x27",
-        "EventName": "UNC_UPI_TxL0P_POWER_CYCLES",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "FLITs that bypassed the TxL Buffer",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x41",
-        "EventName": "UNC_UPI_TxL_BYPASSED",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Sent; Data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.DATA",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA",
         "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "UPI LL"
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.ALL_NULL",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.NULL",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Merging these two together to make room for ANY_REJECT_*0",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
         "PerPkg": "1",
         "UMask": "0x20",
-        "Unit": "UPI LL"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Protocol header and credit FLITs received from any slot",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x97",
-        "Unit": "UPI LL"
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Protocol header and credit FLITs transmitted across any slot",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x97",
-        "Unit": "UPI LL"
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Idle FLITs transmitted",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.IDLE",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x47",
-        "Unit": "UPI LL"
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Null FLITs transmitted from any slot",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x27",
-        "Unit": "UPI LL"
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Null FLITs received from any slot",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
+        "BriefDescription": "ISMQ Rejects; AD REQ on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x27",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid data FLITs received from any slot",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
+        "BriefDescription": "ISMQ Rejects; AD RSP on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x0F",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UPI_DATA_BANDWIDTH_TX",
+        "BriefDescription": "ISMQ Rejects; Non UPI AK Request",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
-        "ScaleUnit": "7.11E-06Bytes",
-        "UMask": "0xf",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI interconnect send bandwidth for payload",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
+        "BriefDescription": "ISMQ Rejects; BL NCB on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
-        "ScaleUnit": "7.11E-06Bytes",
-        "UMask": "0xf",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data Response packets that go direct to Intel UPI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2U",
+        "BriefDescription": "ISMQ Rejects; BL NCS on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Prefetches generated by the flow control queue of the M3UPI unit",
-        "Counter": "0,1,2",
-        "EventCode": "0x29",
-        "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN",
+        "BriefDescription": "ISMQ Rejects; BL RSP on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "Unit": "M3UPI"
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M to iMC Bypass; Taken",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x22",
-        "EventName": "UNC_M2M_BYPASS_M2M_Egress.TAKEN",
+        "BriefDescription": "ISMQ Rejects; BL WB on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles - at UCLK",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_M2M_CLOCKTICKS",
+        "BriefDescription": "ISMQ Rejects; Non UPI IV Request",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Hit; On Dirty Line in I State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I",
+        "BriefDescription": "ISMQ Retries; AD REQ on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
         "UMask": "0x1",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Hit; On Dirty Line in S State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S",
+        "BriefDescription": "ISMQ Retries; AD RSP on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
         "UMask": "0x2",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Hit; On Dirty Line in L State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P",
+        "BriefDescription": "ISMQ Retries; Non UPI AK Request",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Hit; On Dirty Line in A State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A",
+        "BriefDescription": "ISMQ Retries; BL NCB on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
         "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Hit; On NonDirty Line in I State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I",
+        "BriefDescription": "ISMQ Retries; BL NCS on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Hit; On NonDirty Line in S State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S",
+        "BriefDescription": "ISMQ Retries; BL RSP on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Hit; On NonDirty Line in L State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P",
+        "BriefDescription": "ISMQ Retries; BL WB on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Hit; On NonDirty Line in A State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A",
+        "BriefDescription": "ISMQ Retries; Non UPI IV Request",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
         "UMask": "0x80",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Miss; On Dirty Line in I State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I",
+        "BriefDescription": "ISMQ Rejects; ANY0",
+        "EventCode": "0x25",
+        "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
         "UMask": "0x1",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Miss; On Dirty Line in S State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S",
+        "BriefDescription": "ISMQ Rejects; HA",
+        "EventCode": "0x25",
+        "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
         "UMask": "0x2",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Miss; On Dirty Line in L State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P",
+        "BriefDescription": "ISMQ Retries; ANY0",
+        "EventCode": "0x2D",
+        "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Miss; On Dirty Line in A State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A",
+        "BriefDescription": "ISMQ Retries; HA",
+        "EventCode": "0x2D",
+        "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA",
         "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Miss; On NonDirty Line in I State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I",
+        "BriefDescription": "Ingress (from CMS) Occupancy; IPQ",
+        "EventCode": "0x11",
+        "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Miss; On NonDirty Line in S State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S",
+        "BriefDescription": "Ingress (from CMS) Occupancy; IRQ",
+        "EventCode": "0x11",
+        "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Miss; On NonDirty Line in L State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P",
+        "BriefDescription": "Ingress (from CMS) Occupancy; RRQ",
+        "EventCode": "0x11",
+        "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ",
         "PerPkg": "1",
+        "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
         "UMask": "0x40",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Miss; On NonDirty Line in A State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A",
+        "BriefDescription": "Ingress (from CMS) Occupancy; WBQ",
+        "EventCode": "0x11",
+        "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ",
         "PerPkg": "1",
+        "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
         "UMask": "0x80",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC; Critical Priority",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.ISOCH",
+        "BriefDescription": "Other Retries; AD REQ on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
+        "PerPkg": "1",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "Other Retries; AD RSP on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
         "PerPkg": "1",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
         "UMask": "0x2",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC; All, regardless of priority",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.FROM_TRANSGRESS",
+        "BriefDescription": "Other Retries; Non UPI AK Request",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI",
+        "PerPkg": "1",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "Other Retries; BL NCB on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
         "PerPkg": "1",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC; Full Line Non-ISOCH",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.FULL",
+        "BriefDescription": "Other Retries; BL NCS on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "M2M"
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC; ISOCH Full Line",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH",
+        "BriefDescription": "Other Retries; BL RSP on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
         "PerPkg": "1",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
         "UMask": "0x4",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC; ISOCH Partial",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH",
+        "BriefDescription": "Other Retries; BL WB on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
         "PerPkg": "1",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
         "UMask": "0x8",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.FROM_TRANSGRESS",
+        "BriefDescription": "Other Retries; Non UPI IV Request",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Packet Header Matches; Mesh Match",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M2M_PKT_MATCH.MESH",
+        "BriefDescription": "Other Retries; Allow Snoop",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "M2M"
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Packet Header Matches; MC Match",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M2M_PKT_MATCH.MC",
+        "BriefDescription": "Other Retries; ANY0",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0",
+        "PerPkg": "1",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "Other Retries; HA",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA",
         "PerPkg": "1",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
         "UMask": "0x2",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Prefetch CAM Cycles Full",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x53",
-        "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL",
+        "BriefDescription": "Other Retries; Merging these two together to make room for ANY_REJECT_*0",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Prefetch CAM Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x54",
-        "EventName": "UNC_M2M_PREFCAM_CYCLES_NE",
+        "BriefDescription": "Other Retries; LLC Victim",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Prefetch CAM Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x55",
-        "EventName": "UNC_M2M_PREFCAM_OCCUPANCY",
+        "BriefDescription": "Other Retries; PhyAddr Match",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
+        "BriefDescription": "Other Retries; SF Victim",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "M2M"
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
+        "BriefDescription": "Other Retries; Victim",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "M2M"
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "M2M"
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number AD Ingress Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x41",
-        "EventName": "UNC_M2M_TGR_AD_CREDITS",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number BL Ingress Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x42",
-        "EventName": "UNC_M2M_TGR_BL_CREDITS",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Cycles Full; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x45",
-        "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH0",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "M2M"
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Cycles Full; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x45",
-        "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH1",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "M2M"
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Cycles Full; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x45",
-        "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH2",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
         "UMask": "0x4",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Cycles Not Empty; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH0",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "M2M"
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Cycles Not Empty; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH1",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "M2M"
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Cycles Not Empty; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH2",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "M2M"
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Inserts; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x49",
-        "EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0",
         "PerPkg": "1",
         "UMask": "0x1",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Inserts; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x49",
-        "EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA",
         "PerPkg": "1",
         "UMask": "0x2",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Inserts; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x49",
-        "EventName": "UNC_M2M_TRACKER_INSERTS.CH2",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC OR SF Way",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "M2M"
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Occupancy; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x47",
-        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "M2M"
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Occupancy; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x47",
-        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "M2M"
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Occupancy; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x47",
-        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "M2M"
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data Pending Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x48",
-        "EventName": "UNC_M2M_TRACKER_PENDING_OCCUPANCY",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
+        "BriefDescription": "Request Queue Retries; AD REQ on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
         "PerPkg": "1",
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
         "UMask": "0x1",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
+        "BriefDescription": "Request Queue Retries; AD RSP on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
         "PerPkg": "1",
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
         "UMask": "0x2",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
+        "BriefDescription": "Request Queue Retries; Non UPI AK Request",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "M2M"
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Full; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH0",
+        "BriefDescription": "Request Queue Retries; BL NCB on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "M2M"
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Full; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH1",
+        "BriefDescription": "Request Queue Retries; BL NCS on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "M2M"
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Full; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH2",
+        "BriefDescription": "Request Queue Retries; BL RSP on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
         "PerPkg": "1",
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
         "UMask": "0x4",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Not Empty; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH0",
+        "BriefDescription": "Request Queue Retries; BL WB on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "M2M"
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Not Empty; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH1",
+        "BriefDescription": "Request Queue Retries; Non UPI IV Request",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "M2M"
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Not Empty; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH2",
+        "BriefDescription": "Request Queue Retries; Allow Snoop",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "M2M"
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Inserts; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x61",
-        "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH0",
+        "BriefDescription": "Request Queue Retries; ANY0",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
         "PerPkg": "1",
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
         "UMask": "0x1",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Inserts; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x61",
-        "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH1",
+        "BriefDescription": "Request Queue Retries; HA",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA",
         "PerPkg": "1",
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
         "UMask": "0x2",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Inserts; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x61",
-        "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH2",
+        "BriefDescription": "Request Queue Retries; Merging these two together to make room for ANY_REJECT_*0",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "M2M"
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Occupancy; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x60",
-        "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH0",
+        "BriefDescription": "Request Queue Retries; LLC Victim",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "M2M"
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Occupancy; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x60",
-        "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH1",
+        "BriefDescription": "Request Queue Retries; PhyAddr Match",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "M2M"
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Occupancy; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x60",
-        "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH2",
+        "BriefDescription": "Request Queue Retries; SF Victim",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "M2M"
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR0",
+        "BriefDescription": "Request Queue Retries; Victim",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR1",
+        "BriefDescription": "RRQ Rejects; AD REQ on VN0",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR2",
+        "BriefDescription": "RRQ Rejects; AD RSP on VN0",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR3",
+        "BriefDescription": "RRQ Rejects; Non UPI AK Request",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR4",
+        "BriefDescription": "RRQ Rejects; BL NCB on VN0",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR5",
+        "BriefDescription": "RRQ Rejects; BL NCS on VN0",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
         "UMask": "0x20",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR0",
+        "BriefDescription": "RRQ Rejects; BL RSP on VN0",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "RRQ Rejects; BL WB on VN0",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "RRQ Rejects; Non UPI IV Request",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "RRQ Rejects; Allow Snoop",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "RRQ Rejects; ANY0",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR5",
+        "BriefDescription": "RRQ Rejects; HA",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR0",
+        "BriefDescription": "RRQ Rejects; Merging these two together to make room for ANY_REJECT_*0",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR1",
+        "BriefDescription": "RRQ Rejects; LLC Victim",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR2",
+        "BriefDescription": "RRQ Rejects; PhyAddr Match",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR3",
+        "BriefDescription": "RRQ Rejects; SF Victim",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR4",
+        "BriefDescription": "RRQ Rejects; Victim",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR5",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR0",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "WBQ Rejects; AD REQ on VN0",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "WBQ Rejects; AD RSP on VN0",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "WBQ Rejects; Non UPI AK Request",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "WBQ Rejects; BL NCB on VN0",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR5",
+        "BriefDescription": "WBQ Rejects; BL NCS on VN0",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
         "UMask": "0x20",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR0",
+        "BriefDescription": "WBQ Rejects; BL RSP on VN0",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR1",
+        "BriefDescription": "WBQ Rejects; BL WB on VN0",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR2",
+        "BriefDescription": "WBQ Rejects; Non UPI IV Request",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR3",
+        "BriefDescription": "WBQ Rejects; Allow Snoop",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR4",
+        "BriefDescription": "WBQ Rejects; ANY0",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR5",
+        "BriefDescription": "WBQ Rejects; HA",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR0",
+        "BriefDescription": "WBQ Rejects; Merging these two together to make room for ANY_REJECT_*0",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "WBQ Rejects; LLC Victim",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "WBQ Rejects; PhyAddr Match",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "WBQ Rejects; SF Victim",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "WBQ Rejects; Victim",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR5",
+        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+        "EventCode": "0xB4",
+        "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR0",
+        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+        "EventCode": "0xB4",
+        "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+        "EventCode": "0xB4",
+        "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+        "EventCode": "0xB4",
+        "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_CHA_RxR_BYPASS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
+        "EventCode": "0xB2",
+        "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR5",
+        "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_CHA_RxR_BYPASS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR0",
+        "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_CHA_RxR_BYPASS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR1",
+        "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
+        "EventCode": "0xB2",
+        "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR2",
+        "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_CHA_RxR_BYPASS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR3",
+        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR4",
+        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+        "EventCode": "0xB3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR5",
+        "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAE",
-        "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN",
+        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAE",
-        "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP",
+        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+        "EventCode": "0xB3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
+        "EventCode": "0xB3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD",
+        "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_CHA_RxR_INSERTS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
+        "EventCode": "0xB1",
+        "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA9",
-        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_CHA_RxR_INSERTS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA9",
-        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD",
+        "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_CHA_RxR_INSERTS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA9",
-        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
+        "EventCode": "0xB1",
+        "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA9",
-        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_CHA_RxR_INSERTS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD",
+        "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
+        "EventCode": "0xB0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use; Left",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAD",
-        "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT",
+        "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
+        "EventCode": "0xB0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use; Right",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAD",
-        "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT",
+        "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD",
+        "BriefDescription": "Snoop filter capacity evictions for E-state entries.",
+        "EventCode": "0x3D",
+        "EventName": "UNC_CHA_SF_EVICTION.E_STATE",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK",
+        "BriefDescription": "Snoop filter capacity evictions for M-state entries.",
+        "EventCode": "0x3D",
+        "EventName": "UNC_CHA_SF_EVICTION.M_STATE",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL",
+        "BriefDescription": "Snoop filter capacity evictions for S-state entries.",
+        "EventCode": "0x3D",
+        "EventName": "UNC_CHA_SF_EVICTION.S_STATE",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts snoop filter capacity evictions for entries tracking shared lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV",
+        "BriefDescription": "Snoops Sent; All",
+        "EventCode": "0x51",
+        "EventName": "UNC_CHA_SNOOPS_SENT.ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of snoops issued by the HA.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD",
+        "BriefDescription": "Snoops Sent; Broadcast snoop for Local Requests",
+        "EventCode": "0x51",
+        "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast snoops issued by the HA. This filter includes only requests coming from local sockets.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK",
+        "BriefDescription": "Snoops Sent; Broadcast snoops for Remote Requests",
+        "EventCode": "0x51",
+        "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast snoops issued by the HA.This filter includes only requests coming from remote sockets.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL",
+        "BriefDescription": "Snoops Sent; Directed snoops for Local Requests",
+        "EventCode": "0x51",
+        "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of directed snoops issued by the HA. This filter includes only requests coming from local sockets.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV",
+        "BriefDescription": "Snoops Sent; Directed snoops for Remote Requests",
+        "EventCode": "0x51",
+        "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of directed snoops issued by the HA. This filter includes only requests coming from remote sockets.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD",
+        "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Local Requests",
+        "EventCode": "0x51",
+        "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the local socket.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK",
+        "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Remote Requests",
+        "EventCode": "0x51",
+        "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the remote socket.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1",
+        "BriefDescription": "RspCnflct* Snoop Responses Received",
+        "EventCode": "0x5C",
+        "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCTS",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "Counts when a a transaction with the opcode type RspCnflct* Snoop Response was received. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent. This triggers conflict resolution hardware. This covers both the opcode RspCnflct and RspCnflctWbI.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL",
+        "BriefDescription": "Snoop Responses Received; RspFwd",
+        "EventCode": "0x5C",
+        "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspFwd to a CA request.  This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV",
+        "BriefDescription": "RspI Snoop Responses Received",
+        "EventCode": "0x5C",
+        "EventName": "UNC_CHA_SNOOP_RESP.RSPI",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data).",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; AD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD",
+        "BriefDescription": "RspIFwd Snoop Responses Received",
+        "EventCode": "0x5C",
+        "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states.  This is commonly returned with RFO (the Read for Ownership issued before a write) transactions.  The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward)  states.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK",
+        "BriefDescription": "Snoop Responses Received : RspS",
+        "EventCode": "0x5C",
+        "EventName": "UNC_CHA_SNOOP_RESP.RSPS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Snoop Responses Received : RspS : Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for snoop responses of RspS.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL",
+        "BriefDescription": "RspSFwd Snoop Responses Received",
+        "EventCode": "0x5C",
+        "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy.  This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV",
+        "BriefDescription": "Rsp*Fwd*WB Snoop Responses Received",
+        "EventCode": "0x5C",
+        "EventName": "UNC_CHA_SNOOP_RESP.RSP_FWD_WB",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to its home socket, and the cacheline was forwarded to the requestor socket.  This snoop response is only used in >= 4 socket systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to its home socket to be written back to memory.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Source Throttle",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M2M_RING_SRC_THRTL",
+        "BriefDescription": "Rsp*WB Snoop Responses Received",
+        "EventCode": "0x5C",
+        "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to its home.  This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured.  This response will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AD Ingress (from CMS) Full",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL",
+        "BriefDescription": "Snoop Responses Received Local; RspCnflct",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoops responses of RspConflict to local CA requests.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AD Ingress (from CMS) Not Empty",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_M2M_RxC_AD_CYCLES_NE",
+        "BriefDescription": "Snoop Responses Received Local; RspFwd",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of RspFwd to local CA requests.  This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Ingress (from CMS) Full",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8",
-        "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL",
+        "BriefDescription": "Snoop Responses Received Local; RspI",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoops responses of RspI to local CA requests.  RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Ingress (from CMS) Not Empty",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x7",
-        "EventName": "UNC_M2M_RxC_BL_CYCLES_NE",
+        "BriefDescription": "Snoop Responses Received Local; RspIFwd",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoop responses of RspIFwd to local CA requests.  This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states.  This is commonly returned with RFO transactions.  It can be either a HitM or a HitFE.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_BNC",
+        "BriefDescription": "Snoop Responses Received Local; RspS",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoop responses of RspS to local CA requests.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD",
+        "BriefDescription": "Snoop Responses Received Local; RspSFwd",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of RspSFwd to local CA requests.  This is returned when a remote caching agent forwards data but holds on to its currentl copy.  This is common for data and code reads that hit in a remote socket in E or F state.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_BNC",
+        "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of Rsp*Fwd*WB to local CA requests.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD",
+        "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of RspIWB or RspSWB to local CA requests.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M2M_RxR_BYPASS.AD_BNC",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M2M_RxR_BYPASS.AK_BNC",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M2M_RxR_BYPASS.BL_BNC",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M2M_RxR_BYPASS.IV_BNC",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_BNC",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.AK_BNC",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_BNC",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.IV_BNC",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M2M_RxR_INSERTS.AD_BNC",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M2M_RxR_INSERTS.AK_BNC",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M2M_RxR_INSERTS.BL_BNC",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M2M_RxR_INSERTS.IV_BNC",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_BNC",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.AK_BNC",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_BNC",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.IV_BNC",
+        "BriefDescription": "TOR Inserts; All",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0xff",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+        "BriefDescription": "TOR Inserts; Hits from Local",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.ALL_HIT",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0x15",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+        "BriefDescription": "TOR Inserts; All from Local iA and IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.ALL_IO_IA",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests",
+        "UMask": "0x35",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+        "BriefDescription": "TOR Inserts; Misses from Local",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.ALL_MISS",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0x25",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+        "BriefDescription": "TOR Inserts; SF/LLC Evictions",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.EVICT",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+        "BriefDescription": "TOR Inserts; Hit (Not a Miss)",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.HIT",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; HITs (hit is defined to be not a miss [see below], as a result for any request allocated into the TOR, one of either HIT or MISS must be true)",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+        "BriefDescription": "TOR Inserts; All from Local iA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests from iA Cores",
+        "UMask": "0x31",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+        "BriefDescription": "TOR Inserts; Hits from Local iA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+        "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
+        "Filter": "config1=0x40233",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+        "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD",
+        "Filter": "config1=0x40433",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+        "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD",
+        "Filter": "config1=0x4b233",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+        "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD",
+        "Filter": "config1=0x4b433",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+        "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefRFO",
+        "Filter": "config1=0x4b033",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
+        "Filter": "config1=0x40033",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+        "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
-        "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+        "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
+        "Filter": "config1=0x40233",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+        "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD",
+        "Filter": "config1=0x40433",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+        "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD",
+        "Filter": "config1=0x4b233",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+        "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD",
+        "Filter": "config1=0x4b433",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+        "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefRFO",
+        "Filter": "config1=0x4b033",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
+        "Filter": "config1=0x40033",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+        "BriefDescription": "TOR Inserts; All from Local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally generated IO traffic",
+        "UMask": "0x34",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+        "BriefDescription": "TOR Inserts; Hits from Local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0x14",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+        "BriefDescription": "TOR Inserts; Misses from Local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0x24",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Credits Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xE",
-        "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY",
+        "BriefDescription": "TOR Inserts; ItoM misses from Local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
+        "Filter": "config1=0x49033",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO ItoM requests that miss the LLC. An ItoM request is used by IIO to request a data write without first reading the data for ownership.",
+        "UMask": "0x24",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Credit Acquired",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD",
-        "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED",
+        "BriefDescription": "TOR Inserts; RdCur misses from Local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RDCUR",
+        "Filter": "config1=0x43C33",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO RdCur requests and miss the LLC. A RdCur request is used by IIO to read data without changing state.",
+        "UMask": "0x24",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Full",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC",
-        "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL",
+        "BriefDescription": "TOR Inserts; RFO misses from Local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
+        "Filter": "config1=0x40033",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO RFO requests that miss the LLC. A read for ownership (RFO) requests a cache line to be cached in E state with the intent to modify.",
+        "UMask": "0x24",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Not Empty",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB",
-        "EventName": "UNC_M2M_TxC_AD_CYCLES_NE",
+        "BriefDescription": "TOR Inserts; IPQ",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IPQ",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles with No AD Egress (to CMS) Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xF",
-        "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IPQ_HIT",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "UMask": "0x18",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x10",
-        "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IPQ_MISS",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "UMask": "0x28",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Outbound Ring Transactions on AK; CRD Transactions to Cbo",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_M2M_TxC_AK.CRD_CBO",
+        "BriefDescription": "TOR Inserts; IRQ",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IRQ",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Outbound Ring Transactions on AK; NDR Transactions",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_M2M_TxC_AK.NDR",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x37",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1E",
-        "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS0",
+        "BriefDescription": "TOR Inserts; Miss",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.MISS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; Misses.  (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to a local memory controller, in the event that the CHA is the home node)).  Basically, if the LLC/SF/MLC complex were not able to service the request without involving another agent...it is a miss.  If only IDI snoops were required, it is not a miss (that means the SF/MLC com",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1E",
-        "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS1",
+        "BriefDescription": "TOR Inserts; PRQ",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.PRQ",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x30",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.RRQ_HIT",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x50",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1F",
-        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x60",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1F",
-        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.WBQ_HIT",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x90",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.WBQ_MISS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0xa0",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.ALL",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "UMask": "0xff",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2M_TxC_BL.DRS_CACHE",
+        "BriefDescription": "TOR Occupancy; All from Local",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All remotely generated requests",
+        "UMask": "0x37",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2M_TxC_BL.DRS_CORE",
+        "BriefDescription": "TOR Occupancy; Hits from Local",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_HIT",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0x17",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1A",
-        "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS0",
+        "BriefDescription": "TOR Occupancy; Misses from Local",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_MISS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0x27",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1A",
-        "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS1",
+        "BriefDescription": "TOR Occupancy; SF/LLC Evictions",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T; TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0",
+        "BriefDescription": "TOR Occupancy; Hit (Not a Miss)",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T; HITs (hit is defined to be not a miss [see below], as a result for any request allocated into the TOR, one of either HIT or MISS must be true)",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1",
+        "BriefDescription": "TOR Occupancy; All from Local iA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T; All locally initiated requests from iA Cores",
+        "UMask": "0x31",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Full; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL",
+        "BriefDescription": "TOR Occupancy; Hits from Local iA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
+        "Filter": "config1=0x40233",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
+        "Filter": "config1=0x40433",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Not Empty; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x17",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD",
+        "Filter": "config1=0x4b233",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x17",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD",
+        "Filter": "config1=0x4b433",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x17",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO",
+        "Filter": "config1=0x4b033",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
+        "Filter": "config1=0x40033",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1",
+        "BriefDescription": "TOR Occupancy; Misses from Local iA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1B",
-        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
+        "Filter": "config1=0x40233",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1B",
-        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1",
+        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
+        "Filter": "config1=0x40433",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD",
+        "Filter": "config1=0x4b233",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD",
+        "Filter": "config1=0x4b433",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x16",
-        "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS0",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO",
+        "Filter": "config1=0x4b033",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x16",
-        "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS1",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
+        "Filter": "config1=0x40033",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_BNC",
+        "BriefDescription": "TOR Occupancy; All from Local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T; All locally generated IO traffic",
+        "UMask": "0x34",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD",
+        "BriefDescription": "TOR Occupancy; Hits from Local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0x14",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AK_BNC",
+        "BriefDescription": "TOR Occupancy; Misses from Local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0x24",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_BNC",
+        "BriefDescription": "TOR Occupancy;  ITOM Misses from Local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
+        "Filter": "config1=0x49033",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO ItoM requests that miss the LLC. An ItoM is used by IIO to request a data write without first reading the data for ownership.",
+        "UMask": "0x24",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD",
+        "BriefDescription": "TOR Occupancy;  RDCUR isses from Local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RDCUR",
+        "Filter": "config1=0x43C33",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RdCur requests that miss the LLC. A RdCur request is used by IIO to read data without changing state.",
+        "UMask": "0x24",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9F",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_BNC",
+        "BriefDescription": "TOR Occupancy;  RFO misses from Local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
+        "Filter": "config1=0x40033",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RFO requests that miss the LLC. A read for ownership (RFO) requests data to be cached in E state with the intent to modify.",
+        "UMask": "0x24",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9F",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD",
+        "BriefDescription": "TOR Occupancy; IPQ",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9F",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK_BNC",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_HIT",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x18",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9F",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_BNC",
-        "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_MISS",
+        "PerPkg": "1",
+        "UMask": "0x28",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "TOR Occupancy; IRQ",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ",
+        "PerPkg": "1",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
+        "PerPkg": "1",
+        "UMask": "0x37",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "TOR Occupancy; Miss",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
+        "PerPkg": "1",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T; Misses.  (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to a local memory controller, in the event that the CHA is the home node)).  Basically, if the LLC/SF/MLC complex were not able to service the request without involving another agent...it is a miss.  If only IDI snoops were required, it is not a miss (that means the SF/MLC com",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "TOR Occupancy; PRQ",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
+        "PerPkg": "1",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
+        "EventCode": "0x9D",
+        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
+        "EventCode": "0x9D",
+        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD",
+        "PerPkg": "1",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
+        "EventCode": "0x9D",
+        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
+        "EventCode": "0x9D",
+        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
+        "EventCode": "0x9D",
+        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD",
+        "PerPkg": "1",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
+        "EventCode": "0x9F",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
+        "EventCode": "0x9F",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD",
+        "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
+        "EventCode": "0x9F",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce",
+        "EventCode": "0x9F",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9F",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
         "UMask": "0x40",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9F",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x40",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x97",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x97",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x97",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x97",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x97",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x40",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x97",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x95",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x95",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x95",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x95",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x95",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x40",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x95",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x99",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x99",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
         "UMask": "0x20",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x99",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.AK_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x99",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x99",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
         "UMask": "0x40",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x99",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.IV_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x40",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9B",
-        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9B",
-        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9B",
-        "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9B",
-        "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV_BNC",
+        "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9C",
-        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9C",
-        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9C",
-        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9C",
-        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
         "UMask": "0x20",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9C",
-        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9C",
-        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
         "UMask": "0x40",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9E",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9E",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9E",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9E",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
         "UMask": "0x20",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9E",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9E",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
         "UMask": "0x40",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used; IV",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9E",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
         "UMask": "0x20",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
         "UMask": "0x40",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV",
-        "Counter": "0,1,2,3",
         "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.IV",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x93",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x93",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x93",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x93",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
         "UMask": "0x20",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x93",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x93",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
         "UMask": "0x40",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV",
-        "Counter": "0,1,2,3",
         "EventCode": "0x93",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.IV",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x91",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x91",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x91",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x91",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
         "UMask": "0x20",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x91",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x91",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
         "UMask": "0x40",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Allocations; IV",
-        "Counter": "0,1,2,3",
         "EventCode": "0x91",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS.IV",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
         "UMask": "0x20",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
         "UMask": "0x40",
-        "Unit": "M2M"
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "CMS Vertical Egress NACKs; IV",
+        "EventCode": "0x98",
+        "EventName": "UNC_CHA_TxR_VERT_NACK.IV",
+        "PerPkg": "1",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
         "UMask": "0x20",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
         "UMask": "0x40",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Occupancy; IV",
-        "Counter": "0,1,2,3",
         "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.IV",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
         "UMask": "0x20",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
         "UMask": "0x40",
-        "Unit": "M2M"
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
+        "EventCode": "0x9A",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED.IV",
+        "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "UPI Ingress Credit Allocations; AD REQ Credits",
+        "EventCode": "0x38",
+        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_REQ",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "UPI Ingress Credit Allocations; AD RSP VN0 Credits",
+        "EventCode": "0x38",
+        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_RSP",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "UPI Ingress Credit Allocations; BL NCB Credits",
+        "EventCode": "0x38",
+        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCB",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "UPI Ingress Credit Allocations; BL NCS Credits",
+        "EventCode": "0x38",
+        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCS",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x80",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "UPI Ingress Credit Allocations; BL RSP Credits",
+        "EventCode": "0x38",
+        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_RSP",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "UPI Ingress Credit Allocations; BL DRS Credits",
+        "EventCode": "0x38",
+        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_WB",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "UPI Ingress Credit Allocations; VN0 Credits",
+        "EventCode": "0x38",
+        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VN0",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "UPI Ingress Credit Allocations; VNA Credits",
+        "EventCode": "0x38",
+        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VNA",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "UPI Ingress Credits In Use Cycles; AD REQ VN0 Credits",
+        "EventCode": "0x3B",
+        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_REQ",
+        "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "UPI Ingress Credits In Use Cycles; AD RSP VN0 Credits",
+        "EventCode": "0x3B",
+        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_RSP",
+        "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCB VN0 Credits",
+        "EventCode": "0x3B",
+        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCB",
+        "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCS VN0 Credits",
+        "EventCode": "0x3B",
+        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCS",
+        "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x80",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "UPI Ingress Credits In Use Cycles; BL RSP VN0 Credits",
+        "EventCode": "0x3B",
+        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_RSP",
+        "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "UPI Ingress Credits In Use Cycles; BL DRS VN0 Credits",
+        "EventCode": "0x3B",
+        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_WB",
+        "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "UPI Ingress Credits In Use Cycles; AD VNA Credits",
+        "EventCode": "0x3B",
+        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_AD",
+        "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "UPI Ingress Credits In Use Cycles; BL VNA Credits",
+        "EventCode": "0x3B",
+        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_BL",
+        "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical AD Ring In Use; Down and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA6",
-        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN",
+        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical AD Ring In Use; Down and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA6",
-        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD",
+        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical AD Ring In Use; Up and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA6",
-        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN",
+        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical AD Ring In Use; Up and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA6",
-        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD",
+        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical AK Ring In Use; Down and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA8",
-        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN",
+        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical AK Ring In Use; Down and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA8",
-        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD",
+        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical AK Ring In Use; Up and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA8",
-        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN",
+        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical AK Ring In Use; Up and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA8",
-        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD",
+        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical BL Ring in Use; Down and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAA",
-        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN",
+        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical BL Ring in Use; Down and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAA",
-        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD",
+        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical BL Ring in Use; Up and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAA",
-        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN",
+        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical BL Ring in Use; Up and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAA",
-        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD",
+        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical IV Ring in Use; Down",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAC",
-        "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN",
+        "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical IV Ring in Use; Up",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAC",
-        "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP",
+        "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_TxC_BL.DRS_UPI",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x40",
-        "EventName": "UNC_NoUnit_TxC_BL.DRS_UPI",
+        "BriefDescription": "WbPushMtoI; Pushed to LLC",
+        "EventCode": "0x56",
+        "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of times when the CHA was received WbPushMtoI; Counts the number of times when the CHA was able to push WbPushMToI to LLC",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0",
+        "BriefDescription": "WbPushMtoI; Pushed to Memory",
+        "EventCode": "0x56",
+        "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of times when the CHA was received WbPushMtoI; Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM)",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC0_SMI2",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 2 only.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2",
-        "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2M_TxC_BL.DRS_UPI",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC1_SMI3",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 3 only.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK.IV",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC2_SMI4",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 4 only.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED.IV",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC3_SMI5",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 5 only.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC0_SMI0",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 0 only.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC1_SMI1",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 1 only.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2",
+        "BriefDescription": "Core Cross Snoop Responses; Any RspIFwdFE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response I to Fwd F/E",
+        "UMask": "0xe4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M to iMC Bypass; Taken",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN",
+        "BriefDescription": "Core Cross Snoop Responses",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response I to Fwd M",
+        "UMask": "0xf0",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M to iMC Bypass; Not Taken",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN",
+        "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdFE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response S to Fwd F/E",
+        "UMask": "0xe2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Clockticks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_M2M_CMS_CLOCKTICKS",
+        "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdM",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response S to Fwd M",
+        "UMask": "0xe8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN0",
+        "BriefDescription": "Core Cross Snoop Responses; Any RspHitFSE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response any to Hit F/S/E",
+        "UMask": "0xe1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN1",
+        "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdFE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response I to Fwd F/E",
+        "UMask": "0x44",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN2",
+        "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdM",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response I to Fwd M",
+        "UMask": "0x50",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "FaST wire asserted; Vertical",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M2M_FAST_ASSERTED.VERT",
+        "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdFE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response S to Fwd F/E",
+        "UMask": "0x42",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "FaST wire asserted; Horizontal",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M2M_FAST_ASSERTED.HORZ",
+        "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdM",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response S to Fwd M",
+        "UMask": "0x48",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x43",
-        "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN0",
+        "BriefDescription": "Core Cross Snoop Responses; Core RspHitFSE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response any to Hit F/S/E",
+        "UMask": "0x41",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x43",
-        "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN1",
+        "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdFE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response I to Fwd F/E",
+        "UMask": "0x84",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x43",
-        "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN2",
+        "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdM",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response I to Fwd M",
+        "UMask": "0x90",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Clean line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode and regular reads to DRAM in 1LM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2C",
-        "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN",
+        "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdFE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response S to Fwd F/E",
+        "UMask": "0x82",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0",
+        "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdM",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response S to Fwd M",
+        "UMask": "0x88",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1",
+        "BriefDescription": "Core Cross Snoop Responses; Evict RspHitFSE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response any to Hit F/S/E",
+        "UMask": "0x81",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0",
+        "BriefDescription": "Core Cross Snoop Responses; External RspIFwdFE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response I to Fwd F/E",
+        "UMask": "0x24",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0",
+        "BriefDescription": "Core Cross Snoop Responses; External RspIFwdM",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response I to Fwd M",
+        "UMask": "0x30",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0",
+        "BriefDescription": "Core Cross Snoop Responses; External RspSFwdFE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response S to Fwd F/E",
+        "UMask": "0x22",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1",
+        "BriefDescription": "Core Cross Snoop Responses; External RspSFwdM",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM",
         "PerPkg": "1",
-        "UMask": "0x88",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response S to Fwd M",
+        "UMask": "0x28",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1",
+        "BriefDescription": "Core Cross Snoop Responses; External RspHitFSE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE",
         "PerPkg": "1",
-        "UMask": "0x90",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response any to Hit F/S/E",
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CLOCKTICKS",
+        "Deprecated": "1",
+        "EventName": "UNC_C_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0xA0",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_FAST_ASSERTED.HORZ",
+        "Deprecated": "1",
+        "EventCode": "0xA5",
+        "EventName": "UNC_C_FAST_ASSERTED",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.ANY",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_C_LLC_LOOKUP.ANY",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x3",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty; Read Credit Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOCAL",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_C_LLC_LOOKUP.LOCAL",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "UMask": "0x31",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty; Write Credit Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_C_LLC_LOOKUP.REMOTE",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "UMask": "0x91",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty; Write Compare Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "UMask": "0x9",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITE",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_C_LLC_LOOKUP.WRITE",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "UMask": "0x5",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E",
+        "Deprecated": "1",
+        "EventCode": "0x37",
+        "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F",
+        "Deprecated": "1",
+        "EventCode": "0x37",
+        "EventName": "UNC_C_LLC_VICTIMS.F_STATE",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations; Read Credit Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
+        "Deprecated": "1",
+        "EventCode": "0x37",
+        "EventName": "UNC_C_LLC_VICTIMS.LOCAL",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "UMask": "0x2f",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations; Write Credit Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M",
+        "Deprecated": "1",
+        "EventCode": "0x37",
+        "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations; Write Compare Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
+        "Deprecated": "1",
+        "EventCode": "0x37",
+        "EventName": "UNC_C_LLC_VICTIMS.REMOTE",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations; Prefetch Read Cam Hit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S",
+        "Deprecated": "1",
+        "EventCode": "0x37",
+        "EventName": "UNC_C_LLC_VICTIMS.S_STATE",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SRC_THRTL",
+        "Deprecated": "1",
+        "EventCode": "0xA4",
+        "EventName": "UNC_C_RING_SRC_THRTL",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.EVICT",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.EVICT",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.HIT",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.HIT",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy; Read Credit Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IPQ",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.IPQ",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy; Write Credit Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.IPQ_HIT",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "UMask": "0x18",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy; Write Compare Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.IPQ_MISS",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "UMask": "0x28",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.IRQ",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "UMask": "0x31",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Sideband",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6B",
-        "EventName": "UNC_M2M_TxC_AK_SIDEBAND.RD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.IRQ_HIT",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Sideband",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6B",
-        "EventName": "UNC_M2M_TxC_AK_SIDEBAND.WR",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.IRQ_MISS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M-&gt;iMC RPQ Cycles w/Credits - Regular; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN0",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.LOC_ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x37",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M-&gt;iMC RPQ Cycles w/Credits - Regular; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.LOC_IA",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x31",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M-&gt;iMC RPQ Cycles w/Credits - Regular; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN2",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.LOC_IO",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "UMask": "0x34",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M-&gt;iMC WPQ Cycles w/Credits - Regular; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x51",
-        "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.MISS",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.MISS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M-&gt;iMC WPQ Cycles w/Credits - Regular; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x51",
-        "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.PRQ",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.PRQ",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M-&gt;iMC WPQ Cycles w/Credits - Regular; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x51",
-        "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN2",
-        "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_HIT",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.PRQ_HIT",
+        "PerPkg": "1",
+        "UMask": "0x14",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA to iMC Bypass; Taken",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x57",
-        "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_MISS",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.PRQ_MISS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x24",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA to iMC Bypass; Intermediate bypass Taken",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x57",
-        "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.REM_ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x30",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA to iMC Bypass; Not Taken",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x57",
-        "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.RRQ_HIT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x50",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued; Single External Snoops",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.EXT_ONE",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.RRQ_MISS",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "UMask": "0x60",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued; Single Core Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.CORE_ONE",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.WBQ_HIT",
         "PerPkg": "1",
-        "UMask": "0x41",
+        "UMask": "0x90",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued; Single Eviction",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.WBQ_MISS",
         "PerPkg": "1",
-        "UMask": "0x81",
+        "UMask": "0xa0",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued; Any Single Snoop",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.ANY_ONE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.EVICT",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.EVICT",
         "PerPkg": "1",
-        "UMask": "0xE1",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued; Multiple External Snoops",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.HIT",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.HIT",
         "PerPkg": "1",
-        "UMask": "0x22",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued; Any Cycle with Multiple Snoops",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IPQ",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.IPQ",
         "PerPkg": "1",
-        "UMask": "0xE2",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued; External Snoop to Remote Node",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.EXT_REMOTE",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_HIT",
         "PerPkg": "1",
-        "UMask": "0x24",
+        "UMask": "0x18",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued; Core Request to Remote Node",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.CORE_REMOTE",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_MISS",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "UMask": "0x28",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued; Eviction to Remote Node",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.EVICT_REMOTE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.IRQ",
         "PerPkg": "1",
-        "UMask": "0x84",
+        "UMask": "0x31",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued; Any Snoop to Remote Node",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.ANY_REMOTE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_HIT",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_HIT",
         "PerPkg": "1",
-        "UMask": "0xE4",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counter 0 Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1F",
-        "EventName": "UNC_CHA_COUNTER0_OCCUPANCY",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_MISS",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_MISS",
         "PerPkg": "1",
+        "UMask": "0x21",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; Shared hit and op is RdInvOwn, RdInv, Inv*",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5F",
-        "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.LOC_ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x37",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5F",
-        "EventName": "UNC_CHA_HITME_HIT.WBMTOE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IA",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x31",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5F",
-        "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IO",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x34",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5E",
-        "EventName": "UNC_CHA_HITME_LOOKUP.READ",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.MISS",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.MISS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5E",
-        "EventName": "UNC_CHA_HITME_LOOKUP.WRITE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.PRQ",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.PRQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of Misses in HitMe Cache; SF/LLC HitS/F and op is RdInvOwn",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x60",
-        "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_HIT",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_HIT",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x14",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of Misses in HitMe Cache; No SF/LLC HitS/F and op is RdInvOwn",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x60",
-        "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_MISS",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_MISS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x24",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of Misses in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x60",
-        "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0",
+        "Deprecated": "1",
+        "EventCode": "0x80",
+        "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x61",
-        "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1",
+        "Deprecated": "1",
+        "EventCode": "0x80",
+        "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x61",
-        "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2",
+        "Deprecated": "1",
+        "EventCode": "0x80",
+        "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache to SHARed",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x61",
-        "EventName": "UNC_CHA_HITME_UPDATE.SHARED",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3",
+        "Deprecated": "1",
+        "EventCode": "0x80",
+        "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache on RdInvOwn even if not RspFwdI*",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x61",
-        "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4",
+        "Deprecated": "1",
+        "EventCode": "0x80",
+        "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Deallocate HtiME$ on Reads without RspFwdI*",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x61",
-        "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5",
+        "Deprecated": "1",
+        "EventCode": "0x80",
+        "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "HA to iMC Reads Issued; ISOCH",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x59",
-        "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0",
+        "Deprecated": "1",
+        "EventCode": "0x82",
+        "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Writes Issued to the iMC by the HA; Partial Non-ISOCH",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5B",
-        "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1",
+        "Deprecated": "1",
+        "EventCode": "0x82",
+        "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Full Line",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5B",
-        "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2",
+        "Deprecated": "1",
+        "EventCode": "0x82",
+        "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Partial",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5B",
-        "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3",
+        "Deprecated": "1",
+        "EventCode": "0x82",
+        "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Writes Issued to the iMC by the HA; Full Line MIG",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5B",
-        "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_MIG",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4",
+        "Deprecated": "1",
+        "EventCode": "0x82",
+        "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Writes Issued to the iMC by the HA; Partial MIG",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5B",
-        "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5",
+        "Deprecated": "1",
+        "EventCode": "0x82",
+        "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x62",
-        "EventName": "UNC_CHA_IODC_ALLOC.INVITOM",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0",
+        "Deprecated": "1",
+        "EventCode": "0x88",
+        "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations dropped due to IODC Full",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x62",
-        "EventName": "UNC_CHA_IODC_ALLOC.IODCFULL",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1",
+        "Deprecated": "1",
+        "EventCode": "0x88",
+        "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IDOC allocation dropped due to OSB gate",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x62",
-        "EventName": "UNC_CHA_IODC_ALLOC.OSBGATED",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2",
+        "Deprecated": "1",
+        "EventCode": "0x88",
+        "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x63",
-        "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3",
+        "Deprecated": "1",
+        "EventCode": "0x88",
+        "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x63",
-        "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOI",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4",
+        "Deprecated": "1",
+        "EventCode": "0x88",
+        "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbPushMtoI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x63",
-        "EventName": "UNC_CHA_IODC_DEALLOC.WBPUSHMTOI",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5",
+        "Deprecated": "1",
+        "EventCode": "0x88",
+        "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to conflicting transaction",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x63",
-        "EventName": "UNC_CHA_IODC_DEALLOC.SNPOUT",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0",
+        "Deprecated": "1",
+        "EventCode": "0x8A",
+        "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to any reason",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x63",
-        "EventName": "UNC_CHA_IODC_DEALLOC.ALL",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1",
+        "Deprecated": "1",
+        "EventCode": "0x8A",
+        "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITE",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2",
         "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_C_LLC_LOOKUP.WRITE",
+        "EventCode": "0x8A",
+        "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.ANY",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3",
         "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_C_LLC_LOOKUP.ANY",
+        "EventCode": "0x8A",
+        "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOCAL",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4",
         "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_C_LLC_LOOKUP.LOCAL",
+        "EventCode": "0x8A",
+        "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
-        "UMask": "0x31",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5",
         "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_C_LLC_LOOKUP.REMOTE",
+        "EventCode": "0x8A",
+        "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
-        "UMask": "0x91",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0",
         "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_C_LLC_VICTIMS.LOCAL",
+        "EventCode": "0x84",
+        "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "UMask": "0x2f",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1",
         "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_C_LLC_VICTIMS.REMOTE",
+        "EventCode": "0x84",
+        "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2",
+        "Deprecated": "1",
+        "EventCode": "0x84",
+        "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cbo Misc; Write Combining Aliasing",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_CHA_MISC.WC_ALIASING",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3",
+        "Deprecated": "1",
+        "EventCode": "0x84",
+        "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cbo Misc; CV0 Prefetch Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_CHA_MISC.CV0_PREF_VIC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4",
+        "Deprecated": "1",
+        "EventCode": "0x84",
+        "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cbo Misc; CV0 Prefetch Miss",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_CHA_MISC.CV0_PREF_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5",
+        "Deprecated": "1",
+        "EventCode": "0x84",
+        "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "OSB Snoop Broadcast",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x55",
-        "EventName": "UNC_CHA_OSB",
-        "PerPkg": "1",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC0_SMI0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC0_SMI0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0",
+        "Deprecated": "1",
+        "EventCode": "0x86",
+        "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC1_SMI1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC1_SMI1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1",
+        "Deprecated": "1",
+        "EventCode": "0x86",
+        "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC0_SMI2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.EDC0_SMI2",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2",
+        "Deprecated": "1",
+        "EventCode": "0x86",
+        "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC1_SMI3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.EDC1_SMI3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3",
+        "Deprecated": "1",
+        "EventCode": "0x86",
+        "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC2_SMI4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.EDC2_SMI4",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4",
+        "Deprecated": "1",
+        "EventCode": "0x86",
+        "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC3_SMI5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.EDC3_SMI5",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5",
+        "Deprecated": "1",
+        "EventCode": "0x86",
+        "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "write requests from remote home agent",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0",
+        "Deprecated": "1",
+        "EventCode": "0x8E",
+        "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.ALL",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1",
         "Deprecated": "1",
-        "EventCode": "0x51",
-        "EventName": "UNC_H_SNOOPS_SENT.",
+        "EventCode": "0x8E",
+        "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Local Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x51",
-        "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2",
+        "Deprecated": "1",
+        "EventCode": "0x8E",
+        "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Remote Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x51",
-        "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3",
+        "Deprecated": "1",
+        "EventCode": "0x8E",
+        "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4",
         "Deprecated": "1",
-        "EventCode": "0x51",
-        "EventName": "UNC_H_SNOOPS_SENT.BCST_LOC",
+        "EventCode": "0x8E",
+        "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_REMOTE",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5",
         "Deprecated": "1",
-        "EventCode": "0x51",
-        "EventName": "UNC_H_SNOOPS_SENT.BCST_REM",
+        "EventCode": "0x8E",
+        "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0",
         "Deprecated": "1",
-        "EventCode": "0x51",
-        "EventName": "UNC_H_SNOOPS_SENT.DIRECT_LOC",
+        "EventCode": "0x8C",
+        "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1",
         "Deprecated": "1",
-        "EventCode": "0x51",
-        "EventName": "UNC_H_SNOOPS_SENT.DIRECT_REM",
+        "EventCode": "0x8C",
+        "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received : RspS",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5C",
-        "EventName": "UNC_CHA_SNOOP_RESP.RSPS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2",
+        "Deprecated": "1",
+        "EventCode": "0x8C",
+        "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_WBWB",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3",
         "Deprecated": "1",
-        "EventCode": "0x5C",
-        "EventName": "UNC_H_SNOOP_RESP.RSP_WB",
+        "EventCode": "0x8C",
+        "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR3",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received; RspFwd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5C",
-        "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4",
+        "Deprecated": "1",
+        "EventCode": "0x8C",
+        "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR4",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5",
         "Deprecated": "1",
-        "EventCode": "0x5D",
-        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPI",
+        "EventCode": "0x8C",
+        "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR5",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
         "Deprecated": "1",
-        "EventCode": "0x5D",
-        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPS",
+        "EventCode": "0x57",
+        "EventName": "UNC_H_BYPASS_CHA_IMC.INTERMEDIATE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
         "Deprecated": "1",
-        "EventCode": "0x5D",
-        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPIFWD",
+        "EventCode": "0x57",
+        "EventName": "UNC_H_BYPASS_CHA_IMC.NOT_TAKEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.TAKEN",
         "Deprecated": "1",
-        "EventCode": "0x5D",
-        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPSFWD",
+        "EventCode": "0x57",
+        "EventName": "UNC_H_BYPASS_CHA_IMC.TAKEN",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CMS_CLOCKTICKS",
         "Deprecated": "1",
-        "EventCode": "0x5D",
-        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_WB",
+        "EventCode": "0xC0",
+        "EventName": "UNC_H_CLOCK",
         "PerPkg": "1",
-        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C1_STATE",
         "Deprecated": "1",
-        "EventCode": "0x5D",
-        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_FWD_WB",
+        "EventCode": "0x17",
+        "EventName": "UNC_H_CORE_PMA.C1_STATE",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C1_TRANSITION",
         "Deprecated": "1",
-        "EventCode": "0x5D",
-        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPCNFLCT",
+        "EventCode": "0x17",
+        "EventName": "UNC_H_CORE_PMA.C1_TRANSITION",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C6_STATE",
         "Deprecated": "1",
-        "EventCode": "0x5D",
-        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPFWD",
+        "EventCode": "0x17",
+        "EventName": "UNC_H_CORE_PMA.C6_STATE",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.EVICT",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C6_TRANSITION",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.EVICT",
+        "EventCode": "0x17",
+        "EventName": "UNC_H_CORE_PMA.C6_TRANSITION",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.PRQ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.GV",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.PRQ",
+        "EventCode": "0x17",
+        "EventName": "UNC_H_CORE_PMA.GV",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IPQ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_GTONE",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.IPQ",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.ANY_GTONE",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0xe2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.HIT",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_ONE",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.HIT",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.ANY_ONE",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0xe1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.MISS",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_REMOTE",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.MISS",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.ANY_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0xe4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.EVICT",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE",
         "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.EVICT",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.CORE_GTONE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x42",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.PRQ",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_ONE",
         "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.PRQ",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.CORE_ONE",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x41",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IPQ",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_REMOTE",
         "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.IPQ",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.CORE_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x44",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.HIT",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE",
         "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.HIT",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.EVICT_GTONE",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x82",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_ONE",
         "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.MISS",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.EVICT_ONE",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x81",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WbPushMtoI; Pushed to LLC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x56",
-        "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_REMOTE",
+        "Deprecated": "1",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.EVICT_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x84",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WbPushMtoI; Pushed to Memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x56",
-        "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_GTONE",
+        "Deprecated": "1",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.EXT_GTONE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x22",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC0_SMI0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_ONE",
+        "Deprecated": "1",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.EXT_ONE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x21",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC1_SMI1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_REMOTE",
+        "Deprecated": "1",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.EXT_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x24",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC0_SMI2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_COUNTER0_OCCUPANCY",
+        "Deprecated": "1",
+        "EventCode": "0x1F",
+        "EventName": "UNC_H_COUNTER0_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC1_SMI3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP",
+        "Deprecated": "1",
+        "EventCode": "0x53",
+        "EventName": "UNC_H_DIR_LOOKUP.NO_SNP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC2_SMI4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP",
+        "Deprecated": "1",
+        "EventCode": "0x53",
+        "EventName": "UNC_H_DIR_LOOKUP.SNP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC3_SMI5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA",
+        "Deprecated": "1",
+        "EventCode": "0x54",
+        "EventName": "UNC_H_DIR_UPDATE.HA",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.LOC_IO",
+        "EventCode": "0x54",
+        "EventName": "UNC_H_DIR_UPDATE.TOR",
         "PerPkg": "1",
-        "UMask": "0x34",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.LOC_IA",
+        "EventCode": "0xAE",
+        "EventName": "UNC_H_EGRESS_ORDERING.IV_SNOOPGO_DN",
         "PerPkg": "1",
-        "UMask": "0x31",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.LOC_ALL",
+        "EventCode": "0xAE",
+        "EventName": "UNC_H_EGRESS_ORDERING.IV_SNOOPGO_UP",
         "PerPkg": "1",
-        "UMask": "0x37",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS",
         "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IO",
+        "EventCode": "0x5F",
+        "EventName": "UNC_H_HITME_HIT.EX_RDS",
         "PerPkg": "1",
-        "UMask": "0x34",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.SHARED_OWNREQ",
         "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IA",
+        "EventCode": "0x5F",
+        "EventName": "UNC_H_HITME_HIT.SHARED_OWNREQ",
         "PerPkg": "1",
-        "UMask": "0x31",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.WBMTOE",
         "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.LOC_ALL",
+        "EventCode": "0x5F",
+        "EventName": "UNC_H_HITME_HIT.WBMTOE",
         "PerPkg": "1",
-        "UMask": "0x37",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core PMA Events; C1  State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x17",
-        "EventName": "UNC_CHA_CORE_PMA.C1_STATE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.WBMTOI_OR_S",
+        "Deprecated": "1",
+        "EventCode": "0x5F",
+        "EventName": "UNC_H_HITME_HIT.WBMTOI_OR_S",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core PMA Events; C1 Transition",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x17",
-        "EventName": "UNC_CHA_CORE_PMA.C1_TRANSITION",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_LOOKUP.READ",
+        "Deprecated": "1",
+        "EventCode": "0x5E",
+        "EventName": "UNC_H_HITME_LOOKUP.READ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core PMA Events; C6 State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x17",
-        "EventName": "UNC_CHA_CORE_PMA.C6_STATE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_LOOKUP.WRITE",
+        "Deprecated": "1",
+        "EventCode": "0x5E",
+        "EventName": "UNC_H_HITME_LOOKUP.WRITE",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core PMA Events; C6 Transition",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x17",
-        "EventName": "UNC_CHA_CORE_PMA.C6_TRANSITION",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN",
+        "Deprecated": "1",
+        "EventCode": "0x60",
+        "EventName": "UNC_H_HITME_MISS.NOTSHARED_RDINVOWN",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core PMA Events; GV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x17",
-        "EventName": "UNC_CHA_CORE_PMA.GV",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.READ_OR_INV",
+        "Deprecated": "1",
+        "EventCode": "0x60",
+        "EventName": "UNC_H_HITME_MISS.READ_OR_INV",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.SHARED_RDINVOWN",
+        "Deprecated": "1",
+        "EventCode": "0x60",
+        "EventName": "UNC_H_HITME_MISS.SHARED_RDINVOWN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.DEALLOCATE",
+        "Deprecated": "1",
+        "EventCode": "0x61",
+        "EventName": "UNC_H_HITME_UPDATE.DEALLOCATE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
+        "Deprecated": "1",
+        "EventCode": "0x61",
+        "EventName": "UNC_H_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.RDINVOWN",
+        "Deprecated": "1",
+        "EventCode": "0x61",
+        "EventName": "UNC_H_HITME_UPDATE.RDINVOWN",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.RSPFWDI_REM",
+        "Deprecated": "1",
+        "EventCode": "0x61",
+        "EventName": "UNC_H_HITME_UPDATE.RSPFWDI_REM",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.SHARED",
+        "Deprecated": "1",
+        "EventCode": "0x61",
+        "EventName": "UNC_H_HITME_UPDATE.SHARED",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+        "Deprecated": "1",
+        "EventCode": "0xA7",
+        "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD",
+        "Deprecated": "1",
+        "EventCode": "0xA7",
+        "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+        "Deprecated": "1",
+        "EventCode": "0xA7",
+        "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+        "Deprecated": "1",
+        "EventCode": "0xA7",
+        "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+        "Deprecated": "1",
+        "EventCode": "0xA9",
+        "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD",
+        "Deprecated": "1",
+        "EventCode": "0xA9",
+        "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+        "Deprecated": "1",
+        "EventCode": "0xA9",
+        "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1",
-        "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2",
-        "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3",
-        "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+        "Deprecated": "1",
+        "EventCode": "0xA9",
+        "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+        "Deprecated": "1",
+        "EventCode": "0xAB",
+        "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD",
+        "Deprecated": "1",
+        "EventCode": "0xAB",
+        "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+        "Deprecated": "1",
+        "EventCode": "0xAB",
+        "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+        "Deprecated": "1",
+        "EventCode": "0xAB",
+        "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_IV_IN_USE.LEFT",
+        "Deprecated": "1",
+        "EventCode": "0xAD",
+        "EventName": "UNC_H_HORZ_RING_IV_IN_USE.LEFT",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT",
+        "Deprecated": "1",
+        "EventCode": "0xAD",
+        "EventName": "UNC_H_HORZ_RING_IV_IN_USE.RIGHT",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_READS_COUNT.NORMAL",
+        "Deprecated": "1",
+        "EventCode": "0x59",
+        "EventName": "UNC_H_IMC_READS_COUNT.NORMAL",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_READS_COUNT.PRIORITY",
+        "Deprecated": "1",
+        "EventCode": "0x59",
+        "EventName": "UNC_H_IMC_READS_COUNT.PRIORITY",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL",
+        "Deprecated": "1",
+        "EventCode": "0x5B",
+        "EventName": "UNC_H_IMC_WRITES_COUNT.FULL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL_MIG",
+        "Deprecated": "1",
+        "EventCode": "0x5B",
+        "EventName": "UNC_H_IMC_WRITES_COUNT.FULL_MIG",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
+        "Deprecated": "1",
+        "EventCode": "0x5B",
+        "EventName": "UNC_H_IMC_WRITES_COUNT.FULL_PRIORITY",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
+        "Deprecated": "1",
+        "EventCode": "0x5B",
+        "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG",
+        "Deprecated": "1",
+        "EventCode": "0x5B",
+        "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL_MIG",
         "PerPkg": "1",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
+        "Deprecated": "1",
+        "EventCode": "0x5B",
+        "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.INVITOM",
+        "Deprecated": "1",
+        "EventCode": "0x62",
+        "EventName": "UNC_H_IODC_ALLOC.INVITOM",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.IODCFULL",
+        "Deprecated": "1",
+        "EventCode": "0x62",
+        "EventName": "UNC_H_IODC_ALLOC.IODCFULL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.OSBGATED",
+        "Deprecated": "1",
+        "EventCode": "0x62",
+        "EventName": "UNC_H_IODC_ALLOC.OSBGATED",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.ALL",
+        "Deprecated": "1",
+        "EventCode": "0x63",
+        "EventName": "UNC_H_IODC_DEALLOC.ALL",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.SNPOUT",
+        "Deprecated": "1",
+        "EventCode": "0x63",
+        "EventName": "UNC_H_IODC_DEALLOC.SNPOUT",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBMTOE",
+        "Deprecated": "1",
+        "EventCode": "0x63",
+        "EventName": "UNC_H_IODC_DEALLOC.WBMTOE",
         "PerPkg": "1",
         "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBMTOI",
+        "Deprecated": "1",
+        "EventCode": "0x63",
+        "EventName": "UNC_H_IODC_DEALLOC.WBMTOI",
         "PerPkg": "1",
         "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBPUSHMTOI",
+        "Deprecated": "1",
+        "EventCode": "0x63",
+        "EventName": "UNC_H_IODC_DEALLOC.WBPUSHMTOI",
         "PerPkg": "1",
         "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.CV0_PREF_MISS",
+        "Deprecated": "1",
+        "EventCode": "0x39",
+        "EventName": "UNC_H_MISC.CV0_PREF_MISS",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.CV0_PREF_VIC",
+        "Deprecated": "1",
+        "EventCode": "0x39",
+        "EventName": "UNC_H_MISC.CV0_PREF_VIC",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S",
+        "Deprecated": "1",
+        "EventCode": "0x39",
+        "EventName": "UNC_H_MISC.RFO_HIT_S",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RSPI_WAS_FSE",
+        "Deprecated": "1",
+        "EventCode": "0x39",
+        "EventName": "UNC_H_MISC.RSPI_WAS_FSE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.WC_ALIASING",
+        "Deprecated": "1",
+        "EventCode": "0x39",
+        "EventName": "UNC_H_MISC.WC_ALIASING",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_OSB",
+        "Deprecated": "1",
+        "EventCode": "0x55",
+        "EventName": "UNC_H_OSB",
         "PerPkg": "1",
-        "UMask": "0x04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC0_SMI2",
+        "Deprecated": "1",
+        "EventCode": "0x58",
+        "EventName": "UNC_H_READ_NO_CREDITS.EDC0_SMI2",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC1_SMI3",
+        "Deprecated": "1",
+        "EventCode": "0x58",
+        "EventName": "UNC_H_READ_NO_CREDITS.EDC1_SMI3",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC2_SMI4",
+        "Deprecated": "1",
+        "EventCode": "0x58",
+        "EventName": "UNC_H_READ_NO_CREDITS.EDC2_SMI4",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CMS_CLOCKTICKS",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC3_SMI5",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_H_CLOCK",
+        "EventCode": "0x58",
+        "EventName": "UNC_H_READ_NO_CREDITS.EDC3_SMI5",
         "PerPkg": "1",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAE",
-        "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.MC0_SMI0",
+        "Deprecated": "1",
+        "EventCode": "0x58",
+        "EventName": "UNC_H_READ_NO_CREDITS.MC0_SMI0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAE",
-        "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.MC1_SMI1",
+        "Deprecated": "1",
+        "EventCode": "0x58",
+        "EventName": "UNC_H_READ_NO_CREDITS.MC1_SMI1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA7",
-        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL",
+        "Deprecated": "1",
+        "EventCode": "0x50",
+        "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA7",
-        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE",
+        "Deprecated": "1",
+        "EventCode": "0x50",
+        "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA7",
-        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "read requests from home agent",
+        "Deprecated": "1",
+        "EventCode": "0x50",
+        "EventName": "UNC_H_REQUESTS.READS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x3",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA7",
-        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD",
-        "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA9",
-        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA9",
-        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD",
-        "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA9",
-        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
-        "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA9",
-        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD",
-        "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAB",
-        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAB",
-        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD",
+        "BriefDescription": "read requests from local home agent",
+        "Deprecated": "1",
+        "EventCode": "0x50",
+        "EventName": "UNC_H_REQUESTS.READS_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAB",
-        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "read requests from remote home agent",
+        "Deprecated": "1",
+        "EventCode": "0x50",
+        "EventName": "UNC_H_REQUESTS.READS_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAB",
-        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+        "BriefDescription": "write requests from home agent",
+        "Deprecated": "1",
+        "EventCode": "0x50",
+        "EventName": "UNC_H_REQUESTS.WRITES",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0xc",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use; Left",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAD",
-        "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT",
+        "BriefDescription": "write requests from local home agent",
+        "Deprecated": "1",
+        "EventCode": "0x50",
+        "EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use; Right",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAD",
-        "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT",
+        "BriefDescription": "write requests from remote home agent",
+        "Deprecated": "1",
+        "EventCode": "0x50",
+        "EventName": "UNC_H_REQUESTS.WRITES_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.AD",
+        "Deprecated": "1",
         "EventCode": "0xA1",
-        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD",
+        "EventName": "UNC_H_RING_BOUNCES_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.AK",
+        "Deprecated": "1",
         "EventCode": "0xA1",
-        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK",
+        "EventName": "UNC_H_RING_BOUNCES_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.BL",
+        "Deprecated": "1",
         "EventCode": "0xA1",
-        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL",
+        "EventName": "UNC_H_RING_BOUNCES_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.IV",
+        "Deprecated": "1",
         "EventCode": "0xA1",
-        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV",
+        "EventName": "UNC_H_RING_BOUNCES_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.AD",
+        "Deprecated": "1",
         "EventCode": "0xA0",
-        "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD",
+        "EventName": "UNC_H_RING_BOUNCES_VERT.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.AK",
+        "Deprecated": "1",
         "EventCode": "0xA0",
-        "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK",
+        "EventName": "UNC_H_RING_BOUNCES_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.BL",
+        "Deprecated": "1",
         "EventCode": "0xA0",
-        "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL",
+        "EventName": "UNC_H_RING_BOUNCES_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.IV",
+        "Deprecated": "1",
         "EventCode": "0xA0",
-        "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV",
+        "EventName": "UNC_H_RING_BOUNCES_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AD",
+        "Deprecated": "1",
         "EventCode": "0xA3",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD",
+        "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AK",
+        "Deprecated": "1",
         "EventCode": "0xA3",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK",
+        "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1",
+        "Deprecated": "1",
         "EventCode": "0xA3",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL",
+        "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.BL",
+        "Deprecated": "1",
         "EventCode": "0xA3",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV",
+        "EventName": "UNC_H_RING_SINK_STARVED_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.IV",
+        "Deprecated": "1",
         "EventCode": "0xA3",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1",
+        "EventName": "UNC_H_RING_SINK_STARVED_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; AD",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.AD",
+        "Deprecated": "1",
         "EventCode": "0xA2",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD",
+        "EventName": "UNC_H_RING_SINK_STARVED_VERT.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.AK",
+        "Deprecated": "1",
         "EventCode": "0xA2",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK",
+        "EventName": "UNC_H_RING_SINK_STARVED_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.BL",
+        "Deprecated": "1",
         "EventCode": "0xA2",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL",
+        "EventName": "UNC_H_RING_SINK_STARVED_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.IV",
+        "Deprecated": "1",
         "EventCode": "0xA2",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV",
+        "EventName": "UNC_H_RING_SINK_STARVED_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SRC_THRTL",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IPQ",
         "Deprecated": "1",
-        "EventCode": "0xA4",
-        "EventName": "UNC_C_RING_SRC_THRTL",
+        "EventCode": "0x13",
+        "EventName": "UNC_H_RxC_INSERTS.IPQ",
         "PerPkg": "1",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations; IRQ Rejected",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ",
+        "Deprecated": "1",
         "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ",
+        "EventName": "UNC_H_RxC_INSERTS.IRQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations; IPQ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ_REJ",
+        "Deprecated": "1",
         "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.IPQ",
+        "EventName": "UNC_H_RxC_INSERTS.IRQ_REJ",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations; PRQ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.PRQ",
+        "Deprecated": "1",
         "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.PRQ",
+        "EventName": "UNC_H_RxC_INSERTS.PRQ",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations; PRQ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.PRQ_REJ",
+        "Deprecated": "1",
         "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ",
+        "EventName": "UNC_H_RxC_INSERTS.PRQ_REJ",
         "PerPkg": "1",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations; RRQ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.RRQ",
+        "Deprecated": "1",
         "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.RRQ",
+        "EventName": "UNC_H_RxC_INSERTS.RRQ",
         "PerPkg": "1",
         "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations; WBQ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.WBQ",
+        "Deprecated": "1",
         "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.WBQ",
+        "EventName": "UNC_H_RxC_INSERTS.WBQ",
         "PerPkg": "1",
         "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; AD REQ on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0",
+        "Deprecated": "1",
         "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0",
+        "EventName": "UNC_H_RxC_IPQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; AD RSP on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0",
+        "Deprecated": "1",
         "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0",
+        "EventName": "UNC_H_RxC_IPQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; BL RSP on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0",
+        "Deprecated": "1",
         "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0",
+        "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; BL WB on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0",
+        "Deprecated": "1",
         "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0",
+        "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; BL NCB on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0",
+        "Deprecated": "1",
         "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0",
+        "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; BL NCS on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0",
+        "Deprecated": "1",
         "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0",
+        "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ANY0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP",
         "Deprecated": "1",
         "EventCode": "0x23",
-        "EventName": "UNC_H_RxC_IPQ1_REJECT.ANY_IPQ0",
+        "EventName": "UNC_H_RxC_IPQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; HA",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ANY0",
+        "Deprecated": "1",
         "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA",
+        "EventName": "UNC_H_RxC_IPQ1_REJECT.ANY_IPQ0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; LLC Victim",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.HA",
+        "Deprecated": "1",
         "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM",
+        "EventName": "UNC_H_RxC_IPQ1_REJECT.HA",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; SF Victim",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
+        "Deprecated": "1",
         "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM",
+        "EventName": "UNC_H_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; Victim",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM",
+        "Deprecated": "1",
         "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM",
+        "EventName": "UNC_H_RxC_IPQ1_REJECT.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; Merging these two together to make room for ANY_REJECT_*0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH",
+        "Deprecated": "1",
         "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
+        "EventName": "UNC_H_RxC_IPQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; Allow Snoop",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM",
+        "Deprecated": "1",
         "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP",
+        "EventName": "UNC_H_RxC_IPQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; PhyAddr Match",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.VICTIM",
+        "Deprecated": "1",
         "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH",
+        "EventName": "UNC_H_RxC_IPQ1_REJECT.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
+        "Deprecated": "1",
         "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
+        "EventName": "UNC_H_RxC_IRQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
+        "Deprecated": "1",
         "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
+        "EventName": "UNC_H_RxC_IRQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
+        "Deprecated": "1",
         "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
+        "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
+        "Deprecated": "1",
         "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
+        "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
+        "Deprecated": "1",
         "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
+        "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
+        "Deprecated": "1",
         "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
+        "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
+        "Deprecated": "1",
+        "EventCode": "0x19",
+        "EventName": "UNC_H_RxC_IRQ1_REJECT.ALLOW_SNP",
+        "PerPkg": "1",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ANY0",
-        "Counter": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0x19",
         "EventName": "UNC_H_RxC_IRQ1_REJECT.ANY_REJECT_IRQ0",
@@ -8013,170 +7931,169 @@
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.HA",
+        "Deprecated": "1",
         "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA",
+        "EventName": "UNC_H_RxC_IRQ1_REJECT.HA",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
+        "Deprecated": "1",
         "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
+        "EventName": "UNC_H_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
+        "Deprecated": "1",
         "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
+        "EventName": "UNC_H_RxC_IRQ1_REJECT.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
+        "Deprecated": "1",
         "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
+        "EventName": "UNC_H_RxC_IRQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Merging these two together to make room for ANY_REJECT_*0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
+        "Deprecated": "1",
         "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
+        "EventName": "UNC_H_RxC_IRQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
+        "Deprecated": "1",
         "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
+        "EventName": "UNC_H_RxC_IRQ1_REJECT.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects; AD REQ on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
+        "Deprecated": "1",
         "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
+        "EventName": "UNC_H_RxC_ISMQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects; AD RSP on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
+        "Deprecated": "1",
         "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
+        "EventName": "UNC_H_RxC_ISMQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects; BL RSP on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
+        "Deprecated": "1",
         "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
+        "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects; BL WB on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
+        "Deprecated": "1",
         "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
+        "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects; BL NCB on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
+        "Deprecated": "1",
         "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
+        "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects; BL NCS on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
+        "Deprecated": "1",
         "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
+        "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries; AD REQ on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
+        "Deprecated": "1",
         "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
+        "EventName": "UNC_H_RxC_ISMQ0_RETRY.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries; AD RSP on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
+        "Deprecated": "1",
         "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
+        "EventName": "UNC_H_RxC_ISMQ0_RETRY.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries; BL RSP on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
+        "Deprecated": "1",
         "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
+        "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_NCB_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries; BL WB on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
+        "Deprecated": "1",
         "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
+        "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries; BL NCB on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
+        "Deprecated": "1",
         "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
+        "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries; BL NCS on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
+        "Deprecated": "1",
         "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
+        "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
-        "Counter": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0x25",
         "EventName": "UNC_H_RxC_ISMQ1_REJECT.ANY_ISMQ0",
@@ -8185,17 +8102,16 @@
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects; HA",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.HA",
+        "Deprecated": "1",
         "EventCode": "0x25",
-        "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA",
+        "EventName": "UNC_H_RxC_ISMQ1_REJECT.HA",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
-        "Counter": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0x2D",
         "EventName": "UNC_H_RxC_ISMQ1_RETRY.ANY",
@@ -8204,95 +8120,115 @@
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries; HA",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.HA",
+        "Deprecated": "1",
         "EventCode": "0x2D",
-        "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA",
+        "EventName": "UNC_H_RxC_ISMQ1_RETRY.HA",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Occupancy; IPQ",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IPQ",
+        "Deprecated": "1",
         "EventCode": "0x11",
-        "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ",
+        "EventName": "UNC_H_RxC_OCCUPANCY.IPQ",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Occupancy; RRQ",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ",
+        "Deprecated": "1",
         "EventCode": "0x11",
-        "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ",
+        "EventName": "UNC_H_RxC_OCCUPANCY.IRQ",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.RRQ",
+        "Deprecated": "1",
+        "EventCode": "0x11",
+        "EventName": "UNC_H_RxC_OCCUPANCY.RRQ",
         "PerPkg": "1",
         "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Occupancy; WBQ",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.WBQ",
+        "Deprecated": "1",
         "EventCode": "0x11",
-        "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ",
+        "EventName": "UNC_H_RxC_OCCUPANCY.WBQ",
         "PerPkg": "1",
         "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; AD REQ on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
+        "Deprecated": "1",
         "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
+        "EventName": "UNC_H_RxC_OTHER0_RETRY.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; AD RSP on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
+        "Deprecated": "1",
         "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
+        "EventName": "UNC_H_RxC_OTHER0_RETRY.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; BL RSP on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
+        "Deprecated": "1",
         "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
+        "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_NCB_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; BL WB on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
+        "Deprecated": "1",
         "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
+        "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; BL NCB on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
+        "Deprecated": "1",
         "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
+        "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; BL NCS on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
+        "Deprecated": "1",
         "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
+        "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
+        "Deprecated": "1",
+        "EventCode": "0x2F",
+        "EventName": "UNC_H_RxC_OTHER1_RETRY.ALLOW_SNP",
+        "PerPkg": "1",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ANY0",
-        "Counter": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0x2F",
         "EventName": "UNC_H_RxC_OTHER1_RETRY.ANY",
@@ -8301,125 +8237,124 @@
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; HA",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.HA",
+        "Deprecated": "1",
         "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA",
+        "EventName": "UNC_H_RxC_OTHER1_RETRY.HA",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; LLC Victim",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
+        "Deprecated": "1",
         "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
+        "EventName": "UNC_H_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; SF Victim",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
+        "Deprecated": "1",
         "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
+        "EventName": "UNC_H_RxC_OTHER1_RETRY.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; Victim",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
+        "Deprecated": "1",
         "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
+        "EventName": "UNC_H_RxC_OTHER1_RETRY.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; Merging these two together to make room for ANY_REJECT_*0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
+        "Deprecated": "1",
         "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
+        "EventName": "UNC_H_RxC_OTHER1_RETRY.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; Allow Snoop",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
+        "Deprecated": "1",
         "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
+        "EventName": "UNC_H_RxC_OTHER1_RETRY.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; PhyAddr Match",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x20",
+        "EventName": "UNC_H_RxC_PRQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
+        "Deprecated": "1",
         "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
+        "EventName": "UNC_H_RxC_PRQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
+        "Deprecated": "1",
         "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
+        "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
+        "Deprecated": "1",
         "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
+        "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
+        "Deprecated": "1",
         "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
+        "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
+        "Deprecated": "1",
         "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
+        "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
+        "Deprecated": "1",
+        "EventCode": "0x21",
+        "EventName": "UNC_H_RxC_PRQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ANY0",
-        "Counter": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0x21",
         "EventName": "UNC_H_RxC_PRQ1_REJECT.ANY_PRQ0",
@@ -8428,125 +8363,124 @@
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.HA",
+        "Deprecated": "1",
         "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA",
+        "EventName": "UNC_H_RxC_PRQ1_REJECT.HA",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
+        "Deprecated": "1",
         "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
+        "EventName": "UNC_H_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
+        "Deprecated": "1",
         "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
+        "EventName": "UNC_H_RxC_PRQ1_REJECT.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
+        "Deprecated": "1",
         "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
+        "EventName": "UNC_H_RxC_PRQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC OR SF Way",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
+        "Deprecated": "1",
         "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
+        "EventName": "UNC_H_RxC_PRQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
+        "Deprecated": "1",
         "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
+        "EventName": "UNC_H_RxC_PRQ1_REJECT.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x2A",
+        "EventName": "UNC_H_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; AD REQ on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
+        "Deprecated": "1",
         "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
+        "EventName": "UNC_H_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; AD RSP on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
+        "Deprecated": "1",
         "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
+        "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; BL RSP on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
+        "Deprecated": "1",
         "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
+        "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; BL WB on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
+        "Deprecated": "1",
         "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
+        "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; BL NCB on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
+        "Deprecated": "1",
         "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
+        "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
+        "Deprecated": "1",
+        "EventCode": "0x2B",
+        "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
-        "Counter": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0x2B",
         "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ANY",
@@ -8555,125 +8489,124 @@
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; HA",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.HA",
+        "Deprecated": "1",
         "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA",
+        "EventName": "UNC_H_RxC_REQ_Q1_RETRY.HA",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; LLC Victim",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
+        "Deprecated": "1",
         "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
+        "EventName": "UNC_H_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; SF Victim",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
+        "Deprecated": "1",
         "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
+        "EventName": "UNC_H_RxC_REQ_Q1_RETRY.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; Victim",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
+        "Deprecated": "1",
         "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
+        "EventName": "UNC_H_RxC_REQ_Q1_RETRY.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; Merging these two together to make room for ANY_REJECT_*0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
+        "Deprecated": "1",
         "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
+        "EventName": "UNC_H_RxC_REQ_Q1_RETRY.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; Allow Snoop",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
+        "Deprecated": "1",
         "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
+        "EventName": "UNC_H_RxC_REQ_Q1_RETRY.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; PhyAddr Match",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x26",
+        "EventName": "UNC_H_RxC_RRQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; AD REQ on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0",
+        "Deprecated": "1",
         "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0",
+        "EventName": "UNC_H_RxC_RRQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; AD RSP on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0",
+        "Deprecated": "1",
         "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0",
+        "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; BL RSP on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0",
+        "Deprecated": "1",
         "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0",
+        "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; BL WB on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0",
+        "Deprecated": "1",
         "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0",
+        "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; BL NCB on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0",
+        "Deprecated": "1",
         "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0",
+        "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP",
+        "Deprecated": "1",
+        "EventCode": "0x27",
+        "EventName": "UNC_H_RxC_RRQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ANY0",
-        "Counter": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0x27",
         "EventName": "UNC_H_RxC_RRQ1_REJECT.ANY_RRQ0",
@@ -8682,125 +8615,124 @@
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; HA",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.HA",
+        "Deprecated": "1",
         "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA",
+        "EventName": "UNC_H_RxC_RRQ1_REJECT.HA",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; LLC Victim",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
+        "Deprecated": "1",
         "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM",
+        "EventName": "UNC_H_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; SF Victim",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM",
+        "Deprecated": "1",
         "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM",
+        "EventName": "UNC_H_RxC_RRQ1_REJECT.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; Victim",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH",
+        "Deprecated": "1",
         "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM",
+        "EventName": "UNC_H_RxC_RRQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; Merging these two together to make room for ANY_REJECT_*0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM",
+        "Deprecated": "1",
         "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
+        "EventName": "UNC_H_RxC_RRQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; Allow Snoop",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.VICTIM",
+        "Deprecated": "1",
         "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP",
+        "EventName": "UNC_H_RxC_RRQ1_REJECT.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; PhyAddr Match",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x28",
+        "EventName": "UNC_H_RxC_WBQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; AD REQ on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0",
+        "Deprecated": "1",
         "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0",
+        "EventName": "UNC_H_RxC_WBQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; AD RSP on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0",
+        "Deprecated": "1",
         "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0",
+        "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; BL RSP on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0",
+        "Deprecated": "1",
         "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0",
+        "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; BL WB on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0",
+        "Deprecated": "1",
         "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0",
+        "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; BL NCB on VN0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0",
+        "Deprecated": "1",
         "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0",
+        "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP",
+        "Deprecated": "1",
+        "EventCode": "0x29",
+        "EventName": "UNC_H_RxC_WBQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ANY0",
-        "Counter": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0x29",
         "EventName": "UNC_H_RxC_WBQ1_REJECT.ANY_WBQ0",
@@ -8809,3063 +8741,3161 @@
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; HA",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA",
-        "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "WBQ Rejects; LLC Victim",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.HA",
+        "Deprecated": "1",
         "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM",
+        "EventName": "UNC_H_RxC_WBQ1_REJECT.HA",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; SF Victim",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
+        "Deprecated": "1",
         "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM",
+        "EventName": "UNC_H_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; Victim",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM",
+        "Deprecated": "1",
         "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM",
+        "EventName": "UNC_H_RxC_WBQ1_REJECT.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; Merging these two together to make room for ANY_REJECT_*0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH",
+        "Deprecated": "1",
         "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
+        "EventName": "UNC_H_RxC_WBQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; Allow Snoop",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM",
+        "Deprecated": "1",
         "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP",
+        "EventName": "UNC_H_RxC_WBQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; PhyAddr Match",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.VICTIM",
+        "Deprecated": "1",
         "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH",
+        "EventName": "UNC_H_RxC_WBQ1_REJECT.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.AD_BNC",
+        "Deprecated": "1",
         "EventCode": "0xB4",
-        "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_BNC",
+        "EventName": "UNC_H_RxR_BUSY_STARVED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.AD_CRD",
+        "Deprecated": "1",
         "EventCode": "0xB4",
-        "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_BNC",
+        "EventName": "UNC_H_RxR_BUSY_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.BL_BNC",
+        "Deprecated": "1",
         "EventCode": "0xB4",
-        "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD",
+        "EventName": "UNC_H_RxR_BUSY_STARVED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.BL_CRD",
+        "Deprecated": "1",
         "EventCode": "0xB4",
-        "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD",
+        "EventName": "UNC_H_RxR_BUSY_STARVED.BL_CRD",
         "PerPkg": "1",
         "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AD_BNC",
+        "Deprecated": "1",
         "EventCode": "0xB2",
-        "EventName": "UNC_CHA_RxR_BYPASS.AD_BNC",
+        "EventName": "UNC_H_RxR_BYPASS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AD_CRD",
+        "Deprecated": "1",
         "EventCode": "0xB2",
-        "EventName": "UNC_CHA_RxR_BYPASS.AK_BNC",
+        "EventName": "UNC_H_RxR_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AK_BNC",
+        "Deprecated": "1",
         "EventCode": "0xB2",
-        "EventName": "UNC_CHA_RxR_BYPASS.BL_BNC",
+        "EventName": "UNC_H_RxR_BYPASS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.BL_BNC",
+        "Deprecated": "1",
         "EventCode": "0xB2",
-        "EventName": "UNC_CHA_RxR_BYPASS.IV_BNC",
+        "EventName": "UNC_H_RxR_BYPASS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.BL_CRD",
+        "Deprecated": "1",
         "EventCode": "0xB2",
-        "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD",
+        "EventName": "UNC_H_RxR_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.IV_BNC",
+        "Deprecated": "1",
         "EventCode": "0xB2",
-        "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD",
+        "EventName": "UNC_H_RxR_BYPASS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AD_BNC",
+        "Deprecated": "1",
         "EventCode": "0xB3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_BNC",
+        "EventName": "UNC_H_RxR_CRD_STARVED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AD_CRD",
+        "Deprecated": "1",
         "EventCode": "0xB3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.AK_BNC",
+        "EventName": "UNC_H_RxR_CRD_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AK_BNC",
+        "Deprecated": "1",
         "EventCode": "0xB3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_BNC",
+        "EventName": "UNC_H_RxR_CRD_STARVED.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.BL_BNC",
+        "Deprecated": "1",
         "EventCode": "0xB3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.IV_BNC",
+        "EventName": "UNC_H_RxR_CRD_STARVED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.BL_CRD",
+        "Deprecated": "1",
         "EventCode": "0xB3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD",
+        "EventName": "UNC_H_RxR_CRD_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.IFV",
+        "Deprecated": "1",
         "EventCode": "0xB3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD",
+        "EventName": "UNC_H_RxR_CRD_STARVED.IFV",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.IV_BNC",
+        "Deprecated": "1",
         "EventCode": "0xB3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV",
+        "EventName": "UNC_H_RxR_CRD_STARVED.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AD_BNC",
+        "Deprecated": "1",
         "EventCode": "0xB1",
-        "EventName": "UNC_CHA_RxR_INSERTS.AD_BNC",
+        "EventName": "UNC_H_RxR_INSERTS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AD_CRD",
+        "Deprecated": "1",
         "EventCode": "0xB1",
-        "EventName": "UNC_CHA_RxR_INSERTS.AK_BNC",
+        "EventName": "UNC_H_RxR_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AK_BNC",
+        "Deprecated": "1",
         "EventCode": "0xB1",
-        "EventName": "UNC_CHA_RxR_INSERTS.BL_BNC",
+        "EventName": "UNC_H_RxR_INSERTS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.BL_BNC",
+        "Deprecated": "1",
         "EventCode": "0xB1",
-        "EventName": "UNC_CHA_RxR_INSERTS.IV_BNC",
+        "EventName": "UNC_H_RxR_INSERTS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.BL_CRD",
+        "Deprecated": "1",
         "EventCode": "0xB1",
-        "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD",
+        "EventName": "UNC_H_RxR_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.IV_BNC",
+        "Deprecated": "1",
         "EventCode": "0xB1",
-        "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD",
+        "EventName": "UNC_H_RxR_INSERTS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AD_BNC",
+        "Deprecated": "1",
         "EventCode": "0xB0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_BNC",
+        "EventName": "UNC_H_RxR_OCCUPANCY.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AD_CRD",
+        "Deprecated": "1",
         "EventCode": "0xB0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.AK_BNC",
+        "EventName": "UNC_H_RxR_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AK_BNC",
+        "Deprecated": "1",
         "EventCode": "0xB0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_BNC",
+        "EventName": "UNC_H_RxR_OCCUPANCY.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.BL_BNC",
+        "Deprecated": "1",
         "EventCode": "0xB0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.IV_BNC",
+        "EventName": "UNC_H_RxR_OCCUPANCY.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.BL_CRD",
+        "Deprecated": "1",
         "EventCode": "0xB0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD",
+        "EventName": "UNC_H_RxR_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.IV_BNC",
+        "Deprecated": "1",
         "EventCode": "0xB0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD",
+        "EventName": "UNC_H_RxR_OCCUPANCY.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.E_STATE",
+        "Deprecated": "1",
+        "EventCode": "0x3D",
+        "EventName": "UNC_H_SF_EVICTION.E_STATE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.M_STATE",
+        "Deprecated": "1",
+        "EventCode": "0x3D",
+        "EventName": "UNC_H_SF_EVICTION.M_STATE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.S_STATE",
+        "Deprecated": "1",
+        "EventCode": "0x3D",
+        "EventName": "UNC_H_SF_EVICTION.S_STATE",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.ALL",
+        "Deprecated": "1",
+        "EventCode": "0x51",
+        "EventName": "UNC_H_SNOOPS_SENT.",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
+        "Deprecated": "1",
+        "EventCode": "0x51",
+        "EventName": "UNC_H_SNOOPS_SENT.BCST_LOC",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_REMOTE",
+        "Deprecated": "1",
+        "EventCode": "0x51",
+        "EventName": "UNC_H_SNOOPS_SENT.BCST_REM",
         "PerPkg": "1",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
+        "Deprecated": "1",
+        "EventCode": "0x51",
+        "EventName": "UNC_H_SNOOPS_SENT.DIRECT_LOC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE",
+        "Deprecated": "1",
+        "EventCode": "0x51",
+        "EventName": "UNC_H_SNOOPS_SENT.DIRECT_REM",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.LOCAL",
+        "Deprecated": "1",
+        "EventCode": "0x51",
+        "EventName": "UNC_H_SNOOPS_SENT.LOCAL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.REMOTE",
+        "Deprecated": "1",
+        "EventCode": "0x51",
+        "EventName": "UNC_H_SNOOPS_SENT.REMOTE",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPCNFLCTS",
+        "Deprecated": "1",
+        "EventCode": "0x5C",
+        "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPFWD",
+        "Deprecated": "1",
+        "EventCode": "0x5C",
+        "EventName": "UNC_H_SNOOP_RESP.RSPFWD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPI",
+        "Deprecated": "1",
+        "EventCode": "0x5C",
+        "EventName": "UNC_H_SNOOP_RESP.RSPI",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD",
+        "Deprecated": "1",
+        "EventCode": "0x5C",
+        "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPS",
+        "Deprecated": "1",
+        "EventCode": "0x5C",
+        "EventName": "UNC_H_SNOOP_RESP.RSPS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD",
+        "Deprecated": "1",
+        "EventCode": "0x5C",
+        "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB",
+        "Deprecated": "1",
+        "EventCode": "0x5C",
+        "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_WBWB",
+        "Deprecated": "1",
+        "EventCode": "0x5C",
+        "EventName": "UNC_H_SNOOP_RESP.RSP_WB",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
+        "Deprecated": "1",
+        "EventCode": "0x5D",
+        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPCNFLCT",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
+        "Deprecated": "1",
+        "EventCode": "0x5D",
+        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPFWD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
+        "Deprecated": "1",
+        "EventCode": "0x5D",
+        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPI",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
+        "Deprecated": "1",
+        "EventCode": "0x5D",
+        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPIFWD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
+        "Deprecated": "1",
+        "EventCode": "0x5D",
+        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
+        "Deprecated": "1",
+        "EventCode": "0x5D",
+        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPSFWD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB",
+        "Deprecated": "1",
+        "EventCode": "0x5D",
+        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_FWD_WB",
         "PerPkg": "1",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9D",
-        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB",
+        "Deprecated": "1",
+        "EventCode": "0x5D",
+        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_WB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9D",
-        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+        "Deprecated": "1",
+        "EventCode": "0xD0",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9D",
-        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+        "Deprecated": "1",
+        "EventCode": "0xD0",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9D",
-        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+        "Deprecated": "1",
+        "EventCode": "0xD0",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9D",
-        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+        "Deprecated": "1",
+        "EventCode": "0xD0",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9F",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+        "Deprecated": "1",
+        "EventCode": "0xD0",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9F",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+        "Deprecated": "1",
+        "EventCode": "0xD0",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9F",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+        "Deprecated": "1",
+        "EventCode": "0xD2",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9F",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+        "Deprecated": "1",
+        "EventCode": "0xD2",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9F",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+        "Deprecated": "1",
+        "EventCode": "0xD2",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9F",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+        "Deprecated": "1",
+        "EventCode": "0xD2",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+        "Deprecated": "1",
+        "EventCode": "0xD2",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+        "Deprecated": "1",
+        "EventCode": "0xD2",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+        "Deprecated": "1",
+        "EventCode": "0xD4",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+        "Deprecated": "1",
+        "EventCode": "0xD4",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+        "Deprecated": "1",
+        "EventCode": "0xD4",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+        "Deprecated": "1",
+        "EventCode": "0xD4",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x97",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+        "Deprecated": "1",
+        "EventCode": "0xD4",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x97",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+        "Deprecated": "1",
+        "EventCode": "0xD4",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x97",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+        "Deprecated": "1",
+        "EventCode": "0xD6",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x97",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+        "Deprecated": "1",
+        "EventCode": "0xD6",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x97",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+        "Deprecated": "1",
+        "EventCode": "0xD6",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x97",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+        "Deprecated": "1",
+        "EventCode": "0xD6",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x95",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+        "Deprecated": "1",
+        "EventCode": "0xD6",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x95",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+        "Deprecated": "1",
+        "EventCode": "0xD6",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x95",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_H_TxR_HORZ_ADS_USED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x95",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_H_TxR_HORZ_ADS_USED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x95",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_H_TxR_HORZ_ADS_USED.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x95",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_H_TxR_HORZ_ADS_USED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x99",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_H_TxR_HORZ_ADS_USED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x99",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.AK_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AD_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x9F",
+        "EventName": "UNC_H_TxR_HORZ_BYPASS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x99",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AD_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x9F",
+        "EventName": "UNC_H_TxR_HORZ_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x99",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.IV_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AK_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x9F",
+        "EventName": "UNC_H_TxR_HORZ_BYPASS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x99",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.BL_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x9F",
+        "EventName": "UNC_H_TxR_HORZ_BYPASS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x99",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.BL_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x9F",
+        "EventName": "UNC_H_TxR_HORZ_BYPASS.BL_CRD",
         "PerPkg": "1",
         "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.IV_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x9F",
+        "EventName": "UNC_H_TxR_HORZ_BYPASS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x96",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x96",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x96",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x96",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x96",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.BL_CRD",
         "PerPkg": "1",
         "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9B",
-        "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x96",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9B",
-        "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x97",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9B",
-        "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x97",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9B",
-        "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x97",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9C",
-        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x97",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9C",
-        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x97",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9C",
-        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x97",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9C",
-        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AD_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x95",
+        "EventName": "UNC_H_TxR_HORZ_INSERTS.AD_BNC",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AD_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x95",
+        "EventName": "UNC_H_TxR_HORZ_INSERTS.AD_CRD",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9C",
-        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AK_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x95",
+        "EventName": "UNC_H_TxR_HORZ_INSERTS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9C",
-        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.BL_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x95",
+        "EventName": "UNC_H_TxR_HORZ_INSERTS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9E",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.BL_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x95",
+        "EventName": "UNC_H_TxR_HORZ_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9E",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.IV_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x95",
+        "EventName": "UNC_H_TxR_HORZ_INSERTS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9E",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AD_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x99",
+        "EventName": "UNC_H_TxR_HORZ_NACK.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.IV",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AD_CRD",
         "Deprecated": "1",
-        "EventCode": "0x9E",
-        "EventName": "UNC_H_TxR_VERT_BYPASS.IV_AG1",
+        "EventCode": "0x99",
+        "EventName": "UNC_H_TxR_HORZ_NACK.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9E",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AK_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x99",
+        "EventName": "UNC_H_TxR_HORZ_NACK.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9E",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.BL_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x99",
+        "EventName": "UNC_H_TxR_HORZ_NACK.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9E",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.BL_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x99",
+        "EventName": "UNC_H_TxR_HORZ_NACK.BL_CRD",
         "PerPkg": "1",
         "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.IV_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x99",
+        "EventName": "UNC_H_TxR_HORZ_NACK.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x94",
+        "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x94",
+        "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.IV",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC",
         "Deprecated": "1",
-        "EventCode": "0x92",
-        "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.IV_AG0",
+        "EventCode": "0x94",
+        "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x94",
+        "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x94",
+        "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x94",
+        "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x93",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.AD_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x9B",
+        "EventName": "UNC_H_TxR_HORZ_STARVED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x93",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.AK_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x9B",
+        "EventName": "UNC_H_TxR_HORZ_STARVED.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x93",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.BL_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x9B",
+        "EventName": "UNC_H_TxR_HORZ_STARVED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.IV",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.IV_BNC",
         "Deprecated": "1",
-        "EventCode": "0x93",
-        "EventName": "UNC_H_TxR_VERT_CYCLES_NE.IV_AG0",
+        "EventCode": "0x9B",
+        "EventName": "UNC_H_TxR_HORZ_STARVED.IV_BNC",
         "PerPkg": "1",
         "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x93",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AD_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_H_TxR_VERT_ADS_USED.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x93",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AD_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_H_TxR_VERT_ADS_USED.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x93",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AK_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_H_TxR_VERT_ADS_USED.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x91",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AK_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_H_TxR_VERT_ADS_USED.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x91",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.BL_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_H_TxR_VERT_ADS_USED.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x91",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.BL_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_H_TxR_VERT_ADS_USED.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.IV",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AD_AG0",
         "Deprecated": "1",
-        "EventCode": "0x91",
-        "EventName": "UNC_H_TxR_VERT_INSERTS.IV_AG0",
+        "EventCode": "0x9E",
+        "EventName": "UNC_H_TxR_VERT_BYPASS.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x91",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AD_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_H_TxR_VERT_BYPASS.AD_AG1",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x91",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AK_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_H_TxR_VERT_BYPASS.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x91",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AK_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_H_TxR_VERT_BYPASS.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.BL_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_H_TxR_VERT_BYPASS.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.BL_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_H_TxR_VERT_BYPASS.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.IV",
+        "Deprecated": "1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_H_TxR_VERT_BYPASS.IV_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK.IV",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x92",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x92",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AD_AG1",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x92",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x92",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x92",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x92",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.IV",
+        "Deprecated": "1",
+        "EventCode": "0x92",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.IV",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0",
         "Deprecated": "1",
-        "EventCode": "0x90",
-        "EventName": "UNC_H_TxR_VERT_OCCUPANCY.IV_AG0",
+        "EventCode": "0x93",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x93",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AD_AG1",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x93",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x93",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x93",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_NE.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x93",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_NE.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.IV",
+        "Deprecated": "1",
+        "EventCode": "0x93",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_NE.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED.IV",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AD_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x91",
+        "EventName": "UNC_H_TxR_VERT_INSERTS.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AD_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x91",
+        "EventName": "UNC_H_TxR_VERT_INSERTS.AD_AG1",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AK_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x91",
+        "EventName": "UNC_H_TxR_VERT_INSERTS.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AK_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x91",
+        "EventName": "UNC_H_TxR_VERT_INSERTS.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use; Up and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA6",
-        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.BL_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x91",
+        "EventName": "UNC_H_TxR_VERT_INSERTS.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use; Up and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA6",
-        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.BL_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x91",
+        "EventName": "UNC_H_TxR_VERT_INSERTS.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use; Down and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA6",
-        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.IV",
+        "Deprecated": "1",
+        "EventCode": "0x91",
+        "EventName": "UNC_H_TxR_VERT_INSERTS.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use; Down and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA6",
-        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AD_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x98",
+        "EventName": "UNC_H_TxR_VERT_NACK.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use; Up and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA8",
-        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AD_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x98",
+        "EventName": "UNC_H_TxR_VERT_NACK.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use; Up and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA8",
-        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AK_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x98",
+        "EventName": "UNC_H_TxR_VERT_NACK.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use; Down and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA8",
-        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AK_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x98",
+        "EventName": "UNC_H_TxR_VERT_NACK.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use; Down and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA8",
-        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.BL_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x98",
+        "EventName": "UNC_H_TxR_VERT_NACK.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use; Up and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAA",
-        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.BL_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x98",
+        "EventName": "UNC_H_TxR_VERT_NACK.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use; Up and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAA",
-        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.IV",
+        "Deprecated": "1",
+        "EventCode": "0x98",
+        "EventName": "UNC_H_TxR_VERT_NACK.IV",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use; Down and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAA",
-        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x90",
+        "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use; Down and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAA",
-        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x90",
+        "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical IV Ring in Use; Up",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAC",
-        "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x90",
+        "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical IV Ring in Use; Down",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAC",
-        "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x90",
+        "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; External RspHitFSE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x90",
+        "EventName": "UNC_H_TxR_VERT_OCCUPANCY.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Core RspHitFSE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x90",
+        "EventName": "UNC_H_TxR_VERT_OCCUPANCY.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x41",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Evict RspHitFSE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.IV",
+        "Deprecated": "1",
+        "EventCode": "0x90",
+        "EventName": "UNC_H_TxR_VERT_OCCUPANCY.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x81",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Any RspHitFSE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AD_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_H_TxR_VERT_STARVED.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0xE1",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; External RspSFwdFE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AD_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_H_TxR_VERT_STARVED.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x22",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdFE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AK_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_H_TxR_VERT_STARVED.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x42",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdFE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AK_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_H_TxR_VERT_STARVED.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x82",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdFE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.BL_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_H_TxR_VERT_STARVED.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0xE2",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; External RspIFwdFE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.BL_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_H_TxR_VERT_STARVED.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x24",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdFE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.IV",
+        "Deprecated": "1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_H_TxR_VERT_STARVED.IV",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdFE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN",
+        "Deprecated": "1",
+        "EventCode": "0xA6",
+        "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x84",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Any RspIFwdFE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD",
+        "Deprecated": "1",
+        "EventCode": "0xA6",
+        "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0xE4",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; External RspSFwdM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN",
+        "Deprecated": "1",
+        "EventCode": "0xA6",
+        "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x28",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD",
+        "Deprecated": "1",
+        "EventCode": "0xA6",
+        "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x48",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN",
+        "Deprecated": "1",
+        "EventCode": "0xA8",
+        "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x88",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD",
+        "Deprecated": "1",
+        "EventCode": "0xA8",
+        "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0xE8",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; External RspIFwdM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN",
+        "Deprecated": "1",
+        "EventCode": "0xA8",
+        "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x30",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD",
+        "Deprecated": "1",
+        "EventCode": "0xA8",
+        "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x50",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN",
+        "Deprecated": "1",
+        "EventCode": "0xAA",
+        "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x90",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD",
+        "Deprecated": "1",
+        "EventCode": "0xAA",
+        "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0xF0",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.IPQ_HIT",
+        "EventCode": "0xAA",
+        "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x18",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.IPQ_MISS",
+        "EventCode": "0xAA",
+        "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x28",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_IV_IN_USE.DN",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.RRQ_HIT",
+        "EventCode": "0xAC",
+        "EventName": "UNC_H_VERT_RING_IV_IN_USE.DN",
         "PerPkg": "1",
-        "UMask": "0x50",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_IV_IN_USE.UP",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.RRQ_MISS",
+        "EventCode": "0xAC",
+        "EventName": "UNC_H_VERT_RING_IV_IN_USE.UP",
         "PerPkg": "1",
-        "UMask": "0x60",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WB_PUSH_MTOI.LLC",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.WBQ_HIT",
+        "EventCode": "0x56",
+        "EventName": "UNC_H_WB_PUSH_MTOI.LLC",
         "PerPkg": "1",
-        "UMask": "0x90",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WB_PUSH_MTOI.MEM",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.WBQ_MISS",
+        "EventCode": "0x56",
+        "EventName": "UNC_H_WB_PUSH_MTOI.MEM",
         "PerPkg": "1",
-        "UMask": "0xA0",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_HIT",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2",
         "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_HIT",
+        "EventCode": "0x5A",
+        "EventName": "UNC_H_WRITE_NO_CREDITS.EDC0_SMI2",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3",
         "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_MISS",
+        "EventCode": "0x5A",
+        "EventName": "UNC_H_WRITE_NO_CREDITS.EDC1_SMI3",
         "PerPkg": "1",
-        "UMask": "0x24",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4",
         "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_HIT",
+        "EventCode": "0x5A",
+        "EventName": "UNC_H_WRITE_NO_CREDITS.EDC2_SMI4",
         "PerPkg": "1",
-        "UMask": "0x18",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5",
         "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_MISS",
+        "EventCode": "0x5A",
+        "EventName": "UNC_H_WRITE_NO_CREDITS.EDC3_SMI5",
         "PerPkg": "1",
-        "UMask": "0x28",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; All from Local IO",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0",
+        "Deprecated": "1",
+        "EventCode": "0x5A",
+        "EventName": "UNC_H_WRITE_NO_CREDITS.MC0_SMI0",
         "PerPkg": "1",
-        "UMask": "0x34",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; All from Local iA and IO",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.ALL_IO_IA",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1",
+        "Deprecated": "1",
+        "EventCode": "0x5A",
+        "EventName": "UNC_H_WRITE_NO_CREDITS.MC1_SMI1",
         "PerPkg": "1",
-        "UMask": "0x35",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; Hits from Local",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.ALL_HIT",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.ANY_RSPI_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x15",
+        "UMask": "0xe4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; Misses from Local",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.ALL_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.ANY_RSPI_FWDM",
         "PerPkg": "1",
-        "UMask": "0x25",
+        "UMask": "0xf0",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; All from Local IO",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.ANY_RSPS_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x34",
+        "UMask": "0xe2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; Hits from Local IO",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.ANY_RSPS_FWDM",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "UMask": "0xe8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; Misses from Local IO",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.ANY_RSP_HITFSE",
         "PerPkg": "1",
-        "UMask": "0x24",
+        "UMask": "0xe1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; Hits from Local",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_HIT",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.CORE_RSPI_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x17",
+        "UMask": "0x44",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; Misses from Local",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.CORE_RSPI_FWDM",
         "PerPkg": "1",
-        "UMask": "0x27",
+        "UMask": "0x50",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credit Allocations; VNA Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VNA",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.CORE_RSPS_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x42",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credit Allocations; VN0 Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VN0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.CORE_RSPS_FWDM",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x48",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credit Allocations; AD REQ Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_REQ",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.CORE_RSP_HITFSE",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x41",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credit Allocations; AD RSP VN0 Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_RSP",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.EVICT_RSPI_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x84",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credit Allocations; BL RSP Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_RSP",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.EVICT_RSPI_FWDM",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x90",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credit Allocations; BL DRS Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_WB",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.EVICT_RSPS_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x82",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credit Allocations; BL NCB Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCB",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.EVICT_RSPS_FWDM",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x88",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credit Allocations; BL NCS Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.EVICT_RSP_HITFSE",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x81",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credits In Use Cycles; AD VNA Credits",
-        "EventCode": "0x3B",
-        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_AD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.EXT_RSPI_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x24",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credits In Use Cycles; BL VNA Credits",
-        "EventCode": "0x3B",
-        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_BL",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.EXT_RSPI_FWDM",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x30",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credits In Use Cycles; AD REQ VN0 Credits",
-        "EventCode": "0x3B",
-        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_REQ",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.EXT_RSPS_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x22",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credits In Use Cycles; AD RSP VN0 Credits",
-        "EventCode": "0x3B",
-        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_RSP",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.EXT_RSPS_FWDM",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x28",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credits In Use Cycles; BL RSP VN0 Credits",
-        "EventCode": "0x3B",
-        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_RSP",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.EXT_RSP_HITFSE",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x21",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credits In Use Cycles; BL DRS VN0 Credits",
-        "EventCode": "0x3B",
-        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_WB",
+        "BriefDescription": "Clockticks of the IIO Traffic Controller",
+        "EventCode": "0x1",
+        "EventName": "UNC_IIO_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "PublicDescription": "Counts clockticks of the 1GHz traffic controller clock in the IIO unit.",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCB VN0 Credits",
-        "EventCode": "0x3B",
-        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCB",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",
+        "FCMask": "0x4",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "PortMask": "0x0f",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
+        "FCMask": "0x4",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
+        "FCMask": "0x4",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "PortMask": "0x02",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
+        "FCMask": "0x4",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "PortMask": "0x04",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
+        "FCMask": "0x4",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "PortMask": "0x08",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "ISMQ Rejects; Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI",
+        "BriefDescription": "PCIe Completion Buffer Inserts; Port 0",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT0",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "ISMQ Rejects; Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI",
+        "BriefDescription": "PCIe Completion Buffer Inserts; Port 1",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT1",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "PortMask": "0x02",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "ISMQ Retries; Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI",
+        "BriefDescription": "PCIe Completion Buffer Inserts; Port 2",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT2",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "PortMask": "0x04",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "ISMQ Retries; Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI",
+        "BriefDescription": "PCIe Completion Buffer Inserts; Port 3",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT3",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "PortMask": "0x08",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Other Retries; Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI",
+        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3",
+        "EventCode": "0xD5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "UMask": "0xf",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Other Retries; Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI",
+        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0",
+        "EventCode": "0xD5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI",
+        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1",
+        "EventCode": "0xD5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI",
+        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2",
+        "EventCode": "0xD5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Request Queue Retries; Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI",
+        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3",
+        "EventCode": "0xD5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Request Queue Retries; Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI",
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "RRQ Rejects; Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI",
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1",
         "UMask": "0x40",
-        "Unit": "CHA"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "RRQ Rejects; Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI",
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "PortMask": "0x04",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "WBQ Rejects; Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI",
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3",
         "UMask": "0x40",
-        "Unit": "CHA"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "WBQ Rejects; Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI",
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Request Queue Retries; ANY0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Snoops Sent; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x51",
-        "EventName": "UNC_CHA_SNOOPS_SENT.ALL",
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Snoops Sent; Broadcast snoop for Local Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x51",
-        "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1",
         "UMask": "0x10",
-        "Unit": "CHA"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Snoops Sent; Broadcast snoops for Remote Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x51",
-        "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE",
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "PortMask": "0x04",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Snoops Sent; Directed snoops for Local Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x51",
-        "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "PortMask": "0x08",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Snoops Sent; Directed snoops for Remote Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x51",
-        "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE",
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; RspI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; RspS",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; RspIFwd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PortMask": "0x02",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; RspSFwd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PortMask": "0x04",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB",
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PortMask": "0x08",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB",
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; RspCnflct",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; RspFwd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "CMS Clockticks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
         "EventCode": "0xC0",
-        "EventName": "UNC_CHA_CMS_CLOCKTICKS",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "Unit": "CHA"
+        "PortMask": "0x02",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ",
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "CHA"
+        "PortMask": "0x04",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache and Snoop Filter Lookups; Write Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.WRITE",
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x05",
-        "Unit": "CHA"
+        "PortMask": "0x08",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache and Snoop Filter Lookups; External Snoop Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP",
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x09",
-        "Unit": "CHA"
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache and Snoop Filter Lookups; Any Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.ANY",
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x11",
-        "Unit": "CHA"
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache and Snoop Filter Lookups; Local",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL",
+        "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x31",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache and Snoop Filter Lookups; Remote",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE",
+        "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x91",
-        "Unit": "CHA"
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE",
+        "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part2",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE",
+        "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part3",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE",
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.F_STATE",
-        "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Lines Victimized; Local - All Lines",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x2F",
-        "Unit": "CHA"
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE",
+        "BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; IRQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IRQ",
+        "BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; SF/LLC Evictions",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.EVICT",
+        "BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by  a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; PRQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.PRQ",
+        "BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by  a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; IPQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IPQ",
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; Hit (Not a Miss)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.HIT",
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; Miss",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.MISS",
+        "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
+        "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x37",
-        "Unit": "CHA"
+        "PortMask": "0x02",
+        "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.ALL",
+        "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0xFF",
-        "Unit": "CHA"
+        "PortMask": "0x04",
+        "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IPQ_HIT",
+        "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x18",
-        "Unit": "CHA"
+        "PortMask": "0x08",
+        "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IPQ_MISS",
+        "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x28",
-        "Unit": "CHA"
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.RRQ_HIT",
+        "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x50",
-        "Unit": "CHA"
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS",
+        "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x60",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit.  In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.WBQ_HIT",
+        "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x90",
-        "Unit": "CHA"
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.WBQ_MISS",
+        "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0xA0",
-        "Unit": "CHA"
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; IRQ",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ",
+        "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; SF/LLC Evictions",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
+        "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; PRQ",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
+        "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; IPQ",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ",
+        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; Hit (Not a Miss)",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
+        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1",
         "UMask": "0x10",
-        "Unit": "CHA"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; Miss",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
+        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "PortMask": "0x04",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC",
-        "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
-        "PerPkg": "1",
-        "UMask": "0x37",
-        "Unit": "CHA"
+        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.ALL",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL",
+        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0xFF",
-        "Unit": "CHA"
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_HIT",
+        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x18",
-        "Unit": "CHA"
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_MISS",
+        "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x28",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Source Throttle",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA4",
-        "EventName": "UNC_CHA_RING_SRC_THRTL",
+        "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "Unit": "CHA"
+        "PortMask": "0x02",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; ANY0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0",
+        "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "CHA"
+        "PortMask": "0x04",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0",
+        "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "CHA"
+        "PortMask": "0x08",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "ISMQ Rejects; ANY0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x25",
-        "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
+        "BriefDescription": "PCI Express bandwidth reading at IIO, part 0",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "ISMQ Retries; ANY0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2D",
-        "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
+        "BriefDescription": "PCI Express bandwidth reading at IIO, part 1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "CHA"
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Other Retries; ANY0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0",
+        "BriefDescription": "PCI Express bandwidth reading at IIO, part 2",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "CHA"
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0",
+        "BriefDescription": "PCI Express bandwidth reading at IIO, part 3",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "CHA"
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "RRQ Rejects; ANY0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0",
+        "BriefDescription": "Data requested of the CPU; Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "CHA"
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "WBQ Rejects; ANY0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0",
+        "BriefDescription": "Data requested of the CPU; Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "CHA"
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9E",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV",
+        "BriefDescription": "PCI Express bandwidth writing at IIO, part 0",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part0 to a unit onthe main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.IV",
+        "BriefDescription": "PCI Express bandwidth writing at IIO, part 1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x93",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.IV",
+        "BriefDescription": "PCI Express bandwidth writing at IIO, part 2",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x91",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS.IV",
+        "BriefDescription": "PCI Express bandwidth writing at IIO, part 3",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.IV",
+        "BriefDescription": "Data requested of the CPU; Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "FaST wire asserted; Vertical",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA5",
-        "EventName": "UNC_CHA_FAST_ASSERTED.VERT",
+        "BriefDescription": "Data requested of the CPU; Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL",
+        "BriefDescription": "Data requested of the CPU; Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Lines Victimized; Local - Lines in M State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M",
+        "BriefDescription": "Data requested of the CPU; Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x21",
-        "Unit": "CHA"
+        "PortMask": "0x02",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Lines Victimized; Local - Lines in E State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E",
+        "BriefDescription": "Data requested of the CPU; Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x22",
-        "Unit": "CHA"
+        "PortMask": "0x04",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Lines Victimized; Local - Lines in S State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S",
-        "PerPkg": "1",
-        "UMask": "0x24",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Lines Victimized; Local - Lines in F State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_F",
-        "PerPkg": "1",
-        "UMask": "0x28",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Lines Victimized; Remote - Lines in M State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M",
-        "PerPkg": "1",
-        "UMask": "0x81",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Lines Victimized; Remote - Lines in E State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E",
-        "PerPkg": "1",
-        "UMask": "0x82",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Lines Victimized; Remote - Lines in S State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S",
-        "PerPkg": "1",
-        "UMask": "0x84",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Lines Victimized; Remote - Lines in F State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_F",
-        "PerPkg": "1",
-        "UMask": "0x88",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Lines Victimized; Remote - All Lines",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
-        "PerPkg": "1",
-        "UMask": "0x8F",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "TOR Occupancy; All from Local",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC",
-        "PerPkg": "1",
-        "UMask": "0x37",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "TOR Inserts; RdCur misses from Local IO",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RDCUR",
-        "Filter": "config1=0x43C33",
+        "BriefDescription": "Data requested of the CPU; Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x24",
-        "Unit": "CHA"
+        "PortMask": "0x08",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; RFO misses from Local IO",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
-        "Filter": "config1=0x40033",
+        "BriefDescription": "Data requested of the CPU; Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x24",
-        "Unit": "CHA"
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; ItoM misses from Local IO",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
-        "Filter": "config1=0x49033",
+        "BriefDescription": "Data requested of the CPU; Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x24",
-        "Unit": "CHA"
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy;  ITOM Misses from Local IO",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
-        "Filter": "config1=0x49033",
+        "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x24",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy;  RDCUR isses from Local IO",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RDCUR",
-        "Filter": "config1=0x43C33",
+        "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x24",
-        "Unit": "CHA"
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy;  RFO misses from Local IO",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
-        "Filter": "config1=0x40033",
+        "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x24",
-        "Unit": "CHA"
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in IODC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x64",
-        "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.IODC",
+        "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in SF/LLC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x64",
-        "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC",
+        "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in SF/LLC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x64",
-        "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF",
+        "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in TOR",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x64",
-        "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR",
+        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Memory mode related events; Counts the number of times CHA saw NM Set conflict in TOR and the transaction was rejected",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x64",
-        "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR_REJECT",
+        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts; Port 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT0",
-        "FCMask": "0x7",
+        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x04",
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts; Port 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT1",
-        "FCMask": "0x7",
+        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x04",
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts; Port 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT2",
-        "FCMask": "0x7",
+        "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x04",
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts; Port 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT3",
-        "FCMask": "0x7",
+        "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x04",
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "Num Link  Correctable Errors",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "UNC_IIO_LINK_NUM_CORR_ERR",
         "PerPkg": "1",
@@ -11873,7 +11903,6 @@
     },
     {
         "BriefDescription": "Num Link Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE",
         "EventName": "UNC_IIO_LINK_NUM_RETRIES",
         "PerPkg": "1",
@@ -11881,7 +11910,6 @@
     },
     {
         "BriefDescription": "Number packets that passed the Mask/Match Filter",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_IIO_MASK_MATCH",
         "PerPkg": "1",
@@ -11889,314 +11917,362 @@
     },
     {
         "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0",
         "PerPkg": "1",
+        "PublicDescription": "Asserted if all bits specified by mask match",
         "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "AND Mask/match for debug bus; PCIE bus",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and PCIE bus",
         "EventCode": "0x2",
-        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1",
+        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Asserted if all bits specified by mask match",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1",
         "PerPkg": "1",
+        "PublicDescription": "Asserted if all bits specified by mask match",
         "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and PCIE bus",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "AND Mask/match for debug bus; PCIE bus",
         "EventCode": "0x2",
-        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1",
+        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Asserted if all bits specified by mask match",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "AND Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1",
         "PerPkg": "1",
+        "PublicDescription": "Asserted if all bits specified by mask match",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "AND Mask/match for debug bus",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1",
         "PerPkg": "1",
+        "PublicDescription": "Asserted if all bits specified by mask match",
         "UMask": "0x20",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0",
         "PerPkg": "1",
+        "PublicDescription": "Asserted if any bits specified by mask match",
         "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "OR Mask/match for debug bus; PCIE bus",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and PCIE bus",
         "EventCode": "0x3",
-        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1",
+        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Asserted if any bits specified by mask match",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1",
         "PerPkg": "1",
+        "PublicDescription": "Asserted if any bits specified by mask match",
         "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and PCIE bus",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "OR Mask/match for debug bus; PCIE bus",
         "EventCode": "0x3",
-        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1",
+        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Asserted if any bits specified by mask match",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1",
         "PerPkg": "1",
+        "PublicDescription": "Asserted if any bits specified by mask match",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and !(PCIE bus)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1",
         "PerPkg": "1",
+        "PublicDescription": "Asserted if any bits specified by mask match",
         "UMask": "0x20",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "UNC_IIO_NOTHING",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_IIO_NOTHING",
         "PerPkg": "1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x1",
-        "UMask": "0x2",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART1",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x2",
-        "UMask": "0x2",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART2",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x4",
-        "UMask": "0x2",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART3",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x8",
-        "UMask": "0x2",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD0",
+        "FCMask": "0x7",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "UMask": "0x10",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD1",
+        "FCMask": "0x7",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "UMask": "0x10",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x1",
-        "UMask": "0x8",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART1",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x2",
-        "UMask": "0x8",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART2",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x4",
-        "UMask": "0x8",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART3",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x8",
-        "UMask": "0x8",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART1",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x2",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART2",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x4",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART3",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x8",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD0",
+        "FCMask": "0x7",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD1",
+        "FCMask": "0x7",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x1",
-        "UMask": "0x20",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART1",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x2",
-        "UMask": "0x20",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART2",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x4",
-        "UMask": "0x20",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART3",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x8",
-        "UMask": "0x20",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD0",
+        "FCMask": "0x7",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD1",
+        "FCMask": "0x7",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
-        "Counter": "0,1",
         "Deprecated": "1",
         "EventCode": "0x83",
         "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART0",
@@ -12208,7 +12284,6 @@
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
-        "Counter": "0,1",
         "Deprecated": "1",
         "EventCode": "0x83",
         "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART1",
@@ -12220,7 +12295,6 @@
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
-        "Counter": "0,1",
         "Deprecated": "1",
         "EventCode": "0x83",
         "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART2",
@@ -12232,7 +12306,6 @@
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
-        "Counter": "0,1",
         "Deprecated": "1",
         "EventCode": "0x83",
         "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART3",
@@ -12243,344 +12316,293 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART0",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x1",
+        "PortMask": "0x10",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x1",
+        "PortMask": "0x20",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART2",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x1",
+        "PortMask": "0x1",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART3",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x1",
+        "PortMask": "0x2",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART0",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x2",
+        "PortMask": "0x4",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x2",
+        "PortMask": "0x8",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART2",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x2",
+        "PortMask": "0x10",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART3",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x2",
+        "PortMask": "0x20",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART0",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x1",
-        "UMask": "0x4",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x2",
-        "UMask": "0x4",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART2",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x4",
-        "UMask": "0x4",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART3",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x8",
-        "UMask": "0x4",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
-        "Counter": "2,3",
-        "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART0",
-        "FCMask": "0x7",
-        "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x8",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
-        "Counter": "2,3",
-        "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART1",
-        "FCMask": "0x7",
-        "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x8",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART2",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x8",
+        "PortMask": "0x10",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART3",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x8",
+        "PortMask": "0x20",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x1",
-        "UMask": "0x10",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART1",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x2",
-        "UMask": "0x10",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART2",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x4",
-        "UMask": "0x10",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART3",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x8",
-        "UMask": "0x10",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x20",
+        "PortMask": "0x10",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART1",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x20",
+        "PortMask": "0x20",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART2",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x20",
+        "PortMask": "0x1",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART3",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x20",
+        "PortMask": "0x2",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x40",
+        "PortMask": "0x4",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART1",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x40",
+        "PortMask": "0x8",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART2",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x40",
+        "PortMask": "0x10",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART3",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x40",
+        "PortMask": "0x20",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
-        "Counter": "2,3",
         "Deprecated": "1",
         "EventCode": "0xC0",
         "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART0",
@@ -12592,7 +12614,6 @@
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
-        "Counter": "2,3",
         "Deprecated": "1",
         "EventCode": "0xC0",
         "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART1",
@@ -12604,7 +12625,6 @@
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
-        "Counter": "2,3",
         "Deprecated": "1",
         "EventCode": "0xC0",
         "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART2",
@@ -12616,7 +12636,6 @@
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
-        "Counter": "2,3",
         "Deprecated": "1",
         "EventCode": "0xC0",
         "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART3",
@@ -12627,115 +12646,98 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Symbol Times on Link",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_IIO_SYMBOL_TIMES",
-        "PerPkg": "1",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART0",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x1",
+        "PortMask": "0x10",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART1",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x1",
+        "PortMask": "0x20",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART2",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x1",
+        "PortMask": "0x1",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART3",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x1",
+        "PortMask": "0x2",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART0",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x2",
+        "PortMask": "0x4",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART1",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x2",
+        "PortMask": "0x8",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART2",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x2",
+        "PortMask": "0x10",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART3",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x2",
+        "PortMask": "0x20",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART0",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x1",
@@ -12743,11 +12745,10 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART1",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x2",
@@ -12755,11 +12756,10 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART2",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x4",
@@ -12767,11 +12767,10 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART3",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x8",
@@ -12779,491 +12778,480 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART0",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x8",
+        "PortMask": "0x10",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART1",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x8",
+        "PortMask": "0x20",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART2",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x8",
+        "PortMask": "0x1",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART3",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x8",
+        "PortMask": "0x2",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART0",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x10",
+        "PortMask": "0x4",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART1",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x10",
+        "PortMask": "0x8",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART2",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x10",
+        "PortMask": "0x10",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART3",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x10",
+        "PortMask": "0x20",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART0",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART1",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x2",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART2",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x4",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART3",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x8",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MSG.PART0",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x40",
+        "PortMask": "0x10",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MSG.PART1",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x40",
+        "PortMask": "0x20",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MSG.PART2",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x40",
+        "PortMask": "0x1",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MSG.PART3",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x40",
+        "PortMask": "0x2",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART0",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x1",
+        "PortMask": "0x4",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART1",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x1",
+        "PortMask": "0x8",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART2",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x1",
+        "PortMask": "0x10",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART3",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x1",
+        "PortMask": "0x20",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Symbol Times on Link",
+        "EventCode": "0x82",
+        "EventName": "UNC_IIO_SYMBOL_TIMES",
+        "PerPkg": "1",
+        "PublicDescription": "Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART0",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x1",
-        "UMask": "0x2",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x2",
-        "UMask": "0x2",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART2",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x4",
-        "UMask": "0x2",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART3",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x8",
-        "UMask": "0x2",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART0",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x4",
+        "PortMask": "0x10",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x4",
+        "PortMask": "0x20",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART2",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x4",
+        "PortMask": "0x1",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART3",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x4",
+        "PortMask": "0x2",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART0",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x8",
+        "PortMask": "0x4",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x8",
+        "PortMask": "0x8",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART2",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x8",
+        "PortMask": "0x1",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART3",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x8",
+        "PortMask": "0x2",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART0",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x10",
+        "PortMask": "0x4",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x10",
+        "PortMask": "0x8",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART2",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x10",
+        "PortMask": "0x10",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART3",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x10",
+        "PortMask": "0x20",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART0",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x1",
-        "UMask": "0x20",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x2",
-        "UMask": "0x20",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART2",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x4",
-        "UMask": "0x20",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART3",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x8",
-        "UMask": "0x20",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART0",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD0",
+        "FCMask": "0x7",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1",
+        "Deprecated": "1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD1",
+        "FCMask": "0x7",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MSG.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x1",
@@ -13271,11 +13259,10 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MSG.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x2",
@@ -13283,11 +13270,10 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART2",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MSG.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x4",
@@ -13295,11 +13281,10 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART3",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MSG.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x8",
@@ -13307,211 +13292,208 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART0",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MSG.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x80",
+        "PortMask": "0x10",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MSG.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x80",
+        "PortMask": "0x20",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART2",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x80",
+        "PortMask": "0x1",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART3",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x80",
+        "PortMask": "0x2",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "VTd Access; Vtd hit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_VTD_ACCESS.L4_PAGE_HIT",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART2",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PortMask": "0x4",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "VTd Access; context cache miss",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_VTD_ACCESS.CTXT_MISS",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART3",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PortMask": "0x8",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "VTd Access; L1 miss",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_VTD_ACCESS.L1_MISS",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD0",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PortMask": "0x10",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "VTd Access; L2 miss",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_VTD_ACCESS.L2_MISS",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD1",
+        "FCMask": "0x7",
         "PerPkg": "1",
+        "PortMask": "0x20",
         "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "VTd Access; L3 miss",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_VTD_ACCESS.L3_MISS",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART0",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PortMask": "0x1",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "VTd Access; TLB miss",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_VTD_ACCESS.TLB_MISS",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART1",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PortMask": "0x2",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "VTd Access; TLB is full",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_VTD_ACCESS.TLB_FULL",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART2",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PortMask": "0x4",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "VTd Access; TLB miss",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_VTD_ACCESS.TLB1_MISS",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART3",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PortMask": "0x8",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "VTd Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x40",
-        "EventName": "UNC_IIO_VTD_OCCUPANCY",
-        "PerPkg": "1",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD0",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x4",
+        "PortMask": "0x1",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x4",
+        "PortMask": "0x2",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x1",
+        "PortMask": "0x4",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x1",
+        "PortMask": "0x8",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x10",
@@ -13519,11 +13501,10 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x20",
@@ -13531,107 +13512,109 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x8",
+        "PortMask": "0x1",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x8",
+        "PortMask": "0x2",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x2",
+        "PortMask": "0x4",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x2",
+        "PortMask": "0x8",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x40",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x40",
+        "PortMask": "0x1",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x10",
+        "PortMask": "0x2",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x10",
+        "PortMask": "0x4",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART3",
+        "FCMask": "0x7",
+        "PerPkg": "1",
+        "PortMask": "0x8",
+        "UMask": "0x80",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0",
+        "Deprecated": "1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x10",
@@ -13639,11 +13622,10 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x20",
@@ -13651,9304 +13633,12704 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
+        "PortMask": "0x1",
         "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
+        "PortMask": "0x2",
         "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x4",
+        "PortMask": "0x4",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x4",
+        "PortMask": "0x8",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x1",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x1",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x8",
+        "PortMask": "0x1",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x8",
+        "PortMask": "0x2",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x2",
+        "PortMask": "0x4",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x2",
+        "PortMask": "0x8",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x4",
+        "PortMask": "0x1",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x4",
+        "PortMask": "0x2",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
+        "PortMask": "0x4",
         "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
+        "PortMask": "0x8",
         "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MSG.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x40",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MSG.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x40",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
+        "PortMask": "0x1",
         "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
+        "PortMask": "0x2",
         "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x2",
+        "PortMask": "0x4",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x2",
+        "PortMask": "0x8",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0",
         "Deprecated": "1",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD0",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1",
         "Deprecated": "1",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD1",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x40",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.VTD0",
-        "FCMask": "0x7",
-        "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x10",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
         "Deprecated": "1",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD0",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x80",
+        "PortMask": "0x1",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
         "Deprecated": "1",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD1",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x80",
+        "PortMask": "0x2",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
         "Deprecated": "1",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD0",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x20",
+        "PortMask": "0x4",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
         "Deprecated": "1",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD1",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x20",
+        "PortMask": "0x8",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0",
         "Deprecated": "1",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD0",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x4",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1",
         "Deprecated": "1",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD1",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x4",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD0",
-        "FCMask": "0x7",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x1",
+        "PortMask": "0x01",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD1",
-        "FCMask": "0x7",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x1",
+        "PortMask": "0x02",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD0",
-        "FCMask": "0x7",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x8",
+        "PortMask": "0x04",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD1",
-        "FCMask": "0x7",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x8",
+        "PortMask": "0x08",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD0",
-        "FCMask": "0x7",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0",
+        "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x2",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD1",
-        "FCMask": "0x7",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1",
+        "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x2",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x01",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x02",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x04",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x08",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+        "UMask": "0x10",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+        "UMask": "0x10",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x80",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1",
+        "UMask": "0x80",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x80",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3",
+        "UMask": "0x80",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+        "UMask": "0x80",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+        "UMask": "0x80",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x01",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
         "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x02",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1",
+        "UMask": "0x20",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x20",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3",
+        "UMask": "0x20",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+        "UMask": "0x20",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
         "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x10",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1",
+        "UMask": "0x10",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x10",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3",
+        "UMask": "0x10",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
+        "UMask": "0x10",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
+        "UMask": "0x10",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x20",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1",
+        "UMask": "0x20",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x20",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3",
+        "UMask": "0x20",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Read request for up to a 64 byte transaction is  made by IIO Part1 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x40",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1",
+        "UMask": "0x40",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x40",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3",
+        "UMask": "0x40",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
+        "UMask": "0x40",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
+        "UMask": "0x40",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part1 to the MMIO space of an IIO target.In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "VTd Access; context cache miss",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_VTD_ACCESS.CTXT_MISS",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "VTd Access; L1 miss",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_VTD_ACCESS.L1_MISS",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "VTd Access; L2 miss",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_VTD_ACCESS.L2_MISS",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "VTd Access; L3 miss",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_VTD_ACCESS.L3_MISS",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "VTd Access; Vtd hit",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_VTD_ACCESS.L4_PAGE_HIT",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "VTd Access; TLB miss",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_VTD_ACCESS.TLB1_MISS",
+        "PerPkg": "1",
+        "UMask": "0x80",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "VTd Access; TLB is full",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_VTD_ACCESS.TLB_FULL",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "VTd Access; TLB miss",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_VTD_ACCESS.TLB_MISS",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "VTd Occupancy",
+        "EventCode": "0x40",
+        "EventName": "UNC_IIO_VTD_OCCUPANCY",
+        "PerPkg": "1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Total Write Cache Occupancy; Any Source",
+        "EventCode": "0xF",
+        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
+        "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.",
+        "UMask": "0x1",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Total Write Cache Occupancy; Snoops",
+        "EventCode": "0xF",
+        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q",
+        "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.",
+        "UMask": "0x2",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Total IRP occupancy of inbound read and write requests.",
+        "EventCode": "0xF",
+        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
+        "PerPkg": "1",
+        "PublicDescription": "Total IRP occupancy of inbound read and write requests.  This is effectively the sum of read occupancy and write occupancy.",
+        "UMask": "0x4",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "IRP Clocks",
+        "EventCode": "0x1",
+        "EventName": "UNC_I_CLOCKTICKS",
+        "PerPkg": "1",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Coherent Ops; CLFlush",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+        "UMask": "0x80",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Coherent Ops; CRd",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.CRD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+        "UMask": "0x2",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Coherent Ops; DRd",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.DRD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+        "UMask": "0x4",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Coherent Ops; PCIDCAHin5t",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+        "UMask": "0x20",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Coherent Ops; PCIRdCur",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+        "UMask": "0x1",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.PCITOM",
+        "PerPkg": "1",
+        "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO.  PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.",
+        "UMask": "0x10",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.RFO",
+        "PerPkg": "1",
+        "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory.  RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.",
+        "UMask": "0x8",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Coherent Ops; WbMtoI",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+        "UMask": "0x40",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "FAF RF full",
+        "EventCode": "0x17",
+        "EventName": "UNC_I_FAF_FULL",
+        "PerPkg": "1",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.",
+        "EventCode": "0x18",
+        "EventName": "UNC_I_FAF_INSERTS",
+        "PerPkg": "1",
+        "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Occupancy of the IRP FAF queue.",
+        "EventCode": "0x19",
+        "EventName": "UNC_I_FAF_OCCUPANCY",
+        "PerPkg": "1",
+        "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "FAF allocation -- sent to ADQ",
+        "EventCode": "0x16",
+        "EventName": "UNC_I_FAF_TRANSACTIONS",
+        "PerPkg": "1",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "All Inserts Inbound (p2p + faf + cset)",
+        "EventCode": "0x1E",
+        "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "All Inserts Outbound (BL, AK, Snoops)",
+        "EventCode": "0x1E",
+        "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
+        "EventCode": "0x1C",
+        "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
+        "EventCode": "0x1C",
+        "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
+        "EventCode": "0x1C",
+        "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
+        "EventCode": "0x1C",
+        "EventName": "UNC_I_MISC0.FAST_REJ",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
+        "EventCode": "0x1C",
+        "EventName": "UNC_I_MISC0.FAST_REQ",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
+        "EventCode": "0x1C",
+        "EventName": "UNC_I_MISC0.FAST_XFER",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
+        "EventCode": "0x1C",
+        "EventName": "UNC_I_MISC0.PF_ACK_HINT",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Misc Events - Set 0",
+        "EventCode": "0x1C",
+        "EventName": "UNC_I_MISC0.UNKNOWN",
+        "PerPkg": "1",
+        "UMask": "0x80",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Misc Events - Set 1; Lost Forward",
+        "EventCode": "0x1D",
+        "EventName": "UNC_I_MISC1.LOST_FWD",
+        "PerPkg": "1",
+        "PublicDescription": "Snoop pulled away ownership before a write was committed",
+        "UMask": "0x10",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Misc Events - Set 1; Received Invalid",
+        "EventCode": "0x1D",
+        "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
+        "PerPkg": "1",
+        "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
+        "UMask": "0x20",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Misc Events - Set 1; Received Valid",
+        "EventCode": "0x1D",
+        "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
+        "PerPkg": "1",
+        "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
+        "UMask": "0x40",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
+        "EventCode": "0x1D",
+        "EventName": "UNC_I_MISC1.SLOW_E",
+        "PerPkg": "1",
+        "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
+        "UMask": "0x4",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
+        "EventCode": "0x1D",
+        "EventName": "UNC_I_MISC1.SLOW_I",
+        "PerPkg": "1",
+        "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
+        "UMask": "0x1",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
+        "EventCode": "0x1D",
+        "EventName": "UNC_I_MISC1.SLOW_M",
+        "PerPkg": "1",
+        "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
+        "UMask": "0x8",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
+        "EventCode": "0x1D",
+        "EventName": "UNC_I_MISC1.SLOW_S",
+        "PerPkg": "1",
+        "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
+        "UMask": "0x2",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "P2P Requests",
+        "EventCode": "0x14",
+        "EventName": "UNC_I_P2P_INSERTS",
+        "PerPkg": "1",
+        "PublicDescription": "P2P requests from the ITC",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "P2P Occupancy",
+        "EventCode": "0x15",
+        "EventName": "UNC_I_P2P_OCCUPANCY",
+        "PerPkg": "1",
+        "PublicDescription": "P2P B & S Queue Occupancy",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "P2P Transactions; P2P completions",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "P2P Transactions; match if local only",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.LOC",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "P2P Transactions; match if local and target matches",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH",
+        "PerPkg": "1",
+        "UMask": "0x80",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "P2P Transactions; P2P Message",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.MSG",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "P2P Transactions; P2P reads",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.RD",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "P2P Transactions; Match if remote only",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.REM",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "P2P Transactions; match if remote and target matches",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "P2P Transactions; P2P Writes",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.WR",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT",
+        "PerPkg": "1",
+        "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO",
+        "UMask": "0x7e",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES",
+        "PerPkg": "1",
+        "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache",
+        "UMask": "0x74",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I",
+        "PerPkg": "1",
+        "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache",
+        "UMask": "0x72",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M",
+        "PerPkg": "1",
+        "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache",
+        "UMask": "0x78",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Responses to snoops of any type that miss the IIO cache",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.ALL_MISS",
+        "PerPkg": "1",
+        "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that miss the IIO cache",
+        "UMask": "0x71",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Snoop Responses; Hit E or S",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Snoop Responses; Hit I",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.HIT_I",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Snoop Responses; Hit M",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.HIT_M",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Snoop Responses; Miss",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.MISS",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Snoop Responses; SnpCode",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Snoop Responses; SnpData",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Snoop Responses; SnpInv",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.SNPINV",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Inbound Transaction Count; Atomic",
+        "EventCode": "0x11",
+        "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions",
+        "UMask": "0x10",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Inbound Transaction Count; Other",
+        "EventCode": "0x11",
+        "EventName": "UNC_I_TRANSACTIONS.OTHER",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions.",
+        "UMask": "0x20",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Inbound Transaction Count; Read Prefetches",
+        "EventCode": "0x11",
+        "EventName": "UNC_I_TRANSACTIONS.RD_PREF",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.",
+        "UMask": "0x4",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Inbound Transaction Count; Reads",
+        "EventCode": "0x11",
+        "EventName": "UNC_I_TRANSACTIONS.READS",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).",
+        "UMask": "0x1",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Inbound Transaction Count; Writes",
+        "EventCode": "0x11",
+        "EventName": "UNC_I_TRANSACTIONS.WRITES",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests.  Each write request should have a prefetch, so there is no need to explicitly track these requests.  For writes that are tickled and have to retry, the counter will be incremented for each retry.",
+        "UMask": "0x2",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Inbound write (fast path) requests received by the IRP.",
+        "EventCode": "0x11",
+        "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
+        "PerPkg": "1",
+        "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.",
+        "UMask": "0x8",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "AK Egress Allocations",
+        "EventCode": "0xB",
+        "EventName": "UNC_I_TxC_AK_INSERTS",
+        "PerPkg": "1",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "BL DRS Egress Cycles Full",
+        "EventCode": "0x5",
+        "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL",
+        "PerPkg": "1",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "BL DRS Egress Inserts",
+        "EventCode": "0x2",
+        "EventName": "UNC_I_TxC_BL_DRS_INSERTS",
+        "PerPkg": "1",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "BL DRS Egress Occupancy",
+        "EventCode": "0x8",
+        "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY",
+        "PerPkg": "1",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "BL NCB Egress Cycles Full",
+        "EventCode": "0x6",
+        "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL",
+        "PerPkg": "1",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "BL NCB Egress Inserts",
+        "EventCode": "0x3",
+        "EventName": "UNC_I_TxC_BL_NCB_INSERTS",
+        "PerPkg": "1",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "BL NCB Egress Occupancy",
+        "EventCode": "0x9",
+        "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY",
+        "PerPkg": "1",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "BL NCS Egress Cycles Full",
+        "EventCode": "0x7",
+        "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL",
+        "PerPkg": "1",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "BL NCS Egress Inserts",
+        "EventCode": "0x4",
+        "EventName": "UNC_I_TxC_BL_NCS_INSERTS",
+        "PerPkg": "1",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "BL NCS Egress Occupancy",
+        "EventCode": "0xA",
+        "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY",
+        "PerPkg": "1",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "No AD Egress Credit Stalls",
+        "EventCode": "0x1A",
+        "EventName": "UNC_I_TxR2_AD_STALL_CREDIT_CYCLES",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "No BL Egress Credit Stalls",
+        "EventCode": "0x1B",
+        "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Outbound Read Requests",
+        "EventCode": "0xD",
+        "EventName": "UNC_I_TxS_DATA_INSERTS_NCB",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Outbound Read Requests",
+        "EventCode": "0xE",
+        "EventName": "UNC_I_TxS_DATA_INSERTS_NCS",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Outbound Request Queue Occupancy",
+        "EventCode": "0xC",
+        "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY",
+        "PerPkg": "1",
+        "PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices).  This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR0",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR1",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR2",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR3",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR4",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR5",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR0",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR1",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR2",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR3",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR4",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR5",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR0",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR1",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR2",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR3",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR4",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR5",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR0",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR1",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR2",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR3",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR4",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR5",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR0",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR1",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR2",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR3",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR4",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR5",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR0",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR1",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR2",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR3",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR4",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR5",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR0",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR1",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR2",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR3",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR4",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR5",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR0",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR1",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR2",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR3",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR4",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR5",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Traffic in which the M2M to iMC Bypass was not taken",
+        "EventCode": "0x22",
+        "EventName": "UNC_M2M_BYPASS_M2M_Egress.NOT_TAKEN",
+        "PerPkg": "1",
+        "PublicDescription": "Counts traffic in which the M2M (Mesh to Memory) to iMC (Memory Controller) bypass was not taken",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "M2M to iMC Bypass; Taken",
+        "EventCode": "0x22",
+        "EventName": "UNC_M2M_BYPASS_M2M_Egress.TAKEN",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "M2M to iMC Bypass; Not Taken",
+        "EventCode": "0x21",
+        "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "M2M to iMC Bypass; Taken",
+        "EventCode": "0x21",
+        "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Cycles - at UCLK",
+        "EventName": "UNC_M2M_CLOCKTICKS",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Clockticks",
+        "EventCode": "0xC0",
+        "EventName": "UNC_M2M_CMS_CLOCKTICKS",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled",
+        "EventCode": "0x24",
+        "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles when direct to core mode (which bypasses the CHA) was disabled",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Messages sent direct to core (bypassing the CHA)",
+        "EventCode": "0x23",
+        "EventName": "UNC_M2M_DIRECT2CORE_TAKEN",
+        "PerPkg": "1",
+        "PublicDescription": "Counts when messages were sent direct to core (bypassing the CHA)",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Number of reads in which direct to core transaction were overridden",
+        "EventCode": "0x25",
+        "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
+        "PerPkg": "1",
+        "PublicDescription": "Counts reads in which direct to core transactions (which would have bypassed the CHA) were overridden",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden",
+        "EventCode": "0x28",
+        "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS",
+        "PerPkg": "1",
+        "PublicDescription": "Counts reads in which direct to Intel Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overridden",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Cycles when direct to Intel UPI was disabled",
+        "EventCode": "0x27",
+        "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles when the ability to send messages direct to the Intel Ultra Path Interconnect (bypassing the CHA) was disabled",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Messages sent direct to the Intel UPI",
+        "EventCode": "0x26",
+        "EventName": "UNC_M2M_DIRECT2UPI_TAKEN",
+        "PerPkg": "1",
+        "PublicDescription": "Counts when messages were sent direct to the Intel Ultra Path Interconnect (bypassing the CHA)",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden",
+        "EventCode": "0x29",
+        "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE",
+        "PerPkg": "1",
+        "PublicDescription": "Counts when a read message that was sent direct to the Intel Ultra Path Interconnect (bypassing the CHA) was overridden",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Directory Hit; On NonDirty Line in A State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A",
+        "PerPkg": "1",
+        "UMask": "0x80",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Directory Hit; On NonDirty Line in I State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Directory Hit; On NonDirty Line in L State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Directory Hit; On NonDirty Line in S State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Directory Hit; On Dirty Line in A State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Directory Hit; On Dirty Line in I State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Directory Hit; On Dirty Line in L State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Directory Hit; On Dirty Line in S State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY",
+        "PerPkg": "1",
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in Any State (A, I, S or unused)",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A",
+        "PerPkg": "1",
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in the A (SnoopAll) state, indicating the cacheline is stored in another socket in any state, and we must snoop the other sockets to make sure we get the latest data.  The data may be stored in any state in the local socket.",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I",
+        "PerPkg": "1",
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the I (Invalid) state indicating the cacheline is not stored in another socket, and so there is no need to snoop the other sockets for the latest data.  The data may be stored in any state in the local socket.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S",
+        "PerPkg": "1",
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the S (Shared) state indicating the cacheline is either stored in another socket in the S(hared) state , and so there is no need to snoop the other sockets for the latest data.  The data may be stored in any state in the local socket.",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Directory Miss; On NonDirty Line in A State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A",
+        "PerPkg": "1",
+        "UMask": "0x80",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Directory Miss; On NonDirty Line in I State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Directory Miss; On NonDirty Line in L State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Directory Miss; On NonDirty Line in S State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Directory Miss; On Dirty Line in A State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Directory Miss; On Dirty Line in I State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Directory Miss; On Dirty Line in L State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Directory Miss; On Dirty Line in S State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Multi-socket cacheline Directory update from A to I",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I",
+        "PerPkg": "1",
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to I (Invalid)",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Multi-socket cacheline Directory update from A to S",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S",
+        "PerPkg": "1",
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to S (Shared)",
+        "UMask": "0x40",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Multi-socket cacheline Directory update from/to Any state",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY",
+        "PerPkg": "1",
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory to a new state",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Multi-socket cacheline Directory update from I to A",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A",
+        "PerPkg": "1",
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to A (SnoopAll)",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Multi-socket cacheline Directory update from I to S",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S",
+        "PerPkg": "1",
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to S (Shared)",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Multi-socket cacheline Directory update from S to A",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A",
+        "PerPkg": "1",
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to A (SnoopAll)",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Multi-socket cacheline Directory update from S to I",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I",
+        "PerPkg": "1",
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to I (Invalid)",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
+        "EventCode": "0xAE",
+        "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN",
+        "PerPkg": "1",
+        "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
+        "EventCode": "0xAE",
+        "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP",
+        "PerPkg": "1",
+        "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "FaST wire asserted; Horizontal",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M2M_FAST_ASSERTED.HORZ",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "FaST wire asserted; Vertical",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M2M_FAST_ASSERTED.VERT",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
+        "EventCode": "0xA9",
+        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
+        "EventCode": "0xA9",
+        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
+        "EventCode": "0xA9",
+        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
+        "EventCode": "0xA9",
+        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Horizontal IV Ring in Use; Left",
+        "EventCode": "0xAD",
+        "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Horizontal IV Ring in Use; Right",
+        "EventCode": "0xAD",
+        "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Reads to iMC issued",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.ALL",
+        "PerPkg": "1",
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller).",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "M2M Reads Issued to iMC; All, regardless of priority.",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.FROM_TRANSGRESS",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "M2M Reads Issued to iMC; Critical Priority",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.ISOCH",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Reads to iMC issued at Normal Priority (Non-Isochronous)",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.NORMAL",
+        "PerPkg": "1",
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller).  It only counts  normal priority non-isochronous reads.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Read requests to Intel Optane DC persistent memory issued to the iMC from M2M",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.TO_PMM",
+        "PerPkg": "1",
+        "PublicDescription": "M2M Reads Issued to iMC; All, regardless of priority.",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Writes to iMC issued",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.ALL",
+        "PerPkg": "1",
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) issues writes to the iMC (Memory Controller).",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority.",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.FROM_TRANSGRESS",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "M2M Writes Issued to iMC; Full Line Non-ISOCH",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.FULL",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "M2M Writes Issued to iMC; ISOCH Full Line",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority.",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.NI",
+        "PerPkg": "1",
+        "UMask": "0x80",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Partial Non-Isochronous writes to the iMC",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.PARTIAL",
+        "PerPkg": "1",
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) issues partial writes to the iMC (Memory Controller).  It only counts normal priority non-isochronous writes.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "M2M Writes Issued to iMC; ISOCH Partial",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Write requests to Intel Optane DC persistent memory issued to the iMC from M2M",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.TO_PMM",
+        "PerPkg": "1",
+        "PublicDescription": "M2M Writes Issued to iMC; All, regardless of priority.",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Number Packet Header Matches; MC Match",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M2M_PKT_MATCH.MC",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Number Packet Header Matches; Mesh Match",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M2M_PKT_MATCH.MESH",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "M2M-&gt;iMC RPQ Cycles w/Credits - Regular; Channel 0",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "M2M-&gt;iMC RPQ Cycles w/Credits - Regular; Channel 1",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN1",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "M2M-&gt;iMC RPQ Cycles w/Credits - Regular; Channel 2",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN2",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "M2M-&gt;iMC WPQ Cycles w/Credits - Regular; Channel 0",
+        "EventCode": "0x51",
+        "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "M2M-&gt;iMC WPQ Cycles w/Credits - Regular; Channel 1",
+        "EventCode": "0x51",
+        "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN1",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "M2M-&gt;iMC WPQ Cycles w/Credits - Regular; Channel 2",
+        "EventCode": "0x51",
+        "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN2",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Prefetch CAM Cycles Full",
+        "EventCode": "0x53",
+        "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Prefetch CAM Cycles Not Empty",
+        "EventCode": "0x54",
+        "EventName": "UNC_M2M_PREFCAM_CYCLES_NE",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Prefecth requests that got turn into a demand request",
+        "EventCode": "0x56",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_PROMOTIONS",
+        "PerPkg": "1",
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) promotes a outstanding request in the prefetch queue due to a subsequent demand read request that entered the M2M with the same address.  Explanatory Side Note: The Prefecth queue is made of CAM (Content Addressable Memory)",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Inserts into the Memory Controller Prefetch Queue",
+        "EventCode": "0x57",
+        "EventName": "UNC_M2M_PREFCAM_INSERTS",
+        "PerPkg": "1",
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) receives a prefetch request and inserts it into its outstanding prefetch queue.  Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Prefetch CAM Occupancy",
+        "EventCode": "0x55",
+        "EventName": "UNC_M2M_PREFCAM_OCCUPANCY",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Sink Starvation on Vertical Ring; AD",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Source Throttle",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M2M_RING_SRC_THRTL",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0",
+        "Deprecated": "1",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1",
+        "Deprecated": "1",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2",
+        "Deprecated": "1",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 0",
+        "EventCode": "0x43",
+        "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 1",
+        "EventCode": "0x43",
+        "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN1",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 2",
+        "EventCode": "0x43",
+        "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN2",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 0",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 1",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 2",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "AD Ingress (from CMS) Full",
+        "EventCode": "0x4",
+        "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "AD Ingress (from CMS) Not Empty",
+        "EventCode": "0x3",
+        "EventName": "UNC_M2M_RxC_AD_CYCLES_NE",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "AD Ingress (from CMS) Queue Inserts",
+        "EventCode": "0x1",
+        "EventName": "UNC_M2M_RxC_AD_INSERTS",
+        "PerPkg": "1",
+        "PublicDescription": "Counts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop).  This is generally used for reads, and",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "AD Ingress (from CMS) Occupancy",
+        "EventCode": "0x2",
+        "EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "BL Ingress (from CMS) Full",
+        "EventCode": "0x8",
+        "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "BL Ingress (from CMS) Not Empty",
+        "EventCode": "0x7",
+        "EventName": "UNC_M2M_RxC_BL_CYCLES_NE",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "BL Ingress (from CMS) Allocations",
+        "EventCode": "0x5",
+        "EventName": "UNC_M2M_RxC_BL_INSERTS",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "BL Ingress (from CMS) Occupancy",
+        "EventCode": "0x6",
+        "EventName": "UNC_M2M_RxC_BL_OCCUPANCY",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x40",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M2M_RxR_BYPASS.AD_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD",
+        "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M2M_RxR_BYPASS.AK_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M2M_RxR_BYPASS.BL_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD",
+        "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x40",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M2M_RxR_BYPASS.IV_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.AK_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x40",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x80",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.IV_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M2M_RxR_INSERTS.AD_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD",
+        "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M2M_RxR_INSERTS.AK_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M2M_RxR_INSERTS.BL_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD",
+        "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x40",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M2M_RxR_INSERTS.IV_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD",
+        "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.AK_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD",
+        "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x40",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.IV_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Clean line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode and regular reads to DRAM in 1LM",
+        "EventCode": "0x2C",
+        "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN",
+        "PerPkg": "1",
+        "PublicDescription": "Tag Hit; Read Hit from NearMem, Clean Line",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Dirty line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode",
+        "EventCode": "0x2C",
+        "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY",
+        "PerPkg": "1",
+        "PublicDescription": "Tag Hit; Read Hit from NearMem, Dirty  Line",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Clean line underfill read hits to Near Memory(DRAM cache) in Memory Mode",
+        "EventCode": "0x2C",
+        "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN",
+        "PerPkg": "1",
+        "PublicDescription": "Tag Hit; Underfill Rd Hit from NearMem, Clean Line",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Dirty line underfill read hits to Near Memory(DRAM cache) in Memory Mode",
+        "EventCode": "0x2C",
+        "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY",
+        "PerPkg": "1",
+        "PublicDescription": "Tag Hit; Underfill Rd Hit from NearMem, Dirty  Line",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Number AD Ingress Credits",
+        "EventCode": "0x41",
+        "EventName": "UNC_M2M_TGR_AD_CREDITS",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Number BL Ingress Credits",
+        "EventCode": "0x42",
+        "EventName": "UNC_M2M_TGR_BL_CREDITS",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Tracker Cycles Full; Channel 0",
+        "EventCode": "0x45",
+        "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Tracker Cycles Full; Channel 1",
+        "EventCode": "0x45",
+        "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH1",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Tracker Cycles Full; Channel 2",
+        "EventCode": "0x45",
+        "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH2",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Tracker Cycles Not Empty; Channel 0",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Tracker Cycles Not Empty; Channel 1",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH1",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Tracker Cycles Not Empty; Channel 2",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH2",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Tracker Inserts; Channel 0",
+        "EventCode": "0x49",
+        "EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Tracker Inserts; Channel 1",
+        "EventCode": "0x49",
+        "EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Tracker Inserts; Channel 2",
+        "EventCode": "0x49",
+        "EventName": "UNC_M2M_TRACKER_INSERTS.CH2",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Tracker Occupancy; Channel 0",
+        "EventCode": "0x47",
+        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Tracker Occupancy; Channel 1",
+        "EventCode": "0x47",
+        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Tracker Occupancy; Channel 2",
+        "EventCode": "0x47",
+        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Data Pending Occupancy",
+        "EventCode": "0x48",
+        "EventName": "UNC_M2M_TRACKER_PENDING_OCCUPANCY",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "AD Egress (to CMS) Credit Acquired",
+        "EventCode": "0xD",
+        "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "AD Egress (to CMS) Credits Occupancy",
+        "EventCode": "0xE",
+        "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "AD Egress (to CMS) Full",
+        "EventCode": "0xC",
+        "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "AD Egress (to CMS) Not Empty",
+        "EventCode": "0xB",
+        "EventName": "UNC_M2M_TxC_AD_CYCLES_NE",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "AD Egress (to CMS) Allocations",
+        "EventCode": "0x9",
+        "EventName": "UNC_M2M_TxC_AD_INSERTS",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Cycles with No AD Egress (to CMS) Credits",
+        "EventCode": "0xF",
+        "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits",
+        "EventCode": "0x10",
+        "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "AD Egress (to CMS) Occupancy",
+        "EventCode": "0xA",
+        "EventName": "UNC_M2M_TxC_AD_OCCUPANCY",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Outbound Ring Transactions on AK; CRD Transactions to Cbo",
+        "EventCode": "0x39",
+        "EventName": "UNC_M2M_TxC_AK.CRD_CBO",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Outbound Ring Transactions on AK; NDR Transactions",
+        "EventCode": "0x39",
+        "EventName": "UNC_M2M_TxC_AK.NDR",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side",
+        "EventCode": "0x1E",
+        "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side",
+        "EventCode": "0x1E",
+        "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS1",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Full; All",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "UMask": "0x3",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Near Side",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Far Side",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "UMask": "0x88",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "UMask": "0xa0",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "UMask": "0x90",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Not Empty; All",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "UMask": "0x3",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Near Side",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Far Side",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Not Empty; Read Credit Request",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Not Empty; Write Compare Request",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Not Empty; Write Credit Request",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Allocations; All",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "UMask": "0x3",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Near Side",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Far Side",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Allocations; Prefetch Read Cam Hit",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Allocations; Read Credit Request",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Allocations; Write Compare Request",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Allocations; Write Credit Request",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side",
+        "EventCode": "0x1F",
+        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side",
+        "EventCode": "0x1F",
+        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side",
+        "EventCode": "0x20",
+        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side",
+        "EventCode": "0x20",
+        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Occupancy; All",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "UMask": "0x3",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Near Side",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Far Side",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Occupancy; Read Credit Request",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Occupancy; Write Compare Request",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP",
         "PerPkg": "1",
-        "PortMask": "0x02",
         "UMask": "0x20",
-        "Unit": "IIO"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Occupancy; Write Credit Request",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Sideband",
+        "EventCode": "0x6B",
+        "EventName": "UNC_M2M_TxC_AK_SIDEBAND.RD",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Messages",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "AK Egress (to CMS) Sideband",
+        "EventCode": "0x6B",
+        "EventName": "UNC_M2M_TxC_AK_SIDEBAND.WR",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Messages",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2M_TxC_BL.DRS_CACHE",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Messages",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2M_TxC_BL.DRS_CORE",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Messages",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2M_TxC_BL.DRS_UPI",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Card reading from DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side",
+        "EventCode": "0x1A",
+        "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS0",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Card reading from DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side",
+        "EventCode": "0x1A",
+        "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS1",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Card writing to DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "BL Egress (to CMS) Full; All",
+        "EventCode": "0x18",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "UMask": "0x3",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Card writing to DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Near Side",
+        "EventCode": "0x18",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Messages",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Far Side",
+        "EventCode": "0x18",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Messages",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "BL Egress (to CMS) Not Empty; All",
+        "EventCode": "0x17",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "UMask": "0x3",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Near Side",
+        "EventCode": "0x17",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Far Side",
+        "EventCode": "0x17",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "BL Egress (to CMS) Allocations; All",
+        "EventCode": "0x15",
+        "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "UMask": "0x3",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Near Side",
+        "EventCode": "0x15",
+        "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Far Side",
+        "EventCode": "0x15",
+        "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side",
+        "EventCode": "0x1B",
+        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side",
+        "EventCode": "0x1B",
+        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "BL Egress (to CMS) Occupancy; All",
+        "EventCode": "0x16",
+        "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "UMask": "0x3",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Near Side",
+        "EventCode": "0x16",
+        "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS0",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Far Side",
+        "EventCode": "0x16",
+        "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS1",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_BNC",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AK_BNC",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_BNC",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_BNC",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK_BNC",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_BNC",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "PortMask": "0x20",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
         "UMask": "0x40",
-        "Unit": "IIO"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV_BNC",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_BNC",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK_BNC",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_BNC",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV_BNC",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce",
+        "EventCode": "0x97",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_BNC",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit",
+        "EventCode": "0x97",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce",
+        "EventCode": "0x97",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK_BNC",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce",
+        "EventCode": "0x97",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_BNC",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit",
+        "EventCode": "0x97",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce",
+        "EventCode": "0x97",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV_BNC",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce",
+        "EventCode": "0x95",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_BNC",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit",
+        "EventCode": "0x95",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce",
+        "EventCode": "0x95",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK_BNC",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce",
+        "EventCode": "0x95",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_BNC",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit",
+        "EventCode": "0x95",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce",
+        "EventCode": "0x95",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV_BNC",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce",
+        "EventCode": "0x99",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_BNC",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit",
+        "EventCode": "0x99",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce",
+        "EventCode": "0x99",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.AK_BNC",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce",
+        "EventCode": "0x99",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_BNC",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit",
+        "EventCode": "0x99",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce",
+        "EventCode": "0x99",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.IV_BNC",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_BNC",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "PortMask": "0x10",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x10",
-        "Unit": "IIO"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK_BNC",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_BNC",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV_BNC",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_BNC",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Messages",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK_BNC",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Messages",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_BNC",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Messages",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV_BNC",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Messages",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Messages",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Messages",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG0",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Total Write Cache Occupancy; Any Source",
-        "Counter": "0,1",
-        "EventCode": "0xF",
-        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
+        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "IRP"
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Total Write Cache Occupancy; Snoops",
-        "Counter": "0,1",
-        "EventCode": "0xF",
-        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q",
+        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "IRP"
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "IRP Clocks",
-        "Counter": "0,1",
-        "EventCode": "0x1",
-        "EventName": "UNC_I_CLOCKTICKS",
+        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Coherent Ops; PCIRdCur",
-        "Counter": "0,1",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
+        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
         "UMask": "0x1",
-        "Unit": "IRP"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Coherent Ops; CRd",
-        "Counter": "0,1",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.CRD",
+        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1",
+        "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
         "UMask": "0x2",
-        "Unit": "IRP"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Coherent Ops; DRd",
-        "Counter": "0,1",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.DRD",
+        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "IRP"
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Coherent Ops; PCIDCAHin5t",
-        "Counter": "0,1",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
+        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IRP"
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Coherent Ops; WbMtoI",
-        "Counter": "0,1",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
+        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
         "UMask": "0x40",
-        "Unit": "IRP"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Coherent Ops; CLFlush",
-        "Counter": "0,1",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
+        "BriefDescription": "CMS Vertical ADS Used; IV",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "IRP"
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "FAF RF full",
-        "Counter": "0,1",
-        "EventCode": "0x17",
-        "EventName": "UNC_I_FAF_FULL",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG0",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "FAF allocation -- sent to ADQ",
-        "Counter": "0,1",
-        "EventCode": "0x16",
-        "EventName": "UNC_I_FAF_TRANSACTIONS",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG1",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "All Inserts Inbound (p2p + faf + cset)",
-        "Counter": "0,1",
-        "EventCode": "0x1E",
-        "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "IRP"
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "All Inserts Outbound (BL, AK, Snoops)",
-        "Counter": "0,1",
-        "EventCode": "0x1E",
-        "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "IRP"
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
-        "Counter": "0,1",
-        "EventCode": "0x1C",
-        "EventName": "UNC_I_MISC0.FAST_REQ",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "IRP"
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
-        "Counter": "0,1",
-        "EventCode": "0x1C",
-        "EventName": "UNC_I_MISC0.FAST_REJ",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "IRP"
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
-        "Counter": "0,1",
-        "EventCode": "0x1C",
-        "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.IV",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "IRP"
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
-        "Counter": "0,1",
-        "EventCode": "0x1C",
-        "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0",
+        "EventCode": "0x93",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "IRP"
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
-        "Counter": "0,1",
-        "EventCode": "0x1C",
-        "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1",
+        "EventCode": "0x93",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
         "UMask": "0x10",
-        "Unit": "IRP"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
-        "Counter": "0,1",
-        "EventCode": "0x1C",
-        "EventName": "UNC_I_MISC0.FAST_XFER",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0",
+        "EventCode": "0x93",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG0",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1",
+        "EventCode": "0x93",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
         "UMask": "0x20",
-        "Unit": "IRP"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
-        "Counter": "0,1",
-        "EventCode": "0x1C",
-        "EventName": "UNC_I_MISC0.PF_ACK_HINT",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0",
+        "EventCode": "0x93",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG0",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1",
+        "EventCode": "0x93",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
         "UMask": "0x40",
-        "Unit": "IRP"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Misc Events - Set 0",
-        "Counter": "0,1",
-        "EventCode": "0x1C",
-        "EventName": "UNC_I_MISC0.UNKNOWN",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV",
+        "EventCode": "0x93",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "IRP"
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
-        "Counter": "0,1",
-        "EventCode": "0x1D",
-        "EventName": "UNC_I_MISC1.SLOW_I",
+        "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0",
+        "EventCode": "0x91",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG0",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
         "UMask": "0x1",
-        "Unit": "IRP"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
-        "Counter": "0,1",
-        "EventCode": "0x1D",
-        "EventName": "UNC_I_MISC1.SLOW_S",
+        "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1",
+        "EventCode": "0x91",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG1",
+        "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0",
+        "EventCode": "0x91",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG0",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
         "UMask": "0x2",
-        "Unit": "IRP"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
-        "Counter": "0,1",
-        "EventCode": "0x1D",
-        "EventName": "UNC_I_MISC1.SLOW_E",
+        "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1",
+        "EventCode": "0x91",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG1",
+        "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0",
+        "EventCode": "0x91",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG0",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
         "UMask": "0x4",
-        "Unit": "IRP"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
-        "Counter": "0,1",
-        "EventCode": "0x1D",
-        "EventName": "UNC_I_MISC1.SLOW_M",
+        "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1",
+        "EventCode": "0x91",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "IRP"
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Lost Forward",
-        "Counter": "0,1",
-        "EventCode": "0x1D",
-        "EventName": "UNC_I_MISC1.LOST_FWD",
+        "BriefDescription": "CMS Vert Egress Allocations; IV",
+        "EventCode": "0x91",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS.IV",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IRP"
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Received Invalid",
-        "Counter": "0,1",
-        "EventCode": "0x1D",
-        "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
+        "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IRP"
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Received Valid",
-        "Counter": "0,1",
-        "EventCode": "0x1D",
-        "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
+        "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "IRP"
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "P2P Requests",
-        "Counter": "0,1",
-        "EventCode": "0x14",
-        "EventName": "UNC_I_P2P_INSERTS",
+        "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG0",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "P2P Occupancy",
-        "Counter": "0,1",
-        "EventCode": "0x15",
-        "EventName": "UNC_I_P2P_OCCUPANCY",
+        "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG1",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "P2P Transactions; P2P reads",
-        "Counter": "0,1",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.RD",
+        "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "IRP"
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "P2P Transactions; P2P Writes",
-        "Counter": "0,1",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.WR",
+        "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "IRP"
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "P2P Transactions; P2P Message",
-        "Counter": "0,1",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.MSG",
+        "BriefDescription": "CMS Vertical Egress NACKs; IV",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK.IV",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "IRP"
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "P2P Transactions; P2P completions",
-        "Counter": "0,1",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL",
+        "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "IRP"
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "P2P Transactions; Match if remote only",
-        "Counter": "0,1",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.REM",
+        "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
         "UMask": "0x10",
-        "Unit": "IRP"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "P2P Transactions; match if remote and target matches",
-        "Counter": "0,1",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH",
+        "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IRP"
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "P2P Transactions; match if local only",
-        "Counter": "0,1",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.LOC",
+        "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "IRP"
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "P2P Transactions; match if local and target matches",
-        "Counter": "0,1",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH",
+        "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "IRP"
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Snoop Responses; Miss",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.MISS",
+        "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "IRP"
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Snoop Responses; Hit I",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.HIT_I",
+        "BriefDescription": "CMS Vert Egress Occupancy; IV",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.IV",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "IRP"
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Snoop Responses; Hit E or S",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "IRP"
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Snoop Responses; Hit M",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.HIT_M",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "IRP"
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Snoop Responses; SnpCode",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IRP"
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Snoop Responses; SnpData",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
         "UMask": "0x20",
-        "Unit": "IRP"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Snoop Responses; SnpInv",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.SNPINV",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "IRP"
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Inbound Transaction Count; Reads",
-        "Counter": "0,1",
-        "EventCode": "0x11",
-        "EventName": "UNC_I_TRANSACTIONS.READS",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "IRP"
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Inbound Transaction Count; Writes",
-        "Counter": "0,1",
-        "EventCode": "0x11",
-        "EventName": "UNC_I_TRANSACTIONS.WRITES",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED.IV",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "IRP"
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Inbound Transaction Count; Read Prefetches",
-        "Counter": "0,1",
-        "EventCode": "0x11",
-        "EventName": "UNC_I_TRANSACTIONS.RD_PREF",
+        "BriefDescription": "Vertical AD Ring In Use; Down and Even",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
         "UMask": "0x4",
-        "Unit": "IRP"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Inbound Transaction Count; Atomic",
-        "Counter": "0,1",
-        "EventCode": "0x11",
-        "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
+        "BriefDescription": "Vertical AD Ring In Use; Down and Odd",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IRP"
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Inbound Transaction Count; Other",
-        "Counter": "0,1",
-        "EventCode": "0x11",
-        "EventName": "UNC_I_TRANSACTIONS.OTHER",
+        "BriefDescription": "Vertical AD Ring In Use; Up and Even",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IRP"
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "No AD Egress Credit Stalls",
-        "Counter": "0,1",
-        "EventCode": "0x1A",
-        "EventName": "UNC_I_TxR2_AD_STALL_CREDIT_CYCLES",
+        "BriefDescription": "Vertical AD Ring In Use; Up and Odd",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress Allocations",
-        "Counter": "0,1",
-        "EventCode": "0xB",
-        "EventName": "UNC_I_TxC_AK_INSERTS",
+        "BriefDescription": "Vertical AK Ring In Use; Down and Even",
+        "EventCode": "0xA8",
+        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL DRS Egress Cycles Full",
-        "Counter": "0,1",
-        "EventCode": "0x5",
-        "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL",
+        "BriefDescription": "Vertical AK Ring In Use; Down and Odd",
+        "EventCode": "0xA8",
+        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL DRS Egress Inserts",
-        "Counter": "0,1",
-        "EventCode": "0x2",
-        "EventName": "UNC_I_TxC_BL_DRS_INSERTS",
+        "BriefDescription": "Vertical AK Ring In Use; Up and Even",
+        "EventCode": "0xA8",
+        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL DRS Egress Occupancy",
-        "Counter": "0,1",
-        "EventCode": "0x8",
-        "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY",
+        "BriefDescription": "Vertical AK Ring In Use; Up and Odd",
+        "EventCode": "0xA8",
+        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL NCB Egress Cycles Full",
-        "Counter": "0,1",
-        "EventCode": "0x6",
-        "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL",
+        "BriefDescription": "Vertical BL Ring in Use; Down and Even",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL NCB Egress Inserts",
-        "Counter": "0,1",
-        "EventCode": "0x3",
-        "EventName": "UNC_I_TxC_BL_NCB_INSERTS",
+        "BriefDescription": "Vertical BL Ring in Use; Down and Odd",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL NCB Egress Occupancy",
-        "Counter": "0,1",
-        "EventCode": "0x9",
-        "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY",
+        "BriefDescription": "Vertical BL Ring in Use; Up and Even",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL NCS Egress Cycles Full",
-        "Counter": "0,1",
-        "EventCode": "0x7",
-        "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL",
+        "BriefDescription": "Vertical BL Ring in Use; Up and Odd",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL NCS Egress Inserts",
-        "Counter": "0,1",
-        "EventCode": "0x4",
-        "EventName": "UNC_I_TxC_BL_NCS_INSERTS",
+        "BriefDescription": "Vertical IV Ring in Use; Down",
+        "EventCode": "0xAC",
+        "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL NCS Egress Occupancy",
-        "Counter": "0,1",
-        "EventCode": "0xA",
-        "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY",
+        "BriefDescription": "Vertical IV Ring in Use; Up",
+        "EventCode": "0xAC",
+        "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "No BL Egress Credit Stalls",
-        "Counter": "0,1",
-        "EventCode": "0x1B",
-        "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0",
+        "Deprecated": "1",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Outbound Read Requests",
-        "Counter": "0,1",
-        "EventCode": "0xD",
-        "EventName": "UNC_I_TxS_DATA_INSERTS_NCB",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1",
+        "Deprecated": "1",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Outbound Read Requests",
-        "Counter": "0,1",
-        "EventCode": "0xE",
-        "EventName": "UNC_I_TxS_DATA_INSERTS_NCS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2",
+        "Deprecated": "1",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Outbound Request Queue Occupancy",
-        "Counter": "0,1",
-        "EventCode": "0xC",
-        "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY",
+        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I",
+        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1",
         "PerPkg": "1",
-        "UMask": "0x72",
-        "Unit": "IRP"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES",
+        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2",
         "PerPkg": "1",
-        "UMask": "0x74",
-        "Unit": "IRP"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M",
+        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 0",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN0",
         "PerPkg": "1",
-        "UMask": "0x78",
-        "Unit": "IRP"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT",
+        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 1",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN1",
         "PerPkg": "1",
-        "UMask": "0x7e",
-        "Unit": "IRP"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Responses to snoops of any type that miss the IIO cache",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.ALL_MISS",
+        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 2",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN2",
         "PerPkg": "1",
-        "UMask": "0x71",
-        "Unit": "IRP"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
+        "BriefDescription": "Write Tracker Cycles Full; Channel 0",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH0",
         "PerPkg": "1",
         "UMask": "0x1",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
+        "BriefDescription": "Write Tracker Cycles Full; Channel 1",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "UPI LL"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
+        "BriefDescription": "Write Tracker Cycles Full; Channel 2",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH2",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "UPI LL"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
+        "BriefDescription": "Write Tracker Cycles Not Empty; Channel 0",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH0",
         "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "UPI LL"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
+        "BriefDescription": "Write Tracker Cycles Not Empty; Channel 1",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH1",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "UPI LL"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
+        "BriefDescription": "Write Tracker Cycles Not Empty; Channel 2",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH2",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Write Tracker Inserts; Channel 0",
+        "EventCode": "0x61",
+        "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH0",
         "PerPkg": "1",
         "UMask": "0x1",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
+        "BriefDescription": "Write Tracker Inserts; Channel 1",
+        "EventCode": "0x61",
+        "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH1",
         "PerPkg": "1",
         "UMask": "0x2",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
+        "BriefDescription": "Write Tracker Inserts; Channel 2",
+        "EventCode": "0x61",
+        "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH2",
         "PerPkg": "1",
         "UMask": "0x4",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
+        "BriefDescription": "Write Tracker Occupancy; Channel 0",
+        "EventCode": "0x60",
+        "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH0",
         "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "UPI LL"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
+        "BriefDescription": "Write Tracker Occupancy; Channel 1",
+        "EventCode": "0x60",
+        "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH1",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "UPI LL"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x16",
-        "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
+        "BriefDescription": "Write Tracker Occupancy; Channel 2",
+        "EventCode": "0x60",
+        "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH2",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
+        "EventCode": "0x80",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x1",
-        "Unit": "UPI LL"
-    },
-    {
-        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
+        "EventCode": "0x80",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x2",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
+        "EventCode": "0x80",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR2",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x4",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
+        "EventCode": "0x80",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x8",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
+        "EventCode": "0x80",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x10",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
+        "EventCode": "0x80",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x20",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
+        "EventCode": "0x82",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_UPI_PHY_INIT_CYCLES",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
+        "EventCode": "0x82",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "L1 Req Nack",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x23",
-        "EventName": "UNC_UPI_POWER_L1_NACK",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
+        "EventCode": "0x82",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "L1 Req (same as L1 Ack)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x22",
-        "EventName": "UNC_UPI_POWER_L1_REQ",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
+        "EventCode": "0x82",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x46",
-        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
+        "EventCode": "0x82",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x46",
-        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
+        "EventCode": "0x82",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x46",
-        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
+        "EventCode": "0x88",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x46",
-        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
+        "EventCode": "0x88",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles in L0. Receive side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x24",
-        "EventName": "UNC_UPI_RxL0_POWER_CYCLES",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
+        "EventCode": "0x88",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Credit Consumed",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
+        "EventCode": "0x88",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Credit Consumed",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3A",
-        "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
+        "EventCode": "0x88",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VNA Credit Consumed",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
+        "EventCode": "0x88",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Valid Flits Received; Slot 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.SLOT0",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
         "UMask": "0x1",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Valid Flits Received; Slot 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.SLOT1",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
         "UMask": "0x2",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Valid Flits Received; Slot 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.SLOT2",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
         "UMask": "0x4",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Valid Flits Received; Data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.DATA",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
         "UMask": "0x8",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Valid Flits Received; LLCRD Not Empty",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.LLCRD",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
         "UMask": "0x10",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Valid Flits Received; LLCTRL",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.LLCTRL",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.PROTHDR",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.PROT_HDR",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
+        "EventCode": "0x84",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_HDR_MATCH.REQ",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
+        "EventCode": "0x84",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR1",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
+        "EventCode": "0x84",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR2",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
+        "EventCode": "0x84",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x8",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_HDR_MATCH.SNP",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
+        "EventCode": "0x84",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
-        "UMask": "0x9",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_HDR_MATCH.RSP",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
+        "EventCode": "0x84",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
-        "UMask": "0xA",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_HDR_MATCH.WB",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
+        "EventCode": "0x86",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0xB",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_HDR_MATCH.NCB",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
+        "EventCode": "0x86",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "UMask": "0xC",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_HDR_MATCH.NCS",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
+        "EventCode": "0x86",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0xD",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "RxQ Occupancy - All Packets; Slot 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
+        "EventCode": "0x86",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "RxQ Occupancy - All Packets; Slot 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
+        "EventCode": "0x86",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "RxQ Occupancy - All Packets; Slot 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
+        "EventCode": "0x86",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
         "UMask": "0x1",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
         "UMask": "0x2",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
         "UMask": "0x4",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
         "UMask": "0x8",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
         "UMask": "0x10",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
         "UMask": "0x20",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR0",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x1",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR1",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x2",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR2",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x4",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR3",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x8",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x10",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x20",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
+        "BriefDescription": "CBox AD Credits Empty; Requests",
+        "EventCode": "0x22",
+        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "UPI LL"
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
+        "BriefDescription": "CBox AD Credits Empty; Snoops",
+        "EventCode": "0x22",
+        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "UPI LL"
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x28",
-        "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
+        "BriefDescription": "CBox AD Credits Empty; VNA Messages",
+        "EventCode": "0x22",
+        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x29",
-        "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
+        "BriefDescription": "CBox AD Credits Empty; Writebacks",
+        "EventCode": "0x22",
+        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles in L0. Transmit side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x26",
-        "EventName": "UNC_UPI_TxL0_POWER_CYCLES",
+        "BriefDescription": "Number of uclks in domain",
+        "EventCode": "0x1",
+        "EventName": "UNC_M3UPI_CLOCKTICKS",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of uclks in the M3 uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Valid Flits Sent; Slot 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.SLOT0",
+        "BriefDescription": "CMS Clockticks",
+        "EventCode": "0xC0",
+        "EventName": "UNC_M3UPI_CMS_CLOCKTICKS",
+        "PerPkg": "1",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "D2C Sent",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M3UPI_D2C_SENT",
+        "PerPkg": "1",
+        "PublicDescription": "Count cases BL sends direct to core",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "D2U Sent",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M3UPI_D2U_SENT",
+        "PerPkg": "1",
+        "PublicDescription": "Cases where SMI3 sends D2U command",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
+        "EventCode": "0xAE",
+        "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN",
+        "PerPkg": "1",
+        "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
+        "EventCode": "0xAE",
+        "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP",
         "PerPkg": "1",
+        "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
         "UMask": "0x1",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Valid Flits Sent; Slot 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.SLOT1",
+        "BriefDescription": "FaST wire asserted; Horizontal",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M3UPI_FAST_ASSERTED.HORZ",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
         "UMask": "0x2",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Valid Flits Sent; Slot 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.SLOT2",
+        "BriefDescription": "FaST wire asserted; Vertical",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M3UPI_FAST_ASSERTED.VERT",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Valid Flits Sent; LLCRD Not Empty",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.LLCRD",
+        "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Valid Flits Sent; LLCTRL",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.LLCTRL",
+        "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.PROTHDR",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.PROT_HDR",
+        "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.REQ",
+        "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
         "UMask": "0x8",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.SNP",
+        "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
+        "EventCode": "0xA9",
+        "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x9",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.WB",
+        "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
+        "EventCode": "0xA9",
+        "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0xC",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.NCB",
+        "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
+        "EventCode": "0xA9",
+        "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0xE",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.NCS",
+        "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
+        "EventCode": "0xA9",
+        "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0xF",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Tx Flit Buffer Allocations",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x40",
-        "EventName": "UNC_UPI_TxL_INSERTS",
+        "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Tx Flit Buffer Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x42",
-        "EventName": "UNC_UPI_TxL_OCCUPANCY",
+        "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x45",
-        "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
+        "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VNA Credits Pending Return - Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x44",
-        "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY",
+        "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
+        "BriefDescription": "Horizontal IV Ring in Use; Left",
+        "EventCode": "0xAD",
+        "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Valid Flits Received; Protocol Header",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.PROTHDR",
+        "BriefDescription": "Horizontal IV Ring in Use; Right",
+        "EventCode": "0xAD",
+        "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Valid Flits Sent; Protocol Header",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.PROTHDR",
+        "BriefDescription": "M2 BL Credits Empty; IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)",
+        "EventCode": "0x23",
+        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO0_IIO1_NCB",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "UPI LL"
+        "PublicDescription": "No vn0 and vna credits available to send to M2",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
+        "BriefDescription": "M2 BL Credits Empty; IIO2",
+        "EventCode": "0x23",
+        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "UPI LL"
+        "PublicDescription": "No vn0 and vna credits available to send to M2",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
+        "BriefDescription": "M2 BL Credits Empty; IIO3",
+        "EventCode": "0x23",
+        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "UPI LL"
+        "PublicDescription": "No vn0 and vna credits available to send to M2",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.LOC",
+        "BriefDescription": "M2 BL Credits Empty; IIO4",
+        "EventCode": "0x23",
+        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB",
         "PerPkg": "1",
-        "UMaskExt": "0x02",
-        "Unit": "UPI LL"
+        "PublicDescription": "No vn0 and vna credits available to send to M2",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.REM",
+        "BriefDescription": "M2 BL Credits Empty; IIO5",
+        "EventCode": "0x23",
+        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB",
         "PerPkg": "1",
-        "UMaskExt": "0x04",
-        "Unit": "UPI LL"
+        "PublicDescription": "No vn0 and vna credits available to send to M2",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.DATA_HDR",
+        "BriefDescription": "M2 BL Credits Empty; All IIO targets for NCS are in single mask. ORs them together",
+        "EventCode": "0x23",
+        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS",
         "PerPkg": "1",
-        "UMaskExt": "0x08",
-        "Unit": "UPI LL"
+        "PublicDescription": "No vn0 and vna credits available to send to M2",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.NON_DATA_HDR",
+        "BriefDescription": "M2 BL Credits Empty; Selected M2p BL NCS credits",
+        "EventCode": "0x23",
+        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL",
         "PerPkg": "1",
-        "UMaskExt": "0x10",
-        "Unit": "UPI LL"
+        "PublicDescription": "No vn0 and vna credits available to send to M2",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.DUAL_SLOT_HDR",
+        "BriefDescription": "Multi Slot Flit Received; AD - Slot 0",
+        "EventCode": "0x3E",
+        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0",
         "PerPkg": "1",
-        "UMaskExt": "0x20",
-        "Unit": "UPI LL"
+        "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.SGL_SLOT_HDR",
+        "BriefDescription": "Multi Slot Flit Received; AD - Slot 1",
+        "EventCode": "0x3E",
+        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1",
         "PerPkg": "1",
-        "UMaskExt": "0x40",
-        "Unit": "UPI LL"
+        "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_NODATA",
+        "BriefDescription": "Multi Slot Flit Received; AD - Slot 2",
+        "EventCode": "0x3E",
+        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2",
         "PerPkg": "1",
-        "UMask": "0xA",
-        "Unit": "UPI LL"
+        "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_DATA",
+        "BriefDescription": "Multi Slot Flit Received; AK - Slot 0",
+        "EventCode": "0x3E",
+        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0",
         "PerPkg": "1",
-        "UMask": "0xC",
-        "Unit": "UPI LL"
+        "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Valid Flits Received; Idle",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.IDLE",
+        "BriefDescription": "Multi Slot Flit Received; AK - Slot 2",
+        "EventCode": "0x3E",
+        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2",
         "PerPkg": "1",
-        "UMask": "0x47",
-        "Unit": "UPI LL"
+        "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
+        "BriefDescription": "Multi Slot Flit Received; BL - Slot 0",
+        "EventCode": "0x3E",
+        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "UPI LL"
+        "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Request Opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x0108",
-        "UMaskExt": "0x01",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Snoop",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x09",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Snoop Opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x0109",
-        "UMaskExt": "0x01",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x0A",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD",
         "PerPkg": "1",
-        "UMask": "0x010A",
-        "UMaskExt": "0x01",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x0C",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x010C",
-        "UMaskExt": "0x01",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Writeback",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x0D",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Writeback",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x010D",
-        "UMaskExt": "0x01",
-        "Unit": "UPI LL"
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x0E",
-        "Unit": "UPI LL"
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x010E",
-        "UMaskExt": "0x01",
-        "Unit": "UPI LL"
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x0F",
-        "Unit": "UPI LL"
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x010F",
-        "UMaskExt": "0x01",
-        "Unit": "UPI LL"
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
+        "BriefDescription": "Sink Starvation on Vertical Ring; AD",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "UPI LL"
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Request Opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC",
+        "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x108",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
+        "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x09",
-        "Unit": "UPI LL"
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop Opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC",
+        "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x109",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
+        "BriefDescription": "Source Throttle",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M3UPI_RING_SRC_THRTL",
         "PerPkg": "1",
-        "UMask": "0x0A",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
+        "BriefDescription": "Lost Arb for VN0; REQ on AD",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x10A",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PublicDescription": "VN0 message requested but lost arbitration; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
+        "BriefDescription": "Lost Arb for VN0; RSP on AD",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x0C",
-        "Unit": "UPI LL"
+        "PublicDescription": "VN0 message requested but lost arbitration; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
+        "BriefDescription": "Lost Arb for VN0; SNP on AD",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x10C",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PublicDescription": "VN0 message requested but lost arbitration; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
+        "BriefDescription": "Lost Arb for VN0; NCB on BL",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x0D",
-        "Unit": "UPI LL"
+        "PublicDescription": "VN0 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC",
+        "BriefDescription": "Lost Arb for VN0; NCS on BL",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x10D",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PublicDescription": "VN0 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
+        "BriefDescription": "Lost Arb for VN0; RSP on BL",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x0E",
-        "Unit": "UPI LL"
+        "PublicDescription": "VN0 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
+        "BriefDescription": "Lost Arb for VN0; WB on BL",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x10E",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PublicDescription": "VN0 message requested but lost arbitration; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
+        "BriefDescription": "Lost Arb for VN1; REQ on AD",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x0F",
-        "Unit": "UPI LL"
+        "PublicDescription": "VN1 message requested but lost arbitration; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
+        "BriefDescription": "Lost Arb for VN1; RSP on AD",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x10F",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PublicDescription": "VN1 message requested but lost arbitration; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Response - Conflict",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT",
+        "BriefDescription": "Lost Arb for VN1; SNP on AD",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x01AA",
-        "UMaskExt": "0x01",
-        "Unit": "UPI LL"
+        "PublicDescription": "VN1 message requested but lost arbitration; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Response - Invalid",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI",
+        "BriefDescription": "Lost Arb for VN1; NCB on BL",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x012A",
-        "UMaskExt": "0x01",
-        "Unit": "UPI LL"
+        "PublicDescription": "VN1 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "RxQ Flit Buffer Allocations; Slot 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x30",
-        "EventName": "UNC_UPI_RxL_INSERTS.SLOT0",
+        "BriefDescription": "Lost Arb for VN1; NCS on BL",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "UPI LL"
+        "PublicDescription": "VN1 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "RxQ Flit Buffer Allocations; Slot 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x30",
-        "EventName": "UNC_UPI_RxL_INSERTS.SLOT1",
+        "BriefDescription": "Lost Arb for VN1; RSP on BL",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "UPI LL"
+        "PublicDescription": "VN1 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "RxQ Flit Buffer Allocations; Slot 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x30",
-        "EventName": "UNC_UPI_RxL_INSERTS.SLOT2",
+        "BriefDescription": "Lost Arb for VN1; WB on BL",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "UPI LL"
+        "PublicDescription": "VN1 message requested but lost arbitration; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Conflict",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT",
+        "BriefDescription": "Arb Miscellaneous; AD, BL Parallel Win",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN",
         "PerPkg": "1",
-        "UMask": "0x1AA",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PublicDescription": "AD and BL messages won arbitration concurrently / in parallel",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Invalid",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI",
+        "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN0",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0",
         "PerPkg": "1",
-        "UMask": "0x12A",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UPI0 AD Credits Empty; VNA",
-        "Counter": "0,1,2",
-        "EventCode": "0x20",
-        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA",
+        "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN1",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UPI0 AD Credits Empty; VN0 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x20",
-        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ",
+        "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN0",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UPI0 AD Credits Empty; VN0 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x20",
-        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP",
+        "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN1",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UPI0 AD Credits Empty; VN0 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x20",
-        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP",
+        "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN0",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN0",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win to vn0, delaying vn1 win, because vn0 offered parallel ad/bl",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UPI0 AD Credits Empty; VN1 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x20",
-        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ",
+        "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN1",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win to vn1, delaying vn0 win, because vn1 offered parallel ad/bl",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UPI0 AD Credits Empty; VN1 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x20",
-        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP",
+        "BriefDescription": "Can't Arb for VN0; REQ on AD",
+        "EventCode": "0x49",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UPI0 AD Credits Empty; VN1 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x20",
-        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP",
+        "BriefDescription": "Can't Arb for VN0; RSP on AD",
+        "EventCode": "0x49",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UPI0 BL Credits Empty; VN1 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x21",
-        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP",
+        "BriefDescription": "Can't Arb for VN0; SNP on AD",
+        "EventCode": "0x49",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UPI0 BL Credits Empty; VN1 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x21",
-        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB",
+        "BriefDescription": "Can't Arb for VN0; NCB on BL",
+        "EventCode": "0x49",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCB",
         "PerPkg": "1",
+        "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UPI0 BL Credits Empty; VN1 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x21",
-        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB",
+        "BriefDescription": "Can't Arb for VN0; NCS on BL",
+        "EventCode": "0x49",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCS",
         "PerPkg": "1",
+        "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL.",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN0",
-        "EventCode": "0x3C",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI0",
+        "BriefDescription": "Can't Arb for VN0; RSP on BL",
+        "EventCode": "0x49",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN0",
-        "EventCode": "0x3C",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI1",
+        "BriefDescription": "Can't Arb for VN0; WB on BL",
+        "EventCode": "0x49",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN1",
-        "EventCode": "0x3C",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI0",
+        "BriefDescription": "Can't Arb for VN1; REQ on AD",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN1",
-        "EventCode": "0x3C",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI1",
+        "BriefDescription": "Can't Arb for VN1; RSP on AD",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CBox AD Credits Empty; VNA Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x22",
-        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA",
+        "BriefDescription": "Can't Arb for VN1; SNP on AD",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CBox AD Credits Empty; Writebacks",
-        "Counter": "0,1,2",
-        "EventCode": "0x22",
-        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB",
+        "BriefDescription": "Can't Arb for VN1; NCB on BL",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CBox AD Credits Empty; Requests",
-        "Counter": "0,1,2",
-        "EventCode": "0x22",
-        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ",
+        "BriefDescription": "Can't Arb for VN1; NCS on BL",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CBox AD Credits Empty; Snoops",
-        "Counter": "0,1,2",
-        "EventCode": "0x22",
-        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP",
+        "BriefDescription": "Can't Arb for VN1; RSP on BL",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Number of uclks in domain",
-        "Counter": "0,1,2",
-        "EventCode": "0x1",
-        "EventName": "UNC_M3UPI_CLOCKTICKS",
+        "BriefDescription": "Can't Arb for VN1; WB on BL",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_WB",
         "PerPkg": "1",
+        "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "D2U Sent",
-        "Counter": "0,1,2",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M3UPI_D2U_SENT",
+        "BriefDescription": "No Credits to Arb for VN0; REQ on AD",
+        "EventCode": "0x47",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_REQ",
         "PerPkg": "1",
+        "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2 BL Credits Empty; IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)",
-        "Counter": "0,1,2",
-        "EventCode": "0x23",
-        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO0_IIO1_NCB",
+        "BriefDescription": "No Credits to Arb for VN0; RSP on AD",
+        "EventCode": "0x47",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2 BL Credits Empty; IIO2",
-        "Counter": "0,1,2",
-        "EventCode": "0x23",
-        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB",
+        "BriefDescription": "No Credits to Arb for VN0; SNP on AD",
+        "EventCode": "0x47",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2 BL Credits Empty; IIO3",
-        "Counter": "0,1,2",
-        "EventCode": "0x23",
-        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB",
+        "BriefDescription": "No Credits to Arb for VN0; NCB on BL",
+        "EventCode": "0x47",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2 BL Credits Empty; IIO4",
-        "Counter": "0,1,2",
-        "EventCode": "0x23",
-        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB",
+        "BriefDescription": "No Credits to Arb for VN0; NCS on BL",
+        "EventCode": "0x47",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2 BL Credits Empty; IIO5",
-        "Counter": "0,1,2",
-        "EventCode": "0x23",
-        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB",
+        "BriefDescription": "No Credits to Arb for VN0; RSP on BL",
+        "EventCode": "0x47",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2 BL Credits Empty; All IIO targets for NCS are in single mask. ORs them together",
-        "Counter": "0,1,2",
-        "EventCode": "0x23",
-        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS",
+        "BriefDescription": "No Credits to Arb for VN0; WB on BL",
+        "EventCode": "0x47",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2 BL Credits Empty; Selected M2p BL NCS credits",
-        "Counter": "0,1,2",
-        "EventCode": "0x23",
-        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL",
+        "BriefDescription": "No Credits to Arb for VN1; REQ on AD",
+        "EventCode": "0x48",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Multi Slot Flit Received; AD - Slot 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x3E",
-        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0",
+        "BriefDescription": "No Credits to Arb for VN1; RSP on AD",
+        "EventCode": "0x48",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Multi Slot Flit Received; AD - Slot 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x3E",
-        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1",
+        "BriefDescription": "No Credits to Arb for VN1; SNP on AD",
+        "EventCode": "0x48",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Multi Slot Flit Received; AD - Slot 2",
-        "Counter": "0,1,2",
-        "EventCode": "0x3E",
-        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2",
+        "BriefDescription": "No Credits to Arb for VN1; NCB on BL",
+        "EventCode": "0x48",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Multi Slot Flit Received; BL - Slot 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x3E",
-        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0",
+        "BriefDescription": "No Credits to Arb for VN1; NCS on BL",
+        "EventCode": "0x48",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Multi Slot Flit Received; AK - Slot 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x3E",
-        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0",
+        "BriefDescription": "No Credits to Arb for VN1; RSP on BL",
+        "EventCode": "0x48",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Multi Slot Flit Received; AK - Slot 2",
-        "Counter": "0,1,2",
-        "EventCode": "0x3E",
-        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2",
+        "BriefDescription": "No Credits to Arb for VN1; WB on BL",
+        "EventCode": "0x48",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for AD; VN0 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ",
+        "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on BL Arb",
+        "EventCode": "0x40",
+        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number ot times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while bl message is in arbitration",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for AD; VN0 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP",
+        "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on Idle",
+        "EventCode": "0x40",
+        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number ot times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while pipeline is idle",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for AD; VN0 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP",
+        "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 1",
+        "EventCode": "0x40",
+        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number ot times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 1 while merging with bl message in same flit",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for AD; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB",
+        "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 2",
+        "EventCode": "0x40",
+        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number ot times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 2 while merging with bl message in same flit",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for AD; VN1 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ",
+        "BriefDescription": "VN0 message lost contest for flit; REQ on AD",
+        "EventCode": "0x50",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for AD; VN1 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP",
+        "BriefDescription": "VN0 message lost contest for flit; RSP on AD",
+        "EventCode": "0x50",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for AD; VN1 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP",
+        "BriefDescription": "VN0 message lost contest for flit; SNP on AD",
+        "EventCode": "0x50",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for AD; VN1 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB",
+        "BriefDescription": "VN0 message lost contest for flit; NCB on BL",
+        "EventCode": "0x50",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD FlowQ Bypass",
-        "Counter": "0,1,2",
-        "EventCode": "0x2C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0",
+        "BriefDescription": "VN0 message lost contest for flit; NCS on BL",
+        "EventCode": "0x50",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD FlowQ Bypass",
-        "Counter": "0,1,2",
-        "EventCode": "0x2C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1",
+        "BriefDescription": "VN0 message lost contest for flit; RSP on BL",
+        "EventCode": "0x50",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD FlowQ Bypass",
-        "Counter": "0,1,2",
-        "EventCode": "0x2C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2",
+        "BriefDescription": "VN0 message lost contest for flit; WB on BL",
+        "EventCode": "0x50",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD FlowQ Bypass",
-        "Counter": "0,1,2",
-        "EventCode": "0x2C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP",
+        "BriefDescription": "VN1 message lost contest for flit; REQ on AD",
+        "EventCode": "0x51",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty; VN0 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ",
+        "BriefDescription": "VN1 message lost contest for flit; RSP on AD",
+        "EventCode": "0x51",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty; VN0 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP",
+        "BriefDescription": "VN1 message lost contest for flit; SNP on AD",
+        "EventCode": "0x51",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty; VN0 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP",
+        "BriefDescription": "VN1 message lost contest for flit; NCB on BL",
+        "EventCode": "0x51",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB",
+        "BriefDescription": "VN1 message lost contest for flit; NCS on BL",
+        "EventCode": "0x51",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty; VN1 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ",
+        "BriefDescription": "VN1 message lost contest for flit; RSP on BL",
+        "EventCode": "0x51",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty; VN1 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP",
+        "BriefDescription": "VN1 message lost contest for flit; WB on BL",
+        "EventCode": "0x51",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty; VN1 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP",
+        "BriefDescription": "Miscellaneous Credit Events; Any In BGF FIFO",
+        "EventCode": "0x60",
+        "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Indication that at least one packet (flit) is in the bgf (fifo only)",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty; VN1 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB",
+        "BriefDescription": "Miscellaneous Credit Events; Any in BGF Path",
+        "EventCode": "0x60",
+        "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo)",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Inserts; VN0 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ",
+        "BriefDescription": "Miscellaneous Credit Events; No D2K For Arb",
+        "EventCode": "0x60",
+        "EventName": "UNC_M3UPI_RxC_CRD_MISC.NO_D2K_FOR_ARB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "VN0 or VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Inserts; VN0 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP",
+        "BriefDescription": "Credit Occupancy; D2K Credits",
+        "EventCode": "0x61",
+        "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "D2K completion fifo credit occupancy (credits in use), accumulated across all cycles",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Inserts; VN0 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP",
+        "BriefDescription": "Credit Occupancy; Packets in BGF FIFO",
+        "EventCode": "0x61",
+        "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Inserts; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB",
+        "BriefDescription": "Credit Occupancy; Packets in BGF Path",
+        "EventCode": "0x61",
+        "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo)",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Inserts; VN1 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ",
+        "BriefDescription": "Credit Occupancy",
+        "EventCode": "0x61",
+        "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "count of bl messages in pump-1-pending state, in completion fifo only",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Inserts; VN1 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP",
+        "BriefDescription": "Credit Occupancy",
+        "EventCode": "0x61",
+        "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL",
         "PerPkg": "1",
+        "PublicDescription": "count of bl messages in pump-1-pending state, in marker table and in fifo",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Inserts; VN1 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP",
+        "BriefDescription": "Credit Occupancy; Transmit Credits",
+        "EventCode": "0x61",
+        "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Occupancy; VN0 REQ Messages",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ",
+        "BriefDescription": "Credit Occupancy; VNA In Use",
+        "EventCode": "0x61",
+        "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Occupancy; VN0 SNP Messages",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD",
+        "EventCode": "0x43",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Occupancy; VN0 RSP Messages",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD",
+        "EventCode": "0x43",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Occupancy; VN0 WB Messages",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD",
+        "EventCode": "0x43",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Occupancy; VN1 REQ Messages",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL",
+        "EventCode": "0x43",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Occupancy; VN1 SNP Messages",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL",
+        "EventCode": "0x43",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Occupancy; VN1 RSP Messages",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL",
+        "EventCode": "0x43",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN0 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x34",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_REQ",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL",
+        "EventCode": "0x43",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN0 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x34",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_SNP",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD",
+        "EventCode": "0x44",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x34",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_WB",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD",
+        "EventCode": "0x44",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN1 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x34",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_REQ",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD",
+        "EventCode": "0x44",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN1 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x34",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_SNP",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL",
+        "EventCode": "0x44",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN1 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x34",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_WB",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL",
+        "EventCode": "0x44",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - New Message; VN0 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x33",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_REQ",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL",
+        "EventCode": "0x44",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - New Message; VN0 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x33",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_SNP",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL",
+        "EventCode": "0x44",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - New Message; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x33",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_WB",
+        "BriefDescription": "Data Flit Not Sent; All",
+        "EventCode": "0x57",
+        "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Data flit is ready for transmission but could not be sent",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - New Message; VN1 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x33",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_REQ",
+        "BriefDescription": "Data Flit Not Sent; No BGF Credits",
+        "EventCode": "0x57",
+        "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_BGF",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Data flit is ready for transmission but could not be sent",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - New Message; VN1 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x33",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_SNP",
+        "BriefDescription": "Data Flit Not Sent; No TxQ Credits",
+        "EventCode": "0x57",
+        "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_TXQ",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Data flit is ready for transmission but could not be sent",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - New Message; VN1 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x33",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_WB",
+        "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 0",
+        "EventCode": "0x59",
+        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "generating bl data flit sequence; waiting for data pump 0",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - No Credit; VN0 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x32",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_REQ",
+        "BriefDescription": "Generating BL Data Flit Sequence",
+        "EventCode": "0x59",
+        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "pump-1-pending logic is at capacity (pending table plus completion fifo at limit)",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - No Credit; VN0 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x32",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_SNP",
+        "BriefDescription": "Generating BL Data Flit Sequence",
+        "EventCode": "0x59",
+        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "pump-1-pending logic is tracking at least one message",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - No Credit; VN0 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x32",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_RSP",
+        "BriefDescription": "Generating BL Data Flit Sequence",
+        "EventCode": "0x59",
+        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "pump-1-pending completion fifo is full",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - No Credit; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x32",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_WB",
+        "BriefDescription": "Generating BL Data Flit Sequence",
+        "EventCode": "0x59",
+        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - No Credit; VN1 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x32",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_REQ",
+        "BriefDescription": "Generating BL Data Flit Sequence",
+        "EventCode": "0x59",
+        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "a bl message finished but is in limbo and moved to pump-1-pending logic",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - No Credit; VN1 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x32",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_SNP",
+        "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 1",
+        "EventCode": "0x59",
+        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "generating bl data flit sequence; waiting for data pump 1",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - No Credit; VN1 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x32",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_RSP",
+        "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC",
+        "EventCode": "0x5A",
+        "EventName": "UNC_M3UPI_RxC_FLITS_MISC",
         "PerPkg": "1",
-        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - No Credit; VN1 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x32",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_WB",
+        "BriefDescription": "Sent Header Flit; One Message",
+        "EventCode": "0x56",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "One message in flit; VNA or non-VNA flit",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Flow Q Inserts",
-        "Counter": "0,1,2",
-        "EventCode": "0x2F",
-        "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS",
+        "BriefDescription": "Sent Header Flit; One Message in non-VNA",
+        "EventCode": "0x56",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG_VNX",
         "PerPkg": "1",
+        "PublicDescription": "One message in flit; non-VNA flit",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Flow Q Occupancy",
-        "EventCode": "0x1E",
-        "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY",
+        "BriefDescription": "Sent Header Flit; Two Messages",
+        "EventCode": "0x56",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.2_MSGS",
         "PerPkg": "1",
+        "PublicDescription": "Two messages in flit; VNA flit",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for BL; VN0 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP",
+        "BriefDescription": "Sent Header Flit; Three Messages",
+        "EventCode": "0x56",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.3_MSGS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Three messages in flit; VNA flit",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for BL; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB",
+        "BriefDescription": "Sent Header Flit",
+        "EventCode": "0x56",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for BL; VN0 NCB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB",
+        "BriefDescription": "Sent Header Flit",
+        "EventCode": "0x56",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for BL; VN0 NCS Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS",
+        "BriefDescription": "Sent Header Flit",
+        "EventCode": "0x56",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for BL; VN1 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP",
+        "BriefDescription": "Slotting BL Message Into Header Flit; All",
+        "EventCode": "0x58",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for BL; VN1 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB",
+        "BriefDescription": "Slotting BL Message Into Header Flit; Needs Data Flit",
+        "EventCode": "0x58",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "BL message requires data flit sequence",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for BL; VN1 NCS Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB",
+        "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 0",
+        "EventCode": "0x58",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Waiting for header pump 0",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for BL; VN1 NCB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS",
+        "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1",
+        "EventCode": "0x58",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Header pump 1 is not required for flit",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty; VN0 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ",
+        "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Bubble",
+        "EventCode": "0x58",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Header pump 1 is not required for flit but flit transmission delayed",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty; VN0 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP",
+        "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Not Avail",
+        "EventCode": "0x58",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Header pump 1 is not required for flit and not available",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty; VN0 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP",
+        "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 1",
+        "EventCode": "0x58",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Waiting for header pump 1",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB",
+        "BriefDescription": "Flit Gen - Header 1; Acumullate",
+        "EventCode": "0x53",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty; VN1 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ",
+        "BriefDescription": "Flit Gen - Header 1; Accumulate Ready",
+        "EventCode": "0x53",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Events related to Header Flit Generation - Set 1; header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty; VN1 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP",
+        "BriefDescription": "Flit Gen - Header 1; Accumulate Wasted",
+        "EventCode": "0x53",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Events related to Header Flit Generation - Set 1; Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty; VN1 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP",
+        "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Blocked",
+        "EventCode": "0x53",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty; VN1 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB",
+        "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Message",
+        "EventCode": "0x53",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting is in run-ahead to start new flit, and message is actually slotted into new flit",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts; VN0 NCS Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP",
+        "BriefDescription": "Flit Gen - Header 1; Parallel Ok",
+        "EventCode": "0x53",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Events related to Header Flit Generation - Set 1; New header flit construction may proceed in parallel with data flit sequence",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts; VN0 NCB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB",
+        "BriefDescription": "Flit Gen - Header 1; Parallel Flit Finished",
+        "EventCode": "0x53",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_FLIT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit finished assembly in parallel with data flit sequence",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts; VN0 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB",
+        "BriefDescription": "Flit Gen - Header 1; Parallel Message",
+        "EventCode": "0x53",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_MSG",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Events related to Header Flit Generation - Set 1; Message is slotted into header flit in parallel with data flit sequence",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS",
+        "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall",
+        "EventCode": "0x54",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Events related to Header Flit Generation - Set 2; Rate-matching stall injected",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts; VN1_NCB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP",
+        "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall - No Message",
+        "EventCode": "0x54",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Events related to Header Flit Generation - Set 2; Rate matching stall injected, but no additional message slotted during stall cycle",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts; VN1_NCS Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB",
+        "BriefDescription": "Header Not Sent; All",
+        "EventCode": "0x55",
+        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ALL",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "header flit is ready for transmission but could not be sent",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts; VN1 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB",
+        "BriefDescription": "Header Not Sent; No BGF Credits",
+        "EventCode": "0x55",
+        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "header flit is ready for transmission but could not be sent; No BGF credits available",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts; VN1 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS",
+        "BriefDescription": "Header Not Sent; No BGF Credits + No Extra Message Slotted",
+        "EventCode": "0x55",
+        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_NO_MSG",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "header flit is ready for transmission but could not be sent; No BGF credits available; no additional message slotted into flit",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy; VN0 RSP Messages",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP",
+        "BriefDescription": "Header Not Sent; No TxQ Credits",
+        "EventCode": "0x55",
+        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "header flit is ready for transmission but could not be sent; No TxQ credits available",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy; VN0 WB Messages",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB",
+        "BriefDescription": "Header Not Sent; No TxQ Credits + No Extra Message Slotted",
+        "EventCode": "0x55",
+        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_NO_MSG",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "header flit is ready for transmission but could not be sent; No TxQ credits available; no additional message slotted into flit",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy; VN0 NCB Messages",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB",
+        "BriefDescription": "Header Not Sent; Sent - One Slot Taken",
+        "EventCode": "0x55",
+        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ONE_TAKEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with only one slot taken (two slots free)",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy; VN0 NCS Messages",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS",
+        "BriefDescription": "Header Not Sent; Sent - Three Slots Taken",
+        "EventCode": "0x55",
+        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.THREE_TAKEN",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with three slots taken (no slots free)",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy; VN1 RSP Messages",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP",
+        "BriefDescription": "Header Not Sent; Sent - Two Slots Taken",
+        "EventCode": "0x55",
+        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.TWO_TAKEN",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with only two slots taken (one slots free)",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy; VN1 WB Messages",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB",
+        "BriefDescription": "Message Held; Can't Slot AD",
+        "EventCode": "0x52",
+        "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "some AD message could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1})",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy; VN1_NCS Messages",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB",
+        "BriefDescription": "Message Held; Can't Slot BL",
+        "EventCode": "0x52",
+        "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "some BL message could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1})",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy; VN1_NCB Messages",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS",
+        "BriefDescription": "Message Held; Parallel AD Lost",
+        "EventCode": "0x52",
+        "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_AD_LOST",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "some AD message lost contest for slot 0 (logical OR of all AD events under INGR_SLOT_LOST_MC_VN{0,1})",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for BL  - New Message; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x38",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_WB",
+        "BriefDescription": "Message Held; Parallel Attempt",
+        "EventCode": "0x52",
+        "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "ad and bl messages attempted to slot into the same flit in parallel",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for BL  - New Message; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x38",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCB",
+        "BriefDescription": "Message Held; Parallel BL Lost",
+        "EventCode": "0x52",
+        "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_BL_LOST",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "some BL message lost contest for slot 0 (logical OR of all BL events under INGR_SLOT_LOST_MC_VN{0,1})",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for BL  - New Message; VN0 NCS Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x38",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCS",
+        "BriefDescription": "Message Held; Parallel Success",
+        "EventCode": "0x52",
+        "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "ad and bl messages were actually slotted into the same flit in paralle",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for BL  - New Message; VN1 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x38",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_WB",
+        "BriefDescription": "Message Held; VN0",
+        "EventCode": "0x52",
+        "EventName": "UNC_M3UPI_RxC_HELD.VN0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "vn0 message(s) that couldn't be slotted into last vn0 flit are held in slotting stage while processing vn1 flit",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for BL  - New Message; VN1 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x38",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCB",
+        "BriefDescription": "Message Held; VN1",
+        "EventCode": "0x52",
+        "EventName": "UNC_M3UPI_RxC_HELD.VN1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "vn1 message(s) that couldn't be slotted into last vn1 flit are held in slotting stage while processing vn0 flit",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for BL  - New Message; VN1 NCB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x38",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCS",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; REQ on AD",
+        "EventCode": "0x41",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x37",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_RSP",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on AD",
+        "EventCode": "0x41",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x37",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_WB",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; SNP on AD",
+        "EventCode": "0x41",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x37",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCB",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCB on BL",
+        "EventCode": "0x41",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCS Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x37",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCS",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCS on BL",
+        "EventCode": "0x41",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x37",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_RSP",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on BL",
+        "EventCode": "0x41",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x37",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_WB",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; WB on BL",
+        "EventCode": "0x41",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCS Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x37",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCB",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; REQ on AD",
+        "EventCode": "0x42",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x37",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCS",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on AD",
+        "EventCode": "0x42",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Credit Used; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5C",
-        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; SNP on AD",
+        "EventCode": "0x42",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Credit Used; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5C",
-        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCB on BL",
+        "EventCode": "0x42",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Credit Used; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5C",
-        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCS on BL",
+        "EventCode": "0x42",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Credit Used; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5C",
-        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on BL",
+        "EventCode": "0x42",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Credit Used; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5C",
-        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; WB on BL",
+        "EventCode": "0x42",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Credit Used; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5C",
-        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; REQ on AD",
+        "EventCode": "0x45",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 No Credits; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5E",
-        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on AD",
+        "EventCode": "0x45",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 No Credits; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5E",
-        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; SNP on AD",
+        "EventCode": "0x45",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 No Credits; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5E",
-        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCB on BL",
+        "EventCode": "0x45",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 No Credits; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5E",
-        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCS on BL",
+        "EventCode": "0x45",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 No Credits; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5E",
-        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on BL",
+        "EventCode": "0x45",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 No Credits; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5E",
-        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; WB on BL",
+        "EventCode": "0x45",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Credit Used; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5D",
-        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; REQ on AD",
+        "EventCode": "0x46",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Credit Used; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5D",
-        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on AD",
+        "EventCode": "0x46",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Credit Used; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5D",
-        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; SNP on AD",
+        "EventCode": "0x46",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Credit Used; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5D",
-        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCB on BL",
+        "EventCode": "0x46",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Credit Used; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5D",
-        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCS on BL",
+        "EventCode": "0x46",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Credit Used; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5D",
-        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on BL",
+        "EventCode": "0x46",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 No Credits; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5F",
-        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; WB on BL",
+        "EventCode": "0x46",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 No Credits; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5F",
-        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP",
+        "BriefDescription": "VN0 message can't slot into flit; REQ on AD",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 No Credits; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5F",
-        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP",
+        "BriefDescription": "VN0 message can't slot into flit; RSP on AD",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 No Credits; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5F",
-        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB",
+        "BriefDescription": "VN0 message can't slot into flit; SNP on AD",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 No Credits; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5F",
-        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB",
+        "BriefDescription": "VN0 message can't slot into flit; NCB on BL",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 No Credits; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5F",
-        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS",
+        "BriefDescription": "VN0 message can't slot into flit; NCS on BL",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Number of Snoop Targets; CHA on VN0",
-        "EventCode": "0x3C",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_CHA",
+        "BriefDescription": "VN0 message can't slot into flit; RSP on BL",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Number of Snoop Targets; CHA on VN1",
-        "EventCode": "0x3C",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_CHA",
+        "BriefDescription": "VN0 message can't slot into flit; WB on BL",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN0",
-        "EventCode": "0x3C",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_NON_IDLE",
+        "BriefDescription": "VN1 message can't slot into flit; REQ on AD",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN1",
-        "EventCode": "0x3C",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_NON_IDLE",
+        "BriefDescription": "VN1 message can't slot into flit; RSP on AD",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Snoop Arbitration; FlowQ Won",
-        "Counter": "0,1,2",
-        "EventCode": "0x3D",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_NONSNP",
+        "BriefDescription": "VN1 message can't slot into flit; SNP on AD",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Snoop Arbitration; FlowQ Won",
-        "Counter": "0,1,2",
-        "EventCode": "0x3D",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_NONSNP",
+        "BriefDescription": "VN1 message can't slot into flit; NCB on BL",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won",
-        "Counter": "0,1,2",
-        "EventCode": "0x3D",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_VN2SNP",
+        "BriefDescription": "VN1 message can't slot into flit; NCS on BL",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won",
-        "Counter": "0,1,2",
-        "EventCode": "0x3D",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_VN0SNP",
+        "BriefDescription": "VN1 message can't slot into flit; RSP on BL",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x80",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR0",
+        "BriefDescription": "VN1 message can't slot into flit; WB on BL",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x80",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR1",
+        "BriefDescription": "SMI3 Prefetch Messages; Lost Arbitration",
+        "EventCode": "0x62",
+        "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARB_LOST",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2",
-        "EventCode": "0x80",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR2",
+        "BriefDescription": "SMI3 Prefetch Messages; Arrived",
+        "EventCode": "0x62",
+        "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARRIVED",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2",
-        "EventCode": "0x80",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR3",
+        "BriefDescription": "SMI3 Prefetch Messages; Dropped - Old",
+        "EventCode": "0x62",
+        "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_OLD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2",
-        "EventCode": "0x80",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR4",
+        "BriefDescription": "SMI3 Prefetch Messages; Dropped - Wrap",
+        "EventCode": "0x62",
+        "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_WRAP",
         "PerPkg": "1",
+        "PublicDescription": "Dropped because it was overwritten by new message while prefetch queue was full",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2",
-        "EventCode": "0x80",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR5",
+        "BriefDescription": "SMI3 Prefetch Messages; Slotted",
+        "EventCode": "0x62",
+        "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.SLOTTED",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x82",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR0",
+        "BriefDescription": "Remote VNA Credits; Any In Use",
+        "EventCode": "0x5B",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "At least one remote vna credit is in use",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x82",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "Remote VNA Credits; Corrected",
+        "EventCode": "0x5B",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of remote vna credits corrected (local return) per cycle",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
-        "Counter": "0,1,2",
-        "EventCode": "0x82",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "Remote VNA Credits; Level < 1",
+        "EventCode": "0x5B",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Remote vna credit level is less than 1 (i.e. no vna credits available)",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
-        "Counter": "0,1,2",
-        "EventCode": "0x82",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "Remote VNA Credits; Level < 4",
+        "EventCode": "0x5B",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
-        "Counter": "0,1,2",
-        "EventCode": "0x82",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "Remote VNA Credits; Level < 5",
+        "EventCode": "0x5B",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5",
         "PerPkg": "1",
+        "PublicDescription": "Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
-        "Counter": "0,1,2",
-        "EventCode": "0x82",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR5",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
-    },
-    {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x88",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR0",
+        "BriefDescription": "Remote VNA Credits; Used",
+        "EventCode": "0x5B",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD.USED",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of remote vna credits consumed per cycle",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x88",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR1",
+        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2",
-        "EventCode": "0x88",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR2",
+        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2",
-        "EventCode": "0x88",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR3",
+        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2",
-        "EventCode": "0x88",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR4",
+        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2",
-        "EventCode": "0x88",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR5",
+        "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M3UPI_RxR_BYPASS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR0",
+        "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M3UPI_RxR_BYPASS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
-        "Counter": "0,1,2",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M3UPI_RxR_BYPASS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
-        "Counter": "0,1,2",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
-        "Counter": "0,1,2",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M3UPI_RxR_BYPASS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
-        "Counter": "0,1,2",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR5",
+        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x84",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR0",
+        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x84",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR1",
+        "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2",
-        "EventCode": "0x84",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR2",
+        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2",
-        "EventCode": "0x84",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR3",
+        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2",
-        "EventCode": "0x84",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR4",
+        "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2",
-        "EventCode": "0x84",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR5",
+        "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x86",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR0",
+        "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M3UPI_RxR_INSERTS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x86",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
-        "Counter": "0,1,2",
-        "EventCode": "0x86",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M3UPI_RxR_INSERTS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
-        "Counter": "0,1,2",
-        "EventCode": "0x86",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M3UPI_RxR_INSERTS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
-        "Counter": "0,1,2",
-        "EventCode": "0x86",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
-        "Counter": "0,1,2",
-        "EventCode": "0x86",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR5",
+        "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M3UPI_RxR_INSERTS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR0",
+        "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
         "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR5",
+        "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR0",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR1",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR2",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR3",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR4",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR5",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Clockticks",
-        "Counter": "0,1,2",
-        "EventCode": "0xC0",
-        "EventName": "UNC_M3UPI_CMS_CLOCKTICKS",
-        "PerPkg": "1",
-        "Unit": "M3UPI"
-    },
-    {
-        "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
-        "Counter": "0,1,2",
-        "EventCode": "0xAE",
-        "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
-        "Counter": "0,1,2",
-        "EventCode": "0xAE",
-        "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xA9",
-        "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xA9",
-        "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xA9",
-        "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xA9",
-        "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use; Left",
-        "Counter": "0,1,2",
-        "EventCode": "0xAD",
-        "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use; Right",
-        "Counter": "0,1,2",
-        "EventCode": "0xAD",
-        "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
-        "Counter": "0,1,2",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
-        "Counter": "0,1,2",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
-        "Counter": "0,1,2",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL",
+        "BriefDescription": "Failed ARB for AD; VN0 REQ Messages",
+        "EventCode": "0x30",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "AD arb but no win; arb request asserted but not won",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
-        "Counter": "0,1,2",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV",
+        "BriefDescription": "Failed ARB for AD; VN0 RSP Messages",
+        "EventCode": "0x30",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "AD arb but no win; arb request asserted but not won",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
-        "Counter": "0,1,2",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD",
+        "BriefDescription": "Failed ARB for AD; VN0 SNP Messages",
+        "EventCode": "0x30",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "AD arb but no win; arb request asserted but not won",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
-        "Counter": "0,1,2",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK",
+        "BriefDescription": "Failed ARB for AD; VN0 WB Messages",
+        "EventCode": "0x30",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "AD arb but no win; arb request asserted but not won",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
-        "Counter": "0,1,2",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL",
+        "BriefDescription": "Failed ARB for AD; VN1 REQ Messages",
+        "EventCode": "0x30",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "AD arb but no win; arb request asserted but not won",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache",
-        "Counter": "0,1,2",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV",
+        "BriefDescription": "Failed ARB for AD; VN1 RSP Messages",
+        "EventCode": "0x30",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "AD arb but no win; arb request asserted but not won",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
-        "Counter": "0,1,2",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD",
+        "BriefDescription": "Failed ARB for AD; VN1 SNP Messages",
+        "EventCode": "0x30",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "AD arb but no win; arb request asserted but not won",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
-        "Counter": "0,1,2",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK",
+        "BriefDescription": "Failed ARB for AD; VN1 WB Messages",
+        "EventCode": "0x30",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "AD arb but no win; arb request asserted but not won",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
-        "Counter": "0,1,2",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL",
+        "BriefDescription": "AD FlowQ Bypass",
+        "EventCode": "0x2C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
-        "Counter": "0,1,2",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV",
+        "BriefDescription": "AD FlowQ Bypass",
+        "EventCode": "0x2C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1",
+        "BriefDescription": "AD FlowQ Bypass",
+        "EventCode": "0x2C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; AD",
-        "Counter": "0,1,2",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD",
+        "BriefDescription": "AD FlowQ Bypass",
+        "EventCode": "0x2C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
-        "Counter": "0,1,2",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK",
+        "BriefDescription": "AD Flow Q Not Empty; VN0 REQ Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
-        "Counter": "0,1,2",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL",
+        "BriefDescription": "AD Flow Q Not Empty; VN0 RSP Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache",
-        "Counter": "0,1,2",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV",
+        "BriefDescription": "AD Flow Q Not Empty; VN0 SNP Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Source Throttle",
-        "Counter": "0,1,2",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M3UPI_RING_SRC_THRTL",
+        "BriefDescription": "AD Flow Q Not Empty; VN0 WB Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN0; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ",
+        "BriefDescription": "AD Flow Q Not Empty; VN1 REQ Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN0; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP",
+        "BriefDescription": "AD Flow Q Not Empty; VN1 RSP Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN0; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP",
+        "BriefDescription": "AD Flow Q Not Empty; VN1 SNP Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN0; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP",
+        "BriefDescription": "AD Flow Q Not Empty; VN1 WB Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN0; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB",
+        "BriefDescription": "AD Flow Q Inserts; VN0 REQ Messages",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN0; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB",
+        "BriefDescription": "AD Flow Q Inserts; VN0 RSP Messages",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN0; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS",
+        "BriefDescription": "AD Flow Q Inserts; VN0 SNP Messages",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN1; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ",
+        "BriefDescription": "AD Flow Q Inserts; VN0 WB Messages",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN1; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP",
+        "BriefDescription": "AD Flow Q Inserts; VN1 REQ Messages",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN1; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP",
+        "BriefDescription": "AD Flow Q Inserts; VN1 RSP Messages",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN1; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP",
+        "BriefDescription": "AD Flow Q Inserts; VN1 SNP Messages",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN1; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB",
+        "BriefDescription": "AD Flow Q Occupancy; VN0 REQ Messages",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN1; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB",
+        "BriefDescription": "AD Flow Q Occupancy; VN0 RSP Messages",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN1; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS",
+        "BriefDescription": "AD Flow Q Occupancy; VN0 SNP Messages",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN0",
-        "Counter": "0,1,2",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN0",
+        "BriefDescription": "AD Flow Q Occupancy; VN0 WB Messages",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN1",
-        "Counter": "0,1,2",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN1",
+        "BriefDescription": "AD Flow Q Occupancy; VN1 REQ Messages",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN0",
-        "Counter": "0,1,2",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0",
+        "BriefDescription": "AD Flow Q Occupancy; VN1 RSP Messages",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN1",
-        "Counter": "0,1,2",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1",
+        "BriefDescription": "AD Flow Q Occupancy; VN1 SNP Messages",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN0",
-        "Counter": "0,1,2",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0",
+        "BriefDescription": "Number of Snoop Targets; CHA on VN0",
+        "EventCode": "0x3C",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_CHA",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to CHA",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN1",
-        "Counter": "0,1,2",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1",
+        "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN0",
+        "EventCode": "0x3C",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_NON_IDLE",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of non-idle cycles in issuing Vn0 Snpf",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Arb Miscellaneous; AD, BL Parallel Win",
-        "Counter": "0,1,2",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN",
+        "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN0",
+        "EventCode": "0x3C",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to peer UPI0",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN0; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x49",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_REQ",
+        "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN0",
+        "EventCode": "0x3C",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to peer UPI1",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN0; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x49",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_SNP",
+        "BriefDescription": "Number of Snoop Targets; CHA on VN1",
+        "EventCode": "0x3C",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_CHA",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to CHA",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN0; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x49",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_RSP",
+        "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN1",
+        "EventCode": "0x3C",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_NON_IDLE",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of non-idle cycles in issuing Vn1 Snpf",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN0; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x49",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_RSP",
+        "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN1",
+        "EventCode": "0x3C",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to peer UPI0",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN0; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x49",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_WB",
+        "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN1",
+        "EventCode": "0x3C",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI1",
         "PerPkg": "1",
+        "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to peer UPI1",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN0; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x49",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCB",
+        "BriefDescription": "Snoop Arbitration; FlowQ Won",
+        "EventCode": "0x3D",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_NONSNP",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn0",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN0; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x49",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCS",
+        "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won",
+        "EventCode": "0x3D",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_VN2SNP",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ Vn0 SnpF issued when SnpF pending on Vn1",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN1; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_REQ",
+        "BriefDescription": "Snoop Arbitration; FlowQ Won",
+        "EventCode": "0x3D",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_NONSNP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn1",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN1; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_SNP",
+        "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won",
+        "EventCode": "0x3D",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_VN0SNP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ Vn1 SnpF issued when SnpF pending on Vn0",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN1; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_RSP",
+        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN0 REQ Messages",
+        "EventCode": "0x34",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_REQ",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN1; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_RSP",
+        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN0 SNP Messages",
+        "EventCode": "0x34",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_SNP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN1; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_WB",
+        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN0 WB Messages",
+        "EventCode": "0x34",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN1; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCB",
+        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN1 REQ Messages",
+        "EventCode": "0x34",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_REQ",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN1; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCS",
+        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN1 SNP Messages",
+        "EventCode": "0x34",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_SNP",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN0; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x47",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_REQ",
+        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN1 WB Messages",
+        "EventCode": "0x34",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_WB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN0; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x47",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_SNP",
+        "BriefDescription": "Speculative ARB for AD  - New Message; VN0 REQ Messages",
+        "EventCode": "0x33",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_REQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN0; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x47",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_RSP",
+        "BriefDescription": "Speculative ARB for AD  - New Message; VN0 SNP Messages",
+        "EventCode": "0x33",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_SNP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN0; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x47",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_RSP",
+        "BriefDescription": "Speculative ARB for AD  - New Message; VN0 WB Messages",
+        "EventCode": "0x33",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN0; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x47",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_WB",
+        "BriefDescription": "Speculative ARB for AD  - New Message; VN1 REQ Messages",
+        "EventCode": "0x33",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_REQ",
         "PerPkg": "1",
+        "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN0; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x47",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCB",
+        "BriefDescription": "Speculative ARB for AD  - New Message; VN1 SNP Messages",
+        "EventCode": "0x33",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_SNP",
         "PerPkg": "1",
+        "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN0; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x47",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCS",
+        "BriefDescription": "Speculative ARB for AD  - New Message; VN1 WB Messages",
+        "EventCode": "0x33",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_WB",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN1; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x48",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_REQ",
+        "BriefDescription": "Speculative ARB for AD  - No Credit; VN0 REQ Messages",
+        "EventCode": "0x32",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_REQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN1; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x48",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_SNP",
+        "BriefDescription": "Speculative ARB for AD  - No Credit; VN0 RSP Messages",
+        "EventCode": "0x32",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN1; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x48",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_RSP",
+        "BriefDescription": "Speculative ARB for AD  - No Credit; VN0 SNP Messages",
+        "EventCode": "0x32",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_SNP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN1; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x48",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_RSP",
+        "BriefDescription": "Speculative ARB for AD  - No Credit; VN0 WB Messages",
+        "EventCode": "0x32",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN1; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x48",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_WB",
+        "BriefDescription": "Speculative ARB for AD  - No Credit; VN1 REQ Messages",
+        "EventCode": "0x32",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_REQ",
         "PerPkg": "1",
+        "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN1; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x48",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCB",
+        "BriefDescription": "Speculative ARB for AD  - No Credit; VN1 RSP Messages",
+        "EventCode": "0x32",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_RSP",
+        "PerPkg": "1",
+        "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "Speculative ARB for AD  - No Credit; VN1 SNP Messages",
+        "EventCode": "0x32",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_SNP",
         "PerPkg": "1",
+        "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN1; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x48",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCS",
+        "BriefDescription": "Speculative ARB for AD  - No Credit; VN1 WB Messages",
+        "EventCode": "0x32",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_WB",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on Idle",
-        "Counter": "0,1,2",
-        "EventCode": "0x40",
-        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE",
+        "BriefDescription": "AK Flow Q Inserts",
+        "EventCode": "0x2F",
+        "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x01",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on BL Arb",
-        "Counter": "0,1,2",
-        "EventCode": "0x40",
-        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB",
+        "BriefDescription": "AK Flow Q Occupancy",
+        "EventCode": "0x1E",
+        "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x02",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x40",
-        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT",
+        "BriefDescription": "Failed ARB for BL; VN0 NCB Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "BL arb but no win; arb request asserted but not won",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 2",
-        "Counter": "0,1,2",
-        "EventCode": "0x40",
-        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT",
+        "BriefDescription": "Failed ARB for BL; VN0 NCS Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "BL arb but no win; arb request asserted but not won",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message lost contest for flit; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x50",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_REQ",
+        "BriefDescription": "Failed ARB for BL; VN0 RSP Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "BL arb but no win; arb request asserted but not won",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message lost contest for flit; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x50",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_SNP",
+        "BriefDescription": "Failed ARB for BL; VN0 WB Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "BL arb but no win; arb request asserted but not won",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message lost contest for flit; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x50",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_RSP",
+        "BriefDescription": "Failed ARB for BL; VN1 NCS Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "BL arb but no win; arb request asserted but not won",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message lost contest for flit; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x50",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_RSP",
+        "BriefDescription": "Failed ARB for BL; VN1 NCB Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "BL arb but no win; arb request asserted but not won",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message lost contest for flit; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x50",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_WB",
+        "BriefDescription": "Failed ARB for BL; VN1 RSP Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP",
         "PerPkg": "1",
+        "PublicDescription": "BL arb but no win; arb request asserted but not won",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message lost contest for flit; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x50",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCB",
+        "BriefDescription": "Failed ARB for BL; VN1 WB Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB",
         "PerPkg": "1",
+        "PublicDescription": "BL arb but no win; arb request asserted but not won",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message lost contest for flit; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x50",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCS",
+        "BriefDescription": "BL Flow Q Not Empty; VN0 REQ Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message lost contest for flit; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x51",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_REQ",
+        "BriefDescription": "BL Flow Q Not Empty; VN0 RSP Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message lost contest for flit; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x51",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_SNP",
+        "BriefDescription": "BL Flow Q Not Empty; VN0 SNP Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message lost contest for flit; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x51",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_RSP",
+        "BriefDescription": "BL Flow Q Not Empty; VN0 WB Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message lost contest for flit; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x51",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_RSP",
+        "BriefDescription": "BL Flow Q Not Empty; VN1 REQ Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message lost contest for flit; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x51",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_WB",
+        "BriefDescription": "BL Flow Q Not Empty; VN1 RSP Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message lost contest for flit; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x51",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCB",
+        "BriefDescription": "BL Flow Q Not Empty; VN1 SNP Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message lost contest for flit; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x51",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCS",
+        "BriefDescription": "BL Flow Q Not Empty; VN1 WB Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Miscellaneous Credit Events; Any In BGF FIFO",
-        "Counter": "0,1,2",
-        "EventCode": "0x60",
-        "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO",
+        "BriefDescription": "BL Flow Q Inserts; VN0 RSP Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Miscellaneous Credit Events; Any in BGF Path",
-        "Counter": "0,1,2",
-        "EventCode": "0x60",
-        "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH",
+        "BriefDescription": "BL Flow Q Inserts; VN0 WB Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Miscellaneous Credit Events; No D2K For Arb",
-        "Counter": "0,1,2",
-        "EventCode": "0x60",
-        "EventName": "UNC_M3UPI_RxC_CRD_MISC.NO_D2K_FOR_ARB",
+        "BriefDescription": "BL Flow Q Inserts; VN0 NCS Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Credit Occupancy; VNA In Use",
-        "Counter": "0,1,2",
-        "EventCode": "0x61",
-        "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE",
+        "BriefDescription": "BL Flow Q Inserts; VN0 NCB Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Credit Occupancy; Packets in BGF FIFO",
-        "Counter": "0,1,2",
-        "EventCode": "0x61",
-        "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO",
+        "BriefDescription": "BL Flow Q Inserts; VN1 RSP Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Credit Occupancy; Packets in BGF Path",
-        "Counter": "0,1,2",
-        "EventCode": "0x61",
-        "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH",
+        "BriefDescription": "BL Flow Q Inserts; VN1 WB Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Credit Occupancy; Transmit Credits",
-        "Counter": "0,1,2",
-        "EventCode": "0x61",
-        "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD",
+        "BriefDescription": "BL Flow Q Inserts; VN1_NCB Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Credit Occupancy; D2K Credits",
-        "Counter": "0,1,2",
-        "EventCode": "0x61",
-        "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD",
+        "BriefDescription": "BL Flow Q Inserts; VN1_NCS Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Credit Occupancy",
-        "Counter": "0,1,2",
-        "EventCode": "0x61",
-        "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL",
+        "BriefDescription": "BL Flow Q Occupancy; VN0 NCB Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Credit Occupancy",
-        "Counter": "0,1,2",
-        "EventCode": "0x61",
-        "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO",
+        "BriefDescription": "BL Flow Q Occupancy; VN0 NCS Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x43",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ",
+        "BriefDescription": "BL Flow Q Occupancy; VN0 RSP Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x43",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP",
+        "BriefDescription": "BL Flow Q Occupancy; VN0 WB Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x43",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP",
+        "BriefDescription": "BL Flow Q Occupancy; VN1_NCS Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x43",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP",
+        "BriefDescription": "BL Flow Q Occupancy; VN1_NCB Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x43",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB",
+        "BriefDescription": "BL Flow Q Occupancy; VN1 RSP Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x43",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB",
+        "BriefDescription": "BL Flow Q Occupancy; VN1 WB Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB",
         "PerPkg": "1",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x43",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS",
+        "BriefDescription": "Speculative ARB for BL  - New Message; VN0 WB Messages",
+        "EventCode": "0x38",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCB",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x44",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ",
+        "BriefDescription": "Speculative ARB for BL  - New Message; VN0 NCS Messages",
+        "EventCode": "0x38",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x44",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP",
+        "BriefDescription": "Speculative ARB for BL  - New Message; VN0 WB Messages",
+        "EventCode": "0x38",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x44",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP",
+        "BriefDescription": "Speculative ARB for BL  - New Message; VN1 WB Messages",
+        "EventCode": "0x38",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x44",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP",
+        "BriefDescription": "Speculative ARB for BL  - New Message; VN1 NCB Messages",
+        "EventCode": "0x38",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x44",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB",
+        "BriefDescription": "Speculative ARB for BL  - New Message; VN1 RSP Messages",
+        "EventCode": "0x38",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_WB",
         "PerPkg": "1",
+        "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x44",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB",
+        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCB Messages",
+        "EventCode": "0x37",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCB",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x44",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS",
+        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCS Messages",
+        "EventCode": "0x37",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Data Flit Not Sent; All",
-        "Counter": "0,1,2",
-        "EventCode": "0x57",
-        "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.ALL",
+        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 RSP Messages",
+        "EventCode": "0x37",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Data Flit Not Sent; No BGF Credits",
-        "Counter": "0,1,2",
-        "EventCode": "0x57",
-        "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_BGF",
+        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 WB Messages",
+        "EventCode": "0x37",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Data Flit Not Sent; No TxQ Credits",
-        "Counter": "0,1,2",
-        "EventCode": "0x57",
-        "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_TXQ",
+        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCS Messages",
+        "EventCode": "0x37",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x59",
-        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT",
+        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCB Messages",
+        "EventCode": "0x37",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x59",
-        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT",
+        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 RSP Messages",
+        "EventCode": "0x37",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Generating BL Data Flit Sequence",
-        "Counter": "0,1,2",
-        "EventCode": "0x59",
-        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO",
+        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 WB Messages",
+        "EventCode": "0x37",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_WB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Generating BL Data Flit Sequence",
-        "Counter": "0,1,2",
-        "EventCode": "0x59",
-        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY",
+        "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Generating BL Data Flit Sequence",
-        "Counter": "0,1,2",
-        "EventCode": "0x59",
-        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT",
+        "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Generating BL Data Flit Sequence",
-        "Counter": "0,1,2",
-        "EventCode": "0x59",
-        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0",
+        "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Generating BL Data Flit Sequence",
-        "Counter": "0,1,2",
-        "EventCode": "0x59",
-        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL",
+        "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC",
-        "Counter": "0,1,2",
-        "EventCode": "0x5A",
-        "EventName": "UNC_M3UPI_RxC_FLITS_MISC",
+        "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sent Header Flit; One Message",
-        "Counter": "0,1,2",
-        "EventCode": "0x56",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG",
+        "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sent Header Flit; Two Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x56",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.2_MSGS",
+        "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sent Header Flit; Three Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x56",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.3_MSGS",
+        "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sent Header Flit; One Message in non-VNA",
-        "Counter": "0,1,2",
-        "EventCode": "0x56",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG_VNX",
+        "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Slotting BL Message Into Header Flit; All",
-        "Counter": "0,1,2",
-        "EventCode": "0x58",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL",
+        "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Slotting BL Message Into Header Flit; Needs Data Flit",
-        "Counter": "0,1,2",
-        "EventCode": "0x58",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA",
+        "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x58",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce",
+        "EventCode": "0x96",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x58",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit",
+        "EventCode": "0x96",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x58",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce",
+        "EventCode": "0x96",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Bubble",
-        "Counter": "0,1,2",
-        "EventCode": "0x58",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce",
+        "EventCode": "0x96",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Not Avail",
-        "Counter": "0,1,2",
-        "EventCode": "0x58",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit",
+        "EventCode": "0x96",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1; Acumullate",
-        "Counter": "0,1,2",
-        "EventCode": "0x53",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce",
+        "EventCode": "0x96",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1; Accumulate Ready",
-        "Counter": "0,1,2",
-        "EventCode": "0x53",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce",
+        "EventCode": "0x97",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1; Accumulate Wasted",
-        "Counter": "0,1,2",
-        "EventCode": "0x53",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit",
+        "EventCode": "0x97",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Blocked",
-        "Counter": "0,1,2",
-        "EventCode": "0x53",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce",
+        "EventCode": "0x97",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Message",
-        "Counter": "0,1,2",
-        "EventCode": "0x53",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce",
+        "EventCode": "0x97",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1; Parallel Ok",
-        "Counter": "0,1,2",
-        "EventCode": "0x53",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit",
+        "EventCode": "0x97",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1; Parallel Message",
-        "Counter": "0,1,2",
-        "EventCode": "0x53",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_MSG",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce",
+        "EventCode": "0x97",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1; Parallel Flit Finished",
-        "Counter": "0,1,2",
-        "EventCode": "0x53",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_FLIT",
+        "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce",
+        "EventCode": "0x95",
+        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall",
-        "Counter": "0,1,2",
-        "EventCode": "0x54",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL",
+        "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit",
+        "EventCode": "0x95",
+        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall - No Message",
-        "Counter": "0,1,2",
-        "EventCode": "0x54",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG",
+        "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce",
+        "EventCode": "0x95",
+        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Header Not Sent; All",
-        "Counter": "0,1,2",
-        "EventCode": "0x55",
-        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ALL",
+        "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce",
+        "EventCode": "0x95",
+        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Header Not Sent; No BGF Credits",
-        "Counter": "0,1,2",
-        "EventCode": "0x55",
-        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_CRD",
+        "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit",
+        "EventCode": "0x95",
+        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Header Not Sent; No TxQ Credits",
-        "Counter": "0,1,2",
-        "EventCode": "0x55",
-        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_CRD",
+        "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce",
+        "EventCode": "0x95",
+        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Header Not Sent; No BGF Credits + No Extra Message Slotted",
-        "Counter": "0,1,2",
-        "EventCode": "0x55",
-        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_NO_MSG",
+        "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce",
+        "EventCode": "0x99",
+        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Header Not Sent; No TxQ Credits + No Extra Message Slotted",
-        "Counter": "0,1,2",
-        "EventCode": "0x55",
-        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_NO_MSG",
+        "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit",
+        "EventCode": "0x99",
+        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Header Not Sent; Sent - One Slot Taken",
-        "Counter": "0,1,2",
-        "EventCode": "0x55",
-        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ONE_TAKEN",
+        "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce",
+        "EventCode": "0x99",
+        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Header Not Sent; Sent - Two Slots Taken",
-        "Counter": "0,1,2",
-        "EventCode": "0x55",
-        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.TWO_TAKEN",
+        "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce",
+        "EventCode": "0x99",
+        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Header Not Sent; Sent - Three Slots Taken",
-        "Counter": "0,1,2",
-        "EventCode": "0x55",
-        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.THREE_TAKEN",
+        "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit",
+        "EventCode": "0x99",
+        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Message Held; VN0",
-        "Counter": "0,1,2",
-        "EventCode": "0x52",
-        "EventName": "UNC_M3UPI_RxC_HELD.VN0",
+        "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce",
+        "EventCode": "0x99",
+        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Message Held; VN1",
-        "Counter": "0,1,2",
-        "EventCode": "0x52",
-        "EventName": "UNC_M3UPI_RxC_HELD.VN1",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce",
+        "EventCode": "0x94",
+        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Message Held; Parallel Attempt",
-        "Counter": "0,1,2",
-        "EventCode": "0x52",
-        "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit",
+        "EventCode": "0x94",
+        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Message Held; Parallel Success",
-        "Counter": "0,1,2",
-        "EventCode": "0x52",
-        "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce",
+        "EventCode": "0x94",
+        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Message Held; Parallel AD Lost",
-        "Counter": "0,1,2",
-        "EventCode": "0x52",
-        "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_AD_LOST",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce",
+        "EventCode": "0x94",
+        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Message Held; Parallel BL Lost",
-        "Counter": "0,1,2",
-        "EventCode": "0x52",
-        "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_BL_LOST",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit",
+        "EventCode": "0x94",
+        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Message Held; Can't Slot AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x52",
-        "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce",
+        "EventCode": "0x94",
+        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Message Held; Can't Slot BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x52",
-        "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x41",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x41",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x41",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x41",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP",
+        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x41",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB",
+        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x41",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB",
+        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x41",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS",
+        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x42",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ",
+        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x42",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP",
+        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x42",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP",
+        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x42",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP",
+        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x42",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB",
+        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x42",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB",
+        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x42",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS",
+        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x45",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ",
+        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x45",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP",
+        "BriefDescription": "CMS Vertical ADS Used; IV",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x45",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x45",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x45",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x45",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x45",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x46",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x46",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV",
+        "EventCode": "0x92",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.IV",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x46",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0",
+        "EventCode": "0x93",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x46",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1",
+        "EventCode": "0x93",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x46",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0",
+        "EventCode": "0x93",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x46",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1",
+        "EventCode": "0x93",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x46",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0",
+        "EventCode": "0x93",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message can't slot into flit; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1",
+        "EventCode": "0x93",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message can't slot into flit; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV",
+        "EventCode": "0x93",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.IV",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message can't slot into flit; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP",
+        "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0",
+        "EventCode": "0x91",
+        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message can't slot into flit; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP",
+        "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1",
+        "EventCode": "0x91",
+        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message can't slot into flit; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB",
+        "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0",
+        "EventCode": "0x91",
+        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message can't slot into flit; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB",
+        "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1",
+        "EventCode": "0x91",
+        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message can't slot into flit; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS",
+        "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0",
+        "EventCode": "0x91",
+        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message can't slot into flit; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ",
+        "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1",
+        "EventCode": "0x91",
+        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message can't slot into flit; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP",
+        "BriefDescription": "CMS Vert Egress Allocations; IV",
+        "EventCode": "0x91",
+        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.IV",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message can't slot into flit; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP",
+        "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message can't slot into flit; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP",
+        "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message can't slot into flit; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB",
+        "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message can't slot into flit; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB",
+        "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message can't slot into flit; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS",
+        "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "SMI3 Prefetch Messages; Arrived",
-        "Counter": "0,1,2",
-        "EventCode": "0x62",
-        "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARRIVED",
+        "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "SMI3 Prefetch Messages; Lost Arbitration",
-        "Counter": "0,1,2",
-        "EventCode": "0x62",
-        "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARB_LOST",
+        "BriefDescription": "CMS Vertical Egress NACKs; IV",
+        "EventCode": "0x98",
+        "EventName": "UNC_M3UPI_TxR_VERT_NACK.IV",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "SMI3 Prefetch Messages; Slotted",
-        "Counter": "0,1,2",
-        "EventCode": "0x62",
-        "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.SLOTTED",
+        "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "SMI3 Prefetch Messages; Dropped - Old",
-        "Counter": "0,1,2",
-        "EventCode": "0x62",
-        "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_OLD",
+        "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "SMI3 Prefetch Messages; Dropped - Wrap",
-        "Counter": "0,1,2",
-        "EventCode": "0x62",
-        "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_WRAP",
+        "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Remote VNA Credits; Used",
-        "Counter": "0,1,2",
-        "EventCode": "0x5B",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD.USED",
+        "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Remote VNA Credits; Corrected",
-        "Counter": "0,1,2",
-        "EventCode": "0x5B",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED",
+        "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Remote VNA Credits; Level < 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x5B",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1",
+        "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Remote VNA Credits; Level < 4",
-        "Counter": "0,1,2",
-        "EventCode": "0x5B",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4",
+        "BriefDescription": "CMS Vert Egress Occupancy; IV",
+        "EventCode": "0x90",
+        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Remote VNA Credits; Level < 5",
-        "Counter": "0,1,2",
-        "EventCode": "0x5B",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Remote VNA Credits; Any In Use",
-        "Counter": "0,1,2",
-        "EventCode": "0x5B",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_BNC",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_BNC",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M3UPI_RxR_BYPASS.AD_BNC",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.IV",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M3UPI_RxR_BYPASS.AK_BNC",
+        "BriefDescription": "UPI0 AD Credits Empty; VN0 REQ Messages",
+        "EventCode": "0x20",
+        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M3UPI_RxR_BYPASS.BL_BNC",
+        "BriefDescription": "UPI0 AD Credits Empty; VN0 RSP Messages",
+        "EventCode": "0x20",
+        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M3UPI_RxR_BYPASS.IV_BNC",
+        "BriefDescription": "UPI0 AD Credits Empty; VN0 SNP Messages",
+        "EventCode": "0x20",
+        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD",
+        "BriefDescription": "UPI0 AD Credits Empty; VN1 REQ Messages",
+        "EventCode": "0x20",
+        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to UPIs on the AD Ring",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD",
+        "BriefDescription": "UPI0 AD Credits Empty; VN1 RSP Messages",
+        "EventCode": "0x20",
+        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to UPIs on the AD Ring",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_BNC",
+        "BriefDescription": "UPI0 AD Credits Empty; VN1 SNP Messages",
+        "EventCode": "0x20",
+        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK_BNC",
+        "BriefDescription": "UPI0 AD Credits Empty; VNA",
+        "EventCode": "0x20",
+        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_BNC",
+        "BriefDescription": "UPI0 BL Credits Empty; VN0 RSP Messages",
+        "EventCode": "0x21",
+        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV_BNC",
+        "BriefDescription": "UPI0 BL Credits Empty; VN0 REQ Messages",
+        "EventCode": "0x21",
+        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD",
+        "BriefDescription": "UPI0 BL Credits Empty; VN0 SNP Messages",
+        "EventCode": "0x21",
+        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD",
+        "BriefDescription": "UPI0 BL Credits Empty; VN1 RSP Messages",
+        "EventCode": "0x21",
+        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV",
+        "BriefDescription": "UPI0 BL Credits Empty; VN1 REQ Messages",
+        "EventCode": "0x21",
+        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M3UPI_RxR_INSERTS.AD_BNC",
+        "BriefDescription": "UPI0 BL Credits Empty; VN1 SNP Messages",
+        "EventCode": "0x21",
+        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M3UPI_RxR_INSERTS.AK_BNC",
+        "BriefDescription": "UPI0 BL Credits Empty; VNA",
+        "EventCode": "0x21",
+        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M3UPI_RxR_INSERTS.BL_BNC",
+        "BriefDescription": "Prefetches generated by the flow control queue of the M3UPI unit.",
+        "EventCode": "0x29",
+        "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Count cases where flow control queue that sits between the Intel Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller)",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M3UPI_RxR_INSERTS.IV_BNC",
+        "BriefDescription": "Vertical AD Ring In Use; Down and Even",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD",
+        "BriefDescription": "Vertical AD Ring In Use; Down and Odd",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD",
+        "BriefDescription": "Vertical AD Ring In Use; Up and Even",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_BNC",
+        "BriefDescription": "Vertical AD Ring In Use; Up and Odd",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK_BNC",
+        "BriefDescription": "Vertical AK Ring In Use; Down and Even",
+        "EventCode": "0xA8",
+        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_BNC",
+        "BriefDescription": "Vertical AK Ring In Use; Down and Odd",
+        "EventCode": "0xA8",
+        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV_BNC",
+        "BriefDescription": "Vertical AK Ring In Use; Up and Even",
+        "EventCode": "0xA8",
+        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "Vertical AK Ring In Use; Up and Odd",
+        "EventCode": "0xA8",
+        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD",
+        "BriefDescription": "Vertical BL Ring in Use; Down and Even",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD",
+        "BriefDescription": "Vertical BL Ring in Use; Down and Odd",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+        "BriefDescription": "Vertical BL Ring in Use; Up and Even",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+        "BriefDescription": "Vertical BL Ring in Use; Up and Odd",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+        "BriefDescription": "Vertical IV Ring in Use; Down",
+        "EventCode": "0xAC",
+        "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+        "BriefDescription": "Vertical IV Ring in Use; Up",
+        "EventCode": "0xAC",
+        "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+        "BriefDescription": "VN0 Credit Used; WB on BL",
+        "EventCode": "0x5C",
+        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+        "BriefDescription": "VN0 Credit Used; NCB on BL",
+        "EventCode": "0x5C",
+        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+        "BriefDescription": "VN0 Credit Used; REQ on AD",
+        "EventCode": "0x5C",
+        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+        "BriefDescription": "VN0 Credit Used; RSP on AD",
+        "EventCode": "0x5C",
+        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+        "BriefDescription": "VN0 Credit Used; SNP on AD",
+        "EventCode": "0x5C",
+        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+        "BriefDescription": "VN0 Credit Used; RSP on BL",
+        "EventCode": "0x5C",
+        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+        "BriefDescription": "VN0 No Credits; WB on BL",
+        "EventCode": "0x5E",
+        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Number of Cycles there were no VN0 Credits; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+        "BriefDescription": "VN0 No Credits; NCB on BL",
+        "EventCode": "0x5E",
+        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Number of Cycles there were no VN0 Credits; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+        "BriefDescription": "VN0 No Credits; REQ on AD",
+        "EventCode": "0x5E",
+        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of Cycles there were no VN0 Credits; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+        "BriefDescription": "VN0 No Credits; RSP on AD",
+        "EventCode": "0x5E",
+        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of Cycles there were no VN0 Credits; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+        "BriefDescription": "VN0 No Credits; SNP on AD",
+        "EventCode": "0x5E",
+        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of Cycles there were no VN0 Credits; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+        "BriefDescription": "VN0 No Credits; RSP on BL",
+        "EventCode": "0x5E",
+        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of Cycles there were no VN0 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+        "BriefDescription": "VN1 Credit Used; WB on BL",
+        "EventCode": "0x5D",
+        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+        "BriefDescription": "VN1 Credit Used; NCB on BL",
+        "EventCode": "0x5D",
+        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+        "BriefDescription": "VN1 Credit Used; REQ on AD",
+        "EventCode": "0x5D",
+        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+        "BriefDescription": "VN1 Credit Used; RSP on AD",
+        "EventCode": "0x5D",
+        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+        "BriefDescription": "VN1 Credit Used; SNP on AD",
+        "EventCode": "0x5D",
+        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+        "BriefDescription": "VN1 Credit Used; RSP on BL",
+        "EventCode": "0x5D",
+        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+        "BriefDescription": "VN1 No Credits; WB on BL",
+        "EventCode": "0x5F",
+        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Number of Cycles there were no VN1 Credits; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+        "BriefDescription": "VN1 No Credits; NCB on BL",
+        "EventCode": "0x5F",
+        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Number of Cycles there were no VN1 Credits; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_BNC",
+        "BriefDescription": "VN1 No Credits; REQ on AD",
+        "EventCode": "0x5F",
+        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of Cycles there were no VN1 Credits; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AK_BNC",
+        "BriefDescription": "VN1 No Credits; RSP on AD",
+        "EventCode": "0x5F",
+        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of Cycles there were no VN1 Credits; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_BNC",
+        "BriefDescription": "VN1 No Credits; SNP on AD",
+        "EventCode": "0x5F",
+        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of Cycles there were no VN1 Credits; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD",
+        "BriefDescription": "VN1 No Credits; RSP on BL",
+        "EventCode": "0x5F",
+        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of Cycles there were no VN1 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_TxC_BL.DRS_UPI",
+        "Deprecated": "1",
+        "EventCode": "0x40",
+        "EventName": "UNC_NoUnit_TxC_BL.DRS_UPI",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x9F",
-        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_BNC",
+        "BriefDescription": "Clocks of the Intel Ultra Path Interconnect (UPI)",
+        "EventCode": "0x1",
+        "EventName": "UNC_UPI_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts clockticks of the fixed frequency clock controlling the Intel Ultra Path Interconnect (UPI).  This clock runs at1/8th the 'GT/s' speed of the UPI link.  For example, a  9.6GT/s  link will have a fixed Frequency of 1.2 Ghz.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x9F",
-        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK_BNC",
+        "BriefDescription": "Data Response packets that go direct to core",
+        "EventCode": "0x12",
+        "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to core bypassing the CHA.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x9F",
-        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_DIRECT_ATTEMPTS.D2U",
+        "Deprecated": "1",
+        "EventCode": "0x12",
+        "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x9F",
-        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV_BNC",
+        "BriefDescription": "Data Response packets that go direct to Intel UPI",
+        "EventCode": "0x12",
+        "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2U",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to Intel Ultra Path Interconnect (UPI) bypassing the CHA .",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x9F",
-        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD",
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
+    },
+    {
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
+    },
+    {
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "UPI LL"
+    },
+    {
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
         "PerPkg": "1",
         "UMask": "0x10",
-        "Unit": "M3UPI"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x9F",
-        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD",
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "UMask": "0x20",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x96",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_BNC",
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "UMask": "0x40",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x96",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK_BNC",
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "UMask": "0x80",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x96",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_BNC",
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x96",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV_BNC",
+        "BriefDescription": "Cycles Intel UPI is in L1 power mode (shutdown)",
+        "EventCode": "0x21",
+        "EventName": "UNC_UPI_L1_POWER_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts cycles when the Intel Ultra Path Interconnect (UPI) is in L1 power mode.  L1 is a mode that totally shuts down the UPI link.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdown.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x96",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD",
+        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
+        "EventCode": "0x14",
+        "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x96",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD",
+        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
+        "EventCode": "0x14",
+        "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x97",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_BNC",
+        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
+        "EventCode": "0x14",
+        "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x97",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK_BNC",
+        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
+        "EventCode": "0x14",
+        "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x97",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_BNC",
+        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
+        "EventCode": "0x14",
+        "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "UPI LL"
+    },
+    {
+        "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
+        "EventCode": "0x16",
+        "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x97",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV_BNC",
+        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
+        "EventCode": "0x15",
+        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "UMask": "0x20",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x97",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD",
+        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
+        "EventCode": "0x15",
+        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x97",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD",
+        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
+        "EventCode": "0x15",
+        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x95",
-        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_BNC",
+        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
+        "EventCode": "0x15",
+        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "UMask": "0x10",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x95",
-        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK_BNC",
+        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
+        "EventCode": "0x15",
+        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x95",
-        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_BNC",
+        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
+        "EventCode": "0x15",
+        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x95",
-        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV_BNC",
+        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
+        "EventCode": "0x15",
+        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "UMask": "0x40",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x95",
-        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD",
+        "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1",
+        "EventCode": "0x20",
+        "EventName": "UNC_UPI_PHY_INIT_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x95",
-        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD",
+        "BriefDescription": "L1 Req Nack",
+        "EventCode": "0x23",
+        "EventName": "UNC_UPI_POWER_L1_NACK",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts the number of times a link sends/receives a LinkReqNAck.  When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states.  This requests can either be accepted or denied.  If the Rx side replies with an Ack, the power mode will change.  If it replies with NAck, no change will take place.  This can be filtered based on Rx and Tx.  An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change).  A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x99",
-        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_BNC",
+        "BriefDescription": "L1 Req (same as L1 Ack).",
+        "EventCode": "0x22",
+        "EventName": "UNC_UPI_POWER_L1_REQ",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts the number of times a link sends/receives a LinkReqAck.  When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states.  This requests can either be accepted or denied.  If the Rx side replies with an Ack, the power mode will change.  If it replies with NAck, no change will take place.  This can be filtered based on Rx and Tx.  An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change).  A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x99",
-        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK_BNC",
+        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
+        "EventCode": "0x46",
+        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x99",
-        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_BNC",
+        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
+        "EventCode": "0x46",
+        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x99",
-        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV_BNC",
+        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
+        "EventCode": "0x46",
+        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x99",
-        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD",
+        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
+        "EventCode": "0x46",
+        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x99",
-        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD",
+        "BriefDescription": "Cycles the Rx of the Intel UPI is in L0p power mode",
+        "EventCode": "0x25",
+        "EventName": "UNC_UPI_RxL0P_POWER_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts cycles when the receive side (Rx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x94",
-        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_BNC",
+        "BriefDescription": "Cycles in L0. Receive side.",
+        "EventCode": "0x24",
+        "EventName": "UNC_UPI_RxL0_POWER_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Number of UPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x94",
-        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK_BNC",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - NCB",
+        "UMask": "0xe",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x94",
-        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_BNC",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - NCB",
+        "UMask": "0x10e",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x94",
-        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV_BNC",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - NCS",
+        "UMask": "0xf",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x94",
-        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - NCS",
+        "UMask": "0x10f",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x94",
-        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Request",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "REQ Message Class",
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x9B",
-        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_BNC",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Request Opcode",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match REQ Opcodes - Specified in Umask[7:4]",
+        "UMask": "0x108",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x9B",
-        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK_BNC",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Response - Conflict",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "UMask": "0x1aa",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x9B",
-        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_BNC",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Response - Invalid",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "UMask": "0x12a",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x9B",
-        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV_BNC",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class -WB",
+        "UMask": "0xc",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class -WB",
+        "UMask": "0x10c",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG0",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - RSP",
+        "UMask": "0xa",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - RSP",
+        "UMask": "0x10a",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Snoop",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "SNP Message Class",
+        "UMask": "0x9",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG1",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Snoop Opcode",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match SNP Opcodes - Specified in Umask[7:4]",
+        "UMask": "0x109",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Writeback",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class -WB",
+        "UMask": "0xd",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Writeback",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class -WB",
+        "UMask": "0x10d",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0",
+        "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
+        "EventCode": "0x31",
+        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0",
+        "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
+        "EventCode": "0x31",
+        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer  (Receive Queue) and passed directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; IV",
-        "Counter": "0,1,2",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV",
+        "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
+        "EventCode": "0x31",
+        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot2 RxQ buffer (Receive Queue)  and passed directly to the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1",
+        "BriefDescription": "VN0 Credit Consumed",
+        "EventCode": "0x39",
+        "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1",
+        "BriefDescription": "VN1 Credit Consumed",
+        "EventCode": "0x3A",
+        "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1",
+        "BriefDescription": "VNA Credit Consumed",
+        "EventCode": "0x38",
+        "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x92",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG0",
+        "BriefDescription": "Valid data FLITs received from any slot",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts valid data FLITs  (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.",
+        "UMask": "0xf",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x92",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG0",
+        "BriefDescription": "Null FLITs received from any slot",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.",
+        "UMask": "0x27",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x92",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG0",
+        "BriefDescription": "Valid Flits Received; Data",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.DATA",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV",
-        "Counter": "0,1,2",
-        "EventCode": "0x92",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.IV",
+        "BriefDescription": "Valid Flits Received; Idle",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.IDLE",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).",
+        "UMask": "0x47",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x92",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG1",
+        "BriefDescription": "Valid Flits Received; LLCRD Not Empty",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.LLCRD",
         "PerPkg": "1",
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
         "UMask": "0x10",
-        "Unit": "M3UPI"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x92",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG1",
+        "BriefDescription": "Valid Flits Received; LLCTRL",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.LLCTRL",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Equivalent to an idle packet.  Enables counting of slot 0 LLCTRL messages.",
+        "UMask": "0x40",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x92",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG1",
+        "BriefDescription": "Protocol header and credit FLITs received from any slot",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts protocol header and credit FLITs  (80 bit FLow control unITs) received from any of the 3 UPI slots on this UPI unit.",
+        "UMask": "0x97",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x93",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.ALL_NULL",
+        "Deprecated": "1",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.NULL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "UMask": "0x20",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x93",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG0",
+        "BriefDescription": "Valid Flits Received; Protocol Header",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.PROTHDR",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
+        "UMask": "0x80",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x93",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.PROTHDR",
+        "Deprecated": "1",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.PROT_HDR",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "UMask": "0x80",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV",
-        "Counter": "0,1,2",
-        "EventCode": "0x93",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.IV",
+        "BriefDescription": "Valid Flits Received; Slot 0",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.SLOT0",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 0 - Other mask bits determine types of headers to count.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x93",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG1",
+        "BriefDescription": "Valid Flits Received; Slot 1",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.SLOT1",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 1 - Other mask bits determine types of headers to count.",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x93",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG1",
+        "BriefDescription": "Valid Flits Received; Slot 2",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.SLOT2",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 2 - Other mask bits determine types of headers to count.",
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x93",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
+        "Deprecated": "1",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_HDR_MATCH.NCB",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "UMask": "0xc",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x91",
-        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
+        "Deprecated": "1",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_HDR_MATCH.NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "UMask": "0xd",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x91",
-        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
+        "Deprecated": "1",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_HDR_MATCH.REQ",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x91",
-        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
+        "Deprecated": "1",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_HDR_MATCH.RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "UMask": "0xa",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; IV",
-        "Counter": "0,1,2",
-        "EventCode": "0x91",
-        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.IV",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
+        "Deprecated": "1",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_HDR_MATCH.SNP",
+        "PerPkg": "1",
+        "UMask": "0x9",
+        "Unit": "UPI LL"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
+        "Deprecated": "1",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_HDR_MATCH.WB",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "UMask": "0xb",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x91",
-        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG1",
+        "BriefDescription": "RxQ Flit Buffer Allocations; Slot 0",
+        "EventCode": "0x30",
+        "EventName": "UNC_UPI_RxL_INSERTS.SLOT0",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x91",
-        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG1",
+        "BriefDescription": "RxQ Flit Buffer Allocations; Slot 1",
+        "EventCode": "0x30",
+        "EventName": "UNC_UPI_RxL_INSERTS.SLOT1",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x91",
-        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG1",
+        "BriefDescription": "RxQ Flit Buffer Allocations; Slot 2",
+        "EventCode": "0x30",
+        "EventName": "UNC_UPI_RxL_INSERTS.SLOT2",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x98",
-        "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG0",
+        "BriefDescription": "RxQ Occupancy - All Packets; Slot 0",
+        "EventCode": "0x32",
+        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x98",
-        "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG0",
+        "BriefDescription": "RxQ Occupancy - All Packets; Slot 1",
+        "EventCode": "0x32",
+        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x98",
-        "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG0",
+        "BriefDescription": "RxQ Occupancy - All Packets; Slot 2",
+        "EventCode": "0x32",
+        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x98",
-        "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG1",
+        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
+        "EventCode": "0x33",
+        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x98",
-        "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG1",
+        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
+        "EventCode": "0x33",
+        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x98",
-        "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG1",
+        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
+        "EventCode": "0x33",
+        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x90",
-        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG0",
+        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
+        "EventCode": "0x33",
+        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x90",
-        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG0",
+        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
+        "EventCode": "0x33",
+        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "UMask": "0x10",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x90",
-        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG0",
+        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
+        "EventCode": "0x33",
+        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "UMask": "0x20",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; IV",
-        "Counter": "0,1,2",
-        "EventCode": "0x90",
-        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.IV",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x90",
-        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG1",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "UMask": "0x40",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x90",
-        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG1",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
         "PerPkg": "1",
         "UMask": "0x20",
-        "Unit": "M3UPI"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x90",
-        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG1",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG0",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG0",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG0",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "UMask": "0x80",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG1",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
         "PerPkg": "1",
         "UMask": "0x10",
-        "Unit": "M3UPI"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG1",
+        "BriefDescription": "Cycles in which the Tx of the Intel Ultra Path Interconnect (UPI) is in L0p power mode",
+        "EventCode": "0x27",
+        "EventName": "UNC_UPI_TxL0P_POWER_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts cycles when the transmit side (Tx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG1",
+        "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
+        "EventCode": "0x28",
+        "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use; Up and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN",
+        "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
+        "EventCode": "0x29",
+        "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use; Up and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD",
+        "BriefDescription": "Cycles in L0. Transmit side.",
+        "EventCode": "0x26",
+        "EventName": "UNC_UPI_TxL0_POWER_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Number of UPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use; Down and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - NCB",
+        "UMask": "0xe",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use; Down and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - NCB",
+        "UMask": "0x10e",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use; Up and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xA8",
-        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - NCS",
+        "UMask": "0xf",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use; Up and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xA8",
-        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - NCS",
+        "UMask": "0x10f",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use; Down and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xA8",
-        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Request",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "REQ Message Class",
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use; Down and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xA8",
-        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Request Opcode",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match REQ Opcodes - Specified in Umask[7:4]",
+        "UMask": "0x108",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use; Up and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xAA",
-        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Conflict",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "UMask": "0x1aa",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use; Up and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xAA",
-        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Invalid",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "UMask": "0x12a",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use; Down and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xAA",
-        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class -WB",
+        "UMask": "0xc",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use; Down and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xAA",
-        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class -WB",
+        "UMask": "0x10c",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical IV Ring in Use; Up",
-        "Counter": "0,1,2",
-        "EventCode": "0xAC",
-        "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - RSP",
+        "UMask": "0xa",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical IV Ring in Use; Down",
-        "Counter": "0,1,2",
-        "EventCode": "0xAC",
-        "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - RSP",
+        "UMask": "0x10a",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "D2C Sent",
-        "Counter": "0,1,2",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M3UPI_D2C_SENT",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
         "PerPkg": "1",
-        "Unit": "M3UPI"
+        "PublicDescription": "SNP Message Class",
+        "UMask": "0x9",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "FaST wire asserted; Vertical",
-        "Counter": "0,1,2",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M3UPI_FAST_ASSERTED.VERT",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop Opcode",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match SNP Opcodes - Specified in Umask[7:4]",
+        "UMask": "0x109",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "FaST wire asserted; Horizontal",
-        "Counter": "0,1,2",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M3UPI_FAST_ASSERTED.HORZ",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class -WB",
+        "UMask": "0xd",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Sent Header Flit",
-        "Counter": "0,1,2",
-        "EventCode": "0x56",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_1",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class -WB",
+        "UMask": "0x10d",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Sent Header Flit",
-        "Counter": "0,1,2",
-        "EventCode": "0x56",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_2",
+        "BriefDescription": "FLITs that bypassed the TxL Buffer",
+        "EventCode": "0x41",
+        "EventName": "UNC_UPI_TxL_BYPASSED",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR  mode, increasing latency to transfer out to the link.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Sent Header Flit",
-        "Counter": "0,1,2",
-        "EventCode": "0x56",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_3",
+        "BriefDescription": "Valid data FLITs transmitted via any slot",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel Ultra Path Interconnect (UPI) slots on this UPI unit.",
+        "UMask": "0xf",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; IV",
-        "Counter": "0,1,2",
-        "EventCode": "0x98",
-        "EventName": "UNC_M3UPI_TxR_VERT_NACK.IV",
+        "BriefDescription": "Null FLITs transmitted from any slot",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel Ulra Path Interconnect (UPI) slots on this UPI unit.",
+        "UMask": "0x27",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
-        "Counter": "0,1,2",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.IV",
+        "BriefDescription": "Valid Flits Sent; Data",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.DATA",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UPI0 BL Credits Empty; VNA",
-        "Counter": "0,1,2",
-        "EventCode": "0x21",
-        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA",
+        "BriefDescription": "Idle FLITs transmitted",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.IDLE",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts when the Intel Ultra Path Interconnect(UPI) transmits an idle FLIT(80 bit FLow control unITs).  Every UPI cycle must be sending either data FLITs, protocol/credit FLITs or idle FLITs.",
+        "UMask": "0x47",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UPI0 BL Credits Empty; VN0 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x21",
-        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP",
+        "BriefDescription": "Valid Flits Sent; LLCRD Not Empty",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.LLCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
+        "UMask": "0x10",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UPI0 BL Credits Empty; VN0 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x21",
-        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB",
+        "BriefDescription": "Valid Flits Sent; LLCTRL",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.LLCTRL",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Equivalent to an idle packet.  Enables counting of slot 0 LLCTRL messages.",
+        "UMask": "0x40",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UPI0 BL Credits Empty; VN0 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x21",
-        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB",
+        "BriefDescription": "Protocol header and credit FLITs transmitted across any slot",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts protocol header and credit FLITs (80 bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Interconnect) slots on this UPI unit.",
+        "UMask": "0x97",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Message Received; VLW",
-        "Counter": "0,1",
-        "EventCode": "0x42",
-        "EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.ALL_NULL",
+        "Deprecated": "1",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.NULL",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "UBOX"
+        "UMask": "0x20",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Message Received; MSI",
-        "Counter": "0,1",
-        "EventCode": "0x42",
-        "EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
+        "BriefDescription": "Valid Flits Sent; Protocol Header",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.PROTHDR",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "UBOX"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
+        "UMask": "0x80",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Message Received; IPI",
-        "Counter": "0,1",
-        "EventCode": "0x42",
-        "EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.PROTHDR",
+        "Deprecated": "1",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.PROT_HDR",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "UBOX"
+        "UMask": "0x80",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Message Received",
-        "Counter": "0,1",
-        "EventCode": "0x42",
-        "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
+        "BriefDescription": "Valid Flits Sent; Slot 0",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.SLOT0",
         "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "UBOX"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 0 - Other mask bits determine types of headers to count.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Message Received",
-        "Counter": "0,1",
-        "EventCode": "0x42",
-        "EventName": "UNC_U_EVENT_MSG.INT_PRIO",
+        "BriefDescription": "Valid Flits Sent; Slot 1",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.SLOT1",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "UBOX"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 1 - Other mask bits determine types of headers to count.",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "IDI Lock/SplitLock Cycles",
-        "Counter": "0,1",
-        "EventCode": "0x44",
-        "EventName": "UNC_U_LOCK_CYCLES",
+        "BriefDescription": "Valid Flits Sent; Slot 2",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.SLOT2",
         "PerPkg": "1",
-        "Unit": "UBOX"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 2 - Other mask bits determine types of headers to count.",
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
-        "Counter": "0,1",
-        "EventCode": "0x45",
-        "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.DATA_HDR",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "UBOX"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UNC_U_RACU_DRNG.RDRAND",
-        "Counter": "0,1",
-        "EventCode": "0x4C",
-        "EventName": "UNC_U_RACU_DRNG.RDRAND",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.DUAL_SLOT_HDR",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "UBOX"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UNC_U_RACU_DRNG.RDSEED",
-        "Counter": "0,1",
-        "EventCode": "0x4C",
-        "EventName": "UNC_U_RACU_DRNG.RDSEED",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.LOC",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "UBOX"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
-        "Counter": "0,1",
-        "EventCode": "0x4C",
-        "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
+        "Deprecated": "1",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.NCB",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "UBOX"
+        "UMask": "0xe",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "RACU Request",
-        "Counter": "0,1",
-        "EventCode": "0x46",
-        "EventName": "UNC_U_RACU_REQUESTS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
+        "Deprecated": "1",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.NCS",
         "PerPkg": "1",
-        "Unit": "UBOX"
+        "UMask": "0xf",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
-        "Counter": "FIXED",
-        "EventCode": "0xff",
-        "EventName": "UNC_U_CLOCKTICKS",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.NON_DATA_HDR",
         "PerPkg": "1",
-        "Unit": "UBOX"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0x33",
-        "EventName": "UNC_H_CORE_SNP.CORE_GTONE",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.REM",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE",
-        "UMask": "0x42",
-        "Unit": "CHA"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
         "Deprecated": "1",
-        "EventCode": "0x33",
-        "EventName": "UNC_H_CORE_SNP.EVICT_GTONE",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.REQ",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE",
-        "UMask": "0x82",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
         "Deprecated": "1",
-        "EventCode": "0x53",
-        "EventName": "UNC_H_DIR_LOOKUP.NO_SNP",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_DATA",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP",
-        "UMask": "0x2",
-        "Unit": "CHA"
+        "UMask": "0xc",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
         "Deprecated": "1",
-        "EventCode": "0x53",
-        "EventName": "UNC_H_DIR_LOOKUP.SNP",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_NODATA",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP",
-        "UMask": "0x1",
-        "Unit": "CHA"
+        "UMask": "0xa",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0x54",
-        "EventName": "UNC_H_DIR_UPDATE.HA",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.SGL_SLOT_HDR",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA",
-        "UMask": "0x1",
-        "Unit": "CHA"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
         "Deprecated": "1",
-        "EventCode": "0x54",
-        "EventName": "UNC_H_DIR_UPDATE.TOR",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.SNP",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR",
-        "UMask": "0x2",
-        "Unit": "CHA"
+        "UMask": "0x9",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
         "Deprecated": "1",
-        "EventCode": "0x5F",
-        "EventName": "UNC_H_HITME_HIT.EX_RDS",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.WB",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS",
-        "UMask": "0x1",
-        "Unit": "CHA"
+        "UMask": "0xc",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x39",
-        "EventName": "UNC_H_MISC.RFO_HIT_S",
+        "BriefDescription": "Tx Flit Buffer Allocations",
+        "EventCode": "0x40",
+        "EventName": "UNC_UPI_TxL_INSERTS",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S",
-        "UMask": "0x8",
-        "Unit": "CHA"
+        "PublicDescription": "Number of allocations into the UPI Tx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x50",
-        "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
+        "BriefDescription": "Tx Flit Buffer Occupancy",
+        "EventCode": "0x42",
+        "EventName": "UNC_UPI_TxL_OCCUPANCY",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PublicDescription": "Accumulates the number of flits in the TxQ.  Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x50",
-        "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
+        "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
+        "EventCode": "0x45",
+        "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x50",
-        "EventName": "UNC_H_REQUESTS.READS",
+        "BriefDescription": "VNA Credits Pending Return - Occupancy",
+        "EventCode": "0x44",
+        "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS",
-        "UMask": "0x3",
-        "Unit": "CHA"
+        "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS_LOCAL",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x50",
-        "EventName": "UNC_H_REQUESTS.READS_LOCAL",
+        "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
+        "EventCode": "0xff",
+        "EventName": "UNC_U_CLOCKTICKS",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS_LOCAL",
-        "UMask": "0x1",
-        "Unit": "CHA"
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x50",
-        "EventName": "UNC_H_REQUESTS.WRITES",
+        "BriefDescription": "Message Received",
+        "EventCode": "0x42",
+        "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES",
-        "UMask": "0xC",
-        "Unit": "CHA"
+        "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.",
+        "UMask": "0x8",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES_LOCAL",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x50",
-        "EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
+        "BriefDescription": "Message Received",
+        "EventCode": "0x42",
+        "EventName": "UNC_U_EVENT_MSG.INT_PRIO",
+        "PerPkg": "1",
+        "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.",
+        "UMask": "0x10",
+        "Unit": "UBOX"
+    },
+    {
+        "BriefDescription": "Message Received; IPI",
+        "EventCode": "0x42",
+        "EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES_LOCAL",
+        "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.; Inter Processor Interrupts",
         "UMask": "0x4",
-        "Unit": "CHA"
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x13",
-        "EventName": "UNC_H_RxC_INSERTS.IRQ",
+        "BriefDescription": "Message Received; MSI",
+        "EventCode": "0x42",
+        "EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
+        "PerPkg": "1",
+        "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.; Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)",
+        "UMask": "0x2",
+        "Unit": "UBOX"
+    },
+    {
+        "BriefDescription": "Message Received; VLW",
+        "EventCode": "0x42",
+        "EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ",
+        "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.",
         "UMask": "0x1",
-        "Unit": "CHA"
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x19",
-        "EventName": "UNC_H_RxC_IRQ1_REJECT.PA_MATCH",
+        "BriefDescription": "IDI Lock/SplitLock Cycles",
+        "EventCode": "0x44",
+        "EventName": "UNC_U_LOCK_CYCLES",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "PublicDescription": "Number of times an IDI Lock/SplitLock sequence was started",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ",
-        "Deprecated": "1",
-        "EventCode": "0x11",
-        "EventName": "UNC_H_RxC_OCCUPANCY.IRQ",
+        "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
+        "EventCode": "0x45",
+        "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ",
+        "PublicDescription": "PHOLD cycles.",
         "UMask": "0x1",
-        "Unit": "CHA"
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5C",
-        "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
+        "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+        "EventCode": "0x4C",
+        "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD",
         "UMask": "0x4",
-        "Unit": "CHA"
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5C",
-        "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
+        "BriefDescription": "UNC_U_RACU_DRNG.RDRAND",
+        "EventCode": "0x4C",
+        "EventName": "UNC_U_RACU_DRNG.RDRAND",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD",
-        "UMask": "0x8",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5C",
-        "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
+        "BriefDescription": "UNC_U_RACU_DRNG.RDSEED",
+        "EventCode": "0x4C",
+        "EventName": "UNC_U_RACU_DRNG.RDSEED",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "UBOX"
+    },
+    {
+        "BriefDescription": "RACU Request",
+        "EventCode": "0x46",
+        "EventName": "UNC_U_RACU_REQUESTS",
+        "PerPkg": "1",
+        "PublicDescription": "Number outstanding register requests within message channel tracker",
+        "Unit": "UBOX"
+    },
+    {
+        "BriefDescription": "UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data",
+        "EventCode": "0x2",
+        "EventName": "UPI_DATA_BANDWIDTH_TX",
+        "PerPkg": "1",
+        "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel Ultra Path Interconnect (UPI) slots on this UPI unit.",
+        "ScaleUnit": "7.11E-06Bytes",
+        "UMask": "0xf",
+        "Unit": "UPI LL"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json
index 64301a600ede7..6835e14cd42cd 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json
@@ -1,14 +1,13 @@
 [
     {
         "BriefDescription": "pclk Cycles",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_P_CLOCKTICKS",
         "PerPkg": "1",
+        "PublicDescription": "The PCU runs off a fixed 1 GHz clock.  This event counts the number of pclk cycles measured while the counter was enabled.  The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_P_CORE_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -16,7 +15,6 @@
     },
     {
         "BriefDescription": "UNC_P_DEMOTIONS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x30",
         "EventName": "UNC_P_DEMOTIONS",
         "PerPkg": "1",
@@ -24,71 +22,70 @@
     },
     {
         "BriefDescription": "Phase Shed 0 Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x75",
         "EventName": "UNC_P_FIVR_PS_PS0_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Cycles spent in phase-shedding power state 0",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Phase Shed 1 Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x76",
         "EventName": "UNC_P_FIVR_PS_PS1_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Cycles spent in phase-shedding power state 1",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Phase Shed 2 Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x77",
         "EventName": "UNC_P_FIVR_PS_PS2_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Cycles spent in phase-shedding power state 2",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Phase Shed 3 Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x78",
         "EventName": "UNC_P_FIVR_PS_PS3_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Cycles spent in phase-shedding power state 3",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Thermal Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when thermal conditions are the upper limit on frequency.  This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature.  This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Power Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when power is the upper limit on frequency.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x73",
         "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower.  This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW.  This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Cycles spent changing Frequency",
-        "Counter": "0,1,2,3",
         "EventCode": "0x74",
         "EventName": "UNC_P_FREQ_TRANS_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the system is changing frequency.  This can not be filtered by thread ID.  One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "UNC_P_MCP_PROCHOT_CYCLES",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_P_MCP_PROCHOT_CYCLES",
         "PerPkg": "1",
@@ -96,47 +93,46 @@
     },
     {
         "BriefDescription": "Memory Phase Shedding Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2F",
         "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the PCU has triggered memory phase shedding.  This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the package was in C0.  This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C2E",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2B",
         "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the package was in C2E.  This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2C",
         "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the package was in C3.  This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C6",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2D",
         "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the package was in C6.  This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_P_PMAX_THROTTLED_CYCLES",
         "PerPkg": "1",
@@ -144,55 +140,54 @@
     },
     {
         "BriefDescription": "Number of cores in C-State; C0 and C1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
         "PerPkg": "1",
+        "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Number of cores in C-State; C3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
         "PerPkg": "1",
+        "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Number of cores in C-State; C6 and C7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
         "PerPkg": "1",
+        "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "External Prochot",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that we are in external PROCHOT mode.  This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Internal Prochot",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that we are in Interal PROCHOT mode.  This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Total Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x72",
         "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions across all cores.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "VR Hot",
-        "Counter": "0,1,2,3",
         "EventCode": "0x42",
         "EventName": "UNC_P_VR_HOT_CYCLES",
         "PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/virtual-memory.json b/tools/perf/pmu-events/arch/x86/cascadelakex/virtual-memory.json
index dd334b416c57d..f59405877ae8b 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/virtual-memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Load misses in all DTLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
         "PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
         "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
@@ -32,8 +26,6 @@
     },
     {
         "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
         "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -42,8 +34,6 @@
     },
     {
         "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
         "PublicDescription": "Counts completed page walks  (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -52,8 +42,6 @@
     },
     {
         "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
         "PublicDescription": "Counts completed page walks  (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -62,8 +50,6 @@
     },
     {
         "BriefDescription": "Page walk completed due to a demand data load to a 4K page",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
         "PublicDescription": "Counts completed page walks  (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -72,8 +58,6 @@
     },
     {
         "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
         "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture.",
@@ -82,8 +66,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
         "PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
@@ -92,8 +74,6 @@
     },
     {
         "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT",
         "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
@@ -102,8 +82,6 @@
     },
     {
         "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
@@ -113,8 +91,6 @@
     },
     {
         "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
         "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -123,8 +99,6 @@
     },
     {
         "BriefDescription": "Page walk completed due to a demand data store to a 1G page",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
         "PublicDescription": "Counts completed page walks  (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -133,8 +107,6 @@
     },
     {
         "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
         "PublicDescription": "Counts completed page walks  (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -143,8 +115,6 @@
     },
     {
         "BriefDescription": "Page walk completed due to a demand data store to a 4K page",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
         "PublicDescription": "Counts completed page walks  (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -153,8 +123,6 @@
     },
     {
         "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
         "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture.",
@@ -163,8 +131,6 @@
     },
     {
         "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4f",
         "EventName": "EPT.WALK_PENDING",
         "PublicDescription": "Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type.",
@@ -173,8 +139,6 @@
     },
     {
         "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAE",
         "EventName": "ITLB.ITLB_FLUSH",
         "PublicDescription": "Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
@@ -183,8 +147,6 @@
     },
     {
         "BriefDescription": "Misses at all ITLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
         "PublicDescription": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed.",
@@ -193,8 +155,6 @@
     },
     {
         "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT",
         "SampleAfterValue": "100003",
@@ -202,8 +162,6 @@
     },
     {
         "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_ACTIVE",
@@ -213,8 +171,6 @@
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
         "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -223,8 +179,6 @@
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
         "PublicDescription": "Counts completed page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -233,8 +187,6 @@
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
         "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -243,8 +195,6 @@
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
         "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -253,8 +203,6 @@
     },
     {
         "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_PENDING",
         "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.",
@@ -263,8 +211,6 @@
     },
     {
         "BriefDescription": "DTLB flush attempts of the thread-specific entries",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.DTLB_THREAD",
         "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
@@ -273,8 +219,6 @@
     },
     {
         "BriefDescription": "STLB flush attempts",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.STLB_ANY",
         "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
-- 
GitLab


From 5cebe49ce80391513faf0b9315ca93599407542c Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:54:47 -0800
Subject: [PATCH 571/875] perf vendor events intel: Refresh elkhartlake events

Update the elkhartlake events using the new tooling from:

  https://github.com/intel/perfmon

The events are unchanged but unused json values are removed. This
increases consistency across the json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-1-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../arch/x86/elkhartlake/cache.json           | 252 ------------------
 .../arch/x86/elkhartlake/floating-point.json  |  11 -
 .../arch/x86/elkhartlake/frontend.json        |  36 ---
 .../arch/x86/elkhartlake/memory.json          |  84 ------
 .../arch/x86/elkhartlake/other.json           | 143 ----------
 .../arch/x86/elkhartlake/pipeline.json        | 213 ---------------
 .../arch/x86/elkhartlake/virtual-memory.json  | 117 --------
 7 files changed, 856 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/cache.json b/tools/perf/pmu-events/arch/x86/elkhartlake/cache.json
index d674ee88c3a5d..0ab90e3bf76b0 100644
--- a/tools/perf/pmu-events/arch/x86/elkhartlake/cache.json
+++ b/tools/perf/pmu-events/arch/x86/elkhartlake/cache.json
@@ -1,1137 +1,885 @@
 [
     {
         "BriefDescription": "Counts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a full condition.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "CORE_REJECT_L2Q.ANY",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L2Q.  It also counts requests that would have gone directly to the External Queue (XQ), but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link.  The L2Q may also reject transactions  from a core to ensure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops.  (Note that L2 prefetcher requests that are dropped are not counted by this event).  Counts on a per core basis.",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x51",
         "EventName": "DL1.DIRTY_EVICTION",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.  Does not count evictions or dirty writebacks caused by snoops.  Does not count a replacement unless a (dirty) line was written back.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_XQ.ANY",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link.  The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims).",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_REQUEST.ALL",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects  front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only.  Counts on a per core basis.",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_REQUEST.HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front door request only (does not include rejects or recycles), Counts on a per core basis.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_REQUEST.MISS",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of L2 Cache accesses that resulted in a miss from a front door request only (does not include rejects or recycles). Counts on a per core basis.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of L2 Cache accesses that miss the L2 and get rejected. Counts on a per core basis.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_REQUEST.REJECTS",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of L2 Cache accesses that miss the L2 and get BBL reject  short and long rejects (includes those counted in L2_reject_XQ.any). Counts on a per core basis.",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2e",
         "EventName": "LONGEST_LAT_CACHE.MISS",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
         "SampleAfterValue": "200003",
         "UMask": "0x41"
     },
     {
         "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2e",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
         "SampleAfterValue": "200003",
         "UMask": "0x4f"
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "MEM_BOUND_STALLS.IFETCH",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x38"
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM).",
         "SampleAfterValue": "200003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.",
         "SampleAfterValue": "200003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
         "SampleAfterValue": "200003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "MEM_BOUND_STALLS.LOAD",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x7"
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to a store buffer being full.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "MEM_BOUND_STALLS.STORE_BUFFER_FULL",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Counts the number of load uops retired that hit in DRAM.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache, in which a snoop was required and modified data was forwarded from another core or module.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.HITM",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Counts the number of load uops retired that hit in the L1 data cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of load uops retired that miss in the L1 data cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of load uops retired that miss in the L2 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of memory uops retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.ALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of memory uops retired.  A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST)",
         "SampleAfterValue": "200003",
         "UMask": "0x83"
     },
     {
         "BriefDescription": "Counts the number of load uops retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of load uops retired.",
         "SampleAfterValue": "200003",
         "UMask": "0x81"
     },
     {
         "BriefDescription": "Counts the number of store uops retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of store uops retired.",
         "SampleAfterValue": "200003",
         "UMask": "0x82"
     },
     {
         "BriefDescription": "Counts the number of load uops retired that performed one or more locks.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x21"
     },
     {
         "BriefDescription": "Counts the number of memory uops retired that were splits.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x43"
     },
     {
         "BriefDescription": "Counts the number of retired split load uops.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x41"
     },
     {
         "BriefDescription": "Counts the number of retired split store uops.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x42"
     },
     {
         "BriefDescription": "Counts all code reads that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1F803C0044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.COREWB_M.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3001F803C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1F803C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1F803C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1F803C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1F803C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.FULL_STREAMING_WR.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x801F803C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1F803C0040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1F803C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1F803C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.L1WB_M.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1001F803C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.L2WB_M.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2001F803C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.PARTIAL_STREAMING_WR.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x401F803C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1F803C0477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.STREAMING_WR.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1F803C0800",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x101F803C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010003C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004003C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1008003C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1002003C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1001003C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory writes that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_WR.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x201F803C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "TOPDOWN_FE_BOUND.ICACHE",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x20"
     }
diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/floating-point.json b/tools/perf/pmu-events/arch/x86/elkhartlake/floating-point.json
index 2e1b80c714fd8..88522244b7609 100644
--- a/tools/perf/pmu-events/arch/x86/elkhartlake/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/elkhartlake/floating-point.json
@@ -1,36 +1,25 @@
 [
     {
         "BriefDescription": "Counts the number of cycles the floating point divider is busy.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xcd",
         "EventName": "CYCLES_DIV_BUSY.FPDIV",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles the floating point divider is busy.  Does not imply a stall waiting for the divider.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.FP_ASSIST",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",
         "SampleAfterValue": "20003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.FPDIV",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "2000003",
         "UMask": "0x8"
     }
diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/frontend.json b/tools/perf/pmu-events/arch/x86/elkhartlake/frontend.json
index 5d938a5dafcf9..5ba998e06592c 100644
--- a/tools/perf/pmu-events/arch/x86/elkhartlake/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/elkhartlake/frontend.json
@@ -1,103 +1,67 @@
 [
     {
         "BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xe6",
         "EventName": "BACLEARS.ANY",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend.  Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of BACLEARS due to a conditional jump.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xe6",
         "EventName": "BACLEARS.COND",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts the number of BACLEARS due to an indirect branch.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xe6",
         "EventName": "BACLEARS.INDIRECT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of BACLEARS due to a return branch.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xe6",
         "EventName": "BACLEARS.RETURN",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts the number of BACLEARS due to a direct, unconditional jump.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xe6",
         "EventName": "BACLEARS.UNCOND",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of times a decode restriction reduces the decode throughput due to wrong instruction length prediction.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xe9",
         "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "ICACHE.ACCESSES",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of requests to the instruction cache.  The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one.  Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
         "SampleAfterValue": "200003",
         "UMask": "0x3"
     },
     {
         "BriefDescription": "Counts the number of instruction cache hits.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "ICACHE.HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of requests that hit in the instruction cache.  The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one.  Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of instruction cache misses.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "ICACHE.MISSES",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of missed requests to the instruction cache.  The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one.  Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/memory.json b/tools/perf/pmu-events/arch/x86/elkhartlake/memory.json
index 15eba23796e4b..18621909d1a90 100644
--- a/tools/perf/pmu-events/arch/x86/elkhartlake/memory.json
+++ b/tools/perf/pmu-events/arch/x86/elkhartlake/memory.json
@@ -1,441 +1,357 @@
 [
     {
         "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "20003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of misaligned load uops that are 4K page splits.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of misaligned store uops that are 4K page splits.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.COREWB_M.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3002184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.COREWB_M.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3002184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.FULL_STREAMING_WR.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x802184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.FULL_STREAMING_WR.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x802184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.L1WB_M.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1002184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.L1WB_M.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1002184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.L2WB_M.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2002184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.L2WB_M.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2002184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.OTHER.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.OTHER.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x402184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x402184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all hardware and software prefetches that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.PREFETCHES.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000470",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.STREAMING_WR.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000800",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000800",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x102184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x102184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_WR.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x202184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_WR.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x202184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     }
diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/other.json b/tools/perf/pmu-events/arch/x86/elkhartlake/other.json
index 4a1b7cc5aa23c..00ae180ded25c 100644
--- a/tools/perf/pmu-events/arch/x86/elkhartlake/other.json
+++ b/tools/perf/pmu-events/arch/x86/elkhartlake/other.json
@@ -1,674 +1,531 @@
 [
     {
         "BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.SELF_LOCKS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EdgeDetect": "1",
         "EventCode": "0x63",
         "EventName": "BUS_LOCK.ALL",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x63",
         "EventName": "BUS_LOCK.BLOCK_CYCLES",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores. Counts on a per core basis.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.BLOCK_CYCLES",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x63",
         "EventName": "BUS_LOCK.CYCLES_OTHER_BLOCK",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.LOCK_CYCLES",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x63",
         "EventName": "BUS_LOCK.CYCLES_SELF_BLOCK",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x63",
         "EventName": "BUS_LOCK.LOCK_CYCLES",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued. Counts on a per core basis.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EdgeDetect": "1",
         "EventCode": "0x63",
         "EventName": "BUS_LOCK.SELF_LOCKS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks. Counts on a per core basis.",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_DRAM_HIT",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "C0_STALLS.LOAD_DRAM_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_L2_HIT",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "C0_STALLS.LOAD_L2_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_LLC_HIT",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "C0_STALLS.LOAD_LLC_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of core cycles during which interrupts are masked (disabled).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xcb",
         "EventName": "HW_INTERRUPTS.MASKED",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xcb",
         "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled). Increments by 1 each core cycle that both EFLAGS.IF is 0 and an INTR is pending (which means the APIC is telling the ROB to cause an INTR). This event does not increment if EFLAGS.IF is 0 but all interrupt in the APICs Interrupt Request Register (IRR) are inhibited by the PPR (thus either by ISRV or TPR)  because in these cases the interrupts would be held up in the APIC and would not be pended to the ROB. This event does count when an interrupt is only inhibited by MOV/POP SS state machines or the STI state machine. These extra inhibits only last for a single instructions and would not be important.",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of hardware interrupts received by the processor.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xcb",
         "EventName": "HW_INTERRUPTS.RECEIVED",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "203",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all code reads that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all code reads that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all code reads that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all code reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x8000000000000044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.COREWB_M.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3000000010000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.COREWB_M.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x8003000000000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_CODE_RD.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x8000000000000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x8000000000000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x8000000000000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.FULL_STREAMING_WR.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800000010000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x8000000000000040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_DATA_RD.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x8000000000000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.L1WB_M.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000000010000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.L2WB_M.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000000010000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.OTHER.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x18000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400000010000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all hardware and software prefetches that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.PREFETCHES.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10470",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x8000000000000477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10800",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100000010000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x8000100000000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory writes that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_WR.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200000010000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     }
diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json b/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json
index 09919fdb9a381..9dd8c909faccf 100644
--- a/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json
@@ -1,662 +1,449 @@
 [
     {
         "BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires.  All branch type instructions are accounted for.",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Counts the number of near CALL branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.CALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0xf9"
     },
     {
         "BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.FAR_BRANCH",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0xbf"
     },
     {
         "BriefDescription": "Counts the number of near indirect CALL branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.IND_CALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0xfb"
     },
     {
         "BriefDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.JCC",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x7e"
     },
     {
         "BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.NON_RETURN_IND",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0xeb"
     },
     {
         "BriefDescription": "Counts the number of near relative CALL branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.REL_CALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0xfd"
     },
     {
         "BriefDescription": "Counts the number of near RET branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.RETURN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0xf7"
     },
     {
         "BriefDescription": "Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.TAKEN_JCC",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0xfe"
     },
     {
         "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of mispredicted branch instructions retired.  All branch type instructions are accounted for.  Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP.    A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.IND_CALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0xfb"
     },
     {
         "BriefDescription": "Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.JCC",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x7e"
     },
     {
         "BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0xeb"
     },
     {
         "BriefDescription": "Counts the number of mispredicted near RET branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.RETURN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0xf7"
     },
     {
         "BriefDescription": "Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.TAKEN_JCC",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0xfe"
     },
     {
         "BriefDescription": "Counts the total number of BTCLEARS.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xe8",
         "EventName": "BTCLEAR.ANY",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.CORE",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "33",
         "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of unhalted core clock cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_UNHALTED.CORE_P",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_UNHALTED.REF",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 2",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "34",
         "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
         "SampleAfterValue": "2000003",
         "UMask": "0x3"
     },
     {
         "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xcd",
         "EventName": "CYCLES_DIV_BUSY.ANY",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Counts the number of cycles the integer divider is busy.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xcd",
         "EventName": "CYCLES_DIV_BUSY.IDIV",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles the integer divider is busy.  Does not imply a stall waiting for the divider.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the total number of instructions retired. (Fixed event)",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 0",
         "EventName": "INST_RETIRED.ANY",
         "PEBS": "1",
-        "PEBScounters": "32",
         "PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the total number of instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc0",
         "EventName": "INST_RETIRED.ANY_P",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter.",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.4K_ALIAS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of retired loads that are blocked for any of the following reasons:  DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.ALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.DATA_UNKNOWN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of retired loads that are blocked because its address partially overlapped with an older store.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.STORE_FORWARD",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assist.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.ANY",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "20003"
     },
     {
         "BriefDescription": "Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.DISAMBIGUATION",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "20003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts the number of machine clears due to a page fault.  Counts both I-Side and D-Side (Loads/Stores) page faults.  A page fault occurs when either the page is not present, or an access violation occurs.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.PAGE_FAULT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "20003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.SMC",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "20003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x73",
         "EventName": "TOPDOWN_BAD_SPECULATION.ALL",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
         "SampleAfterValue": "1000003",
         "UMask": "0x6"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x73",
         "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x73",
         "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x73",
         "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x73",
         "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x74",
         "EventName": "TOPDOWN_BE_BOUND.ALL",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x74",
         "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x74",
         "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x74",
         "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x74",
         "EventName": "TOPDOWN_BE_BOUND.REGISTER",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x74",
         "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x74",
         "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "This event is deprecated.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x74",
         "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to frontend stalls.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "TOPDOWN_FE_BOUND.ALL",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
         "SampleAfterValue": "1000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
         "SampleAfterValue": "1000003",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "TOPDOWN_FE_BOUND.CISC",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "TOPDOWN_FE_BOUND.DECODE",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "TOPDOWN_FE_BOUND.ITLB",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.",
         "SampleAfterValue": "1000003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "TOPDOWN_FE_BOUND.OTHER",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "TOPDOWN_FE_BOUND.PREDECODE",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the total number of consumed retirement slots.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc2",
         "EventName": "TOPDOWN_RETIRING.ALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003"
     },
     {
         "BriefDescription": "Counts the number of uops issued by the front end every cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x0e",
         "EventName": "UOPS_ISSUED.ANY",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2.  Uops_issued correlates to the number of ROB entries.  If uop takes 2 ROB slots it counts as 2 uops_issued.",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Counts the total number of uops retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.ALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Counts the number of integer divide uops retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.IDIV",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "2000003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.MS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of x87 uops retired, includes those in MS flows.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.X87",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     }
diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json b/tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json
index b82f11591f133..cabe29e70e796 100644
--- a/tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json
@@ -1,363 +1,246 @@
 [
     {
         "BriefDescription": "Counts the number of page walks due to loads that miss the PDE (Page Directory Entry) cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Account for all page sizes. Will result in a DTLB write from STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
         "SampleAfterValue": "200003",
         "UMask": "0xe"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1GB pages. Includes page walks that page fault.",
         "SampleAfterValue": "200003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for demand loads every cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for demand loads every cycle.  A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
         "SampleAfterValue": "200003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts the number of page walks due to stores that miss the PDE (Page Directory Entry) cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "2000003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Account for all pages sizes. Will result in a DTLB write from STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "2000003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size.  Includes page walks that page fault.",
         "SampleAfterValue": "200003",
         "UMask": "0xe"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages.  Includes page walks that page fault.",
         "SampleAfterValue": "200003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 2M or 4M page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages.  Includes page walks that page fault.",
         "SampleAfterValue": "2000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages.  Includes page walks that page fault.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.  A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
         "SampleAfterValue": "200003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts the number of Extended Page Directory Entry hits.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4f",
         "EventName": "EPT.EPDE_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of Extended Page Directory Entry hits.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of Extended Page Directory Entry misses.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4f",
         "EventName": "EPT.EPDE_MISS",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number Extended Page Directory Entry misses.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of Extended Page Directory Pointer Entry hits.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4f",
         "EventName": "EPT.EPDPE_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number Extended Page Directory Pointer Entry hits.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
         "SampleAfterValue": "2000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of Extended Page Directory Pointer Entry misses.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4f",
         "EventName": "EPT.EPDPE_MISS",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number Extended Page Directory Pointer Entry misses.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
         "SampleAfterValue": "2000003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4f",
         "EventName": "EPT.WALK_PENDING",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
         "SampleAfterValue": "200003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts the number of times there was an ITLB miss and a new translation was filled into the ITLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x81",
         "EventName": "ITLB.FILLS",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and a new translation was filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.PDE_CACHE_MISS",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "2000003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "2000003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size.  Includes page walks that page fault.",
         "SampleAfterValue": "200003",
         "UMask": "0xe"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 1G page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages.  Includes page walks that page fault.",
         "SampleAfterValue": "200003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages.  Includes page walks that page fault.",
         "SampleAfterValue": "2000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 4K page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages.  Includes page walks that page fault.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_PENDING",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle.  A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk).",
         "SampleAfterValue": "200003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts the number of retired loads that are blocked due to a first level TLB miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.DTLB_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts the number of memory uops retired that missed in the second level TLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.DTLB_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x13"
     },
     {
         "BriefDescription": "Counts the number of load uops retired that miss in the second Level TLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x11"
     },
     {
         "BriefDescription": "Counts the number of store uops retired that miss in the second level TLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x12"
     }
-- 
GitLab


From 387bc79f83948e9f6eca6429d3ccdbc96a11228d Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:54:48 -0800
Subject: [PATCH 572/875] perf vendor events intel: Refresh goldmont events

Update the goldmont events using the new tooling from:

  https://github.com/intel/perfmon

The events are unchanged but unused json values are removed. This
increases consistency across the json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-2-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../pmu-events/arch/x86/goldmont/cache.json   | 288 ------------------
 .../arch/x86/goldmont/floating-point.json     |   6 -
 .../arch/x86/goldmont/frontend.json           |  16 -
 .../pmu-events/arch/x86/goldmont/memory.json  |   6 -
 .../pmu-events/arch/x86/goldmont/other.json   |  10 -
 .../arch/x86/goldmont/pipeline.json           |  77 -----
 .../arch/x86/goldmont/virtual-memory.json     |  14 -
 7 files changed, 417 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/goldmont/cache.json b/tools/perf/pmu-events/arch/x86/goldmont/cache.json
index ed957d4f9c6d3..ee47a09172a15 100644
--- a/tools/perf/pmu-events/arch/x86/goldmont/cache.json
+++ b/tools/perf/pmu-events/arch/x86/goldmont/cache.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Requests rejected by the L2Q",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "CORE_REJECT_L2Q.ALL",
         "PublicDescription": "Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops.",
@@ -10,8 +8,6 @@
     },
     {
         "BriefDescription": "L1 Cache evictions for dirty data",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x51",
         "EventName": "DL1.DIRTY_EVICTION",
         "PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory.  No count will occur if the evicted line is clean, and hence does not require a writeback.",
@@ -20,8 +16,6 @@
     },
     {
         "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x86",
         "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES",
         "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss.  Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.",
@@ -30,8 +24,6 @@
     },
     {
         "BriefDescription": "Requests rejected by the XQ",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_XQ.ALL",
         "PublicDescription": "Counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cacheable requests), L2 misses and L2 write-back victims.",
@@ -39,8 +31,6 @@
     },
     {
         "BriefDescription": "L2 cache request misses",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.MISS",
         "PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
@@ -49,8 +39,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
         "PublicDescription": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
@@ -59,8 +47,6 @@
     },
     {
         "BriefDescription": "Loads retired that came from DRAM (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
@@ -71,8 +57,6 @@
     },
     {
         "BriefDescription": "Memory uop retired where cross core or cross module HITM occurred (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.HITM",
@@ -83,8 +67,6 @@
     },
     {
         "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
@@ -95,8 +77,6 @@
     },
     {
         "BriefDescription": "Load uops retired that missed L1 data cache (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
@@ -107,8 +87,6 @@
     },
     {
         "BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
@@ -119,8 +97,6 @@
     },
     {
         "BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
@@ -131,8 +107,6 @@
     },
     {
         "BriefDescription": "Loads retired that hit WCB (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT",
@@ -143,8 +117,6 @@
     },
     {
         "BriefDescription": "Memory uops retired (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.ALL",
@@ -155,8 +127,6 @@
     },
     {
         "BriefDescription": "Load uops retired (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
@@ -167,8 +137,6 @@
     },
     {
         "BriefDescription": "Store uops retired (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
@@ -179,8 +147,6 @@
     },
     {
         "BriefDescription": "Locked load uops retired (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
@@ -191,8 +157,6 @@
     },
     {
         "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT",
@@ -203,8 +167,6 @@
     },
     {
         "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
@@ -215,8 +177,6 @@
     },
     {
         "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
@@ -227,8 +187,6 @@
     },
     {
         "BriefDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE",
         "SampleAfterValue": "100007",
@@ -236,1066 +194,820 @@
     },
     {
         "BriefDescription": "Counts data reads (demand & prefetch) that hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000043091",
-        "Offcore": "1",
         "PublicDescription": "Counts data reads (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3600003091",
-        "Offcore": "1",
         "PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000003091",
-        "Offcore": "1",
         "PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400003091",
-        "Offcore": "1",
         "PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200003091",
-        "Offcore": "1",
         "PublicDescription": "Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000043010",
-        "Offcore": "1",
         "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3600003010",
-        "Offcore": "1",
         "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000003010",
-        "Offcore": "1",
         "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400003010",
-        "Offcore": "1",
         "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200003010",
-        "Offcore": "1",
         "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00000432b7",
-        "Offcore": "1",
         "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x36000032b7",
-        "Offcore": "1",
         "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10000032b7",
-        "Offcore": "1",
         "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x04000032b7",
-        "Offcore": "1",
         "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x02000032b7",
-        "Offcore": "1",
         "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystem.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000018000",
-        "Offcore": "1",
         "PublicDescription": "Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts requests to the uncore subsystem that hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000048000",
-        "Offcore": "1",
         "PublicDescription": "Counts requests to the uncore subsystem that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000008000",
-        "Offcore": "1",
         "PublicDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400008000",
-        "Offcore": "1",
         "PublicDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200008000",
-        "Offcore": "1",
         "PublicDescription": "Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000040022",
-        "Offcore": "1",
         "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3600000022",
-        "Offcore": "1",
         "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000000022",
-        "Offcore": "1",
         "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400000022",
-        "Offcore": "1",
         "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200000022",
-        "Offcore": "1",
         "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts bus lock and split lock requests that have any transaction responses from the uncore subsystem.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010400",
-        "Offcore": "1",
         "PublicDescription": "Counts bus lock and split lock requests that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.L2_HIT",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x0000040008",
-        "Offcore": "1",
         "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.ANY",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x3600000008",
-        "Offcore": "1",
         "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x1000000008",
-        "Offcore": "1",
         "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x0400000008",
-        "Offcore": "1",
         "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x0200000008",
-        "Offcore": "1",
         "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000040004",
-        "Offcore": "1",
         "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3600000004",
-        "Offcore": "1",
         "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400000004",
-        "Offcore": "1",
         "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200000004",
-        "Offcore": "1",
         "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000004",
-        "Offcore": "1",
         "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data reads of full cache lines that hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000040001",
-        "Offcore": "1",
         "PublicDescription": "Counts demand cacheable data reads of full cache lines that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3600000001",
-        "Offcore": "1",
         "PublicDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000000001",
-        "Offcore": "1",
         "PublicDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400000001",
-        "Offcore": "1",
         "PublicDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200000001",
-        "Offcore": "1",
         "PublicDescription": "Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000001",
-        "Offcore": "1",
         "PublicDescription": "Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000040002",
-        "Offcore": "1",
         "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3600000002",
-        "Offcore": "1",
         "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000000002",
-        "Offcore": "1",
         "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400000002",
-        "Offcore": "1",
         "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200000002",
-        "Offcore": "1",
         "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000002",
-        "Offcore": "1",
         "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000040800",
-        "Offcore": "1",
         "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3600000800",
-        "Offcore": "1",
         "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000000800",
-        "Offcore": "1",
         "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400000800",
-        "Offcore": "1",
         "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200000800",
-        "Offcore": "1",
         "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3600000080",
-        "Offcore": "1",
         "PublicDescription": "Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000044000",
-        "Offcore": "1",
         "PublicDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3600004000",
-        "Offcore": "1",
         "PublicDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000004000",
-        "Offcore": "1",
         "PublicDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400004000",
-        "Offcore": "1",
         "PublicDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200004000",
-        "Offcore": "1",
         "PublicDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3600000100",
-        "Offcore": "1",
         "PublicDescription": "Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000042000",
-        "Offcore": "1",
         "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3600002000",
-        "Offcore": "1",
         "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000002000",
-        "Offcore": "1",
         "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400002000",
-        "Offcore": "1",
         "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200002000",
-        "Offcore": "1",
         "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000040010",
-        "Offcore": "1",
         "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3600000010",
-        "Offcore": "1",
         "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000000010",
-        "Offcore": "1",
         "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400000010",
-        "Offcore": "1",
         "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200000010",
-        "Offcore": "1",
         "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000040020",
-        "Offcore": "1",
         "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3600000020",
-        "Offcore": "1",
         "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000000020",
-        "Offcore": "1",
         "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400000020",
-        "Offcore": "1",
         "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200000020",
-        "Offcore": "1",
         "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  that hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000044800",
-        "Offcore": "1",
         "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3600004800",
-        "Offcore": "1",
         "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cache lines requests by software prefetch instructions that hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000041000",
-        "Offcore": "1",
         "PublicDescription": "Counts data cache lines requests by software prefetch instructions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3600001000",
-        "Offcore": "1",
         "PublicDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000001000",
-        "Offcore": "1",
         "PublicDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400001000",
-        "Offcore": "1",
         "PublicDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200001000",
-        "Offcore": "1",
         "PublicDescription": "Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
diff --git a/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json b/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json
index 37174392a5108..a3f03855ca05d 100644
--- a/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Cycles the FP divide unit is busy",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCD",
         "EventName": "CYCLES_DIV_BUSY.FPDIV",
         "PublicDescription": "Counts core cycles the floating point divide unit is busy.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Machine clears due to FP assists",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.FP_ASSIST",
         "PublicDescription": "Counts machine clears due to floating point (FP) operations needing assists.  For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result.",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Floating point divide uops retired. (Precise Event Capable)",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.FPDIV",
         "PEBS": "2",
diff --git a/tools/perf/pmu-events/arch/x86/goldmont/frontend.json b/tools/perf/pmu-events/arch/x86/goldmont/frontend.json
index 216da6e121c87..ace2a114b546f 100644
--- a/tools/perf/pmu-events/arch/x86/goldmont/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/goldmont/frontend.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "BACLEARs asserted for any branch type",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE6",
         "EventName": "BACLEARS.ALL",
         "PublicDescription": "Counts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call,  Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returns.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "BACLEARs asserted for conditional branch",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE6",
         "EventName": "BACLEARS.COND",
         "PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branches.",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "BACLEARs asserted for return branch",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE6",
         "EventName": "BACLEARS.RETURN",
         "PublicDescription": "Counts BACLEARS on return instructions.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Decode restrictions due to predicting wrong instruction length",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE9",
         "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",
         "PublicDescription": "Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect.",
@@ -41,8 +33,6 @@
     },
     {
         "BriefDescription": "References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "ICACHE.ACCESSES",
         "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line.  The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS.  Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.\r\nThis event counts differently than Intel processors based on Silvermont microarchitecture.",
@@ -51,8 +41,6 @@
     },
     {
         "BriefDescription": "References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "ICACHE.HIT",
         "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit).  The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT.  Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
@@ -61,8 +49,6 @@
     },
     {
         "BriefDescription": "References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "ICACHE.MISSES",
         "PublicDescription": "Counts requests to the Instruction Cache (ICache)  for one or more bytes in an ICache Line and that cache line is not in the ICache (miss).  The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS.  Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
@@ -71,8 +57,6 @@
     },
     {
         "BriefDescription": "MS decode starts",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE7",
         "EventName": "MS_DECODED.MS_ENTRY",
         "PublicDescription": "Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM.  The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine.  Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops.  The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear.",
diff --git a/tools/perf/pmu-events/arch/x86/goldmont/memory.json b/tools/perf/pmu-events/arch/x86/goldmont/memory.json
index 9f6f0328249e7..b97642a109ee4 100644
--- a/tools/perf/pmu-events/arch/x86/goldmont/memory.json
+++ b/tools/perf/pmu-events/arch/x86/goldmont/memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Machine clears due to memory ordering issue",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
         "PublicDescription": "Counts machine clears due to memory ordering issues.  This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved as another core is in the process of modifying the data.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Load uops that split a page (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",
         "PEBS": "2",
@@ -22,8 +18,6 @@
     },
     {
         "BriefDescription": "Store uops that split a page (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",
         "PEBS": "2",
diff --git a/tools/perf/pmu-events/arch/x86/goldmont/other.json b/tools/perf/pmu-events/arch/x86/goldmont/other.json
index d888f67aa2ea5..c4fd0acb15bcf 100644
--- a/tools/perf/pmu-events/arch/x86/goldmont/other.json
+++ b/tools/perf/pmu-events/arch/x86/goldmont/other.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Cycles code-fetch stalled due to any reason.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x86",
         "EventName": "FETCH_STALL.ALL",
         "PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes.  This will include cycles due to an ITLB miss, ICache miss and other events.",
@@ -10,8 +8,6 @@
     },
     {
         "BriefDescription": "Cycles code-fetch stalled due to an outstanding ITLB miss.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x86",
         "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES",
         "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss.  Note: this event is not the same as page walk cycles to retrieve an instruction translation.",
@@ -20,8 +16,6 @@
     },
     {
         "BriefDescription": "Cycles hardware interrupts are masked",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "HW_INTERRUPTS.MASKED",
         "PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.",
@@ -30,8 +24,6 @@
     },
     {
         "BriefDescription": "Cycles pending interrupts are masked",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED",
         "PublicDescription": "Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0).",
@@ -40,8 +32,6 @@
     },
     {
         "BriefDescription": "Hardware interrupts received",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "HW_INTERRUPTS.RECEIVED",
         "PublicDescription": "Counts hardware interrupts received by the processor.",
diff --git a/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json b/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json
index 42ff0b134aebd..acb897483a879 100644
--- a/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Retired branch instructions (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "PEBS": "2",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Retired taken branch instructions (Precise event capable)",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES",
         "PEBS": "2",
@@ -22,8 +18,6 @@
     },
     {
         "BriefDescription": "Retired near call instructions (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.CALL",
         "PEBS": "2",
@@ -33,8 +27,6 @@
     },
     {
         "BriefDescription": "Retired far branch instructions (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.FAR_BRANCH",
         "PEBS": "2",
@@ -44,8 +36,6 @@
     },
     {
         "BriefDescription": "Retired near indirect call instructions (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.IND_CALL",
         "PEBS": "2",
@@ -55,8 +45,6 @@
     },
     {
         "BriefDescription": "Retired conditional branch instructions (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.JCC",
         "PEBS": "2",
@@ -66,8 +54,6 @@
     },
     {
         "BriefDescription": "Retired instructions of near indirect Jmp or call (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NON_RETURN_IND",
         "PEBS": "2",
@@ -77,8 +63,6 @@
     },
     {
         "BriefDescription": "Retired near relative call instructions (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.REL_CALL",
         "PEBS": "2",
@@ -88,8 +72,6 @@
     },
     {
         "BriefDescription": "Retired near return instructions (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.RETURN",
         "PEBS": "2",
@@ -99,8 +81,6 @@
     },
     {
         "BriefDescription": "Retired conditional branch instructions that were taken (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.TAKEN_JCC",
         "PEBS": "2",
@@ -110,8 +90,6 @@
     },
     {
         "BriefDescription": "Retired mispredicted branch instructions (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PEBS": "2",
@@ -120,8 +98,6 @@
     },
     {
         "BriefDescription": "Retired mispredicted near indirect call instructions (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.IND_CALL",
         "PEBS": "2",
@@ -131,8 +107,6 @@
     },
     {
         "BriefDescription": "Retired mispredicted conditional branch instructions (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.JCC",
         "PEBS": "2",
@@ -142,8 +116,6 @@
     },
     {
         "BriefDescription": "Retired mispredicted instructions of near indirect Jmp or near indirect call. (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
         "PEBS": "2",
@@ -153,8 +125,6 @@
     },
     {
         "BriefDescription": "Retired mispredicted near return instructions (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.RETURN",
         "PEBS": "2",
@@ -164,8 +134,6 @@
     },
     {
         "BriefDescription": "Retired mispredicted conditional branch instructions that were taken (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.TAKEN_JCC",
         "PEBS": "2",
@@ -175,7 +143,6 @@
     },
     {
         "BriefDescription": "Core cycles when core is not halted  (Fixed event)",
-        "Counter": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.CORE",
         "PublicDescription": "Counts the number of core cycles while the core is not in a halt state.  The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time.  This event uses fixed counter 1.  You cannot collect a PEBs record for this event.",
         "SampleAfterValue": "2000003",
@@ -183,8 +150,6 @@
     },
     {
         "BriefDescription": "Core cycles when core is not halted",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.CORE_P",
         "PublicDescription": "Core cycles when core is not halted.  This event uses a (_P)rogrammable general purpose performance counter.",
@@ -192,8 +157,6 @@
     },
     {
         "BriefDescription": "Reference cycles when core is not halted",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF",
         "PublicDescription": "Reference cycles when core is not halted.  This event uses a programmable general purpose performance counter.",
@@ -202,7 +165,6 @@
     },
     {
         "BriefDescription": "Reference cycles when core is not halted  (Fixed event)",
-        "Counter": "Fixed counter 2",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
         "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction.  In mobile systems the core frequency may change from time.  This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  This event uses fixed counter 2.  You cannot collect a PEBs record for this event.",
         "SampleAfterValue": "2000003",
@@ -210,8 +172,6 @@
     },
     {
         "BriefDescription": "Cycles a divider is busy",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCD",
         "EventName": "CYCLES_DIV_BUSY.ALL",
         "PublicDescription": "Counts core cycles if either divide unit is busy.",
@@ -219,8 +179,6 @@
     },
     {
         "BriefDescription": "Cycles the integer divide unit is busy",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCD",
         "EventName": "CYCLES_DIV_BUSY.IDIV",
         "PublicDescription": "Counts core cycles the integer divide unit is busy.",
@@ -229,7 +187,6 @@
     },
     {
         "BriefDescription": "Instructions retired (Fixed event)",
-        "Counter": "Fixed counter 0",
         "EventName": "INST_RETIRED.ANY",
         "PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers.  This event uses fixed counter 0.  You cannot collect a PEBs record for this event.",
         "SampleAfterValue": "2000003",
@@ -237,8 +194,6 @@
     },
     {
         "BriefDescription": "Instructions retired (Precise event capable)",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.ANY_P",
         "PEBS": "2",
@@ -247,8 +202,6 @@
     },
     {
         "BriefDescription": "Unfilled issue slots per cycle",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCA",
         "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY",
         "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource  in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY).",
@@ -256,8 +209,6 @@
     },
     {
         "BriefDescription": "Unfilled issue slots per cycle to recover",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCA",
         "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY",
         "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows).   Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue.",
@@ -266,8 +217,6 @@
     },
     {
         "BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCA",
         "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL",
         "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend.  Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable.   Note that uops must be available for consumption in order for this event to fire.  If a uop is not available (Instruction Queue is empty), this event will not count.",
@@ -276,8 +225,6 @@
     },
     {
         "BriefDescription": "Loads blocked because address has 4k partial address false dependence (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.4K_ALIAS",
         "PEBS": "2",
@@ -287,8 +234,6 @@
     },
     {
         "BriefDescription": "Loads blocked (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.ALL_BLOCK",
         "PEBS": "2",
@@ -298,8 +243,6 @@
     },
     {
         "BriefDescription": "Loads blocked due to store data not ready (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.DATA_UNKNOWN",
         "PEBS": "2",
@@ -309,8 +252,6 @@
     },
     {
         "BriefDescription": "Loads blocked due to store forward restriction (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.STORE_FORWARD",
         "PEBS": "2",
@@ -320,8 +261,6 @@
     },
     {
         "BriefDescription": "Loads blocked because address in not in the UTLB (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.UTLB_MISS",
         "PEBS": "2",
@@ -331,8 +270,6 @@
     },
     {
         "BriefDescription": "All machine clears",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.ALL",
         "PublicDescription": "Counts machine clears for any reason.",
@@ -340,8 +277,6 @@
     },
     {
         "BriefDescription": "Machine clears due to memory disambiguation",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.DISAMBIGUATION",
         "PublicDescription": "Counts machine clears due to memory disambiguation.  Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load address.",
@@ -350,8 +285,6 @@
     },
     {
         "BriefDescription": "Self-Modifying Code detected",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.SMC",
         "PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification.  Self-modifying code (SMC) causes a severe penalty in all Intel(R) architecture processors.",
@@ -360,8 +293,6 @@
     },
     {
         "BriefDescription": "Uops issued to the back end per cycle",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.ANY",
         "PublicDescription": "Counts uops issued by the front end and allocated into the back end of the machine.  This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clear.",
@@ -369,8 +300,6 @@
     },
     {
         "BriefDescription": "Uops requested but not-delivered to the back-end per cycle",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9C",
         "EventName": "UOPS_NOT_DELIVERED.ANY",
         "PublicDescription": "This event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound.  When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources.  When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks.  However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all.  Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots.  These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots.  A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock.  The low uop issue rate for a stream of INC instructions is considered to be a back end issue.",
@@ -378,8 +307,6 @@
     },
     {
         "BriefDescription": "Uops retired (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ANY",
         "PEBS": "2",
@@ -388,8 +315,6 @@
     },
     {
         "BriefDescription": "Integer divide uops retired. (Precise Event Capable)",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.IDIV",
         "PEBS": "2",
@@ -399,8 +324,6 @@
     },
     {
         "BriefDescription": "MS uops retired (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.MS",
         "PEBS": "2",
diff --git a/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json b/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json
index 2e17e02e14634..8c4929a517fa9 100644
--- a/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "ITLB misses",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x81",
         "EventName": "ITLB.MISS",
         "PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch.  It counts when new translation are filled into the ITLB.  The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Memory uops retired that missed the DTLB (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.DTLB_MISS",
@@ -23,8 +19,6 @@
     },
     {
         "BriefDescription": "Load uops retired that missed the DTLB (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
@@ -35,8 +29,6 @@
     },
     {
         "BriefDescription": "Store uops retired that missed the DTLB (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES",
@@ -47,8 +39,6 @@
     },
     {
         "BriefDescription": "Duration of page-walks in cycles",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x05",
         "EventName": "PAGE_WALKS.CYCLES",
         "PublicDescription": "Counts every core cycle a page-walk is in progress due to either a data memory operation or an instruction fetch.",
@@ -57,8 +47,6 @@
     },
     {
         "BriefDescription": "Duration of D-side page-walks in cycles",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x05",
         "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
         "PublicDescription": "Counts every core cycle when a Data-side (walks due to a data operation) page walk is in progress.",
@@ -67,8 +55,6 @@
     },
     {
         "BriefDescription": "Duration of I-side pagewalks in cycles",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x05",
         "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
         "PublicDescription": "Counts every core cycle when a Instruction-side (walks due to an instruction fetch) page walk is in progress.",
-- 
GitLab


From a335420d32988f39e889b6ae3be2c965ec32a38e Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:54:49 -0800
Subject: [PATCH 573/875] perf vendor events intel: Refresh goldmontplus events

Update the goldmontplus events using the new tooling from:

  https://github.com/intel/perfmon

The events are unchanged but unused json values are removed. This
increases consistency across the json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-3-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../arch/x86/goldmontplus/cache.json          | 470 ------------------
 .../arch/x86/goldmontplus/floating-point.json |  11 -
 .../arch/x86/goldmontplus/frontend.json       |  32 --
 .../arch/x86/goldmontplus/memory.json         |  10 -
 .../arch/x86/goldmontplus/other.json          |  20 -
 .../arch/x86/goldmontplus/pipeline.json       | 143 ------
 .../arch/x86/goldmontplus/virtual-memory.json |  69 ---
 7 files changed, 755 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json b/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json
index 16e8913c04349..a7f80fd1b1df2 100644
--- a/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json
+++ b/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json
@@ -1,1463 +1,993 @@
 [
     {
         "BriefDescription": "Requests rejected by the L2Q",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "CORE_REJECT_L2Q.ALL",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops.",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "L1 Cache evictions for dirty data",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x51",
         "EventName": "DL1.REPLACEMENT",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory.  No count will occur if the evicted line is clean, and hence does not require a writeback.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x86",
         "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss.  Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Requests rejected by the XQ",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_XQ.ALL",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cacheable requests), L2 misses and L2 write-back victims.",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "L2 cache request misses",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.MISS",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
         "SampleAfterValue": "200003",
         "UMask": "0x41"
     },
     {
         "BriefDescription": "L2 cache requests",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
         "SampleAfterValue": "200003",
         "UMask": "0x4f"
     },
     {
         "BriefDescription": "Loads retired that came from DRAM (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts memory load uops retired where the data is retrieved from DRAM.  Event is counted at retirement, so the speculative loads are ignored.  A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response.",
         "SampleAfterValue": "200003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Memory uop retired where cross core or cross module HITM occurred (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.HITM",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts load uops retired where the cache line containing the data was in the modified state of another core or modules cache (HITM).  More specifically, this means that when the load address was checked by other caching agents (typically another processor) in the system, one of those caching agents indicated that they had a dirty copy of the data.  Loads that obtain a HITM response incur greater latency than most is typical for a load.  In addition, since HITM indicates that some other processor had this data in its cache, it implies that the data was shared between processors, or potentially was a lock or semaphore value.  This event is useful for locating sharing, false sharing, and contended locks.",
         "SampleAfterValue": "200003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts load uops retired that hit the L1 data cache.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Load uops retired that missed L1 data cache (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts load uops retired that miss the L1 data cache.",
         "SampleAfterValue": "200003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts load uops retired that hit in the L2 cache.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts load uops retired that miss in the L2 cache.",
         "SampleAfterValue": "200003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Loads retired that hit WCB (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts memory load uops retired where the data is retrieved from the WCB (or fill buffer), indicating that the load found its data while that data was in the process of being brought into the L1 cache.  Typically a load will receive this indication when some other load or prefetch missed the L1 cache and was in the process of retrieving the cache line containing the data, but that process had not yet finished (and written the data back to the cache). For example, consider load X and Y, both referencing the same cache line that is not in the L1 cache.  If load X misses cache first, it obtains and WCB (or fill buffer) and begins the process of requesting the data.  When load Y requests the data, it will either hit the WCB, or the L1 cache, depending on exactly what time the request to Y occurs.",
         "SampleAfterValue": "200003",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Memory uops retired (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.ALL",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of memory uops retired that is either a loads or a store or both.",
         "SampleAfterValue": "200003",
         "UMask": "0x83"
     },
     {
         "BriefDescription": "Load uops retired (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of load uops retired.",
         "SampleAfterValue": "200003",
         "UMask": "0x81"
     },
     {
         "BriefDescription": "Store uops retired (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of store uops retired.",
         "SampleAfterValue": "200003",
         "UMask": "0x82"
     },
     {
         "BriefDescription": "Locked load uops retired (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts locked memory uops retired.  This includes regular locks and bus locks. (To specifically count bus locks only, see the Offcore response event.)  A locked access is one with a lock prefix, or an exchange to memory.  See the SDM for a complete description of which memory load accesses are locks.",
         "SampleAfterValue": "200003",
         "UMask": "0x21"
     },
     {
         "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts memory uops retired where the data requested spans a 64 byte cache line boundary.",
         "SampleAfterValue": "200003",
         "UMask": "0x43"
     },
     {
         "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts load uops retired where the data requested spans a 64 byte cache line boundary.",
         "SampleAfterValue": "200003",
         "UMask": "0x41"
     },
     {
         "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts store uops retired where the data requested spans a 64 byte cache line boundary.",
         "SampleAfterValue": "200003",
         "UMask": "0x42"
     },
     {
         "BriefDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000013091",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data reads (demand & prefetch) hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000043091",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x1000003091",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0200003091",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000003091",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000013010",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_HIT",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000043010",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x1000003010",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0200003010",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000003010",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.ANY_RESPONSE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x00000132b7",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x00000432b7",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x10000032b7",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x02000032b7",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x40000032b7",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000018000",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts requests to the uncore subsystem hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000048000",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts requests to the uncore subsystem hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x1000008000",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0200008000",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000008000",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000010022",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000040022",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x1000000022",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0200000022",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000022",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts bus lock and split lock requests have any transaction responses from the uncore subsystem.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000010400",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts bus lock and split lock requests have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts bus lock and split lock requests hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000040400",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts bus lock and split lock requests hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x1000000400",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0200000400",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000400",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000010008",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.L2_HIT",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000040008",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x1000000008",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0200000008",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000008",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000010004",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000040004",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x1000000004",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0200000004",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000004",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000010001",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data reads of full cache lines hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000040001",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts demand cacheable data reads of full cache lines hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x1000000001",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0200000001",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000001",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000010002",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000040002",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x1000000002",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0200000002",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000002",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.ANY_RESPONSE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000010800",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_HIT",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000040800",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x1000000800",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0200000800",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000800",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000012000",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000042000",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x1000002000",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0200002000",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000002000",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000010010",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_HIT",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000040010",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x1000000010",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0200000010",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000010",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000010020",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000040020",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x1000000020",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0200000020",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000020",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  have any transaction responses from the uncore subsystem.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000014800",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_HIT",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000044800",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x1000004800",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0200004800",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  outstanding, per cycle, from the time of the L2 miss to when any response is received.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000004800",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.ANY_RESPONSE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000011000",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cache lines requests by software prefetch instructions hit the L2 cache.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_HIT",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0000041000",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data cache lines requests by software prefetch instructions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x1000001000",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6, 0x1a7",
         "MSRValue": "0x0200001000",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000001000",
-        "Offcore": "1",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json b/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json
index 9c3d224395303..822a7a6bcaeb1 100644
--- a/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json
@@ -1,36 +1,25 @@
 [
     {
         "BriefDescription": "Cycles the FP divide unit is busy",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCD",
         "EventName": "CYCLES_DIV_BUSY.FPDIV",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts core cycles the floating point divide unit is busy.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Machine clears due to FP assists",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.FP_ASSIST",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts machine clears due to floating point (FP) operations needing assists.  For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result.",
         "SampleAfterValue": "20003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Floating point divide uops retired (Precise Event Capable)",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.FPDIV",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of floating point divide uops retired.",
         "SampleAfterValue": "2000003",
         "UMask": "0x8"
diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json b/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json
index 4c2abfbac8f8f..ace2a114b546f 100644
--- a/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json
@@ -1,96 +1,64 @@
 [
     {
         "BriefDescription": "BACLEARs asserted for any branch type",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE6",
         "EventName": "BACLEARS.ALL",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call,  Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returns.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "BACLEARs asserted for conditional branch",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE6",
         "EventName": "BACLEARS.COND",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branches.",
         "SampleAfterValue": "200003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "BACLEARs asserted for return branch",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE6",
         "EventName": "BACLEARS.RETURN",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts BACLEARS on return instructions.",
         "SampleAfterValue": "200003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Decode restrictions due to predicting wrong instruction length",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE9",
         "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "ICACHE.ACCESSES",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line.  The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS.  Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.\r\nThis event counts differently than Intel processors based on Silvermont microarchitecture.",
         "SampleAfterValue": "200003",
         "UMask": "0x3"
     },
     {
         "BriefDescription": "References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "ICACHE.HIT",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit).  The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT.  Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "ICACHE.MISSES",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts requests to the Instruction Cache (ICache)  for one or more bytes in an ICache Line and that cache line is not in the ICache (miss).  The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS.  Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "MS decode starts",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE7",
         "EventName": "MS_DECODED.MS_ENTRY",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM.  The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine.  Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops.  The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json b/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json
index ae0cb3451866f..7038873a5c8d1 100644
--- a/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json
+++ b/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json
@@ -1,36 +1,26 @@
 [
     {
         "BriefDescription": "Machine clears due to memory ordering issue",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts machine clears due to memory ordering issues.  This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved - as another core is in the process of modifying the data.",
         "SampleAfterValue": "20003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Load uops that split a page (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts when a memory load of a uop spans a page boundary (a split) is retired.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Store uops that split a page (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts when a memory store of a uop spans a page boundary (a split) is retired.",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/other.json b/tools/perf/pmu-events/arch/x86/goldmontplus/other.json
index 92586fe4538ad..ec0ce9078c988 100644
--- a/tools/perf/pmu-events/arch/x86/goldmontplus/other.json
+++ b/tools/perf/pmu-events/arch/x86/goldmontplus/other.json
@@ -1,59 +1,39 @@
 [
     {
         "BriefDescription": "Cycles code-fetch stalled due to any reason.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x86",
         "EventName": "FETCH_STALL.ALL",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes.  This will include cycles due to an ITLB miss, ICache miss and other events.",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Cycles the code-fetch stalls and an ITLB miss is outstanding.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x86",
         "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss.  Note: this event is not the same as page walk cycles to retrieve an instruction translation.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles hardware interrupts are masked",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "HW_INTERRUPTS.MASKED",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles pending interrupts are masked",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0).",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Hardware interrupts received",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "HW_INTERRUPTS.RECEIVED",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts hardware interrupts received by the processor.",
         "SampleAfterValue": "203",
         "UMask": "0x1"
diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json b/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json
index 2b712b12cc1fc..33ef331e77e08 100644
--- a/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json
@@ -1,289 +1,208 @@
 [
     {
         "BriefDescription": "Retired branch instructions (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts branch instructions retired for all branch types.  This is an architectural performance event.",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Retired taken branch instructions (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of taken branch instructions retired.",
         "SampleAfterValue": "200003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Retired near call instructions (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.CALL",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts near CALL branch instructions retired.",
         "SampleAfterValue": "200003",
         "UMask": "0xf9"
     },
     {
         "BriefDescription": "Retired far branch instructions (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.FAR_BRANCH",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts far branch instructions retired.  This includes far jump, far call and return, and Interrupt call and return.",
         "SampleAfterValue": "200003",
         "UMask": "0xbf"
     },
     {
         "BriefDescription": "Retired near indirect call instructions (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.IND_CALL",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts near indirect CALL branch instructions retired.",
         "SampleAfterValue": "200003",
         "UMask": "0xfb"
     },
     {
         "BriefDescription": "Retired conditional branch instructions (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.JCC",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was taken and when it was not taken.",
         "SampleAfterValue": "200003",
         "UMask": "0x7e"
     },
     {
         "BriefDescription": "Retired instructions of near indirect Jmp or call (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NON_RETURN_IND",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts near indirect call or near indirect jmp branch instructions retired.",
         "SampleAfterValue": "200003",
         "UMask": "0xeb"
     },
     {
         "BriefDescription": "Retired near relative call instructions (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.REL_CALL",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts near relative CALL branch instructions retired.",
         "SampleAfterValue": "200003",
         "UMask": "0xfd"
     },
     {
         "BriefDescription": "Retired near return instructions (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.RETURN",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts near return branch instructions retired.",
         "SampleAfterValue": "200003",
         "UMask": "0xf7"
     },
     {
         "BriefDescription": "Retired conditional branch instructions that were taken (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.TAKEN_JCC",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were taken and does not count when the Jcc branch instruction were not taken.",
         "SampleAfterValue": "200003",
         "UMask": "0xfe"
     },
     {
         "BriefDescription": "Retired mispredicted branch instructions (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts mispredicted branch instructions retired including all branch types.",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Retired mispredicted near indirect call instructions (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.IND_CALL",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts mispredicted near indirect CALL branch instructions retired, where the target address taken was not what the processor predicted.",
         "SampleAfterValue": "200003",
         "UMask": "0xfb"
     },
     {
         "BriefDescription": "Retired mispredicted conditional branch instructions (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.JCC",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was supposed to be taken and when it was not supposed to be taken (but the processor predicted the opposite condition).",
         "SampleAfterValue": "200003",
         "UMask": "0x7e"
     },
     {
         "BriefDescription": "Retired mispredicted instructions of near indirect Jmp or near indirect call (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted.",
         "SampleAfterValue": "200003",
         "UMask": "0xeb"
     },
     {
         "BriefDescription": "Retired mispredicted near return instructions (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.RETURN",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts mispredicted near RET branch instructions retired, where the return address taken was not what the processor predicted.",
         "SampleAfterValue": "200003",
         "UMask": "0xf7"
     },
     {
         "BriefDescription": "Retired mispredicted conditional branch instructions that were taken (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.TAKEN_JCC",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were supposed to be taken but the processor predicted that it would not be taken.",
         "SampleAfterValue": "200003",
         "UMask": "0xfe"
     },
     {
         "BriefDescription": "Core cycles when core is not halted  (Fixed event)",
-        "CollectPEBSRecord": "1",
-        "Counter": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.CORE",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "33",
         "PublicDescription": "Counts the number of core cycles while the core is not in a halt state.  The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time.  This event uses fixed counter 1.  You cannot collect a PEBs record for this event.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Core cycles when core is not halted",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.CORE_P",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Core cycles when core is not halted.  This event uses a (_P)rogrammable general purpose performance counter.",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Reference cycles when core is not halted",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Reference cycles when core is not halted.  This event uses a (_P)rogrammable general purpose performance counter.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Reference cycles when core is not halted  (Fixed event)",
-        "CollectPEBSRecord": "1",
-        "Counter": "Fixed counter 2",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "34",
         "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction.  In mobile systems the core frequency may change from time.  This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  This event uses fixed counter 2.  You cannot collect a PEBs record for this event.",
         "SampleAfterValue": "2000003",
         "UMask": "0x3"
     },
     {
         "BriefDescription": "Cycles a divider is busy",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCD",
         "EventName": "CYCLES_DIV_BUSY.ALL",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts core cycles if either divide unit is busy.",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Cycles the integer divide unit is busy",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCD",
         "EventName": "CYCLES_DIV_BUSY.IDIV",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts core cycles the integer divide unit is busy.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Instructions retired (Fixed event)",
-        "CollectPEBSRecord": "1",
-        "Counter": "Fixed counter 0",
         "EventName": "INST_RETIRED.ANY",
-        "PDIR_COUNTER": "na",
         "PEBS": "2",
-        "PEBScounters": "32",
         "PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers.  This event uses fixed counter 0.  You cannot collect a PEBs record for this event.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Instructions retired (Precise event capable)",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.ANY_P",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers.  This is an architectural performance event.  This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable:  The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event.  Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time.",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Instructions retired - using Reduced Skid PEBS feature",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.PREC_DIST",
         "PEBS": "2",
@@ -292,201 +211,139 @@
     },
     {
         "BriefDescription": "Unfilled issue slots per cycle",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCA",
         "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource  in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY).",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Unfilled issue slots per cycle to recover",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCA",
         "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows).   Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCA",
         "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend.  Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable.   Note that uops must be available for consumption in order for this event to fire.  If a uop is not available (Instruction Queue is empty), this event will not count.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads blocked because address has 4k partial address false dependence (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.4K_ALIAS",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts loads that block because their address modulo 4K matches a pending store.",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Loads blocked (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.ALL_BLOCK",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts anytime a load that retires is blocked for any reason.",
         "SampleAfterValue": "200003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Loads blocked due to store data not ready (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.DATA_UNKNOWN",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts a load blocked from using a store forward, but did not occur because the store data was not available at the right time.  The forward might occur subsequently when the data is available.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads blocked due to store forward restriction (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.STORE_FORWARD",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts a load blocked from using a store forward because of an address/size mismatch, only one of the loads blocked from each store will be counted.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Loads blocked because address in not in the UTLB (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.UTLB_MISS",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts loads blocked because they are unable to find their physical address in the micro TLB (UTLB).",
         "SampleAfterValue": "200003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "All machine clears",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.ALL",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts machine clears for any reason.",
         "SampleAfterValue": "20003"
     },
     {
         "BriefDescription": "Machine clears due to memory disambiguation",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.DISAMBIGUATION",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts machine clears due to memory disambiguation.  Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load address.",
         "SampleAfterValue": "20003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Machines clear due to a page fault",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.PAGE_FAULT",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times that the machines clears due to a page fault. Covers both I-side and D-side(Loads/Stores) page faults. A page fault occurs when either page is not present, or an access violation",
         "SampleAfterValue": "20003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Self-Modifying Code detected",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.SMC",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification.  Self-modifying code (SMC) causes a severe penalty in all Intel(R) architecture processors.",
         "SampleAfterValue": "20003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Uops issued to the back end per cycle",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.ANY",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts uops issued by the front end and allocated into the back end of the machine.  This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clear.",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Uops requested but not-delivered to the back-end per cycle",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9C",
         "EventName": "UOPS_NOT_DELIVERED.ANY",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "This event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound.  When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources.  When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks.  However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all.  Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots.  These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots.  A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock.  The low uop issue rate for a stream of INC instructions is considered to be a back end issue.",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Uops retired (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ANY",
-        "PDIR_COUNTER": "na",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts uops which retired.",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Integer divide uops retired (Precise Event Capable)",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.IDIV",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of integer divide uops retired.",
         "SampleAfterValue": "2000003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "MS uops retired (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.MS",
-        "PDIR_COUNTER": "na",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts uops retired that are from the complex flows issued by the micro-sequencer (MS).  Counts both the uops from a micro-coded instruction, and the uops that might be generated from a micro-coded assist.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json b/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json
index 1f7db22c15e6d..3d6feb45a50b6 100644
--- a/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json
@@ -1,219 +1,150 @@
 [
     {
         "BriefDescription": "Page walk completed due to a demand load to a 1GB page",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1GB",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 1GB pages.  The page walks can end with or without a page fault.",
         "SampleAfterValue": "200003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Page walk completed due to a demand load to a 2M or 4M page",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 2M or 4M pages.  The page walks can end with or without a page fault.",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Page walk completed due to a demand load to a 4K page",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 4K pages.  The page walks can end with or without a page fault.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Page walks outstanding due to a demand load every cycle.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts once per cycle for each page walk occurring due to a load (demand data loads or SW prefetches). Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks.",
         "SampleAfterValue": "200003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Page walk completed due to a demand data store to a 1GB page",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1GB",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1GB pages.  The page walks can end with or without a page fault.",
         "SampleAfterValue": "2000003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Page walk completed due to a demand data store to a 2M or 4M page",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M or 4M pages.  The page walks can end with or without a page fault.",
         "SampleAfterValue": "2000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Page walk completed due to a demand data store to a 4K page",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Page walks outstanding due to a demand data store every cycle.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts once per cycle for each page walk occurring due to a demand data store. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks.",
         "SampleAfterValue": "200003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Page walks outstanding due to walking the EPT every cycle",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4F",
         "EventName": "EPT.WALK_PENDING",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts once per cycle for each page walk only while traversing the Extended Page Table (EPT), and does not count during the rest of the translation.  The EPT is used for translating Guest-Physical Addresses to Physical Addresses for Virtual Machine Monitors (VMMs).  Average cycles per walk can be calculated by dividing the count by number of walks.",
         "SampleAfterValue": "200003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "ITLB misses",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x81",
         "EventName": "ITLB.MISS",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch.  It counts when new translation are filled into the ITLB.  The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Page walk completed due to an instruction fetch in a 1GB page",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_1GB",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 1GB pages.  The page walks can end with or without a page fault.",
         "SampleAfterValue": "2000003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Page walk completed due to an instruction fetch in a 2M or 4M page",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 2M or 4M pages.  The page walks can end with or without a page fault.",
         "SampleAfterValue": "2000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Page walk completed due to an instruction fetch in a 4K page",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Page walks outstanding due to an instruction fetch every cycle.",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_PENDING",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts once per cycle for each page walk occurring due to an instruction fetch. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks.",
         "SampleAfterValue": "200003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Memory uops retired that missed the DTLB (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.DTLB_MISS",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts uops retired that had a DTLB miss on load, store or either.  Note that when two distinct memory operations to the same page miss the DTLB, only one of them will be recorded as a DTLB miss.",
         "SampleAfterValue": "200003",
         "UMask": "0x13"
     },
     {
         "BriefDescription": "Load uops retired that missed the DTLB (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts load uops retired that caused a DTLB miss.",
         "SampleAfterValue": "200003",
         "UMask": "0x11"
     },
     {
         "BriefDescription": "Store uops retired that missed the DTLB (Precise event capable)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts store uops retired that caused a DTLB miss.",
         "SampleAfterValue": "200003",
         "UMask": "0x12"
     },
     {
         "BriefDescription": "STLB flushes",
-        "CollectPEBSRecord": "1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSHES.STLB_ANY",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts STLB flushes.  The TLBs are flushed on instructions like INVLPG and MOV to CR3.",
         "SampleAfterValue": "20003",
         "UMask": "0x20"
-- 
GitLab


From 8749311045ef5c727a540bbdfcf54f5b81683312 Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:54:50 -0800
Subject: [PATCH 574/875] perf vendor events intel: Refresh haswell metrics and
 events

Update the haswell metrics and events using the new tooling from:

  https://github.com/intel/perfmon

The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1".  The
events are unchanged but unused json values are removed. The
formatting changes increase consistency across the json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-4-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../pmu-events/arch/x86/haswell/cache.json    | 211 --------------
 .../arch/x86/haswell/floating-point.json      |  20 --
 .../pmu-events/arch/x86/haswell/frontend.json |  58 ----
 .../arch/x86/haswell/hsw-metrics.json         | 117 ++++----
 .../pmu-events/arch/x86/haswell/memory.json   | 149 ----------
 .../pmu-events/arch/x86/haswell/other.json    |   8 -
 .../pmu-events/arch/x86/haswell/pipeline.json | 258 ------------------
 .../arch/x86/haswell/uncore-cache.json        |  50 ----
 .../arch/x86/haswell/uncore-other.json        |  21 +-
 .../arch/x86/haswell/virtual-memory.json      |  98 -------
 10 files changed, 73 insertions(+), 917 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/haswell/cache.json b/tools/perf/pmu-events/arch/x86/haswell/cache.json
index 719b8e622f596..5a1489e79859d 100644
--- a/tools/perf/pmu-events/arch/x86/haswell/cache.json
+++ b/tools/perf/pmu-events/arch/x86/haswell/cache.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "L1D data line replacements",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x51",
         "EventName": "L1D.REPLACEMENT",
         "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.FB_FULL",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "L1D miss outstanding duration in cycles",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING",
         "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Cycles with L1D load Misses outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -42,8 +34,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -52,8 +42,6 @@
     },
     {
         "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL",
         "SampleAfterValue": "2000003",
@@ -61,8 +49,6 @@
     },
     {
         "BriefDescription": "Not rejected writebacks that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x27",
         "EventName": "L2_DEMAND_RQSTS.WB_HIT",
         "PublicDescription": "Not rejected writebacks that hit L2 cache.",
@@ -71,8 +57,6 @@
     },
     {
         "BriefDescription": "L2 cache lines filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.ALL",
         "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache.  Lines are filled into the L2 cache when there was an L2 miss.",
@@ -81,8 +65,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in E state filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.E",
         "PublicDescription": "L2 cache lines in E state filling L2.",
@@ -91,8 +73,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in I state filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.I",
         "PublicDescription": "L2 cache lines in I state filling L2.",
@@ -101,8 +81,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in S state filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.S",
         "PublicDescription": "L2 cache lines in S state filling L2.",
@@ -111,8 +89,6 @@
     },
     {
         "BriefDescription": "Clean L2 cache lines evicted by demand",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
         "PublicDescription": "Clean L2 cache lines evicted by demand.",
@@ -121,8 +97,6 @@
     },
     {
         "BriefDescription": "Dirty L2 cache lines evicted by demand",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
         "PublicDescription": "Dirty L2 cache lines evicted by demand.",
@@ -131,8 +105,6 @@
     },
     {
         "BriefDescription": "L2 code requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_CODE_RD",
         "PublicDescription": "Counts all L2 code requests.",
@@ -141,8 +113,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD78, HSM80",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
@@ -152,8 +122,6 @@
     },
     {
         "BriefDescription": "Demand requests that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD78, HSM80",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
@@ -163,8 +131,6 @@
     },
     {
         "BriefDescription": "Demand requests to L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD78, HSM80",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
@@ -174,8 +140,6 @@
     },
     {
         "BriefDescription": "Requests from L2 hardware prefetchers",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_PF",
         "PublicDescription": "Counts all L2 HW prefetcher requests.",
@@ -184,8 +148,6 @@
     },
     {
         "BriefDescription": "RFO requests to L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_RFO",
         "PublicDescription": "Counts all L2 store RFO requests.",
@@ -194,8 +156,6 @@
     },
     {
         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_HIT",
         "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
@@ -204,8 +164,6 @@
     },
     {
         "BriefDescription": "L2 cache misses when fetching instructions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_MISS",
         "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
@@ -214,8 +172,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD78, HSM80",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
@@ -225,8 +181,6 @@
     },
     {
         "BriefDescription": "Demand Data Read miss L2, no rejects",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD78, HSM80",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
@@ -236,8 +190,6 @@
     },
     {
         "BriefDescription": "L2 prefetch requests that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.L2_PF_HIT",
         "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
@@ -246,8 +198,6 @@
     },
     {
         "BriefDescription": "L2 prefetch requests that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.L2_PF_MISS",
         "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
@@ -256,8 +206,6 @@
     },
     {
         "BriefDescription": "All requests that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD78, HSM80",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.MISS",
@@ -267,8 +215,6 @@
     },
     {
         "BriefDescription": "All L2 requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD78, HSM80",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.REFERENCES",
@@ -278,8 +224,6 @@
     },
     {
         "BriefDescription": "RFO requests that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_HIT",
         "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.",
@@ -288,8 +232,6 @@
     },
     {
         "BriefDescription": "RFO requests that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_MISS",
         "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
@@ -298,8 +240,6 @@
     },
     {
         "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xf0",
         "EventName": "L2_TRANS.ALL_PF",
         "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.",
@@ -308,8 +248,6 @@
     },
     {
         "BriefDescription": "Transactions accessing L2 pipe",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xf0",
         "EventName": "L2_TRANS.ALL_REQUESTS",
         "PublicDescription": "Transactions accessing L2 pipe.",
@@ -318,8 +256,6 @@
     },
     {
         "BriefDescription": "L2 cache accesses when fetching instructions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xf0",
         "EventName": "L2_TRANS.CODE_RD",
         "PublicDescription": "L2 cache accesses when fetching instructions.",
@@ -328,8 +264,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xf0",
         "EventName": "L2_TRANS.DEMAND_DATA_RD",
         "PublicDescription": "Demand data read requests that access L2 cache.",
@@ -338,8 +272,6 @@
     },
     {
         "BriefDescription": "L1D writebacks that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xf0",
         "EventName": "L2_TRANS.L1D_WB",
         "PublicDescription": "L1D writebacks that access L2 cache.",
@@ -348,8 +280,6 @@
     },
     {
         "BriefDescription": "L2 fill requests that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xf0",
         "EventName": "L2_TRANS.L2_FILL",
         "PublicDescription": "L2 fill requests that access L2 cache.",
@@ -358,8 +288,6 @@
     },
     {
         "BriefDescription": "L2 writebacks that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xf0",
         "EventName": "L2_TRANS.L2_WB",
         "PublicDescription": "L2 writebacks that access L2 cache.",
@@ -368,8 +296,6 @@
     },
     {
         "BriefDescription": "RFO requests that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xf0",
         "EventName": "L2_TRANS.RFO",
         "PublicDescription": "RFO requests that access L2 cache.",
@@ -378,8 +304,6 @@
     },
     {
         "BriefDescription": "Cycles when L1D is locked",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x63",
         "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
         "PublicDescription": "Cycles in which the L1D is locked.",
@@ -388,8 +312,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests missed L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.MISS",
         "PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
@@ -398,8 +320,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
         "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
@@ -408,8 +328,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD29, HSD25, HSM26, HSM30",
         "EventCode": "0xD2",
@@ -420,8 +338,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD29, HSD25, HSM26, HSM30",
         "EventCode": "0xD2",
@@ -432,8 +348,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD29, HSD25, HSM26, HSM30",
         "EventCode": "0xD2",
@@ -444,8 +358,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
         "EventCode": "0xD2",
@@ -456,8 +368,6 @@
     },
     {
         "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD74, HSD29, HSD25, HSM30",
         "EventCode": "0xD3",
@@ -469,8 +379,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSM30",
         "EventCode": "0xD1",
@@ -481,8 +389,6 @@
     },
     {
         "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD29, HSM30",
         "EventCode": "0xD1",
@@ -493,8 +399,6 @@
     },
     {
         "BriefDescription": "Retired load uops misses in L1 cache as data sources.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSM30",
         "EventCode": "0xD1",
@@ -506,8 +410,6 @@
     },
     {
         "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD76, HSD29, HSM30",
         "EventCode": "0xD1",
@@ -518,8 +420,6 @@
     },
     {
         "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD29, HSM30",
         "EventCode": "0xD1",
@@ -531,8 +431,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
         "EventCode": "0xD1",
@@ -544,8 +442,6 @@
     },
     {
         "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
         "EventCode": "0xD1",
@@ -557,8 +453,6 @@
     },
     {
         "BriefDescription": "Retired load uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD29, HSM30",
         "EventCode": "0xD0",
@@ -570,13 +464,10 @@
     },
     {
         "BriefDescription": "Retired store uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD29, HSM30",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "PublicDescription": "Counts all retired store uops.",
         "SampleAfterValue": "2000003",
@@ -584,8 +475,6 @@
     },
     {
         "BriefDescription": "Retired load uops with locked access.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD76, HSD29, HSM30",
         "EventCode": "0xD0",
@@ -596,8 +485,6 @@
     },
     {
         "BriefDescription": "Retired load uops that split across a cacheline boundary.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD29, HSM30",
         "EventCode": "0xD0",
@@ -608,21 +495,16 @@
     },
     {
         "BriefDescription": "Retired store uops that split across a cacheline boundary.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD29, HSM30",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x42"
     },
     {
         "BriefDescription": "Retired load uops that miss the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD29, HSM30",
         "EventCode": "0xD0",
@@ -633,21 +515,16 @@
     },
     {
         "BriefDescription": "Retired store uops that miss the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD29, HSM30",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x12"
     },
     {
         "BriefDescription": "Demand and prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
         "PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
@@ -656,8 +533,6 @@
     },
     {
         "BriefDescription": "Cacheable and noncacheable code read requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
         "PublicDescription": "Demand code read requests sent to uncore.",
@@ -666,8 +541,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests sent to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD78, HSM80",
         "EventCode": "0xb0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
@@ -677,8 +550,6 @@
     },
     {
         "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
         "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
@@ -687,8 +558,6 @@
     },
     {
         "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb2",
         "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
         "SampleAfterValue": "2000003",
@@ -696,8 +565,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD62, HSD61, HSM63",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
@@ -707,8 +574,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "Errata": "HSD62, HSD61, HSM63",
         "EventCode": "0x60",
@@ -718,8 +583,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
         "EventCode": "0x60",
@@ -729,8 +592,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "Errata": "HSD62, HSD61, HSM63",
         "EventCode": "0x60",
@@ -740,8 +601,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD62, HSD61, HSM63",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
@@ -751,8 +610,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
@@ -762,8 +619,6 @@
     },
     {
         "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "6",
         "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
         "EventCode": "0x60",
@@ -773,8 +628,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD62, HSD61, HSM63",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
@@ -784,8 +637,6 @@
     },
     {
         "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE",
         "SampleAfterValue": "100003",
@@ -793,248 +644,186 @@
     },
     {
         "BriefDescription": "Counts all demand & prefetch code readshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0244",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data readshit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data readshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C07F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C07F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all requestshit in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C8FFF",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOshit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code readshit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code readshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data readshit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data readshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code readshit in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data readshit in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOshit in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code readshit in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0200",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data readshit in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOshit in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Split locks in SQ",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xf4",
         "EventName": "SQ_MISC.SPLIT_LOCK",
         "SampleAfterValue": "100003",
diff --git a/tools/perf/pmu-events/arch/x86/haswell/floating-point.json b/tools/perf/pmu-events/arch/x86/haswell/floating-point.json
index 7cf203a90a749..8fcc10f74ad99 100644
--- a/tools/perf/pmu-events/arch/x86/haswell/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/haswell/floating-point.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores.  May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC6",
         "EventName": "AVX_INSTS.ALL",
         "PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Cycles with any input/output SSE or FP assist",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.ANY",
@@ -22,8 +18,6 @@
     },
     {
         "BriefDescription": "Number of SIMD FP assists due to input values",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.SIMD_INPUT",
         "PublicDescription": "Number of SIMD FP assists due to input values.",
@@ -32,8 +26,6 @@
     },
     {
         "BriefDescription": "Number of SIMD FP assists due to Output values",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.SIMD_OUTPUT",
         "PublicDescription": "Number of SIMD FP assists due to output values.",
@@ -42,8 +34,6 @@
     },
     {
         "BriefDescription": "Number of X87 assists due to input value.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.X87_INPUT",
         "PublicDescription": "Number of X87 FP assists due to input values.",
@@ -52,8 +42,6 @@
     },
     {
         "BriefDescription": "Number of X87 assists due to output value.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.X87_OUTPUT",
         "PublicDescription": "Number of X87 FP assists due to output values.",
@@ -62,8 +50,6 @@
     },
     {
         "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
         "PublicDescription": "Number of SIMD move elimination candidate uops that were eliminated.",
@@ -72,8 +58,6 @@
     },
     {
         "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
         "PublicDescription": "Number of SIMD move elimination candidate uops that were not eliminated.",
@@ -82,8 +66,6 @@
     },
     {
         "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD56, HSM57",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.AVX_TO_SSE",
@@ -92,8 +74,6 @@
     },
     {
         "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD56, HSM57",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.SSE_TO_AVX",
diff --git a/tools/perf/pmu-events/arch/x86/haswell/frontend.json b/tools/perf/pmu-events/arch/x86/haswell/frontend.json
index 18a993297108c..73d6d681dfa71 100644
--- a/tools/perf/pmu-events/arch/x86/haswell/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/haswell/frontend.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xe6",
         "EventName": "BACLEARS.ANY",
         "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAB",
         "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
         "SampleAfterValue": "2000003",
@@ -20,8 +16,6 @@
     },
     {
         "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.HIT",
         "SampleAfterValue": "2000003",
@@ -29,8 +23,6 @@
     },
     {
         "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.IFDATA_STALL",
         "SampleAfterValue": "2000003",
@@ -38,8 +30,6 @@
     },
     {
         "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.IFETCH_STALL",
         "SampleAfterValue": "2000003",
@@ -47,8 +37,6 @@
     },
     {
         "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.MISSES",
         "PublicDescription": "This event counts Instruction Cache (ICACHE) misses.",
@@ -57,8 +45,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -68,8 +54,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -79,8 +63,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering 4 Uops",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -90,8 +72,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering any Uop",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -101,8 +81,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_CYCLES",
@@ -111,8 +89,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_UOPS",
         "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
@@ -121,8 +97,6 @@
     },
     {
         "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "HSD135",
         "EventCode": "0x79",
         "EventName": "IDQ.EMPTY",
@@ -132,8 +106,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_ALL_UOPS",
         "PublicDescription": "Number of uops delivered to IDQ from any path.",
@@ -142,8 +114,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_CYCLES",
@@ -152,8 +122,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_UOPS",
         "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",
@@ -162,8 +130,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_CYCLES",
@@ -173,8 +139,6 @@
     },
     {
         "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_DSB_CYCLES",
@@ -183,8 +147,6 @@
     },
     {
         "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
@@ -194,8 +156,6 @@
     },
     {
         "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_DSB_UOPS",
         "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
@@ -204,8 +164,6 @@
     },
     {
         "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_MITE_UOPS",
         "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
@@ -214,8 +172,6 @@
     },
     {
         "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
@@ -225,8 +181,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_UOPS",
         "PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the microcode sequencer.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance.",
@@ -235,8 +189,6 @@
     },
     {
         "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "HSD135",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
@@ -246,8 +198,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "Errata": "HSD135",
         "EventCode": "0x9C",
@@ -258,8 +208,6 @@
     },
     {
         "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "Errata": "HSD135",
         "EventCode": "0x9C",
@@ -270,8 +218,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "3",
         "Errata": "HSD135",
         "EventCode": "0x9C",
@@ -281,8 +227,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "2",
         "Errata": "HSD135",
         "EventCode": "0x9C",
@@ -292,8 +236,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "Errata": "HSD135",
         "EventCode": "0x9C",
diff --git a/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json b/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json
index 6cb6603efbd8f..2e032beee542a 100644
--- a/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json
@@ -88,7 +88,7 @@
     },
     {
         "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
-        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
         "MetricGroup": "TopdownL1;tma_L1_group",
         "MetricName": "tma_bad_speculation",
         "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
@@ -96,7 +96,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
-        "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
+        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
         "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
         "MetricName": "tma_branch_mispredicts",
         "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
@@ -120,7 +120,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
-        "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB)) * tma_backend_bound",
+        "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if IPC > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB) if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if IPC > 1.8 else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB))) * tma_backend_bound",
         "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
         "MetricName": "tma_memory_bound",
         "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@@ -152,7 +152,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
-        "MetricExpr": "(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
+        "MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
         "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
         "MetricName": "tma_lock_latency",
         "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS",
@@ -192,7 +192,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
-        "MetricExpr": "(MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
+        "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
         "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_l3_bound",
         "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
@@ -200,7 +200,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
-        "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / CLKS",
+        "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / CLKS",
         "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_contested_accesses",
         "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
@@ -208,7 +208,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
-        "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
+        "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
         "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_data_sharing",
         "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
@@ -216,7 +216,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
-        "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
+        "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
         "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_l3_hit_latency",
         "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
@@ -224,7 +224,7 @@
     },
     {
         "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
-        "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
+        "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
         "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_sq_full",
         "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
@@ -232,7 +232,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
-        "MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS))) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
+        "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
         "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_dram_bound",
         "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS",
@@ -264,7 +264,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
-        "MetricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES))) + (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
+        "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
         "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
         "MetricName": "tma_store_latency",
         "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
@@ -312,7 +312,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
-        "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / CLKS",
+        "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if IPC > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB) if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if IPC > 1.8 else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / CLKS",
         "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
         "MetricName": "tma_ports_utilization",
         "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@@ -320,7 +320,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@) / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else 0) / CORE_CLKS",
+        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) / CORE_CLKS)",
         "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
         "MetricName": "tma_ports_utilized_0",
         "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
@@ -328,7 +328,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / CORE_CLKS",
+        "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / CORE_CLKS)",
         "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
         "MetricName": "tma_ports_utilized_1",
         "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
@@ -336,7 +336,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / CORE_CLKS",
+        "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / CORE_CLKS)",
         "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
         "MetricName": "tma_ports_utilized_2",
         "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
@@ -344,14 +344,14 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
-        "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / CORE_CLKS",
+        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / CORE_CLKS",
         "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
         "MetricName": "tma_ports_utilized_3m",
         "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
-        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / (4 * CORE_CLKS)",
+        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS",
         "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
         "MetricName": "tma_alu_op_utilization",
         "ScaleUnit": "100%"
@@ -407,7 +407,7 @@
     },
     {
         "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
+        "MetricExpr": "tma_port_4",
         "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
         "MetricName": "tma_store_op_utilization",
         "ScaleUnit": "100%"
@@ -460,7 +460,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
-        "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
         "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
         "MetricName": "tma_microcode_sequencer",
         "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
@@ -526,13 +526,13 @@
     },
     {
         "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
-        "MetricExpr": "(UOPS_EXECUTED.CORE / 2 / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@)) if #SMT_on else UOPS_EXECUTED.CORE / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@)",
+        "MetricExpr": "(UOPS_EXECUTED.CORE / 2 / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@) if #SMT_on else UOPS_EXECUTED.CORE / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@))",
         "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
         "MetricName": "ILP"
     },
     {
         "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
-        "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
+        "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
         "MetricGroup": "SMT",
         "MetricName": "CORE_CLKS"
     },
@@ -586,7 +586,7 @@
     },
     {
         "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
-        "MetricExpr": "IDQ.DSB_UOPS / ((IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS))",
+        "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
         "MetricGroup": "DSB;Fed;FetchBW",
         "MetricName": "DSB_Coverage"
     },
@@ -598,7 +598,7 @@
     },
     {
         "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
-        "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb)",
+        "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)",
         "MetricGroup": "Mem;MemoryBound;MemoryLat",
         "MetricName": "Load_Miss_Real_Latency"
     },
@@ -610,19 +610,19 @@
     },
     {
         "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L1MPKI"
     },
     {
         "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
         "MetricGroup": "Backend;CacheMisses;Mem",
         "MetricName": "L2MPKI"
     },
     {
         "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L3MPKI"
     },
@@ -635,19 +635,19 @@
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
-        "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
+        "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L1D_Cache_Fill_BW"
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
-        "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
+        "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L2_Cache_Fill_BW"
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
+        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L3_Cache_Fill_BW"
     },
@@ -677,13 +677,13 @@
     },
     {
         "BriefDescription": "Average CPU Utilization",
-        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
+        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
         "MetricGroup": "HPC;Summary",
         "MetricName": "CPU_Utilization"
     },
     {
         "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
-        "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
+        "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
         "MetricGroup": "Power;Summary",
         "MetricName": "Average_Frequency"
     },
@@ -695,7 +695,7 @@
     },
     {
         "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
-        "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
+        "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
         "MetricGroup": "SMT",
         "MetricName": "SMT_2T_Utilization"
     },
@@ -713,68 +713,87 @@
     },
     {
         "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
-        "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1000000 / duration_time / 1000",
+        "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3",
         "MetricGroup": "HPC;Mem;MemoryBW;SoC",
         "MetricName": "DRAM_BW_Use"
     },
     {
         "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)",
-        "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
+        "MetricExpr": "MEM_Parallel_Requests",
         "MetricGroup": "Mem;SoC",
         "MetricName": "MEM_Request_Latency"
     },
     {
         "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests",
-        "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
+        "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL",
         "MetricGroup": "Mem;SoC",
         "MetricName": "MEM_Parallel_Requests"
     },
+    {
+        "BriefDescription": "Socket actual clocks when any core is active on that socket",
+        "MetricExpr": "UNC_CLOCK.SOCKET",
+        "MetricGroup": "SoC",
+        "MetricName": "Socket_CLKS"
+    },
     {
         "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
         "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
         "MetricGroup": "Branches;OS",
         "MetricName": "IpFarBranch"
     },
+    {
+        "BriefDescription": "Uncore frequency per die [GHZ]",
+        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+        "MetricGroup": "SoC",
+        "MetricName": "UNCORE_FREQ"
+    },
     {
         "BriefDescription": "C3 residency percent per core",
-        "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C3_Core_Residency"
+        "MetricName": "C3_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C6 residency percent per core",
-        "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C6_Core_Residency"
+        "MetricName": "C6_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C7 residency percent per core",
-        "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C7_Core_Residency"
+        "MetricName": "C7_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C2 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C2_Pkg_Residency"
+        "MetricName": "C2_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C3 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C3_Pkg_Residency"
+        "MetricName": "C3_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C6 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C6_Pkg_Residency"
+        "MetricName": "C6_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C7 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C7_Pkg_Residency"
+        "MetricName": "C7_Pkg_Residency",
+        "ScaleUnit": "100%"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/haswell/memory.json b/tools/perf/pmu-events/arch/x86/haswell/memory.json
index 9e5a1e0966d92..9fb63e1dab085 100644
--- a/tools/perf/pmu-events/arch/x86/haswell/memory.json
+++ b/tools/perf/pmu-events/arch/x86/haswell/memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED",
         "PEBS": "1",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC1",
         "SampleAfterValue": "2000003",
@@ -20,8 +16,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC2",
         "SampleAfterValue": "2000003",
@@ -29,8 +23,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC3",
         "SampleAfterValue": "2000003",
@@ -38,8 +30,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD65",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC4",
@@ -48,8 +38,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC5",
         "PublicDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts).",
@@ -58,8 +46,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution successfully committed.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.COMMIT",
         "SampleAfterValue": "2000003",
@@ -67,8 +53,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution started.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.START",
         "SampleAfterValue": "2000003",
@@ -76,8 +60,6 @@
     },
     {
         "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
         "PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline.  Machine clears can have a significant performance impact if they are happening frequently.",
@@ -86,8 +68,6 @@
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 128.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "HSD76, HSD25, HSM26",
         "EventCode": "0xcd",
@@ -96,13 +76,10 @@
         "MSRValue": "0x80",
         "PEBS": "2",
         "SampleAfterValue": "1009",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 16.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "HSD76, HSD25, HSM26",
         "EventCode": "0xcd",
@@ -111,13 +88,10 @@
         "MSRValue": "0x10",
         "PEBS": "2",
         "SampleAfterValue": "20011",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 256.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "HSD76, HSD25, HSM26",
         "EventCode": "0xcd",
@@ -126,13 +100,10 @@
         "MSRValue": "0x100",
         "PEBS": "2",
         "SampleAfterValue": "503",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 32.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "HSD76, HSD25, HSM26",
         "EventCode": "0xcd",
@@ -141,13 +112,10 @@
         "MSRValue": "0x20",
         "PEBS": "2",
         "SampleAfterValue": "100003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 4.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "HSD76, HSD25, HSM26",
         "EventCode": "0xcd",
@@ -156,13 +124,10 @@
         "MSRValue": "0x4",
         "PEBS": "2",
         "SampleAfterValue": "100003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 512.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "HSD76, HSD25, HSM26",
         "EventCode": "0xcd",
@@ -171,13 +136,10 @@
         "MSRValue": "0x200",
         "PEBS": "2",
         "SampleAfterValue": "101",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 64.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "HSD76, HSD25, HSM26",
         "EventCode": "0xcd",
@@ -186,13 +148,10 @@
         "MSRValue": "0x40",
         "PEBS": "2",
         "SampleAfterValue": "2003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 8.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "HSD76, HSD25, HSM26",
         "EventCode": "0xcd",
@@ -201,13 +160,10 @@
         "MSRValue": "0x8",
         "PEBS": "2",
         "SampleAfterValue": "50021",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x05",
         "EventName": "MISALIGN_MEM_REF.LOADS",
         "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.",
@@ -216,8 +172,6 @@
     },
     {
         "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x05",
         "EventName": "MISALIGN_MEM_REF.STORES",
         "PublicDescription": "Speculative cache-line split store-address uops dispatched to L1D.",
@@ -226,260 +180,195 @@
     },
     {
         "BriefDescription": "Counts all demand & prefetch code readsmiss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFFC00244",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch code readsmiss the L3 and the data is returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400244",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data readsmiss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFFC00091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data readsmiss the L3 and the data is returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFFC007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "miss the L3 and the data is returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all requestsmiss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFFC08FFF",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOsmiss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFFC00122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOsmiss the L3 and the data is returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code readsmiss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFFC00004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code readsmiss the L3 and the data is returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data readsmiss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFFC00001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data readsmiss the L3 and the data is returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFFC00002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)miss the L3 and the data is returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code readsmiss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFFC00040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data readsmiss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFFC00010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOsmiss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFFC00020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code readsmiss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFFC00200",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data readsmiss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFFC00080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOsmiss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFFC00100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED",
         "PEBS": "1",
@@ -488,8 +377,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC1",
         "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
@@ -498,8 +385,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC2",
         "SampleAfterValue": "2000003",
@@ -507,8 +392,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC3",
         "SampleAfterValue": "2000003",
@@ -516,8 +399,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "HSD65",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC4",
@@ -526,8 +407,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC5",
         "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
@@ -536,8 +415,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution successfully committed.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.COMMIT",
         "SampleAfterValue": "2000003",
@@ -545,8 +422,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution started.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.START",
         "SampleAfterValue": "2000003",
@@ -554,8 +429,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC1",
         "SampleAfterValue": "2000003",
@@ -563,8 +436,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC2",
         "SampleAfterValue": "2000003",
@@ -572,8 +443,6 @@
     },
     {
         "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC3",
         "SampleAfterValue": "2000003",
@@ -581,8 +450,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC4",
         "SampleAfterValue": "2000003",
@@ -590,8 +457,6 @@
     },
     {
         "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC5",
         "SampleAfterValue": "2000003",
@@ -599,8 +464,6 @@
     },
     {
         "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
         "SampleAfterValue": "2000003",
@@ -608,8 +471,6 @@
     },
     {
         "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CONFLICT",
         "SampleAfterValue": "2000003",
@@ -617,8 +478,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
         "SampleAfterValue": "2000003",
@@ -626,8 +485,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
         "SampleAfterValue": "2000003",
@@ -635,8 +492,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
         "SampleAfterValue": "2000003",
@@ -644,8 +499,6 @@
     },
     {
         "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
         "SampleAfterValue": "2000003",
@@ -653,8 +506,6 @@
     },
     {
         "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
         "SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/haswell/other.json b/tools/perf/pmu-events/arch/x86/haswell/other.json
index 7ca34f09b185e..2395ebf112db3 100644
--- a/tools/perf/pmu-events/arch/x86/haswell/other.json
+++ b/tools/perf/pmu-events/arch/x86/haswell/other.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5C",
         "EventName": "CPL_CYCLES.RING0",
         "PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5C",
@@ -22,8 +18,6 @@
     },
     {
         "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5C",
         "EventName": "CPL_CYCLES.RING123",
         "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
@@ -32,8 +26,6 @@
     },
     {
         "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x63",
         "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
         "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
diff --git a/tools/perf/pmu-events/arch/x86/haswell/pipeline.json b/tools/perf/pmu-events/arch/x86/haswell/pipeline.json
index 42f6a81006613..9ac36c1c24b66 100644
--- a/tools/perf/pmu-events/arch/x86/haswell/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/haswell/pipeline.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Any uop executed by the Divider. (This includes all divide uops, sqrt, ...)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x14",
         "EventName": "ARITH.DIVIDER_UOPS",
         "SampleAfterValue": "2000003",
@@ -10,8 +8,6 @@
     },
     {
         "BriefDescription": "Speculative and retired  branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_BRANCHES",
         "PublicDescription": "Counts all near executed branches (not necessarily retired).",
@@ -20,8 +16,6 @@
     },
     {
         "BriefDescription": "Speculative and retired macro-conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -29,8 +23,6 @@
     },
     {
         "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
         "SampleAfterValue": "200003",
@@ -38,8 +30,6 @@
     },
     {
         "BriefDescription": "Speculative and retired direct near calls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
         "SampleAfterValue": "200003",
@@ -47,8 +37,6 @@
     },
     {
         "BriefDescription": "Speculative and retired indirect branches excluding calls and returns.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
         "SampleAfterValue": "200003",
@@ -56,8 +44,6 @@
     },
     {
         "BriefDescription": "Speculative and retired indirect return branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
         "SampleAfterValue": "200003",
@@ -65,8 +51,6 @@
     },
     {
         "BriefDescription": "Not taken macro-conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -74,8 +58,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired macro-conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -83,8 +65,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
         "SampleAfterValue": "200003",
@@ -92,8 +72,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired direct near calls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
         "SampleAfterValue": "200003",
@@ -101,8 +79,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
         "SampleAfterValue": "200003",
@@ -110,8 +86,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect calls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
         "SampleAfterValue": "200003",
@@ -119,8 +93,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
         "SampleAfterValue": "200003",
@@ -128,8 +100,6 @@
     },
     {
         "BriefDescription": "All (macro) branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "PublicDescription": "Branch instructions at retirement.",
@@ -137,8 +107,6 @@
     },
     {
         "BriefDescription": "All (macro) branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
         "PEBS": "2",
@@ -147,8 +115,6 @@
     },
     {
         "BriefDescription": "Conditional branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -158,8 +124,6 @@
     },
     {
         "BriefDescription": "Far branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.FAR_BRANCH",
         "PublicDescription": "Number of far branches retired.",
@@ -168,8 +132,6 @@
     },
     {
         "BriefDescription": "Direct and indirect near call instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -178,8 +140,6 @@
     },
     {
         "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
         "PEBS": "1",
@@ -188,8 +148,6 @@
     },
     {
         "BriefDescription": "Return instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_RETURN",
         "PEBS": "1",
@@ -199,8 +157,6 @@
     },
     {
         "BriefDescription": "Taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
@@ -210,8 +166,6 @@
     },
     {
         "BriefDescription": "Not taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NOT_TAKEN",
         "PublicDescription": "Counts the number of not taken branch instructions retired.",
@@ -220,8 +174,6 @@
     },
     {
         "BriefDescription": "Speculative and retired mispredicted macro conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_BRANCHES",
         "PublicDescription": "Counts all near executed branches (not necessarily retired).",
@@ -230,8 +182,6 @@
     },
     {
         "BriefDescription": "Speculative and retired mispredicted macro conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -239,8 +189,6 @@
     },
     {
         "BriefDescription": "Mispredicted indirect branches excluding calls and returns.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
         "SampleAfterValue": "200003",
@@ -248,8 +196,6 @@
     },
     {
         "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -257,8 +203,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -266,8 +210,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
         "SampleAfterValue": "200003",
@@ -275,8 +217,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect calls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
         "SampleAfterValue": "200003",
@@ -284,8 +224,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
         "SampleAfterValue": "200003",
@@ -293,8 +231,6 @@
     },
     {
         "BriefDescription": "All mispredicted macro branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PublicDescription": "Mispredicted branch instructions at retirement.",
@@ -302,8 +238,6 @@
     },
     {
         "BriefDescription": "Mispredicted macro branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
         "PEBS": "2",
@@ -313,8 +247,6 @@
     },
     {
         "BriefDescription": "Mispredicted conditional branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -323,8 +255,6 @@
     },
     {
         "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
@@ -334,8 +264,6 @@
     },
     {
         "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "100003",
@@ -343,8 +271,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
         "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.",
@@ -354,8 +280,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
         "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
@@ -364,8 +288,6 @@
     },
     {
         "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "100003",
@@ -373,8 +295,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the core is not in halt state.",
-        "Counter": "Fixed counter 2",
-        "CounterHTOff": "Fixed counter 2",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
         "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state.",
         "SampleAfterValue": "2000003",
@@ -382,8 +302,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
         "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)",
@@ -393,8 +311,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
         "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
@@ -403,8 +319,6 @@
     },
     {
         "BriefDescription": "Core cycles when the thread is not in halt state.",
-        "Counter": "Fixed counter 1",
-        "CounterHTOff": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD",
         "PublicDescription": "This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.",
         "SampleAfterValue": "2000003",
@@ -413,16 +327,12 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
-        "Counter": "Fixed counter 1",
-        "CounterHTOff": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Thread cycles when thread is not in halt state",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
         "PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.",
@@ -431,16 +341,12 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Cycles with pending L1 cache miss loads.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "8",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
@@ -450,8 +356,6 @@
     },
     {
         "BriefDescription": "Cycles with pending L2 cache miss loads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "Errata": "HSD78, HSM63, HSM80",
         "EventCode": "0xa3",
@@ -462,8 +366,6 @@
     },
     {
         "BriefDescription": "Cycles with pending memory loads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
@@ -473,8 +375,6 @@
     },
     {
         "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
@@ -484,8 +384,6 @@
     },
     {
         "BriefDescription": "Execution stalls due to L1 data cache misses",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "12",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
@@ -495,8 +393,6 @@
     },
     {
         "BriefDescription": "Execution stalls due to L2 cache misses.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "5",
         "Errata": "HSM63, HSM80",
         "EventCode": "0xa3",
@@ -507,8 +403,6 @@
     },
     {
         "BriefDescription": "Execution stalls due to memory subsystem.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "6",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",
@@ -518,8 +412,6 @@
     },
     {
         "BriefDescription": "Stall cycles because IQ is full",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.IQ_FULL",
         "PublicDescription": "Stall cycles due to IQ is full.",
@@ -528,8 +420,6 @@
     },
     {
         "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.LCP",
         "PublicDescription": "This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP).",
@@ -538,8 +428,6 @@
     },
     {
         "BriefDescription": "Instructions retired from execution.",
-        "Counter": "Fixed counter 0",
-        "CounterHTOff": "Fixed counter 0",
         "Errata": "HSD140, HSD143",
         "EventName": "INST_RETIRED.ANY",
         "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
@@ -548,8 +436,6 @@
     },
     {
         "BriefDescription": "Number of instructions retired. General Counter   - architectural event",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD11, HSD140",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.ANY_P",
@@ -558,8 +444,6 @@
     },
     {
         "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
-        "Counter": "1",
-        "CounterHTOff": "1",
         "Errata": "HSD140",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.PREC_DIST",
@@ -570,8 +454,6 @@
     },
     {
         "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.X87",
         "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.",
@@ -580,8 +462,6 @@
     },
     {
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES",
@@ -592,8 +472,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
@@ -603,8 +481,6 @@
     },
     {
         "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.NO_SR",
         "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
@@ -613,8 +489,6 @@
     },
     {
         "BriefDescription": "loads blocked by overlapping with store buffer that cannot be forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.STORE_FORWARD",
         "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load.  The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issued.",
@@ -623,8 +497,6 @@
     },
     {
         "BriefDescription": "False dependencies in MOB due to partial compare on address.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x07",
         "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
         "PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K.  This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impact.",
@@ -633,8 +505,6 @@
     },
     {
         "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4c",
         "EventName": "LOAD_HIT_PRE.HW_PF",
         "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.",
@@ -643,8 +513,6 @@
     },
     {
         "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4c",
         "EventName": "LOAD_HIT_PRE.SW_PF",
         "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.",
@@ -653,8 +521,6 @@
     },
     {
         "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_4_UOPS",
@@ -663,8 +529,6 @@
     },
     {
         "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_ACTIVE",
@@ -673,8 +537,6 @@
     },
     {
         "BriefDescription": "Number of Uops delivered by the LSD.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa8",
         "EventName": "LSD.UOPS",
         "PublicDescription": "Number of uops delivered by the LSD.",
@@ -683,8 +545,6 @@
     },
     {
         "BriefDescription": "Number of machine clears (nukes) of any type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xC3",
@@ -694,8 +554,6 @@
     },
     {
         "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.CYCLES",
         "SampleAfterValue": "2000003",
@@ -703,8 +561,6 @@
     },
     {
         "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MASKMOV",
         "SampleAfterValue": "100003",
@@ -712,8 +568,6 @@
     },
     {
         "BriefDescription": "Self-modifying code (SMC) detected.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.SMC",
         "PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear.  Machine clears can have a significant performance impact if they are happening frequently.",
@@ -722,8 +576,6 @@
     },
     {
         "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.INT_ELIMINATED",
         "PublicDescription": "Number of integer move elimination candidate uops that were eliminated.",
@@ -732,8 +584,6 @@
     },
     {
         "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",
         "PublicDescription": "Number of integer move elimination candidate uops that were not eliminated.",
@@ -742,8 +592,6 @@
     },
     {
         "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",
         "PublicDescription": "Number of microcode assists invoked by HW upon uop writeback.",
@@ -752,8 +600,6 @@
     },
     {
         "BriefDescription": "Resource-related stall cycles",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD135",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ANY",
@@ -763,8 +609,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to re-order buffer full.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ROB",
         "SampleAfterValue": "2000003",
@@ -772,8 +616,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no eligible RS entry available.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.RS",
         "SampleAfterValue": "2000003",
@@ -781,8 +623,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.SB",
         "PublicDescription": "This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were available.",
@@ -791,8 +631,6 @@
     },
     {
         "BriefDescription": "Count cases of saving new LBR",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCC",
         "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
         "PublicDescription": "Count cases of saving new LBR records by hardware.",
@@ -801,8 +639,6 @@
     },
     {
         "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5E",
         "EventName": "RS_EVENTS.EMPTY_CYCLES",
         "PublicDescription": "This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-end.",
@@ -811,8 +647,6 @@
     },
     {
         "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5E",
@@ -823,8 +657,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_0",
         "SampleAfterValue": "2000003",
@@ -832,8 +664,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 1.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_1",
         "SampleAfterValue": "2000003",
@@ -841,8 +671,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_2",
         "SampleAfterValue": "2000003",
@@ -850,8 +678,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_3",
         "SampleAfterValue": "2000003",
@@ -859,8 +685,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 4.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_4",
         "SampleAfterValue": "2000003",
@@ -868,8 +692,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 5.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_5",
         "SampleAfterValue": "2000003",
@@ -877,8 +699,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 6.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_6",
         "SampleAfterValue": "2000003",
@@ -886,8 +706,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 7.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_7",
         "SampleAfterValue": "2000003",
@@ -895,8 +713,6 @@
     },
     {
         "BriefDescription": "Number of uops executed on the core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD30, HSM31",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE",
@@ -906,8 +722,6 @@
     },
     {
         "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "Errata": "HSD30, HSM31",
         "EventCode": "0xb1",
@@ -917,8 +731,6 @@
     },
     {
         "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "Errata": "HSD30, HSM31",
         "EventCode": "0xb1",
@@ -928,8 +740,6 @@
     },
     {
         "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "Errata": "HSD30, HSM31",
         "EventCode": "0xb1",
@@ -939,8 +749,6 @@
     },
     {
         "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "Errata": "HSD30, HSM31",
         "EventCode": "0xb1",
@@ -950,8 +758,6 @@
     },
     {
         "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD30, HSM31",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
@@ -961,8 +767,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "Errata": "HSD144, HSD30, HSM31",
         "EventCode": "0xB1",
@@ -973,8 +777,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "2",
         "Errata": "HSD144, HSD30, HSM31",
         "EventCode": "0xB1",
@@ -985,8 +787,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "3",
         "Errata": "HSD144, HSD30, HSM31",
         "EventCode": "0xB1",
@@ -997,8 +797,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 4 uops were executed per-thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "Errata": "HSD144, HSD30, HSM31",
         "EventCode": "0xB1",
@@ -1008,8 +806,6 @@
     },
     {
         "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "Errata": "HSD144, HSD30, HSM31",
         "EventCode": "0xB1",
@@ -1020,8 +816,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_0",
         "PublicDescription": "Cycles which a uop is dispatched on port 0 in this thread.",
@@ -1031,8 +825,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are executed in port 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE",
         "SampleAfterValue": "2000003",
@@ -1040,8 +832,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 1",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_1",
         "PublicDescription": "Cycles which a uop is dispatched on port 1 in this thread.",
@@ -1051,8 +841,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are executed in port 1.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE",
         "SampleAfterValue": "2000003",
@@ -1060,8 +848,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_2",
         "PublicDescription": "Cycles which a uop is dispatched on port 2 in this thread.",
@@ -1071,8 +857,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE",
         "SampleAfterValue": "2000003",
@@ -1080,8 +864,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_3",
         "PublicDescription": "Cycles which a uop is dispatched on port 3 in this thread.",
@@ -1091,8 +873,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE",
         "SampleAfterValue": "2000003",
@@ -1100,8 +880,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 4",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_4",
         "PublicDescription": "Cycles which a uop is dispatched on port 4 in this thread.",
@@ -1111,8 +889,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are executed in port 4.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE",
         "SampleAfterValue": "2000003",
@@ -1120,8 +896,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 5",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_5",
         "PublicDescription": "Cycles which a uop is dispatched on port 5 in this thread.",
@@ -1131,8 +905,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are executed in port 5.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE",
         "SampleAfterValue": "2000003",
@@ -1140,8 +912,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 6",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_6",
         "PublicDescription": "Cycles which a uop is dispatched on port 6 in this thread.",
@@ -1151,8 +921,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are executed in port 6.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE",
         "SampleAfterValue": "2000003",
@@ -1160,8 +928,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 7",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_7",
         "PublicDescription": "Cycles which a uop is dispatched on port 7 in this thread.",
@@ -1171,8 +937,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 7.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE",
         "SampleAfterValue": "2000003",
@@ -1180,8 +944,6 @@
     },
     {
         "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.ANY",
         "PublicDescription": "This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uops.",
@@ -1191,8 +953,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -1202,8 +962,6 @@
     },
     {
         "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.FLAGS_MERGE",
         "PublicDescription": "Number of flags-merge uops allocated. Such uops add delay.",
@@ -1212,8 +970,6 @@
     },
     {
         "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.SINGLE_MUL",
         "PublicDescription": "Number of multiply packed/scalar single precision uops allocated.",
@@ -1222,8 +978,6 @@
     },
     {
         "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.SLOW_LEA",
         "PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (for example, 2 sources + immediate) regardless of whether it is a result of LEA instruction or not.",
@@ -1232,8 +986,6 @@
     },
     {
         "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -1243,8 +995,6 @@
     },
     {
         "BriefDescription": "Actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ALL",
         "PEBS": "1",
@@ -1255,8 +1005,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles without actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",
@@ -1266,8 +1014,6 @@
     },
     {
         "BriefDescription": "Retirement slots used.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
         "PEBS": "1",
@@ -1277,8 +1023,6 @@
     },
     {
         "BriefDescription": "Cycles without actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -1288,8 +1032,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 10 actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "16",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json b/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json
index 6b0639944d78f..c538557ba4c09 100644
--- a/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json
@@ -1,251 +1,201 @@
 [
     {
         "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
         "UMask": "0x86",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
         "UMask": "0x88",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
         "UMask": "0x81",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
         "UMask": "0x8f",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
         "UMask": "0x46",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
         "UMask": "0x48",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
         "UMask": "0x41",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
         "UMask": "0x4f",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
         "UMask": "0x16",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup read request that access cache and found line in I-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",
         "UMask": "0x18",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup read request that access cache and found line in M-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup read request that access cache and found line in M-state.",
         "UMask": "0x11",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
         "UMask": "0x1f",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
         "UMask": "0x26",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup write request that access cache and found line in I-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup write request that access cache and found line in I-state.",
         "UMask": "0x28",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup write request that access cache and found line in M-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",
         "UMask": "0x21",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
         "UMask": "0x2f",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
         "UMask": "0x88",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "An external snoop hits a modified line in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL",
         "PerPkg": "1",
-        "PublicDescription": "An external snoop hits a modified line in some processor core.",
         "UMask": "0x28",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
         "UMask": "0x48",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
         "UMask": "0x84",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "An external snoop hits a non-modified line in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL",
         "PerPkg": "1",
-        "PublicDescription": "An external snoop hits a non-modified line in some processor core.",
         "UMask": "0x24",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
         "UMask": "0x44",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
         "UMask": "0x81",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "An external snoop misses in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL",
         "PerPkg": "1",
-        "PublicDescription": "An external snoop misses in some processor core.",
         "UMask": "0x21",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
         "UMask": "0x41",
         "Unit": "CBO"
     }
diff --git a/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json b/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json
index 56c4b380dc959..84cc2536de69a 100644
--- a/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json
@@ -5,17 +5,15 @@
         "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.All",
         "PerPkg": "1",
         "PublicDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory).",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
-        "Counter": "0,1",
         "EventCode": "0x84",
         "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
         "PerPkg": "1",
-        "PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
@@ -23,48 +21,39 @@
         "EventCode": "0x80",
         "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "PublicDescription": "Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
-        "Counter": "0,",
         "CounterMask": "1",
         "EventCode": "0x80",
         "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
         "PerPkg": "1",
-        "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.\n",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
-        "Counter": "0,1",
         "EventCode": "0x81",
         "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
         "PerPkg": "1",
-        "PublicDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
-        "Counter": "0,1",
         "EventCode": "0x81",
         "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
         "PerPkg": "1",
-        "PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
         "UMask": "0x20",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
-        "Counter": "FIXED",
         "EventCode": "0xff",
         "EventName": "UNC_CLOCK.SOCKET",
         "PerPkg": "1",
-        "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
         "Unit": "CLOCK"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json b/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json
index 57d2a6452fecf..87a4ec1ee7d71 100644
--- a/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Load misses in all DTLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
         "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS",
         "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
         "PublicDescription": "Number of cache load STLB hits. No page walk.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (2M)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
         "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
@@ -41,8 +33,6 @@
     },
     {
         "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (4K)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
         "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
@@ -51,8 +41,6 @@
     },
     {
         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
         "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.",
@@ -61,8 +49,6 @@
     },
     {
         "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
         "SampleAfterValue": "2000003",
@@ -70,8 +56,6 @@
     },
     {
         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
         "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.",
@@ -80,8 +64,6 @@
     },
     {
         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
         "PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.",
@@ -90,8 +72,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
         "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
@@ -100,8 +80,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
         "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
@@ -110,8 +88,6 @@
     },
     {
         "BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS",
         "PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.",
@@ -120,8 +96,6 @@
     },
     {
         "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT",
         "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
@@ -130,8 +104,6 @@
     },
     {
         "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (2M)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
         "PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
@@ -140,8 +112,6 @@
     },
     {
         "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (4K)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
         "PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
@@ -150,8 +120,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
         "PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).",
@@ -160,8 +128,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
         "SampleAfterValue": "100003",
@@ -169,8 +135,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
         "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.",
@@ -179,8 +143,6 @@
     },
     {
         "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
         "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.",
@@ -189,8 +151,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_DURATION",
         "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB store misses.",
@@ -199,8 +159,6 @@
     },
     {
         "BriefDescription": "Cycle count for an Extended Page table walk.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4f",
         "EventName": "EPT.WALK_CYCLES",
         "SampleAfterValue": "2000003",
@@ -208,8 +166,6 @@
     },
     {
         "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xae",
         "EventName": "ITLB.ITLB_FLUSH",
         "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.",
@@ -218,8 +174,6 @@
     },
     {
         "BriefDescription": "Misses at all ITLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
         "PublicDescription": "Misses in ITLB that causes a page walk of any page size.",
@@ -228,8 +182,6 @@
     },
     {
         "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT",
         "PublicDescription": "ITLB misses that hit STLB. No page walk.",
@@ -238,8 +190,6 @@
     },
     {
         "BriefDescription": "Code misses that miss the  DTLB and hit the STLB (2M)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT_2M",
         "PublicDescription": "ITLB misses that hit STLB (2M).",
@@ -248,8 +198,6 @@
     },
     {
         "BriefDescription": "Core misses that miss the  DTLB and hit the STLB (4K)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT_4K",
         "PublicDescription": "ITLB misses that hit STLB (4K).",
@@ -258,8 +206,6 @@
     },
     {
         "BriefDescription": "Misses in all ITLB levels that cause completed page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
         "PublicDescription": "Completed page walks in ITLB of any page size.",
@@ -268,8 +214,6 @@
     },
     {
         "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
         "SampleAfterValue": "100003",
@@ -277,8 +221,6 @@
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
         "PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.",
@@ -287,8 +229,6 @@
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
         "PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.",
@@ -297,8 +237,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_DURATION",
         "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by ITLB misses.",
@@ -307,8 +245,6 @@
     },
     {
         "BriefDescription": "Number of DTLB page walker hits in the L1+FB",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.DTLB_L1",
         "PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.",
@@ -317,8 +253,6 @@
     },
     {
         "BriefDescription": "Number of DTLB page walker hits in the L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.DTLB_L2",
         "PublicDescription": "Number of DTLB page walker loads that hit in the L2.",
@@ -327,8 +261,6 @@
     },
     {
         "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "HSD25",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.DTLB_L3",
@@ -338,8 +270,6 @@
     },
     {
         "BriefDescription": "Number of DTLB page walker hits in Memory",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "HSD25",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
@@ -349,8 +279,6 @@
     },
     {
         "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1",
         "SampleAfterValue": "2000003",
@@ -358,8 +286,6 @@
     },
     {
         "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2",
         "SampleAfterValue": "2000003",
@@ -367,8 +293,6 @@
     },
     {
         "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3",
         "SampleAfterValue": "2000003",
@@ -376,8 +300,6 @@
     },
     {
         "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY",
         "SampleAfterValue": "2000003",
@@ -385,8 +307,6 @@
     },
     {
         "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1",
         "SampleAfterValue": "2000003",
@@ -394,8 +314,6 @@
     },
     {
         "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2",
         "SampleAfterValue": "2000003",
@@ -403,8 +321,6 @@
     },
     {
         "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3",
         "SampleAfterValue": "2000003",
@@ -412,8 +328,6 @@
     },
     {
         "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY",
         "SampleAfterValue": "2000003",
@@ -421,8 +335,6 @@
     },
     {
         "BriefDescription": "Number of ITLB page walker hits in the L1+FB",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.ITLB_L1",
         "PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.",
@@ -431,8 +343,6 @@
     },
     {
         "BriefDescription": "Number of ITLB page walker hits in the L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.ITLB_L2",
         "PublicDescription": "Number of ITLB page walker loads that hit in the L2.",
@@ -441,8 +351,6 @@
     },
     {
         "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "HSD25",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.ITLB_L3",
@@ -452,8 +360,6 @@
     },
     {
         "BriefDescription": "Number of ITLB page walker hits in Memory",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "HSD25",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY",
@@ -463,8 +369,6 @@
     },
     {
         "BriefDescription": "DTLB flush attempts of the thread-specific entries",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.DTLB_THREAD",
         "PublicDescription": "DTLB flush attempts of the thread-specific entries.",
@@ -473,8 +377,6 @@
     },
     {
         "BriefDescription": "STLB flush attempts",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.STLB_ANY",
         "PublicDescription": "Count number of STLB flush attempts.",
-- 
GitLab


From 667433c4eb847731ce92af6894ffb095123eff30 Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:54:51 -0800
Subject: [PATCH 575/875] perf vendor events intel: Refresh haswellx metrics
 and events

Update the haswellx metrics and events using the new tooling from:

  https://github.com/intel/perfmon

The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
order of metrics varies as TMA metrics are first converted and then
removed if perfmon versions are found. The events are updated with
fixes to uncore events and improved descriptions. The formatting
changes increase consistency across the json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-5-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../pmu-events/arch/x86/haswellx/cache.json   |  217 --
 .../arch/x86/haswellx/floating-point.json     |   20 -
 .../arch/x86/haswellx/frontend.json           |   58 -
 .../arch/x86/haswellx/hsx-metrics.json        | 1467 +++++-----
 .../pmu-events/arch/x86/haswellx/memory.json  |  170 --
 .../pmu-events/arch/x86/haswellx/other.json   |    8 -
 .../arch/x86/haswellx/pipeline.json           |  258 --
 .../arch/x86/haswellx/uncore-cache.json       | 2448 ++++++++---------
 .../x86/haswellx/uncore-interconnect.json     |  722 ++---
 .../arch/x86/haswellx/uncore-memory.json      | 2037 +++++++-------
 .../arch/x86/haswellx/uncore-other.json       | 1834 ++++++------
 .../arch/x86/haswellx/uncore-power.json       |  150 +-
 .../arch/x86/haswellx/virtual-memory.json     |   98 -
 13 files changed, 4206 insertions(+), 5281 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/haswellx/cache.json b/tools/perf/pmu-events/arch/x86/haswellx/cache.json
index 427c949bed6ed..1836ed62694e4 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/cache.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/cache.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "L1D data line replacements",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x51",
         "EventName": "L1D.REPLACEMENT",
         "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.FB_FULL",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "L1D miss outstanding duration in cycles",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING",
         "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Cycles with L1D load Misses outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -42,8 +34,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -52,8 +42,6 @@
     },
     {
         "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL",
         "SampleAfterValue": "2000003",
@@ -61,8 +49,6 @@
     },
     {
         "BriefDescription": "Not rejected writebacks that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x27",
         "EventName": "L2_DEMAND_RQSTS.WB_HIT",
         "PublicDescription": "Not rejected writebacks that hit L2 cache.",
@@ -71,8 +57,6 @@
     },
     {
         "BriefDescription": "L2 cache lines filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.ALL",
         "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache.  Lines are filled into the L2 cache when there was an L2 miss.",
@@ -81,8 +65,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in E state filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.E",
         "PublicDescription": "L2 cache lines in E state filling L2.",
@@ -91,8 +73,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in I state filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.I",
         "PublicDescription": "L2 cache lines in I state filling L2.",
@@ -101,8 +81,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in S state filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.S",
         "PublicDescription": "L2 cache lines in S state filling L2.",
@@ -111,8 +89,6 @@
     },
     {
         "BriefDescription": "Clean L2 cache lines evicted by demand",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
         "PublicDescription": "Clean L2 cache lines evicted by demand.",
@@ -121,8 +97,6 @@
     },
     {
         "BriefDescription": "Dirty L2 cache lines evicted by demand",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
         "PublicDescription": "Dirty L2 cache lines evicted by demand.",
@@ -131,8 +105,6 @@
     },
     {
         "BriefDescription": "L2 code requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_CODE_RD",
         "PublicDescription": "Counts all L2 code requests.",
@@ -141,8 +113,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD78, HSM80",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
@@ -152,8 +122,6 @@
     },
     {
         "BriefDescription": "Demand requests that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD78, HSM80",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
@@ -163,8 +131,6 @@
     },
     {
         "BriefDescription": "Demand requests to L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD78, HSM80",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
@@ -174,8 +140,6 @@
     },
     {
         "BriefDescription": "Requests from L2 hardware prefetchers",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_PF",
         "PublicDescription": "Counts all L2 HW prefetcher requests.",
@@ -184,8 +148,6 @@
     },
     {
         "BriefDescription": "RFO requests to L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_RFO",
         "PublicDescription": "Counts all L2 store RFO requests.",
@@ -194,8 +156,6 @@
     },
     {
         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_HIT",
         "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
@@ -204,8 +164,6 @@
     },
     {
         "BriefDescription": "L2 cache misses when fetching instructions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_MISS",
         "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
@@ -214,8 +172,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD78, HSM80",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
@@ -225,8 +181,6 @@
     },
     {
         "BriefDescription": "Demand Data Read miss L2, no rejects",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD78, HSM80",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
@@ -236,8 +190,6 @@
     },
     {
         "BriefDescription": "L2 prefetch requests that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.L2_PF_HIT",
         "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
@@ -246,8 +198,6 @@
     },
     {
         "BriefDescription": "L2 prefetch requests that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.L2_PF_MISS",
         "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
@@ -256,8 +206,6 @@
     },
     {
         "BriefDescription": "All requests that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD78, HSM80",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.MISS",
@@ -267,8 +215,6 @@
     },
     {
         "BriefDescription": "All L2 requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD78, HSM80",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.REFERENCES",
@@ -278,8 +224,6 @@
     },
     {
         "BriefDescription": "RFO requests that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_HIT",
         "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.",
@@ -288,8 +232,6 @@
     },
     {
         "BriefDescription": "RFO requests that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_MISS",
         "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
@@ -298,8 +240,6 @@
     },
     {
         "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xf0",
         "EventName": "L2_TRANS.ALL_PF",
         "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.",
@@ -308,8 +248,6 @@
     },
     {
         "BriefDescription": "Transactions accessing L2 pipe",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xf0",
         "EventName": "L2_TRANS.ALL_REQUESTS",
         "PublicDescription": "Transactions accessing L2 pipe.",
@@ -318,8 +256,6 @@
     },
     {
         "BriefDescription": "L2 cache accesses when fetching instructions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xf0",
         "EventName": "L2_TRANS.CODE_RD",
         "PublicDescription": "L2 cache accesses when fetching instructions.",
@@ -328,8 +264,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xf0",
         "EventName": "L2_TRANS.DEMAND_DATA_RD",
         "PublicDescription": "Demand data read requests that access L2 cache.",
@@ -338,8 +272,6 @@
     },
     {
         "BriefDescription": "L1D writebacks that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xf0",
         "EventName": "L2_TRANS.L1D_WB",
         "PublicDescription": "L1D writebacks that access L2 cache.",
@@ -348,8 +280,6 @@
     },
     {
         "BriefDescription": "L2 fill requests that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xf0",
         "EventName": "L2_TRANS.L2_FILL",
         "PublicDescription": "L2 fill requests that access L2 cache.",
@@ -358,8 +288,6 @@
     },
     {
         "BriefDescription": "L2 writebacks that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xf0",
         "EventName": "L2_TRANS.L2_WB",
         "PublicDescription": "L2 writebacks that access L2 cache.",
@@ -368,8 +296,6 @@
     },
     {
         "BriefDescription": "RFO requests that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xf0",
         "EventName": "L2_TRANS.RFO",
         "PublicDescription": "RFO requests that access L2 cache.",
@@ -378,8 +304,6 @@
     },
     {
         "BriefDescription": "Cycles when L1D is locked",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x63",
         "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
         "PublicDescription": "Cycles in which the L1D is locked.",
@@ -388,8 +312,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests missed L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.MISS",
         "PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
@@ -398,8 +320,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
         "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
@@ -408,8 +328,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD29, HSD25, HSM26, HSM30",
         "EventCode": "0xD2",
@@ -420,8 +338,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD29, HSD25, HSM26, HSM30",
         "EventCode": "0xD2",
@@ -432,8 +348,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD29, HSD25, HSM26, HSM30",
         "EventCode": "0xD2",
@@ -444,8 +358,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
         "EventCode": "0xD2",
@@ -456,8 +368,6 @@
     },
     {
         "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD74, HSD29, HSD25, HSM30",
         "EventCode": "0xD3",
@@ -469,8 +379,6 @@
     },
     {
         "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD29, HSM30",
         "EventCode": "0xD3",
@@ -481,8 +389,6 @@
     },
     {
         "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSM30",
         "EventCode": "0xD3",
@@ -493,8 +399,6 @@
     },
     {
         "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSM30",
         "EventCode": "0xD3",
@@ -505,8 +409,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSM30",
         "EventCode": "0xD1",
@@ -517,8 +419,6 @@
     },
     {
         "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD29, HSM30",
         "EventCode": "0xD1",
@@ -529,8 +429,6 @@
     },
     {
         "BriefDescription": "Retired load uops misses in L1 cache as data sources.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSM30",
         "EventCode": "0xD1",
@@ -542,8 +440,6 @@
     },
     {
         "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD76, HSD29, HSM30",
         "EventCode": "0xD1",
@@ -554,8 +450,6 @@
     },
     {
         "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD29, HSM30",
         "EventCode": "0xD1",
@@ -567,8 +461,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
         "EventCode": "0xD1",
@@ -580,8 +472,6 @@
     },
     {
         "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
         "EventCode": "0xD1",
@@ -593,8 +483,6 @@
     },
     {
         "BriefDescription": "Retired load uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD29, HSM30",
         "EventCode": "0xD0",
@@ -606,13 +494,10 @@
     },
     {
         "BriefDescription": "Retired store uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD29, HSM30",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "PublicDescription": "Counts all retired store uops.",
         "SampleAfterValue": "2000003",
@@ -620,8 +505,6 @@
     },
     {
         "BriefDescription": "Retired load uops with locked access.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD76, HSD29, HSM30",
         "EventCode": "0xD0",
@@ -632,8 +515,6 @@
     },
     {
         "BriefDescription": "Retired load uops that split across a cacheline boundary.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD29, HSM30",
         "EventCode": "0xD0",
@@ -644,21 +525,16 @@
     },
     {
         "BriefDescription": "Retired store uops that split across a cacheline boundary.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD29, HSM30",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x42"
     },
     {
         "BriefDescription": "Retired load uops that miss the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD29, HSM30",
         "EventCode": "0xD0",
@@ -669,21 +545,16 @@
     },
     {
         "BriefDescription": "Retired store uops that miss the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "Errata": "HSD29, HSM30",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x12"
     },
     {
         "BriefDescription": "Demand and prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
         "PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
@@ -692,8 +563,6 @@
     },
     {
         "BriefDescription": "Cacheable and noncacheable code read requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
         "PublicDescription": "Demand code read requests sent to uncore.",
@@ -702,8 +571,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests sent to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD78, HSM80",
         "EventCode": "0xb0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
@@ -713,8 +580,6 @@
     },
     {
         "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
         "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
@@ -723,8 +588,6 @@
     },
     {
         "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb2",
         "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
         "SampleAfterValue": "2000003",
@@ -732,8 +595,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD62, HSD61, HSM63",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
@@ -743,8 +604,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "Errata": "HSD62, HSD61, HSM63",
         "EventCode": "0x60",
@@ -754,8 +613,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
         "EventCode": "0x60",
@@ -765,8 +622,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "Errata": "HSD62, HSD61, HSM63",
         "EventCode": "0x60",
@@ -776,8 +631,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD62, HSD61, HSM63",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
@@ -787,8 +640,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
@@ -798,8 +649,6 @@
     },
     {
         "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "6",
         "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
         "EventCode": "0x60",
@@ -809,8 +658,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD62, HSD61, HSM63",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
@@ -820,8 +667,6 @@
     },
     {
         "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE",
         "SampleAfterValue": "100003",
@@ -829,248 +674,186 @@
     },
     {
         "BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0244",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C07F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C07F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all requests hit in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C8FFF",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0200",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Split locks in SQ",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xf4",
         "EventName": "SQ_MISC.SPLIT_LOCK",
         "SampleAfterValue": "100003",
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json b/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json
index 7cf203a90a749..8fcc10f74ad99 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores.  May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC6",
         "EventName": "AVX_INSTS.ALL",
         "PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Cycles with any input/output SSE or FP assist",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.ANY",
@@ -22,8 +18,6 @@
     },
     {
         "BriefDescription": "Number of SIMD FP assists due to input values",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.SIMD_INPUT",
         "PublicDescription": "Number of SIMD FP assists due to input values.",
@@ -32,8 +26,6 @@
     },
     {
         "BriefDescription": "Number of SIMD FP assists due to Output values",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.SIMD_OUTPUT",
         "PublicDescription": "Number of SIMD FP assists due to output values.",
@@ -42,8 +34,6 @@
     },
     {
         "BriefDescription": "Number of X87 assists due to input value.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.X87_INPUT",
         "PublicDescription": "Number of X87 FP assists due to input values.",
@@ -52,8 +42,6 @@
     },
     {
         "BriefDescription": "Number of X87 assists due to output value.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.X87_OUTPUT",
         "PublicDescription": "Number of X87 FP assists due to output values.",
@@ -62,8 +50,6 @@
     },
     {
         "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
         "PublicDescription": "Number of SIMD move elimination candidate uops that were eliminated.",
@@ -72,8 +58,6 @@
     },
     {
         "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
         "PublicDescription": "Number of SIMD move elimination candidate uops that were not eliminated.",
@@ -82,8 +66,6 @@
     },
     {
         "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD56, HSM57",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.AVX_TO_SSE",
@@ -92,8 +74,6 @@
     },
     {
         "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD56, HSM57",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.SSE_TO_AVX",
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/frontend.json b/tools/perf/pmu-events/arch/x86/haswellx/frontend.json
index 18a993297108c..73d6d681dfa71 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/frontend.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xe6",
         "EventName": "BACLEARS.ANY",
         "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAB",
         "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
         "SampleAfterValue": "2000003",
@@ -20,8 +16,6 @@
     },
     {
         "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.HIT",
         "SampleAfterValue": "2000003",
@@ -29,8 +23,6 @@
     },
     {
         "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.IFDATA_STALL",
         "SampleAfterValue": "2000003",
@@ -38,8 +30,6 @@
     },
     {
         "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.IFETCH_STALL",
         "SampleAfterValue": "2000003",
@@ -47,8 +37,6 @@
     },
     {
         "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.MISSES",
         "PublicDescription": "This event counts Instruction Cache (ICACHE) misses.",
@@ -57,8 +45,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -68,8 +54,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -79,8 +63,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering 4 Uops",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -90,8 +72,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering any Uop",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -101,8 +81,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_CYCLES",
@@ -111,8 +89,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_UOPS",
         "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
@@ -121,8 +97,6 @@
     },
     {
         "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "HSD135",
         "EventCode": "0x79",
         "EventName": "IDQ.EMPTY",
@@ -132,8 +106,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_ALL_UOPS",
         "PublicDescription": "Number of uops delivered to IDQ from any path.",
@@ -142,8 +114,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_CYCLES",
@@ -152,8 +122,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_UOPS",
         "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",
@@ -162,8 +130,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_CYCLES",
@@ -173,8 +139,6 @@
     },
     {
         "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_DSB_CYCLES",
@@ -183,8 +147,6 @@
     },
     {
         "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
@@ -194,8 +156,6 @@
     },
     {
         "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_DSB_UOPS",
         "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
@@ -204,8 +164,6 @@
     },
     {
         "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_MITE_UOPS",
         "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
@@ -214,8 +172,6 @@
     },
     {
         "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
@@ -225,8 +181,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_UOPS",
         "PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the microcode sequencer.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance.",
@@ -235,8 +189,6 @@
     },
     {
         "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "HSD135",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
@@ -246,8 +198,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "Errata": "HSD135",
         "EventCode": "0x9C",
@@ -258,8 +208,6 @@
     },
     {
         "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "Errata": "HSD135",
         "EventCode": "0x9C",
@@ -270,8 +218,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "3",
         "Errata": "HSD135",
         "EventCode": "0x9C",
@@ -281,8 +227,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "2",
         "Errata": "HSD135",
         "EventCode": "0x9C",
@@ -292,8 +236,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "Errata": "HSD135",
         "EventCode": "0x9C",
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json b/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json
index 2cd86750986af..2e1fbc936d259 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json
@@ -1,1040 +1,1023 @@
 [
     {
-        "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
-        "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS",
-        "MetricGroup": "PGO;TopdownL1;tma_L1_group",
-        "MetricName": "tma_frontend_bound",
-        "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
+        "MetricExpr": "INST_RETIRED.ANY / CLKS",
+        "MetricGroup": "Ret;Summary",
+        "MetricName": "IPC"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
-        "MetricExpr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / SLOTS",
-        "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
-        "MetricName": "tma_fetch_latency",
-        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Uops Per Instruction",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
+        "MetricGroup": "Pipeline;Ret;Retire",
+        "MetricName": "UPI"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.",
-        "MetricExpr": "ICACHE.IFDATA_STALL / CLKS",
-        "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_icache_misses",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instruction per taken branch",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
+        "MetricGroup": "Branches;Fed;FetchBW",
+        "MetricName": "UpTB"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses",
-        "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / CLKS",
-        "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_itlb_misses",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
+        "MetricExpr": "1 / IPC",
+        "MetricGroup": "Mem;Pipeline",
+        "MetricName": "CPI"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
-        "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / CLKS",
-        "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_branch_resteers",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "Pipeline",
+        "MetricName": "CLKS"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
-        "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS",
-        "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_dsb_switches",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
+        "MetricExpr": "4 * CORE_CLKS",
+        "MetricGroup": "tma_L1_group",
+        "MetricName": "SLOTS"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
-        "MetricExpr": "ILD_STALL.LCP / CLKS",
-        "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_lcp",
-        "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
+        "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
+        "MetricGroup": "Ret;SMT;tma_L1_group",
+        "MetricName": "CoreIPC"
     },
     {
-        "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
-        "MetricExpr": "2 * IDQ.MS_SWITCHES / CLKS",
-        "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_ms_switches",
-        "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
+        "MetricExpr": "(UOPS_EXECUTED.CORE / 2 / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@) if #SMT_on else UOPS_EXECUTED.CORE / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@))",
+        "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
+        "MetricName": "ILP"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
-        "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
-        "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
-        "MetricName": "tma_fetch_bandwidth",
-        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues.  For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
+        "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
+        "MetricGroup": "SMT",
+        "MetricName": "CORE_CLKS"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
-        "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
-        "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
-        "MetricName": "tma_mite",
-        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
+        "MetricGroup": "InsType",
+        "MetricName": "IpLoad"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
-        "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2",
-        "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
-        "MetricName": "tma_dsb",
-        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline.  For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
+        "MetricGroup": "InsType",
+        "MetricName": "IpStore"
     },
     {
-        "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
-        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
-        "MetricGroup": "TopdownL1;tma_L1_group",
-        "MetricName": "tma_bad_speculation",
-        "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Branches;Fed;InsType",
+        "MetricName": "IpBranch"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
-        "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
-        "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
-        "MetricName": "tma_branch_mispredicts",
-        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
+        "MetricGroup": "Branches;Fed;PGO",
+        "MetricName": "IpCall"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
-        "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
-        "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group",
-        "MetricName": "tma_machine_clears",
-        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears.  These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instruction per taken branch",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
+        "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
+        "MetricName": "IpTB"
     },
     {
-        "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
-        "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)",
-        "MetricGroup": "TopdownL1;tma_L1_group",
-        "MetricName": "tma_backend_bound",
-        "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Branch instructions per taken branch. ",
+        "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
+        "MetricGroup": "Branches;Fed;PGO",
+        "MetricName": "BpTkBranch"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
-        "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB)) * tma_backend_bound",
-        "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
-        "MetricName": "tma_memory_bound",
-        "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
+        "MetricExpr": "INST_RETIRED.ANY",
+        "MetricGroup": "Summary;tma_L1_group",
+        "MetricName": "Instructions"
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
-        "MetricExpr": "max((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) - CYCLE_ACTIVITY.STALLS_L1D_PENDING) / CLKS, 0)",
-        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_l1_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache.  The L1 data cache typically has the shortest latency.  However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT_PS;MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
+        "MetricGroup": "Pipeline;Ret",
+        "MetricName": "Retire"
     },
     {
-        "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
-        "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / CLKS",
-        "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_dtlb_load",
-        "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
+        "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
+        "MetricGroup": "DSB;Fed;FetchBW",
+        "MetricName": "DSB_Coverage"
     },
     {
-        "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
-        "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS",
-        "MetricGroup": "TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_store_fwd_blk",
-        "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;BadSpec;BrMispredicts",
+        "MetricName": "IpMispredict"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
-        "MetricExpr": "(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
-        "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_lock_latency",
-        "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
+        "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)",
+        "MetricGroup": "Mem;MemoryBound;MemoryLat",
+        "MetricName": "Load_Miss_Real_Latency"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary",
-        "MetricExpr": "Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS",
-        "MetricGroup": "TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_split_loads",
-        "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary.  Sample with: MEM_UOPS_RETIRED.SPLIT_LOADS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
+        "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
+        "MetricGroup": "Mem;MemoryBW;MemoryBound",
+        "MetricName": "MLP"
     },
     {
-        "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
-        "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CLKS",
-        "MetricGroup": "TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_4k_aliasing",
-        "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
+        "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L1MPKI"
     },
     {
-        "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
-        "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.REQUEST_FB_FULL\\,cmask\\=1@ / CLKS",
-        "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_fb_full",
-        "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
+        "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
+        "MetricGroup": "Backend;CacheMisses;Mem",
+        "MetricName": "L2MPKI"
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
-        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING) / CLKS",
-        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_l2_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
+        "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L3MPKI"
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
-        "MetricExpr": "(MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
-        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_l3_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
+        "MetricConstraint": "NO_NMI_WATCHDOG",
+        "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION) / CORE_CLKS",
+        "MetricGroup": "Mem;MemoryTLB",
+        "MetricName": "Page_Walks_Utilization"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
-        "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CLKS",
-        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_contested_accesses",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
+        "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L1D_Cache_Fill_BW"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
-        "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS",
-        "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_data_sharing",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
+        "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L2_Cache_Fill_BW"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
-        "MetricExpr": "41 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS",
-        "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_l3_hit_latency",
-        "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
+        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L3_Cache_Fill_BW"
     },
     {
-        "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
-        "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
-        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_sq_full",
-        "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
+        "MetricExpr": "L1D_Cache_Fill_BW",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L1D_Cache_Fill_BW_1T"
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
-        "MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS))) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
-        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_dram_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
+        "MetricExpr": "L2_Cache_Fill_BW",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L2_Cache_Fill_BW_1T"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
-        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=6@) / CLKS",
-        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group",
-        "MetricName": "tma_mem_bandwidth",
-        "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM).  The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
+        "MetricExpr": "L3_Cache_Fill_BW",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L3_Cache_Fill_BW_1T"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
-        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth",
-        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group",
-        "MetricName": "tma_mem_latency",
-        "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM).  This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
+        "MetricExpr": "0",
+        "MetricGroup": "Mem;MemoryBW;Offcore",
+        "MetricName": "L3_Cache_Access_BW_1T"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
-        "MetricExpr": "200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS",
-        "MetricGroup": "Server;TopdownL5;tma_mem_latency_group",
-        "MetricName": "tma_local_dram",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average CPU Utilization",
+        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+        "MetricGroup": "HPC;Summary",
+        "MetricName": "CPU_Utilization"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
-        "MetricExpr": "310 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS",
-        "MetricGroup": "Server;Snoop;TopdownL5;tma_mem_latency_group",
-        "MetricName": "tma_remote_dram",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
+        "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
+        "MetricGroup": "Power;Summary",
+        "MetricName": "Average_Frequency"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
-        "MetricExpr": "(200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CLKS",
-        "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_mem_latency_group",
-        "MetricName": "tma_remote_cache",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average Frequency Utilization relative nominal frequency",
+        "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
+        "MetricGroup": "Power",
+        "MetricName": "Turbo_Utilization"
     },
     {
-        "BriefDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
-        "MetricExpr": "RESOURCE_STALLS.SB / CLKS",
-        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_store_bound",
-        "PublicDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
+        "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
+        "MetricGroup": "SMT",
+        "MetricName": "SMT_2T_Utilization"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
-        "MetricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES))) + (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
-        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_store_latency",
-        "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "OS",
+        "MetricName": "Kernel_Utilization"
     },
     {
-        "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
-        "MetricExpr": "(200 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE) / CLKS",
-        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_false_sharing",
-        "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line.  Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
+        "MetricGroup": "OS",
+        "MetricName": "Kernel_CPI"
     },
     {
-        "BriefDescription": "This metric represents rate of split store accesses",
-        "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / CORE_CLKS",
-        "MetricGroup": "TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_split_stores",
-        "PublicDescription": "This metric represents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_UOPS_RETIRED.SPLIT_STORES_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
+        "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time",
+        "MetricGroup": "HPC;Mem;MemoryBW;SoC",
+        "MetricName": "DRAM_BW_Use"
     },
     {
-        "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
-        "MetricExpr": "(8 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION) / CLKS",
-        "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_dtlb_store",
-        "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead.  Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page.  Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
+        "MetricExpr": "1e9 * (UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_INSERTS.MISS_OPCODE@filter_opc\\=0x182@) / (Socket_CLKS / duration_time)",
+        "MetricGroup": "Mem;MemoryLat;SoC",
+        "MetricName": "MEM_Read_Latency"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
-        "MetricExpr": "tma_backend_bound - tma_memory_bound",
-        "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group",
-        "MetricName": "tma_core_bound",
-        "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
+        "MetricExpr": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182\\,thresh\\=1@",
+        "MetricGroup": "Mem;MemoryBW;SoC",
+        "MetricName": "MEM_Parallel_Reads"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
-        "MetricExpr": "10 * ARITH.DIVIDER_UOPS / CORE_CLKS",
-        "MetricGroup": "TopdownL3;tma_core_bound_group",
-        "MetricName": "tma_divider",
-        "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Socket actual clocks when any core is active on that socket",
+        "MetricExpr": "cbox_0@event\\=0x0@",
+        "MetricGroup": "SoC",
+        "MetricName": "Socket_CLKS"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
-        "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / CLKS",
-        "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
-        "MetricName": "tma_ports_utilization",
-        "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
+        "MetricGroup": "Branches;OS",
+        "MetricName": "IpFarBranch"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@) / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else 0) / CORE_CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_0",
-        "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Uncore frequency per die [GHZ]",
+        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+        "MetricGroup": "SoC",
+        "MetricName": "UNCORE_FREQ"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / CORE_CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_1",
-        "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "CPU operating frequency (in GHz)",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / duration_time",
+        "MetricName": "cpu_operating_frequency",
+        "ScaleUnit": "1GHz"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / CORE_CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_2",
-        "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY",
+        "MetricName": "cpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
-        "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / CORE_CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_3m",
-        "ScaleUnit": "100%"
+        "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
+        "MetricExpr": "MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
+        "MetricName": "loads_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
-        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / (4 * CORE_CLKS)",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
-        "MetricName": "tma_alu_op_utilization",
-        "ScaleUnit": "100%"
+        "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
+        "MetricExpr": "MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY",
+        "MetricName": "stores_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED_PORT.PORT_0",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS",
-        "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group",
-        "MetricName": "tma_port_0",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
+        "MetricName": "l1d_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_1",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
-        "MetricName": "tma_port_1",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions",
+        "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L1_HIT / INST_RETIRED.ANY",
+        "MetricName": "l1d_demand_data_read_hits_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) Sample with: UOPS_DISPATCHED.PORT_5",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
-        "MetricName": "tma_port_5",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
+        "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
+        "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_6",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
-        "MetricName": "tma_port_6",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions",
+        "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_HIT / INST_RETIRED.ANY",
+        "MetricName": "l2_demand_data_read_hits_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3",
-        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
-        "MetricName": "tma_load_op_utilization",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
+        "MetricName": "l2_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_2",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_load_op_utilization_group",
-        "MetricName": "tma_port_2",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
+        "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
+        "MetricName": "l2_demand_data_read_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_3",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_load_op_utilization_group",
-        "MetricName": "tma_port_3",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
+        "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
+        "MetricName": "l2_demand_code_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
-        "MetricName": "tma_store_op_utilization",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds",
+        "MetricExpr": "1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time",
+        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency",
+        "ScaleUnit": "1ns"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data) Sample with: UOPS_DISPATCHED_PORT.PORT_4",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_store_op_utilization_group",
-        "MetricName": "tma_port_4",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds",
+        "MetricExpr": "1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time",
+        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests",
+        "ScaleUnit": "1ns"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address) Sample with: UOPS_DISPATCHED_PORT.PORT_7",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_store_op_utilization_group",
-        "MetricName": "tma_port_7",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds",
+        "MetricExpr": "1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time",
+        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests",
+        "ScaleUnit": "1ns"
     },
     {
-        "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
-        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS",
-        "MetricGroup": "TopdownL1;tma_L1_group",
-        "MetricName": "tma_retiring",
-        "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided.  Sample with: UOPS_RETIRED.RETIRE_SLOTS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions",
+        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+        "MetricName": "itlb_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
-        "MetricExpr": "tma_retiring - tma_heavy_operations",
-        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
-        "MetricName": "tma_light_operations",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions",
+        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+        "MetricName": "itlb_large_page_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
-        "MetricExpr": "INST_RETIRED.X87 * UPI / UOPS_RETIRED.RETIRE_SLOTS",
-        "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group",
-        "MetricName": "tma_x87_use",
-        "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions",
+        "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+        "MetricName": "dtlb_load_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
-        "MetricExpr": "tma_microcode_sequencer",
-        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
-        "MetricName": "tma_heavy_operations",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions",
+        "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+        "MetricName": "dtlb_store_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
-        "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
-        "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
-        "MetricName": "tma_microcode_sequencer",
-        "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Uncore operating frequency in GHz",
+        "MetricExpr": "UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages) / 1e9 / duration_time",
+        "MetricName": "uncore_frequency",
+        "ScaleUnit": "1GHz"
     },
     {
-        "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
-        "MetricExpr": "100 * OTHER_ASSISTS.ANY_WB_ASSIST / SLOTS",
-        "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
-        "MetricName": "tma_assists",
-        "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Intel(R) Quick Path Interconnect (QPI) data transmit bandwidth (MB/sec)",
+        "MetricExpr": "UNC_Q_TxL_FLITS_G0.DATA * 8 / 1e6 / duration_time",
+        "MetricName": "qpi_data_transmit_bw",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
-        "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
-        "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
-        "MetricName": "tma_cisc",
-        "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "DDR memory read bandwidth (MB/sec)",
+        "MetricExpr": "UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time",
+        "MetricName": "memory_bandwidth_read",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
-        "MetricExpr": "INST_RETIRED.ANY / CLKS",
-        "MetricGroup": "Ret;Summary",
-        "MetricName": "IPC"
+        "BriefDescription": "DDR memory write bandwidth (MB/sec)",
+        "MetricExpr": "UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time",
+        "MetricName": "memory_bandwidth_write",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Uops Per Instruction",
-        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
-        "MetricGroup": "Pipeline;Ret;Retire",
-        "MetricName": "UPI"
+        "BriefDescription": "DDR memory bandwidth (MB/sec)",
+        "MetricExpr": "(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time",
+        "MetricName": "memory_bandwidth_total",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instruction per taken branch",
-        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
-        "MetricGroup": "Branches;Fed;FetchBW",
-        "MetricName": "UpTB"
+        "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
+        "MetricExpr": "cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x19e@ * 64 / 1e6 / duration_time",
+        "MetricName": "io_bandwidth_disk_or_network_writes",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
-        "MetricExpr": "1 / IPC",
-        "MetricGroup": "Mem;Pipeline",
-        "MetricName": "CPI"
+        "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
+        "MetricExpr": "cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x1c8\\,filter_tid\\=0x3e@ * 64 / 1e6 / duration_time",
+        "MetricName": "io_bandwidth_disk_or_network_reads",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
-        "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
-        "MetricGroup": "Pipeline",
-        "MetricName": "CLKS"
+        "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
+        "MetricExpr": "IDQ.DSB_UOPS / UOPS_ISSUED.ANY",
+        "MetricName": "percent_uops_delivered_from_decoded_icache",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
-        "MetricExpr": "4 * CORE_CLKS",
-        "MetricGroup": "tma_L1_group",
-        "MetricName": "SLOTS"
+        "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
+        "MetricExpr": "IDQ.MITE_UOPS / UOPS_ISSUED.ANY",
+        "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
-        "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
-        "MetricGroup": "Ret;SMT;tma_L1_group",
-        "MetricName": "CoreIPC"
+        "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
+        "MetricExpr": "IDQ.MS_UOPS / UOPS_ISSUED.ANY",
+        "MetricName": "percent_uops_delivered_from_microcode_sequencer",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
-        "MetricExpr": "(UOPS_EXECUTED.CORE / 2 / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@)) if #SMT_on else UOPS_EXECUTED.CORE / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@)",
-        "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
-        "MetricName": "ILP"
+        "BriefDescription": "Uops delivered from loop stream detector(LSD) as a percent of total uops delivered to Instruction Decode Queue",
+        "MetricExpr": "(UOPS_ISSUED.ANY - IDQ.MITE_UOPS - IDQ.MS_UOPS - IDQ.DSB_UOPS) / UOPS_ISSUED.ANY",
+        "MetricName": "percent_uops_delivered_from_loop_stream_detector",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
-        "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
-        "MetricGroup": "SMT",
-        "MetricName": "CORE_CLKS"
+        "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "(cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x192@) / INST_RETIRED.ANY",
+        "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
-        "MetricGroup": "InsType",
-        "MetricName": "IpLoad"
+        "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "(cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x181@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x191@) / INST_RETIRED.ANY",
+        "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
-        "MetricGroup": "InsType",
-        "MetricName": "IpStore"
+        "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+        "MetricExpr": "cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / (cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@)",
+        "MetricName": "numa_reads_addressed_to_local_dram",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Branches;Fed;InsType",
-        "MetricName": "IpBranch"
+        "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+        "MetricExpr": "cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / (cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@)",
+        "MetricName": "numa_reads_addressed_to_remote_dram",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
-        "MetricGroup": "Branches;Fed;PGO",
-        "MetricName": "IpCall"
+        "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
+        "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS",
+        "MetricGroup": "PGO;TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_frontend_bound",
+        "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instruction per taken branch",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
-        "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
-        "MetricName": "IpTB"
+        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
+        "MetricExpr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / SLOTS",
+        "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+        "MetricName": "tma_fetch_latency",
+        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Branch instructions per taken branch. ",
-        "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
-        "MetricGroup": "Branches;Fed;PGO",
-        "MetricName": "BpTkBranch"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.",
+        "MetricExpr": "ICACHE.IFDATA_STALL / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_icache_misses",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
-        "MetricExpr": "INST_RETIRED.ANY",
-        "MetricGroup": "Summary;tma_L1_group",
-        "MetricName": "Instructions"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.",
+        "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_itlb_misses",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
-        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
-        "MetricGroup": "Pipeline;Ret",
-        "MetricName": "Retire"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
+        "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_branch_resteers",
+        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
-        "MetricExpr": "IDQ.DSB_UOPS / ((IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS))",
-        "MetricGroup": "DSB;Fed;FetchBW",
-        "MetricName": "DSB_Coverage"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
+        "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_dsb_switches",
+        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;BadSpec;BrMispredicts",
-        "MetricName": "IpMispredict"
+        "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
+        "MetricExpr": "ILD_STALL.LCP / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_lcp",
+        "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
-        "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb)",
-        "MetricGroup": "Mem;MemoryBound;MemoryLat",
-        "MetricName": "Load_Miss_Real_Latency"
+        "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
+        "MetricExpr": "2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_ms_switches",
+        "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
-        "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
-        "MetricGroup": "Mem;MemoryBW;MemoryBound",
-        "MetricName": "MLP"
+        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
+        "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
+        "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+        "MetricName": "tma_fetch_bandwidth",
+        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues.  For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L1MPKI"
+        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
+        "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
+        "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+        "MetricName": "tma_mite",
+        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "Backend;CacheMisses;Mem",
-        "MetricName": "L2MPKI"
+        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
+        "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2",
+        "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+        "MetricName": "tma_dsb",
+        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline.  For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L3MPKI"
+        "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
+        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+        "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_bad_speculation",
+        "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
-        "MetricConstraint": "NO_NMI_WATCHDOG",
-        "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION) / CORE_CLKS",
-        "MetricGroup": "Mem;MemoryTLB",
-        "MetricName": "Page_Walks_Utilization"
+        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
+        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
+        "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+        "MetricName": "tma_branch_mispredicts",
+        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
-        "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L1D_Cache_Fill_BW"
+        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
+        "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
+        "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+        "MetricName": "tma_machine_clears",
+        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears.  These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
-        "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L2_Cache_Fill_BW"
+        "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
+        "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + UOPS_RETIRED.RETIRE_SLOTS / SLOTS)",
+        "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_backend_bound",
+        "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L3_Cache_Fill_BW"
+        "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
+        "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@)) / 2 - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB if #SMT_on else min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound",
+        "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+        "MetricName": "tma_memory_bound",
+        "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
-        "MetricExpr": "L1D_Cache_Fill_BW",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L1D_Cache_Fill_BW_1T"
+        "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
+        "MetricExpr": "max((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) - CYCLE_ACTIVITY.STALLS_L1D_PENDING) / CPU_CLK_UNHALTED.THREAD, 0)",
+        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_l1_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache.  The L1 data cache typically has the shortest latency.  However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
-        "MetricExpr": "L2_Cache_Fill_BW",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L2_Cache_Fill_BW_1T"
+        "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
+        "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_dtlb_load",
+        "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "L3_Cache_Fill_BW",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L3_Cache_Fill_BW_1T"
+        "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
+        "MetricExpr": "min(13 * LD_BLOCKS.STORE_FORWARD / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_store_fwd_blk",
+        "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "0",
-        "MetricGroup": "Mem;MemoryBW;Offcore",
-        "MetricName": "L3_Cache_Access_BW_1T"
+        "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
+        "MetricExpr": "min(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_lock_latency",
+        "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average CPU Utilization",
-        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
-        "MetricGroup": "HPC;Summary",
-        "MetricName": "CPU_Utilization"
+        "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ",
+        "MetricExpr": "min(Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_split_loads",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
-        "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
-        "MetricGroup": "Power;Summary",
-        "MetricName": "Average_Frequency"
+        "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
+        "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_4k_aliasing",
+        "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average Frequency Utilization relative nominal frequency",
-        "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
-        "MetricGroup": "Power",
-        "MetricName": "Turbo_Utilization"
+        "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
+        "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.REQUEST_FB_FULL\\,cmask\\=0x1@ / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_fb_full",
+        "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
-        "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
-        "MetricGroup": "SMT",
-        "MetricName": "SMT_2T_Utilization"
+        "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
+        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_l2_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
-        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
-        "MetricGroup": "OS",
-        "MetricName": "Kernel_Utilization"
+        "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
+        "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_l3_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
-        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
-        "MetricGroup": "OS",
-        "MetricName": "Kernel_CPI"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
+        "MetricExpr": "min((60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_contested_accesses",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
-        "MetricExpr": "(64 * (uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@) / 1000000000) / duration_time",
-        "MetricGroup": "HPC;Mem;MemoryBW;SoC",
-        "MetricName": "DRAM_BW_Use"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
+        "MetricExpr": "min(43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_data_sharing",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
-        "MetricExpr": "1000000000 * (cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x35\\,umask\\=0x3\\,filter_opc\\=0x182@) / (Socket_CLKS / duration_time)",
-        "MetricGroup": "Mem;MemoryLat;SoC",
-        "MetricName": "MEM_Read_Latency"
+        "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
+        "MetricExpr": "min(41 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_l3_hit_latency",
+        "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
-        "MetricExpr": "cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182\\,thresh\\=1@",
-        "MetricGroup": "Mem;MemoryBW;SoC",
-        "MetricName": "MEM_Parallel_Reads"
+        "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
+        "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
+        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_sq_full",
+        "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Socket actual clocks when any core is active on that socket",
-        "MetricExpr": "cbox_0@event\\=0x0@",
-        "MetricGroup": "SoC",
-        "MetricName": "Socket_CLKS"
+        "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
+        "MetricExpr": "min((1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_dram_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
-        "MetricGroup": "Branches;OS",
-        "MetricName": "IpFarBranch"
+        "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
+        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x6@) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+        "MetricName": "tma_mem_bandwidth",
+        "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM).  The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C3 residency percent per core",
-        "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C3_Core_Residency"
+        "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
+        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CPU_CLK_UNHALTED.THREAD - tma_mem_bandwidth",
+        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+        "MetricName": "tma_mem_latency",
+        "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM).  This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C6 residency percent per core",
-        "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C6_Core_Residency"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
+        "MetricExpr": "min(200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group",
+        "MetricName": "tma_local_dram",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C7 residency percent per core",
-        "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C7_Core_Residency"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
+        "MetricExpr": "min(310 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+        "MetricName": "tma_remote_dram",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C2 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C2_Pkg_Residency"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
+        "MetricExpr": "min((200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+        "MetricName": "tma_remote_cache",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C3 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C3_Pkg_Residency"
+        "BriefDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
+        "MetricExpr": "RESOURCE_STALLS.SB / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_store_bound",
+        "PublicDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C6 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C6_Pkg_Residency"
+        "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
+        "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_store_latency",
+        "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C7 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C7_Pkg_Residency"
+        "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
+        "MetricExpr": "min((200 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_false_sharing",
+        "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uncore frequency per die [GHZ]",
-        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000",
-        "MetricGroup": "SoC",
-        "MetricName": "UNCORE_FREQ"
+        "BriefDescription": "This metric represents rate of split store accesses",
+        "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / CORE_CLKS",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_split_stores",
+        "PublicDescription": "This metric represents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granularity.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "CPU operating frequency (in GHz)",
-        "MetricExpr": "(( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ ) / 1000000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "cpu_operating_frequency",
-        "ScaleUnit": "1GHz"
+        "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
+        "MetricExpr": "min((8 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_dtlb_store",
+        "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead.  Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page.  Try using larger page sizes for large amounts of frequently-used data.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
-        "MetricExpr": "MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "loads_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
+        "MetricExpr": "tma_backend_bound - tma_memory_bound",
+        "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+        "MetricName": "tma_core_bound",
+        "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
-        "MetricExpr": "MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "stores_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
+        "MetricExpr": "10 * ARITH.DIVIDER_UOPS / CORE_CLKS",
+        "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group",
+        "MetricName": "tma_divider",
+        "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l1d_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
+        "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@)) / 2 - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB if #SMT_on else min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group",
+        "MetricName": "tma_ports_utilization",
+        "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions",
-        "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L1_HIT / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l1d_demand_data_read_hits_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\=0x1\\,cmask\\=0x1@ / 2 if #SMT_on else min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0)) / CORE_CLKS",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_0",
+        "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
-        "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+        "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@) / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@) / CORE_CLKS",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_1",
+        "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions",
-        "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_HIT / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_demand_data_read_hits_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+        "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@) / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@) / CORE_CLKS",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_2",
+        "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
+        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@) / CORE_CLKS",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_3m",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
-        "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_demand_data_read_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
+        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+        "MetricName": "tma_alu_op_utilization",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
-        "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_demand_code_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS",
+        "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+        "MetricName": "tma_port_0",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds",
-        "MetricExpr": "( 1000000000 * ( cbox@UNC_C_TOR_OCCUPANCY.MISS_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ ) / ( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency",
-        "ScaleUnit": "1ns"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+        "MetricName": "tma_port_1",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds",
-        "MetricExpr": "( 1000000000 * ( cbox@UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ ) / ( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests",
-        "ScaleUnit": "1ns"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+        "MetricName": "tma_port_5",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds",
-        "MetricExpr": "( 1000000000 * ( cbox@UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ ) / ( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests",
-        "ScaleUnit": "1ns"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+        "MetricName": "tma_port_6",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
-        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "itlb_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations",
+        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+        "MetricName": "tma_load_op_utilization",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
-        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "itlb_large_page_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group",
+        "MetricName": "tma_port_2",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
-        "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "dtlb_load_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group",
+        "MetricName": "tma_port_3",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
-        "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "dtlb_store_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+        "MetricName": "tma_store_op_utilization",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uncore operating frequency in GHz",
-        "MetricExpr": "( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) / 1000000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "uncore_frequency",
-        "ScaleUnit": "1GHz"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)",
+        "MetricExpr": "tma_store_op_utilization",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group",
+        "MetricName": "tma_port_4",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Intel(R) Quick Path Interconnect (QPI) data transmit bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_Q_TxL_FLITS_G0.DATA * 8 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "qpi_data_transmit_bw",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group",
+        "MetricName": "tma_port_7",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "DDR memory read bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "memory_bandwidth_read",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS",
+        "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_retiring",
+        "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "DDR memory write bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "memory_bandwidth_write",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
+        "MetricExpr": "tma_retiring - UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
+        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+        "MetricName": "tma_light_operations",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "DDR memory bandwidth (MB/sec)",
-        "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "memory_bandwidth_total",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
+        "MetricExpr": "INST_RETIRED.X87 * UPI / UOPS_RETIRED.RETIRE_SLOTS",
+        "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_x87_use",
+        "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
-        "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x19e@ * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "io_bandwidth_disk_or_network_writes",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
+        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+        "MetricName": "tma_heavy_operations",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
-        "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x1c8\\,filter_tid\\=0x3e@ * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "io_bandwidth_disk_or_network_reads",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
+        "MetricExpr": "tma_heavy_operations",
+        "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group",
+        "MetricName": "tma_microcode_sequencer",
+        "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
-        "MetricExpr": "100 * ( IDQ.DSB_UOPS / UOPS_ISSUED.ANY )",
-        "MetricGroup": "",
-        "MetricName": "percent_uops_delivered_from_decoded_icache",
-        "ScaleUnit": "1%"
+        "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
+        "MetricExpr": "min(100 * OTHER_ASSISTS.ANY_WB_ASSIST / SLOTS, 1)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+        "MetricName": "tma_assists",
+        "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
-        "MetricExpr": "100 * ( IDQ.MITE_UOPS / UOPS_ISSUED.ANY )",
-        "MetricGroup": "",
-        "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
-        "ScaleUnit": "1%"
+        "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
+        "MetricExpr": "max(0, tma_heavy_operations - tma_assists)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+        "MetricName": "tma_cisc",
+        "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
-        "MetricExpr": "100 * ( IDQ.MS_UOPS / UOPS_ISSUED.ANY )",
-        "MetricGroup": "",
-        "MetricName": "percent_uops_delivered_from_microcode_sequencer",
-        "ScaleUnit": "1%"
+        "BriefDescription": "C3 residency percent per core",
+        "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C3_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uops delivered from loop stream detector(LSD) as a percent of total uops delivered to Instruction Decode Queue",
-        "MetricExpr": "100 * ( UOPS_ISSUED.ANY - IDQ.MITE_UOPS - IDQ.MS_UOPS - IDQ.DSB_UOPS ) / UOPS_ISSUED.ANY",
-        "MetricGroup": "",
-        "MetricName": "percent_uops_delivered_from_loop_stream_detector",
-        "ScaleUnit": "1%"
+        "BriefDescription": "C6 residency percent per core",
+        "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C6_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x192@ ) / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "C7 residency percent per core",
+        "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C7_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x181@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x191@ ) / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "C2 residency percent per package",
+        "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C2_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
-        "MetricExpr": "100 * cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / ( cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ )",
-        "MetricGroup": "",
-        "MetricName": "numa_reads_addressed_to_local_dram",
-        "ScaleUnit": "1%"
+        "BriefDescription": "C3 residency percent per package",
+        "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C3_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
-        "MetricExpr": "100 * cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / ( cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ )",
-        "MetricGroup": "",
-        "MetricName": "numa_reads_addressed_to_remote_dram",
-        "ScaleUnit": "1%"
+        "BriefDescription": "C6 residency percent per package",
+        "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C6_Pkg_Residency",
+        "ScaleUnit": "100%"
+    },
+    {
+        "BriefDescription": "C7 residency percent per package",
+        "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C7_Pkg_Residency",
+        "ScaleUnit": "100%"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/memory.json b/tools/perf/pmu-events/arch/x86/haswellx/memory.json
index fdabc9fe12a52..2d212cf59e923 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/memory.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED",
         "PEBS": "1",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC1",
         "SampleAfterValue": "2000003",
@@ -20,8 +16,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC2",
         "SampleAfterValue": "2000003",
@@ -29,8 +23,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC3",
         "SampleAfterValue": "2000003",
@@ -38,8 +30,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD65",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC4",
@@ -48,8 +38,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MISC5",
         "PublicDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts).",
@@ -58,8 +46,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution successfully committed.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.COMMIT",
         "SampleAfterValue": "2000003",
@@ -67,8 +53,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution started.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.START",
         "SampleAfterValue": "2000003",
@@ -76,8 +60,6 @@
     },
     {
         "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
         "PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline.  Machine clears can have a significant performance impact if they are happening frequently.",
@@ -86,8 +68,6 @@
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 128.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "HSD76, HSD25, HSM26",
         "EventCode": "0xcd",
@@ -96,13 +76,10 @@
         "MSRValue": "0x80",
         "PEBS": "2",
         "SampleAfterValue": "1009",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 16.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "HSD76, HSD25, HSM26",
         "EventCode": "0xcd",
@@ -111,13 +88,10 @@
         "MSRValue": "0x10",
         "PEBS": "2",
         "SampleAfterValue": "20011",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 256.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "HSD76, HSD25, HSM26",
         "EventCode": "0xcd",
@@ -126,13 +100,10 @@
         "MSRValue": "0x100",
         "PEBS": "2",
         "SampleAfterValue": "503",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 32.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "HSD76, HSD25, HSM26",
         "EventCode": "0xcd",
@@ -141,13 +112,10 @@
         "MSRValue": "0x20",
         "PEBS": "2",
         "SampleAfterValue": "100003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 4.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "HSD76, HSD25, HSM26",
         "EventCode": "0xcd",
@@ -156,13 +124,10 @@
         "MSRValue": "0x4",
         "PEBS": "2",
         "SampleAfterValue": "100003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 512.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "HSD76, HSD25, HSM26",
         "EventCode": "0xcd",
@@ -171,13 +136,10 @@
         "MSRValue": "0x200",
         "PEBS": "2",
         "SampleAfterValue": "101",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 64.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "HSD76, HSD25, HSM26",
         "EventCode": "0xcd",
@@ -186,13 +148,10 @@
         "MSRValue": "0x40",
         "PEBS": "2",
         "SampleAfterValue": "2003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Randomly selected loads with latency value being above 8.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "Data_LA": "1",
         "Errata": "HSD76, HSD25, HSM26",
         "EventCode": "0xcd",
@@ -201,13 +160,10 @@
         "MSRValue": "0x8",
         "PEBS": "2",
         "SampleAfterValue": "50021",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x05",
         "EventName": "MISALIGN_MEM_REF.LOADS",
         "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.",
@@ -216,8 +172,6 @@
     },
     {
         "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x05",
         "EventName": "MISALIGN_MEM_REF.STORES",
         "PublicDescription": "Speculative cache-line split store-address uops dispatched to L1D.",
@@ -226,344 +180,258 @@
     },
     {
         "BriefDescription": "Counts all demand & prefetch code reads miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC00244",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x600400244",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC00091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x600400091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63F800091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x6004007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63F8007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC007F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all requests miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC08FFF",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC00122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x600400122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC00004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x600400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC00001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads miss the L3 and the data is returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x600400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC00002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x600400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC00040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC00010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC00020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC00200",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC00080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC00100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED",
         "PEBS": "1",
@@ -572,8 +440,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC1",
         "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
@@ -582,8 +448,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC2",
         "SampleAfterValue": "2000003",
@@ -591,8 +455,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC3",
         "SampleAfterValue": "2000003",
@@ -600,8 +462,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "HSD65",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC4",
@@ -610,8 +470,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MISC5",
         "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
@@ -620,8 +478,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution successfully committed.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.COMMIT",
         "SampleAfterValue": "2000003",
@@ -629,8 +485,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution started.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.START",
         "SampleAfterValue": "2000003",
@@ -638,8 +492,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC1",
         "SampleAfterValue": "2000003",
@@ -647,8 +499,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC2",
         "SampleAfterValue": "2000003",
@@ -656,8 +506,6 @@
     },
     {
         "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC3",
         "SampleAfterValue": "2000003",
@@ -665,8 +513,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC4",
         "SampleAfterValue": "2000003",
@@ -674,8 +520,6 @@
     },
     {
         "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC5",
         "SampleAfterValue": "2000003",
@@ -683,8 +527,6 @@
     },
     {
         "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
         "SampleAfterValue": "2000003",
@@ -692,8 +534,6 @@
     },
     {
         "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CONFLICT",
         "SampleAfterValue": "2000003",
@@ -701,8 +541,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
         "SampleAfterValue": "2000003",
@@ -710,8 +548,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
         "SampleAfterValue": "2000003",
@@ -719,8 +555,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
         "SampleAfterValue": "2000003",
@@ -728,8 +562,6 @@
     },
     {
         "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
         "SampleAfterValue": "2000003",
@@ -737,8 +569,6 @@
     },
     {
         "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
         "SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/other.json b/tools/perf/pmu-events/arch/x86/haswellx/other.json
index 7ca34f09b185e..2395ebf112db3 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/other.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/other.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5C",
         "EventName": "CPL_CYCLES.RING0",
         "PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5C",
@@ -22,8 +18,6 @@
     },
     {
         "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5C",
         "EventName": "CPL_CYCLES.RING123",
         "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
@@ -32,8 +26,6 @@
     },
     {
         "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x63",
         "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
         "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json b/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json
index 42f6a81006613..9ac36c1c24b66 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Any uop executed by the Divider. (This includes all divide uops, sqrt, ...)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x14",
         "EventName": "ARITH.DIVIDER_UOPS",
         "SampleAfterValue": "2000003",
@@ -10,8 +8,6 @@
     },
     {
         "BriefDescription": "Speculative and retired  branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_BRANCHES",
         "PublicDescription": "Counts all near executed branches (not necessarily retired).",
@@ -20,8 +16,6 @@
     },
     {
         "BriefDescription": "Speculative and retired macro-conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -29,8 +23,6 @@
     },
     {
         "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
         "SampleAfterValue": "200003",
@@ -38,8 +30,6 @@
     },
     {
         "BriefDescription": "Speculative and retired direct near calls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
         "SampleAfterValue": "200003",
@@ -47,8 +37,6 @@
     },
     {
         "BriefDescription": "Speculative and retired indirect branches excluding calls and returns.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
         "SampleAfterValue": "200003",
@@ -56,8 +44,6 @@
     },
     {
         "BriefDescription": "Speculative and retired indirect return branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
         "SampleAfterValue": "200003",
@@ -65,8 +51,6 @@
     },
     {
         "BriefDescription": "Not taken macro-conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -74,8 +58,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired macro-conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -83,8 +65,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
         "SampleAfterValue": "200003",
@@ -92,8 +72,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired direct near calls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
         "SampleAfterValue": "200003",
@@ -101,8 +79,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
         "SampleAfterValue": "200003",
@@ -110,8 +86,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect calls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
         "SampleAfterValue": "200003",
@@ -119,8 +93,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
         "SampleAfterValue": "200003",
@@ -128,8 +100,6 @@
     },
     {
         "BriefDescription": "All (macro) branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "PublicDescription": "Branch instructions at retirement.",
@@ -137,8 +107,6 @@
     },
     {
         "BriefDescription": "All (macro) branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
         "PEBS": "2",
@@ -147,8 +115,6 @@
     },
     {
         "BriefDescription": "Conditional branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -158,8 +124,6 @@
     },
     {
         "BriefDescription": "Far branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.FAR_BRANCH",
         "PublicDescription": "Number of far branches retired.",
@@ -168,8 +132,6 @@
     },
     {
         "BriefDescription": "Direct and indirect near call instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -178,8 +140,6 @@
     },
     {
         "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
         "PEBS": "1",
@@ -188,8 +148,6 @@
     },
     {
         "BriefDescription": "Return instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_RETURN",
         "PEBS": "1",
@@ -199,8 +157,6 @@
     },
     {
         "BriefDescription": "Taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
@@ -210,8 +166,6 @@
     },
     {
         "BriefDescription": "Not taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NOT_TAKEN",
         "PublicDescription": "Counts the number of not taken branch instructions retired.",
@@ -220,8 +174,6 @@
     },
     {
         "BriefDescription": "Speculative and retired mispredicted macro conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_BRANCHES",
         "PublicDescription": "Counts all near executed branches (not necessarily retired).",
@@ -230,8 +182,6 @@
     },
     {
         "BriefDescription": "Speculative and retired mispredicted macro conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -239,8 +189,6 @@
     },
     {
         "BriefDescription": "Mispredicted indirect branches excluding calls and returns.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
         "SampleAfterValue": "200003",
@@ -248,8 +196,6 @@
     },
     {
         "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -257,8 +203,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -266,8 +210,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
         "SampleAfterValue": "200003",
@@ -275,8 +217,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect calls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
         "SampleAfterValue": "200003",
@@ -284,8 +224,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
         "SampleAfterValue": "200003",
@@ -293,8 +231,6 @@
     },
     {
         "BriefDescription": "All mispredicted macro branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PublicDescription": "Mispredicted branch instructions at retirement.",
@@ -302,8 +238,6 @@
     },
     {
         "BriefDescription": "Mispredicted macro branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
         "PEBS": "2",
@@ -313,8 +247,6 @@
     },
     {
         "BriefDescription": "Mispredicted conditional branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -323,8 +255,6 @@
     },
     {
         "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
@@ -334,8 +264,6 @@
     },
     {
         "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "100003",
@@ -343,8 +271,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
         "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.",
@@ -354,8 +280,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
         "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
@@ -364,8 +288,6 @@
     },
     {
         "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "100003",
@@ -373,8 +295,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the core is not in halt state.",
-        "Counter": "Fixed counter 2",
-        "CounterHTOff": "Fixed counter 2",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
         "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state.",
         "SampleAfterValue": "2000003",
@@ -382,8 +302,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
         "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)",
@@ -393,8 +311,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
         "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
@@ -403,8 +319,6 @@
     },
     {
         "BriefDescription": "Core cycles when the thread is not in halt state.",
-        "Counter": "Fixed counter 1",
-        "CounterHTOff": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD",
         "PublicDescription": "This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.",
         "SampleAfterValue": "2000003",
@@ -413,16 +327,12 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
-        "Counter": "Fixed counter 1",
-        "CounterHTOff": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Thread cycles when thread is not in halt state",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
         "PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.",
@@ -431,16 +341,12 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Cycles with pending L1 cache miss loads.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "8",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
@@ -450,8 +356,6 @@
     },
     {
         "BriefDescription": "Cycles with pending L2 cache miss loads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "Errata": "HSD78, HSM63, HSM80",
         "EventCode": "0xa3",
@@ -462,8 +366,6 @@
     },
     {
         "BriefDescription": "Cycles with pending memory loads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
@@ -473,8 +375,6 @@
     },
     {
         "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
@@ -484,8 +384,6 @@
     },
     {
         "BriefDescription": "Execution stalls due to L1 data cache misses",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "12",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
@@ -495,8 +393,6 @@
     },
     {
         "BriefDescription": "Execution stalls due to L2 cache misses.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "5",
         "Errata": "HSM63, HSM80",
         "EventCode": "0xa3",
@@ -507,8 +403,6 @@
     },
     {
         "BriefDescription": "Execution stalls due to memory subsystem.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "6",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",
@@ -518,8 +412,6 @@
     },
     {
         "BriefDescription": "Stall cycles because IQ is full",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.IQ_FULL",
         "PublicDescription": "Stall cycles due to IQ is full.",
@@ -528,8 +420,6 @@
     },
     {
         "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.LCP",
         "PublicDescription": "This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP).",
@@ -538,8 +428,6 @@
     },
     {
         "BriefDescription": "Instructions retired from execution.",
-        "Counter": "Fixed counter 0",
-        "CounterHTOff": "Fixed counter 0",
         "Errata": "HSD140, HSD143",
         "EventName": "INST_RETIRED.ANY",
         "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
@@ -548,8 +436,6 @@
     },
     {
         "BriefDescription": "Number of instructions retired. General Counter   - architectural event",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD11, HSD140",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.ANY_P",
@@ -558,8 +444,6 @@
     },
     {
         "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
-        "Counter": "1",
-        "CounterHTOff": "1",
         "Errata": "HSD140",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.PREC_DIST",
@@ -570,8 +454,6 @@
     },
     {
         "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.X87",
         "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.",
@@ -580,8 +462,6 @@
     },
     {
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES",
@@ -592,8 +472,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
@@ -603,8 +481,6 @@
     },
     {
         "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.NO_SR",
         "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
@@ -613,8 +489,6 @@
     },
     {
         "BriefDescription": "loads blocked by overlapping with store buffer that cannot be forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.STORE_FORWARD",
         "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load.  The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issued.",
@@ -623,8 +497,6 @@
     },
     {
         "BriefDescription": "False dependencies in MOB due to partial compare on address.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x07",
         "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
         "PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K.  This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impact.",
@@ -633,8 +505,6 @@
     },
     {
         "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4c",
         "EventName": "LOAD_HIT_PRE.HW_PF",
         "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.",
@@ -643,8 +513,6 @@
     },
     {
         "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4c",
         "EventName": "LOAD_HIT_PRE.SW_PF",
         "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.",
@@ -653,8 +521,6 @@
     },
     {
         "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_4_UOPS",
@@ -663,8 +529,6 @@
     },
     {
         "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_ACTIVE",
@@ -673,8 +537,6 @@
     },
     {
         "BriefDescription": "Number of Uops delivered by the LSD.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa8",
         "EventName": "LSD.UOPS",
         "PublicDescription": "Number of uops delivered by the LSD.",
@@ -683,8 +545,6 @@
     },
     {
         "BriefDescription": "Number of machine clears (nukes) of any type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xC3",
@@ -694,8 +554,6 @@
     },
     {
         "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.CYCLES",
         "SampleAfterValue": "2000003",
@@ -703,8 +561,6 @@
     },
     {
         "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MASKMOV",
         "SampleAfterValue": "100003",
@@ -712,8 +568,6 @@
     },
     {
         "BriefDescription": "Self-modifying code (SMC) detected.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.SMC",
         "PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear.  Machine clears can have a significant performance impact if they are happening frequently.",
@@ -722,8 +576,6 @@
     },
     {
         "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.INT_ELIMINATED",
         "PublicDescription": "Number of integer move elimination candidate uops that were eliminated.",
@@ -732,8 +584,6 @@
     },
     {
         "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",
         "PublicDescription": "Number of integer move elimination candidate uops that were not eliminated.",
@@ -742,8 +592,6 @@
     },
     {
         "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",
         "PublicDescription": "Number of microcode assists invoked by HW upon uop writeback.",
@@ -752,8 +600,6 @@
     },
     {
         "BriefDescription": "Resource-related stall cycles",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD135",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ANY",
@@ -763,8 +609,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to re-order buffer full.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ROB",
         "SampleAfterValue": "2000003",
@@ -772,8 +616,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no eligible RS entry available.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.RS",
         "SampleAfterValue": "2000003",
@@ -781,8 +623,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.SB",
         "PublicDescription": "This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were available.",
@@ -791,8 +631,6 @@
     },
     {
         "BriefDescription": "Count cases of saving new LBR",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCC",
         "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
         "PublicDescription": "Count cases of saving new LBR records by hardware.",
@@ -801,8 +639,6 @@
     },
     {
         "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5E",
         "EventName": "RS_EVENTS.EMPTY_CYCLES",
         "PublicDescription": "This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-end.",
@@ -811,8 +647,6 @@
     },
     {
         "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5E",
@@ -823,8 +657,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_0",
         "SampleAfterValue": "2000003",
@@ -832,8 +664,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 1.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_1",
         "SampleAfterValue": "2000003",
@@ -841,8 +671,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_2",
         "SampleAfterValue": "2000003",
@@ -850,8 +678,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_3",
         "SampleAfterValue": "2000003",
@@ -859,8 +685,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 4.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_4",
         "SampleAfterValue": "2000003",
@@ -868,8 +692,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 5.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_5",
         "SampleAfterValue": "2000003",
@@ -877,8 +699,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 6.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_6",
         "SampleAfterValue": "2000003",
@@ -886,8 +706,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 7.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_7",
         "SampleAfterValue": "2000003",
@@ -895,8 +713,6 @@
     },
     {
         "BriefDescription": "Number of uops executed on the core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD30, HSM31",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE",
@@ -906,8 +722,6 @@
     },
     {
         "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "Errata": "HSD30, HSM31",
         "EventCode": "0xb1",
@@ -917,8 +731,6 @@
     },
     {
         "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "Errata": "HSD30, HSM31",
         "EventCode": "0xb1",
@@ -928,8 +740,6 @@
     },
     {
         "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "Errata": "HSD30, HSM31",
         "EventCode": "0xb1",
@@ -939,8 +749,6 @@
     },
     {
         "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "Errata": "HSD30, HSM31",
         "EventCode": "0xb1",
@@ -950,8 +758,6 @@
     },
     {
         "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "HSD30, HSM31",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
@@ -961,8 +767,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "Errata": "HSD144, HSD30, HSM31",
         "EventCode": "0xB1",
@@ -973,8 +777,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "2",
         "Errata": "HSD144, HSD30, HSM31",
         "EventCode": "0xB1",
@@ -985,8 +787,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "3",
         "Errata": "HSD144, HSD30, HSM31",
         "EventCode": "0xB1",
@@ -997,8 +797,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 4 uops were executed per-thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "Errata": "HSD144, HSD30, HSM31",
         "EventCode": "0xB1",
@@ -1008,8 +806,6 @@
     },
     {
         "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "Errata": "HSD144, HSD30, HSM31",
         "EventCode": "0xB1",
@@ -1020,8 +816,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_0",
         "PublicDescription": "Cycles which a uop is dispatched on port 0 in this thread.",
@@ -1031,8 +825,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are executed in port 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE",
         "SampleAfterValue": "2000003",
@@ -1040,8 +832,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 1",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_1",
         "PublicDescription": "Cycles which a uop is dispatched on port 1 in this thread.",
@@ -1051,8 +841,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are executed in port 1.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE",
         "SampleAfterValue": "2000003",
@@ -1060,8 +848,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_2",
         "PublicDescription": "Cycles which a uop is dispatched on port 2 in this thread.",
@@ -1071,8 +857,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE",
         "SampleAfterValue": "2000003",
@@ -1080,8 +864,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_3",
         "PublicDescription": "Cycles which a uop is dispatched on port 3 in this thread.",
@@ -1091,8 +873,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE",
         "SampleAfterValue": "2000003",
@@ -1100,8 +880,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 4",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_4",
         "PublicDescription": "Cycles which a uop is dispatched on port 4 in this thread.",
@@ -1111,8 +889,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are executed in port 4.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE",
         "SampleAfterValue": "2000003",
@@ -1120,8 +896,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 5",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_5",
         "PublicDescription": "Cycles which a uop is dispatched on port 5 in this thread.",
@@ -1131,8 +905,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are executed in port 5.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE",
         "SampleAfterValue": "2000003",
@@ -1140,8 +912,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 6",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_6",
         "PublicDescription": "Cycles which a uop is dispatched on port 6 in this thread.",
@@ -1151,8 +921,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are executed in port 6.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE",
         "SampleAfterValue": "2000003",
@@ -1160,8 +928,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 7",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_7",
         "PublicDescription": "Cycles which a uop is dispatched on port 7 in this thread.",
@@ -1171,8 +937,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 7.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE",
         "SampleAfterValue": "2000003",
@@ -1180,8 +944,6 @@
     },
     {
         "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.ANY",
         "PublicDescription": "This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uops.",
@@ -1191,8 +953,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -1202,8 +962,6 @@
     },
     {
         "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.FLAGS_MERGE",
         "PublicDescription": "Number of flags-merge uops allocated. Such uops add delay.",
@@ -1212,8 +970,6 @@
     },
     {
         "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.SINGLE_MUL",
         "PublicDescription": "Number of multiply packed/scalar single precision uops allocated.",
@@ -1222,8 +978,6 @@
     },
     {
         "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.SLOW_LEA",
         "PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (for example, 2 sources + immediate) regardless of whether it is a result of LEA instruction or not.",
@@ -1232,8 +986,6 @@
     },
     {
         "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -1243,8 +995,6 @@
     },
     {
         "BriefDescription": "Actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ALL",
         "PEBS": "1",
@@ -1255,8 +1005,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles without actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",
@@ -1266,8 +1014,6 @@
     },
     {
         "BriefDescription": "Retirement slots used.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
         "PEBS": "1",
@@ -1277,8 +1023,6 @@
     },
     {
         "BriefDescription": "Cycles without actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -1288,8 +1032,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 10 actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "16",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json b/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json
index 56047f9c6f202..183bcac996427 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json
@@ -1,446 +1,627 @@
 [
     {
-        "BriefDescription": "Bounce Control",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA",
-        "EventName": "UNC_C_BOUNCE_CONTROL",
+        "BriefDescription": "LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.CODE_LLC_PREFETCH",
+        "Filter": "filter_opc=0x191",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Uncore Clocks",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_C_CLOCKTICKS",
+        "BriefDescription": "LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.DATA_LLC_PREFETCH",
+        "Filter": "filter_opc=0x192",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Counter 0 Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1F",
-        "EventName": "UNC_C_COUNTER0_OCCUPANCY",
+        "BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.DATA_READ",
+        "Filter": "filter_opc=0x182",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "FaST wire asserted",
-        "Counter": "0,1",
-        "EventCode": "0x9",
-        "EventName": "UNC_C_FAST_ASSERTED",
+        "BriefDescription": "MMIO reads. Derived from unc_c_tor_inserts.miss_opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.MMIO_READ",
+        "Filter": "filter_opc=0x187,filter_nc=1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Cache Lookups; Data Read Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x34",
-        "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
+        "BriefDescription": "MMIO writes. Derived from unc_c_tor_inserts.miss_opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.MMIO_WRITE",
+        "Filter": "filter_opc=0x18f,filter_nc=1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+        "ScaleUnit": "64Bytes",
         "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Cache Lookups; Write Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x34",
-        "EventName": "UNC_C_LLC_LOOKUP.WRITE",
+        "BriefDescription": "PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.PCIE_NON_SNOOP_WRITE",
+        "Filter": "filter_opc=0x1c8,filter_tid=0x3e",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Cache Lookups; External Snoop Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x34",
-        "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
+        "BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.PCIE_READ",
+        "Filter": "filter_opc=0x19e",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x3",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.PCIE_WRITE",
+        "Filter": "filter_opc=0x1c8",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x3",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.RFO_LLC_PREFETCH",
+        "Filter": "filter_opc=0x190",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x3",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.miss_opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.UNCACHEABLE",
+        "Filter": "filter_opc=0x187",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x3",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "L2 demand and L2 prefetch code references to LLC. Derived from unc_c_tor_inserts.opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_REFERENCES.CODE_LLC_PREFETCH",
+        "Filter": "filter_opc=0x181",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x1",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE",
+        "Filter": "filter_opc=0x180,filter_tid=0x3e",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+        "UMask": "0x1",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "PCIe read current. Derived from unc_c_tor_inserts.opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_REFERENCES.PCIE_READ",
+        "Filter": "filter_opc=0x19e",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x1",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "PCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_REFERENCES.PCIE_WRITE",
+        "Filter": "filter_opc=0x1c8,filter_tid=0x3e",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x1",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_REFERENCES.STREAMING_FULL",
+        "Filter": "filter_opc=0x18c",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x1",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode",
+        "EventCode": "0x35",
+        "EventName": "LLC_REFERENCES.STREAMING_PARTIAL",
+        "Filter": "filter_opc=0x18d",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x1",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "Bounce Control",
+        "EventCode": "0xA",
+        "EventName": "UNC_C_BOUNCE_CONTROL",
+        "PerPkg": "1",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "Uncore Clocks",
+        "EventName": "UNC_C_CLOCKTICKS",
+        "PerPkg": "1",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "Counter 0 Occupancy",
+        "EventCode": "0x1F",
+        "EventName": "UNC_C_COUNTER0_OCCUPANCY",
+        "PerPkg": "1",
+        "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0.   The filtering available is found in the control register - threshold, invert and edge detect.   E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "FaST wire asserted",
+        "EventCode": "0x9",
+        "EventName": "UNC_C_FAST_ASSERTED",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles either the local distress or incoming distress signals are asserted.  Incoming distress includes both up and dn.",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "UNC_C_LLC_LOOKUP.ANY",
         "Filter": "filter_state=0x1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ.  This does not include lookups originating from the ISMQ.",
         "ScaleUnit": "64Bytes",
         "UMask": "0x11",
         "Unit": "CBO"
     },
+    {
+        "BriefDescription": "Cache Lookups; Data Read Request",
+        "EventCode": "0x34",
+        "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions",
+        "UMask": "0x3",
+        "Unit": "CBO"
+    },
     {
         "BriefDescription": "Cache Lookups; Lookups that Match NID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "UNC_C_LLC_LOOKUP.NID",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Qualify one of the other subevents by the Target NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.   In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
         "UMask": "0x41",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Cache Lookups; Any Read Request",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "UNC_C_LLC_LOOKUP.READ",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions",
         "UMask": "0x21",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "M line evictions from LLC (writebacks to memory)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
+        "BriefDescription": "Cache Lookups; External Snoop Request",
+        "EventCode": "0x34",
+        "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.",
+        "UMask": "0x9",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Lines Victimized; Lines in E state",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
+        "BriefDescription": "Cache Lookups; Write Requests",
+        "EventCode": "0x34",
+        "EventName": "UNC_C_LLC_LOOKUP.WRITE",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC  This includes all write transactions -- both Cacheable and UC.",
+        "UMask": "0x5",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Lines in S State",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Lines Victimized; Lines in E state",
         "EventCode": "0x37",
-        "EventName": "UNC_C_LLC_VICTIMS.S_STATE",
+        "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x2",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Lines Victimized",
-        "Counter": "0,1,2,3",
         "EventCode": "0x37",
         "EventName": "UNC_C_LLC_VICTIMS.F_STATE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
         "UMask": "0x8",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Lines Victimized; Victimized Lines that Match NID",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Lines Victimized; Lines in S State",
         "EventCode": "0x37",
-        "EventName": "UNC_C_LLC_VICTIMS.NID",
+        "EventName": "UNC_C_LLC_VICTIMS.I_STATE",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x4",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Lines Victimized",
-        "Counter": "0,1,2,3",
         "EventCode": "0x37",
         "EventName": "UNC_C_LLC_VICTIMS.MISS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
         "UMask": "0x10",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_C_MISC.RSPI_WAS_FSE",
+        "BriefDescription": "M line evictions from LLC (writebacks to memory)",
+        "EventCode": "0x37",
+        "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "ScaleUnit": "64Bytes",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Cbo Misc; Write Combining Aliasing",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Lines Victimized; Victimized Lines that Match NID",
+        "EventCode": "0x37",
+        "EventName": "UNC_C_LLC_VICTIMS.NID",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.; Qualify one of the other subevents by the Target NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.   In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+        "UMask": "0x40",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "Lines in S State",
+        "EventCode": "0x37",
+        "EventName": "UNC_C_LLC_VICTIMS.S_STATE",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x4",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=0",
         "EventCode": "0x39",
-        "EventName": "UNC_C_MISC.WC_ALIASING",
+        "EventName": "UNC_C_MISC.CVZERO_PREFETCH_MISS",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Miscellaneous events in the Cbo.",
+        "UMask": "0x20",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Cbo Misc",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Cbo Misc; Clean Victim with raw CV=0",
         "EventCode": "0x39",
-        "EventName": "UNC_C_MISC.STARTED",
+        "EventName": "UNC_C_MISC.CVZERO_PREFETCH_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Miscellaneous events in the Cbo.",
+        "UMask": "0x10",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Cbo Misc; RFO HitS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_C_MISC.RFO_HIT_S",
         "PerPkg": "1",
+        "PublicDescription": "Miscellaneous events in the Cbo.; Number of times that an RFO hit in S state.  This is useful for determining if it might be good for a workload to use RspIWB instead of RspSWB.",
         "UMask": "0x8",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Cbo Misc; Clean Victim with raw CV=0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
         "EventCode": "0x39",
-        "EventName": "UNC_C_MISC.CVZERO_PREFETCH_VICTIM",
+        "EventName": "UNC_C_MISC.RSPI_WAS_FSE",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction.  This is useful because this information is lost in the PRE encodings.",
+        "UMask": "0x1",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Cbo Misc",
         "EventCode": "0x39",
-        "EventName": "UNC_C_MISC.CVZERO_PREFETCH_MISS",
+        "EventName": "UNC_C_MISC.STARTED",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Miscellaneous events in the Cbo.",
+        "UMask": "0x4",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "Cbo Misc; Write Combining Aliasing",
+        "EventCode": "0x39",
+        "EventName": "UNC_C_MISC.WC_ALIASING",
+        "PerPkg": "1",
+        "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write.  This occurs when there is WC aliasing.",
+        "UMask": "0x2",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "LRU Queue; LRU Age 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "UNC_C_QLRU.AGE0",
         "PerPkg": "1",
+        "PublicDescription": "How often age was set to 0",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "LRU Queue; LRU Age 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "UNC_C_QLRU.AGE1",
         "PerPkg": "1",
+        "PublicDescription": "How often age was set to 1",
         "UMask": "0x2",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "LRU Queue; LRU Age 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "UNC_C_QLRU.AGE2",
         "PerPkg": "1",
+        "PublicDescription": "How often age was set to 2",
         "UMask": "0x4",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "LRU Queue; LRU Age 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "UNC_C_QLRU.AGE3",
         "PerPkg": "1",
+        "PublicDescription": "How often age was set to 3",
         "UMask": "0x8",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "LRU Queue; LRU Bits Decremented",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "UNC_C_QLRU.LRU_DECREMENT",
         "PerPkg": "1",
+        "PublicDescription": "How often all LRU bits were decremented by 1",
         "UMask": "0x10",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "LRU Queue; Non-0 Aged Victim",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "UNC_C_QLRU.VICTIM_NON_ZERO",
         "PerPkg": "1",
+        "PublicDescription": "How often we picked a victim that had a non-zero age",
         "UMask": "0x20",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "AD Ring In Use; Up and Even",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "AD Ring In Use; All",
         "EventCode": "0x1B",
-        "EventName": "UNC_C_RING_AD_USED.UP_EVEN",
+        "EventName": "UNC_C_RING_AD_USED.ALL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0xf",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "AD Ring In Use; Up and Odd",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "AD Ring In Use; Down",
         "EventCode": "0x1B",
-        "EventName": "UNC_C_RING_AD_USED.UP_ODD",
+        "EventName": "UNC_C_RING_AD_USED.DOWN",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0xc",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "AD Ring In Use; Down and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_C_RING_AD_USED.DOWN_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
         "UMask": "0x4",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "AD Ring In Use; Down and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_C_RING_AD_USED.DOWN_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "AD Ring In Use; Up",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_C_RING_AD_USED.UP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
         "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "AD Ring In Use; Down",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "AD Ring In Use; Up and Even",
         "EventCode": "0x1B",
-        "EventName": "UNC_C_RING_AD_USED.DOWN",
+        "EventName": "UNC_C_RING_AD_USED.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "AD Ring In Use; All",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "AD Ring In Use; Up and Odd",
         "EventCode": "0x1B",
-        "EventName": "UNC_C_RING_AD_USED.ALL",
+        "EventName": "UNC_C_RING_AD_USED.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+        "UMask": "0x2",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "AK Ring In Use; Up and Even",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "AK Ring In Use; All",
         "EventCode": "0x1C",
-        "EventName": "UNC_C_RING_AK_USED.UP_EVEN",
+        "EventName": "UNC_C_RING_AK_USED.ALL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0xf",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "AK Ring In Use; Up and Odd",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "AK Ring In Use; Down",
         "EventCode": "0x1C",
-        "EventName": "UNC_C_RING_AK_USED.UP_ODD",
+        "EventName": "UNC_C_RING_AK_USED.DOWN",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0xc",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "AK Ring In Use; Down and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_C_RING_AK_USED.DOWN_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
         "UMask": "0x4",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "AK Ring In Use; Down and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_C_RING_AK_USED.DOWN_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "AK Ring In Use; Up",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_C_RING_AK_USED.UP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
         "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "AK Ring In Use; Down",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "AK Ring In Use; Up and Even",
         "EventCode": "0x1C",
-        "EventName": "UNC_C_RING_AK_USED.DOWN",
+        "EventName": "UNC_C_RING_AK_USED.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "AK Ring In Use; All",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "AK Ring In Use; Up and Odd",
         "EventCode": "0x1C",
-        "EventName": "UNC_C_RING_AK_USED.ALL",
+        "EventName": "UNC_C_RING_AK_USED.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+        "UMask": "0x2",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "BL Ring in Use; Up and Even",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "BL Ring in Use; Down",
         "EventCode": "0x1D",
-        "EventName": "UNC_C_RING_BL_USED.UP_EVEN",
+        "EventName": "UNC_C_RING_BL_USED.ALL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0xf",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "BL Ring in Use; Up and Odd",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "BL Ring in Use; Down",
         "EventCode": "0x1D",
-        "EventName": "UNC_C_RING_BL_USED.UP_ODD",
+        "EventName": "UNC_C_RING_BL_USED.DOWN",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0xc",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Down and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_C_RING_BL_USED.DOWN_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
         "UMask": "0x4",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Down and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_C_RING_BL_USED.DOWN_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Up",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_C_RING_BL_USED.UP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
         "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "BL Ring in Use; Down",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "BL Ring in Use; Up and Even",
         "EventCode": "0x1D",
-        "EventName": "UNC_C_RING_BL_USED.DOWN",
+        "EventName": "UNC_C_RING_BL_USED.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "BL Ring in Use; Down",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "BL Ring in Use; Up and Odd",
         "EventCode": "0x1D",
-        "EventName": "UNC_C_RING_BL_USED.ALL",
+        "EventName": "UNC_C_RING_BL_USED.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+        "UMask": "0x2",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.; AD",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_C_RING_BOUNCES.AD",
         "PerPkg": "1",
@@ -449,7 +630,6 @@
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.; AK",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_C_RING_BOUNCES.AK",
         "PerPkg": "1",
@@ -458,7 +638,6 @@
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.; BL",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_C_RING_BOUNCES.BL",
         "PerPkg": "1",
@@ -466,8 +645,7 @@
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
         "EventCode": "0x5",
         "EventName": "UNC_C_RING_BOUNCES.IV",
         "PerPkg": "1",
@@ -476,43 +654,42 @@
     },
     {
         "BriefDescription": "BL Ring in Use; Any",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
         "EventName": "UNC_C_RING_IV_USED.ANY",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in HSX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+        "UMask": "0xf",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Any",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
-        "EventName": "UNC_C_RING_IV_USED.UP",
+        "EventName": "UNC_C_RING_IV_USED.DN",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in HSX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+        "UMask": "0xc",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Down",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
         "EventName": "UNC_C_RING_IV_USED.DOWN",
         "PerPkg": "1",
-        "UMask": "0xCC",
+        "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in HSX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters for Down polarity",
+        "UMask": "0xcc",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Any",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
-        "EventName": "UNC_C_RING_IV_USED.DN",
+        "EventName": "UNC_C_RING_IV_USED.UP",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring in HSX  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+        "UMask": "0x3",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "UNC_C_RING_SINK_STARVED.AD",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_C_RING_SINK_STARVED.AD",
         "PerPkg": "1",
@@ -521,7 +698,6 @@
     },
     {
         "BriefDescription": "UNC_C_RING_SINK_STARVED.AK",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_C_RING_SINK_STARVED.AK",
         "PerPkg": "1",
@@ -529,396 +705,404 @@
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "UNC_C_RING_SINK_STARVED.IV",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "UNC_C_RING_SINK_STARVED.BL",
         "EventCode": "0x6",
-        "EventName": "UNC_C_RING_SINK_STARVED.IV",
+        "EventName": "UNC_C_RING_SINK_STARVED.BL",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0x4",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "UNC_C_RING_SINK_STARVED.BL",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "UNC_C_RING_SINK_STARVED.IV",
         "EventCode": "0x6",
-        "EventName": "UNC_C_RING_SINK_STARVED.BL",
+        "EventName": "UNC_C_RING_SINK_STARVED.IV",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0x8",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic.",
         "EventCode": "0x7",
         "EventName": "UNC_C_RING_SRC_THRTL",
         "PerPkg": "1",
         "Unit": "CBO"
     },
+    {
+        "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ",
+        "EventCode": "0x12",
+        "EventName": "UNC_C_RxR_EXT_STARVED.IPQ",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally startved and therefore we are blocking the IRQ.",
+        "UMask": "0x2",
+        "Unit": "CBO"
+    },
     {
         "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_C_RxR_EXT_STARVED.IRQ",
         "PerPkg": "1",
+        "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; IRQ is externally starved and therefore we are blocking the IPQ.",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID",
         "EventCode": "0x12",
-        "EventName": "UNC_C_RxR_EXT_STARVED.IPQ",
+        "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.; Number of times that the ISMQ Bid.",
+        "UMask": "0x8",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Ingress Arbiter Blocking Cycles; PRQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_C_RxR_EXT_STARVED.PRQ",
         "PerPkg": "1",
+        "PublicDescription": "Counts cycles in external starvation.  This occurs when one of the ingress queues is being starved by the other queues.",
         "UMask": "0x4",
         "Unit": "CBO"
     },
-    {
-        "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
+    {
+        "BriefDescription": "Ingress Allocations; IPQ",
+        "EventCode": "0x13",
+        "EventName": "UNC_C_RxR_INSERTS.IPQ",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x4",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Ingress Allocations; IRQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_C_RxR_INSERTS.IRQ",
         "PerPkg": "1",
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Ingress Allocations; IRQ Rejected",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_C_RxR_INSERTS.IRQ_REJ",
         "PerPkg": "1",
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
         "UMask": "0x2",
         "Unit": "CBO"
     },
-    {
-        "BriefDescription": "Ingress Allocations; IPQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_C_RxR_INSERTS.IPQ",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "CBO"
-    },
     {
         "BriefDescription": "Ingress Allocations; PRQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_C_RxR_INSERTS.PRQ",
         "PerPkg": "1",
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
         "UMask": "0x10",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Ingress Allocations; PRQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_C_RxR_INSERTS.PRQ_REJ",
         "PerPkg": "1",
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
         "UMask": "0x20",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Ingress Internal Starvation Cycles; IRQ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Ingress Internal Starvation Cycles; IPQ",
         "EventCode": "0x14",
-        "EventName": "UNC_C_RxR_INT_STARVED.IRQ",
+        "EventName": "UNC_C_RxR_INT_STARVED.IPQ",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IPQ in Internal Starvation.",
+        "UMask": "0x4",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Ingress Internal Starvation Cycles; IPQ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Ingress Internal Starvation Cycles; IRQ",
         "EventCode": "0x14",
-        "EventName": "UNC_C_RxR_INT_STARVED.IPQ",
+        "EventName": "UNC_C_RxR_INT_STARVED.IRQ",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IRQ in Internal Starvation.",
+        "UMask": "0x1",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_C_RxR_INT_STARVED.ISMQ",
         "PerPkg": "1",
+        "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the ISMQ in Internal Starvation.",
         "UMask": "0x8",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Ingress Internal Starvation Cycles; PRQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_C_RxR_INT_STARVED.PRQ",
         "PerPkg": "1",
+        "PublicDescription": "Counts cycles in internal starvation.  This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.",
         "UMask": "0x10",
         "Unit": "CBO"
     },
+    {
+        "BriefDescription": "Probe Queue Retries; Address Conflict",
+        "EventCode": "0x31",
+        "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
+        "PerPkg": "1",
+        "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from an address conflicts.  Address conflicts out of the IPQ should be rare.  They will generally only occur if two different sockets are sending requests to the same address at the same time.  This is a true conflict case, unlike the IPQ Address Conflict which is commonly caused by prefetching characteristics.",
+        "UMask": "0x4",
+        "Unit": "CBO"
+    },
     {
         "BriefDescription": "Probe Queue Retries; Any Reject",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_C_RxR_IPQ_RETRY.ANY",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject.  TOR rejects from the IPQ can be caused by the Egress being full or Address Conflicts.",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Probe Queue Retries; No Egress Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_C_RxR_IPQ_RETRY.FULL",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from the Egress being full.  IPQ requests make use of the AD Egress for regular responses, the BL egress to forward data, and the AK egress to return credits.",
         "UMask": "0x2",
         "Unit": "CBO"
     },
-    {
-        "BriefDescription": "Probe Queue Retries; Address Conflict",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x31",
-        "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "CBO"
-    },
     {
         "BriefDescription": "Probe Queue Retries; No QPI Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.",
         "UMask": "0x10",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Probe Queue Retries; No AD Sbo Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "UNC_C_RxR_IPQ_RETRY2.AD_SBO",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo.",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Probe Queue Retries; Target Node Filter",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "UNC_C_RxR_IPQ_RETRY2.TARGET",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a snoop (probe) request had to retry.  Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
         "UMask": "0x40",
         "Unit": "CBO"
     },
+    {
+        "BriefDescription": "Ingress Request Queue Rejects; Address Conflict",
+        "EventCode": "0x32",
+        "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that a request from the IRQ was retried because of an address match in the TOR.  In order to maintain coherency, requests to the same address are not allowed to pass each other up in the Cbo.  Therefore, if there is an outstanding request to a given address, one cannot issue another request to that address until it is complete.  This comes up most commonly with prefetches.  Outstanding prefetches occasionally will not complete their memory fetch and a demand request to the same address will then sit in the IRQ and get retried until the prefetch fills the data into the LLC.  Therefore, it will not be uncommon to see this case in high bandwidth streaming workloads when the LLC Prefetcher in the core is enabled.",
+        "UMask": "0x4",
+        "Unit": "CBO"
+    },
     {
         "BriefDescription": "Ingress Request Queue Rejects; Any Reject",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.ANY",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of IRQ retries that occur.  Requests from the IRQ are retried if they are rejected from the TOR pipeline for a variety of reasons.  Some of the most common reasons include if the Egress is full, there are no RTIDs, or there is a Physical Address match to another outstanding request.",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; No Egress Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.FULL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that a request from the IRQ was retried because it failed to acquire an entry in the Egress.  The egress is the buffer that queues up for allocating onto the ring.  IRQ requests can make use of all four rings and all four Egresses.  If any of the queues that a given request needs to make use of are full, the request will be retried.",
         "UMask": "0x2",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Ingress Request Queue Rejects; Address Conflict",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits",
         "EventCode": "0x32",
-        "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
+        "EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO.  There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.",
+        "UMask": "0x20",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Ingress Request Queue Rejects; No RTIDs",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Ingress Request Queue Rejects",
         "EventCode": "0x32",
-        "EventName": "UNC_C_RxR_IRQ_RETRY.RTID",
+        "EventName": "UNC_C_RxR_IRQ_RETRY.NID",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Qualify one of the other subevents by a given RTID destination NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
+        "UMask": "0x40",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS",
         "PerPkg": "1",
+        "PublicDescription": "Number of requests rejects because of lack of QPI Ingress credits.  These credits are required in order to send transactions to the QPI agent.  Please see the QPI_IGR_CREDITS events for more information.",
         "UMask": "0x10",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Ingress Request Queue Rejects; No RTIDs",
         "EventCode": "0x32",
-        "EventName": "UNC_C_RxR_IRQ_RETRY.NID",
+        "EventName": "UNC_C_RxR_IRQ_RETRY.RTID",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of times that requests from the IRQ were retried because there were no RTIDs available.  RTIDs are required after a request misses the LLC and needs to send snoops and/or requests to memory.  If there are no RTIDs available, requests will queue up in the IRQ and retry until one becomes available.  Note that there are multiple RTID pools for the different sockets.  There may be cases where the local RTIDs are all used, but requests destined for remote memory can still acquire an RTID because there are remote RTIDs available.  This event does not provide any filtering for this case.",
+        "UMask": "0x8",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; No AD Sbo Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_C_RxR_IRQ_RETRY2.AD_SBO",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo.",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; No BL Sbo Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_C_RxR_IRQ_RETRY2.BL_SBO",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an BL packet to the Sbo.",
         "UMask": "0x2",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; Target Node Filter",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_C_RxR_IRQ_RETRY2.TARGET",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
         "UMask": "0x40",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "ISMQ Retries; Any Reject",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_C_RxR_ISMQ_RETRY.ANY",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the total number of times that a request from the ISMQ retried because of a TOR reject.  ISMQ requests generally will not need to retry (or at least ISMQ retries are less common than IRQ retries).  ISMQ requests will retry if they are not able to acquire a needed Egress credit to get onto the ring, or for cache evictions that need to acquire an RTID.  Most ISMQ requests already have an RTID, so eviction retries will be less common here.",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "ISMQ Retries; No Egress Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_C_RxR_ISMQ_RETRY.FULL",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by a lack of Egress credits. The egress is the buffer that queues up for allocating onto the ring.  If any of the Egress queues that a given request needs to make use of are full, the request will be retried.",
         "UMask": "0x2",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "ISMQ Retries; No RTIDs",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "ISMQ Retries; No IIO Credits",
         "EventCode": "0x33",
-        "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID",
+        "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO.  There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.",
+        "UMask": "0x20",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "ISMQ Retries; No QPI Credits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "ISMQ Retries",
         "EventCode": "0x33",
-        "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
+        "EventName": "UNC_C_RxR_ISMQ_RETRY.NID",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
+        "UMask": "0x40",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "ISMQ Retries; No IIO Credits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "ISMQ Retries; No QPI Credits",
         "EventCode": "0x33",
-        "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
+        "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x10",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "ISMQ Retries",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "ISMQ Retries; No RTIDs",
         "EventCode": "0x33",
-        "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS",
+        "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by no RTIDs.  M-state cache evictions are serviced through the ISMQ, and must acquire an RTID in order to write back to memory.  If no RTIDs are available, they will be retried.",
+        "UMask": "0x8",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "ISMQ Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
-        "EventName": "UNC_C_RxR_ISMQ_RETRY.NID",
+        "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
+        "UMask": "0x80",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "ISMQ Request Queue Rejects; No AD Sbo Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_C_RxR_ISMQ_RETRY2.AD_SBO",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an AD packet to the Sbo.",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "ISMQ Request Queue Rejects; No BL Sbo Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_C_RxR_ISMQ_RETRY2.BL_SBO",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an BL packet to the Sbo.",
         "UMask": "0x2",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "ISMQ Request Queue Rejects; Target Node Filter",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_C_RxR_ISMQ_RETRY2.TARGET",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that a request from the ISMQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
         "UMask": "0x40",
         "Unit": "CBO"
     },
+    {
+        "BriefDescription": "Ingress Occupancy; IPQ",
+        "EventCode": "0x11",
+        "EventName": "UNC_C_RxR_OCCUPANCY.IPQ",
+        "PerPkg": "1",
+        "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+        "UMask": "0x4",
+        "Unit": "CBO"
+    },
     {
         "BriefDescription": "Ingress Occupancy; IRQ",
         "EventCode": "0x11",
         "EventName": "UNC_C_RxR_OCCUPANCY.IRQ",
         "PerPkg": "1",
+        "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Ingress Occupancy; IPQ",
+        "BriefDescription": "Ingress Occupancy; IRQ Rejected",
         "EventCode": "0x11",
-        "EventName": "UNC_C_RxR_OCCUPANCY.IPQ",
+        "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJ",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+        "UMask": "0x2",
         "Unit": "CBO"
     },
     {
@@ -926,24 +1110,25 @@
         "EventCode": "0x11",
         "EventName": "UNC_C_RxR_OCCUPANCY.PRQ_REJ",
         "PerPkg": "1",
+        "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
         "UMask": "0x20",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "SBo Credits Acquired; For AD Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3D",
         "EventName": "UNC_C_SBO_CREDITS_ACQUIRED.AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo credits acquired in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "SBo Credits Acquired; For BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3D",
         "EventName": "UNC_C_SBO_CREDITS_ACQUIRED.BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo credits acquired in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
         "UMask": "0x2",
         "Unit": "CBO"
     },
@@ -952,6 +1137,7 @@
         "EventCode": "0x3E",
         "EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo credits in use in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
         "UMask": "0x1",
         "Unit": "CBO"
     },
@@ -960,361 +1146,188 @@
         "EventCode": "0x3E",
         "EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo credits in use in a given cycle, per ring.  Each Cbo is assigned an Sbo it can communicate with.",
         "UMask": "0x2",
         "Unit": "CBO"
     },
-    {
-        "BriefDescription": "TOR Inserts; Opcode Match",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.OPCODE",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE",
-        "Filter": "filter_opc=0x180,filter_tid=0x3e",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "L2 demand and L2 prefetch code references to LLC. Derived from unc_c_tor_inserts.opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "LLC_REFERENCES.CODE_LLC_PREFETCH",
-        "Filter": "filter_opc=0x181",
-        "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x1",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "LLC_REFERENCES.STREAMING_FULL",
-        "Filter": "filter_opc=0x18c",
-        "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x1",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "LLC_REFERENCES.STREAMING_PARTIAL",
-        "Filter": "filter_opc=0x18d",
-        "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x1",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "PCIe read current. Derived from unc_c_tor_inserts.opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "LLC_REFERENCES.PCIE_READ",
-        "Filter": "filter_opc=0x19e",
-        "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x1",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "PCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "LLC_REFERENCES.PCIE_WRITE",
-        "Filter": "filter_opc=0x1c8,filter_tid=0x3e",
-        "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x1",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "TOR Inserts; Evictions",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.EVICTION",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "CBO"
-    },
     {
         "BriefDescription": "TOR Inserts; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.ALL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR.    This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues.  The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger.  Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20.  Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.",
         "UMask": "0x8",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; Writebacks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.WB",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "TOR Inserts; Miss Opcode Match",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE",
-        "PerPkg": "1",
-        "UMask": "0x3",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "LLC_MISSES.DATA_READ",
-        "Filter": "filter_opc=0x182",
-        "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x3",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.miss_opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "LLC_MISSES.UNCACHEABLE",
-        "Filter": "filter_opc=0x187",
-        "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x3",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "MMIO reads. Derived from unc_c_tor_inserts.miss_opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "LLC_MISSES.MMIO_READ",
-        "Filter": "filter_opc=0x187,filter_nc=1",
-        "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x3",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "MMIO writes. Derived from unc_c_tor_inserts.miss_opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "LLC_MISSES.MMIO_WRITE",
-        "Filter": "filter_opc=0x18f,filter_nc=1",
-        "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x3",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; Evictions",
         "EventCode": "0x35",
-        "EventName": "LLC_MISSES.RFO_LLC_PREFETCH",
-        "Filter": "filter_opc=0x190",
+        "EventName": "UNC_C_TOR_INSERTS.EVICTION",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Eviction transactions inserted into the TOR.  Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set.  They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).",
+        "UMask": "0x4",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; Local Memory",
         "EventCode": "0x35",
-        "EventName": "LLC_MISSES.CODE_LLC_PREFETCH",
-        "Filter": "filter_opc=0x191",
+        "EventName": "UNC_C_TOR_INSERTS.LOCAL",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR that are satisfied by locally HOMed memory.",
+        "UMask": "0x28",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched",
         "EventCode": "0x35",
-        "EventName": "LLC_MISSES.DATA_LLC_PREFETCH",
-        "Filter": "filter_opc=0x192",
+        "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions, satisfied by an opcode,  inserted into the TOR that are satisfied by locally HOMed memory.",
+        "UMask": "0x21",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; Misses to Local Memory",
         "EventCode": "0x35",
-        "EventName": "LLC_MISSES.PCIE_READ",
-        "Filter": "filter_opc=0x19e",
+        "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by locally HOMed memory.",
+        "UMask": "0x2a",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_opcode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched",
         "EventCode": "0x35",
-        "EventName": "LLC_MISSES.PCIE_WRITE",
-        "Filter": "filter_opc=0x1c8",
+        "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory.",
+        "UMask": "0x23",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opcode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; Miss Opcode Match",
         "EventCode": "0x35",
-        "EventName": "LLC_MISSES.PCIE_NON_SNOOP_WRITE",
-        "Filter": "filter_opc=0x1c8,filter_tid=0x3e",
+        "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
         "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; NID and Opcode Matched",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; Misses to Remote Memory",
         "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE",
+        "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x41",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by remote caches or remote memory.",
+        "UMask": "0x8a",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; NID Matched Evictions",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched",
         "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION",
+        "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions, satisfied by an opcode,  inserted into the TOR that are satisfied by remote caches or remote memory.",
+        "UMask": "0x83",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "TOR Inserts; NID Matched",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.NID_ALL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.  In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
         "UMask": "0x48",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; NID Matched Writebacks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; NID Matched Evictions",
         "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.NID_WB",
+        "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION",
         "PerPkg": "1",
-        "UMask": "0x50",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; NID matched eviction transactions inserted into the TOR.",
+        "UMask": "0x44",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; NID Matched Miss All",
         "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
+        "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL",
         "PerPkg": "1",
-        "UMask": "0x43",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.",
+        "UMask": "0x4a",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; NID Matched Miss All",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss",
         "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL",
+        "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
         "PerPkg": "1",
-        "UMask": "0x4A",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode.",
+        "UMask": "0x43",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; Misses to Local Memory",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; NID and Opcode Matched",
         "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL",
+        "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE",
         "PerPkg": "1",
-        "UMask": "0x2A",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode.",
+        "UMask": "0x41",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; Misses to Remote Memory",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; NID Matched Writebacks",
         "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE",
+        "EventName": "UNC_C_TOR_INSERTS.NID_WB",
         "PerPkg": "1",
-        "UMask": "0x8A",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; NID matched write transactions inserted into the TOR.",
+        "UMask": "0x50",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; Local Memory",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; Opcode Match",
         "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.LOCAL",
+        "EventName": "UNC_C_TOR_INSERTS.OPCODE",
         "PerPkg": "1",
-        "UMask": "0x28",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+        "UMask": "0x1",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "TOR Inserts; Remote Memory",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.REMOTE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions inserted into the TOR that are satisfied by remote caches or remote memory.",
         "UMask": "0x88",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE",
-        "PerPkg": "1",
-        "UMask": "0x23",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE",
-        "PerPkg": "1",
-        "UMask": "0x83",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched",
         "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE",
+        "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All transactions, satisfied by an opcode,  inserted into the TOR that are satisfied by remote caches or remote memory.",
+        "UMask": "0x81",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "TOR Inserts; Writebacks",
         "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE",
+        "EventName": "UNC_C_TOR_INSERTS.WB",
         "PerPkg": "1",
-        "UMask": "0x81",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Write transactions inserted into the TOR.   This does not include RFO, but actual operations that contain data being sent from the core.",
+        "UMask": "0x10",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Occupancy; Opcode Match",
+        "BriefDescription": "TOR Occupancy; Any",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE",
+        "EventName": "UNC_C_TOR_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All valid TOR entries.  This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues.  The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger.  Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20.  Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.",
+        "UMask": "0x8",
         "Unit": "CBO"
     },
     {
@@ -1322,33 +1335,36 @@
         "EventCode": "0x36",
         "EventName": "UNC_C_TOR_OCCUPANCY.EVICTION",
         "PerPkg": "1",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding eviction transactions in the TOR.  Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set.  They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).",
         "UMask": "0x4",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Occupancy; Any",
+        "BriefDescription": "Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.ALL",
+        "EventName": "UNC_C_TOR_OCCUPANCY.LLC_DATA_READ",
+        "Filter": "filter_opc=0x182",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO.",
+        "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode",
+        "BriefDescription": "TOR Occupancy",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.LLC_DATA_READ",
-        "Filter": "filter_opc=0x182",
+        "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+        "UMask": "0x28",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Occupancy counter for LLC data reads (demand and L2 prefetch)",
+        "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE",
-        "Filter": "filter_opc=0x182",
+        "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding  transactions, satisfied by an opcode,  in the TOR that are satisfied by locally HOMed memory.",
+        "UMask": "0x21",
         "Unit": "CBO"
     },
     {
@@ -1356,103 +1372,125 @@
         "EventCode": "0x36",
         "EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR.  'Miss' means the allocation requires an RTID.  This generally means that the request was sent to memory or MMIO.",
+        "UMask": "0xa",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Occupancy; NID and Opcode Matched",
+        "BriefDescription": "TOR Occupancy",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE",
+        "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x41",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+        "UMask": "0x2a",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Occupancy; NID Matched Evictions",
+        "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcode Matched",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION",
+        "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by locally HOMed memory.",
+        "UMask": "0x23",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Occupancy; NID Matched",
+        "BriefDescription": "TOR Occupancy; Miss Opcode Match",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL",
+        "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE",
         "PerPkg": "1",
-        "UMask": "0x48",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO.",
+        "UMask": "0x3",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss",
+        "BriefDescription": "TOR Occupancy",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE",
+        "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x43",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+        "UMask": "0x8a",
+        "Unit": "CBO"
+    },
+    {
+        "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opcode Matched",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE",
+        "PerPkg": "1",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by remote caches or remote memory.",
+        "UMask": "0x83",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "TOR Occupancy; NID Matched",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
+        "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL",
         "PerPkg": "1",
-        "UMask": "0x4A",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of NID matched outstanding requests in the TOR.  The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+        "UMask": "0x48",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Occupancy",
+        "BriefDescription": "TOR Occupancy; NID Matched Evictions",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL",
+        "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION",
         "PerPkg": "1",
-        "UMask": "0x2A",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding NID matched eviction transactions in the TOR .",
+        "UMask": "0x44",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Occupancy",
+        "BriefDescription": "TOR Occupancy; NID Matched",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE",
+        "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
         "PerPkg": "1",
-        "UMask": "0x8A",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID.",
+        "UMask": "0x4a",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Occupancy",
+        "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL",
+        "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE",
         "PerPkg": "1",
-        "UMask": "0x28",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID and an opcode.",
+        "UMask": "0x43",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Occupancy",
+        "BriefDescription": "TOR Occupancy; NID and Opcode Matched",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE",
+        "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE",
         "PerPkg": "1",
-        "UMask": "0x88",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match a NID and an opcode.",
+        "UMask": "0x41",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcode Matched",
+        "BriefDescription": "TOR Occupancy; NID Matched Writebacks",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE",
+        "EventName": "UNC_C_TOR_OCCUPANCY.NID_WB",
         "PerPkg": "1",
-        "UMask": "0x23",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); NID matched write transactions int the TOR.",
+        "UMask": "0x50",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opcode Matched",
+        "BriefDescription": "TOR Occupancy; Opcode Match",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE",
+        "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE",
         "PerPkg": "1",
-        "UMask": "0x83",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc).",
+        "UMask": "0x1",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched",
+        "BriefDescription": "TOR Occupancy",
         "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE",
+        "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+        "UMask": "0x88",
         "Unit": "CBO"
     },
     {
@@ -1460,6 +1498,7 @@
         "EventCode": "0x36",
         "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE",
         "PerPkg": "1",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding  transactions, satisfied by an opcode,  in the TOR that are satisfied by remote caches or remote memory.",
         "UMask": "0x81",
         "Unit": "CBO"
     },
@@ -1468,20 +1507,12 @@
         "EventCode": "0x36",
         "EventName": "UNC_C_TOR_OCCUPANCY.WB",
         "PerPkg": "1",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Write transactions in the TOR.   This does not include RFO, but actual operations that contain data being sent from the core.",
         "UMask": "0x10",
         "Unit": "CBO"
     },
-    {
-        "BriefDescription": "TOR Occupancy; NID Matched Writebacks",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.NID_WB",
-        "PerPkg": "1",
-        "UMask": "0x50",
-        "Unit": "CBO"
-    },
     {
         "BriefDescription": "Onto AD Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_C_TxR_ADS_USED.AD",
         "PerPkg": "1",
@@ -1490,7 +1521,6 @@
     },
     {
         "BriefDescription": "Onto AK Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_C_TxR_ADS_USED.AK",
         "PerPkg": "1",
@@ -1499,7 +1529,6 @@
     },
     {
         "BriefDescription": "Onto BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_C_TxR_ADS_USED.BL",
         "PerPkg": "1",
@@ -1508,386 +1537,307 @@
     },
     {
         "BriefDescription": "Egress Allocations; AD - Cachebo",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.AD_CACHE",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
         "UMask": "0x1",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Egress Allocations; AK - Cachebo",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_C_TxR_INSERTS.AK_CACHE",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "Egress Allocations; BL - Cacheno",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_C_TxR_INSERTS.BL_CACHE",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "Egress Allocations; IV - Cachebo",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Egress Allocations; AD - Corebo",
         "EventCode": "0x2",
-        "EventName": "UNC_C_TxR_INSERTS.IV_CACHE",
+        "EventName": "UNC_C_TxR_INSERTS.AD_CORE",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Egress Allocations; AD - Corebo",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Egress Allocations; AK - Cachebo",
         "EventCode": "0x2",
-        "EventName": "UNC_C_TxR_INSERTS.AD_CORE",
+        "EventName": "UNC_C_TxR_INSERTS.AK_CACHE",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Egress Allocations; AK - Corebo",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.AK_CORE",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AK ring.  This is commonly used for snoop responses coming from the core and destined for a Cachebo.",
         "UMask": "0x20",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Egress Allocations; BL - Corebo",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Egress Allocations; BL - Cacheno",
         "EventCode": "0x2",
-        "EventName": "UNC_C_TxR_INSERTS.BL_CORE",
-        "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CBO"
-    },
-    {
-        "BriefDescription": "Injection Starvation; Onto AK Ring",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_C_TxR_STARVED.AK_BOTH",
+        "EventName": "UNC_C_TxR_INSERTS.BL_CACHE",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Injection Starvation; Onto BL Ring",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_C_TxR_STARVED.BL_BOTH",
+        "BriefDescription": "Egress Allocations; BL - Corebo",
+        "EventCode": "0x2",
+        "EventName": "UNC_C_TxR_INSERTS.BL_CORE",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Injection Starvation; Onto IV Ring",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_C_TxR_STARVED.IV",
+        "BriefDescription": "Egress Allocations; IV - Cachebo",
+        "EventCode": "0x2",
+        "EventName": "UNC_C_TxR_INSERTS.IV_CACHE",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Cbo Egress.  The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the IV ring.  This is commonly used for snoops to the cores.",
         "UMask": "0x8",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Injection Starvation; Onto AD Ring (to core)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_C_TxR_STARVED.AD_CORE",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the core AD egress spent in starvation",
         "UMask": "0x10",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Ingress Occupancy; IRQ Rejected",
-        "EventCode": "0x11",
-        "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJ",
+        "BriefDescription": "Injection Starvation; Onto AK Ring",
+        "EventCode": "0x3",
+        "EventName": "UNC_C_TxR_STARVED.AK_BOTH",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both AK egresses spent in starvation",
         "UMask": "0x2",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "Lines Victimized; Lines in S State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_C_LLC_VICTIMS.I_STATE",
+        "BriefDescription": "Injection Starvation; Onto BL Ring",
+        "EventCode": "0x3",
+        "EventName": "UNC_C_TxR_STARVED.BL_BOTH",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both BL egresses spent in starvation",
         "UMask": "0x4",
         "Unit": "CBO"
     },
     {
-        "BriefDescription": "QPI Address/Opcode Match; Address & Opcode Match",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_H_ADDR_OPC_MATCH.FILT",
-        "PerPkg": "1",
-        "UMask": "0x3",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "QPI Address/Opcode Match; Address",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_H_ADDR_OPC_MATCH.ADDR",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "QPI Address/Opcode Match; Opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_H_ADDR_OPC_MATCH.OPC",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "QPI Address/Opcode Match; AD Opcodes",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_H_ADDR_OPC_MATCH.AD",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "QPI Address/Opcode Match; BL Opcodes",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_H_ADDR_OPC_MATCH.BL",
+        "BriefDescription": "Injection Starvation; Onto IV Ring",
+        "EventCode": "0x3",
+        "EventName": "UNC_C_TxR_STARVED.IV",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the cachebo IV egress spent in starvation",
         "UMask": "0x8",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "QPI Address/Opcode Match; AK Opcodes",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_H_ADDR_OPC_MATCH.AK",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "HA"
+        "Unit": "CBO"
     },
     {
         "BriefDescription": "BT Cycles Not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0x42",
         "EventName": "UNC_H_BT_CYCLES_NE",
         "PerPkg": "1",
+        "PublicDescription": "Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT.",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
         "EventCode": "0x51",
-        "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD",
+        "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard",
         "EventCode": "0x51",
-        "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD",
+        "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming snoop hazard",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
-        "Counter": "0,1,2,3",
         "EventCode": "0x51",
         "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
         "UMask": "0x8",
         "Unit": "HA"
     },
     {
         "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
-        "Counter": "0,1,2,3",
         "EventCode": "0x51",
         "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
         "UMask": "0x10",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA to iMC Bypass; Taken",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "HA to iMC Bypass; Not Taken",
         "EventCode": "0x14",
-        "EventName": "UNC_H_BYPASS_IMC.TAKEN",
+        "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass.",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA to iMC Bypass; Not Taken",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "HA to iMC Bypass; Taken",
         "EventCode": "0x14",
-        "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN",
+        "EventName": "UNC_H_BYPASS_IMC.TAKEN",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filted by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass.",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "uclks",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_H_CLOCKTICKS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of uclks in the HA.  This will be slightly different than the count in the Ubox because of enable/freeze delays.  The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Direct2Core Messages Sent",
-        "Counter": "0,1,2,3",
         "EventCode": "0x11",
         "EventName": "UNC_H_DIRECT2CORE_COUNT",
         "PerPkg": "1",
+        "PublicDescription": "Number of Direct2Core messages sent",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Cycles when Direct2Core was Disabled",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles in which Direct2Core was disabled",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Number of Reads that had Direct2Core Overridden",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE",
         "PerPkg": "1",
+        "PublicDescription": "Number of Reads where Direct2Core overridden",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Directory Lat Opt Return",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_H_DIRECTORY_LAT_OPT",
         "PerPkg": "1",
+        "PublicDescription": "Directory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory returned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc).",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Directory Lookups; Snoop Needed",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Directory Lookups; Snoop Not Needed",
         "EventCode": "0xC",
-        "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP",
+        "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that did not have to send any snoops because the directory bit was clear.",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Directory Lookups; Snoop Not Needed",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Directory Lookups; Snoop Needed",
         "EventCode": "0xC",
-        "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP",
+        "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that had to send one or more snoops because the directory bit was set.",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Directory Updates; Directory Set",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Directory Updates; Any Directory Update",
         "EventCode": "0xD",
-        "EventName": "UNC_H_DIRECTORY_UPDATE.SET",
+        "EventName": "UNC_H_DIRECTORY_UPDATE.ANY",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.",
+        "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Directory Updates; Directory Clear",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD",
         "EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.; Filter for directory clears.  This occurs when snoops were sent and all returned with RspI.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Directory Updates; Any Directory Update",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Directory Updates; Directory Set",
         "EventCode": "0xD",
-        "EventName": "UNC_H_DIRECTORY_UPDATE.ANY",
+        "EventName": "UNC_H_DIRECTORY_UPDATE.SET",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the number of directory updates that were required.  These result in writes to the memory controller.  This can be filtered by directory sets and directory clears.; Filter for directory sets.  This occurs when a remote read transaction requests memory, bringing it to a remote cache.",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is AckCnfltWbI",
         "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.READ_OR_INVITOE",
+        "EventName": "UNC_H_HITME_HIT.ACKCNFLTWBI",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; All Requests",
         "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.WBMTOI",
+        "EventName": "UNC_H_HITME_HIT.ALL",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "UMask": "0xff",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is AckCnfltWbI",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
         "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.ACKCNFLTWBI",
+        "EventName": "UNC_H_HITME_HIT.ALLOCS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0x70",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
         "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.WBMTOE_OR_S",
+        "EventName": "UNC_H_HITME_HIT.EVICTS",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0x42",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; HOM Requests",
         "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.RSPFWDI_REMOTE",
+        "EventName": "UNC_H_HITME_HIT.HOM",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0xf",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; Invalidations",
         "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.RSPFWDI_LOCAL",
+        "EventName": "UNC_H_HITME_HIT.INVALS",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x26",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
         "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.RSPFWDS",
+        "EventName": "UNC_H_HITME_HIT.READ_OR_INVITOE",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "UNC_H_HITME_HIT.RSP",
         "PerPkg": "1",
@@ -1895,98 +1845,87 @@
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
         "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.ALLOCS",
+        "EventName": "UNC_H_HITME_HIT.RSPFWDI_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x70",
+        "UMask": "0x20",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
         "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.EVICTS",
+        "EventName": "UNC_H_HITME_HIT.RSPFWDI_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x42",
+        "UMask": "0x10",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; Invalidations",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb",
         "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.INVALS",
+        "EventName": "UNC_H_HITME_HIT.RSPFWDS",
         "PerPkg": "1",
-        "UMask": "0x26",
+        "UMask": "0x40",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; All Requests",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS",
         "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.ALL",
+        "EventName": "UNC_H_HITME_HIT.WBMTOE_OR_S",
         "PerPkg": "1",
-        "UMask": "0xFF",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; HOM Requests",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI",
         "EventCode": "0x71",
-        "EventName": "UNC_H_HITME_HIT.HOM",
+        "EventName": "UNC_H_HITME_HIT.WBMTOI",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI",
         "EventCode": "0x72",
-        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE",
+        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; All Requests",
         "EventCode": "0x72",
-        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI",
+        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ALL",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "UMask": "0xff",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests",
         "EventCode": "0x72",
-        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI",
+        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.HOM",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0xf",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
         "EventCode": "0x72",
-        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S",
+        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
         "EventCode": "0x72",
-        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE",
+        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x80",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a local request",
-        "Counter": "0,1,2,3",
         "EventCode": "0x72",
         "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL",
         "PerPkg": "1",
@@ -1994,107 +1933,87 @@
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request",
         "EventCode": "0x72",
-        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS",
+        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x10",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb",
         "EventCode": "0x72",
-        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSP",
+        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x40",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; All Requests",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS",
         "EventCode": "0x72",
-        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ALL",
+        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S",
         "PerPkg": "1",
-        "UMask": "0xFF",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI",
         "EventCode": "0x72",
-        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.HOM",
-        "PerPkg": "1",
-        "UMask": "0xF",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x70",
-        "EventName": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE",
+        "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoI",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI",
         "EventCode": "0x70",
-        "EventName": "UNC_H_HITME_LOOKUP.WBMTOI",
+        "EventName": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; All Requests",
         "EventCode": "0x70",
-        "EventName": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI",
+        "EventName": "UNC_H_HITME_LOOKUP.ALL",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0xff",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; Allocations",
         "EventCode": "0x70",
-        "EventName": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S",
+        "EventName": "UNC_H_HITME_LOOKUP.ALLOCS",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0x70",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; HOM Requests",
         "EventCode": "0x70",
-        "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE",
+        "EventName": "UNC_H_HITME_LOOKUP.HOM",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0xf",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; Invalidations",
         "EventCode": "0x70",
-        "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL",
+        "EventName": "UNC_H_HITME_LOOKUP.INVALS",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x26",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
         "EventCode": "0x70",
-        "EventName": "UNC_H_HITME_LOOKUP.RSPFWDS",
+        "EventName": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
-        "Counter": "0,1,2,3",
         "EventCode": "0x70",
         "EventName": "UNC_H_HITME_LOOKUP.RSP",
         "PerPkg": "1",
@@ -2102,1536 +2021,1537 @@
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; Allocations",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request",
         "EventCode": "0x70",
-        "EventName": "UNC_H_HITME_LOOKUP.ALLOCS",
+        "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x70",
+        "UMask": "0x20",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; Invalidations",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request",
         "EventCode": "0x70",
-        "EventName": "UNC_H_HITME_LOOKUP.INVALS",
+        "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x26",
+        "UMask": "0x10",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; All Requests",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb",
         "EventCode": "0x70",
-        "EventName": "UNC_H_HITME_LOOKUP.ALL",
+        "EventName": "UNC_H_HITME_LOOKUP.RSPFWDS",
         "PerPkg": "1",
-        "UMask": "0xFF",
+        "UMask": "0x40",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; HOM Requests",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS",
         "EventCode": "0x70",
-        "EventName": "UNC_H_HITME_LOOKUP.HOM",
+        "EventName": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoI",
+        "EventCode": "0x70",
+        "EventName": "UNC_H_HITME_LOOKUP.WBMTOI",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
-        "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
+        "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+        "UMask": "0x10",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
         "EventCode": "0x22",
-        "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
+        "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
         "EventCode": "0x22",
-        "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2",
+        "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent.  This can be filtered by the different credit pools and the different links.",
         "UMask": "0x20",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA to iMC Normal Priority Reads Issued; Normal Priority",
-        "Counter": "0,1,2,3",
         "EventCode": "0x17",
         "EventName": "UNC_H_IMC_READS.NORMAL",
         "PerPkg": "1",
+        "PublicDescription": "Count of the number of reads issued to any of the memory controller channels.  This can be filtered by the priority of the reads.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Retry Events",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
         "EventName": "UNC_H_IMC_RETRY",
         "PerPkg": "1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes",
         "EventCode": "0x1A",
-        "EventName": "UNC_H_IMC_WRITES.FULL",
+        "EventName": "UNC_H_IMC_WRITES.ALL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+        "UMask": "0xf",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
         "EventCode": "0x1A",
-        "EventName": "UNC_H_IMC_WRITES.PARTIAL",
+        "EventName": "UNC_H_IMC_WRITES.FULL",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full Line",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1A",
         "EventName": "UNC_H_IMC_WRITES.FULL_ISOCH",
         "PerPkg": "1",
+        "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
         "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
         "EventCode": "0x1A",
-        "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH",
+        "EventName": "UNC_H_IMC_WRITES.PARTIAL",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial",
         "EventCode": "0x1A",
-        "EventName": "UNC_H_IMC_WRITES.ALL",
+        "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
         "BriefDescription": "IOT Backpressure",
-        "Counter": "0,1,2",
         "EventCode": "0x61",
-        "EventName": "UNC_H_IOT_BACKPRESSURE.SAT",
+        "EventName": "UNC_H_IOT_BACKPRESSURE.HUB",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "IOT Backpressure",
-        "Counter": "0,1,2",
         "EventCode": "0x61",
-        "EventName": "UNC_H_IOT_BACKPRESSURE.HUB",
+        "EventName": "UNC_H_IOT_BACKPRESSURE.SAT",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "IOT Common Trigger Sequencer - Lo",
-        "Counter": "0,1,2",
         "EventCode": "0x64",
         "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS0",
         "PerPkg": "1",
+        "PublicDescription": "Debug Mask/Match Tie-Ins",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "IOT Common Trigger Sequencer - Lo",
-        "Counter": "0,1,2",
         "EventCode": "0x64",
         "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS1",
         "PerPkg": "1",
+        "PublicDescription": "Debug Mask/Match Tie-Ins",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "IOT Common Trigger Sequencer - Hi",
-        "Counter": "0,1,2",
         "EventCode": "0x65",
         "EventName": "UNC_H_IOT_CTS_HI.CTS2",
         "PerPkg": "1",
+        "PublicDescription": "Debug Mask/Match Tie-Ins",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "IOT Common Trigger Sequencer - Hi",
-        "Counter": "0,1,2",
         "EventCode": "0x65",
         "EventName": "UNC_H_IOT_CTS_HI.CTS3",
         "PerPkg": "1",
+        "PublicDescription": "Debug Mask/Match Tie-Ins",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "IOT Common Trigger Sequencer - Lo",
-        "Counter": "0,1,2",
         "EventCode": "0x62",
         "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS0",
         "PerPkg": "1",
+        "PublicDescription": "Debug Mask/Match Tie-Ins",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "IOT Common Trigger Sequencer - Lo",
-        "Counter": "0,1,2",
         "EventCode": "0x62",
         "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS1",
         "PerPkg": "1",
+        "PublicDescription": "Debug Mask/Match Tie-Ins",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "OSB Snoop Broadcast; Local Reads",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "OSB Snoop Broadcast; Cancelled",
         "EventCode": "0x53",
-        "EventName": "UNC_H_OSB.READS_LOCAL",
+        "EventName": "UNC_H_OSB.CANCELLED",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.; OSB Snoop broadcast cancelled due to D2C or Other. OSB cancel is counted when OSB local read is not allowed even when the transaction in local InItoE. It also counts D2C OSB cancel, but also includes the cases were D2C was not set in the first place for the transaction coming from the ring.",
+        "UMask": "0x10",
         "Unit": "HA"
     },
     {
         "BriefDescription": "OSB Snoop Broadcast; Local InvItoE",
-        "Counter": "0,1,2,3",
         "EventCode": "0x53",
         "EventName": "UNC_H_OSB.INVITOE_LOCAL",
         "PerPkg": "1",
+        "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
         "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "OSB Snoop Broadcast; Remote",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "OSB Snoop Broadcast; Local Reads",
         "EventCode": "0x53",
-        "EventName": "UNC_H_OSB.REMOTE",
+        "EventName": "UNC_H_OSB.READS_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "OSB Snoop Broadcast; Cancelled",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "OSB Snoop Broadcast; Reads Local -  Useful",
         "EventCode": "0x53",
-        "EventName": "UNC_H_OSB.CANCELLED",
+        "EventName": "UNC_H_OSB.READS_LOCAL_USEFUL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+        "UMask": "0x20",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "OSB Snoop Broadcast; Reads Local -  Useful",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "OSB Snoop Broadcast; Remote",
         "EventCode": "0x53",
-        "EventName": "UNC_H_OSB.READS_LOCAL_USEFUL",
+        "EventName": "UNC_H_OSB.REMOTE",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
         "BriefDescription": "OSB Snoop Broadcast; Remote - Useful",
-        "Counter": "0,1,2,3",
         "EventCode": "0x53",
         "EventName": "UNC_H_OSB.REMOTE_USEFUL",
         "PerPkg": "1",
+        "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
         "UMask": "0x40",
         "Unit": "HA"
     },
     {
         "BriefDescription": "OSB Early Data Return; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "UNC_H_OSB_EDR.ALL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "OSB Early Data Return; Reads to Local  I",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "UNC_H_OSB_EDR.READS_LOCAL_I",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "OSB Early Data Return; Reads to Remote I",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "OSB Early Data Return; Reads to Local S",
         "EventCode": "0x54",
-        "EventName": "UNC_H_OSB_EDR.READS_REMOTE_I",
+        "EventName": "UNC_H_OSB_EDR.READS_LOCAL_S",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "OSB Early Data Return; Reads to Local S",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "OSB Early Data Return; Reads to Remote I",
         "EventCode": "0x54",
-        "EventName": "UNC_H_OSB_EDR.READS_LOCAL_S",
+        "EventName": "UNC_H_OSB_EDR.READS_REMOTE_I",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
         "BriefDescription": "OSB Early Data Return; Reads to Remote S",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "UNC_H_OSB_EDR.READS_REMOTE_S",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
         "UMask": "0x10",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Read and Write Requests; Reads",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Read and Write Requests; Local InvItoEs",
         "EventCode": "0x1",
-        "EventName": "UNC_H_REQUESTS.READS",
+        "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from the local socket.",
+        "UMask": "0x10",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Read and Write Requests; Writes",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Read and Write Requests; Remote InvItoEs",
         "EventCode": "0x1",
-        "EventName": "UNC_H_REQUESTS.WRITES",
+        "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from remote sockets.",
+        "UMask": "0x20",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "Read and Write Requests; Reads",
+        "EventCode": "0x1",
+        "EventName": "UNC_H_REQUESTS.READS",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; Incoming ead requests.  This is a good proxy for LLC Read Misses (including RFOs).",
+        "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Read and Write Requests; Local Reads",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_H_REQUESTS.READS_LOCAL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the local socket.  This is a good proxy for LLC Read Misses (including RFOs) from the local socket.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Read and Write Requests; Remote Reads",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_H_REQUESTS.READS_REMOTE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the remote socket.  This is a good proxy for LLC Read Misses (including RFOs) from the remote socket.",
         "UMask": "0x2",
         "Unit": "HA"
     },
+    {
+        "BriefDescription": "Read and Write Requests; Writes",
+        "EventCode": "0x1",
+        "EventName": "UNC_H_REQUESTS.WRITES",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; Incoming write requests.",
+        "UMask": "0xc",
+        "Unit": "HA"
+    },
     {
         "BriefDescription": "Read and Write Requests; Local Writes",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from the local socket.",
         "UMask": "0x4",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Read and Write Requests; Remote Writes",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_H_REQUESTS.WRITES_REMOTE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from remote sockets.",
         "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Read and Write Requests; Local InvItoEs",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "Read and Write Requests; Remote InvItoEs",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "HA AD Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3E",
-        "EventName": "UNC_H_RING_AD_USED.CW_EVEN",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "HA AD Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "HA AD Ring in Use; Counterclockwise",
         "EventCode": "0x3E",
-        "EventName": "UNC_H_RING_AD_USED.CW_ODD",
+        "EventName": "UNC_H_RING_AD_USED.CCW",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xc",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3E",
         "EventName": "UNC_H_RING_AD_USED.CCW_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
         "UMask": "0x4",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3E",
         "EventName": "UNC_H_RING_AD_USED.CCW_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA AD Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3E",
         "EventName": "UNC_H_RING_AD_USED.CW",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA AD Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "HA AD Ring in Use; Clockwise and Even",
         "EventCode": "0x3E",
-        "EventName": "UNC_H_RING_AD_USED.CCW",
+        "EventName": "UNC_H_RING_AD_USED.CW_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA AK Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3F",
-        "EventName": "UNC_H_RING_AK_USED.CW_EVEN",
+        "BriefDescription": "HA AD Ring in Use; Clockwise and Odd",
+        "EventCode": "0x3E",
+        "EventName": "UNC_H_RING_AD_USED.CW_ODD",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA AK Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "HA AK Ring in Use; Counterclockwise",
         "EventCode": "0x3F",
-        "EventName": "UNC_H_RING_AK_USED.CW_ODD",
+        "EventName": "UNC_H_RING_AK_USED.CCW",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xc",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3F",
         "EventName": "UNC_H_RING_AK_USED.CCW_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
         "UMask": "0x4",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3F",
         "EventName": "UNC_H_RING_AK_USED.CCW_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA AK Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3F",
         "EventName": "UNC_H_RING_AK_USED.CW",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA AK Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "HA AK Ring in Use; Clockwise and Even",
         "EventCode": "0x3F",
-        "EventName": "UNC_H_RING_AK_USED.CCW",
+        "EventName": "UNC_H_RING_AK_USED.CW_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA BL Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x40",
-        "EventName": "UNC_H_RING_BL_USED.CW_EVEN",
+        "BriefDescription": "HA AK Ring in Use; Clockwise and Odd",
+        "EventCode": "0x3F",
+        "EventName": "UNC_H_RING_AK_USED.CW_ODD",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA BL Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "HA BL Ring in Use; Counterclockwise",
         "EventCode": "0x40",
-        "EventName": "UNC_H_RING_BL_USED.CW_ODD",
+        "EventName": "UNC_H_RING_BL_USED.CCW",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xc",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.CCW_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
         "UMask": "0x4",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.CCW_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA BL Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.CW",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA BL Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "HA BL Ring in Use; Clockwise and Even",
         "EventCode": "0x40",
-        "EventName": "UNC_H_RING_BL_USED.CCW",
+        "EventName": "UNC_H_RING_BL_USED.CW_EVEN",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+        "UMask": "0x1",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "HA BL Ring in Use; Clockwise and Odd",
+        "EventCode": "0x40",
+        "EventName": "UNC_H_RING_BL_USED.CW_ODD",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
         "UMask": "0x4",
         "Unit": "HA"
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
         "UMask": "0x8",
         "Unit": "HA"
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
         "UMask": "0x4",
         "Unit": "HA"
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue).  This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
         "UMask": "0x8",
         "Unit": "HA"
     },
     {
         "BriefDescription": "SBo0 Credits Acquired; For AD Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x68",
         "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "SBo0 Credits Acquired; For BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x68",
         "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6A",
         "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6A",
         "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "SBo1 Credits Acquired; For AD Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x69",
         "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "SBo1 Credits Acquired; For BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x69",
         "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "SBo1 Credits Occupancy; For AD Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6B",
         "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "SBo1 Credits Occupancy; For BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6B",
         "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Data beat the Snoop Responses; Local Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from the local socket.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Data beat the Snoop Responses; Remote Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from remote sockets.",
         "UMask": "0x2",
         "Unit": "HA"
     },
+    {
+        "BriefDescription": "Cycles with Snoops Outstanding; All Requests",
+        "EventCode": "0x8",
+        "EventName": "UNC_H_SNOOP_CYCLES_NE.ALL",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles when one or more snoops are outstanding.; Tracked for snoops from both local and remote sockets.",
+        "UMask": "0x3",
+        "Unit": "HA"
+    },
     {
         "BriefDescription": "Cycles with Snoops Outstanding; Local Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_H_SNOOP_CYCLES_NE.LOCAL",
         "PerPkg": "1",
+        "PublicDescription": "Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from the local socket.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Cycles with Snoops Outstanding; Remote Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_H_SNOOP_CYCLES_NE.REMOTE",
         "PerPkg": "1",
+        "PublicDescription": "Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from remote sockets.",
         "UMask": "0x2",
         "Unit": "HA"
     },
-    {
-        "BriefDescription": "Cycles with Snoops Outstanding; All Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8",
-        "EventName": "UNC_H_SNOOP_CYCLES_NE.ALL",
-        "PerPkg": "1",
-        "UMask": "0x3",
-        "Unit": "HA"
-    },
     {
         "BriefDescription": "Tracker Snoops Outstanding Accumulator; Local Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_H_SNOOP_OCCUPANCY.LOCAL",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle.    This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from the local socket.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Tracker Snoops Outstanding Accumulator; Remote Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_H_SNOOP_OCCUPANCY.REMOTE",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle.    This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from remote sockets.",
         "UMask": "0x2",
         "Unit": "HA"
     },
+    {
+        "BriefDescription": "Snoop Responses Received; RSPCNFLCT*",
+        "EventCode": "0x21",
+        "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspConflict.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI.",
+        "UMask": "0x40",
+        "Unit": "HA"
+    },
     {
         "BriefDescription": "Snoop Responses Received; RspI",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_H_SNOOP_RESP.RSPI",
         "PerPkg": "1",
+        "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspI.  RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
         "UMask": "0x1",
         "Unit": "HA"
     },
+    {
+        "BriefDescription": "M line forwarded from remote cache with no writeback to memory",
+        "EventCode": "0x21",
+        "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspIFwd.  This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states.  This is commonly returned with RFO transactions.  It can be either a HitM or a HitFE.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x4",
+        "Unit": "HA"
+    },
     {
         "BriefDescription": "Shared line response from remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_H_SNOOP_RESP.RSPS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspS.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS.",
         "ScaleUnit": "64Bytes",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "M line forwarded from remote cache with no writeback to memory",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Shared line forwarded from remote cache",
         "EventCode": "0x21",
-        "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
+        "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd.  This is returned when a remote caching agent forwards data but holds on to its currently copy.  This is common for data and code reads that hit in a remote socket in E or F state.",
         "ScaleUnit": "64Bytes",
-        "UMask": "0x4",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Shared line forwarded from remote cache",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "M line forwarded from remote cache along with writeback to memory",
         "EventCode": "0x21",
-        "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
+        "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of Rsp*Fwd*WB.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
         "ScaleUnit": "64Bytes",
-        "UMask": "0x8",
+        "UMask": "0x20",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Snoop Responses Received; Rsp*WB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_H_SNOOP_RESP.RSP_WB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspIWB or RspSWB.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership.",
         "UMask": "0x10",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "M line forwarded from remote cache along with writeback to memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
+        "BriefDescription": "Snoop Responses Received Local; Other",
+        "EventCode": "0x60",
+        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x20",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for all other snoop responses.",
+        "UMask": "0x80",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Snoop Responses Received; RSPCNFLCT*",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
+        "BriefDescription": "Snoop Responses Received Local; RspCnflct",
+        "EventCode": "0x60",
+        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT",
         "PerPkg": "1",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoops responses of RspConflict.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI.",
         "UMask": "0x40",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Snoop Responses Received Local; RspI",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPI",
         "PerPkg": "1",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoops responses of RspI.  RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
         "UMask": "0x1",
         "Unit": "HA"
     },
-    {
-        "BriefDescription": "Snoop Responses Received Local; RspS",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x60",
-        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "HA"
-    },
     {
         "BriefDescription": "Snoop Responses Received Local; RspIFwd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD",
         "PerPkg": "1",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoop responses of RspIFwd.  This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states.  This is commonly returned with RFO transactions.  It can be either a HitM or a HitFE.",
         "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; RspSFwd",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Snoop Responses Received Local; RspS",
         "EventCode": "0x60",
-        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD",
+        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoop responses of RspS.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS.",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Snoop Responses Received Local; RspSFwd",
         "EventCode": "0x60",
-        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB",
+        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of RspSFwd.  This is returned when a remote caching agent forwards data but holds on to its currently copy.  This is common for data and code reads that hit in a remote socket in E or F state.",
+        "UMask": "0x8",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB",
         "PerPkg": "1",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of Rsp*Fwd*WB.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
         "UMask": "0x20",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; RspCnflct",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x60",
-        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT",
-        "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "Snoop Responses Received Local; Other",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
         "EventCode": "0x60",
-        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER",
+        "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of RspIWB or RspSWB.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership.",
+        "UMask": "0x10",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6C",
         "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
         "EventCode": "0x6C",
-        "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD",
+        "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+        "UMask": "0x4",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
         "EventCode": "0x6C",
-        "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL",
+        "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6C",
         "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
         "UMask": "0x8",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION0",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 0",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 1",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION2",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 2",
         "UMask": "0x4",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION3",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 3",
         "UMask": "0x8",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION4",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 4",
         "UMask": "0x10",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION5",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 5",
         "UMask": "0x20",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION6",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 6",
         "UMask": "0x40",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION7",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 0 to 7.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 7",
         "UMask": "0x80",
         "Unit": "HA"
     },
+    {
+        "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10",
+        "EventCode": "0x1C",
+        "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 10",
+        "UMask": "0x4",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11",
+        "EventCode": "0x1C",
+        "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 11",
+        "UMask": "0x8",
+        "Unit": "HA"
+    },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_H_TAD_REQUESTS_G1.REGION8",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 8",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_H_TAD_REQUESTS_G1.REGION9",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of HA requests to a given TAD region.  There are up to 11 TAD (target address decode) regions in each home agent.  All requests destined for the memory controller must first be decoded to determine which TAD region they are in.  This event is filtered based on the TAD region ID, and covers regions 8 to 10.  This event is useful for understanding how applications are using the memory that is spread across the different memory regions.  It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 9",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1C",
-        "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10",
+        "BriefDescription": "Tracker Cycles Full; Cycles Completely Used",
+        "EventCode": "0x2",
+        "EventName": "UNC_H_TRACKER_CYCLES_FULL.ALL",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of cycles when the local HA tracker pool is completely used.  This can be used with edge detect to identify the number of situations when the pool became fully utilized.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, the system could be starved for RTIDs but not fill up the HA trackers.  HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the HA tracker pool (HT) is completely used including reserved HT entries.  It will not return valid count when BT is disabled.",
+        "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1C",
-        "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11",
+        "BriefDescription": "Tracker Cycles Full; Cycles GP Completely Used",
+        "EventCode": "0x2",
+        "EventName": "UNC_H_TRACKER_CYCLES_FULL.GP",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of cycles when the local HA tracker pool is completely used.  This can be used with edge detect to identify the number of situations when the pool became fully utilized.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, the system could be starved for RTIDs but not fill up the HA trackers.  HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the general purpose (GP) HA tracker pool (HT) is completely used.  It will not return valid count when BT is disabled.",
+        "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Tracker Cycles Full; Cycles GP Completely Used",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_H_TRACKER_CYCLES_FULL.GP",
+        "BriefDescription": "Tracker Cycles Not Empty; All Requests",
+        "EventCode": "0x3",
+        "EventName": "UNC_H_TRACKER_CYCLES_NE.ALL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Requests coming from both local and remote sockets.",
+        "UMask": "0x3",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "Tracker Cycles Not Empty; Local Requests",
+        "EventCode": "0x3",
+        "EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from the local socket.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "Tracker Cycles Full; Cycles Completely Used",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_H_TRACKER_CYCLES_FULL.ALL",
+        "BriefDescription": "Tracker Cycles Not Empty; Remote Requests",
+        "EventCode": "0x3",
+        "EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty.  This can be used with edge detect to identify the number of situations when the pool became empty.  This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure.  In other words, this buffer could be completely empty, but there may still be credits in use by the CBos.  This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy.  HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from remote sockets.",
         "UMask": "0x2",
         "Unit": "HA"
     },
+    {
+        "BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE Requests",
+        "EventCode": "0x4",
+        "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL",
+        "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+        "UMask": "0x40",
+        "Unit": "HA"
+    },
+    {
+        "BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE Requests",
+        "EventCode": "0x4",
+        "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE",
+        "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+        "UMask": "0x80",
+        "Unit": "HA"
+    },
     {
         "BriefDescription": "Tracker Occupancy Accumultor; Local Read Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
         "UMask": "0x4",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Tracker Occupancy Accumultor; Remote Read Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
         "UMask": "0x8",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Tracker Occupancy Accumultor; Local Write Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
         "UMask": "0x10",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Tracker Occupancy Accumultor; Remote Write Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle.  This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency.  HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
         "UMask": "0x20",
         "Unit": "HA"
     },
-    {
-        "BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL",
-        "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE",
-        "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "HA"
-    },
     {
         "BriefDescription": "Data Pending Occupancy Accumultor; Local Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress.  This can be used to calculate the queuing latency for two things.  (1) If the system is waiting for snoops, this will increase.  (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from the local socket.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Data Pending Occupancy Accumultor; Remote Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress.  This can be used to calculate the queuing latency for two things.  (1) If the system is waiting for snoops, this will increase.  (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from remote sockets.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Outbound NDR Ring Transactions; Non-data Responses",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "UNC_H_TxR_AD.HOM",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of outbound transactions on the AD ring.  This can be filtered by the NDR and SNP message classes.  See the filter descriptions for more details.; Filter for outbound NDR transactions sent on the AD ring.  NDR stands for non-data response and is generally used for completions that do not include data.  AD NDR is used for transactions to remote sockets.",
         "UMask": "0x4",
         "Unit": "HA"
     },
+    {
+        "BriefDescription": "AD Egress Full; All",
+        "EventCode": "0x2A",
+        "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL",
+        "PerPkg": "1",
+        "PublicDescription": "AD Egress Full; Cycles full from both schedulers",
+        "UMask": "0x3",
+        "Unit": "HA"
+    },
     {
         "BriefDescription": "AD Egress Full; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
         "PerPkg": "1",
+        "PublicDescription": "AD Egress Full; Filter for cycles full  from scheduler bank 0",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AD Egress Full; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
         "PerPkg": "1",
+        "PublicDescription": "AD Egress Full; Filter for cycles full  from scheduler bank 1",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "AD Egress Full; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL",
+        "BriefDescription": "AD Egress Not Empty; All",
+        "EventCode": "0x29",
+        "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL",
         "PerPkg": "1",
+        "PublicDescription": "AD Egress Not Empty; Cycles full from both schedulers",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AD Egress Not Empty; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0",
         "PerPkg": "1",
+        "PublicDescription": "AD Egress Not Empty; Filter for cycles not empty  from scheduler bank 0",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AD Egress Not Empty; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1",
         "PerPkg": "1",
+        "PublicDescription": "AD Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "AD Egress Not Empty; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x29",
-        "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL",
+        "BriefDescription": "AD Egress Allocations; All",
+        "EventCode": "0x27",
+        "EventName": "UNC_H_TxR_AD_INSERTS.ALL",
         "PerPkg": "1",
+        "PublicDescription": "AD Egress Allocations; Allocations from both schedulers",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AD Egress Allocations; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "UNC_H_TxR_AD_INSERTS.SCHED0",
         "PerPkg": "1",
+        "PublicDescription": "AD Egress Allocations; Filter for allocations from scheduler bank 0",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AD Egress Allocations; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "UNC_H_TxR_AD_INSERTS.SCHED1",
         "PerPkg": "1",
+        "PublicDescription": "AD Egress Allocations; Filter for allocations from scheduler bank 1",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "AD Egress Allocations; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x27",
-        "EventName": "UNC_H_TxR_AD_INSERTS.ALL",
+        "BriefDescription": "AK Egress Full; All",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL",
         "PerPkg": "1",
+        "PublicDescription": "AK Egress Full; Cycles full from both schedulers",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AK Egress Full; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
         "PerPkg": "1",
+        "PublicDescription": "AK Egress Full; Filter for cycles full  from scheduler bank 0",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AK Egress Full; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
         "PerPkg": "1",
+        "PublicDescription": "AK Egress Full; Filter for cycles full  from scheduler bank 1",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "AK Egress Full; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL",
+        "BriefDescription": "AK Egress Not Empty; All",
+        "EventCode": "0x31",
+        "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL",
         "PerPkg": "1",
+        "PublicDescription": "AK Egress Not Empty; Cycles full from both schedulers",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AK Egress Not Empty; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0",
         "PerPkg": "1",
+        "PublicDescription": "AK Egress Not Empty; Filter for cycles not empty  from scheduler bank 0",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AK Egress Not Empty; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1",
         "PerPkg": "1",
+        "PublicDescription": "AK Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "AK Egress Not Empty; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x31",
-        "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL",
+        "BriefDescription": "AK Egress Allocations; All",
+        "EventCode": "0x2F",
+        "EventName": "UNC_H_TxR_AK_INSERTS.ALL",
         "PerPkg": "1",
+        "PublicDescription": "AK Egress Allocations; Allocations from both schedulers",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AK Egress Allocations; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2F",
         "EventName": "UNC_H_TxR_AK_INSERTS.SCHED0",
         "PerPkg": "1",
+        "PublicDescription": "AK Egress Allocations; Filter for allocations from scheduler bank 0",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AK Egress Allocations; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2F",
         "EventName": "UNC_H_TxR_AK_INSERTS.SCHED1",
         "PerPkg": "1",
+        "PublicDescription": "AK Egress Allocations; Filter for allocations from scheduler bank 1",
         "UMask": "0x2",
         "Unit": "HA"
     },
-    {
-        "BriefDescription": "AK Egress Allocations; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2F",
-        "EventName": "UNC_H_TxR_AK_INSERTS.ALL",
-        "PerPkg": "1",
-        "UMask": "0x3",
-        "Unit": "HA"
-    },
     {
         "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_H_TxR_BL.DRS_CACHE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent to the cache.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_H_TxR_BL.DRS_CORE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent directly to the requesting core.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_H_TxR_BL.DRS_QPI",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRS messages sent out on the BL ring.   This can be filtered by the destination.; Filter for data being sent to a remote socket over QPI.",
         "UMask": "0x4",
         "Unit": "HA"
     },
+    {
+        "BriefDescription": "BL Egress Full; All",
+        "EventCode": "0x36",
+        "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL",
+        "PerPkg": "1",
+        "PublicDescription": "BL Egress Full; Cycles full from both schedulers",
+        "UMask": "0x3",
+        "Unit": "HA"
+    },
     {
         "BriefDescription": "BL Egress Full; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x36",
         "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
         "PerPkg": "1",
+        "PublicDescription": "BL Egress Full; Filter for cycles full  from scheduler bank 0",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "BL Egress Full; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x36",
         "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
         "PerPkg": "1",
+        "PublicDescription": "BL Egress Full; Filter for cycles full  from scheduler bank 1",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "BL Egress Full; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x36",
-        "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL",
+        "BriefDescription": "BL Egress Not Empty; All",
+        "EventCode": "0x35",
+        "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL",
         "PerPkg": "1",
+        "PublicDescription": "BL Egress Not Empty; Cycles full from both schedulers",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "BL Egress Not Empty; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0",
         "PerPkg": "1",
+        "PublicDescription": "BL Egress Not Empty; Filter for cycles not empty  from scheduler bank 0",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "BL Egress Not Empty; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1",
         "PerPkg": "1",
+        "PublicDescription": "BL Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
-        "BriefDescription": "BL Egress Not Empty; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL",
+        "BriefDescription": "BL Egress Allocations; All",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_TxR_BL_INSERTS.ALL",
         "PerPkg": "1",
+        "PublicDescription": "BL Egress Allocations; Allocations from both schedulers",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "BL Egress Allocations; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_H_TxR_BL_INSERTS.SCHED0",
         "PerPkg": "1",
+        "PublicDescription": "BL Egress Allocations; Filter for allocations from scheduler bank 0",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "BL Egress Allocations; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_H_TxR_BL_INSERTS.SCHED1",
         "PerPkg": "1",
+        "PublicDescription": "BL Egress Allocations; Filter for allocations from scheduler bank 1",
         "UMask": "0x2",
         "Unit": "HA"
     },
-    {
-        "BriefDescription": "BL Egress Allocations; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_H_TxR_BL_INSERTS.ALL",
-        "PerPkg": "1",
-        "UMask": "0x3",
-        "Unit": "HA"
-    },
     {
         "BriefDescription": "Injection Starvation; For AK Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6D",
         "EventName": "UNC_H_TxR_STARVED.AK",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Injection Starvation; For BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6D",
         "EventName": "UNC_H_TxR_STARVED.BL",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
         "UMask": "0x4",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the regular credits  Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
         "UMask": "0x8",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
         "UMask": "0x4",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC.  In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue).  This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes.  This count only tracks the special credits.  This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH.  One can filter based on the memory controller channel.  One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
         "UMask": "0x8",
         "Unit": "HA"
-    },
-    {
-        "BriefDescription": "Tracker Cycles Not Empty; Local Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "Tracker Cycles Not Empty; Remote Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "HA"
-    },
-    {
-        "BriefDescription": "Tracker Cycles Not Empty; All Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_H_TRACKER_CYCLES_NE.ALL",
-        "PerPkg": "1",
-        "UMask": "0x3",
-        "Unit": "HA"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/haswellx/uncore-interconnect.json
index eb0a05fbb7048..15059b17cd199 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-interconnect.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-interconnect.json
@@ -1,1452 +1,1332 @@
 [
+    {
+        "BriefDescription": "Number of non data (control) flits transmitted . Derived from unc_q_txl_flits_g0.non_data",
+        "EventName": "QPI_CTL_BANDWIDTH_TX",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI.  This basically tracks the protocol overhead on the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This includes the header flits for data packets.",
+        "ScaleUnit": "8Bytes",
+        "UMask": "0x4",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data",
+        "EventName": "QPI_DATA_BANDWIDTH_TX",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI.  Each flit contains 64b of data.  This includes both DRS and NCB data flits (coherent and non-coherent).  This can be used to calculate the data bandwidth of the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This does not include the header flits that go in data packets.",
+        "ScaleUnit": "8Bytes",
+        "UMask": "0x2",
+        "Unit": "QPI LL"
+    },
     {
         "BriefDescription": "Number of qfclks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_Q_CLOCKTICKS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of clocks in the QPI LL.  This clock runs at 1/4th the GT/s speed of the QPI link.  For example, a 4GT/s link will have qfclk or 1GHz.  HSX does not support dynamic link speeds, so this frequency is fixed.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Count of CTO Events",
-        "Counter": "0,1,2,3",
         "EventCode": "0x38",
         "EventName": "UNC_Q_CTO_COUNT",
-        "ExtSel": "1",
         "PerPkg": "1",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "Direct 2 Core Spawning; Spawn Success",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT",
-        "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots.  If both slots trigger in a given cycle, the event will increment by 2.  You can use edge detect to count the number of cases when both events triggered.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits.  Had there been enough credits, the spawn would have worked as the RBT bit was set and the RBT tag matched.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Invalid",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss",
         "EventCode": "0x13",
-        "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT",
+        "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and there weren't enough Egress credits.   The valid bit was set.",
+        "UMask": "0x20",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Invalid",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits AND the RBT bit was not set, but the RBT tag matched.",
         "UMask": "0x8",
         "Unit": "QPI LL"
     },
+    {
+        "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid",
+        "EventCode": "0x13",
+        "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match, the valid bit was not set and there weren't enough Egress credits.",
+        "UMask": "0x80",
+        "Unit": "QPI LL"
+    },
     {
         "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_DIRECT2CORE.FAILURE_MISS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match although the valid bit was set and there were enough Egress credits.",
         "UMask": "0x10",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Invalid",
         "EventCode": "0x13",
-        "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS",
+        "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the route-back table (RBT) specified that the transaction should not trigger a direct2core transaction.  This is common for IO transactions.  There were enough Egress credits and the RBT tag matched but the valid bit was not set.",
+        "UMask": "0x4",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss and Invalid",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and the valid bit was not set although there were enough Egress credits.",
         "UMask": "0x40",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Direct 2 Core Spawning; Spawn Success",
         "EventCode": "0x13",
-        "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS",
+        "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn was successful.  There were sufficient credits, the RBT valid bit was set and there was an RBT tag match.  The message was marked to spawn direct2core.",
+        "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Cycles in L1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_Q_L1_POWER_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of QPI qfclk cycles spent in L1 power mode.  L1 is a mode that totally shuts down a QPI link.  Use edge detect to count the number of instances when the QPI link entered L1.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Cycles in L0p",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_Q_RxL0P_POWER_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses.  Use edge detect to count the number of instances when the QPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Cycles in L0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "UNC_Q_RxL0_POWER_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Bypassed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_Q_RxL_BYPASSED",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "CRC Errors Detected; LinkInit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT",
         "PerPkg": "1",
+        "PublicDescription": "Number of CRC errors detected in the QPI Agent.  Each QPI flit incorporates 8 bits of CRC for error detection.  This counts the number of flits where the CRC was able to detect an error.  After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during link initialization.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "CRC Errors Detected; Normal Operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
         "PerPkg": "1",
+        "PublicDescription": "Number of CRC errors detected in the QPI Agent.  Each QPI flit incorporates 8 bits of CRC for error detection.  This counts the number of flits where the CRC was able to detect an error.  After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during normal operation.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "VN0 Credit Consumed; DRS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the DRS message class.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
+    {
+        "BriefDescription": "VN0 Credit Consumed; HOM",
+        "EventCode": "0x1E",
+        "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the HOM message class.",
+        "UMask": "0x8",
+        "Unit": "QPI LL"
+    },
     {
         "BriefDescription": "VN0 Credit Consumed; NCB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCB message class.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "VN0 Credit Consumed; NCS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCS message class.",
         "UMask": "0x4",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "VN0 Credit Consumed; HOM",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "VN0 Credit Consumed; NDR",
         "EventCode": "0x1E",
-        "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NDR message class.",
+        "UMask": "0x20",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "VN0 Credit Consumed; SNP",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the SNP message class.",
         "UMask": "0x10",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "VN0 Credit Consumed; NDR",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1E",
-        "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR",
-        "ExtSel": "1",
+        "BriefDescription": "VN1 Credit Consumed; DRS",
+        "EventCode": "0x39",
+        "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the DRS message class.",
+        "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "VN1 Credit Consumed; DRS",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "VN1 Credit Consumed; HOM",
         "EventCode": "0x39",
-        "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the HOM message class.",
+        "UMask": "0x8",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "VN1 Credit Consumed; NCB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCB message class.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "VN1 Credit Consumed; NCS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCS message class.",
         "UMask": "0x4",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "VN1 Credit Consumed; HOM",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "VN1 Credit Consumed; NDR",
         "EventCode": "0x39",
-        "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NDR message class.",
+        "UMask": "0x20",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "VN1 Credit Consumed; SNP",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the SNP message class.",
         "UMask": "0x10",
         "Unit": "QPI LL"
     },
-    {
-        "BriefDescription": "VN1 Credit Consumed; NDR",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "QPI LL"
-    },
     {
         "BriefDescription": "VNA Credit Consumed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_Q_RxL_CYCLES_NE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors DRS flits only.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors DRS flits only.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors HOM flits only.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors HOM flits only.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCB flits only.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCB flits only.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x11",
         "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCS flits only.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x11",
         "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCS flits only.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NDR flits only.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NDR flits only.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors SNP flits only.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors SNP flits only.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Flits Received - Group 0; Idle and Null Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_Q_RxL_FLITS_G0.IDLE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received over QPI that do not hold protocol payload.  When QPI is not in a power saving state, it continuously transmits flits across the link.  When there are no protocol flits to send, it will send IDLE and NULL flits  across.  These flits sometimes do carry a payload, such as credit returns, but are generally not considered part of the QPI bandwidth.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Received - Group 1; SNP Flits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)",
         "EventCode": "0x2",
-        "EventName": "UNC_Q_RxL_FLITS_G1.SNP",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_RxL_FLITS_G1.DRS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits received over the NCB channel which transmits non-coherent data.",
+        "UMask": "0x18",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Received - Group 1; HOM Request Flits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Flits Received - Group 1; DRS Data Flits",
         "EventCode": "0x2",
-        "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits received over the NCB channel which transmits non-coherent data.  This includes only the data flits (not the header).",
+        "UMask": "0x8",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Flits Received - Group 1; DRS Header Flits",
         "EventCode": "0x2",
-        "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits received over the NCB channel which transmits non-coherent data.  This includes only the header flits (not the data).  This includes extended headers.",
+        "UMask": "0x10",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Flits Received - Group 1; HOM Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_Q_RxL_FLITS_G1.HOM",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel.",
         "UMask": "0x6",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Received - Group 1; DRS Data Flits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits",
         "EventCode": "0x2",
-        "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel.  These are most commonly snoop responses, and this event can be used as a proxy for that.",
+        "UMask": "0x4",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Received - Group 1; DRS Header Flits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Flits Received - Group 1; HOM Request Flits",
         "EventCode": "0x2",
-        "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel.  This basically counts the number of remote memory requests received over QPI.  In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.",
+        "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Flits Received - Group 1; SNP Flits",
         "EventCode": "0x2",
-        "EventName": "UNC_Q_RxL_FLITS_G1.DRS",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x18",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_RxL_FLITS_G1.SNP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI.  These requests are contained in the snoop channel.  This does not include snoop responses, which are received on the home channel.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits",
         "EventCode": "0x3",
-        "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_RxL_FLITS_G2.NCB",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits.  These packets are generally used to transmit non-coherent data across QPI.",
+        "UMask": "0xc",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Flits Received - Group 2; Non-Coherent data Rx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits.  These flits are generally used to transmit non-coherent data across QPI.  This does not include a count of the DRS (coherent) data flits.  This only counts the data flits, not the NCB headers.",
         "UMask": "0x4",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Flits Received - Group 2; Non-Coherent non-data Rx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits.  These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits.  This includes extended headers.",
         "UMask": "0x8",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits",
         "EventCode": "0x3",
-        "EventName": "UNC_Q_RxL_FLITS_G2.NCB",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_RxL_FLITS_G2.NCS",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI.    This includes extended headers.",
+        "UMask": "0x10",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD",
         "EventCode": "0x3",
-        "EventName": "UNC_Q_RxL_FLITS_G2.NCS",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets to the local socket which use the AK ring.",
+        "UMask": "0x1",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK",
+        "EventCode": "0x3",
+        "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets destined for Route-thru to a remote socket.",
+        "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_Q_RxL_INSERTS",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_Q_RxL_INSERTS_DRS.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only DRS flits.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_Q_RxL_INSERTS_DRS.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only DRS flits.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC",
         "EventName": "UNC_Q_RxL_INSERTS_HOM.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only HOM flits.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC",
         "EventName": "UNC_Q_RxL_INSERTS_HOM.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only HOM flits.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_Q_RxL_INSERTS_NCB.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCB flits.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_Q_RxL_INSERTS_NCB.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCB flits.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB",
         "EventName": "UNC_Q_RxL_INSERTS_NCS.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCS flits.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB",
         "EventName": "UNC_Q_RxL_INSERTS_NCS.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCS flits.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE",
         "EventName": "UNC_Q_RxL_INSERTS_NDR.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NDR flits.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE",
         "EventName": "UNC_Q_RxL_INSERTS_NDR.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NDR flits.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD",
         "EventName": "UNC_Q_RxL_INSERTS_SNP.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only SNP flits.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD",
         "EventName": "UNC_Q_RxL_INSERTS_SNP.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only SNP flits.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - All Packets",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB",
         "EventName": "UNC_Q_RxL_OCCUPANCY",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - DRS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors DRS flits only.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - DRS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors DRS flits only.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - HOM; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors HOM flits only.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - HOM; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors HOM flits only.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - NCB; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCB flits only.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - NCB; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCB flits only.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - NCS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x17",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCS flits only.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - NCS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x17",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCS flits only.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - NDR; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1A",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NDR flits only.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - NDR; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1A",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NDR flits only.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - SNP; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors SNP flits only.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - SNP; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors SNP flits only.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - HOM",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_DRS",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the HOM message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
+    {
+        "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - DRS",
+        "EventCode": "0x35",
+        "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM",
+        "PerPkg": "1",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the DRS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+        "UMask": "0x8",
+        "Unit": "QPI LL"
+    },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - SNP",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCB",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the SNP message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NDR",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCS",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NDR message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
         "UMask": "0x4",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - DRS",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCS",
         "EventCode": "0x35",
-        "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+        "UMask": "0x20",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_SNP",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCB message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
         "UMask": "0x10",
         "Unit": "QPI LL"
     },
-    {
-        "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCS",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "QPI LL"
-    },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN0; Egress Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet because there were insufficient BGF credits.  For details on a message class granularity, use the Egress Credit Occupancy events.",
         "UMask": "0x40",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN0; GV",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_Q_RxL_STALLS_VN0.GV",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled because a GV transition (frequency transition) was taking place.",
         "UMask": "0x80",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - HOM",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3A",
         "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_DRS",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the HOM message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
+    {
+        "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - DRS",
+        "EventCode": "0x3A",
+        "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM",
+        "PerPkg": "1",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the DRS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+        "UMask": "0x8",
+        "Unit": "QPI LL"
+    },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - SNP",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3A",
         "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCB",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the SNP message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NDR",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3A",
         "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCS",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NDR message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
         "UMask": "0x4",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - DRS",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCS",
         "EventCode": "0x3A",
-        "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+        "UMask": "0x20",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3A",
         "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_SNP",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCB message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
         "UMask": "0x10",
         "Unit": "QPI LL"
     },
-    {
-        "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCS",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3A",
-        "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "QPI LL"
-    },
     {
         "BriefDescription": "Cycles in L0p",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD",
         "EventName": "UNC_Q_TxL0P_POWER_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses.  Use edge detect to count the number of instances when the QPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Cycles in L0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC",
         "EventName": "UNC_Q_TxL0_POWER_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Tx Flit Buffer Bypassed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_Q_TxL_BYPASSED",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full",
         "EventCode": "0x2",
-        "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL",
+        "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is almost full, we block some but not all packets.",
+        "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full",
         "EventCode": "0x2",
-        "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL",
+        "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is totally full, we are not allowed to send any packets.",
+        "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Tx Flit Buffer Cycles not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_Q_TxL_CYCLES_NE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G0.DATA",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data",
-        "Counter": "0,1,2,3",
-        "EventName": "QPI_DATA_BANDWIDTH_TX",
-        "PerPkg": "1",
-        "ScaleUnit": "8Bytes",
+        "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI.  Each flit contains 64b of data.  This includes both DRS and NCB data flits (coherent and non-coherent).  This can be used to calculate the data bandwidth of the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This does not include the header flits that go in data packets.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI.  This basically tracks the protocol overhead on the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This includes the header flits for data packets.",
         "UMask": "0x4",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Number of non data (control) flits transmitted . Derived from unc_q_txl_flits_g0.non_data",
-        "Counter": "0,1,2,3",
-        "EventName": "QPI_CTL_BANDWIDTH_TX",
-        "PerPkg": "1",
-        "ScaleUnit": "8Bytes",
-        "UMask": "0x4",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "Flits Transferred - Group 1; SNP Flits",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_Q_TxL_FLITS_G1.SNP",
-        "ExtSel": "1",
+        "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)",
+        "EventName": "UNC_Q_TxL_FLITS_G1.DRS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.",
+        "UMask": "0x18",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ",
-        "ExtSel": "1",
+        "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits",
+        "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits transmitted over the NCB channel which transmits non-coherent data.  This includes only the data flits (not the header).",
+        "UMask": "0x8",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ",
-        "ExtSel": "1",
+        "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits",
+        "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits transmitted over the NCB channel which transmits non-coherent data.  This includes only the header flits (not the data).  This includes extended headers.",
+        "UMask": "0x10",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Flits Transferred - Group 1; HOM Flits",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G1.HOM",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel.",
         "UMask": "0x6",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA",
-        "ExtSel": "1",
-        "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "QPI LL"
-    },
-    {
-        "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA",
-        "ExtSel": "1",
+        "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits",
+        "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel.  These are most commonly snoop responses, and this event can be used as a proxy for that.",
+        "UMask": "0x4",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_Q_TxL_FLITS_G1.DRS",
-        "ExtSel": "1",
+        "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits",
+        "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ",
         "PerPkg": "1",
-        "UMask": "0x18",
+        "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel.  This basically counts the number of remote memory requests transmitted over QPI.  In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.",
+        "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD",
-        "ExtSel": "1",
+        "BriefDescription": "Flits Transferred - Group 1; SNP Flits",
+        "EventName": "UNC_Q_TxL_FLITS_G1.SNP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI.  These requests are contained in the snoop channel.  This does not include snoop responses, which are transmitted on the home channel.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits",
         "EventCode": "0x1",
-        "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_TxL_FLITS_G2.NCB",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits.  These packets are generally used to transmit non-coherent data across QPI.",
+        "UMask": "0xc",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Flits Transferred - Group 2; Non-Coherent data Tx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits.  These flits are generally used to transmit non-coherent data across QPI.  This does not include a count of the DRS (coherent) data flits.  This only counts the data flits, not the NCB headers.",
         "UMask": "0x4",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Flits Transferred - Group 2; Non-Coherent non-data Tx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits.  These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits.  This includes extended headers.",
         "UMask": "0x8",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits",
         "EventCode": "0x1",
-        "EventName": "UNC_Q_TxL_FLITS_G2.NCB",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_TxL_FLITS_G2.NCS",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI.    This includes extended headers.",
+        "UMask": "0x10",
         "Unit": "QPI LL"
     },
     {
-        "BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD",
         "EventCode": "0x1",
-        "EventName": "UNC_Q_TxL_FLITS_G2.NCS",
-        "ExtSel": "1",
+        "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets to the local socket which use the AK ring.",
+        "UMask": "0x1",
+        "Unit": "QPI LL"
+    },
+    {
+        "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK",
+        "EventCode": "0x1",
+        "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets destined for Route-thru to a remote socket.",
+        "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Tx Flit Buffer Allocations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_Q_TxL_INSERTS",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the QPI Tx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Tx Flit Buffer Occupancy",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_Q_TxL_OCCUPANCY",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of flits in the TxQ.  Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO for HOM messages on AD.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO for HOM messages on AD.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for NDR messages on AD.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for NDR messages on AD.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO  for NDR messages on AD.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO  for NDR messages on AD.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for Snoop messages on AD.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for Snoop messages on AD.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x23",
         "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO for Snoop messages on AD.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x23",
         "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO for Snoop messages on AD.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR",
-        "Counter": "0,1,2,3",
         "EventCode": "0x25",
         "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  Local NDR message class to AK Egress.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for Shared VN",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
         "UMask": "0x4",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1F",
         "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  DRS message class to BL Egress.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1F",
         "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  DRS message class to BL Egress.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for Shared VN",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1F",
         "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  DRS message class to BL Egress.",
         "UMask": "0x4",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2B",
         "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2B",
         "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCB message class to BL Egress.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCB message class to BL Egress.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2C",
         "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2C",
         "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCS message class to BL Egress.",
         "UMask": "0x1",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCS message class to BL Egress.",
         "UMask": "0x2",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "VNA Credits Returned",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_Q_VNA_CREDIT_RETURNS",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of VNA credits returned.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "VNA Credits Pending Return - Occupancy",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY",
-        "ExtSel": "1",
         "PerPkg": "1",
+        "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.",
         "Unit": "QPI LL"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-memory.json b/tools/perf/pmu-events/arch/x86/haswellx/uncore-memory.json
index c003daa9ed8cf..c005f51157227 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-memory.json
@@ -1,34 +1,53 @@
 [
     {
-        "BriefDescription": "DRAM Activate Count; Activate due to Read",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_M_ACT_COUNT.RD",
+        "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
+        "EventCode": "0x4",
+        "EventName": "LLC_MISSES.MEM_READ",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills).",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Activate Count; Activate due to Write",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_M_ACT_COUNT.WR",
+        "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
+        "EventCode": "0x4",
+        "EventName": "LLC_MISSES.MEM_WRITE",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM Activate Count; Activate due to Write",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_M_ACT_COUNT.BYP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
         "UMask": "0x8",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "DRAM Activate Count; Activate due to Read",
+        "EventCode": "0x1",
+        "EventName": "UNC_M_ACT_COUNT.RD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+        "UMask": "0x1",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "DRAM Activate Count; Activate due to Write",
+        "EventCode": "0x1",
+        "EventName": "UNC_M_ACT_COUNT.WR",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+        "UMask": "0x2",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "ACT command issued by 2 cycle bypass",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA1",
         "EventName": "UNC_M_BYP_CMDS.ACT",
         "PerPkg": "1",
@@ -37,7 +56,6 @@
     },
     {
         "BriefDescription": "CAS command issued by 2 cycle bypass",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA1",
         "EventName": "UNC_M_BYP_CMDS.CAS",
         "PerPkg": "1",
@@ -46,7 +64,6 @@
     },
     {
         "BriefDescription": "PRE command issued by 2 cycle bypass",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA1",
         "EventName": "UNC_M_BYP_CMDS.PRE",
         "PerPkg": "1",
@@ -54,282 +71,264 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.RD_REG",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
         "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
+        "EventName": "UNC_M_CAS_COUNT.ALL",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS commands issued on this channel.",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.RD",
         "PerPkg": "1",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills).",
         "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
         "EventCode": "0x4",
-        "EventName": "LLC_MISSES.MEM_READ",
+        "EventName": "UNC_M_CAS_COUNT.RD_REG",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x3",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Read CAS commands issued on this channel.  This includes both regular RD CAS commands as well as those with implicit Precharge.  AutoPre is only used in systems that are using closed page policy.  We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM",
         "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.WR_WMM",
+        "EventName": "UNC_M_CAS_COUNT.RD_RMM",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
         "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.WR_RMM",
+        "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the number of underfill reads that are issued by the memory controller.  This will generally be about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ.  While it is possible for underfills to be issed in both WMM and RMM, this event counts both.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM",
         "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.WR",
+        "EventName": "UNC_M_CAS_COUNT.RD_WMM",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
         "EventCode": "0x4",
-        "EventName": "LLC_MISSES.MEM_WRITE",
+        "EventName": "UNC_M_CAS_COUNT.WR",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0xC",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel.",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
         "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.ALL",
+        "EventName": "UNC_M_CAS_COUNT.WR_RMM",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of Opportunistic DRAM Write CAS commands issued on this channel while in Read-Major-Mode.",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
         "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.RD_WMM",
+        "EventName": "UNC_M_CAS_COUNT.WR_WMM",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode.",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.RD_RMM",
+        "BriefDescription": "DRAM Clockticks",
+        "EventName": "UNC_M_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM Clockticks",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_M_CLOCKTICKS",
+        "EventName": "UNC_M_DCLOCKTICKS",
         "PerPkg": "1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM Precharge All Commands",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_M_DRAM_PRE_ALL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that the precharge all command was sent.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Number of DRAM Refreshes Issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
-        "EventName": "UNC_M_DRAM_REFRESH.PANIC",
+        "EventName": "UNC_M_DRAM_REFRESH.HIGH",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of refreshes issued.",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Number of DRAM Refreshes Issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
-        "EventName": "UNC_M_DRAM_REFRESH.HIGH",
+        "EventName": "UNC_M_DRAM_REFRESH.PANIC",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of refreshes issued.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "ECC Correctable Errors",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of ECC errors detected and corrected by the iMC on this channel.  This counter is only useful with ECC DRAM devices.  This count will increment one time for each correction regardless of the number of bits corrected.  The iMC can correct up to 4 bit errors in independent channel mode and 8 bit errors in lockstep mode.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
         "EventCode": "0x7",
-        "EventName": "UNC_M_MAJOR_MODES.READ",
+        "EventName": "UNC_M_MAJOR_MODES.ISOCH",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group these two modes together so that we can use four counters to track each of the major modes at one time.  These major modes are used whenever there is an ISOCH txn in the memory controller.  In these mode, only ISOCH transactions are processed.",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
         "EventCode": "0x7",
-        "EventName": "UNC_M_MAJOR_MODES.WRITE",
+        "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode is used to drain starved underfill reads.  Regular reads and writes are blocked and only underfill reads will be processed.",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
         "EventCode": "0x7",
-        "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
+        "EventName": "UNC_M_MAJOR_MODES.READ",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode is the default mode for the iMC, as reads are generally more critical to forward progress than writes.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
         "EventCode": "0x7",
-        "EventName": "UNC_M_MAJOR_MODES.ISOCH",
+        "EventName": "UNC_M_MAJOR_MODES.WRITE",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is triggered when the WPQ hits high occupancy and causes writes to be higher priority than reads.  This can cause blips in the available read bandwidth in the system and temporarily increase read latencies in order to achieve better bus utilizations and higher bandwidth.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Channel DLLOFF Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x84",
         "EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Channel PPD Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "UNC_M_POWER_CHANNEL_PPD",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles when all the ranks in the channel are in PPD mode.  If IBT=off is enabled, then this can be used to count those cycles.  If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x4",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x8",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x10",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x20",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x40",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x80",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Critical Throttle Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x86",
         "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the iMC is in critical thermal throttling.  When this happens, all traffic is blocked.  This should be rare unless something bad is going on in the platform.  There is no filtering by rank for this event.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "UNC_M_POWER_PCU_THROTTLING",
-        "Counter": "0,1,2,3",
         "EventCode": "0x42",
         "EventName": "UNC_M_POWER_PCU_THROTTLING",
         "PerPkg": "1",
@@ -337,150 +336,157 @@
     },
     {
         "BriefDescription": "Clock-Enabled Self-Refresh",
-        "Counter": "0,1,2,3",
         "EventCode": "0x43",
         "EventName": "UNC_M_POWER_SELF_REFRESH",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock.  This happens in some package C-states.  For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing.  One use of this is for Monroe technology.  Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.; Thermal throttling is performed per DIMM.  We support 3 DIMMs per channel.  This ID allows us to filter by ID.",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x4",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x8",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x10",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x20",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x40",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x80",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Read Preemption Count; Read over Read Preemption",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts another read.",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Read Preemption Count; Read over Write Preemption",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts a write.",
         "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
         "EventCode": "0x2",
-        "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+        "EventName": "UNC_M_PRE_COUNT.BYP",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of the page close counter expiring.  This does not include implicit precharge commands sent in auto-precharge mode.",
         "UMask": "0x2",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
+        "EventCode": "0x2",
+        "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of page misses.  This does not include explicit precharge commands sent with CAS commands in Auto-Precharge mode.  This does not include PRE commands sent as a result of the page close counter expiration.",
+        "UMask": "0x1",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "DRAM Precharge commands.; Precharge due to read",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_M_PRE_COUNT.RD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
         "UMask": "0x4",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM Precharge commands.; Precharge due to write",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_M_PRE_COUNT.WR",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
         "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_M_PRE_COUNT.BYP",
+        "BriefDescription": "Read CAS issued with HIGH priority",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Read CAS issued with LOW priority",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA0",
         "EventName": "UNC_M_RD_CAS_PRIO.LOW",
         "PerPkg": "1",
@@ -489,25 +495,14 @@
     },
     {
         "BriefDescription": "Read CAS issued with MEDIUM priority",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA0",
         "EventName": "UNC_M_RD_CAS_PRIO.MED",
         "PerPkg": "1",
         "UMask": "0x2",
         "Unit": "iMC"
     },
-    {
-        "BriefDescription": "Read CAS issued with HIGH priority",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "iMC"
-    },
     {
         "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA0",
         "EventName": "UNC_M_RD_CAS_PRIO.PANIC",
         "PerPkg": "1",
@@ -515,1186 +510,1182 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK1",
+        "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK2",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK4",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK8",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK10",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK11",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK0",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK12",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK3",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK13",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 14",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK5",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK14",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 15",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK6",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK15",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK7",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK2",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK9",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK3",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK4",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK5",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK6",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK7",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK14",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK8",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK15",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK9",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
         "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; All Banks",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK1",
+        "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK2",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK4",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 10",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK8",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK10",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 11",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK11",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 12",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK0",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK12",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 13",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK3",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK13",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 14",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK5",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK14",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 15",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK6",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK15",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 2",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK7",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK2",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 3",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK9",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK3",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 4",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK4",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 5",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK5",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 6",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK6",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 7",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK7",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 8",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK14",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK8",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 9",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK15",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK9",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
         "UMask": "0x14",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 2; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_M_RD_CAS_RANK2.BANK0",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; All Banks",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK1",
+        "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 0",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK2",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 1",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK4",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 10",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK8",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK10",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 11",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK11",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 12",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK0",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK12",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 13",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK3",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK13",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 14",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK5",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK14",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 15",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK6",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK15",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 2",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK7",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK2",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 3",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK9",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK3",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 4",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK4",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 5",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK5",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 6",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK6",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 7",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK7",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 8",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK14",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK8",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 9",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK15",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK9",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
         "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; All Banks",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK1",
+        "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 0",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK2",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 1",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK4",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 10",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK8",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK10",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 11",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK11",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 12",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK0",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK12",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 13",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK3",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK13",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 14",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK5",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK14",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 15",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK6",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK15",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 2",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK7",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK2",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 3",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK9",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK3",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 4",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK4",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 5",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK5",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 6",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK6",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 7",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK7",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 8",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK14",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK8",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 9",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK15",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK9",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
         "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; All Banks",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK1",
+        "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 0",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK2",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 1",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK4",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 10",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK8",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK10",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 11",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK11",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 12",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK0",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK12",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 13",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK3",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK13",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 14",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK5",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK14",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 15",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK6",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK15",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 2",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK7",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK2",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 3",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK9",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK3",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 4",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK4",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 5",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK5",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 6",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK6",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 7",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK7",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 8",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK14",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK8",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 9",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK15",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK9",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
         "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; All Banks",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK1",
+        "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK2",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 1",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK4",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 10",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK8",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK10",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK11",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK0",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK12",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK3",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK13",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK5",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK14",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK6",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK15",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 2",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK7",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK2",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 3",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK9",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK3",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 4",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK4",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 5",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK5",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 6",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK6",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 7",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK7",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 8",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK14",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK8",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 9",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK15",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK9",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
         "UMask": "0x14",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Read Pending Queue Not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0x11",
         "EventName": "UNC_M_RPQ_CYCLES_NE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Read Pending Queue is not empty.  This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Read Pending Queue Allocations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_M_RPQ_INSERTS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "VMSE MXB write buffer occupancy",
-        "Counter": "0,1,2,3",
         "EventCode": "0x91",
         "EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY",
         "PerPkg": "1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in WMM",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in RMM",
         "EventCode": "0x90",
-        "EventName": "UNC_M_VMSE_WR_PUSH.WMM",
+        "EventName": "UNC_M_VMSE_WR_PUSH.RMM",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in RMM",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in WMM",
         "EventCode": "0x90",
-        "EventName": "UNC_M_VMSE_WR_PUSH.RMM",
+        "EventName": "UNC_M_VMSE_WR_PUSH.WMM",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH",
         "PerPkg": "1",
@@ -1703,7 +1694,6 @@
     },
     {
         "BriefDescription": "Transition from WMM to RMM because of low threshold",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "UNC_M_WMM_TO_RMM.STARVE",
         "PerPkg": "1",
@@ -1712,7 +1702,6 @@
     },
     {
         "BriefDescription": "Transition from WMM to RMM because of low threshold",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY",
         "PerPkg": "1",
@@ -1721,1177 +1710,1169 @@
     },
     {
         "BriefDescription": "Write Pending Queue Full Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_M_WPQ_CYCLES_FULL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Write Pending Queue Not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_M_WPQ_CYCLES_NE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Write Pending Queue CAM Match",
-        "Counter": "0,1,2,3",
         "EventCode": "0x23",
         "EventName": "UNC_M_WPQ_READ_HIT",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Write Pending Queue CAM Match",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_M_WPQ_WRITE_HIT",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Not getting the requested Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC1",
         "EventName": "UNC_M_WRONG_MM",
         "PerPkg": "1",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 0; All Banks",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
+        "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : All Banks",
+        "UMask": "0x10",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK0",
+        "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK1",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK2",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK10",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK4",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK11",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK8",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK12",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK13",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 14",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK14",
+        "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14",
+        "UMask": "0xe",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 15",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK15",
+        "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15",
+        "UMask": "0xf",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK2",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK3",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3",
         "UMask": "0x3",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK4",
+        "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4",
+        "UMask": "0x4",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK5",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5",
         "UMask": "0x5",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK6",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6",
         "UMask": "0x6",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK7",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7",
         "UMask": "0x7",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 8",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK8",
+        "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8",
+        "UMask": "0x8",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK9",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9",
         "UMask": "0x9",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK10",
-        "PerPkg": "1",
-        "UMask": "0xA",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK11",
-        "PerPkg": "1",
-        "UMask": "0xB",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK12",
-        "PerPkg": "1",
-        "UMask": "0xC",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK13",
-        "PerPkg": "1",
-        "UMask": "0xD",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 14",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK14",
-        "PerPkg": "1",
-        "UMask": "0xE",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 15",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK15",
-        "PerPkg": "1",
-        "UMask": "0xF",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
         "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; All Banks",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : All Banks",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 0",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK2",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 1",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK4",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 10",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK8",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK10",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 11",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK11",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 12",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK12",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 13",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK3",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK13",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 14",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK5",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK14",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 15",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK6",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK15",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 2",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK7",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK2",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 3",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK9",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK3",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 4",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK4",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 5",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK5",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 6",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK6",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 7",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK7",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 8",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK14",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK8",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 9",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK15",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK9",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
         "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; All Banks",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : All Banks",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 0",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK2",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 1",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK4",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 10",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK8",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK10",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 11",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK11",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 12",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK12",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 13",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK3",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK13",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 14",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK5",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK14",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 15",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK6",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK15",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 2",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK7",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK2",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 3",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK9",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK3",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 4",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK4",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 5",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK5",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 6",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK6",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 7",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK7",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 8",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK14",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK8",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 9",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK15",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK9",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
         "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; All Banks",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : All Banks",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 0",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK2",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 1",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK4",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 10",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK8",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK10",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 11",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK11",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 12",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK12",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 13",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK3",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK13",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 14",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK5",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK14",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 15",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK6",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK15",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 2",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK7",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK2",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 3",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK9",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK3",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 4",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK4",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 5",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK5",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 6",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK6",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 7",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK7",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 8",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK14",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK8",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 9",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK15",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK9",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
         "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; All Banks",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : All Banks",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 0",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK2",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 1",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK4",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 10",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK8",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK10",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 11",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK11",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 12",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK12",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 13",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK3",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK13",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 14",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK5",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK14",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 15",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK6",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK15",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 2",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK7",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK2",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 3",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK9",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK3",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 4",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK4",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 5",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK5",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 6",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK6",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 7",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK7",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 8",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK14",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK8",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 9",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK15",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK9",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
         "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; All Banks",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : All Banks",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK2",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK0",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK4",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK1",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 10",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK8",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK10",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 11",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK11",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK12",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK3",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK13",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK5",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK14",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK6",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK15",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 2",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK7",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK2",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 3",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK9",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK3",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 4",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK4",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 5",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK5",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 6",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK6",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK7",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 8",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK14",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK8",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 9",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK15",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK9",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANKG0",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
         "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANKG1",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
         "UMask": "0x12",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANKG2",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
         "UMask": "0x13",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANKG3",
         "PerPkg": "1",
+        "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
         "UMask": "0x14",
         "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "DRAM Clockticks",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_M_DCLOCKTICKS",
-        "PerPkg": "1",
-        "Unit": "iMC"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-other.json b/tools/perf/pmu-events/arch/x86/haswellx/uncore-other.json
index 135b59f34f37d..4c3e2a7941173 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-other.json
@@ -1,829 +1,816 @@
 [
     {
         "BriefDescription": "Total Write Cache Occupancy; Any Source",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.",
         "UMask": "0x1",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Total Write Cache Occupancy; Select Source",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register.  This register allows one to select one specific queue.  It is not possible to monitor multiple queues at a time.",
         "UMask": "0x2",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Clocks in the IRP",
-        "Counter": "0,1",
         "EventName": "UNC_I_CLOCKTICKS",
         "PerPkg": "1",
+        "PublicDescription": "Number of clocks in the IRP.",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Coherent Ops; PCIRdCur",
-        "Counter": "0,1",
+        "BriefDescription": "Coherent Ops; CLFlush",
         "EventCode": "0x13",
-        "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
+        "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+        "UMask": "0x80",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Coherent Ops; CRd",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_I_COHERENT_OPS.CRD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
         "UMask": "0x2",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Coherent Ops; DRd",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_I_COHERENT_OPS.DRD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
         "UMask": "0x4",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Coherent Ops; RFO",
-        "Counter": "0,1",
+        "BriefDescription": "Coherent Ops; PCIDCAHin5t",
         "EventCode": "0x13",
-        "EventName": "UNC_I_COHERENT_OPS.RFO",
+        "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+        "UMask": "0x20",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Coherent Ops; PCIRdCur",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+        "UMask": "0x1",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Coherent Ops; PCIItoM",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_I_COHERENT_OPS.PCITOM",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
         "UMask": "0x10",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Coherent Ops; PCIDCAHin5t",
-        "Counter": "0,1",
+        "BriefDescription": "Coherent Ops; RFO",
         "EventCode": "0x13",
-        "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
+        "EventName": "UNC_I_COHERENT_OPS.RFO",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+        "UMask": "0x8",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Coherent Ops; WbMtoI",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
         "UMask": "0x40",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Coherent Ops; CLFlush",
-        "Counter": "0,1",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
-        "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "IRP"
-    },
-    {
-        "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
-        "Counter": "0,1",
-        "EventCode": "0x14",
-        "EventName": "UNC_I_MISC0.FAST_REQ",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "IRP"
-    },
-    {
-        "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
-        "Counter": "0,1",
+        "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
         "EventCode": "0x14",
-        "EventName": "UNC_I_MISC0.FAST_REJ",
+        "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
+        "UMask": "0x10",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
         "PerPkg": "1",
+        "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
         "UMask": "0x4",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
         "PerPkg": "1",
+        "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
         "UMask": "0x8",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
-        "Counter": "0,1",
+        "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
         "EventCode": "0x14",
-        "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
+        "EventName": "UNC_I_MISC0.FAST_REJ",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
+        "UMask": "0x2",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
+        "EventCode": "0x14",
+        "EventName": "UNC_I_MISC0.FAST_REQ",
+        "PerPkg": "1",
+        "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
+        "UMask": "0x1",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_I_MISC0.FAST_XFER",
         "PerPkg": "1",
+        "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
         "UMask": "0x20",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_I_MISC0.PF_ACK_HINT",
         "PerPkg": "1",
+        "PublicDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary",
         "UMask": "0x40",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
-        "Counter": "0,1",
+        "BriefDescription": "Misc Events - Set 0; Prefetch TimeOut",
+        "EventCode": "0x14",
+        "EventName": "UNC_I_MISC0.PF_TIMEOUT",
+        "PerPkg": "1",
+        "PublicDescription": "Indicates the fetch for a previous prefetch wasn't accepted by the prefetch.   This happens in the case of a prefetch TimeOut",
+        "UMask": "0x80",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Misc Events - Set 1; Data Throttled",
         "EventCode": "0x15",
-        "EventName": "UNC_I_MISC1.SLOW_I",
+        "EventName": "UNC_I_MISC1.DATA_THROTTLE",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "IRP throttled switch data",
+        "UMask": "0x80",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
-        "Counter": "0,1",
+        "BriefDescription": "Misc Events - Set 1",
         "EventCode": "0x15",
-        "EventName": "UNC_I_MISC1.SLOW_S",
+        "EventName": "UNC_I_MISC1.LOST_FWD",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed",
+        "UMask": "0x10",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
-        "Counter": "0,1",
+        "BriefDescription": "Misc Events - Set 1; Received Invalid",
         "EventCode": "0x15",
-        "EventName": "UNC_I_MISC1.SLOW_E",
+        "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
+        "UMask": "0x20",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
-        "Counter": "0,1",
+        "BriefDescription": "Misc Events - Set 1; Received Valid",
         "EventCode": "0x15",
-        "EventName": "UNC_I_MISC1.SLOW_M",
+        "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
+        "UMask": "0x40",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 1",
-        "Counter": "0,1",
+        "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
         "EventCode": "0x15",
-        "EventName": "UNC_I_MISC1.LOST_FWD",
+        "EventName": "UNC_I_MISC1.SLOW_E",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
+        "UMask": "0x4",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Received Invalid",
-        "Counter": "0,1",
+        "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
         "EventCode": "0x15",
-        "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
+        "EventName": "UNC_I_MISC1.SLOW_I",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
+        "UMask": "0x1",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Received Valid",
-        "Counter": "0,1",
+        "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
         "EventCode": "0x15",
-        "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
+        "EventName": "UNC_I_MISC1.SLOW_M",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
+        "UMask": "0x8",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Data Throttled",
-        "Counter": "0,1",
+        "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
         "EventCode": "0x15",
-        "EventName": "UNC_I_MISC1.DATA_THROTTLE",
+        "EventName": "UNC_I_MISC1.SLOW_S",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
+        "UMask": "0x2",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "AK Ingress Occupancy",
-        "Counter": "0,1",
         "EventCode": "0xA",
         "EventName": "UNC_I_RxR_AK_INSERTS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the AK Ingress.  This queue is where the IRP receives responses from R2PCIe (the ring).",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
-        "Counter": "0,1",
         "EventCode": "0x4",
         "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "BL Ingress Occupancy - DRS",
-        "Counter": "0,1",
         "EventCode": "0x1",
         "EventName": "UNC_I_RxR_BL_DRS_INSERTS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "UNC_I_RxR_BL_DRS_OCCUPANCY",
-        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "BL Ingress Occupancy - NCB",
-        "Counter": "0,1",
         "EventCode": "0x2",
         "EventName": "UNC_I_RxR_BL_NCB_INSERTS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "UNC_I_RxR_BL_NCB_OCCUPANCY",
-        "Counter": "0,1",
         "EventCode": "0x8",
         "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
-        "Counter": "0,1",
         "EventCode": "0x6",
         "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the BL Ingress is full.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "BL Ingress Occupancy - NCS",
-        "Counter": "0,1",
         "EventCode": "0x3",
         "EventName": "UNC_I_RxR_BL_NCS_INSERTS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the BL Ingress.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "UNC_I_RxR_BL_NCS_OCCUPANCY",
-        "Counter": "0,1",
         "EventCode": "0x9",
         "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles.  This queue is where the IRP receives data from R2PCIe (the ring).  It is used for data returns from read requets as well as outbound MMIO writes.",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Snoop Responses; Miss",
-        "Counter": "0,1",
+        "BriefDescription": "Snoop Responses; Hit E or S",
         "EventCode": "0x17",
-        "EventName": "UNC_I_SNOOP_RESP.MISS",
+        "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Snoop Responses : Hit E or S",
+        "UMask": "0x4",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Snoop Responses; Hit I",
-        "Counter": "0,1",
         "EventCode": "0x17",
         "EventName": "UNC_I_SNOOP_RESP.HIT_I",
         "PerPkg": "1",
+        "PublicDescription": "Snoop Responses : Hit I",
         "UMask": "0x2",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Snoop Responses; Hit E or S",
-        "Counter": "0,1",
+        "BriefDescription": "Snoop Responses; Hit M",
         "EventCode": "0x17",
-        "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
+        "EventName": "UNC_I_SNOOP_RESP.HIT_M",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Snoop Responses : Hit M",
+        "UMask": "0x8",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Snoop Responses; Hit M",
-        "Counter": "0,1",
+        "BriefDescription": "Snoop Responses; Miss",
         "EventCode": "0x17",
-        "EventName": "UNC_I_SNOOP_RESP.HIT_M",
+        "EventName": "UNC_I_SNOOP_RESP.MISS",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Snoop Responses : Miss",
+        "UMask": "0x1",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Snoop Responses; SnpCode",
-        "Counter": "0,1",
         "EventCode": "0x17",
         "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
         "PerPkg": "1",
+        "PublicDescription": "Snoop Responses : SnpCode",
         "UMask": "0x10",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Snoop Responses; SnpData",
-        "Counter": "0,1",
         "EventCode": "0x17",
         "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
         "PerPkg": "1",
+        "PublicDescription": "Snoop Responses : SnpData",
         "UMask": "0x20",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Snoop Responses; SnpInv",
-        "Counter": "0,1",
         "EventCode": "0x17",
         "EventName": "UNC_I_SNOOP_RESP.SNPINV",
         "PerPkg": "1",
+        "PublicDescription": "Snoop Responses : SnpInv",
         "UMask": "0x40",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Inbound Transaction Count; Reads",
-        "Counter": "0,1",
+        "BriefDescription": "Inbound Transaction Count; Atomic",
         "EventCode": "0x16",
-        "EventName": "UNC_I_TRANSACTIONS.READS",
+        "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions",
+        "UMask": "0x10",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Inbound Transaction Count; Writes",
-        "Counter": "0,1",
+        "BriefDescription": "Inbound Transaction Count; Other",
         "EventCode": "0x16",
-        "EventName": "UNC_I_TRANSACTIONS.WRITES",
+        "EventName": "UNC_I_TRANSACTIONS.OTHER",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions.",
+        "UMask": "0x20",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Inbound Transaction Count; Read Prefetches",
-        "Counter": "0,1",
         "EventCode": "0x16",
         "EventName": "UNC_I_TRANSACTIONS.RD_PREF",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.",
         "UMask": "0x4",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Inbound Transaction Count; Write Prefetches",
-        "Counter": "0,1",
-        "EventCode": "0x16",
-        "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
-        "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "IRP"
-    },
-    {
-        "BriefDescription": "Inbound Transaction Count; Atomic",
-        "Counter": "0,1",
+        "BriefDescription": "Inbound Transaction Count; Reads",
         "EventCode": "0x16",
-        "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
+        "EventName": "UNC_I_TRANSACTIONS.READS",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).",
+        "UMask": "0x1",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Inbound Transaction Count; Other",
-        "Counter": "0,1",
+        "BriefDescription": "Inbound Transaction Count; Writes",
         "EventCode": "0x16",
-        "EventName": "UNC_I_TRANSACTIONS.OTHER",
+        "EventName": "UNC_I_TRANSACTIONS.WRITES",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests.  Each write request should have a prefetch, so there is no need to explicitly track these requests.  For writes that are tickled and have to retry, the counter will be incremented for each retry.",
+        "UMask": "0x2",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Inbound Transaction Count; Select Source",
-        "Counter": "0,1",
+        "BriefDescription": "Inbound Transaction Count; Write Prefetches",
         "EventCode": "0x16",
-        "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ",
+        "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of write prefetches.",
+        "UMask": "0x8",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "No AD Egress Credit Stalls",
-        "Counter": "0,1",
         "EventCode": "0x18",
         "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "No BL Egress Credit Stalls",
-        "Counter": "0,1",
         "EventCode": "0x19",
         "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Outbound Read Requests",
-        "Counter": "0,1",
         "EventCode": "0xE",
         "EventName": "UNC_I_TxR_DATA_INSERTS_NCB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Outbound Read Requests",
-        "Counter": "0,1",
         "EventCode": "0xF",
         "EventName": "UNC_I_TxR_DATA_INSERTS_NCS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Outbound Request Queue Occupancy",
-        "Counter": "0,1",
         "EventCode": "0xD",
         "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY",
         "PerPkg": "1",
-        "Unit": "IRP"
-    },
-    {
-        "BriefDescription": "Misc Events - Set 0; Prefetch TimeOut",
-        "Counter": "0,1",
-        "EventCode": "0x14",
-        "EventName": "UNC_I_MISC0.PF_TIMEOUT",
-        "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices).  This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.",
         "Unit": "IRP"
     },
     {
         "BriefDescription": "Number of uclks in domain",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_R2_CLOCKTICKS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of uclks in the R2PCIe uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
-        "Counter": "0,1",
+        "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
         "EventCode": "0x2D",
-        "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
+        "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x4",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
-        "Counter": "0,1",
+        "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
         "EventCode": "0x2D",
-        "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
+        "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "UMask": "0x8",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
-        "Counter": "0,1",
+        "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
         "EventCode": "0x2D",
-        "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
+        "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0x1",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
-        "Counter": "0,1",
+        "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
         "EventCode": "0x2D",
-        "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
+        "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0x2",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2PCIe IIO Credit Acquired; DRS",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.",
         "UMask": "0x8",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2PCIe IIO Credit Acquired; NCB",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.",
         "UMask": "0x10",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2PCIe IIO Credit Acquired; NCS",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.",
         "UMask": "0x20",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2PCIe IIO Credits in Use; DRS",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_R2_IIO_CREDITS_USED.DRS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.",
         "UMask": "0x8",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2PCIe IIO Credits in Use; NCB",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_R2_IIO_CREDITS_USED.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.",
         "UMask": "0x10",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2PCIe IIO Credits in Use; NCS",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_R2_IIO_CREDITS_USED.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.",
         "UMask": "0x20",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "R2 AD Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x7",
-        "EventName": "UNC_R2_RING_AD_USED.CW_EVEN",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "R2PCIe"
-    },
-    {
-        "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "R2 AD Ring in Use; Counterclockwise",
         "EventCode": "0x7",
-        "EventName": "UNC_R2_RING_AD_USED.CW_ODD",
+        "EventName": "UNC_R2_RING_AD_USED.CCW",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xc",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CCW_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
         "UMask": "0x4",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CCW_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CW",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
         "UMask": "0x3",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "R2 AD Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "R2 AD Ring in Use; Clockwise and Even",
         "EventCode": "0x7",
-        "EventName": "UNC_R2_RING_AD_USED.CCW",
+        "EventName": "UNC_R2_RING_AD_USED.CW_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "AK Ingress Bounced; Up",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_R2_RING_AK_BOUNCES.UP",
+        "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd",
+        "EventCode": "0x7",
+        "EventName": "UNC_R2_RING_AD_USED.CW_ODD",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+        "UMask": "0x2",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "AK Ingress Bounced; Dn",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_R2_RING_AK_BOUNCES.DN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.",
         "UMask": "0x2",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "R2 AK Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8",
-        "EventName": "UNC_R2_RING_AK_USED.CW_EVEN",
+        "BriefDescription": "AK Ingress Bounced; Up",
+        "EventCode": "0x12",
+        "EventName": "UNC_R2_RING_AK_BOUNCES.UP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.",
         "UMask": "0x1",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "R2 AK Ring in Use; Counterclockwise",
         "EventCode": "0x8",
-        "EventName": "UNC_R2_RING_AK_USED.CW_ODD",
+        "EventName": "UNC_R2_RING_AK_USED.CCW",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xc",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CCW_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
         "UMask": "0x4",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CCW_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CW",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
         "UMask": "0x3",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "R2 AK Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "R2 AK Ring in Use; Clockwise and Even",
         "EventCode": "0x8",
-        "EventName": "UNC_R2_RING_AK_USED.CCW",
+        "EventName": "UNC_R2_RING_AK_USED.CW_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "R2 BL Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9",
-        "EventName": "UNC_R2_RING_BL_USED.CW_EVEN",
+        "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd",
+        "EventCode": "0x8",
+        "EventName": "UNC_R2_RING_AK_USED.CW_ODD",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+        "UMask": "0x2",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "R2 BL Ring in Use; Counterclockwise",
         "EventCode": "0x9",
-        "EventName": "UNC_R2_RING_BL_USED.CW_ODD",
+        "EventName": "UNC_R2_RING_BL_USED.CCW",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xc",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CCW_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
         "UMask": "0x4",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CCW_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CW",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
         "UMask": "0x3",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "R2 BL Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "R2 BL Ring in Use; Clockwise and Even",
         "EventCode": "0x9",
-        "EventName": "UNC_R2_RING_BL_USED.CCW",
+        "EventName": "UNC_R2_RING_BL_USED.CW_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "R2 IV Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd",
+        "EventCode": "0x9",
+        "EventName": "UNC_R2_RING_BL_USED.CW_ODD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+        "UMask": "0x2",
+        "Unit": "R2PCIe"
+    },
+    {
+        "BriefDescription": "R2 IV Ring in Use; Any",
         "EventCode": "0xA",
-        "EventName": "UNC_R2_RING_IV_USED.CW",
+        "EventName": "UNC_R2_RING_IV_USED.ANY",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+        "UMask": "0xf",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 IV Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_R2_RING_IV_USED.CCW",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+        "UMask": "0xc",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "R2 IV Ring in Use; Any",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "R2 IV Ring in Use; Clockwise",
         "EventCode": "0xA",
-        "EventName": "UNC_R2_RING_IV_USED.ANY",
+        "EventName": "UNC_R2_RING_IV_USED.CW",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+        "UMask": "0x3",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "Ingress Cycles Not Empty; NCB",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R2_RxR_CYCLES_NE.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
         "UMask": "0x10",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "Ingress Cycles Not Empty; NCS",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R2_RxR_CYCLES_NE.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
         "UMask": "0x20",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "Ingress Allocations; NCB",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R2_RxR_INSERTS.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
         "UMask": "0x10",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "Ingress Allocations; NCS",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R2_RxR_INSERTS.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
         "UMask": "0x20",
         "Unit": "R2PCIe"
     },
@@ -832,24 +819,25 @@
         "EventCode": "0x13",
         "EventName": "UNC_R2_RxR_OCCUPANCY.DRS",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue",
         "UMask": "0x8",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "SBo0 Credits Acquired; For AD Ring",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
         "UMask": "0x1",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "SBo0 Credits Acquired; For BL Ring",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
         "UMask": "0x2",
         "Unit": "R2PCIe"
     },
@@ -858,6 +846,7 @@
         "EventCode": "0x2A",
         "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
         "UMask": "0x1",
         "Unit": "R2PCIe"
     },
@@ -866,42 +855,43 @@
         "EventCode": "0x2A",
         "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
         "UMask": "0x2",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
-        "Counter": "0,1",
         "EventCode": "0x2C",
         "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
         "UMask": "0x1",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
-        "Counter": "0,1",
+        "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
         "EventCode": "0x2C",
-        "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD",
+        "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+        "UMask": "0x4",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
-        "Counter": "0,1",
+        "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
         "EventCode": "0x2C",
-        "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL",
+        "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+        "UMask": "0x2",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
-        "Counter": "0,1",
         "EventCode": "0x2C",
         "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
         "UMask": "0x8",
         "Unit": "R2PCIe"
     },
@@ -910,6 +900,7 @@
         "EventCode": "0x25",
         "EventName": "UNC_R2_TxR_CYCLES_FULL.AD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AD Egress Queue",
         "UMask": "0x1",
         "Unit": "R2PCIe"
     },
@@ -918,6 +909,7 @@
         "EventCode": "0x25",
         "EventName": "UNC_R2_TxR_CYCLES_FULL.AK",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AK Egress Queue",
         "UMask": "0x2",
         "Unit": "R2PCIe"
     },
@@ -926,6 +918,7 @@
         "EventCode": "0x25",
         "EventName": "UNC_R2_TxR_CYCLES_FULL.BL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; BL Egress Queue",
         "UMask": "0x4",
         "Unit": "R2PCIe"
     },
@@ -934,6 +927,7 @@
         "EventCode": "0x23",
         "EventName": "UNC_R2_TxR_CYCLES_NE.AD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.; AD Egress Queue",
         "UMask": "0x1",
         "Unit": "R2PCIe"
     },
@@ -942,6 +936,7 @@
         "EventCode": "0x23",
         "EventName": "UNC_R2_TxR_CYCLES_NE.AK",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.; AK Egress Queue",
         "UMask": "0x2",
         "Unit": "R2PCIe"
     },
@@ -950,911 +945,896 @@
         "EventCode": "0x23",
         "EventName": "UNC_R2_TxR_CYCLES_NE.BL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty.  This tracks one of the three rings that are used by the R2PCIe agent.  This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single Egress queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.; BL Egress Queue",
         "UMask": "0x4",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "Egress CCW NACK; AD CCW",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R2_TxR_NACK_CW.DN_AD",
         "PerPkg": "1",
+        "PublicDescription": "AD CounterClockwise Egress Queue",
         "UMask": "0x1",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "Egress CCW NACK; BL CCW",
-        "Counter": "0,1",
+        "BriefDescription": "Egress CCW NACK; AK CCW",
         "EventCode": "0x26",
-        "EventName": "UNC_R2_TxR_NACK_CW.DN_BL",
+        "EventName": "UNC_R2_TxR_NACK_CW.DN_AK",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "AK CounterClockwise Egress Queue",
+        "UMask": "0x4",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "Egress CCW NACK; AK CCW",
-        "Counter": "0,1",
+        "BriefDescription": "Egress CCW NACK; BL CCW",
         "EventCode": "0x26",
-        "EventName": "UNC_R2_TxR_NACK_CW.DN_AK",
+        "EventName": "UNC_R2_TxR_NACK_CW.DN_BL",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "BL CounterClockwise Egress Queue",
+        "UMask": "0x2",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "Egress CCW NACK; AK CCW",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R2_TxR_NACK_CW.UP_AD",
         "PerPkg": "1",
+        "PublicDescription": "BL CounterClockwise Egress Queue",
         "UMask": "0x8",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "Egress CCW NACK; BL CCW",
-        "Counter": "0,1",
+        "BriefDescription": "Egress CCW NACK; BL CW",
         "EventCode": "0x26",
-        "EventName": "UNC_R2_TxR_NACK_CW.UP_BL",
+        "EventName": "UNC_R2_TxR_NACK_CW.UP_AK",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "AD Clockwise Egress Queue",
+        "UMask": "0x20",
         "Unit": "R2PCIe"
     },
     {
-        "BriefDescription": "Egress CCW NACK; BL CW",
-        "Counter": "0,1",
+        "BriefDescription": "Egress CCW NACK; BL CCW",
         "EventCode": "0x26",
-        "EventName": "UNC_R2_TxR_NACK_CW.UP_AK",
+        "EventName": "UNC_R2_TxR_NACK_CW.UP_BL",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "AD CounterClockwise Egress Queue",
+        "UMask": "0x10",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "Number of uclks in domain",
-        "Counter": "0,1,2",
         "EventCode": "0x1",
         "EventName": "UNC_R3_CLOCKTICKS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of uclks in the QPI uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x1F",
-        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8",
+        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 10",
+        "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x1F",
-        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9",
+        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 11",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x1F",
-        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10",
+        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 12",
+        "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x1F",
-        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11",
+        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 13",
+        "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x1F",
-        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12",
+        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 14&16",
+        "UMask": "0x40",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x1F",
-        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13",
+        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 8",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x1F",
-        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16",
+        "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 9",
+        "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x1F",
         "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO_15_17",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 15&17",
         "UMask": "0x80",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 0",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 1",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 2",
         "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 3",
         "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 4",
         "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 5",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 6",
         "UMask": "0x40",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 7",
         "UMask": "0x80",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "HA/R2 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2D",
         "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA0",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "HA/R2 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2D",
         "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA1",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "HA/R2 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2D",
         "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCB Messages",
         "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "HA/R2 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2D",
         "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCS Messages",
         "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "IOT Backpressure",
-        "Counter": "0,1,2",
         "EventCode": "0xB",
-        "EventName": "UNC_R3_IOT_BACKPRESSURE.SAT",
+        "EventName": "UNC_R3_IOT_BACKPRESSURE.HUB",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "IOT Backpressure",
-        "Counter": "0,1,2",
         "EventCode": "0xB",
-        "EventName": "UNC_R3_IOT_BACKPRESSURE.HUB",
+        "EventName": "UNC_R3_IOT_BACKPRESSURE.SAT",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "IOT Common Trigger Sequencer - Hi",
-        "Counter": "0,1,2",
         "EventCode": "0xD",
         "EventName": "UNC_R3_IOT_CTS_HI.CTS2",
         "PerPkg": "1",
+        "PublicDescription": "Debug Mask/Match Tie-Ins",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "IOT Common Trigger Sequencer - Hi",
-        "Counter": "0,1,2",
         "EventCode": "0xD",
         "EventName": "UNC_R3_IOT_CTS_HI.CTS3",
         "PerPkg": "1",
+        "PublicDescription": "Debug Mask/Match Tie-Ins",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "IOT Common Trigger Sequencer - Lo",
-        "Counter": "0,1,2",
         "EventCode": "0xC",
         "EventName": "UNC_R3_IOT_CTS_LO.CTS0",
         "PerPkg": "1",
+        "PublicDescription": "Debug Mask/Match Tie-Ins",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "IOT Common Trigger Sequencer - Lo",
-        "Counter": "0,1,2",
         "EventCode": "0xC",
         "EventName": "UNC_R3_IOT_CTS_LO.CTS1",
         "PerPkg": "1",
+        "PublicDescription": "Debug Mask/Match Tie-Ins",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI0 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x20",
-        "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA",
+        "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 HOM Messages",
+        "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI0 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x20",
-        "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM",
+        "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 NDR Messages",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI0 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x20",
         "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 SNP Messages",
         "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI0 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x20",
-        "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR",
+        "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 HOM Messages",
+        "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI0 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x20",
-        "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM",
+        "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 NDR Messages",
+        "UMask": "0x40",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI0 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x20",
         "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 SNP Messages",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI0 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x20",
-        "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR",
+        "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VNA",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI0 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x21",
-        "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA",
+        "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 HOM Messages",
+        "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI0 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x21",
-        "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM",
+        "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 NDR Messages",
+        "UMask": "0x40",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI0 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x21",
         "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 SNP Messages",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI0 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x21",
-        "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR",
+        "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VNA",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI1 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2E",
-        "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA",
+        "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 HOM Messages",
+        "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI1 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2E",
-        "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM",
+        "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 NDR Messages",
+        "UMask": "0x40",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI1 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 SNP Messages",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI1 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2E",
-        "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR",
+        "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VNA",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI1 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2F",
-        "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA",
+        "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 HOM Messages",
+        "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI1 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2F",
-        "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM",
+        "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 NDR Messages",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI1 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2F",
         "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 SNP Messages",
         "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI1 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2F",
-        "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR",
+        "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 HOM Messages",
+        "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI1 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2F",
-        "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM",
+        "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 NDR Messages",
+        "UMask": "0x40",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI1 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2F",
         "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 SNP Messages",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "QPI1 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2F",
-        "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR",
-        "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "R3QPI"
-    },
-    {
-        "BriefDescription": "R3 AD Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0x7",
-        "EventName": "UNC_R3_RING_AD_USED.CW_EVEN",
+        "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VNA",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2",
+        "BriefDescription": "R3 AD Ring in Use; Counterclockwise",
         "EventCode": "0x7",
-        "EventName": "UNC_R3_RING_AD_USED.CW_ODD",
+        "EventName": "UNC_R3_RING_AD_USED.CCW",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xc",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2",
         "EventCode": "0x7",
         "EventName": "UNC_R3_RING_AD_USED.CCW_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
         "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2",
         "EventCode": "0x7",
         "EventName": "UNC_R3_RING_AD_USED.CCW_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R3 AD Ring in Use; Clockwise",
-        "Counter": "0,1,2",
         "EventCode": "0x7",
         "EventName": "UNC_R3_RING_AD_USED.CW",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
         "UMask": "0x3",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "R3 AD Ring in Use; Counterclockwise",
-        "Counter": "0,1,2",
+        "BriefDescription": "R3 AD Ring in Use; Clockwise and Even",
         "EventCode": "0x7",
-        "EventName": "UNC_R3_RING_AD_USED.CCW",
+        "EventName": "UNC_R3_RING_AD_USED.CW_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "R3 AK Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0x8",
-        "EventName": "UNC_R3_RING_AK_USED.CW_EVEN",
+        "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd",
+        "EventCode": "0x7",
+        "EventName": "UNC_R3_RING_AD_USED.CW_ODD",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+        "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2",
+        "BriefDescription": "R3 AK Ring in Use; Counterclockwise",
         "EventCode": "0x8",
-        "EventName": "UNC_R3_RING_AK_USED.CW_ODD",
+        "EventName": "UNC_R3_RING_AK_USED.CCW",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xc",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2",
         "EventCode": "0x8",
         "EventName": "UNC_R3_RING_AK_USED.CCW_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
         "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2",
         "EventCode": "0x8",
         "EventName": "UNC_R3_RING_AK_USED.CCW_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R3 AK Ring in Use; Clockwise",
-        "Counter": "0,1,2",
         "EventCode": "0x8",
         "EventName": "UNC_R3_RING_AK_USED.CW",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
         "UMask": "0x3",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "R3 AK Ring in Use; Counterclockwise",
-        "Counter": "0,1,2",
+        "BriefDescription": "R3 AK Ring in Use; Clockwise and Even",
         "EventCode": "0x8",
-        "EventName": "UNC_R3_RING_AK_USED.CCW",
+        "EventName": "UNC_R3_RING_AK_USED.CW_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "R3 BL Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0x9",
-        "EventName": "UNC_R3_RING_BL_USED.CW_EVEN",
+        "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd",
+        "EventCode": "0x8",
+        "EventName": "UNC_R3_RING_AK_USED.CW_ODD",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+        "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2",
+        "BriefDescription": "R3 BL Ring in Use; Counterclockwise",
         "EventCode": "0x9",
-        "EventName": "UNC_R3_RING_BL_USED.CW_ODD",
+        "EventName": "UNC_R3_RING_BL_USED.CCW",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+        "UMask": "0xc",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2",
         "EventCode": "0x9",
         "EventName": "UNC_R3_RING_BL_USED.CCW_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
         "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2",
         "EventCode": "0x9",
         "EventName": "UNC_R3_RING_BL_USED.CCW_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R3 BL Ring in Use; Clockwise",
-        "Counter": "0,1,2",
         "EventCode": "0x9",
         "EventName": "UNC_R3_RING_BL_USED.CW",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
         "UMask": "0x3",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "R3 BL Ring in Use; Counterclockwise",
-        "Counter": "0,1,2",
+        "BriefDescription": "R3 BL Ring in Use; Clockwise and Even",
         "EventCode": "0x9",
-        "EventName": "UNC_R3_RING_BL_USED.CCW",
+        "EventName": "UNC_R3_RING_BL_USED.CW_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "R3 IV Ring in Use; Clockwise",
-        "Counter": "0,1,2",
-        "EventCode": "0xA",
-        "EventName": "UNC_R3_RING_IV_USED.CW",
+        "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd",
+        "EventCode": "0x9",
+        "EventName": "UNC_R3_RING_BL_USED.CW_ODD",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+        "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R3 IV Ring in Use; Any",
-        "Counter": "0,1,2",
         "EventCode": "0xA",
         "EventName": "UNC_R3_RING_IV_USED.ANY",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+        "UMask": "0xf",
+        "Unit": "R3QPI"
+    },
+    {
+        "BriefDescription": "R3 IV Ring in Use; Clockwise",
+        "EventCode": "0xA",
+        "EventName": "UNC_R3_RING_IV_USED.CW",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+        "UMask": "0x3",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "Ring Stop Starved; AK",
-        "Counter": "0,1,2",
         "EventCode": "0xE",
         "EventName": "UNC_R3_RING_SINK_STARVED.AK",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the ringstop is in starvation (per ring)",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "Ingress Cycles Not Empty; HOM",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R3_RxR_CYCLES_NE.HOM",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
+    {
+        "BriefDescription": "Ingress Cycles Not Empty; NDR",
+        "EventCode": "0x10",
+        "EventName": "UNC_R3_RxR_CYCLES_NE.NDR",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+        "UMask": "0x4",
+        "Unit": "R3QPI"
+    },
     {
         "BriefDescription": "Ingress Cycles Not Empty; SNP",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R3_RxR_CYCLES_NE.SNP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "Ingress Cycles Not Empty; NDR",
-        "Counter": "0,1",
-        "EventCode": "0x10",
-        "EventName": "UNC_R3_RxR_CYCLES_NE.NDR",
+        "BriefDescription": "VN1 Ingress Cycles Not Empty; DRS",
+        "EventCode": "0x14",
+        "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.DRS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VN1 Ingress Cycles Not Empty; HOM",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.HOM",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Ingress Cycles Not Empty; SNP",
-        "Counter": "0,1",
+        "BriefDescription": "VN1 Ingress Cycles Not Empty; NCB",
         "EventCode": "0x14",
-        "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.SNP",
+        "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCB",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
+        "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Ingress Cycles Not Empty; NDR",
-        "Counter": "0,1",
+        "BriefDescription": "VN1 Ingress Cycles Not Empty; NCS",
         "EventCode": "0x14",
-        "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NDR",
+        "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
+        "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Ingress Cycles Not Empty; DRS",
-        "Counter": "0,1",
+        "BriefDescription": "VN1 Ingress Cycles Not Empty; NDR",
         "EventCode": "0x14",
-        "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.DRS",
+        "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NDR",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+        "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Ingress Cycles Not Empty; NCB",
-        "Counter": "0,1",
+        "BriefDescription": "VN1 Ingress Cycles Not Empty; SNP",
         "EventCode": "0x14",
-        "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCB",
+        "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.SNP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of cycles when the QPI VN1  Ingress is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
+        "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Ingress Cycles Not Empty; NCS",
-        "Counter": "0,1",
-        "EventCode": "0x14",
-        "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCS",
+        "BriefDescription": "Ingress Allocations; DRS",
+        "EventCode": "0x11",
+        "EventName": "UNC_R3_RxR_INSERTS.DRS",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "Ingress Allocations; HOM",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R3_RxR_INSERTS.HOM",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
-    {
-        "BriefDescription": "Ingress Allocations; SNP",
-        "Counter": "0,1",
-        "EventCode": "0x11",
-        "EventName": "UNC_R3_RxR_INSERTS.SNP",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "R3QPI"
-    },
-    {
-        "BriefDescription": "Ingress Allocations; NDR",
-        "Counter": "0,1",
-        "EventCode": "0x11",
-        "EventName": "UNC_R3_RxR_INSERTS.NDR",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "R3QPI"
-    },
-    {
-        "BriefDescription": "Ingress Allocations; DRS",
-        "Counter": "0,1",
-        "EventCode": "0x11",
-        "EventName": "UNC_R3_RxR_INSERTS.DRS",
-        "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "R3QPI"
-    },
     {
         "BriefDescription": "Ingress Allocations; NCB",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R3_RxR_INSERTS.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
         "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "Ingress Allocations; NCS",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R3_RxR_INSERTS.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Ingress Allocations; HOM",
-        "Counter": "0,1",
-        "EventCode": "0x15",
-        "EventName": "UNC_R3_RxR_INSERTS_VN1.HOM",
+        "BriefDescription": "Ingress Allocations; NDR",
+        "EventCode": "0x11",
+        "EventName": "UNC_R3_RxR_INSERTS.NDR",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+        "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Ingress Allocations; SNP",
-        "Counter": "0,1",
-        "EventCode": "0x15",
-        "EventName": "UNC_R3_RxR_INSERTS_VN1.SNP",
+        "BriefDescription": "Ingress Allocations; SNP",
+        "EventCode": "0x11",
+        "EventName": "UNC_R3_RxR_INSERTS.SNP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the QPI Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Ingress Allocations; NDR",
-        "Counter": "0,1",
+        "BriefDescription": "VN1 Ingress Allocations; DRS",
         "EventCode": "0x15",
-        "EventName": "UNC_R3_RxR_INSERTS_VN1.NDR",
+        "EventName": "UNC_R3_RxR_INSERTS_VN1.DRS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Ingress Allocations; DRS",
-        "Counter": "0,1",
+        "BriefDescription": "VN1 Ingress Allocations; HOM",
         "EventCode": "0x15",
-        "EventName": "UNC_R3_RxR_INSERTS_VN1.DRS",
+        "EventName": "UNC_R3_RxR_INSERTS_VN1.HOM",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VN1 Ingress Allocations; NCB",
-        "Counter": "0,1",
         "EventCode": "0x15",
         "EventName": "UNC_R3_RxR_INSERTS_VN1.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
         "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VN1 Ingress Allocations; NCS",
-        "Counter": "0,1",
         "EventCode": "0x15",
         "EventName": "UNC_R3_RxR_INSERTS_VN1.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Ingress Occupancy Accumulator; HOM",
-        "EventCode": "0x13",
-        "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.HOM",
+        "BriefDescription": "VN1 Ingress Allocations; NDR",
+        "EventCode": "0x15",
+        "EventName": "UNC_R3_RxR_INSERTS_VN1.NDR",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+        "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Ingress Occupancy Accumulator; SNP",
-        "EventCode": "0x13",
-        "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.SNP",
+        "BriefDescription": "VN1 Ingress Allocations; SNP",
+        "EventCode": "0x15",
+        "EventName": "UNC_R3_RxR_INSERTS_VN1.SNP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the QPI VN1  Ingress.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Ingress Occupancy Accumulator; NDR",
+        "BriefDescription": "VN1 Ingress Occupancy Accumulator; DRS",
         "EventCode": "0x13",
-        "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NDR",
+        "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.DRS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Ingress Occupancy Accumulator; DRS",
+        "BriefDescription": "VN1 Ingress Occupancy Accumulator; HOM",
         "EventCode": "0x13",
-        "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.DRS",
+        "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.HOM",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; HOM Ingress Queue",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
@@ -1862,6 +1842,7 @@
         "EventCode": "0x13",
         "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; NCB Ingress Queue",
         "UMask": "0x10",
         "Unit": "R3QPI"
     },
@@ -1870,24 +1851,43 @@
         "EventCode": "0x13",
         "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; NCS Ingress Queue",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
+    {
+        "BriefDescription": "VN1 Ingress Occupancy Accumulator; NDR",
+        "EventCode": "0x13",
+        "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NDR",
+        "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; NDR Ingress Queue",
+        "UMask": "0x4",
+        "Unit": "R3QPI"
+    },
+    {
+        "BriefDescription": "VN1 Ingress Occupancy Accumulator; SNP",
+        "EventCode": "0x13",
+        "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.SNP",
+        "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of a given QPI VN1  Ingress queue in each cycles.  This tracks one of the three ring Ingress buffers.  This can be used with the QPI VN1  Ingress Not Empty event to calculate average occupancy or the QPI VN1  Ingress Allocations event in order to calculate average queuing latency.; SNP Ingress Queue",
+        "UMask": "0x2",
+        "Unit": "R3QPI"
+    },
     {
         "BriefDescription": "SBo0 Credits Acquired; For AD Ring",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "SBo0 Credits Acquired; For BL Ring",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
@@ -1896,6 +1896,7 @@
         "EventCode": "0x2A",
         "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
@@ -1904,24 +1905,25 @@
         "EventCode": "0x2A",
         "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "SBo1 Credits Acquired; For AD Ring",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "SBo1 Credits Acquired; For BL Ring",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
@@ -1930,6 +1932,7 @@
         "EventCode": "0x2B",
         "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
@@ -1938,390 +1941,390 @@
         "EventCode": "0x2B",
         "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
-        "Counter": "0,1",
         "EventCode": "0x2C",
         "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
-        "Counter": "0,1",
+        "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
         "EventCode": "0x2C",
-        "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD",
+        "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_BL",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+        "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
-        "Counter": "0,1",
+        "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
         "EventCode": "0x2C",
-        "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_BL",
+        "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
+        "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
-        "Counter": "0,1",
         "EventCode": "0x2C",
         "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available.  Per Sbo, per Ring.",
         "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "Egress CCW NACK; AD CCW",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R3_TxR_NACK.DN_AD",
         "PerPkg": "1",
+        "PublicDescription": "AD CounterClockwise Egress Queue",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
-    {
-        "BriefDescription": "Egress CCW NACK; BL CCW",
-        "Counter": "0,1",
-        "EventCode": "0x26",
-        "EventName": "UNC_R3_TxR_NACK.DN_BL",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "R3QPI"
-    },
     {
         "BriefDescription": "Egress CCW NACK; AK CCW",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R3_TxR_NACK.DN_AK",
         "PerPkg": "1",
+        "PublicDescription": "AK CounterClockwise Egress Queue",
         "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "Egress CCW NACK; AK CCW",
-        "Counter": "0,1",
+        "BriefDescription": "Egress CCW NACK; BL CCW",
         "EventCode": "0x26",
-        "EventName": "UNC_R3_TxR_NACK.UP_AD",
+        "EventName": "UNC_R3_TxR_NACK.DN_BL",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "BL CounterClockwise Egress Queue",
+        "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "Egress CCW NACK; BL CCW",
-        "Counter": "0,1",
+        "BriefDescription": "Egress CCW NACK; AK CCW",
         "EventCode": "0x26",
-        "EventName": "UNC_R3_TxR_NACK.UP_BL",
+        "EventName": "UNC_R3_TxR_NACK.UP_AD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "BL CounterClockwise Egress Queue",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "Egress CCW NACK; BL CW",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R3_TxR_NACK.UP_AK",
         "PerPkg": "1",
+        "PublicDescription": "AD Clockwise Egress Queue",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class",
-        "Counter": "0,1",
-        "EventCode": "0x37",
-        "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "R3QPI"
-    },
-    {
-        "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class",
-        "Counter": "0,1",
-        "EventCode": "0x37",
-        "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP",
+        "BriefDescription": "Egress CCW NACK; BL CCW",
+        "EventCode": "0x26",
+        "EventName": "UNC_R3_TxR_NACK.UP_BL",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "AD CounterClockwise Egress Queue",
+        "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class",
         "EventCode": "0x37",
-        "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR",
+        "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class",
         "EventCode": "0x37",
-        "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS",
+        "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Message Class",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ?",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN0 Credit Used; HOM Message Class",
-        "Counter": "0,1",
-        "EventCode": "0x36",
-        "EventName": "UNC_R3_VN0_CREDITS_USED.HOM",
+        "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class",
+        "EventCode": "0x37",
+        "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN0 Credit Used; SNP Message Class",
-        "Counter": "0,1",
-        "EventCode": "0x36",
-        "EventName": "UNC_R3_VN0_CREDITS_USED.SNP",
+        "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class",
+        "EventCode": "0x37",
+        "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed.  This should generally be a rare situation.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN0 Credit Used; NDR Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VN0 Credit Used; DRS Message Class",
         "EventCode": "0x36",
-        "EventName": "UNC_R3_VN0_CREDITS_USED.NDR",
+        "EventName": "UNC_R3_VN0_CREDITS_USED.DRS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN0 Credit Used; DRS Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VN0 Credit Used; HOM Message Class",
         "EventCode": "0x36",
-        "EventName": "UNC_R3_VN0_CREDITS_USED.DRS",
+        "EventName": "UNC_R3_VN0_CREDITS_USED.HOM",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VN0 Credit Used; NCB Message Class",
-        "Counter": "0,1",
         "EventCode": "0x36",
         "EventName": "UNC_R3_VN0_CREDITS_USED.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VN0 Credit Used; NCS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x36",
         "EventName": "UNC_R3_VN0_CREDITS_USED.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ?",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Message Class",
-        "Counter": "0,1",
-        "EventCode": "0x39",
-        "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM",
+        "BriefDescription": "VN0 Credit Used; NDR Message Class",
+        "EventCode": "0x36",
+        "EventName": "UNC_R3_VN0_CREDITS_USED.NDR",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Message Class",
-        "Counter": "0,1",
-        "EventCode": "0x39",
-        "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP",
+        "BriefDescription": "VN0 Credit Used; SNP Message Class",
+        "EventCode": "0x36",
+        "EventName": "UNC_R3_VN0_CREDITS_USED.SNP",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Message Class",
         "EventCode": "0x39",
-        "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR",
+        "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Message Class",
         "EventCode": "0x39",
-        "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS",
+        "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCB Message Class",
-        "Counter": "0,1",
         "EventCode": "0x39",
         "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x39",
         "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ?",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Credit Used; HOM Message Class",
-        "Counter": "0,1",
-        "EventCode": "0x38",
-        "EventName": "UNC_R3_VN1_CREDITS_USED.HOM",
+        "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Message Class",
+        "EventCode": "0x39",
+        "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Credit Used; SNP Message Class",
-        "Counter": "0,1",
-        "EventCode": "0x38",
-        "EventName": "UNC_R3_VN1_CREDITS_USED.SNP",
+        "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Message Class",
+        "EventCode": "0x39",
+        "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a request failed to acquire a VN1 credit.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed.  This should generally be a rare situation.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.",
         "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Credit Used; NDR Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VN1 Credit Used; DRS Message Class",
         "EventCode": "0x38",
-        "EventName": "UNC_R3_VN1_CREDITS_USED.NDR",
+        "EventName": "UNC_R3_VN1_CREDITS_USED.DRS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VN1 Credit Used; DRS Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VN1 Credit Used; HOM Message Class",
         "EventCode": "0x38",
-        "EventName": "UNC_R3_VN1_CREDITS_USED.DRS",
+        "EventName": "UNC_R3_VN1_CREDITS_USED.HOM",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VN1 Credit Used; NCB Message Class",
-        "Counter": "0,1",
         "EventCode": "0x38",
         "EventName": "UNC_R3_VN1_CREDITS_USED.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VN1 Credit Used; NCS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x38",
         "EventName": "UNC_R3_VN1_CREDITS_USED.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS).  NCS is commonly used for ?",
         "UMask": "0x20",
         "Unit": "R3QPI"
     },
+    {
+        "BriefDescription": "VN1 Credit Used; NDR Message Class",
+        "EventCode": "0x38",
+        "EventName": "UNC_R3_VN1_CREDITS_USED.NDR",
+        "PerPkg": "1",
+        "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
+        "Unit": "R3QPI"
+    },
+    {
+        "BriefDescription": "VN1 Credit Used; SNP Message Class",
+        "EventCode": "0x38",
+        "EventName": "UNC_R3_VN1_CREDITS_USED.SNP",
+        "PerPkg": "1",
+        "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.",
+        "UMask": "0x2",
+        "Unit": "R3QPI"
+    },
     {
         "BriefDescription": "VNA credit Acquisitions; HOM Message Class",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of QPI VNA Credit acquisitions.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder.  VNA credits are used by all message classes in order to communicate across QPI.  If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool.  Note that a single packet may require multiple flit buffers (i.e. when data is being transferred).  Therefore, this event will increment by the number of credits acquired in each cycle.  Filtering based on message class is not provided.  One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
         "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "VNA credit Acquisitions; HOM Message Class",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL",
         "PerPkg": "1",
+        "PublicDescription": "Number of QPI VNA Credit acquisitions.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder.  VNA credits are used by all message classes in order to communicate across QPI.  If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool.  Note that a single packet may require multiple flit buffers (i.e. when data is being transferred).  Therefore, this event will increment by the number of credits acquired in each cycle.  Filtering based on message class is not provided.  One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
         "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VNA Credit Reject; HOM Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VNA Credit Reject; DRS Message Class",
         "EventCode": "0x34",
-        "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM",
+        "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Data Response (DRS).  DRS is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+        "UMask": "0x8",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VNA Credit Reject; SNP Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VNA Credit Reject; HOM Message Class",
         "EventCode": "0x34",
-        "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP",
+        "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for the Home (HOM) message class.  HOM is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VNA Credit Reject; NDR Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VNA Credit Reject; NCB Message Class",
         "EventCode": "0x34",
-        "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR",
+        "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Broadcast (NCB).  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x10",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VNA Credit Reject; DRS Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VNA Credit Reject; NCS Message Class",
         "EventCode": "0x34",
-        "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS",
+        "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Standard (NCS).",
+        "UMask": "0x20",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VNA Credit Reject; NCB Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VNA Credit Reject; NDR Message Class",
         "EventCode": "0x34",
-        "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB",
+        "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "R3QPI"
     },
     {
-        "BriefDescription": "VNA Credit Reject; NCS Message Class",
-        "Counter": "0,1",
+        "BriefDescription": "VNA Credit Reject; SNP Message Class",
         "EventCode": "0x34",
-        "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS",
+        "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full).  It is possible to filter this event by message class.  Some packets use more than one flit buffer, and therefore must acquire multiple credits.  Therefore, one could get a reject even if the VNA credits were not fully used up.  The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress).  VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially.  This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Snoop (SNP) message class.  SNP is used for outgoing snoops.  Note that snoop responses flow on the HOM message class.",
+        "UMask": "0x2",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "Bounce Control",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_S_BOUNCE_CONTROL",
         "PerPkg": "1",
@@ -2329,184 +2332,182 @@
     },
     {
         "BriefDescription": "Uncore Clocks",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_S_CLOCKTICKS",
         "PerPkg": "1",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "FaST wire asserted",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_S_FAST_ASSERTED",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "AD Ring In Use; Up and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1B",
-        "EventName": "UNC_S_RING_AD_USED.UP_EVEN",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "SBO"
-    },
-    {
-        "BriefDescription": "AD Ring In Use; Up and Odd",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "AD Ring In Use; Down",
         "EventCode": "0x1B",
-        "EventName": "UNC_S_RING_AD_USED.UP_ODD",
+        "EventName": "UNC_S_RING_AD_USED.DOWN",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0xc",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "AD Ring In Use; Down and Event",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_S_RING_AD_USED.DOWN_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.",
         "UMask": "0x4",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "AD Ring In Use; Down and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_S_RING_AD_USED.DOWN_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "AD Ring In Use; Up",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_S_RING_AD_USED.UP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
         "UMask": "0x3",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "AD Ring In Use; Down",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "AD Ring In Use; Up and Even",
         "EventCode": "0x1B",
-        "EventName": "UNC_S_RING_AD_USED.DOWN",
+        "EventName": "UNC_S_RING_AD_USED.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "AK Ring In Use; Up and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1C",
-        "EventName": "UNC_S_RING_AK_USED.UP_EVEN",
+        "BriefDescription": "AD Ring In Use; Up and Odd",
+        "EventCode": "0x1B",
+        "EventName": "UNC_S_RING_AD_USED.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+        "UMask": "0x2",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "AK Ring In Use; Up and Odd",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "AK Ring In Use; Down",
         "EventCode": "0x1C",
-        "EventName": "UNC_S_RING_AK_USED.UP_ODD",
+        "EventName": "UNC_S_RING_AK_USED.DOWN",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0xc",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "AK Ring In Use; Down and Event",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_S_RING_AK_USED.DOWN_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.",
         "UMask": "0x4",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "AK Ring In Use; Down and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_S_RING_AK_USED.DOWN_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "AK Ring In Use; Up",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_S_RING_AK_USED.UP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
         "UMask": "0x3",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "AK Ring In Use; Down",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "AK Ring In Use; Up and Even",
         "EventCode": "0x1C",
-        "EventName": "UNC_S_RING_AK_USED.DOWN",
+        "EventName": "UNC_S_RING_AK_USED.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "BL Ring in Use; Up and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1D",
-        "EventName": "UNC_S_RING_BL_USED.UP_EVEN",
+        "BriefDescription": "AK Ring In Use; Up and Odd",
+        "EventCode": "0x1C",
+        "EventName": "UNC_S_RING_AK_USED.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+        "UMask": "0x2",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "BL Ring in Use; Up and Odd",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "BL Ring in Use; Down",
         "EventCode": "0x1D",
-        "EventName": "UNC_S_RING_BL_USED.UP_ODD",
+        "EventName": "UNC_S_RING_BL_USED.DOWN",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0xc",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Down and Event",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_S_RING_BL_USED.DOWN_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.",
         "UMask": "0x4",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Down and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_S_RING_BL_USED.DOWN_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
         "UMask": "0x8",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Up",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1D",
-        "EventName": "UNC_S_RING_BL_USED.UP",
+        "EventName": "UNC_S_RING_BL_USED.UP",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x3",
+        "Unit": "SBO"
+    },
+    {
+        "BriefDescription": "BL Ring in Use; Up and Even",
+        "EventCode": "0x1D",
+        "EventName": "UNC_S_RING_BL_USED.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+        "UMask": "0x1",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "BL Ring in Use; Down",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "BL Ring in Use; Up and Odd",
         "EventCode": "0x1D",
-        "EventName": "UNC_S_RING_BL_USED.DOWN",
+        "EventName": "UNC_S_RING_BL_USED.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+        "UMask": "0x2",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Number of LLC responses that bounced on the Ring",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Number of LLC responses that bounced on the Ring.",
         "EventCode": "0x5",
         "EventName": "UNC_S_RING_BOUNCES.AD_CACHE",
         "PerPkg": "1",
@@ -2515,7 +2516,6 @@
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.; Acknowledgements to core",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_S_RING_BOUNCES.AK_CORE",
         "PerPkg": "1",
@@ -2524,7 +2524,6 @@
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.; Data Responses to core",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_S_RING_BOUNCES.BL_CORE",
         "PerPkg": "1",
@@ -2532,8 +2531,7 @@
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
         "EventCode": "0x5",
         "EventName": "UNC_S_RING_BOUNCES.IV_CORE",
         "PerPkg": "1",
@@ -2542,25 +2540,24 @@
     },
     {
         "BriefDescription": "BL Ring in Use; Any",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
-        "EventName": "UNC_S_RING_IV_USED.UP",
+        "EventName": "UNC_S_RING_IV_USED.DN",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  There is only 1 IV ring in HSX.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+        "UMask": "0xc",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Any",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
-        "EventName": "UNC_S_RING_IV_USED.DN",
+        "EventName": "UNC_S_RING_IV_USED.UP",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  There is only 1 IV ring in HSX.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+        "UMask": "0x3",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "UNC_S_RING_SINK_STARVED.AD_CACHE",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_S_RING_SINK_STARVED.AD_CACHE",
         "PerPkg": "1",
@@ -2569,7 +2566,6 @@
     },
     {
         "BriefDescription": "UNC_S_RING_SINK_STARVED.AK_CORE",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_S_RING_SINK_STARVED.AK_CORE",
         "PerPkg": "1",
@@ -2578,7 +2574,6 @@
     },
     {
         "BriefDescription": "UNC_S_RING_SINK_STARVED.BL_CORE",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_S_RING_SINK_STARVED.BL_CORE",
         "PerPkg": "1",
@@ -2587,277 +2582,275 @@
     },
     {
         "BriefDescription": "UNC_S_RING_SINK_STARVED.IV_CORE",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_S_RING_SINK_STARVED.IV_CORE",
         "PerPkg": "1",
         "UMask": "0x8",
         "Unit": "SBO"
     },
-    {
-        "BriefDescription": "Injection Starvation; AD - Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_S_RxR_BUSY_STARVED.AD_CRD",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "SBO"
-    },
     {
         "BriefDescription": "Injection Starvation; AD - Bounces",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_S_RxR_BUSY_STARVED.AD_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is  being sent.",
         "UMask": "0x2",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Injection Starvation; BL - Credits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Injection Starvation; AD - Credits",
         "EventCode": "0x15",
-        "EventName": "UNC_S_RxR_BUSY_STARVED.BL_CRD",
+        "EventName": "UNC_S_RxR_BUSY_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is  being sent.",
+        "UMask": "0x1",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Injection Starvation; BL - Bounces",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_S_RxR_BUSY_STARVED.BL_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is  being sent.",
         "UMask": "0x8",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Bypass; AD - Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_S_RxR_BYPASS.AD_CRD",
+        "BriefDescription": "Injection Starvation; BL - Credits",
+        "EventCode": "0x15",
+        "EventName": "UNC_S_RxR_BUSY_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is  being sent.",
+        "UMask": "0x4",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Bypass; AD - Bounces",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_S_RxR_BYPASS.AD_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Bypass the Sbo Ingress.",
         "UMask": "0x2",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Bypass; BL - Credits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Bypass; AD - Credits",
         "EventCode": "0x12",
-        "EventName": "UNC_S_RxR_BYPASS.BL_CRD",
+        "EventName": "UNC_S_RxR_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Bypass the Sbo Ingress.",
+        "UMask": "0x1",
+        "Unit": "SBO"
+    },
+    {
+        "BriefDescription": "Bypass; AK",
+        "EventCode": "0x12",
+        "EventName": "UNC_S_RxR_BYPASS.AK",
+        "PerPkg": "1",
+        "PublicDescription": "Bypass the Sbo Ingress.",
+        "UMask": "0x10",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Bypass; BL - Bounces",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_S_RxR_BYPASS.BL_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Bypass the Sbo Ingress.",
         "UMask": "0x8",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Bypass; AK",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Bypass; BL - Credits",
         "EventCode": "0x12",
-        "EventName": "UNC_S_RxR_BYPASS.AK",
+        "EventName": "UNC_S_RxR_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Bypass the Sbo Ingress.",
+        "UMask": "0x4",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Bypass; IV",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_S_RxR_BYPASS.IV",
         "PerPkg": "1",
+        "PublicDescription": "Bypass the Sbo Ingress.",
         "UMask": "0x20",
         "Unit": "SBO"
     },
-    {
-        "BriefDescription": "Injection Starvation; AD - Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_S_RxR_CRD_STARVED.AD_CRD",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "SBO"
-    },
     {
         "BriefDescription": "Injection Starvation; AD - Bounces",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_S_RxR_CRD_STARVED.AD_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit.",
         "UMask": "0x2",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Injection Starvation; BL - Credits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Injection Starvation; AD - Credits",
         "EventCode": "0x14",
-        "EventName": "UNC_S_RxR_CRD_STARVED.BL_CRD",
+        "EventName": "UNC_S_RxR_CRD_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+        "UMask": "0x1",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Injection Starvation; BL - Bounces",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Injection Starvation; AK",
         "EventCode": "0x14",
-        "EventName": "UNC_S_RxR_CRD_STARVED.BL_BNC",
+        "EventName": "UNC_S_RxR_CRD_STARVED.AK",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+        "UMask": "0x10",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Injection Starvation; AK",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Injection Starvation; BL - Bounces",
         "EventCode": "0x14",
-        "EventName": "UNC_S_RxR_CRD_STARVED.AK",
+        "EventName": "UNC_S_RxR_CRD_STARVED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+        "UMask": "0x8",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Injection Starvation; IV",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Injection Starvation; BL - Credits",
         "EventCode": "0x14",
-        "EventName": "UNC_S_RxR_CRD_STARVED.IV",
+        "EventName": "UNC_S_RxR_CRD_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+        "UMask": "0x4",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Injection Starvation; IVF Credit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_S_RxR_CRD_STARVED.IFV",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit.",
         "UMask": "0x40",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Ingress Allocations; AD - Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_S_RxR_INSERTS.AD_CRD",
+        "BriefDescription": "Injection Starvation; IV",
+        "EventCode": "0x14",
+        "EventName": "UNC_S_RxR_CRD_STARVED.IV",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time.  In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+        "UMask": "0x20",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Ingress Allocations; AD - Bounces",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_S_RxR_INSERTS.AD_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring.",
         "UMask": "0x2",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Ingress Allocations; BL - Credits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Ingress Allocations; AD - Credits",
         "EventCode": "0x13",
-        "EventName": "UNC_S_RxR_INSERTS.BL_CRD",
+        "EventName": "UNC_S_RxR_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring.",
+        "UMask": "0x1",
+        "Unit": "SBO"
+    },
+    {
+        "BriefDescription": "Ingress Allocations; AK",
+        "EventCode": "0x13",
+        "EventName": "UNC_S_RxR_INSERTS.AK",
+        "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring.",
+        "UMask": "0x10",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Ingress Allocations; BL - Bounces",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_S_RxR_INSERTS.BL_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring.",
         "UMask": "0x8",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Ingress Allocations; AK",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Ingress Allocations; BL - Credits",
         "EventCode": "0x13",
-        "EventName": "UNC_S_RxR_INSERTS.AK",
+        "EventName": "UNC_S_RxR_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring.",
+        "UMask": "0x4",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Ingress Allocations; IV",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_S_RxR_INSERTS.IV",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Sbo Ingress  The Ingress is used to queue up requests received from the ring.",
         "UMask": "0x20",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Ingress Occupancy; AD - Credits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Ingress Occupancy; AD - Bounces",
         "EventCode": "0x11",
-        "EventName": "UNC_S_RxR_OCCUPANCY.AD_CRD",
+        "EventName": "UNC_S_RxR_OCCUPANCY.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring.",
+        "UMask": "0x2",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Ingress Occupancy; AD - Bounces",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Ingress Occupancy; AD - Credits",
         "EventCode": "0x11",
-        "EventName": "UNC_S_RxR_OCCUPANCY.AD_BNC",
+        "EventName": "UNC_S_RxR_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring.",
+        "UMask": "0x1",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Ingress Occupancy; BL - Credits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Ingress Occupancy; AK",
         "EventCode": "0x11",
-        "EventName": "UNC_S_RxR_OCCUPANCY.BL_CRD",
+        "EventName": "UNC_S_RxR_OCCUPANCY.AK",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring.",
+        "UMask": "0x10",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Ingress Occupancy; BL - Bounces",
-        "Counter": "0,1,2,3",
         "EventCode": "0x11",
         "EventName": "UNC_S_RxR_OCCUPANCY.BL_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring.",
         "UMask": "0x8",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Ingress Occupancy; AK",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Ingress Occupancy; BL - Credits",
         "EventCode": "0x11",
-        "EventName": "UNC_S_RxR_OCCUPANCY.AK",
+        "EventName": "UNC_S_RxR_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring.",
+        "UMask": "0x4",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Ingress Occupancy; IV",
-        "Counter": "0,1,2,3",
         "EventCode": "0x11",
         "EventName": "UNC_S_RxR_OCCUPANCY.IV",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo.  The Ingress is used to queue up requests received from the ring.",
         "UMask": "0x20",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "UNC_S_TxR_ADS_USED.AD",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_S_TxR_ADS_USED.AD",
         "PerPkg": "1",
@@ -2866,7 +2859,6 @@
     },
     {
         "BriefDescription": "UNC_S_TxR_ADS_USED.AK",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_S_TxR_ADS_USED.AK",
         "PerPkg": "1",
@@ -2875,7 +2867,6 @@
     },
     {
         "BriefDescription": "UNC_S_TxR_ADS_USED.BL",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_S_TxR_ADS_USED.BL",
         "PerPkg": "1",
@@ -2883,288 +2874,287 @@
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Egress Allocations; AD - Credits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Egress Allocations; AD - Bounces",
         "EventCode": "0x2",
-        "EventName": "UNC_S_TxR_INSERTS.AD_CRD",
+        "EventName": "UNC_S_TxR_INSERTS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring.",
+        "UMask": "0x2",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Egress Allocations; AD - Bounces",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Egress Allocations; AD - Credits",
         "EventCode": "0x2",
-        "EventName": "UNC_S_TxR_INSERTS.AD_BNC",
+        "EventName": "UNC_S_TxR_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring.",
+        "UMask": "0x1",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Egress Allocations; BL - Credits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Egress Allocations; AK",
         "EventCode": "0x2",
-        "EventName": "UNC_S_TxR_INSERTS.BL_CRD",
+        "EventName": "UNC_S_TxR_INSERTS.AK",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring.",
+        "UMask": "0x10",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Egress Allocations; BL - Bounces",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_S_TxR_INSERTS.BL_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring.",
         "UMask": "0x8",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Egress Allocations; AK",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Egress Allocations; BL - Credits",
         "EventCode": "0x2",
-        "EventName": "UNC_S_TxR_INSERTS.AK",
+        "EventName": "UNC_S_TxR_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring.",
+        "UMask": "0x4",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Egress Allocations; IV",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_S_TxR_INSERTS.IV",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Sbo Egress.  The Egress is used to queue up requests destined for the ring.",
         "UMask": "0x20",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Egress Occupancy; AD - Credits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Egress Occupancy; AD - Bounces",
         "EventCode": "0x1",
-        "EventName": "UNC_S_TxR_OCCUPANCY.AD_CRD",
+        "EventName": "UNC_S_TxR_OCCUPANCY.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring.",
+        "UMask": "0x2",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Egress Occupancy; AD - Bounces",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Egress Occupancy; AD - Credits",
         "EventCode": "0x1",
-        "EventName": "UNC_S_TxR_OCCUPANCY.AD_BNC",
+        "EventName": "UNC_S_TxR_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring.",
+        "UMask": "0x1",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Egress Occupancy; BL - Credits",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Egress Occupancy; AK",
         "EventCode": "0x1",
-        "EventName": "UNC_S_TxR_OCCUPANCY.BL_CRD",
+        "EventName": "UNC_S_TxR_OCCUPANCY.AK",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring.",
+        "UMask": "0x10",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Egress Occupancy; BL - Bounces",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_S_TxR_OCCUPANCY.BL_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring.",
         "UMask": "0x8",
         "Unit": "SBO"
     },
     {
-        "BriefDescription": "Egress Occupancy; AK",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Egress Occupancy; BL - Credits",
         "EventCode": "0x1",
-        "EventName": "UNC_S_TxR_OCCUPANCY.AK",
+        "EventName": "UNC_S_TxR_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring.",
+        "UMask": "0x4",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Egress Occupancy; IV",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_S_TxR_OCCUPANCY.IV",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Sbo.  The egress is used to queue up requests destined for the ring.",
         "UMask": "0x20",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Injection Starvation; Onto AD Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_S_TxR_STARVED.AD",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
         "UMask": "0x1",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Injection Starvation; Onto AK Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_S_TxR_STARVED.AK",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
         "UMask": "0x2",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Injection Starvation; Onto BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_S_TxR_STARVED.BL",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
         "UMask": "0x4",
         "Unit": "SBO"
     },
     {
         "BriefDescription": "Injection Starvation; Onto IV Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_S_TxR_STARVED.IV",
         "PerPkg": "1",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
         "UMask": "0x8",
         "Unit": "SBO"
     },
+    {
+        "BriefDescription": "UNC_U_CLOCKTICKS",
+        "EventName": "UNC_U_CLOCKTICKS",
+        "PerPkg": "1",
+        "Unit": "UBOX"
+    },
     {
         "BriefDescription": "VLW Received",
-        "Counter": "0,1",
         "EventCode": "0x42",
         "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
         "PerPkg": "1",
+        "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.   Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
         "UMask": "0x8",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "Filter Match",
-        "Counter": "0,1",
         "EventCode": "0x41",
-        "EventName": "UNC_U_FILTER_MATCH.ENABLE",
+        "EventName": "UNC_U_FILTER_MATCH.DISABLE",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+        "UMask": "0x2",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "Filter Match",
-        "Counter": "0,1",
         "EventCode": "0x41",
-        "EventName": "UNC_U_FILTER_MATCH.DISABLE",
+        "EventName": "UNC_U_FILTER_MATCH.ENABLE",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+        "UMask": "0x1",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "Filter Match",
-        "Counter": "0,1",
         "EventCode": "0x41",
-        "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE",
+        "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+        "UMask": "0x8",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "Filter Match",
-        "Counter": "0,1",
         "EventCode": "0x41",
-        "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
+        "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable).  Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+        "UMask": "0x4",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
-        "Counter": "0,1",
         "EventCode": "0x45",
         "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
         "PerPkg": "1",
+        "PublicDescription": "PHOLD cycles.  Filter from source CoreID.",
         "UMask": "0x1",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "RACU Request",
-        "Counter": "0,1",
         "EventCode": "0x46",
         "EventName": "UNC_U_RACU_REQUESTS",
         "PerPkg": "1",
+        "PublicDescription": "Number outstanding register requests within message channel tracker",
         "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Monitor Sent to T0; Monitor T0",
-        "Counter": "0,1",
-        "EventCode": "0x43",
-        "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "UBOX"
-    },
-    {
-        "BriefDescription": "Monitor Sent to T0; Monitor T1",
-        "Counter": "0,1",
+        "BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
         "EventCode": "0x43",
-        "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
+        "EventName": "UNC_U_U2C_EVENTS.CMC",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+        "UMask": "0x10",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "Monitor Sent to T0; Livelock",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.LIVELOCK",
         "PerPkg": "1",
+        "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
         "UMask": "0x4",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "Monitor Sent to T0; LTError",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.LTERROR",
         "PerPkg": "1",
+        "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
         "UMask": "0x8",
         "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
-        "Counter": "0,1",
+        "BriefDescription": "Monitor Sent to T0; Monitor T0",
         "EventCode": "0x43",
-        "EventName": "UNC_U_U2C_EVENTS.CMC",
+        "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
+        "UMask": "0x1",
         "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
-        "Counter": "0,1",
+        "BriefDescription": "Monitor Sent to T0; Monitor T1",
         "EventCode": "0x43",
-        "EventName": "UNC_U_U2C_EVENTS.UMC",
+        "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
+        "UMask": "0x2",
         "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Monitor Sent to T0; Trap",
-        "Counter": "0,1",
+        "BriefDescription": "Monitor Sent to T0; Other",
         "EventCode": "0x43",
-        "EventName": "UNC_U_U2C_EVENTS.TRAP",
+        "EventName": "UNC_U_U2C_EVENTS.OTHER",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Events coming from Uncore can be sent to one or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI",
+        "UMask": "0x80",
         "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Monitor Sent to T0; Other",
-        "Counter": "0,1",
+        "BriefDescription": "Monitor Sent to T0; Trap",
         "EventCode": "0x43",
-        "EventName": "UNC_U_U2C_EVENTS.OTHER",
+        "EventName": "UNC_U_U2C_EVENTS.TRAP",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+        "UMask": "0x40",
         "Unit": "UBOX"
     },
     {
-        "BriefDescription": "UNC_U_CLOCKTICKS",
-        "Counter": "0,1",
-        "EventName": "UNC_U_CLOCKTICKS",
+        "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
+        "EventCode": "0x43",
+        "EventName": "UNC_U_U2C_EVENTS.UMC",
         "PerPkg": "1",
+        "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+        "UMask": "0x20",
         "Unit": "UBOX"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-power.json b/tools/perf/pmu-events/arch/x86/haswellx/uncore-power.json
index 86b7c22af96b5..daebf1050acbf 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-power.json
@@ -1,497 +1,497 @@
 [
     {
         "BriefDescription": "pclk Cycles",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_P_CLOCKTICKS",
         "PerPkg": "1",
+        "PublicDescription": "The PCU runs off a fixed 800 MHz clock.  This event counts the number of pclk cycles measured while the counter was enabled.  The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_P_CORE0_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6A",
         "EventName": "UNC_P_CORE10_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6B",
         "EventName": "UNC_P_CORE11_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6C",
         "EventName": "UNC_P_CORE12_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6D",
         "EventName": "UNC_P_CORE13_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6E",
         "EventName": "UNC_P_CORE14_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6F",
         "EventName": "UNC_P_CORE15_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x70",
         "EventName": "UNC_P_CORE16_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "UNC_P_CORE17_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x61",
         "EventName": "UNC_P_CORE1_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x62",
         "EventName": "UNC_P_CORE2_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x63",
         "EventName": "UNC_P_CORE3_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x64",
         "EventName": "UNC_P_CORE4_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x65",
         "EventName": "UNC_P_CORE5_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x66",
         "EventName": "UNC_P_CORE6_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x67",
         "EventName": "UNC_P_CORE7_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x68",
         "EventName": "UNC_P_CORE8_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x69",
         "EventName": "UNC_P_CORE9_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x30",
         "EventName": "UNC_P_DEMOTIONS_CORE0",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_P_DEMOTIONS_CORE1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3A",
         "EventName": "UNC_P_DEMOTIONS_CORE10",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3B",
         "EventName": "UNC_P_DEMOTIONS_CORE11",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "UNC_P_DEMOTIONS_CORE12",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3D",
         "EventName": "UNC_P_DEMOTIONS_CORE13",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3E",
         "EventName": "UNC_P_DEMOTIONS_CORE14",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3F",
         "EventName": "UNC_P_DEMOTIONS_CORE15",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_P_DEMOTIONS_CORE16",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_P_DEMOTIONS_CORE17",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_P_DEMOTIONS_CORE2",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_P_DEMOTIONS_CORE3",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "UNC_P_DEMOTIONS_CORE4",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_P_DEMOTIONS_CORE5",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x36",
         "EventName": "UNC_P_DEMOTIONS_CORE6",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x37",
         "EventName": "UNC_P_DEMOTIONS_CORE7",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x38",
         "EventName": "UNC_P_DEMOTIONS_CORE8",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_P_DEMOTIONS_CORE9",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Frequency Residency",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB",
         "EventName": "UNC_P_FREQ_BAND0_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Frequency Residency",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC",
         "EventName": "UNC_P_FREQ_BAND1_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Frequency Residency",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD",
         "EventName": "UNC_P_FREQ_BAND2_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Frequency Residency",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE",
         "EventName": "UNC_P_FREQ_BAND3_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  One can use all four counters with this event, so it is possible to track up to 4 configurable bands.  One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Thermal Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when thermal conditions are the upper limit on frequency.  This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature.  This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "OS Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_P_FREQ_MAX_OS_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the OS is the upper limit on frequency.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Power Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when power is the upper limit on frequency.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x73",
         "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower.  This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW.  This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Cycles spent changing Frequency",
-        "Counter": "0,1,2,3",
         "EventCode": "0x74",
         "EventName": "UNC_P_FREQ_TRANS_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the system is changing frequency.  This can not be filtered by thread ID.  One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Memory Phase Shedding Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2F",
         "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the PCU has triggered memory phase shedding.  This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the package was in C0.  This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert).  Residency events do not include transition times.",
+        "Unit": "PCU"
+    },
+    {
+        "BriefDescription": "Package C State Residency - C1E",
+        "EventCode": "0x4E",
+        "EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the package was in C1E.  This event can be used in conjunction with edge detect to count C1E entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C2E",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2B",
         "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the package was in C2E.  This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2C",
         "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the package was in C3.  This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C6",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2D",
         "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the package was in C6.  This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C7 State Residency",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the package was in C7.  This event can be used in conjunction with edge detect to count C7 entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Number of cores in C-State; C0 and C1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
         "PerPkg": "1",
+        "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Number of cores in C-State; C3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
         "PerPkg": "1",
+        "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Number of cores in C-State; C6 and C7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
         "PerPkg": "1",
+        "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "External Prochot",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that we are in external PROCHOT mode.  This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Internal Prochot",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that we are in Internal PROCHOT mode.  This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Total Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x72",
         "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions across all cores.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "UNC_P_UFS_TRANSITIONS_NO_CHANGE",
-        "Counter": "0,1,2,3",
         "EventCode": "0x79",
         "EventName": "UNC_P_UFS_TRANSITIONS_NO_CHANGE",
         "PerPkg": "1",
+        "PublicDescription": "Ring GV with same final and initial frequency",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "VR Hot",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x42",
-        "EventName": "UNC_P_VR_HOT_CYCLES",
-        "PerPkg": "1",
-        "Unit": "PCU"
-    },
-    {
-        "BriefDescription": "Package C State Residency - C1E",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4E",
-        "EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES",
+        "BriefDescription": "UNC_P_UFS_TRANSITIONS_RING_GV",
+        "EventCode": "0x79",
+        "EventName": "UNC_P_UFS_TRANSITIONS_RING_GV",
         "PerPkg": "1",
+        "PublicDescription": "Ring GV with same final and initial frequency",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "UNC_P_UFS_TRANSITIONS_RING_GV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x79",
-        "EventName": "UNC_P_UFS_TRANSITIONS_RING_GV",
+        "BriefDescription": "VR Hot",
+        "EventCode": "0x42",
+        "EventName": "UNC_P_VR_HOT_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR is hot.  Does not cover DRAM VRs",
         "Unit": "PCU"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json b/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json
index 57d2a6452fecf..87a4ec1ee7d71 100644
--- a/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Load misses in all DTLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
         "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS",
         "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
         "PublicDescription": "Number of cache load STLB hits. No page walk.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (2M)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
         "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
@@ -41,8 +33,6 @@
     },
     {
         "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (4K)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
         "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
@@ -51,8 +41,6 @@
     },
     {
         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
         "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.",
@@ -61,8 +49,6 @@
     },
     {
         "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
         "SampleAfterValue": "2000003",
@@ -70,8 +56,6 @@
     },
     {
         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
         "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.",
@@ -80,8 +64,6 @@
     },
     {
         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
         "PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.",
@@ -90,8 +72,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
         "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
@@ -100,8 +80,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
         "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
@@ -110,8 +88,6 @@
     },
     {
         "BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS",
         "PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.",
@@ -120,8 +96,6 @@
     },
     {
         "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT",
         "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
@@ -130,8 +104,6 @@
     },
     {
         "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (2M)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
         "PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
@@ -140,8 +112,6 @@
     },
     {
         "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (4K)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
         "PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
@@ -150,8 +120,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
         "PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).",
@@ -160,8 +128,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
         "SampleAfterValue": "100003",
@@ -169,8 +135,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
         "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.",
@@ -179,8 +143,6 @@
     },
     {
         "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
         "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.",
@@ -189,8 +151,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_DURATION",
         "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB store misses.",
@@ -199,8 +159,6 @@
     },
     {
         "BriefDescription": "Cycle count for an Extended Page table walk.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4f",
         "EventName": "EPT.WALK_CYCLES",
         "SampleAfterValue": "2000003",
@@ -208,8 +166,6 @@
     },
     {
         "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xae",
         "EventName": "ITLB.ITLB_FLUSH",
         "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.",
@@ -218,8 +174,6 @@
     },
     {
         "BriefDescription": "Misses at all ITLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
         "PublicDescription": "Misses in ITLB that causes a page walk of any page size.",
@@ -228,8 +182,6 @@
     },
     {
         "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT",
         "PublicDescription": "ITLB misses that hit STLB. No page walk.",
@@ -238,8 +190,6 @@
     },
     {
         "BriefDescription": "Code misses that miss the  DTLB and hit the STLB (2M)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT_2M",
         "PublicDescription": "ITLB misses that hit STLB (2M).",
@@ -248,8 +198,6 @@
     },
     {
         "BriefDescription": "Core misses that miss the  DTLB and hit the STLB (4K)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT_4K",
         "PublicDescription": "ITLB misses that hit STLB (4K).",
@@ -258,8 +206,6 @@
     },
     {
         "BriefDescription": "Misses in all ITLB levels that cause completed page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
         "PublicDescription": "Completed page walks in ITLB of any page size.",
@@ -268,8 +214,6 @@
     },
     {
         "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
         "SampleAfterValue": "100003",
@@ -277,8 +221,6 @@
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
         "PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.",
@@ -287,8 +229,6 @@
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
         "PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.",
@@ -297,8 +237,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_DURATION",
         "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by ITLB misses.",
@@ -307,8 +245,6 @@
     },
     {
         "BriefDescription": "Number of DTLB page walker hits in the L1+FB",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.DTLB_L1",
         "PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.",
@@ -317,8 +253,6 @@
     },
     {
         "BriefDescription": "Number of DTLB page walker hits in the L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.DTLB_L2",
         "PublicDescription": "Number of DTLB page walker loads that hit in the L2.",
@@ -327,8 +261,6 @@
     },
     {
         "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "HSD25",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.DTLB_L3",
@@ -338,8 +270,6 @@
     },
     {
         "BriefDescription": "Number of DTLB page walker hits in Memory",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "HSD25",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
@@ -349,8 +279,6 @@
     },
     {
         "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1",
         "SampleAfterValue": "2000003",
@@ -358,8 +286,6 @@
     },
     {
         "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2",
         "SampleAfterValue": "2000003",
@@ -367,8 +293,6 @@
     },
     {
         "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3",
         "SampleAfterValue": "2000003",
@@ -376,8 +300,6 @@
     },
     {
         "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY",
         "SampleAfterValue": "2000003",
@@ -385,8 +307,6 @@
     },
     {
         "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1",
         "SampleAfterValue": "2000003",
@@ -394,8 +314,6 @@
     },
     {
         "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2",
         "SampleAfterValue": "2000003",
@@ -403,8 +321,6 @@
     },
     {
         "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3",
         "SampleAfterValue": "2000003",
@@ -412,8 +328,6 @@
     },
     {
         "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY",
         "SampleAfterValue": "2000003",
@@ -421,8 +335,6 @@
     },
     {
         "BriefDescription": "Number of ITLB page walker hits in the L1+FB",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.ITLB_L1",
         "PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.",
@@ -431,8 +343,6 @@
     },
     {
         "BriefDescription": "Number of ITLB page walker hits in the L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.ITLB_L2",
         "PublicDescription": "Number of ITLB page walker loads that hit in the L2.",
@@ -441,8 +351,6 @@
     },
     {
         "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "HSD25",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.ITLB_L3",
@@ -452,8 +360,6 @@
     },
     {
         "BriefDescription": "Number of ITLB page walker hits in Memory",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "HSD25",
         "EventCode": "0xBC",
         "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY",
@@ -463,8 +369,6 @@
     },
     {
         "BriefDescription": "DTLB flush attempts of the thread-specific entries",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.DTLB_THREAD",
         "PublicDescription": "DTLB flush attempts of the thread-specific entries.",
@@ -473,8 +377,6 @@
     },
     {
         "BriefDescription": "STLB flush attempts",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.STLB_ANY",
         "PublicDescription": "Count number of STLB flush attempts.",
-- 
GitLab


From f8473086e3440a787c874531cdefb9bbf101f0cc Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:54:52 -0800
Subject: [PATCH 576/875] perf vendor events intel: Refresh icelake metrics and
 events

Update the icelake metrics and events using the new tooling from:

  https://github.com/intel/perfmon

The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1".  The
events are unchanged but unused json values are removed. The
formatting changes increase consistency across the json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-6-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../pmu-events/arch/x86/icelake/cache.json    | 412 ------------------
 .../arch/x86/icelake/floating-point.json      |  28 --
 .../pmu-events/arch/x86/icelake/frontend.json | 144 ------
 .../arch/x86/icelake/icl-metrics.json         | 151 ++++---
 .../pmu-events/arch/x86/icelake/memory.json   | 171 --------
 .../pmu-events/arch/x86/icelake/other.json    | 132 ------
 .../pmu-events/arch/x86/icelake/pipeline.json | 349 +--------------
 .../arch/x86/icelake/uncore-other.json        |  10 +-
 .../arch/x86/icelake/virtual-memory.json      |  80 ----
 9 files changed, 89 insertions(+), 1388 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/icelake/cache.json b/tools/perf/pmu-events/arch/x86/icelake/cache.json
index 0f6b918484d50..bc6587391760c 100644
--- a/tools/perf/pmu-events/arch/x86/icelake/cache.json
+++ b/tools/perf/pmu-events/arch/x86/icelake/cache.json
@@ -1,1272 +1,860 @@
 [
     {
         "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x51",
         "EventName": "L1D.REPLACEMENT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.FB_FULL",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.L2_STALL",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of L1D misses that are outstanding",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles with L1D load Misses outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "L2 cache lines filling L2",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.ALL",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1f"
     },
     {
         "BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.NON_SILENT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.SILENT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xf2",
         "EventName": "L2_LINES_OUT.USELESS_HWPF",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "L2 code requests",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_CODE_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of L2 code requests.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xe4"
     },
     {
         "BriefDescription": "Demand Data Read requests",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xe1"
     },
     {
         "BriefDescription": "Demand requests that miss L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts demand requests that miss L2 cache.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x27"
     },
     {
         "BriefDescription": "Demand requests to L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts demand requests to L2 cache.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xe7"
     },
     {
         "BriefDescription": "RFO requests to L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_RFO",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xe2"
     },
     {
         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xc4"
     },
     {
         "BriefDescription": "L2 cache misses when fetching instructions",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts L2 cache misses when fetching instructions.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x24"
     },
     {
         "BriefDescription": "Demand Data Read requests that hit L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xc1"
     },
     {
         "BriefDescription": "Demand Data Read miss L2, no rejects",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x21"
     },
     {
         "BriefDescription": "RFO requests that hit L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xc2"
     },
     {
         "BriefDescription": "RFO requests that miss L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x22"
     },
     {
         "BriefDescription": "SW prefetch requests that hit L2 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.SWPF_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xc8"
     },
     {
         "BriefDescription": "SW prefetch requests that miss L2 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.SWPF_MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x28"
     },
     {
         "BriefDescription": "L2 writebacks that access L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L2_WB",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts L2 writebacks that access L2 cache.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Core-originated cacheable requests that missed L3  (Except hardware prefetches to the L3)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2e",
         "EventName": "LONGEST_LAT_CACHE.MISS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2.  It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x41"
     },
     {
         "BriefDescription": "Retired load instructions.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.ALL_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",
         "SampleAfterValue": "1000003",
         "UMask": "0x81"
     },
     {
         "BriefDescription": "Retired store instructions.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.ALL_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts all retired store instructions.",
         "SampleAfterValue": "1000003",
         "UMask": "0x82"
     },
     {
         "BriefDescription": "All retired memory instructions.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.ANY",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts all retired memory instructions - loads and stores.",
         "SampleAfterValue": "1000003",
         "UMask": "0x83"
     },
     {
         "BriefDescription": "Retired load instructions with locked access.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.LOCK_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with locked access.",
         "SampleAfterValue": "100007",
         "UMask": "0x21"
     },
     {
         "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",
         "SampleAfterValue": "100003",
         "UMask": "0x41"
     },
     {
         "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.SPLIT_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
         "SampleAfterValue": "100003",
         "UMask": "0x42"
     },
     {
         "BriefDescription": "Retired load instructions that miss the STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).",
         "SampleAfterValue": "100003",
         "UMask": "0x11"
     },
     {
         "BriefDescription": "Retired store instructions that miss the STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).",
         "SampleAfterValue": "100003",
         "UMask": "0x12"
     },
     {
         "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.",
         "SampleAfterValue": "20011",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.",
         "SampleAfterValue": "20011",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
         "SampleAfterValue": "20011",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.",
         "SampleAfterValue": "100003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.FB_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.",
         "SampleAfterValue": "100007",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L1_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.",
         "SampleAfterValue": "1000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired load instructions missed L1 cache as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L1_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
         "SampleAfterValue": "200003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L2_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Retired load instructions missed L2 cache as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L2_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
         "SampleAfterValue": "100021",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L3_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.",
         "SampleAfterValue": "100021",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Retired load instructions missed L3 cache as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L3_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.",
         "SampleAfterValue": "50021",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC03C0004",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0004",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0004",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0004",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0004",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_SENT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1E003C0004",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC03C0001",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0001",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0001",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0001",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0001",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_SENT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1E003C0001",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC03C0002",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0002",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0002",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0002",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0002",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_SENT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1E003C0002",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC03C0400",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0400",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0400",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was sent or not.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC03C0010",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0010",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0010",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0010",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0010",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was sent.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_SENT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1E003C0010",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L2_RFO.L3_HIT.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC03C0020",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0020",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0020",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0020",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0020",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_SENT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1E003C0020",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L3.L3_HIT.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC03C2380",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C8000",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C8000",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C8000",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_HIT.SNOOP_SENT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1E003C8000",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.STREAMING_WR.L3_HIT.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC03C0800",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Demand and prefetch data reads",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts memory transactions sent to the uncore.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts memory transactions sent to the uncore including requests initiated by the core, all L3 prefetches, reads resulting from page walks, and snoop responses.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Demand Data Read requests sent to uncore",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "For every cycle, increments by the number of outstanding data read requests pending.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "For every cycle, increments by the number of outstanding data read requests pending.  Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3.  Reads due to page walks resulting from any request type will also be counted.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Cycles where at least 1 outstanding data read request is pending.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Cycles where at least 1 outstanding data read request is pending.  Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3.  Reads due to page walks resulting from any request type will also be counted.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Cycles where at least 1 outstanding Demand RFO request is pending.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Cycles where at least 1 outstanding Demand RFO request is pending.   RFOs are initiated by a core as part of a data store operation.  Demand RFO requests include RFOs, locks, and ItoM transactions.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.   Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Store Read transactions pending for off-core. Highly correlated.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Cycles the queue waiting for offcore responses is full.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xf4",
         "EventName": "SQ_MISC.SQ_FULL",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the cycles for which the thread is active and the queue waiting for responses from the uncore cannot take any more entries.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of PREFETCHNTA instructions executed.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.NTA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of PREFETCHW instructions executed.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Number of PREFETCHT0 instructions executed.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.T0",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.T1_T2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/icelake/floating-point.json b/tools/perf/pmu-events/arch/x86/icelake/floating-point.json
index 1925388969bba..655342dadac66 100644
--- a/tools/perf/pmu-events/arch/x86/icelake/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/icelake/floating-point.json
@@ -1,100 +1,72 @@
 [
     {
         "BriefDescription": "Counts all microcode FP assists.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc1",
         "EventName": "ASSISTS.FP",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts all microcode Floating Point assists.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x2"
diff --git a/tools/perf/pmu-events/arch/x86/icelake/frontend.json b/tools/perf/pmu-events/arch/x86/icelake/frontend.json
index 739361d3f52f2..3e3d2b0021707 100644
--- a/tools/perf/pmu-events/arch/x86/icelake/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/icelake/frontend.json
@@ -1,497 +1,353 @@
 [
     {
         "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xe6",
         "EventName": "BACLEARS.ANY",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xab",
         "EventName": "DSB2MITE_SWITCHES.COUNT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xab",
         "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Retired Instructions who experienced DSB miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x1",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.DSB_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x11",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.ITLB_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x14",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.L1I_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x12",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.L2_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x13",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x500106",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x508006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x501006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x500206",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x510006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x100206",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x502006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x500406",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x520006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x504006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x500806",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.STLB_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x15",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "ICACHE_16B.IFDATA_STALL",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.",
         "SampleAfterValue": "500009",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "ICACHE_64B.IFTAG_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "ICACHE_64B.IFTAG_MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "ICACHE_64B.IFTAG_STALL",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_CYCLES_ANY",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Cycles DSB is delivering optimal number of Uops",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "5",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_CYCLES_OK",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_UOPS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Cycles MITE is delivering any Uop",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_CYCLES_ANY",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Cycles MITE is delivering optimal number of Uops",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "5",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_CYCLES_OK",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_UOPS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_CYCLES_ANY",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x30"
     },
     {
         "BriefDescription": "Number of switches from DSB or MITE to the MS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_SWITCHES",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x30"
     },
     {
         "BriefDescription": "Uops delivered to IDQ while MS is busy",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_UOPS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x30"
     },
     {
         "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x9c",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "5",
         "EventCode": "0x9c",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json b/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json
index 3b5ef09eb8efc..2ad36e00d2895 100644
--- a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json
@@ -41,7 +41,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage",
-        "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
+        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
         "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group",
         "MetricName": "tma_mispredicts_resteers",
         "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage.  Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
@@ -49,7 +49,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears",
-        "MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT))) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
+        "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
         "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group",
         "MetricName": "tma_clears_resteers",
         "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears.  Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
@@ -143,7 +143,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
-        "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
+        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
         "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
         "MetricName": "tma_branch_mispredicts",
         "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
@@ -159,7 +159,7 @@
     },
     {
         "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
-        "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + (5 * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=1\\,edge@) / SLOTS",
+        "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=1\\,edge@ / SLOTS",
         "MetricGroup": "TopdownL1;tma_L1_group",
         "MetricName": "tma_backend_bound",
         "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS",
@@ -167,7 +167,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
-        "MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * tma_backend_bound",
+        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound",
         "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
         "MetricName": "tma_memory_bound",
         "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@@ -213,7 +213,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
-        "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
+        "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
         "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
         "MetricName": "tma_lock_latency",
         "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS",
@@ -245,7 +245,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
-        "MetricExpr": "((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / ((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + L1D_PEND_MISS.FB_FULL_PERIODS)) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS)",
+        "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS)",
         "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_l2_bound",
         "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS",
@@ -261,7 +261,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
-        "MetricExpr": "((29 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM + (23.5 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+        "MetricExpr": "(29 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM + 23.5 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
         "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_contested_accesses",
         "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
@@ -269,7 +269,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
-        "MetricExpr": "(23.5 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+        "MetricExpr": "23.5 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
         "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_data_sharing",
         "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
@@ -277,7 +277,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
-        "MetricExpr": "(9 * Average_Frequency) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+        "MetricExpr": "9 * Average_Frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
         "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_l3_hit_latency",
         "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
@@ -293,7 +293,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
-        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS) - tma_l2_bound)",
+        "MetricExpr": "CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS - tma_l2_bound",
         "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_dram_bound",
         "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS",
@@ -325,7 +325,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
-        "MetricExpr": "((L2_RQSTS.RFO_HIT * 10 * (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES))) + (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
+        "MetricExpr": "(L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
         "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
         "MetricName": "tma_store_latency",
         "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
@@ -333,7 +333,7 @@
     },
     {
         "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
-        "MetricExpr": "(32.5 * Average_Frequency) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
+        "MetricExpr": "32.5 * Average_Frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
         "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
         "MetricName": "tma_false_sharing",
         "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line.  Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
@@ -395,7 +395,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
-        "MetricExpr": "(cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if (ARITH.DIVIDER_ACTIVE < (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY)) else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CLKS",
+        "MetricExpr": "((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CLKS)",
         "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
         "MetricName": "tma_ports_utilization",
         "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@@ -508,7 +508,7 @@
     },
     {
         "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
-        "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
+        "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS",
         "MetricGroup": "TopdownL1;tma_L1_group",
         "MetricName": "tma_retiring",
         "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided.  Sample with: UOPS_RETIRED.SLOTS",
@@ -625,7 +625,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
-        "MetricExpr": "((tma_retiring * SLOTS) / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
+        "MetricExpr": "tma_retiring * SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
         "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
         "MetricName": "tma_microcode_sequencer",
         "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
@@ -655,19 +655,19 @@
     },
     {
         "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) ",
+        "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))",
         "MetricGroup": "Mem;MemoryBW;Offcore",
         "MetricName": "Memory_Bandwidth"
     },
     {
         "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + (tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)))",
+        "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound))",
         "MetricGroup": "Mem;MemoryLat;Offcore",
         "MetricName": "Memory_Latency"
     },
     {
         "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) ",
+        "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))",
         "MetricGroup": "Mem;MemoryTLB;Offcore",
         "MetricName": "Memory_Data_TLBs"
     },
@@ -697,13 +697,13 @@
     },
     {
         "BriefDescription": "Uops Per Instruction",
-        "MetricExpr": "(tma_retiring * SLOTS) / INST_RETIRED.ANY",
+        "MetricExpr": "tma_retiring * SLOTS / INST_RETIRED.ANY",
         "MetricGroup": "Pipeline;Ret;Retire",
         "MetricName": "UPI"
     },
     {
         "BriefDescription": "Instruction per taken branch",
-        "MetricExpr": "(tma_retiring * SLOTS) / BR_INST_RETIRED.NEAR_TAKEN",
+        "MetricExpr": "tma_retiring * SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
         "MetricGroup": "Branches;Fed;FetchBW",
         "MetricName": "UpTB"
     },
@@ -727,7 +727,7 @@
     },
     {
         "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
-        "MetricExpr": "SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1",
+        "MetricExpr": "(SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)",
         "MetricGroup": "SMT;tma_L1_group",
         "MetricName": "Slots_Utilization"
     },
@@ -746,26 +746,26 @@
     },
     {
         "BriefDescription": "Floating Point Operations Per Cycle",
-        "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS",
         "MetricGroup": "Flops;Ret",
         "MetricName": "FLOPc"
     },
     {
         "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
-        "MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
         "MetricGroup": "Cor;Flops;HPC",
         "MetricName": "FP_Arith_Utilization",
         "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
     },
     {
         "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / ((UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
         "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
         "MetricName": "ILP"
     },
     {
         "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
-        "MetricExpr": "(1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0",
+        "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)",
         "MetricGroup": "Cor;SMT",
         "MetricName": "Core_Bound_Likely"
     },
@@ -813,13 +813,13 @@
     },
     {
         "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
         "MetricGroup": "Flops;InsType",
         "MetricName": "IpFLOP"
     },
     {
         "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))",
         "MetricGroup": "Flops;InsType",
         "MetricName": "IpArith",
         "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
@@ -873,7 +873,7 @@
     },
     {
         "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
-        "MetricExpr": "(tma_retiring * SLOTS) / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
+        "MetricExpr": "tma_retiring * SLOTS / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
         "MetricGroup": "Pipeline;Ret",
         "MetricName": "Retire"
     },
@@ -927,7 +927,7 @@
     },
     {
         "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
-        "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
+        "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
         "MetricGroup": "Bad;BrMispredicts",
         "MetricName": "Branch_Misprediction_Cost"
     },
@@ -975,49 +975,49 @@
     },
     {
         "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L1MPKI"
     },
     {
         "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L1MPKI_Load"
     },
     {
         "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
         "MetricGroup": "Backend;CacheMisses;Mem",
         "MetricName": "L2MPKI"
     },
     {
         "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
-        "MetricExpr": "1000 * ((OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD) + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS) / Instructions",
+        "MetricExpr": "1e3 * (OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS) / Instructions",
         "MetricGroup": "CacheMisses;Mem;Offcore",
         "MetricName": "L2MPKI_All"
     },
     {
         "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L2MPKI_Load"
     },
     {
         "BriefDescription": "L2 cache hits per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L2HPKI_Load"
     },
     {
         "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L3MPKI"
     },
     {
         "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "FB_HPKI"
     },
@@ -1030,25 +1030,25 @@
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
-        "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
+        "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L1D_Cache_Fill_BW"
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
-        "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
+        "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L2_Cache_Fill_BW"
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
+        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L3_Cache_Fill_BW"
     },
     {
         "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time",
+        "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW;Offcore",
         "MetricName": "L3_Cache_Access_BW"
     },
@@ -1078,19 +1078,19 @@
     },
     {
         "BriefDescription": "Average CPU Utilization",
-        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
+        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
         "MetricGroup": "HPC;Summary",
         "MetricName": "CPU_Utilization"
     },
     {
         "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
-        "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
+        "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
         "MetricGroup": "Power;Summary",
         "MetricName": "Average_Frequency"
     },
     {
         "BriefDescription": "Giga Floating Point Operations Per Second",
-        "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1000000000) / duration_time",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time",
         "MetricGroup": "Cor;Flops;HPC",
         "MetricName": "GFLOPs",
         "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
@@ -1124,7 +1124,7 @@
     },
     {
         "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
-        "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0",
+        "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)",
         "MetricGroup": "SMT",
         "MetricName": "SMT_2T_Utilization"
     },
@@ -1142,68 +1142,89 @@
     },
     {
         "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
-        "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1000000 / duration_time / 1000",
+        "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3",
         "MetricGroup": "HPC;Mem;MemoryBW;SoC",
         "MetricName": "DRAM_BW_Use"
     },
+    {
+        "BriefDescription": "Socket actual clocks when any core is active on that socket",
+        "MetricExpr": "UNC_CLOCK.SOCKET",
+        "MetricGroup": "SoC",
+        "MetricName": "Socket_CLKS"
+    },
     {
         "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
         "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
         "MetricGroup": "Branches;OS",
         "MetricName": "IpFarBranch"
     },
+    {
+        "BriefDescription": "Uncore frequency per die [GHZ]",
+        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+        "MetricGroup": "SoC",
+        "MetricName": "UNCORE_FREQ"
+    },
     {
         "BriefDescription": "C6 residency percent per core",
-        "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C6_Core_Residency"
+        "MetricName": "C6_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C7 residency percent per core",
-        "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C7_Core_Residency"
+        "MetricName": "C7_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C2 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C2_Pkg_Residency"
+        "MetricName": "C2_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C3 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C3_Pkg_Residency"
+        "MetricName": "C3_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C6 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C6_Pkg_Residency"
+        "MetricName": "C6_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C7 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C7_Pkg_Residency"
+        "MetricName": "C7_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C8 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c8\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C8_Pkg_Residency"
+        "MetricName": "C8_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C9 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c9\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C9_Pkg_Residency"
+        "MetricName": "C9_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C10 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c10\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C10_Pkg_Residency"
+        "MetricName": "C10_Pkg_Residency",
+        "ScaleUnit": "100%"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/icelake/memory.json b/tools/perf/pmu-events/arch/x86/icelake/memory.json
index a6f43cbc2d0a7..e8d2ec1c029bf 100644
--- a/tools/perf/pmu-events/arch/x86/icelake/memory.json
+++ b/tools/perf/pmu-events/arch/x86/icelake/memory.json
@@ -1,565 +1,394 @@
 [
     {
         "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "6",
         "EventCode": "0xa3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x6"
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times HLE abort was triggered.",
         "SampleAfterValue": "100003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_EVENTS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
         "SampleAfterValue": "100003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_MEM",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
         "SampleAfterValue": "100003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
         "SampleAfterValue": "100003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Number of times an HLE execution successfully committed",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.COMMIT",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times HLE commit succeeded.",
         "SampleAfterValue": "100003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of times an HLE execution started.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc8",
         "EventName": "HLE_RETIRED.START",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times we entered an HLE region. Does not count nested transactions.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of machine clears due to memory ordering conflicts.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x80",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "1009",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x10",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "20011",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x100",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "503",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x20",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x4",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "100003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x200",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "101",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x40",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "2003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x8",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "50021",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that was not supplied by the L3 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFFC00004",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that was not supplied by the L3 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFFC00001",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFFC00002",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that was not supplied by the L3 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFFC00400",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2)  that was not supplied by the L3 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFFC00010",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that was not supplied by the L3 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L2_RFO.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFFC00020",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that was not supplied by the L3 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFFC08000",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores that was not supplied by the L3 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.STREAMING_WR.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFFC00800",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data read requests that miss the L3 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb0",
         "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending.  Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times RTM abort was triggered.",
         "SampleAfterValue": "100003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_EVENTS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
         "SampleAfterValue": "100003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MEM",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
         "SampleAfterValue": "100003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
         "SampleAfterValue": "100003",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
         "SampleAfterValue": "100003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Number of times an RTM execution successfully committed",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.COMMIT",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times RTM commit succeeded.",
         "SampleAfterValue": "100003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of times an RTM execution started.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.START",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC3",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CAPACITY_READ",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CONFLICT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times we could not allocate Lock Buffer.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x40"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/icelake/other.json b/tools/perf/pmu-events/arch/x86/icelake/other.json
index 3055710595c46..cfb590632918f 100644
--- a/tools/perf/pmu-events/arch/x86/icelake/other.json
+++ b/tools/perf/pmu-events/arch/x86/icelake/other.json
@@ -1,374 +1,242 @@
 [
     {
         "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x7"
     },
     {
         "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x18"
     },
     {
         "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture).  This includes high current AVX 512-bit instructions.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10004",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000004",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000004",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that have any type of response.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10001",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that DRAM supplied the request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000001",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that DRAM supplied the request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000001",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10002",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000002",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000002",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10400",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000400",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000400",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2)  that have any type of response.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10010",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2)  that DRAM supplied the request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L2_DATA_RD.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000010",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2)  that DRAM supplied the request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000010",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that have any type of response.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10020",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L2_RFO.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000020",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000020",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x18000",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184008000",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184008000",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores that have any type of response.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10800",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores that DRAM supplied the request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.STREAMING_WR.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000800",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores that DRAM supplied the request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.STREAMING_WR.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000800",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json b/tools/perf/pmu-events/arch/x86/icelake/pipeline.json
index c74a7369cff35..3b31a842a0b14 100644
--- a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/icelake/pipeline.json
@@ -1,703 +1,490 @@
 [
     {
         "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x14",
         "EventName": "ARITH.DIVIDER_ACTIVE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x9"
     },
     {
         "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc1",
         "EventName": "ASSISTS.ANY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x7"
     },
     {
         "BriefDescription": "All branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts all branch instructions retired.",
         "SampleAfterValue": "400009"
     },
     {
         "BriefDescription": "Conditional branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.COND",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts conditional branch instructions retired.",
         "SampleAfterValue": "400009",
         "UMask": "0x11"
     },
     {
         "BriefDescription": "Not taken branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.COND_NTAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts not taken branch instructions retired.",
         "SampleAfterValue": "400009",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Taken conditional branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.COND_TAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts taken conditional branch instructions retired.",
         "SampleAfterValue": "400009",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Far branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.FAR_BRANCH",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts far branch instructions retired.",
         "SampleAfterValue": "100007",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Indirect near branch instructions retired (excluding returns)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.INDIRECT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.",
         "SampleAfterValue": "100003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Direct and indirect near call instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts both direct and indirect near call instructions retired.",
         "SampleAfterValue": "100007",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Return instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.NEAR_RETURN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts return instructions retired.",
         "SampleAfterValue": "100007",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Taken branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts taken branch instructions retired.",
         "SampleAfterValue": "400009",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "All mispredicted branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch.  When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
         "SampleAfterValue": "50021"
     },
     {
         "BriefDescription": "Mispredicted conditional branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.COND",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts mispredicted conditional branch instructions retired.",
         "SampleAfterValue": "50021",
         "UMask": "0x11"
     },
     {
         "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.COND_NTAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.",
         "SampleAfterValue": "50021",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "number of branch instructions retired that were mispredicted and taken.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.COND_TAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts taken conditional mispredicted branch instructions retired.",
         "SampleAfterValue": "50021",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.INDIRECT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
         "SampleAfterValue": "50021",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Mispredicted indirect CALL instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.INDIRECT_CALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.",
         "SampleAfterValue": "50021",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.",
         "SampleAfterValue": "50021",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xec",
         "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0.  A hyperthread becomes inactive when it executes the HLT or MWAIT instructions.  If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.",
         "SampleAfterValue": "25003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Reference cycles when the core is not in halt state.",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 2",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
-        "PEBScounters": "34",
         "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x3"
     },
     {
         "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts core crystal clock cycles when the thread is unhalted.",
         "SampleAfterValue": "25003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Core cycles when the thread is not in halt state",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD",
-        "PEBScounters": "33",
         "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Thread cycles when thread is not in halt state",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
-        "SampleAfterValue": "2000003",
-        "Speculative": "1"
+        "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "8",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "16",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "12",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0xc"
     },
     {
         "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "5",
         "EventCode": "0xa3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x5"
     },
     {
         "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "20",
         "EventCode": "0xa3",
         "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x14"
     },
     {
         "BriefDescription": "Total execution stalls.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xa3",
         "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa6",
         "EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa6",
         "EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa6",
         "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa6",
         "EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xA6",
         "EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.LCP",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
         "SampleAfterValue": "500009",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Instruction decoders utilized in a cycle",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x55",
         "EventName": "INST_DECODED.DECODERS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 0",
         "EventName": "INST_RETIRED.ANY",
         "PEBS": "1",
-        "PEBScounters": "32",
         "PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of instructions retired. General Counter - architectural event",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc0",
         "EventName": "INST_RETIRED.ANY_P",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Number of all retired NOP instructions.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc0",
         "EventName": "INST_RETIRED.NOP",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 0",
         "EventName": "INST_RETIRED.PREC_DIST",
         "PEBS": "1",
-        "PEBScounters": "32",
         "PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles without actually retired instructions.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xc0",
         "EventName": "INST_RETIRED.STALL_CYCLES",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "This event counts cycles without actually retired instructions.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.ALL_RECOVERY_CYCLES",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x3"
     },
     {
         "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0d",
         "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
         "SampleAfterValue": "500009",
-        "Speculative": "1",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
         "SampleAfterValue": "500009",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "TMA slots where uops got dropped",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0d",
         "EventName": "INT_MISC.UOP_DROPPING",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.NO_SR",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.STORE_FORWARD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "False dependencies due to partial compare on address.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x07",
         "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times a load got blocked due to false dependencies due to partial compare on address.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4c",
         "EventName": "LOAD_HIT_PREFETCH.SWPF",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_ACTIVE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "5",
         "EventCode": "0xa8",
         "EventName": "LSD.CYCLES_OK",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of Uops delivered by the LSD.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xa8",
         "EventName": "LSD.UOPS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of machine clears (nukes) of any type.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.COUNT",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of machine clears (nukes) of any type.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Self-modifying code (SMC) detected.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.SMC",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Increments whenever there is an update to the LBR array.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xcc",
         "EventName": "MISC_RETIRED.LBR_INSERTS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR to be enabled properly.",
         "SampleAfterValue": "100003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xcc",
         "EventName": "MISC_RETIRED.PAUSE_INST",
         "PublicDescription": "Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.",
@@ -706,422 +493,288 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa2",
         "EventName": "RESOURCE_STALLS.SB",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa2",
         "EventName": "RESOURCE_STALLS.SCOREBOARD",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5e",
         "EventName": "RS_EVENTS.EMPTY_CYCLES",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5E",
         "EventName": "RS_EVENTS.EMPTY_END",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa4",
         "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's  slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
         "SampleAfterValue": "10000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa4",
         "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.",
         "SampleAfterValue": "10000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 3",
         "EventName": "TOPDOWN.SLOTS",
-        "PEBScounters": "35",
         "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
         "SampleAfterValue": "10000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa4",
         "EventName": "TOPDOWN.SLOTS_P",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
         "SampleAfterValue": "10000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x56",
         "EventName": "UOPS_DECODED.DEC0",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Uops exclusively fetched by decoder 0",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of uops executed on port 0",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa1",
         "EventName": "UOPS_DISPATCHED.PORT_0",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of uops executed on port 1",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa1",
         "EventName": "UOPS_DISPATCHED.PORT_1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of uops executed on port 2 and 3",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa1",
         "EventName": "UOPS_DISPATCHED.PORT_2_3",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of uops executed on port 4 and 9",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa1",
         "EventName": "UOPS_DISPATCHED.PORT_4_9",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Number of uops executed on port 5",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa1",
         "EventName": "UOPS_DISPATCHED.PORT_5",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Number of uops executed on port 6",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa1",
         "EventName": "UOPS_DISPATCHED.PORT_6",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Number of uops executed on port 7 and 8",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa1",
         "EventName": "UOPS_DISPATCHED.PORT_7_8",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Number of uops executed on the core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of uops executed from any thread.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_3",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_4",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.STALL_CYCLES",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.THREAD",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of x87 uops dispatched.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.X87",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of x87 uops executed.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Uops that RAT issues to RS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0e",
         "EventName": "UOPS_ISSUED.ANY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles when RAT does not issue Uops to RS for the thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.STALL_CYCLES",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0e",
         "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Retirement slots used.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.SLOTS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the retirement slots used each cycle.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles without actually retired uops.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.STALL_CYCLES",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "This event counts cycles without actually retired uops.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles with less than 10 actually retired uops.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "10",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of cycles using always true condition (uops_ret &amp;lt; 16) applied to non PEBS uops retired event.",
         "SampleAfterValue": "1000003",
         "UMask": "0x2"
diff --git a/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json b/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json
index e007b976547db..f7aff8818f469 100644
--- a/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json
@@ -1,31 +1,25 @@
 [
     {
         "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop,  etc.",
-        "Counter": "1",
         "EventCode": "0x84",
         "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
         "PerPkg": "1",
-        "PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop,  etc.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
-        "Counter": "1",
         "EventCode": "0x81",
         "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
         "PerPkg": "1",
-        "PublicDescription": "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "UNC_CLOCK.SOCKET",
-        "Counter": "FIXED",
         "EventCode": "0xff",
         "EventName": "UNC_CLOCK.SOCKET",
         "PerPkg": "1",
-        "PublicDescription": "UNC_CLOCK.SOCKET",
         "Unit": "CLOCK"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json b/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json
index 58809e16bf982..b28f62ce1f398 100644
--- a/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json
@@ -1,245 +1,165 @@
 [
     {
         "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0xe"
     },
     {
         "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0xe"
     },
     {
         "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_ACTIVE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0xe"
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_PENDING",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "DTLB flush attempts of the thread-specific entries",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.DTLB_THREAD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
         "SampleAfterValue": "100007",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "STLB flush attempts",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.STLB_ANY",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
         "SampleAfterValue": "100007",
-        "Speculative": "1",
         "UMask": "0x20"
     }
 ]
-- 
GitLab


From f8e23ad10520876fa9165425235867788383dbbc Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:54:53 -0800
Subject: [PATCH 577/875] perf vendor events intel: Refresh icelakex metrics
 and events

Update the icelakex metrics and events using the new tooling from:

  https://github.com/intel/perfmon

The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
order of metrics varies as TMA metrics are first converted and then
removed if perfmon versions are found. The events are updated to 1.17,
in particular uncore, with fixes to uncore events and improved
descriptions. The formatting changes increase consistency across the
json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-7-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../pmu-events/arch/x86/icelakex/cache.json   |   316 +-
 .../arch/x86/icelakex/floating-point.json     |    28 -
 .../arch/x86/icelakex/frontend.json           |   140 -
 .../arch/x86/icelakex/icx-metrics.json        |  2192 +-
 .../pmu-events/arch/x86/icelakex/memory.json  |   139 +-
 .../pmu-events/arch/x86/icelakex/other.json   |   117 -
 .../arch/x86/icelakex/pipeline.json           |   344 +-
 .../arch/x86/icelakex/uncore-memory.json      |  1878 +-
 .../arch/x86/icelakex/uncore-other.json       | 45144 +++++++---------
 .../arch/x86/icelakex/uncore-power.json       |   115 +-
 .../arch/x86/icelakex/virtual-memory.json     |    88 -
 tools/perf/pmu-events/arch/x86/mapfile.csv    |     2 +-
 12 files changed, 22074 insertions(+), 28429 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/icelakex/cache.json b/tools/perf/pmu-events/arch/x86/icelakex/cache.json
index e4035b3e55caa..d6463c8d94625 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/cache.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/cache.json
@@ -1,1172 +1,868 @@
 [
     {
         "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x51",
         "EventName": "L1D.REPLACEMENT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.FB_FULL",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.L2_STALL",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of L1D misses that are outstanding",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles with L1D load Misses outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "L2 cache lines filling L2",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.ALL",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1f"
     },
     {
         "BriefDescription": "Cache lines that are evicted by L2 cache when triggered by an L2 cache fill.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.NON_SILENT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of lines that are evicted by the L2 cache due to L2 cache fills.  Evicted lines are delivered to the L3, which may or may not cache them, according to system load and priorities.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.SILENT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "L2 code requests",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_CODE_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of L2 code requests.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xe4"
     },
     {
         "BriefDescription": "Demand Data Read requests",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xe1"
     },
     {
         "BriefDescription": "Demand requests that miss L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts demand requests that miss L2 cache.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x27"
     },
     {
         "BriefDescription": "RFO requests to L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_RFO",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xe2"
     },
     {
         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xc4"
     },
     {
         "BriefDescription": "L2 cache misses when fetching instructions",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts L2 cache misses when fetching instructions.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x24"
     },
     {
         "BriefDescription": "Demand Data Read requests that hit L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xc1"
     },
     {
         "BriefDescription": "Demand Data Read miss L2, no rejects",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x21"
     },
     {
         "BriefDescription": "RFO requests that hit L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xc2"
     },
     {
         "BriefDescription": "RFO requests that miss L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x22"
     },
     {
         "BriefDescription": "SW prefetch requests that hit L2 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.SWPF_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xc8"
     },
     {
         "BriefDescription": "SW prefetch requests that miss L2 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.SWPF_MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x28"
     },
     {
         "BriefDescription": "L2 writebacks that access L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L2_WB",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts L2 writebacks that access L2 cache.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Core-originated cacheable requests that missed L3  (Except hardware prefetches to the L3)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2e",
         "EventName": "LONGEST_LAT_CACHE.MISS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2.  It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x41"
     },
     {
         "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2e",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2.  It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4f"
     },
     {
         "BriefDescription": "Retired load instructions.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.ALL_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",
         "SampleAfterValue": "1000003",
         "UMask": "0x81"
     },
     {
         "BriefDescription": "Retired store instructions.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.ALL_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts all retired store instructions.",
         "SampleAfterValue": "1000003",
         "UMask": "0x82"
     },
     {
         "BriefDescription": "All retired memory instructions.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.ANY",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts all retired memory instructions - loads and stores.",
         "SampleAfterValue": "1000003",
         "UMask": "0x83"
     },
     {
         "BriefDescription": "Retired load instructions with locked access.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.LOCK_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with locked access.",
         "SampleAfterValue": "100007",
         "UMask": "0x21"
     },
     {
         "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",
         "SampleAfterValue": "100003",
         "UMask": "0x41"
     },
     {
         "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.SPLIT_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
         "SampleAfterValue": "100003",
         "UMask": "0x42"
     },
     {
         "BriefDescription": "Retired load instructions that miss the STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).",
         "SampleAfterValue": "100003",
         "UMask": "0x11"
     },
     {
         "BriefDescription": "Retired store instructions that miss the STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).",
         "SampleAfterValue": "100003",
         "UMask": "0x12"
     },
     {
         "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.",
         "SampleAfterValue": "20011",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
+        "Deprecated": "1",
         "EventCode": "0xd2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "20011",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
+        "Deprecated": "1",
         "EventCode": "0xd2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "20011",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
         "SampleAfterValue": "20011",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.",
         "SampleAfterValue": "100003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.",
         "SampleAfterValue": "20011",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd3",
         "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Retired load instructions which data sources missed L3 but serviced from local DRAM.",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from remote dram",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd3",
         "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100007",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd3",
         "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Retired load instructions whose data sources was forwarded from a remote cache.",
         "SampleAfterValue": "100007",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Retired load instructions whose data sources was remote HITM",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd3",
         "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Retired load instructions whose data sources was remote HITM.",
         "SampleAfterValue": "100007",
         "UMask": "0x4"
     },
     {
-        "BriefDescription": "Retired load instructions with remote Intel Optane DC persistent memory as the data source where the data request missed all caches.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.",
         "Data_LA": "1",
         "EventCode": "0xd3",
         "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
-        "PublicDescription": "Counts retired load instructions with remote Intel Optane DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).",
+        "PublicDescription": "Counts retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).",
         "SampleAfterValue": "100007",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Retired instructions with at least 1 uncacheable load or Bus Lock.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd4",
         "EventName": "MEM_LOAD_MISC_RETIRED.UC",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock).",
         "SampleAfterValue": "100007",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.FB_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.",
         "SampleAfterValue": "100007",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L1_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.",
         "SampleAfterValue": "1000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired load instructions missed L1 cache as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L1_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
         "SampleAfterValue": "200003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L2_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Retired load instructions missed L2 cache as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L2_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
         "SampleAfterValue": "100021",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L3_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.",
         "SampleAfterValue": "100021",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Retired load instructions missed L3 cache as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L3_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.",
         "SampleAfterValue": "50021",
         "UMask": "0x20"
     },
     {
-        "BriefDescription": "Retired load instructions with local Intel Optane DC persistent memory as the data source where the data request missed all caches.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.LOCAL_PMM",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
-        "PublicDescription": "Counts retired load instructions with local Intel Optane DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).",
+        "PublicDescription": "Counts retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).",
         "SampleAfterValue": "100003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1008000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x808000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1030000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x830000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1008000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x808000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1008000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x808000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L3.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80082380",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PREFETCHES.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C27F0",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F003C0477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1830000477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1030000477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x830000477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1008000477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x808000477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.STREAMING_WR.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080800",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Demand and prefetch data reads",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts memory transactions sent to the uncore.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts memory transactions sent to the uncore including requests initiated by the core, all L3 prefetches, reads resulting from page walks, and snoop responses.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Counts cacheable and non-cacheable code reads to the core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts both cacheable and non-cacheable code reads to the core.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Demand Data Read requests sent to uncore",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "For every cycle, increments by the number of outstanding data read requests pending.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "For every cycle, increments by the number of outstanding data read requests pending.  Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3.  Reads due to page walks resulting from any request type will also be counted.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Cycles where at least 1 outstanding data read request is pending.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Cycles where at least 1 outstanding data read request is pending.  Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3.  Reads due to page walks resulting from any request type will also be counted.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Cycles with outstanding code read requests pending.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Cycles with outstanding code read requests pending.  Code Read requests include both cacheable and non-cacheable Code Reads.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles where at least 1 outstanding Demand RFO request is pending.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Cycles where at least 1 outstanding Demand RFO request is pending.   RFOs are initiated by a core as part of a data store operation.  Demand RFO requests include RFOs, locks, and ItoM transactions.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "For every cycle, increments by the number of outstanding code read requests pending.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "For every cycle, increments by the number of outstanding code read requests pending.  Code Read requests include both cacheable and non-cacheable Code Reads.   Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.   Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles the queue waiting for offcore responses is full.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xf4",
         "EventName": "SQ_MISC.SQ_FULL",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the cycles for which the thread is active and the queue waiting for responses from the uncore cannot take any more entries.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of PREFETCHNTA instructions executed.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.NTA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of PREFETCHW instructions executed.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Number of PREFETCHT0 instructions executed.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.T0",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.T1_T2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json b/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json
index 1925388969bba..655342dadac66 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json
@@ -1,100 +1,72 @@
 [
     {
         "BriefDescription": "Counts all microcode FP assists.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc1",
         "EventName": "ASSISTS.FP",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts all microcode Floating Point assists.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x2"
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/frontend.json b/tools/perf/pmu-events/arch/x86/icelakex/frontend.json
index eb27d9d9c8bed..71498044f1cbf 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/frontend.json
@@ -1,484 +1,344 @@
 [
     {
         "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xe6",
         "EventName": "BACLEARS.ANY",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xab",
         "EventName": "DSB2MITE_SWITCHES.COUNT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xab",
         "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Retired Instructions who experienced DSB miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x1",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.DSB_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x11",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.ITLB_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x14",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.L1I_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x12",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.L2_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x13",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x500106",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x508006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x501006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x500206",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x510006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x100206",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x502006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x500406",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x520006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x504006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x500806",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.STLB_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x15",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "ICACHE_16B.IFDATA_STALL",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.",
         "SampleAfterValue": "500009",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "ICACHE_64B.IFTAG_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "ICACHE_64B.IFTAG_MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "ICACHE_64B.IFTAG_STALL",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_CYCLES_ANY",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Cycles DSB is delivering optimal number of Uops",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "5",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_CYCLES_OK",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_UOPS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Cycles MITE is delivering any Uop",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_CYCLES_ANY",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Cycles MITE is delivering optimal number of Uops",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "5",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_CYCLES_OK",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_UOPS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of switches from DSB or MITE to the MS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_SWITCHES",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x30"
     },
     {
         "BriefDescription": "Uops delivered to IDQ while MS is busy",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_UOPS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x30"
     },
     {
         "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x9c",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "5",
         "EventCode": "0x9c",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json
index b52afc34a1694..22b2a97d0ff8a 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json
@@ -1,1563 +1,1529 @@
 [
     {
-        "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
-        "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / SLOTS",
-        "MetricGroup": "PGO;TopdownL1;tma_L1_group",
-        "MetricName": "tma_frontend_bound",
-        "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
+        "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
+        "MetricGroup": "Bad;BadSpec;BrMispredicts",
+        "MetricName": "Mispredictions"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
-        "MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / SLOTS",
-        "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
-        "MetricName": "tma_fetch_latency",
-        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
+        "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))",
+        "MetricGroup": "Mem;MemoryBW;Offcore",
+        "MetricName": "Memory_Bandwidth"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses",
-        "MetricExpr": "ICACHE_16B.IFDATA_STALL / CLKS",
-        "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_icache_misses",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
+        "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound))",
+        "MetricGroup": "Mem;MemoryLat;Offcore",
+        "MetricName": "Memory_Latency"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses",
-        "MetricExpr": "ICACHE_64B.IFTAG_STALL / CLKS",
-        "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_itlb_misses",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
+        "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))",
+        "MetricGroup": "Mem;MemoryTLB;Offcore",
+        "MetricName": "Memory_Data_TLBs"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
-        "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CLKS + tma_unknown_branches",
-        "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_branch_resteers",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)",
+        "MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)",
+        "MetricGroup": "Ret",
+        "MetricName": "Branching_Overhead"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage",
-        "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
-        "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group",
-        "MetricName": "tma_mispredicts_resteers",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage.  Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)",
+        "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)",
+        "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB",
+        "MetricName": "Big_Code"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears",
-        "MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT))) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
-        "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group",
-        "MetricName": "tma_clears_resteers",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears.  Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks",
+        "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code",
+        "MetricGroup": "Fed;FetchBW;Frontend",
+        "MetricName": "Instruction_Fetch_BW"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
-        "MetricExpr": "10 * BACLEARS.ANY / CLKS",
-        "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_branch_resteers_group",
-        "MetricName": "tma_unknown_branches",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: BACLEARS.ANY",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
+        "MetricExpr": "INST_RETIRED.ANY / CLKS",
+        "MetricGroup": "Ret;Summary",
+        "MetricName": "IPC"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
-        "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS",
-        "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_dsb_switches",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Uops Per Instruction",
+        "MetricExpr": "tma_retiring * SLOTS / INST_RETIRED.ANY",
+        "MetricGroup": "Pipeline;Ret;Retire",
+        "MetricName": "UPI"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
-        "MetricExpr": "ILD_STALL.LCP / CLKS",
-        "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_lcp",
-        "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instruction per taken branch",
+        "MetricExpr": "tma_retiring * SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
+        "MetricGroup": "Branches;Fed;FetchBW",
+        "MetricName": "UpTB"
     },
     {
-        "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
-        "MetricExpr": "3 * IDQ.MS_SWITCHES / CLKS",
-        "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_ms_switches",
-        "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
+        "MetricExpr": "1 / IPC",
+        "MetricGroup": "Mem;Pipeline",
+        "MetricName": "CPI"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
-        "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
-        "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
-        "MetricName": "tma_fetch_bandwidth",
-        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues.  For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "Pipeline",
+        "MetricName": "CLKS"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
-        "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / CORE_CLKS / 2",
-        "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
-        "MetricName": "tma_mite",
-        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
+        "MetricExpr": "TOPDOWN.SLOTS",
+        "MetricGroup": "tma_L1_group",
+        "MetricName": "SLOTS"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder",
-        "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) / CORE_CLKS",
-        "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_mite_group",
-        "MetricName": "tma_decoder0_alone",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
+        "MetricExpr": "(SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)",
+        "MetricGroup": "SMT;tma_L1_group",
+        "MetricName": "Slots_Utilization"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles where (only) 4 uops were delivered by the MITE pipeline",
-        "MetricExpr": "(cpu@IDQ.MITE_UOPS\\,cmask\\=4@ - cpu@IDQ.MITE_UOPS\\,cmask\\=5@) / CLKS",
-        "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_mite_group",
-        "MetricName": "tma_mite_4wide",
-        "ScaleUnit": "100%"
+        "BriefDescription": "The ratio of Executed- by Issued-Uops",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
+        "MetricGroup": "Cor;Pipeline",
+        "MetricName": "Execute_per_Issue",
+        "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
-        "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / CORE_CLKS / 2",
-        "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
-        "MetricName": "tma_dsb",
-        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline.  For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
+        "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
+        "MetricGroup": "Ret;SMT;tma_L1_group",
+        "MetricName": "CoreIPC"
     },
     {
-        "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
-        "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)",
-        "MetricGroup": "TopdownL1;tma_L1_group",
-        "MetricName": "tma_bad_speculation",
-        "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Floating Point Operations Per Cycle",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS",
+        "MetricGroup": "Flops;Ret",
+        "MetricName": "FLOPc"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
-        "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
-        "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
-        "MetricName": "tma_branch_mispredicts",
-        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
+        "MetricGroup": "Cor;Flops;HPC",
+        "MetricName": "FP_Arith_Utilization",
+        "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
-        "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)",
-        "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group",
-        "MetricName": "tma_machine_clears",
-        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears.  These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
+        "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
+        "MetricName": "ILP"
     },
     {
-        "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
-        "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + (5 * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=1\\,edge@) / SLOTS",
-        "MetricGroup": "TopdownL1;tma_L1_group",
-        "MetricName": "tma_backend_bound",
-        "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
+        "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)",
+        "MetricGroup": "Cor;SMT",
+        "MetricName": "Core_Bound_Likely"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
-        "MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * tma_backend_bound",
-        "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
-        "MetricName": "tma_memory_bound",
-        "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
+        "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED",
+        "MetricGroup": "SMT",
+        "MetricName": "CORE_CLKS"
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
-        "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CLKS, 0)",
-        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_l1_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache.  The L1 data cache typically has the shortest latency.  However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS",
+        "MetricGroup": "InsType",
+        "MetricName": "IpLoad"
     },
     {
-        "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
-        "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / CLKS",
-        "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_dtlb_load",
-        "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES",
+        "MetricGroup": "InsType",
+        "MetricName": "IpStore"
     },
     {
-        "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
-        "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
-        "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group",
-        "MetricName": "tma_load_stlb_hit",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Branches;Fed;InsType",
+        "MetricName": "IpBranch"
     },
     {
-        "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk",
-        "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CLKS",
-        "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group",
-        "MetricName": "tma_load_stlb_miss",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
+        "MetricGroup": "Branches;Fed;PGO",
+        "MetricName": "IpCall"
     },
     {
-        "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
-        "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS",
-        "MetricGroup": "TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_store_fwd_blk",
-        "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instruction per taken branch",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
+        "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
+        "MetricName": "IpTB"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
-        "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
-        "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_lock_latency",
-        "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Branch instructions per taken branch. ",
+        "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
+        "MetricGroup": "Branches;Fed;PGO",
+        "MetricName": "BpTkBranch"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary",
-        "MetricExpr": "Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS",
-        "MetricGroup": "TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_split_loads",
-        "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary.  Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
+        "MetricGroup": "Flops;InsType",
+        "MetricName": "IpFLOP"
     },
     {
-        "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
-        "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CLKS",
-        "MetricGroup": "TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_4k_aliasing",
-        "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))",
+        "MetricGroup": "Flops;InsType",
+        "MetricName": "IpArith",
+        "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
     },
     {
-        "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
-        "MetricExpr": "L1D_PEND_MISS.FB_FULL / CLKS",
-        "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_fb_full",
-        "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
+        "MetricGroup": "Flops;FpScalar;InsType",
+        "MetricName": "IpArith_Scalar_SP",
+        "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
-        "MetricExpr": "((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / ((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + L1D_PEND_MISS.FB_FULL_PERIODS)) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS)",
-        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_l2_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
+        "MetricGroup": "Flops;FpScalar;InsType",
+        "MetricName": "IpArith_Scalar_DP",
+        "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
-        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / CLKS",
-        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_l3_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)",
+        "MetricGroup": "Flops;FpVector;InsType",
+        "MetricName": "IpArith_AVX128",
+        "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
-        "MetricExpr": "((44 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + (43.5 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_contested_accesses",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
+        "MetricGroup": "Flops;FpVector;InsType",
+        "MetricName": "IpArith_AVX256",
+        "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
-        "MetricExpr": "(43.5 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD)))) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_data_sharing",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
+        "MetricGroup": "Flops;FpVector;InsType",
+        "MetricName": "IpArith_AVX512",
+        "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
-        "MetricExpr": "(19 * Average_Frequency) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_l3_hit_latency",
-        "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@",
+        "MetricGroup": "Prefetches",
+        "MetricName": "IpSWPF"
     },
     {
-        "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
-        "MetricExpr": "L1D_PEND_MISS.L2_STALL / CLKS",
-        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_sq_full",
-        "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
+        "MetricExpr": "INST_RETIRED.ANY",
+        "MetricGroup": "Summary;tma_L1_group",
+        "MetricName": "Instructions"
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
-        "MetricExpr": "((CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS) - tma_l2_bound) - tma_pmm_bound)",
-        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_dram_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS",
-        "ScaleUnit": "100%"
-    },
-    {
-        "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
-        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / CLKS",
-        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group",
-        "MetricName": "tma_mem_bandwidth",
-        "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM).  The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
+        "MetricExpr": "tma_retiring * SLOTS / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
+        "MetricGroup": "Pipeline;Ret",
+        "MetricName": "Retire"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
-        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth",
-        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group",
-        "MetricName": "tma_mem_latency",
-        "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM).  This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
+        "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
+        "MetricName": "Execute"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
-        "MetricExpr": "(43.5 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "Server;TopdownL5;tma_mem_latency_group",
-        "MetricName": "tma_local_dram",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average number of Uops issued by front-end when it issued something",
+        "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@",
+        "MetricGroup": "Fed;FetchBW",
+        "MetricName": "Fetch_UpC"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
-        "MetricExpr": "(108 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "Server;Snoop;TopdownL5;tma_mem_latency_group",
-        "MetricName": "tma_remote_dram",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
+        "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
+        "MetricGroup": "DSB;Fed;FetchBW",
+        "MetricName": "DSB_Coverage"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
-        "MetricExpr": "((97 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + (97 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_mem_latency_group",
-        "MetricName": "tma_remote_cache",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
+        "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@",
+        "MetricGroup": "DSBmiss",
+        "MetricName": "DSB_Switch_Cost"
     },
     {
-        "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a",
-        "MetricExpr": "(((1 - ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + 10 * ((MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) / ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + 10 * ((MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS) - tma_l2_bound)) if (1000000 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS) else 0)",
-        "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_pmm_bound",
-        "PublicDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
+        "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))",
+        "MetricGroup": "DSBmiss;Fed",
+        "MetricName": "DSB_Misses"
     },
     {
-        "BriefDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
-        "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CLKS",
-        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_store_bound",
-        "PublicDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS",
+        "MetricGroup": "DSBmiss;Fed",
+        "MetricName": "IpDSB_Miss_Ret"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
-        "MetricExpr": "((L2_RQSTS.RFO_HIT * 10 * (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES))) + (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
-        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_store_latency",
-        "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;BadSpec;BrMispredicts",
+        "MetricName": "IpMispredict"
     },
     {
-        "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
-        "MetricExpr": "(48 * Average_Frequency) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
-        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_false_sharing",
-        "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line.  Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
+        "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;BrMispredicts",
+        "MetricName": "Branch_Misprediction_Cost"
     },
     {
-        "BriefDescription": "This metric represents rate of split store accesses",
-        "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CORE_CLKS",
-        "MetricGroup": "TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_split_stores",
-        "PublicDescription": "This metric represents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of branches that are non-taken conditionals",
+        "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;Branches;CodeGen;PGO",
+        "MetricName": "Cond_NT"
     },
     {
-        "BriefDescription": "This metric estimates how often CPU was stalled  due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores",
-        "MetricExpr": "9 * OCR.STREAMING_WR.ANY_RESPONSE / CLKS",
-        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_streaming_stores",
-        "PublicDescription": "This metric estimates how often CPU was stalled  due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck. Sample with: OCR.STREAMING_WR.ANY_RESPONSE",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of branches that are taken conditionals",
+        "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;Branches;CodeGen;PGO",
+        "MetricName": "Cond_TK"
     },
     {
-        "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
-        "MetricExpr": "(7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CORE_CLKS",
-        "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_dtlb_store",
-        "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead.  Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page.  Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of branches that are CALL or RET",
+        "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;Branches",
+        "MetricName": "CallRet"
     },
     {
-        "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
-        "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
-        "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group",
-        "MetricName": "tma_store_stlb_hit",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps",
+        "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;Branches",
+        "MetricName": "Jump"
     },
     {
-        "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk",
-        "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS",
-        "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group",
-        "MetricName": "tma_store_stlb_miss",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)",
+        "MetricExpr": "1 - (Cond_NT + Cond_TK + CallRet + Jump)",
+        "MetricGroup": "Bad;Branches",
+        "MetricName": "Other_Branches"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
-        "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)",
-        "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group",
-        "MetricName": "tma_core_bound",
-        "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
+        "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)",
+        "MetricGroup": "Mem;MemoryBound;MemoryLat",
+        "MetricName": "Load_Miss_Real_Latency"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
-        "MetricExpr": "ARITH.DIVIDER_ACTIVE / CLKS",
-        "MetricGroup": "TopdownL3;tma_core_bound_group",
-        "MetricName": "tma_divider",
-        "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
+        "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
+        "MetricGroup": "Mem;MemoryBW;MemoryBound",
+        "MetricName": "MLP"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
-        "MetricExpr": "(cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if (ARITH.DIVIDER_ACTIVE < (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY)) else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CLKS",
-        "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
-        "MetricName": "tma_ports_utilization",
-        "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L1MPKI"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / CLKS + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_0",
-        "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
+        "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L1MPKI_Load"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations",
-        "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / CLKS",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_0_group",
-        "MetricName": "tma_serializing_operation",
-        "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+        "MetricGroup": "Backend;CacheMisses;Mem",
+        "MetricName": "L2MPKI"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions",
-        "MetricExpr": "37 * MISC_RETIRED.PAUSE_INST / CLKS",
-        "MetricGroup": "TopdownL6;tma_serializing_operation_group",
-        "MetricName": "tma_slow_pause",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: MISC_RETIRED.PAUSE_INST",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
+        "MetricExpr": "1e3 * (OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS) / Instructions",
+        "MetricGroup": "CacheMisses;Mem;Offcore",
+        "MetricName": "L2MPKI_All"
     },
     {
-        "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued",
-        "MetricExpr": "CLKS * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_0_group",
-        "MetricName": "tma_mixing_vectors",
-        "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (including speculative)",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L2MPKI_Load"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "EXE_ACTIVITY.1_PORTS_UTIL / CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_1",
-        "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache hits per kilo instruction for all demand loads  (including speculative)",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L2HPKI_Load"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "EXE_ACTIVITY.2_PORTS_UTIL / CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_2",
-        "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L3MPKI"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_3m",
-        "PublicDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "FB_HPKI"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
-        "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5 + UOPS_DISPATCHED.PORT_6) / (4 * CORE_CLKS)",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
-        "MetricName": "tma_alu_op_utilization",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
+        "MetricConstraint": "NO_NMI_WATCHDOG",
+        "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (2 * CORE_CLKS)",
+        "MetricGroup": "Mem;MemoryTLB",
+        "MetricName": "Page_Walks_Utilization"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED.PORT_0",
-        "MetricExpr": "UOPS_DISPATCHED.PORT_0 / CORE_CLKS",
-        "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group",
-        "MetricName": "tma_port_0",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
+        "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L1D_Cache_Fill_BW"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED.PORT_1",
-        "MetricExpr": "UOPS_DISPATCHED.PORT_1 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
-        "MetricName": "tma_port_1",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
+        "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L2_Cache_Fill_BW"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) Sample with: UOPS_DISPATCHED.PORT_5",
-        "MetricExpr": "UOPS_DISPATCHED.PORT_5 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
-        "MetricName": "tma_port_5",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
+        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L3_Cache_Fill_BW"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) Sample with: UOPS_DISPATCHED.PORT_6",
-        "MetricExpr": "UOPS_DISPATCHED.PORT_6 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
-        "MetricName": "tma_port_6",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
+        "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW;Offcore",
+        "MetricName": "L3_Cache_Access_BW"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3",
-        "MetricExpr": "UOPS_DISPATCHED.PORT_2_3 / (2 * CORE_CLKS)",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
-        "MetricName": "tma_load_op_utilization",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
+        "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / Instructions",
+        "MetricGroup": "L2Evicts;Mem;Server",
+        "MetricName": "L2_Evictions_Silent_PKI"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations Sample with: UOPS_DISPATCHED.PORT_7_8",
-        "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * CORE_CLKS)",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
-        "MetricName": "tma_store_op_utilization",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
+        "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / Instructions",
+        "MetricGroup": "L2Evicts;Mem;Server",
+        "MetricName": "L2_Evictions_NonSilent_PKI"
     },
     {
-        "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
-        "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
-        "MetricGroup": "TopdownL1;tma_L1_group",
-        "MetricName": "tma_retiring",
-        "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided.  Sample with: UOPS_RETIRED.SLOTS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
+        "MetricExpr": "L1D_Cache_Fill_BW",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L1D_Cache_Fill_BW_1T"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
-        "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)",
-        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
-        "MetricName": "tma_light_operations",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
+        "MetricExpr": "L2_Cache_Fill_BW",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L2_Cache_Fill_BW_1T"
     },
     {
-        "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
-        "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector",
-        "MetricGroup": "HPC;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_fp_arith",
-        "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
+        "MetricExpr": "L3_Cache_Fill_BW",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L3_Cache_Fill_BW_1T"
     },
     {
-        "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
-        "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD",
-        "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group",
-        "MetricName": "tma_x87_use",
-        "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
+        "MetricExpr": "L3_Cache_Access_BW",
+        "MetricGroup": "Mem;MemoryBW;Offcore",
+        "MetricName": "L3_Cache_Access_BW_1T"
     },
     {
-        "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / (tma_retiring * SLOTS)",
-        "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group",
-        "MetricName": "tma_fp_scalar",
-        "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average CPU Utilization",
+        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+        "MetricGroup": "HPC;Summary",
+        "MetricName": "CPU_Utilization"
     },
     {
-        "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (tma_retiring * SLOTS)",
-        "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group",
-        "MetricName": "tma_fp_vector",
-        "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
+        "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
+        "MetricGroup": "Power;Summary",
+        "MetricName": "Average_Frequency"
     },
     {
-        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / (tma_retiring * SLOTS)",
-        "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
-        "MetricName": "tma_fp_vector_128b",
-        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Giga Floating Point Operations Per Second",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time",
+        "MetricGroup": "Cor;Flops;HPC",
+        "MetricName": "GFLOPs",
+        "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
     },
     {
-        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / (tma_retiring * SLOTS)",
-        "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
-        "MetricName": "tma_fp_vector_256b",
-        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average Frequency Utilization relative nominal frequency",
+        "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
+        "MetricGroup": "Power",
+        "MetricName": "Turbo_Utilization"
     },
     {
-        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (tma_retiring * SLOTS)",
-        "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
-        "MetricName": "tma_fp_vector_512b",
-        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0",
+        "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / CORE_CLKS",
+        "MetricGroup": "Power",
+        "MetricName": "Power_License0_Utilization",
+        "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes."
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.",
-        "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY",
-        "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_memory_operations",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1",
+        "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / CORE_CLKS",
+        "MetricGroup": "Power",
+        "MetricName": "Power_License1_Utilization",
+        "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions."
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions.",
-        "MetricExpr": "tma_light_operations * BR_INST_RETIRED.ALL_BRANCHES / (tma_retiring * SLOTS)",
-        "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_branch_instructions",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)",
+        "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / CORE_CLKS",
+        "MetricGroup": "Power",
+        "MetricName": "Power_License2_Utilization",
+        "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX).  This includes high current AVX 512-bit instructions."
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions",
-        "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_retiring * SLOTS)",
-        "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_nop_instructions",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
+        "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)",
+        "MetricGroup": "SMT",
+        "MetricName": "SMT_2T_Utilization"
     },
     {
-        "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting",
-        "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_branch_instructions + tma_nop_instructions))",
-        "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_other_light_ops",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "OS",
+        "MetricName": "Kernel_Utilization"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
-        "MetricExpr": "tma_microcode_sequencer + tma_retiring * (UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=1@) / IDQ.MITE_UOPS",
-        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
-        "MetricName": "tma_heavy_operations",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
+        "MetricGroup": "OS",
+        "MetricName": "Kernel_CPI"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops",
-        "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer",
-        "MetricGroup": "TopdownL3;tma_heavy_operations_group",
-        "MetricName": "tma_few_uops_instructions",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
+        "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time",
+        "MetricGroup": "HPC;Mem;MemoryBW;SoC",
+        "MetricName": "DRAM_BW_Use"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
-        "MetricExpr": "((tma_retiring * SLOTS) / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
-        "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
-        "MetricName": "tma_microcode_sequencer",
-        "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
+        "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (Socket_CLKS / duration_time)",
+        "MetricGroup": "Mem;MemoryLat;SoC",
+        "MetricName": "MEM_Read_Latency"
     },
     {
-        "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
-        "MetricExpr": "100 * ASSISTS.ANY / SLOTS",
-        "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
-        "MetricName": "tma_assists",
-        "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
+        "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@thresh\\=1@",
+        "MetricGroup": "Mem;MemoryBW;SoC",
+        "MetricName": "MEM_Parallel_Reads"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
-        "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
-        "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
-        "MetricName": "tma_cisc",
-        "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
+        "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / cha_0@event\\=0x0@",
+        "MetricGroup": "Mem;MemoryLat;Server;SoC",
+        "MetricName": "MEM_PMM_Read_Latency"
     },
     {
-        "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
-        "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
-        "MetricGroup": "Bad;BadSpec;BrMispredicts",
-        "MetricName": "Mispredictions"
+        "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
+        "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / cha_0@event\\=0x0@",
+        "MetricGroup": "Mem;MemoryLat;Server;SoC",
+        "MetricName": "MEM_DRAM_Read_Latency"
     },
     {
-        "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) ",
-        "MetricGroup": "Mem;MemoryBW;Offcore",
-        "MetricName": "Memory_Bandwidth"
+        "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]",
+        "MetricExpr": "64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW;Server;SoC",
+        "MetricName": "PMM_Read_BW"
     },
     {
-        "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + (tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)))",
-        "MetricGroup": "Mem;MemoryLat;Offcore",
-        "MetricName": "Memory_Latency"
+        "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]",
+        "MetricExpr": "64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW;Server;SoC",
+        "MetricName": "PMM_Write_BW"
     },
     {
-        "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) ",
-        "MetricGroup": "Mem;MemoryTLB;Offcore",
-        "MetricName": "Memory_Data_TLBs"
+        "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]",
+        "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e9 / duration_time",
+        "MetricGroup": "IoBW;Mem;Server;SoC",
+        "MetricName": "IO_Write_BW"
     },
     {
-        "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)",
-        "MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)",
-        "MetricGroup": "Ret",
-        "MetricName": "Branching_Overhead"
+        "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]",
+        "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR) * 64 / 1e9 / duration_time",
+        "MetricGroup": "IoBW;Mem;Server;SoC",
+        "MetricName": "IO_Read_BW"
     },
     {
-        "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)",
-        "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)",
-        "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB",
-        "MetricName": "Big_Code"
+        "BriefDescription": "Socket actual clocks when any core is active on that socket",
+        "MetricExpr": "cha_0@event\\=0x0@",
+        "MetricGroup": "SoC",
+        "MetricName": "Socket_CLKS"
     },
     {
-        "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks",
-        "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code",
-        "MetricGroup": "Fed;FetchBW;Frontend",
-        "MetricName": "Instruction_Fetch_BW"
+        "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
+        "MetricGroup": "Branches;OS",
+        "MetricName": "IpFarBranch"
     },
     {
-        "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
-        "MetricExpr": "INST_RETIRED.ANY / CLKS",
-        "MetricGroup": "Ret;Summary",
-        "MetricName": "IPC"
+        "BriefDescription": "Uncore frequency per die [GHZ]",
+        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+        "MetricGroup": "SoC",
+        "MetricName": "UNCORE_FREQ"
     },
     {
-        "BriefDescription": "Uops Per Instruction",
-        "MetricExpr": "(tma_retiring * SLOTS) / INST_RETIRED.ANY",
-        "MetricGroup": "Pipeline;Ret;Retire",
-        "MetricName": "UPI"
+        "BriefDescription": "Percentage of time spent in the active CPU power state C0",
+        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+        "MetricName": "cpu_utilization",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instruction per taken branch",
-        "MetricExpr": "(tma_retiring * SLOTS) / BR_INST_RETIRED.NEAR_TAKEN",
-        "MetricGroup": "Branches;Fed;FetchBW",
-        "MetricName": "UpTB"
+        "BriefDescription": "CPU operating frequency (in GHz)",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / duration_time",
+        "MetricName": "cpu_operating_frequency",
+        "ScaleUnit": "1GHz"
     },
     {
-        "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
-        "MetricExpr": "1 / IPC",
-        "MetricGroup": "Mem;Pipeline",
-        "MetricName": "CPI"
+        "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY",
+        "MetricName": "cpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
-        "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
-        "MetricGroup": "Pipeline",
-        "MetricName": "CLKS"
+        "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
+        "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
+        "MetricName": "loads_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
-        "MetricExpr": "TOPDOWN.SLOTS",
-        "MetricGroup": "tma_L1_group",
-        "MetricName": "SLOTS"
+        "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
+        "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY",
+        "MetricName": "stores_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
-        "MetricExpr": "SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1",
-        "MetricGroup": "SMT;tma_L1_group",
-        "MetricName": "Slots_Utilization"
+        "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
+        "MetricName": "l1d_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "The ratio of Executed- by Issued-Uops",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
-        "MetricGroup": "Cor;Pipeline",
-        "MetricName": "Execute_per_Issue",
-        "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
+        "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ",
+        "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY",
+        "MetricName": "l1d_demand_data_read_hits_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
-        "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
-        "MetricGroup": "Ret;SMT;tma_L1_group",
-        "MetricName": "CoreIPC"
+        "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
+        "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
+        "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Floating Point Operations Per Cycle",
-        "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS",
-        "MetricGroup": "Flops;Ret",
-        "MetricName": "FLOPc"
+        "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ",
+        "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY",
+        "MetricName": "l2_demand_data_read_hits_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
-        "MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
-        "MetricGroup": "Cor;Flops;HPC",
-        "MetricName": "FP_Arith_Utilization",
-        "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
+        "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
+        "MetricName": "l2_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / ((UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
-        "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
-        "MetricName": "ILP"
+        "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
+        "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+        "MetricName": "l2_demand_data_read_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
-        "MetricExpr": "(1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0",
-        "MetricGroup": "Cor;SMT",
-        "MetricName": "Core_Bound_Likely"
+        "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
+        "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
+        "MetricName": "l2_demand_code_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
-        "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED",
-        "MetricGroup": "SMT",
-        "MetricName": "CORE_CLKS"
+        "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA + UNC_CHA_TOR_INSERTS.IA_MISS_DRD + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF) / INST_RETIRED.ANY",
+        "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS",
-        "MetricGroup": "InsType",
-        "MetricName": "IpLoad"
+        "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_CRD + UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF) / INST_RETIRED.ANY",
+        "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES",
-        "MetricGroup": "InsType",
-        "MetricName": "IpStore"
+        "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds",
+        "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD) * #num_packages)) * duration_time",
+        "MetricName": "llc_demand_data_read_miss_latency",
+        "ScaleUnit": "1ns"
     },
     {
-        "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Branches;Fed;InsType",
-        "MetricName": "IpBranch"
+        "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds",
+        "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL) * #num_packages)) * duration_time",
+        "MetricName": "llc_demand_data_read_miss_latency_for_local_requests",
+        "ScaleUnit": "1ns"
     },
     {
-        "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
-        "MetricGroup": "Branches;Fed;PGO",
-        "MetricName": "IpCall"
+        "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds",
+        "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE) * #num_packages)) * duration_time",
+        "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests",
+        "ScaleUnit": "1ns"
     },
     {
-        "BriefDescription": "Instruction per taken branch",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
-        "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
-        "MetricName": "IpTB"
+        "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to Intel(R) Optane(TM) Persistent Memory(PMEM) in nano seconds",
+        "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM) * #num_packages)) * duration_time",
+        "MetricName": "llc_demand_data_read_miss_to_pmem_latency",
+        "ScaleUnit": "1ns"
     },
     {
-        "BriefDescription": "Branch instructions per taken branch. ",
-        "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
-        "MetricGroup": "Branches;Fed;PGO",
-        "MetricName": "BpTkBranch"
+        "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds",
+        "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR) * #num_packages)) * duration_time",
+        "MetricName": "llc_demand_data_read_miss_to_dram_latency",
+        "ScaleUnit": "1ns"
     },
     {
-        "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
-        "MetricGroup": "Flops;InsType",
-        "MetricName": "IpFLOP"
+        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions",
+        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+        "MetricName": "itlb_2nd_level_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))",
-        "MetricGroup": "Flops;InsType",
-        "MetricName": "IpArith",
-        "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
+        "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions",
+        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+        "MetricName": "itlb_2nd_level_large_page_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
-        "MetricGroup": "Flops;FpScalar;InsType",
-        "MetricName": "IpArith_Scalar_SP",
-        "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions",
+        "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+        "MetricName": "dtlb_2nd_level_load_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
-        "MetricGroup": "Flops;FpScalar;InsType",
-        "MetricName": "IpArith_Scalar_DP",
-        "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions",
+        "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+        "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)",
-        "MetricGroup": "Flops;FpVector;InsType",
-        "MetricName": "IpArith_AVX128",
-        "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions",
+        "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+        "MetricName": "dtlb_2nd_level_store_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
-        "MetricGroup": "Flops;FpVector;InsType",
-        "MetricName": "IpArith_AVX256",
-        "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+        "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE)",
+        "MetricName": "numa_reads_addressed_to_local_dram",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
-        "MetricGroup": "Flops;FpVector;InsType",
-        "MetricName": "IpArith_AVX512",
-        "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+        "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE)",
+        "MetricName": "numa_reads_addressed_to_remote_dram",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@",
-        "MetricGroup": "Prefetches",
-        "MetricName": "IpSWPF"
+        "BriefDescription": "Uncore operating frequency in GHz",
+        "MetricExpr": "UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages) / 1e9 / duration_time",
+        "MetricName": "uncore_frequency",
+        "ScaleUnit": "1GHz"
     },
     {
-        "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
-        "MetricExpr": "INST_RETIRED.ANY",
-        "MetricGroup": "Summary;tma_L1_group",
-        "MetricName": "Instructions"
+        "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)",
+        "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 7.111111111111111 / 1e6 / duration_time",
+        "MetricName": "upi_data_transmit_bw",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
-        "MetricExpr": "(tma_retiring * SLOTS) / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
-        "MetricGroup": "Pipeline;Ret",
-        "MetricName": "Retire"
+        "BriefDescription": "DDR memory read bandwidth (MB/sec)",
+        "MetricExpr": "UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time",
+        "MetricName": "memory_bandwidth_read",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
-        "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
-        "MetricName": "Execute"
+        "BriefDescription": "DDR memory write bandwidth (MB/sec)",
+        "MetricExpr": "UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time",
+        "MetricName": "memory_bandwidth_write",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Average number of Uops issued by front-end when it issued something",
-        "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@",
-        "MetricGroup": "Fed;FetchBW",
-        "MetricName": "Fetch_UpC"
+        "BriefDescription": "DDR memory bandwidth (MB/sec)",
+        "MetricExpr": "(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time",
+        "MetricName": "memory_bandwidth_total",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
-        "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
-        "MetricGroup": "DSB;Fed;FetchBW",
-        "MetricName": "DSB_Coverage"
+        "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)",
+        "MetricExpr": "UNC_M_PMM_RPQ_INSERTS * 64 / 1e6 / duration_time",
+        "MetricName": "pmem_memory_bandwidth_read",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
-        "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@",
-        "MetricGroup": "DSBmiss",
-        "MetricName": "DSB_Switch_Cost"
+        "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)",
+        "MetricExpr": "UNC_M_PMM_WPQ_INSERTS * 64 / 1e6 / duration_time",
+        "MetricName": "pmem_memory_bandwidth_write",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
-        "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))",
-        "MetricGroup": "DSBmiss;Fed",
-        "MetricName": "DSB_Misses"
+        "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)",
+        "MetricExpr": "(UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS) * 64 / 1e6 / duration_time",
+        "MetricName": "pmem_memory_bandwidth_total",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS",
-        "MetricGroup": "DSBmiss;Fed",
-        "MetricName": "IpDSB_Miss_Ret"
+        "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
+        "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR + UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR) * 64 / 1e6 / duration_time",
+        "MetricName": "io_bandwidth_disk_or_network_writes",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;BadSpec;BrMispredicts",
-        "MetricName": "IpMispredict"
+        "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
+        "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR) * 64 / 1e6 / duration_time",
+        "MetricName": "io_bandwidth_disk_or_network_reads",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
-        "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;BrMispredicts",
-        "MetricName": "Branch_Misprediction_Cost"
+        "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
+        "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+        "MetricName": "percent_uops_delivered_from_decoded_icache",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of branches that are non-taken conditionals",
-        "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;Branches;CodeGen;PGO",
-        "MetricName": "Cond_NT"
+        "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
+        "MetricExpr": "IDQ.MITE_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+        "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of branches that are taken conditionals",
-        "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;Branches;CodeGen;PGO",
-        "MetricName": "Cond_TK"
+        "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
+        "MetricExpr": "IDQ.MS_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+        "MetricName": "percent_uops_delivered_from_microcode_sequencer",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of branches that are CALL or RET",
-        "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;Branches",
-        "MetricName": "CallRet"
+        "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.",
+        "MetricExpr": "UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1e6 / duration_time",
+        "MetricName": "llc_miss_local_memory_bandwidth_read",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps",
-        "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;Branches",
-        "MetricName": "Jump"
+        "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.",
+        "MetricExpr": "UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1e6 / duration_time",
+        "MetricName": "llc_miss_local_memory_bandwidth_write",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)",
-        "MetricExpr": "1 - (Cond_NT + Cond_TK + CallRet + Jump)",
-        "MetricGroup": "Bad;Branches",
-        "MetricName": "Other_Branches"
+        "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.",
+        "MetricExpr": "UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1e6 / duration_time",
+        "MetricName": "llc_miss_remote_memory_bandwidth_read",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
-        "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)",
-        "MetricGroup": "Mem;MemoryBound;MemoryLat",
-        "MetricName": "Load_Miss_Real_Latency"
+        "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.",
+        "MetricExpr": "UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1e6 / duration_time",
+        "MetricName": "llc_miss_remote_memory_bandwidth_write",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
-        "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
-        "MetricGroup": "Mem;MemoryBW;MemoryBound",
-        "MetricName": "MLP"
+        "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
+        "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / slots",
+        "MetricGroup": "PGO;TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_frontend_bound",
+        "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L1MPKI"
+        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
+        "MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / slots",
+        "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+        "MetricName": "tma_fetch_latency",
+        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L1MPKI_Load"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.",
+        "MetricExpr": "ICACHE_16B.IFDATA_STALL / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_icache_misses",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "Backend;CacheMisses;Mem",
-        "MetricName": "L2MPKI"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.",
+        "MetricExpr": "ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_itlb_misses",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
-        "MetricExpr": "1000 * ((OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD) + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS) / Instructions",
-        "MetricGroup": "CacheMisses;Mem;Offcore",
-        "MetricName": "L2MPKI_All"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
+        "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + tma_unknown_branches",
+        "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_branch_resteers",
+        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L2MPKI_Load"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ",
+        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+        "MetricName": "tma_mispredicts_resteers",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache hits per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L2HPKI_Load"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ",
+        "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+        "MetricName": "tma_clears_resteers",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L3MPKI"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
+        "MetricExpr": "10 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+        "MetricName": "tma_unknown_branches",
+        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "FB_HPKI"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
+        "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_dsb_switches",
+        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
-        "MetricConstraint": "NO_NMI_WATCHDOG",
-        "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (2 * CORE_CLKS)",
-        "MetricGroup": "Mem;MemoryTLB",
-        "MetricName": "Page_Walks_Utilization"
+        "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
+        "MetricExpr": "ILD_STALL.LCP / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_lcp",
+        "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
+        "ScaleUnit": "100%"
+    },
+    {
+        "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
+        "MetricExpr": "3 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_ms_switches",
+        "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
-        "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L1D_Cache_Fill_BW"
+        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
+        "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
+        "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+        "MetricName": "tma_fetch_bandwidth",
+        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues.  For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
-        "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L2_Cache_Fill_BW"
+        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
+        "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / CPU_CLK_UNHALTED.DISTRIBUTED / 2",
+        "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+        "MetricName": "tma_mite",
+        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L3_Cache_Fill_BW"
+        "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder",
+        "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=0x1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=0x2@) / CPU_CLK_UNHALTED.DISTRIBUTED",
+        "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group",
+        "MetricName": "tma_decoder0_alone",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time",
-        "MetricGroup": "Mem;MemoryBW;Offcore",
-        "MetricName": "L3_Cache_Access_BW"
+        "BriefDescription": "This metric represents fraction of cycles where (only) 4 uops were delivered by the MITE pipeline",
+        "MetricExpr": "(cpu@IDQ.MITE_UOPS\\,cmask\\=0x4@ - cpu@IDQ.MITE_UOPS\\,cmask\\=0x5@) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group",
+        "MetricName": "tma_mite_4wide",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
-        "MetricExpr": "1000 * L2_LINES_OUT.SILENT / Instructions",
-        "MetricGroup": "L2Evicts;Mem;Server",
-        "MetricName": "L2_Evictions_Silent_PKI"
+        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
+        "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / CPU_CLK_UNHALTED.DISTRIBUTED / 2",
+        "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+        "MetricName": "tma_dsb",
+        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline.  For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
-        "MetricExpr": "1000 * L2_LINES_OUT.NON_SILENT / Instructions",
-        "MetricGroup": "L2Evicts;Mem;Server",
-        "MetricName": "L2_Evictions_NonSilent_PKI"
+        "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
+        "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)), 0)",
+        "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_bad_speculation",
+        "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
-        "MetricExpr": "L1D_Cache_Fill_BW",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L1D_Cache_Fill_BW_1T"
+        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
+        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
+        "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+        "MetricName": "tma_branch_mispredicts",
+        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
-        "MetricExpr": "L2_Cache_Fill_BW",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L2_Cache_Fill_BW_1T"
+        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
+        "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)",
+        "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+        "MetricName": "tma_machine_clears",
+        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears.  These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "L3_Cache_Fill_BW",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L3_Cache_Fill_BW_1T"
+        "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
+        "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=0x1\\,edge\\=0x1@ / slots",
+        "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_backend_bound",
+        "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "L3_Cache_Access_BW",
-        "MetricGroup": "Mem;MemoryBW;Offcore",
-        "MetricName": "L3_Cache_Access_BW_1T"
+        "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
+        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound",
+        "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+        "MetricName": "tma_memory_bound",
+        "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average CPU Utilization",
-        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
-        "MetricGroup": "HPC;Summary",
-        "MetricName": "CPU_Utilization"
+        "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
+        "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CPU_CLK_UNHALTED.THREAD, 0)",
+        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_l1_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache.  The L1 data cache typically has the shortest latency.  However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
-        "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
-        "MetricGroup": "Power;Summary",
-        "MetricName": "Average_Frequency"
+        "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
+        "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_dtlb_load",
+        "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Giga Floating Point Operations Per Second",
-        "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1000000000) / duration_time",
-        "MetricGroup": "Cor;Flops;HPC",
-        "MetricName": "GFLOPs",
-        "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
+        "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
+        "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
+        "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group",
+        "MetricName": "tma_load_stlb_hit",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average Frequency Utilization relative nominal frequency",
-        "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
-        "MetricGroup": "Power",
-        "MetricName": "Turbo_Utilization"
+        "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk",
+        "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group",
+        "MetricName": "tma_load_stlb_miss",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0",
-        "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / CORE_CLKS",
-        "MetricGroup": "Power",
-        "MetricName": "Power_License0_Utilization",
-        "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes."
+        "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
+        "MetricExpr": "min(13 * LD_BLOCKS.STORE_FORWARD / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_store_fwd_blk",
+        "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1",
-        "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / CORE_CLKS",
-        "MetricGroup": "Power",
-        "MetricName": "Power_License1_Utilization",
-        "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions."
+        "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
+        "MetricExpr": "min((16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_lock_latency",
+        "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)",
-        "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / CORE_CLKS",
-        "MetricGroup": "Power",
-        "MetricName": "Power_License2_Utilization",
-        "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX).  This includes high current AVX 512-bit instructions."
+        "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ",
+        "MetricExpr": "min(Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_split_loads",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
-        "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0",
-        "MetricGroup": "SMT",
-        "MetricName": "SMT_2T_Utilization"
+        "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
+        "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_4k_aliasing",
+        "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
-        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
-        "MetricGroup": "OS",
-        "MetricName": "Kernel_Utilization"
+        "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
+        "MetricExpr": "L1D_PEND_MISS.FB_FULL / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_fb_full",
+        "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
-        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
-        "MetricGroup": "OS",
-        "MetricName": "Kernel_CPI"
+        "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
+        "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD)",
+        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_l2_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
-        "MetricExpr": "(64 * (uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@) / 1000000000) / duration_time",
-        "MetricGroup": "HPC;Mem;MemoryBW;SoC",
-        "MetricName": "DRAM_BW_Use"
+        "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
+        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_l3_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
-        "MetricExpr": "1000000000 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (Socket_CLKS / duration_time)",
-        "MetricGroup": "Mem;MemoryLat;SoC",
-        "MetricName": "MEM_Read_Latency"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
+        "MetricExpr": "min(((48 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 4 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + (47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 4 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_contested_accesses",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
-        "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / cha@event\\=0x36\\,umask\\=0xC817FE01\\,thresh\\=1@",
-        "MetricGroup": "Mem;MemoryBW;SoC",
-        "MetricName": "MEM_Parallel_Reads"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
+        "MetricExpr": "min((47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 4 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_data_sharing",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
-        "MetricExpr": "(1000000000 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / cha_0@event\\=0x0@)",
-        "MetricGroup": "Mem;MemoryLat;Server;SoC",
-        "MetricName": "MEM_PMM_Read_Latency"
+        "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
+        "MetricExpr": "min((23 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 4 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_l3_hit_latency",
+        "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
-        "MetricExpr": " 1000000000 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / cha_0@event\\=0x0@",
-        "MetricGroup": "Mem;MemoryLat;Server;SoC",
-        "MetricName": "MEM_DRAM_Read_Latency"
+        "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
+        "MetricExpr": "L1D_PEND_MISS.L2_STALL / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_sq_full",
+        "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]",
-        "MetricExpr": "((64 * imc@event\\=0xe3@ / 1000000000) / duration_time)",
-        "MetricGroup": "Mem;MemoryBW;Server;SoC",
-        "MetricName": "PMM_Read_BW"
+        "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
+        "MetricExpr": "min(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound - min(((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0), 1), 1)",
+        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_dram_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]",
-        "MetricExpr": "((64 * imc@event\\=0xe7@ / 1000000000) / duration_time)",
-        "MetricGroup": "Mem;MemoryBW;Server;SoC",
-        "MetricName": "PMM_Write_BW"
+        "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
+        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+        "MetricName": "tma_mem_bandwidth",
+        "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM).  The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]",
-        "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1000000000 / duration_time",
-        "MetricGroup": "IoBW;Mem;Server;SoC",
-        "MetricName": "IO_Write_BW"
+        "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
+        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CPU_CLK_UNHALTED.THREAD - tma_mem_bandwidth",
+        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+        "MetricName": "tma_mem_latency",
+        "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM).  This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]",
-        "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR) * 64 / 1000000000 / duration_time",
-        "MetricGroup": "IoBW;Mem;Server;SoC",
-        "MetricName": "IO_Read_BW"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
+        "MetricExpr": "min((66.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 23 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group",
+        "MetricName": "tma_local_dram",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Socket actual clocks when any core is active on that socket",
-        "MetricExpr": "cha_0@event\\=0x0@",
-        "MetricGroup": "SoC",
-        "MetricName": "Socket_CLKS"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
+        "MetricExpr": "min((131 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 23 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+        "MetricName": "tma_remote_dram",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
-        "MetricGroup": "Branches;OS",
-        "MetricName": "IpFarBranch"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
+        "MetricExpr": "min(((120 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 23 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + (120 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 23 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+        "MetricName": "tma_remote_cache",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C1 residency percent per core",
-        "MetricExpr": "(cstate_core@c1\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C1_Core_Residency"
+        "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a",
+        "MetricExpr": "min(((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0), 1)",
+        "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_pmm_bound",
+        "PublicDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C6 residency percent per core",
-        "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C6_Core_Residency"
+        "BriefDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
+        "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_store_bound",
+        "PublicDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C2 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C2_Pkg_Residency"
+        "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
+        "MetricExpr": "(L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_store_latency",
+        "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C6 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C6_Pkg_Residency"
+        "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
+        "MetricExpr": "min(48 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_false_sharing",
+        "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uncore frequency per die [GHZ]",
-        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000",
-        "MetricGroup": "SoC",
-        "MetricName": "UNCORE_FREQ"
+        "BriefDescription": "This metric represents rate of split store accesses",
+        "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CPU_CLK_UNHALTED.DISTRIBUTED",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_split_stores",
+        "PublicDescription": "This metric represents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granularity.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "CPU operating frequency (in GHz)",
-        "MetricExpr": "(( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ ) / 1000000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "cpu_operating_frequency",
-        "ScaleUnit": "1GHz"
+        "BriefDescription": "This metric estimates how often CPU was stalled  due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores",
+        "MetricExpr": "min(9 * OCR.STREAMING_WR.ANY_RESPONSE / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_streaming_stores",
+        "PublicDescription": "This metric estimates how often CPU was stalled  due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
-        "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "loads_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
+        "MetricExpr": "min((7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CPU_CLK_UNHALTED.DISTRIBUTED, 1)",
+        "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_dtlb_store",
+        "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead.  Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page.  Try using larger page sizes for large amounts of frequently-used data.",
+        "ScaleUnit": "100%"
+    },
+    {
+        "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
+        "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
+        "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group",
+        "MetricName": "tma_store_stlb_hit",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
-        "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "stores_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk",
+        "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CPU_CLK_UNHALTED.DISTRIBUTED",
+        "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group",
+        "MetricName": "tma_store_stlb_miss",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l1d_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
+        "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)",
+        "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+        "MetricName": "tma_core_bound",
+        "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ",
-        "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l1d_demand_data_read_hits_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
+        "MetricExpr": "ARITH.DIVIDER_ACTIVE / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group",
+        "MetricName": "tma_divider",
+        "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
-        "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
+        "MetricExpr": "((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) + 0 * slots",
+        "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group",
+        "MetricName": "tma_ports_utilization",
+        "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ",
-        "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_demand_data_read_hits_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+        "MetricExpr": "cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / CPU_CLK_UNHALTED.THREAD + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_0",
+        "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations",
+        "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group",
+        "MetricName": "tma_serializing_operation",
+        "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
-        "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_demand_data_read_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.",
+        "MetricExpr": "37 * MISC_RETIRED.PAUSE_INST / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group",
+        "MetricName": "tma_slow_pause",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
-        "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_demand_code_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued",
+        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY, 1)",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group",
+        "MetricName": "tma_mixing_vectors",
+        "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "( UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA + UNC_CHA_TOR_INSERTS.IA_MISS_DRD + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF ) / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+        "MetricExpr": "EXE_ACTIVITY.1_PORTS_UTIL / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_1",
+        "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "( UNC_CHA_TOR_INSERTS.IA_MISS_CRD + UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF ) / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+        "MetricExpr": "EXE_ACTIVITY.2_PORTS_UTIL / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_2",
+        "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds",
-        "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD) * #num_packages ) ) ) * duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_demand_data_read_miss_latency",
-        "ScaleUnit": "1ns"
+        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
+        "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_3m",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds",
-        "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL) * #num_packages ) ) ) * duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_demand_data_read_miss_latency_for_local_requests",
-        "ScaleUnit": "1ns"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
+        "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5 + UOPS_DISPATCHED.PORT_6) / (4 * CPU_CLK_UNHALTED.DISTRIBUTED)",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+        "MetricName": "tma_alu_op_utilization",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds",
-        "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE) * #num_packages ) ) ) * duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests",
-        "ScaleUnit": "1ns"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)",
+        "MetricExpr": "UOPS_DISPATCHED.PORT_0 / CPU_CLK_UNHALTED.DISTRIBUTED",
+        "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+        "MetricName": "tma_port_0",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to Intel(R) Optane(TM) Persistent Memory(PMEM) in nano seconds",
-        "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM) * #num_packages ) ) ) * duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_demand_data_read_miss_to_pmem_latency",
-        "ScaleUnit": "1ns"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)",
+        "MetricExpr": "UOPS_DISPATCHED.PORT_1 / CPU_CLK_UNHALTED.DISTRIBUTED",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+        "MetricName": "tma_port_1",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds",
-        "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR) * #num_packages ) ) ) * duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_demand_data_read_miss_to_dram_latency",
-        "ScaleUnit": "1ns"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)",
+        "MetricExpr": "UOPS_DISPATCHED.PORT_5 / CPU_CLK_UNHALTED.DISTRIBUTED",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+        "MetricName": "tma_port_5",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
-        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "itlb_2nd_level_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)",
+        "MetricExpr": "UOPS_DISPATCHED.PORT_6 / CPU_CLK_UNHALTED.DISTRIBUTED",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+        "MetricName": "tma_port_6",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
-        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "itlb_2nd_level_large_page_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations",
+        "MetricExpr": "UOPS_DISPATCHED.PORT_2_3 / (2 * CPU_CLK_UNHALTED.DISTRIBUTED)",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+        "MetricName": "tma_load_op_utilization",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
-        "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "dtlb_2nd_level_load_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
+        "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * CPU_CLK_UNHALTED.DISTRIBUTED)",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+        "MetricName": "tma_store_op_utilization",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.",
-        "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
+        "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * slots",
+        "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_retiring",
+        "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
-        "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "dtlb_2nd_level_store_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
+        "MetricExpr": "max(0, topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - tma_heavy_operations)",
+        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+        "MetricName": "tma_light_operations",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
-        "MetricExpr": "100 * ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL ) / ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE )",
-        "MetricGroup": "",
-        "MetricName": "numa_reads_addressed_to_local_dram",
-        "ScaleUnit": "1%"
+        "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
+        "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD + tma_fp_scalar + tma_fp_vector",
+        "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_fp_arith",
+        "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
-        "MetricExpr": "100 * ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE ) / ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE )",
-        "MetricGroup": "",
-        "MetricName": "numa_reads_addressed_to_remote_dram",
-        "ScaleUnit": "1%"
+        "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
+        "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD + 0 * slots",
+        "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group",
+        "MetricName": "tma_x87_use",
+        "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uncore operating frequency in GHz",
-        "MetricExpr": "( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_CLOCKTICKS) * #num_packages ) / 1000000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "uncore_frequency",
-        "ScaleUnit": "1GHz"
+        "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+        "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group",
+        "MetricName": "tma_fp_scalar",
+        "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_UPI_TxL_FLITS.ALL_DATA * (64 / 9.0) / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "upi_data_transmit_bw",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
+        "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)",
+        "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group",
+        "MetricName": "tma_fp_vector",
+        "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "DDR memory read bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "memory_bandwidth_read",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
+        "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)",
+        "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+        "MetricName": "tma_fp_vector_128b",
+        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "DDR memory write bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "memory_bandwidth_write",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
+        "MetricExpr": "min((FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)",
+        "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+        "MetricName": "tma_fp_vector_256b",
+        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "DDR memory bandwidth (MB/sec)",
-        "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "memory_bandwidth_total",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
+        "MetricExpr": "min((FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)",
+        "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+        "MetricName": "tma_fp_vector_512b",
+        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_M_PMM_RPQ_INSERTS * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "pmem_memory_bandwidth_read",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.",
+        "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY",
+        "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_memory_operations",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_M_PMM_WPQ_INSERTS * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "pmem_memory_bandwidth_write",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions.",
+        "MetricExpr": "tma_light_operations * BR_INST_RETIRED.ALL_BRANCHES / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+        "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_branch_instructions",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)",
-        "MetricExpr": "(( UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS ) * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "pmem_memory_bandwidth_total",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions",
+        "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+        "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_nop_instructions",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
-        "MetricExpr": "(( UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR + UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR ) * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "io_bandwidth_disk_or_network_writes",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting",
+        "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_branch_instructions + tma_nop_instructions))",
+        "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_other_light_ops",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
-        "MetricExpr": "(( UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR ) * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "io_bandwidth_disk_or_network_reads",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
+        "MetricExpr": "tma_microcode_sequencer + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * (UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@) / IDQ.MITE_UOPS",
+        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+        "MetricName": "tma_heavy_operations",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
-        "MetricExpr": "100 * ( IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )",
-        "MetricGroup": "",
-        "MetricName": "percent_uops_delivered_from_decoded_icache",
-        "ScaleUnit": "1%"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops",
+        "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer",
+        "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group",
+        "MetricName": "tma_few_uops_instructions",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
-        "MetricExpr": "100 * ( IDQ.MITE_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )",
-        "MetricGroup": "",
-        "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
-        "ScaleUnit": "1%"
+        "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
+        "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots / UOPS_ISSUED.ANY * IDQ.MS_UOPS / slots",
+        "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group",
+        "MetricName": "tma_microcode_sequencer",
+        "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
-        "MetricExpr": "100 * ( IDQ.MS_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )",
-        "MetricGroup": "",
-        "MetricName": "percent_uops_delivered_from_microcode_sequencer",
-        "ScaleUnit": "1%"
+        "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
+        "MetricExpr": "min(100 * ASSISTS.ANY / slots, 1)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+        "MetricName": "tma_assists",
+        "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.",
-        "MetricExpr": "( UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_miss_local_memory_bandwidth_read",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
+        "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+        "MetricName": "tma_cisc",
+        "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.",
-        "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_miss_local_memory_bandwidth_write",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "C1 residency percent per core",
+        "MetricExpr": "cstate_core@c1\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C1_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.",
-        "MetricExpr": "( UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_miss_remote_memory_bandwidth_read",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "C6 residency percent per core",
+        "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C6_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.",
-        "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_miss_remote_memory_bandwidth_write",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "C2 residency percent per package",
+        "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C2_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "%",
-        "MetricExpr": "100 * ( ( LSD.CYCLES_ACTIVE - LSD.CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED ) / 2 )",
-        "MetricGroup": "FetchBW;LSD;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
-        "MetricName": "tma_lsd",
-        "ScaleUnit": "1%"
+        "BriefDescription": "C6 residency percent per package",
+        "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C6_Pkg_Residency",
+        "ScaleUnit": "100%"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/memory.json b/tools/perf/pmu-events/arch/x86/icelakex/memory.json
index 48e8d1102b9d3..f36ac04f8d76a 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/memory.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/memory.json
@@ -1,549 +1,414 @@
 [
     {
         "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "6",
         "EventCode": "0xa3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x6"
     },
     {
         "BriefDescription": "Number of machine clears due to memory ordering conflicts.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x80",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "1009",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x10",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "20011",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x100",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "503",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x20",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x4",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "100003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x200",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "101",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x40",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "2003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x8",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "50021",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC00004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC00001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F3FC00002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F04400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC00400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84400400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L3.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x94002380",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L3.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84002380",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ITOM.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC08000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F84408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware and software prefetches to all cache levels that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.PREFETCHES.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F844027F0",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F3FC00477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F04400477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x70CC00477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores that missed the local socket's L1, L2, and L3 caches.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.STREAMING_WR.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x94000800",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000800",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data read requests that miss the L3 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb0",
         "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending.  Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
-        "BriefDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
-        "PEBScounters": "0,1,2,3",
-        "PublicDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.  Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "6",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache.  Note that this event does not capture all elapsed cycles while the requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times RTM abort was triggered.",
         "SampleAfterValue": "100003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_EVENTS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
         "SampleAfterValue": "100003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MEM",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
         "SampleAfterValue": "100003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
         "SampleAfterValue": "100003",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
         "SampleAfterValue": "100003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Number of times an RTM execution successfully committed",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.COMMIT",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times RTM commit succeeded.",
         "SampleAfterValue": "100003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of times an RTM execution started.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.START",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC3",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CAPACITY_READ",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CONFLICT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/other.json b/tools/perf/pmu-events/arch/x86/icelakex/other.json
index 919e620e7db87..63d5faf2fc43e 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/other.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/other.json
@@ -1,576 +1,459 @@
 [
     {
         "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x7"
     },
     {
         "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x18"
     },
     {
         "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture).  This includes high current AVX 512-bit instructions.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Hit snoop reply with data, line invalidated.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xef",
         "EventName": "CORE_SNOOP_RESPONSE.I_FWD_FE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's cache, after the data is forwarded back to the requestor and indicating the data was found unmodified in the (FE) Forward or Exclusive State in this cores caches cache.  A single snoop response from the core counts on all hyperthreads of the core.",
         "SampleAfterValue": "1000003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "HitM snoop reply with data, line invalidated.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xef",
         "EventName": "CORE_SNOOP_RESPONSE.I_FWD_M",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's caches, after the data is forwarded back to the requestor, and indicating the data was found modified(M) in this cores caches cache (aka HitM response).  A single snoop response from the core counts on all hyperthreads of the core.",
         "SampleAfterValue": "1000003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Hit snoop reply without sending the data, line invalidated.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xef",
         "EventName": "CORE_SNOOP_RESPONSE.I_HIT_FSE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated in this core's caches without being forwarded back to the requestor. The line was in Forward, Shared or Exclusive (FSE) state in this cores caches.  A single snoop response from the core counts on all hyperthreads of the core.",
         "SampleAfterValue": "1000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Line not found snoop reply",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xef",
         "EventName": "CORE_SNOOP_RESPONSE.MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts responses to snoops indicating that the data was not found (IHitI) in this core's caches. A single snoop response from the core counts on all hyperthreads of the Core.",
         "SampleAfterValue": "1000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Hit snoop reply with data, line kept in Shared state.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xef",
         "EventName": "CORE_SNOOP_RESPONSE.S_FWD_FE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (FS) Forward or Shared state.  A single snoop response from the core counts on all hyperthreads of the core.",
         "SampleAfterValue": "1000003",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "HitM snoop reply with data, line kept in Shared state",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xef",
         "EventName": "CORE_SNOOP_RESPONSE.S_FWD_M",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (M)odified state.  A single snoop response from the core counts on all hyperthreads of the core.",
         "SampleAfterValue": "1000003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Hit snoop reply without sending the data, line kept in Shared state.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xef",
         "EventName": "CORE_SNOOP_RESPONSE.S_HIT_FSE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts responses to snoops indicating the line was kept on this core in the (S)hared state, and that the data was found unmodified but not forwarded back to the requestor, initially the data was found in the cache in the (FSE) Forward, Shared state or Exclusive state.  A single snoop response from the core counts on all hyperthreads of the core.",
         "SampleAfterValue": "1000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x73C000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_CODE_RD.SNC_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x708000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x73C000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.LOCAL_PMM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that were supplied by PMM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.PMM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x703C00001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x730000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that were supplied by PMM attached to another socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.REMOTE_PMM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x703000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.SNC_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x708000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.SNC_PMM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x700800001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F3FFC0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x73C000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.LOCAL_PMM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.PMM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x703C00002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to another socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.REMOTE_PMM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x703000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.SNC_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x708000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.SNC_PMM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x700800002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x73C000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetch (which bring data to L2) that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L2.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10070",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetches to the L3 only that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L3.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x12380",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.HWPF_L3.REMOTE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90002380",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.ITOM.REMOTE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.OTHER.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x18000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F3FFC0477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x73C000477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.LOCAL_PMM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x70C000477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_PMM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x700C00477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.REMOTE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F33000477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x730000477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.REMOTE_MEMORY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x731800477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.REMOTE_PMM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x703000477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.SNC_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x708000477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.READS_TO_CORE.SNC_PMM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x700800477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10800",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.WRITE_ESTIMATE.MEMORY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xFBFF80822",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     }
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
index 52fba238bf1fd..4cf16a1fcad42 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
@@ -1,701 +1,489 @@
 [
     {
         "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x14",
         "EventName": "ARITH.DIVIDER_ACTIVE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x9"
     },
     {
         "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc1",
         "EventName": "ASSISTS.ANY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x7"
     },
     {
         "BriefDescription": "All branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts all branch instructions retired.",
         "SampleAfterValue": "400009"
     },
     {
         "BriefDescription": "Conditional branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.COND",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts conditional branch instructions retired.",
         "SampleAfterValue": "400009",
         "UMask": "0x11"
     },
     {
         "BriefDescription": "Not taken branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.COND_NTAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts not taken branch instructions retired.",
         "SampleAfterValue": "400009",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Taken conditional branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.COND_TAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts taken conditional branch instructions retired.",
         "SampleAfterValue": "400009",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Far branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.FAR_BRANCH",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts far branch instructions retired.",
         "SampleAfterValue": "100007",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Indirect near branch instructions retired (excluding returns)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.INDIRECT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.",
         "SampleAfterValue": "100003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Direct and indirect near call instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts both direct and indirect near call instructions retired.",
         "SampleAfterValue": "100007",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Return instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.NEAR_RETURN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts return instructions retired.",
         "SampleAfterValue": "100007",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Taken branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts taken branch instructions retired.",
         "SampleAfterValue": "400009",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "All mispredicted branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch.  When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
         "SampleAfterValue": "50021"
     },
     {
         "BriefDescription": "Mispredicted conditional branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.COND",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts mispredicted conditional branch instructions retired.",
         "SampleAfterValue": "50021",
         "UMask": "0x11"
     },
     {
         "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.COND_NTAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.",
         "SampleAfterValue": "50021",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "number of branch instructions retired that were mispredicted and taken.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.COND_TAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts taken conditional mispredicted branch instructions retired.",
         "SampleAfterValue": "50021",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.INDIRECT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
         "SampleAfterValue": "50021",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Mispredicted indirect CALL instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.INDIRECT_CALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired mispredicted indirect (near taken) calls, including both register and memory indirect.",
         "SampleAfterValue": "50021",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.",
         "SampleAfterValue": "50021",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.RET",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.",
         "SampleAfterValue": "50021",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xec",
         "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0.  A hyperthread becomes inactive when it executes the HLT or MWAIT instructions.  If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.",
         "SampleAfterValue": "25003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Reference cycles when the core is not in halt state.",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 2",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
-        "PEBScounters": "34",
         "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x3"
     },
     {
         "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts core crystal clock cycles when the thread is unhalted.",
         "SampleAfterValue": "25003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Core cycles when the thread is not in halt state",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD",
-        "PEBScounters": "33",
         "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Thread cycles when thread is not in halt state",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
-        "SampleAfterValue": "2000003",
-        "Speculative": "1"
+        "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "8",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "16",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "12",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0xc"
     },
     {
         "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "5",
         "EventCode": "0xa3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x5"
     },
     {
         "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "20",
         "EventCode": "0xa3",
         "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x14"
     },
     {
         "BriefDescription": "Total execution stalls.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xa3",
         "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa6",
         "EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa6",
         "EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa6",
         "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa6",
         "EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xA6",
         "EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.LCP",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
         "SampleAfterValue": "500009",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Instruction decoders utilized in a cycle",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x55",
         "EventName": "INST_DECODED.DECODERS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 0",
         "EventName": "INST_RETIRED.ANY",
         "PEBS": "1",
-        "PEBScounters": "32",
         "PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of instructions retired. General Counter - architectural event",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc0",
         "EventName": "INST_RETIRED.ANY_P",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Number of all retired NOP instructions.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc0",
         "EventName": "INST_RETIRED.NOP",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 0",
         "EventName": "INST_RETIRED.PREC_DIST",
         "PEBS": "1",
-        "PEBScounters": "32",
         "PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.ALL_RECOVERY_CYCLES",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x3"
     },
     {
         "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0d",
         "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
         "SampleAfterValue": "500009",
-        "Speculative": "1",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
         "SampleAfterValue": "500009",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "TMA slots where uops got dropped",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0d",
         "EventName": "INT_MISC.UOP_DROPPING",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.NO_SR",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.STORE_FORWARD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "False dependencies due to partial compare on address.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x07",
         "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times a load got blocked due to false dependencies due to partial compare on address.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4c",
         "EventName": "LOAD_HIT_PREFETCH.SWPF",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_ACTIVE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "5",
         "EventCode": "0xa8",
         "EventName": "LSD.CYCLES_OK",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of Uops delivered by the LSD.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xa8",
         "EventName": "LSD.UOPS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of machine clears (nukes) of any type.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.COUNT",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of machine clears (nukes) of any type.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Self-modifying code (SMC) detected.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.SMC",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Increments whenever there is an update to the LBR array.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xcc",
         "EventName": "MISC_RETIRED.LBR_INSERTS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR to be enabled properly.",
         "SampleAfterValue": "100003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xcc",
         "EventName": "MISC_RETIRED.PAUSE_INST",
         "PublicDescription": "Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.",
@@ -704,399 +492,273 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa2",
         "EventName": "RESOURCE_STALLS.SB",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa2",
         "EventName": "RESOURCE_STALLS.SCOREBOARD",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5e",
         "EventName": "RS_EVENTS.EMPTY_CYCLES",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5E",
         "EventName": "RS_EVENTS.EMPTY_END",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa4",
         "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's  slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
         "SampleAfterValue": "10000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 3",
         "EventName": "TOPDOWN.SLOTS",
-        "PEBScounters": "35",
         "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
         "SampleAfterValue": "10000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa4",
         "EventName": "TOPDOWN.SLOTS_P",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
         "SampleAfterValue": "10000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x56",
         "EventName": "UOPS_DECODED.DEC0",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Uops exclusively fetched by decoder 0",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of uops executed on port 0",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa1",
         "EventName": "UOPS_DISPATCHED.PORT_0",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of uops executed on port 1",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa1",
         "EventName": "UOPS_DISPATCHED.PORT_1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of uops executed on port 2 and 3",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa1",
         "EventName": "UOPS_DISPATCHED.PORT_2_3",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of uops executed on port 4 and 9",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa1",
         "EventName": "UOPS_DISPATCHED.PORT_4_9",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Number of uops executed on port 5",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa1",
         "EventName": "UOPS_DISPATCHED.PORT_5",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Number of uops executed on port 6",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa1",
         "EventName": "UOPS_DISPATCHED.PORT_6",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Number of uops executed on port 7 and 8",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa1",
         "EventName": "UOPS_DISPATCHED.PORT_7_8",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_3",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_4",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.STALL_CYCLES",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.THREAD",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of x87 uops dispatched.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.X87",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of x87 uops executed.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Uops that RAT issues to RS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0e",
         "EventName": "UOPS_ISSUED.ANY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles when RAT does not issue Uops to RS for the thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.STALL_CYCLES",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0e",
         "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
-        "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.",
+        "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to 'Mixing Intel AVX and Intel SSE Code' section of the Optimization Guide.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Retirement slots used.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.SLOTS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the retirement slots used each cycle.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles without actually retired uops.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.STALL_CYCLES",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "This event counts cycles without actually retired uops.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles with less than 10 actually retired uops.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "10",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
-        "PublicDescription": "Counts the number of cycles using always true condition (uops_ret &amp;lt; 16) applied to non PEBS uops retired event.",
+        "PublicDescription": "Counts the number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.",
         "SampleAfterValue": "1000003",
         "UMask": "0x2"
     }
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json
index 6872ae4b29d9b..0d495ae53f3d2 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json
@@ -1,1856 +1,1546 @@
 [
     {
-        "BriefDescription": "2LM Tag Check : Hit in Near Memory Cache",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD3",
-        "EventName": "UNC_M_TAGCHK.HIT",
+        "BriefDescription": "DRAM Activate Count : All Activates",
+        "EventCode": "0x01",
+        "EventName": "UNC_M_ACT_COUNT.ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "2LM Tag Check : Miss, no data in this line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD3",
-        "EventName": "UNC_M_TAGCHK.MISS_CLEAN",
+        "BriefDescription": "DRAM Activate Count : Activate due to Bypass",
+        "EventCode": "0x01",
+        "EventName": "UNC_M_ACT_COUNT.BYP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "DRAM Activate Count : Activate due to Bypass : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "2LM Tag Check : Miss, existing data may be evicted to Far Memory",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD3",
-        "EventName": "UNC_M_TAGCHK.MISS_DIRTY",
+        "BriefDescription": "All DRAM CAS commands issued",
+        "EventCode": "0x04",
+        "EventName": "UNC_M_CAS_COUNT.ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.",
+        "UMask": "0x3f",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "2LM Tag Check : Read Hit in Near Memory Cache",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD3",
-        "EventName": "UNC_M_TAGCHK.NM_RD_HIT",
+        "BriefDescription": "All DRAM read CAS commands issued (including underfills)",
+        "EventCode": "0x04",
+        "EventName": "UNC_M_CAS_COUNT.RD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issued on this channel.  This includes underfills.",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "2LM Tag Check : Write Hit in Near Memory Cache",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD3",
-        "EventName": "UNC_M_TAGCHK.NM_WR_HIT",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
+        "EventCode": "0x04",
+        "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the total number or DRAM Read CAS commands issued on this channel.  This includes both regular RD CAS commands as well as those with explicit Precharge.  AutoPre is only used in systems that are using closed page policy.  We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge commands. : Precharge due to read",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_M_PRE_COUNT.RD",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.",
+        "EventCode": "0x04",
+        "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge commands. : Precharge due to write",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_M_PRE_COUNT.WR",
+        "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)",
+        "EventCode": "0x04",
+        "EventName": "UNC_M_CAS_COUNT.RD_REG",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the total number of DRAM Read CAS commands issued on this channel.  This includes both regular RD CAS commands as well as those with implicit Precharge.   We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "All DRAM read CAS commands issued (including underfills)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "DRAM underfill read CAS commands issued",
         "EventCode": "0x04",
-        "EventName": "UNC_M_CAS_COUNT.RD",
+        "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
         "PerPkg": "1",
-        "UMask": "0x0f",
+        "PublicDescription": "Counts the total of DRAM Read CAS commands issued due to an underfill",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "All DRAM write CAS commands issued",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x04",
         "EventName": "UNC_M_CAS_COUNT.WR",
         "PerPkg": "1",
+        "PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel.",
         "UMask": "0x30",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "All DRAM CAS commands issued",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre",
         "EventCode": "0x04",
-        "EventName": "UNC_M_CAS_COUNT.ALL",
-        "PerPkg": "1",
-        "UMask": "0x3f",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "Number of DRAM Refreshes Issued",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M_DRAM_REFRESH.OPPORTUNISTIC",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "Number of DRAM Refreshes Issued",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M_DRAM_REFRESH.PANIC",
+        "EventName": "UNC_M_CAS_COUNT.WR_NONPRE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Number of DRAM Refreshes Issued",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M_DRAM_REFRESH.HIGH",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre",
+        "EventCode": "0x04",
+        "EventName": "UNC_M_CAS_COUNT.WR_PRE",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre : DRAM RD_CAS and WR_CAS Commands",
+        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Pending Queue Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_M_RPQ_INSERTS.PCH0",
+        "BriefDescription": "DRAM Clockticks",
+        "EventName": "UNC_M_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x01",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Pending Queue Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_M_RPQ_INSERTS.PCH1",
+        "BriefDescription": "Free running counter that increments for the Memory Controller",
+        "EventName": "UNC_M_CLOCKTICKS_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x02",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_M_WPQ_INSERTS.PCH0",
+        "BriefDescription": "DRAM Precharge All Commands",
+        "EventCode": "0x44",
+        "EventName": "UNC_M_DRAM_PRE_ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "DRAM Precharge All Commands : Counts the number of times that the precharge all command was sent.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_M_WPQ_INSERTS.PCH1",
+        "BriefDescription": "Number of DRAM Refreshes Issued",
+        "EventCode": "0x45",
+        "EventName": "UNC_M_DRAM_REFRESH.HIGH",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge commands. : Precharge due to page table",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_M_PRE_COUNT.PGT",
+        "BriefDescription": "Number of DRAM Refreshes Issued",
+        "EventCode": "0x45",
+        "EventName": "UNC_M_DRAM_REFRESH.OPPORTUNISTIC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Clockticks",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventName": "UNC_M_CLOCKTICKS",
+        "BriefDescription": "Number of DRAM Refreshes Issued",
+        "EventCode": "0x45",
+        "EventName": "UNC_M_DRAM_REFRESH.PANIC",
         "PerPkg": "1",
+        "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Half clockticks for IMC",
-        "Counter": "FIXED",
-        "CounterType": "FIXED",
         "EventCode": "0xff",
         "EventName": "UNC_M_HCLOCKTICKS",
         "PerPkg": "1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0",
+        "BriefDescription": "UNC_M_PARITY_ERRORS",
+        "EventCode": "0x2c",
+        "EventName": "UNC_M_PARITY_ERRORS",
         "PerPkg": "1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x81",
-        "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1",
+        "BriefDescription": "UNC_M_PCLS.RD",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M_PCLS.RD",
         "PerPkg": "1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0",
+        "BriefDescription": "UNC_M_PCLS.TOTAL",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M_PCLS.TOTAL",
         "PerPkg": "1",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1",
+        "BriefDescription": "UNC_M_PCLS.WR",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M_PCLS.WR",
         "PerPkg": "1",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Activate Count : All Activates",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x01",
-        "EventName": "UNC_M_ACT_COUNT.ALL",
+        "BriefDescription": "PMM Commands : All",
+        "EventCode": "0xEA",
+        "EventName": "UNC_M_PMM_CMD1.ALL",
         "PerPkg": "1",
-        "UMask": "0x0B",
+        "PublicDescription": "PMM Commands : All : Counts all commands issued to PMM",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge commands",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_M_PRE_COUNT.ALL",
+        "BriefDescription": "PMM Commands : Misc Commands (error, flow ACKs)",
+        "EventCode": "0xEA",
+        "EventName": "UNC_M_PMM_CMD1.MISC",
         "PerPkg": "1",
-        "UMask": "0x1C",
+        "UMask": "0x80",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Read Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL",
+        "BriefDescription": "PMM Commands : Misc GNTs",
+        "EventCode": "0xEA",
+        "EventName": "UNC_M_PMM_CMD1.MISC_GNT",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x40",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Read Queue Inserts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_M_PMM_RPQ_INSERTS",
+        "BriefDescription": "PMM Commands : Reads - RPQ",
+        "EventCode": "0xEA",
+        "EventName": "UNC_M_PMM_CMD1.RD",
         "PerPkg": "1",
+        "PublicDescription": "PMM Commands : Reads - RPQ : Counts read requests issued to the PMM RPQ",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Write Queue Inserts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE7",
-        "EventName": "UNC_M_PMM_WPQ_INSERTS",
+        "BriefDescription": "PMM Commands : RPQ GNTs",
+        "EventCode": "0xEA",
+        "EventName": "UNC_M_PMM_CMD1.RPQ_GNTS",
         "PerPkg": "1",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Commands : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "PMM Commands : Underfill reads",
         "EventCode": "0xEA",
-        "EventName": "UNC_M_PMM_CMD1.ALL",
+        "EventName": "UNC_M_PMM_CMD1.UFILL_RD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "PMM Commands : Underfill reads : Counts underfill read commands, due to a partial write, issued to PMM",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Commands : Reads - RPQ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "PMM Commands : Underfill GNTs",
         "EventCode": "0xEA",
-        "EventName": "UNC_M_PMM_CMD1.RD",
+        "EventName": "UNC_M_PMM_CMD1.WPQ_GNTS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "PMM Commands : Writes",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xEA",
         "EventName": "UNC_M_PMM_CMD1.WR",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "PMM Commands : Writes : Counts write commands issued to PMM",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Commands : Underfill reads",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xEA",
-        "EventName": "UNC_M_PMM_CMD1.UFILL_RD",
+        "BriefDescription": "PMM Commands - Part 2 : Expected No data packet (ERID matched NDP encoding)",
+        "EventCode": "0xEB",
+        "EventName": "UNC_M_PMM_CMD2.NODATA_EXP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Write Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE4",
-        "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL",
+        "BriefDescription": "PMM Commands - Part 2 : Unexpected No data packet (ERID matched a Read, but data was a NDP)",
+        "EventCode": "0xEB",
+        "EventName": "UNC_M_PMM_CMD2.NODATA_UNEXP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Data Buffer Inserts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x17",
-        "EventName": "UNC_M_RDB_INSERTS",
+        "BriefDescription": "PMM Commands - Part 2 : Opportunistic Reads",
+        "EventCode": "0xEB",
+        "EventName": "UNC_M_PMM_CMD2.OPP_RD",
         "PerPkg": "1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Accesses : Scoreboard Accesses Accepted",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M_SB_ACCESSES.ACCEPTS",
+        "BriefDescription": "PMM Commands - Part 2 : ECC Errors",
+        "EventCode": "0xEB",
+        "EventName": "UNC_M_PMM_CMD2.PMM_ECC_ERROR",
         "PerPkg": "1",
-        "UMask": "0x05",
+        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Accesses : Scoreboard Accesses Rejected",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M_SB_ACCESSES.REJECTS",
+        "BriefDescription": "PMM Commands - Part 2 : ERID detectable parity error",
+        "EventCode": "0xEB",
+        "EventName": "UNC_M_PMM_CMD2.PMM_ERID_ERROR",
         "PerPkg": "1",
-        "UMask": "0x0A",
+        "UMask": "0x40",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_M_CAS_COUNT.RD_REG",
+        "BriefDescription": "PMM Commands - Part 2",
+        "EventCode": "0xEB",
+        "EventName": "UNC_M_PMM_CMD2.PMM_ERID_STARVED",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x80",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM underfill read CAS commands issued",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
+        "BriefDescription": "PMM Commands - Part 2 : Read Requests - Slot 0",
+        "EventCode": "0xEB",
+        "EventName": "UNC_M_PMM_CMD2.REQS_SLOT0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Activate Count : Activate due to Bypass",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x01",
-        "EventName": "UNC_M_ACT_COUNT.BYP",
+        "BriefDescription": "PMM Commands - Part 2 : Read Requests - Slot 1",
+        "EventCode": "0xEB",
+        "EventName": "UNC_M_PMM_CMD2.REQS_SLOT1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG",
+        "BriefDescription": "PMM Read Queue Cycles Full",
+        "EventCode": "0xE2",
+        "EventName": "UNC_M_PMM_RPQ_CYCLES_FULL",
         "PerPkg": "1",
-        "UMask": "0x02",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL",
+        "BriefDescription": "PMM Read Queue Cycles Not Empty",
+        "EventCode": "0xE1",
+        "EventName": "UNC_M_PMM_RPQ_CYCLES_NE",
         "PerPkg": "1",
-        "UMask": "0x08",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_M_CAS_COUNT.WR_PRE",
+        "BriefDescription": "PMM Read Queue Inserts",
+        "EventCode": "0xE3",
+        "EventName": "UNC_M_PMM_RPQ_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "PMM Read Queue Inserts : Counts number of read requests allocated in the PMM Read Pending Queue.   This includes both ISOCH and non-ISOCH requests.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0",
+        "BriefDescription": "PMM Read Pending Queue Occupancy",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1",
+        "BriefDescription": "PMM Read Pending Queue Occupancy",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2",
+        "BriefDescription": "PMM Read Pending Queue Occupancy",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3",
+        "BriefDescription": "PMM Write Queue Cycles Full",
+        "EventCode": "0xE6",
+        "EventName": "UNC_M_PMM_WPQ_CYCLES_FULL",
         "PerPkg": "1",
-        "UMask": "0x08",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Throttle Cycles for Rank 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT0",
+        "BriefDescription": "PMM Write Queue Cycles Not Empty",
+        "EventCode": "0xE5",
+        "EventName": "UNC_M_PMM_WPQ_CYCLES_NE",
         "PerPkg": "1",
-        "UMask": "0x01",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Throttle Cycles for Rank 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT1",
+        "BriefDescription": "UNC_M_PMM_WPQ_FLUSH",
+        "EventCode": "0xe8",
+        "EventName": "UNC_M_PMM_WPQ_FLUSH",
         "PerPkg": "1",
-        "UMask": "0x02",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Throttle Cycles for Rank 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT0",
+        "BriefDescription": "UNC_M_PMM_WPQ_FLUSH_CYC",
+        "EventCode": "0xe9",
+        "EventName": "UNC_M_PMM_WPQ_FLUSH_CYC",
         "PerPkg": "1",
-        "UMask": "0x01",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Throttle Cycles for Rank 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT1",
+        "BriefDescription": "PMM Write Queue Inserts",
+        "EventCode": "0xE7",
+        "EventName": "UNC_M_PMM_WPQ_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "PMM Write Queue Inserts : Counts number of  write requests allocated in the PMM Write Pending Queue.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Pending Queue Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M_RPQ_CYCLES_NE.PCH0",
+        "BriefDescription": "PMM Write Pending Queue Occupancy",
+        "EventCode": "0xE4",
+        "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Pending Queue Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M_RPQ_CYCLES_NE.PCH1",
+        "BriefDescription": "PMM Write Pending Queue Occupancy",
+        "EventCode": "0xE4",
+        "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.CAS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Accesses : Read Accepts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M_SB_ACCESSES.RD_ACCEPTS",
+        "BriefDescription": "PMM Write Pending Queue Occupancy",
+        "EventCode": "0xE4",
+        "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.PWR",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Accesses : Read Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M_SB_ACCESSES.RD_REJECTS",
+        "BriefDescription": "Channel PPD Cycles",
+        "EventCode": "0x85",
+        "EventName": "UNC_M_POWER_CHANNEL_PPD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Channel PPD Cycles : Number of cycles when all the ranks in the channel are in PPD mode.  If IBT=off is enabled, then this can be used to count those cycles.  If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Accesses : NM read completions",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M_SB_ACCESSES.WR_ACCEPTS",
+        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+        "EventCode": "0x47",
+        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Accesses : NM write completions",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M_SB_ACCESSES.WR_REJECTS",
+        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+        "EventCode": "0x47",
+        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Accesses : FM read completions",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M_SB_ACCESSES.NM_RD_CMPS",
+        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+        "EventCode": "0x47",
+        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Accesses : FM write completions",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M_SB_ACCESSES.NM_WR_CMPS",
+        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+        "EventCode": "0x47",
+        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Accesses : Write Accepts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M_SB_ACCESSES.FM_RD_CMPS",
+        "BriefDescription": "Throttle Cycles for Rank 0",
+        "EventCode": "0x86",
+        "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. : Thermal throttling is performed per DIMM.  We support 3 DIMMs per channel.  This ID allows us to filter by ID.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Accesses : Write Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M_SB_ACCESSES.FM_WR_CMPS",
+        "BriefDescription": "Throttle Cycles for Rank 0",
+        "EventCode": "0x86",
+        "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT1",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": ": Alloc",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD9",
-        "EventName": "UNC_M_SB_CANARY.ALLOC",
+        "BriefDescription": "Clock-Enabled Self-Refresh",
+        "EventCode": "0x43",
+        "EventName": "UNC_M_POWER_SELF_REFRESH",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Clock-Enabled Self-Refresh : Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock.  This happens in some package C-states.  For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing.  One use of this is for Monroe technology.  Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": ": Dealloc",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD9",
-        "EventName": "UNC_M_SB_CANARY.DEALLOC",
+        "BriefDescription": "Throttle Cycles for Rank 0",
+        "EventCode": "0x46",
+        "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. : Thermal throttling is performed per DIMM.  We support 3 DIMMs per channel.  This ID allows us to filter by ID.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": ": Reject",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD9",
-        "EventName": "UNC_M_SB_CANARY.VLD",
+        "BriefDescription": "Throttle Cycles for Rank 0",
+        "EventCode": "0x46",
+        "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.NM_RD_STARVED",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0xd9",
-        "EventName": "UNC_M_SB_CANARY.NMRD_STARVED",
+        "BriefDescription": "DRAM Precharge commands.",
+        "EventCode": "0x02",
+        "EventName": "UNC_M_PRE_COUNT.ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
+        "UMask": "0x1c",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.NM_WR_STARVED",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0xd9",
-        "EventName": "UNC_M_SB_CANARY.NMWR_STARVED",
+        "BriefDescription": "DRAM Precharge commands. : Precharge due to page miss",
+        "EventCode": "0x02",
+        "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "DRAM Precharge commands. : Precharge due to page miss : Counts the number of DRAM Precharge commands sent on this channel. : Pages Misses are due to precharges from bank scheduler (rd/wr requests)",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_RD_STARVED",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0xd9",
-        "EventName": "UNC_M_SB_CANARY.FMRD_STARVED",
+        "BriefDescription": "DRAM Precharge commands. : Precharge due to page table",
+        "EventCode": "0x02",
+        "EventName": "UNC_M_PRE_COUNT.PGT",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel. : Prechages from Page Table",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_WR_STARVED",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0xd9",
-        "EventName": "UNC_M_SB_CANARY.FMWR_STARVED",
+        "BriefDescription": "DRAM Precharge commands. : Precharge due to read",
+        "EventCode": "0x02",
+        "EventName": "UNC_M_PRE_COUNT.RD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_TGR_WR_STARVED",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0xd9",
-        "EventName": "UNC_M_SB_CANARY.FMTGRWR_STARVED",
+        "BriefDescription": "DRAM Precharge commands. : Precharge due to write",
+        "EventCode": "0x02",
+        "EventName": "UNC_M_PRE_COUNT.WR",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Inserts : Reads",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M_SB_INSERTS.RDS",
+        "BriefDescription": "Read Data Buffer Full",
+        "EventCode": "0x19",
+        "EventName": "UNC_M_RDB_FULL",
         "PerPkg": "1",
-        "UMask": "0x01",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Inserts : Writes",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M_SB_INSERTS.WRS",
+        "BriefDescription": "Read Data Buffer Inserts",
+        "EventCode": "0x17",
+        "EventName": "UNC_M_RDB_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x02",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Inserts : Block region reads",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M_SB_INSERTS.BLOCK_RDS",
+        "BriefDescription": "Read Data Buffer Not Empty",
+        "EventCode": "0x18",
+        "EventName": "UNC_M_RDB_NOT_EMPTY",
         "PerPkg": "1",
-        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Inserts : Block region writes",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M_SB_INSERTS.BLOCK_WRS",
+        "BriefDescription": "Read Data Buffer Occupancy",
+        "EventCode": "0x1A",
+        "EventName": "UNC_M_RDB_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Occupancy : Reads",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD5",
-        "EventName": "UNC_M_SB_OCCUPANCY.RDS",
+        "BriefDescription": "Read Pending Queue Full Cycles",
+        "EventCode": "0x12",
+        "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Read Pending Queue Full Cycles : Counts the number of cycles when the Read Pending Queue is full.  When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead.  We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM.  This event only tracks non-ISOC queue entries.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Occupancy : Block region reads",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD5",
-        "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_RDS",
+        "BriefDescription": "Read Pending Queue Full Cycles",
+        "EventCode": "0x15",
+        "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Read Pending Queue Full Cycles : Counts the number of cycles when the Read Pending Queue is full.  When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead.  We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM.  This event only tracks non-ISOC queue entries.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Occupancy : Block region writes",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD5",
-        "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_WRS",
+        "BriefDescription": "Read Pending Queue Not Empty",
+        "EventCode": "0x11",
+        "EventName": "UNC_M_RPQ_CYCLES_NE.PCH0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Read Pending Queue Not Empty : Counts the number of cycles that the Read Pending Queue is not empty.  This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Number of Scoreboard Requests Rejected : NM requests rejected due to set conflict",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M_SB_REJECT.NM_SET_CNFLT",
+        "BriefDescription": "Read Pending Queue Not Empty",
+        "EventCode": "0x11",
+        "EventName": "UNC_M_RPQ_CYCLES_NE.PCH1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Read Pending Queue Not Empty : Counts the number of cycles that the Read Pending Queue is not empty.  This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Number of Scoreboard Requests Rejected : FM requests rejected due to full address conflict",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M_SB_REJECT.FM_ADDR_CNFLT",
+        "BriefDescription": "Read Pending Queue Allocations",
+        "EventCode": "0x10",
+        "EventName": "UNC_M_RPQ_INSERTS.PCH0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Number of Scoreboard Requests Rejected : Patrol requests rejected due to set conflict",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M_SB_REJECT.PATROL_SET_CNFLT",
+        "BriefDescription": "Read Pending Queue Allocations",
+        "EventCode": "0x10",
+        "EventName": "UNC_M_RPQ_INSERTS.PCH1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Number of Scoreboard Requests Rejected",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M_SB_REJECT.CANARY",
+        "BriefDescription": "Read Pending Queue Occupancy",
+        "EventCode": "0x80",
+        "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle.  This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_RD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0xd7",
-        "EventName": "UNC_M_SB_STRV_ALLOC.NMRD",
+        "BriefDescription": "Read Pending Queue Occupancy",
+        "EventCode": "0x81",
+        "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle.  This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_RD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0xd7",
-        "EventName": "UNC_M_SB_STRV_ALLOC.FMRD",
+        "BriefDescription": "Scoreboard Accesses : Scoreboard Accesses Accepted",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M_SB_ACCESSES.ACCEPTS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_WR",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xd7",
-        "EventName": "UNC_M_SB_STRV_ALLOC.NMWR",
+        "EventCode": "0xd2",
+        "EventName": "UNC_M_SB_ACCESSES.FMRD_CMPS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x40",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_WR",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xd7",
-        "EventName": "UNC_M_SB_STRV_ALLOC.FMWR",
+        "EventCode": "0xd2",
+        "EventName": "UNC_M_SB_ACCESSES.FMWR_CMPS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x80",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_TGR",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0xd7",
-        "EventName": "UNC_M_SB_STRV_ALLOC.FMTGR",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_RD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0xde",
-        "EventName": "UNC_M_SB_STRV_DEALLOC.NMRD",
+        "BriefDescription": "Scoreboard Accesses : Write Accepts",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M_SB_ACCESSES.FM_RD_CMPS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x40",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_RD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0xde",
-        "EventName": "UNC_M_SB_STRV_DEALLOC.FMRD",
+        "BriefDescription": "Scoreboard Accesses : Write Rejects",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M_SB_ACCESSES.FM_WR_CMPS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x80",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_WR",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xde",
-        "EventName": "UNC_M_SB_STRV_DEALLOC.NMWR",
+        "EventCode": "0xd2",
+        "EventName": "UNC_M_SB_ACCESSES.NMRD_CMPS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_WR",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xde",
-        "EventName": "UNC_M_SB_STRV_DEALLOC.FMWR",
+        "EventCode": "0xd2",
+        "EventName": "UNC_M_SB_ACCESSES.NMWR_CMPS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_TGR",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0xde",
-        "EventName": "UNC_M_SB_STRV_DEALLOC.FMTGR",
+        "BriefDescription": "Scoreboard Accesses : FM read completions",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M_SB_ACCESSES.NM_RD_CMPS",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_RD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0xd8",
-        "EventName": "UNC_M_SB_STRV_OCC.NMRD",
+        "BriefDescription": "Scoreboard Accesses : FM write completions",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M_SB_ACCESSES.NM_WR_CMPS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_RD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0xd8",
-        "EventName": "UNC_M_SB_STRV_OCC.FMRD",
+        "BriefDescription": "Scoreboard Accesses : Read Accepts",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M_SB_ACCESSES.RD_ACCEPTS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_WR",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0xd8",
-        "EventName": "UNC_M_SB_STRV_OCC.NMWR",
+        "BriefDescription": "Scoreboard Accesses : Read Rejects",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M_SB_ACCESSES.RD_REJECTS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_WR",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0xd8",
-        "EventName": "UNC_M_SB_STRV_OCC.FMWR",
+        "BriefDescription": "Scoreboard Accesses : Scoreboard Accesses Rejected",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M_SB_ACCESSES.REJECTS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_TGR",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0xd8",
-        "EventName": "UNC_M_SB_STRV_OCC.FMTGR",
+        "BriefDescription": "Scoreboard Accesses : NM read completions",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M_SB_ACCESSES.WR_ACCEPTS",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "UNC_M_SB_TAGGED.NEW",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xDD",
-        "EventName": "UNC_M_SB_TAGGED.NEW",
+        "BriefDescription": "Scoreboard Accesses : NM write completions",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M_SB_ACCESSES.WR_REJECTS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "UNC_M_SB_TAGGED.RD_HIT",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xDD",
-        "EventName": "UNC_M_SB_TAGGED.RD_HIT",
+        "BriefDescription": ": Alloc",
+        "EventCode": "0xD9",
+        "EventName": "UNC_M_SB_CANARY.ALLOC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "UNC_M_SB_TAGGED.RD_MISS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xDD",
-        "EventName": "UNC_M_SB_TAGGED.RD_MISS",
+        "BriefDescription": ": Dealloc",
+        "EventCode": "0xD9",
+        "EventName": "UNC_M_SB_CANARY.DEALLOC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "UNC_M_SB_TAGGED.DDR4_CMP",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xDD",
-        "EventName": "UNC_M_SB_TAGGED.DDR4_CMP",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_RD_STARVED",
+        "Deprecated": "1",
+        "EventCode": "0xd9",
+        "EventName": "UNC_M_SB_CANARY.FMRD_STARVED",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "UNC_M_SB_TAGGED.OCC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xDD",
-        "EventName": "UNC_M_SB_TAGGED.OCC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_TGR_WR_STARVED",
+        "Deprecated": "1",
+        "EventCode": "0xd9",
+        "EventName": "UNC_M_SB_CANARY.FMTGRWR_STARVED",
         "PerPkg": "1",
         "UMask": "0x80",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_M_WPQ_CYCLES_NE.PCH0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_WR_STARVED",
+        "Deprecated": "1",
+        "EventCode": "0xd9",
+        "EventName": "UNC_M_SB_CANARY.FMWR_STARVED",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x40",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_M_WPQ_CYCLES_NE.PCH1",
+        "BriefDescription": ": Near Mem Write Starved",
+        "EventCode": "0xD9",
+        "EventName": "UNC_M_SB_CANARY.FM_RD_STARVED",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue CAM Match",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M_WPQ_READ_HIT.PCH0",
+        "BriefDescription": ": Far Mem Write Starved",
+        "EventCode": "0xD9",
+        "EventName": "UNC_M_SB_CANARY.FM_TGR_WR_STARVED",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x80",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue CAM Match",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M_WPQ_READ_HIT.PCH1",
+        "BriefDescription": ": Far Mem Read Starved",
+        "EventCode": "0xD9",
+        "EventName": "UNC_M_SB_CANARY.FM_WR_STARVED",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x40",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue CAM Match",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_M_WPQ_WRITE_HIT.PCH0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.NM_RD_STARVED",
+        "Deprecated": "1",
+        "EventCode": "0xd9",
+        "EventName": "UNC_M_SB_CANARY.NMRD_STARVED",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue CAM Match",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_M_WPQ_WRITE_HIT.PCH1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.NM_WR_STARVED",
+        "Deprecated": "1",
+        "EventCode": "0xd9",
+        "EventName": "UNC_M_SB_CANARY.NMWR_STARVED",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "UNC_M_PCLS.RD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M_PCLS.RD",
+        "BriefDescription": ": Valid",
+        "EventCode": "0xD9",
+        "EventName": "UNC_M_SB_CANARY.NM_RD_STARVED",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "UNC_M_PCLS.WR",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M_PCLS.WR",
+        "BriefDescription": ": Near Mem Read Starved",
+        "EventCode": "0xD9",
+        "EventName": "UNC_M_SB_CANARY.NM_WR_STARVED",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "UNC_M_PCLS.TOTAL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M_PCLS.TOTAL",
+        "BriefDescription": ": Reject",
+        "EventCode": "0xD9",
+        "EventName": "UNC_M_SB_CANARY.VLD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Prefetch Inserts : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xDA",
-        "EventName": "UNC_M_SB_PREF_INSERTS.ALL",
+        "BriefDescription": "Scoreboard Cycles Full",
+        "EventCode": "0xD1",
+        "EventName": "UNC_M_SB_CYCLES_FULL",
         "PerPkg": "1",
-        "UMask": "0x01",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Prefetch Occupancy : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xDB",
-        "EventName": "UNC_M_SB_PREF_OCCUPANCY.ALL",
+        "BriefDescription": "Scoreboard Cycles Not-Empty",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M_SB_CYCLES_NE",
         "PerPkg": "1",
-        "UMask": "0x01",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Number of Scoreboard Requests Rejected",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M_SB_REJECT.DDR_EARLY_CMP",
+        "BriefDescription": "Scoreboard Inserts : Block region reads",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M_SB_INSERTS.BLOCK_RDS",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge All Commands",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M_DRAM_PRE_ALL",
+        "BriefDescription": "Scoreboard Inserts : Block region writes",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M_SB_INSERTS.BLOCK_WRS",
         "PerPkg": "1",
+        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "UNC_M_PARITY_ERRORS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2c",
-        "EventName": "UNC_M_PARITY_ERRORS",
+        "BriefDescription": "Scoreboard Inserts : Persistent Mem reads",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M_SB_INSERTS.PMM_RDS",
         "PerPkg": "1",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Channel PPD Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_M_POWER_CHANNEL_PPD",
+        "BriefDescription": "Scoreboard Inserts : Persistent Mem writes",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M_SB_INSERTS.PMM_WRS",
         "PerPkg": "1",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Clock-Enabled Self-Refresh",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_M_POWER_SELF_REFRESH",
+        "BriefDescription": "Scoreboard Inserts : Reads",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M_SB_INSERTS.RDS",
         "PerPkg": "1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Data Buffer Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_M_RDB_FULL",
+        "BriefDescription": "Scoreboard Inserts : Writes",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M_SB_INSERTS.WRS",
         "PerPkg": "1",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Data Buffer Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_M_RDB_NOT_EMPTY",
+        "BriefDescription": "Scoreboard Occupancy : Block region reads",
+        "EventCode": "0xD5",
+        "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_RDS",
         "PerPkg": "1",
+        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Data Buffer Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1A",
-        "EventName": "UNC_M_RDB_OCCUPANCY",
+        "BriefDescription": "Scoreboard Occupancy : Block region writes",
+        "EventCode": "0xD5",
+        "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_WRS",
         "PerPkg": "1",
+        "UMask": "0x40",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Pending Queue Full Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH0",
+        "BriefDescription": "Scoreboard Occupancy : Persistent Mem reads",
+        "EventCode": "0xD5",
+        "EventName": "UNC_M_SB_OCCUPANCY.PMM_RDS",
         "PerPkg": "1",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Pending Queue Full Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH1",
+        "BriefDescription": "Scoreboard Occupancy : Persistent Mem writes",
+        "EventCode": "0xD5",
+        "EventName": "UNC_M_SB_OCCUPANCY.PMM_WRS",
         "PerPkg": "1",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Cycles Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD1",
-        "EventName": "UNC_M_SB_CYCLES_FULL",
+        "BriefDescription": "Scoreboard Occupancy : Reads",
+        "EventCode": "0xD5",
+        "EventName": "UNC_M_SB_OCCUPANCY.RDS",
         "PerPkg": "1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Cycles Not-Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M_SB_CYCLES_NE",
+        "BriefDescription": "Scoreboard Prefetch Inserts : All",
+        "EventCode": "0xDA",
+        "EventName": "UNC_M_SB_PREF_INSERTS.ALL",
         "PerPkg": "1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Full Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x22",
-        "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH0",
+        "BriefDescription": "Scoreboard Prefetch Inserts : DDR4",
+        "EventCode": "0xDA",
+        "EventName": "UNC_M_SB_PREF_INSERTS.DDR",
         "PerPkg": "1",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Full Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x16",
-        "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH1",
+        "BriefDescription": "Scoreboard Prefetch Inserts : Persistent Mem",
+        "EventCode": "0xDA",
+        "EventName": "UNC_M_SB_PREF_INSERTS.PMM",
         "PerPkg": "1",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_M_CAS_COUNT.WR_NONPRE",
+        "BriefDescription": "Scoreboard Prefetch Occupancy : All",
+        "EventCode": "0xDB",
+        "EventName": "UNC_M_SB_PREF_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge commands. : Precharge due to page miss",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+        "BriefDescription": "Scoreboard Prefetch Occupancy : DDR4",
+        "EventCode": "0xDB",
+        "EventName": "UNC_M_SB_PREF_OCCUPANCY.DDR",
         "PerPkg": "1",
-        "UMask": "0x0c",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_PREF_OCCUPANCY.PMM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "Deprecated": "1",
         "EventCode": "0xdb",
         "EventName": "UNC_M_SB_PREF_OCCUPANCY.PMEM",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0xd2",
-        "EventName": "UNC_M_SB_ACCESSES.NMRD_CMPS",
+        "BriefDescription": "Scoreboard Prefetch Occupancy : Persistent Mem",
+        "EventCode": "0xdb",
+        "EventName": "UNC_M_SB_PREF_OCCUPANCY.PMM",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0xd2",
-        "EventName": "UNC_M_SB_ACCESSES.NMWR_CMPS",
+        "BriefDescription": "Number of Scoreboard Requests Rejected",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M_SB_REJECT.CANARY",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Commands : RPQ GNTs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xEA",
-        "EventName": "UNC_M_PMM_CMD1.RPQ_GNTS",
+        "BriefDescription": "Number of Scoreboard Requests Rejected",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M_SB_REJECT.DDR_EARLY_CMP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Commands : Underfill GNTs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xEA",
-        "EventName": "UNC_M_PMM_CMD1.WPQ_GNTS",
+        "BriefDescription": "Number of Scoreboard Requests Rejected : FM requests rejected due to full address conflict",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M_SB_REJECT.FM_ADDR_CNFLT",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Commands : Misc GNTs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xEA",
-        "EventName": "UNC_M_PMM_CMD1.MISC_GNT",
+        "BriefDescription": "Number of Scoreboard Requests Rejected : NM requests rejected due to set conflict",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M_SB_REJECT.NM_SET_CNFLT",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Commands : Misc Commands (error, flow ACKs)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xEA",
-        "EventName": "UNC_M_PMM_CMD1.MISC",
+        "BriefDescription": "Number of Scoreboard Requests Rejected : Patrol requests rejected due to set conflict",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M_SB_REJECT.PATROL_SET_CNFLT",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Commands - Part 2 : Opportunistic Reads",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xEB",
-        "EventName": "UNC_M_PMM_CMD2.OPP_RD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_RD",
+        "Deprecated": "1",
+        "EventCode": "0xd7",
+        "EventName": "UNC_M_SB_STRV_ALLOC.FMRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Commands - Part 2 : Expected No data packet (ERID matched NDP encoding)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xEB",
-        "EventName": "UNC_M_PMM_CMD2.NODATA_EXP",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_TGR",
+        "Deprecated": "1",
+        "EventCode": "0xd7",
+        "EventName": "UNC_M_SB_STRV_ALLOC.FMTGR",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Commands - Part 2 : Unexpected No data packet (ERID matched a Read, but data was a NDP)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xEB",
-        "EventName": "UNC_M_PMM_CMD2.NODATA_UNEXP",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_WR",
+        "Deprecated": "1",
+        "EventCode": "0xd7",
+        "EventName": "UNC_M_SB_STRV_ALLOC.FMWR",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Commands - Part 2 : Read Requests - Slot 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xEB",
-        "EventName": "UNC_M_PMM_CMD2.REQS_SLOT0",
+        "BriefDescription": ": Far Mem Read - Set",
+        "EventCode": "0xD7",
+        "EventName": "UNC_M_SB_STRV_ALLOC.FM_RD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Commands - Part 2 : Read Requests - Slot 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xEB",
-        "EventName": "UNC_M_PMM_CMD2.REQS_SLOT1",
+        "BriefDescription": ": Near Mem Read - Clear",
+        "EventCode": "0xD7",
+        "EventName": "UNC_M_SB_STRV_ALLOC.FM_TGR",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Commands - Part 2 : ECC Errors",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xEB",
-        "EventName": "UNC_M_PMM_CMD2.PMM_ECC_ERROR",
+        "BriefDescription": ": Far Mem Write - Set",
+        "EventCode": "0xD7",
+        "EventName": "UNC_M_SB_STRV_ALLOC.FM_WR",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Commands - Part 2 : ERID detectable parity error",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xEB",
-        "EventName": "UNC_M_PMM_CMD2.PMM_ERID_ERROR",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_RD",
+        "Deprecated": "1",
+        "EventCode": "0xd7",
+        "EventName": "UNC_M_SB_STRV_ALLOC.NMRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Commands - Part 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xEB",
-        "EventName": "UNC_M_PMM_CMD2.PMM_ERID_STARVED",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_WR",
+        "Deprecated": "1",
+        "EventCode": "0xd7",
+        "EventName": "UNC_M_SB_STRV_ALLOC.NMWR",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Read Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT",
+        "BriefDescription": ": Near Mem Read - Set",
+        "EventCode": "0xD7",
+        "EventName": "UNC_M_SB_STRV_ALLOC.NM_RD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Read Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT",
+        "BriefDescription": ": Near Mem Write - Set",
+        "EventCode": "0xD7",
+        "EventName": "UNC_M_SB_STRV_ALLOC.NM_WR",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Write Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE4",
-        "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.CAS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_RD",
+        "Deprecated": "1",
+        "EventCode": "0xde",
+        "EventName": "UNC_M_SB_STRV_DEALLOC.FMRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Write Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE4",
-        "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.PWR",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_TGR",
+        "Deprecated": "1",
+        "EventCode": "0xde",
+        "EventName": "UNC_M_SB_STRV_DEALLOC.FMTGR",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_WR",
         "Deprecated": "1",
-        "EventCode": "0xd2",
-        "EventName": "UNC_M_SB_ACCESSES.FMRD_CMPS",
+        "EventCode": "0xde",
+        "EventName": "UNC_M_SB_STRV_DEALLOC.FMWR",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": ": Far Mem Read - Set",
+        "EventCode": "0xDE",
+        "EventName": "UNC_M_SB_STRV_DEALLOC.FM_RD",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": ": Near Mem Read - Clear",
+        "EventCode": "0xDE",
+        "EventName": "UNC_M_SB_STRV_DEALLOC.FM_TGR",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": ": Far Mem Write - Set",
+        "EventCode": "0xDE",
+        "EventName": "UNC_M_SB_STRV_DEALLOC.FM_WR",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_RD",
         "Deprecated": "1",
-        "EventCode": "0xd2",
-        "EventName": "UNC_M_SB_ACCESSES.FMWR_CMPS",
+        "EventCode": "0xde",
+        "EventName": "UNC_M_SB_STRV_DEALLOC.NMRD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Inserts : Persistent Mem reads",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M_SB_INSERTS.PMM_RDS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_WR",
+        "Deprecated": "1",
+        "EventCode": "0xde",
+        "EventName": "UNC_M_SB_STRV_DEALLOC.NMWR",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Inserts : Persistent Mem writes",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M_SB_INSERTS.PMM_WRS",
+        "BriefDescription": ": Near Mem Read - Set",
+        "EventCode": "0xDE",
+        "EventName": "UNC_M_SB_STRV_DEALLOC.NM_RD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Occupancy : Persistent Mem reads",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD5",
-        "EventName": "UNC_M_SB_OCCUPANCY.PMM_RDS",
+        "BriefDescription": ": Near Mem Write - Set",
+        "EventCode": "0xDE",
+        "EventName": "UNC_M_SB_STRV_DEALLOC.NM_WR",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Occupancy : Persistent Mem writes",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD5",
-        "EventName": "UNC_M_SB_OCCUPANCY.PMM_WRS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_RD",
+        "Deprecated": "1",
+        "EventCode": "0xd8",
+        "EventName": "UNC_M_SB_STRV_OCC.FMRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "UNC_M_SB_TAGGED.PMM0_CMP",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xDD",
-        "EventName": "UNC_M_SB_TAGGED.PMM0_CMP",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_TGR",
+        "Deprecated": "1",
+        "EventCode": "0xd8",
+        "EventName": "UNC_M_SB_STRV_OCC.FMTGR",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "UNC_M_SB_TAGGED.PMM1_CMP",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xDD",
-        "EventName": "UNC_M_SB_TAGGED.PMM1_CMP",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_WR",
+        "Deprecated": "1",
+        "EventCode": "0xd8",
+        "EventName": "UNC_M_SB_STRV_OCC.FMWR",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "UNC_M_SB_TAGGED.PMM2_CMP",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xDD",
-        "EventName": "UNC_M_SB_TAGGED.PMM2_CMP",
+        "BriefDescription": ": Far Mem Read",
+        "EventCode": "0xD8",
+        "EventName": "UNC_M_SB_STRV_OCC.FM_RD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Prefetch Inserts : DDR4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xDA",
-        "EventName": "UNC_M_SB_PREF_INSERTS.DDR",
+        "BriefDescription": ": Near Mem Read - Clear",
+        "EventCode": "0xD8",
+        "EventName": "UNC_M_SB_STRV_OCC.FM_TGR",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Prefetch Inserts : Persistent Mem",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xDA",
-        "EventName": "UNC_M_SB_PREF_INSERTS.PMM",
+        "BriefDescription": ": Far Mem Write",
+        "EventCode": "0xD8",
+        "EventName": "UNC_M_SB_STRV_OCC.FM_WR",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Prefetch Occupancy : DDR4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xDB",
-        "EventName": "UNC_M_SB_PREF_OCCUPANCY.DDR",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_RD",
+        "Deprecated": "1",
+        "EventCode": "0xd8",
+        "EventName": "UNC_M_SB_STRV_OCC.NMRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Read Queue Cycles Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_M_PMM_RPQ_CYCLES_FULL",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_WR",
+        "Deprecated": "1",
+        "EventCode": "0xd8",
+        "EventName": "UNC_M_SB_STRV_OCC.NMWR",
         "PerPkg": "1",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Read Queue Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_M_PMM_RPQ_CYCLES_NE",
+        "BriefDescription": ": Near Mem Read",
+        "EventCode": "0xD8",
+        "EventName": "UNC_M_SB_STRV_OCC.NM_RD",
         "PerPkg": "1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Write Queue Cycles Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE6",
-        "EventName": "UNC_M_PMM_WPQ_CYCLES_FULL",
+        "BriefDescription": ": Near Mem Write",
+        "EventCode": "0xD8",
+        "EventName": "UNC_M_SB_STRV_OCC.NM_WR",
         "PerPkg": "1",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Write Queue Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_M_PMM_WPQ_CYCLES_NE",
+        "BriefDescription": "UNC_M_SB_TAGGED.DDR4_CMP",
+        "EventCode": "0xDD",
+        "EventName": "UNC_M_SB_TAGGED.DDR4_CMP",
         "PerPkg": "1",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "UNC_M_PMM_WPQ_FLUSH",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe8",
-        "EventName": "UNC_M_PMM_WPQ_FLUSH",
+        "BriefDescription": "UNC_M_SB_TAGGED.NEW",
+        "EventCode": "0xDD",
+        "EventName": "UNC_M_SB_TAGGED.NEW",
         "PerPkg": "1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "UNC_M_PMM_WPQ_FLUSH_CYC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe9",
-        "EventName": "UNC_M_PMM_WPQ_FLUSH_CYC",
+        "BriefDescription": "UNC_M_SB_TAGGED.OCC",
+        "EventCode": "0xDD",
+        "EventName": "UNC_M_SB_TAGGED.OCC",
         "PerPkg": "1",
+        "UMask": "0x80",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Scoreboard Prefetch Occupancy : Persistent Mem",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xdb",
-        "EventName": "UNC_M_SB_PREF_OCCUPANCY.PMM",
+        "BriefDescription": "UNC_M_SB_TAGGED.PMM0_CMP",
+        "EventCode": "0xDD",
+        "EventName": "UNC_M_SB_TAGGED.PMM0_CMP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Free running counter that increments for the Memory Controller",
-        "Counter": "4",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_M_CLOCKTICKS_FREERUN",
+        "BriefDescription": "UNC_M_SB_TAGGED.PMM1_CMP",
+        "EventCode": "0xDD",
+        "EventName": "UNC_M_SB_TAGGED.PMM1_CMP",
         "PerPkg": "1",
+        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": ": Valid",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD9",
-        "EventName": "UNC_M_SB_CANARY.NM_RD_STARVED",
+        "BriefDescription": "UNC_M_SB_TAGGED.PMM2_CMP",
+        "EventCode": "0xDD",
+        "EventName": "UNC_M_SB_TAGGED.PMM2_CMP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x40",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": ": Near Mem Read Starved",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD9",
-        "EventName": "UNC_M_SB_CANARY.NM_WR_STARVED",
+        "BriefDescription": "UNC_M_SB_TAGGED.RD_HIT",
+        "EventCode": "0xDD",
+        "EventName": "UNC_M_SB_TAGGED.RD_HIT",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": ": Near Mem Write Starved",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD9",
-        "EventName": "UNC_M_SB_CANARY.FM_RD_STARVED",
+        "BriefDescription": "UNC_M_SB_TAGGED.RD_MISS",
+        "EventCode": "0xDD",
+        "EventName": "UNC_M_SB_TAGGED.RD_MISS",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": ": Far Mem Read Starved",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD9",
-        "EventName": "UNC_M_SB_CANARY.FM_WR_STARVED",
+        "BriefDescription": "2LM Tag Check : Hit in Near Memory Cache",
+        "EventCode": "0xD3",
+        "EventName": "UNC_M_TAGCHK.HIT",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": ": Far Mem Write Starved",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD9",
-        "EventName": "UNC_M_SB_CANARY.FM_TGR_WR_STARVED",
+        "BriefDescription": "2LM Tag Check : Miss, no data in this line",
+        "EventCode": "0xD3",
+        "EventName": "UNC_M_TAGCHK.MISS_CLEAN",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": ": Near Mem Read - Set",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD7",
-        "EventName": "UNC_M_SB_STRV_ALLOC.NM_RD",
+        "BriefDescription": "2LM Tag Check : Miss, existing data may be evicted to Far Memory",
+        "EventCode": "0xD3",
+        "EventName": "UNC_M_TAGCHK.MISS_DIRTY",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": ": Far Mem Read - Set",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD7",
-        "EventName": "UNC_M_SB_STRV_ALLOC.FM_RD",
+        "BriefDescription": "2LM Tag Check : Read Hit in Near Memory Cache",
+        "EventCode": "0xD3",
+        "EventName": "UNC_M_TAGCHK.NM_RD_HIT",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": ": Near Mem Write - Set",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD7",
-        "EventName": "UNC_M_SB_STRV_ALLOC.NM_WR",
+        "BriefDescription": "2LM Tag Check : Write Hit in Near Memory Cache",
+        "EventCode": "0xD3",
+        "EventName": "UNC_M_TAGCHK.NM_WR_HIT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": ": Far Mem Write - Set",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD7",
-        "EventName": "UNC_M_SB_STRV_ALLOC.FM_WR",
+        "BriefDescription": "Write Pending Queue Full Cycles",
+        "EventCode": "0x22",
+        "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Write Pending Queue Full Cycles : Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC.  This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": ": Near Mem Read - Clear",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD7",
-        "EventName": "UNC_M_SB_STRV_ALLOC.FM_TGR",
+        "BriefDescription": "Write Pending Queue Full Cycles",
+        "EventCode": "0x16",
+        "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Write Pending Queue Full Cycles : Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC.  This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": ": Near Mem Read - Set",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xDE",
-        "EventName": "UNC_M_SB_STRV_DEALLOC.NM_RD",
+        "BriefDescription": "Write Pending Queue Not Empty",
+        "EventCode": "0x21",
+        "EventName": "UNC_M_WPQ_CYCLES_NE.PCH0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Write Pending Queue Not Empty : Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": ": Far Mem Read - Set",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xDE",
-        "EventName": "UNC_M_SB_STRV_DEALLOC.FM_RD",
+        "BriefDescription": "Write Pending Queue Not Empty",
+        "EventCode": "0x21",
+        "EventName": "UNC_M_WPQ_CYCLES_NE.PCH1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Write Pending Queue Not Empty : Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": ": Near Mem Write - Set",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xDE",
-        "EventName": "UNC_M_SB_STRV_DEALLOC.NM_WR",
+        "BriefDescription": "Write Pending Queue Allocations",
+        "EventCode": "0x20",
+        "EventName": "UNC_M_WPQ_INSERTS.PCH0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue.  This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": ": Far Mem Write - Set",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xDE",
-        "EventName": "UNC_M_SB_STRV_DEALLOC.FM_WR",
+        "BriefDescription": "Write Pending Queue Allocations",
+        "EventCode": "0x20",
+        "EventName": "UNC_M_WPQ_INSERTS.PCH1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue.  This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": ": Near Mem Read - Clear",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xDE",
-        "EventName": "UNC_M_SB_STRV_DEALLOC.FM_TGR",
+        "BriefDescription": "Write Pending Queue Occupancy",
+        "EventCode": "0x82",
+        "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle.  This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.  So, we provide filtering based on if the request has posted or not.  By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA.  The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory.  High average occupancies will generally coincide with high write major mode counts.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": ": Near Mem Read",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD8",
-        "EventName": "UNC_M_SB_STRV_OCC.NM_RD",
+        "BriefDescription": "Write Pending Queue Occupancy",
+        "EventCode": "0x83",
+        "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle.  This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.  So, we provide filtering based on if the request has posted or not.  By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA.  The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory.  High average occupancies will generally coincide with high write major mode counts.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": ": Far Mem Read",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD8",
-        "EventName": "UNC_M_SB_STRV_OCC.FM_RD",
+        "BriefDescription": "Write Pending Queue CAM Match",
+        "EventCode": "0x23",
+        "EventName": "UNC_M_WPQ_READ_HIT.PCH0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": ": Near Mem Write",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD8",
-        "EventName": "UNC_M_SB_STRV_OCC.NM_WR",
+        "BriefDescription": "Write Pending Queue CAM Match",
+        "EventCode": "0x23",
+        "EventName": "UNC_M_WPQ_READ_HIT.PCH1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": ": Far Mem Write",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD8",
-        "EventName": "UNC_M_SB_STRV_OCC.FM_WR",
+        "BriefDescription": "Write Pending Queue CAM Match",
+        "EventCode": "0x24",
+        "EventName": "UNC_M_WPQ_WRITE_HIT.PCH0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": ": Near Mem Read - Clear",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD8",
-        "EventName": "UNC_M_SB_STRV_OCC.FM_TGR",
+        "BriefDescription": "Write Pending Queue CAM Match",
+        "EventCode": "0x24",
+        "EventName": "UNC_M_WPQ_WRITE_HIT.PCH1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+        "UMask": "0x2",
         "Unit": "iMC"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json
index 03e99b8aed93e..8c09d13588494 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json
@@ -1,38557 +1,33727 @@
 [
     {
-        "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and are sent to the CHA's home agent",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL",
+        "Deprecated": "1",
+        "EventCode": "0x65",
+        "EventName": "UNC_CHA_2LM_NM_INVITOX.LOCAL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Remote INVITOE requests (exclusive ownership of a cache line without receiving data) sent to the CHA's home agent",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE",
+        "Deprecated": "1",
+        "EventCode": "0x65",
+        "EventName": "UNC_CHA_2LM_NM_INVITOX.REMOTE",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Local read requests that miss the SF/LLC and are sent to the CHA's home agent",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.READS_LOCAL",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT",
+        "Deprecated": "1",
+        "EventCode": "0x65",
+        "EventName": "UNC_CHA_2LM_NM_INVITOX.SETCONFLICT",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Remote read requests sent to the CHA's home agent",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.READS_REMOTE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC",
+        "Deprecated": "1",
+        "EventCode": "0x64",
+        "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.LLC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Local write requests that miss the SF/LLC and are sent to the CHA's home agent",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF",
+        "Deprecated": "1",
+        "EventCode": "0x64",
+        "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.SF",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Remote write requests sent to the CHA's home agent",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR",
+        "Deprecated": "1",
+        "EventCode": "0x64",
+        "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.TOR",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Clockticks of the uncore caching and home agent (CHA)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventName": "UNC_CHA_CLOCKTICKS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR",
+        "Deprecated": "1",
+        "EventCode": "0x70",
+        "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS2.MEMWR",
         "PerPkg": "1",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Normal priority reads issued to the memory controller from the CHA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x59",
-        "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI",
+        "Deprecated": "1",
+        "EventCode": "0x70",
+        "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS2.MEMWRNI",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5B",
-        "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized : All Lines Victimized",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.ALL",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x0F",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.READS",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x03",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Local write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.WRITES",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x0c",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop filter capacity evictions for E-state entries",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x3D",
-        "EventName": "UNC_CHA_SF_EVICTION.E_STATE",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop filter capacity evictions for M-state entries",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x3D",
-        "EventName": "UNC_CHA_SF_EVICTION.M_STATE",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop filter capacity evictions for S-state entries",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x3D",
-        "EventName": "UNC_CHA_SF_EVICTION.S_STATE",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All requests from iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
-        "UMask": "0xC001FF01",
-        "UMaskExt": "0xC001FF",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
+        "EventCode": "0x81",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0xC001FD01",
-        "UMaskExt": "0xC001FD",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
+        "EventCode": "0x81",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0xC80FFD01",
-        "UMaskExt": "0xC80FFD",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
+        "EventCode": "0x81",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMask": "0xC817FD01",
-        "UMaskExt": "0xC817FD",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0xCCC7FD01",
-        "UMaskExt": "0xCCC7FD",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0xC807FD01",
-        "UMaskExt": "0xC807FD",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0xC001FE01",
-        "UMaskExt": "0xC001FE",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "UMask": "0xC80FFE01",
-        "UMaskExt": "0xC80FFE",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
-        "UMask": "0xC817FE01",
-        "UMaskExt": "0xC817FE",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
-        "UMask": "0xCCC7FE01",
-        "UMaskExt": "0xCCC7FE",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
-        "UMask": "0xC807FE01",
-        "UMaskExt": "0xC807FE",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All requests from IO Devices",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
-        "UMask": "0xC001FF04",
-        "UMaskExt": "0xC001FF",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All requests from IO Devices that hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
+        "EventCode": "0x83",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "UMask": "0xC001FD04",
-        "UMaskExt": "0xC001FD",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All requests from IO Devices that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
+        "EventCode": "0x83",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0xC001FE04",
-        "UMaskExt": "0xC001FE",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : All requests from iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
+        "EventCode": "0x83",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "UMask": "0xC001FF01",
-        "UMaskExt": "0xC001FF",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "UMask": "0xC001FD01",
-        "UMaskExt": "0xC001FD",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "UMask": "0xC001FE01",
-        "UMaskExt": "0xC001FE",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0xC80FFE01",
-        "UMaskExt": "0xC80FFE",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0xC817FE01",
-        "UMaskExt": "0xC817FE",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
-        "UMask": "0xC807FE01",
-        "UMaskExt": "0xC807FE",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : All requests from IO Devices",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
-        "UMask": "0xC001FF04",
-        "UMaskExt": "0xC001FF",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
-        "UMask": "0xC001FD04",
-        "UMaskExt": "0xC001FD",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
-        "UMask": "0xC001FE04",
-        "UMaskExt": "0xC001FE",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
+        "EventCode": "0x89",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0xCC43FE04",
-        "UMaskExt": "0xCC43FE",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x01",
-        "EventName": "UNC_IIO_CLOCKTICKS",
-        "PerPkg": "1",
-        "Unit": "IIO"
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
+        "EventCode": "0x89",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR8",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
+        "EventCode": "0x89",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
-        "PortMask": "0x01",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
         "UMask": "0x80",
-        "Unit": "IIO"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
+        "EventCode": "0x8B",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
+        "EventCode": "0x8B",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
+        "EventCode": "0x8B",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
+        "EventCode": "0x85",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
+        "EventCode": "0x85",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
+        "EventCode": "0x85",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
-        "PortMask": "0x04",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
         "UMask": "0x80",
-        "Unit": "IIO"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
+        "EventCode": "0x87",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
+        "EventCode": "0x87",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
+        "EventCode": "0x87",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Misc Events - Set 1 : Lost Forward",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1F",
-        "EventName": "UNC_I_MISC1.LOST_FWD",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IRP"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.PCITOM",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IRP"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Coherent Ops : WbMtoI",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
+        "EventCode": "0x8D",
+        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "IRP"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in any state",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
+        "EventCode": "0x8D",
+        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in A state",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
+        "EventCode": "0x8D",
+        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in I state",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in S state",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2e",
-        "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tag Hit : Clean NearMem Read Hit",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tag Hit : Dirty NearMem Read Hit",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Clockticks of the mesh to memory (M2M)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventName": "UNC_M2M_CLOCKTICKS",
-        "PerPkg": "1",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
+        "EventCode": "0x8F",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
+        "EventCode": "0x8F",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
+        "EventCode": "0x8F",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken",
+        "EventCode": "0x57",
+        "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CHA to iMC Bypass : Intermediate bypass Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the intermediate bypass.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "CHA to iMC Bypass : Not Taken",
+        "EventCode": "0x57",
+        "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CHA to iMC Bypass : Not Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "CHA to iMC Bypass : Taken",
+        "EventCode": "0x57",
+        "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CHA to iMC Bypass : Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the full bypass.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "Clockticks of the uncore caching and home agent (CHA)",
+        "EventName": "UNC_CHA_CLOCKTICKS",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Clockticks",
+        "EventCode": "0xc0",
+        "EventName": "UNC_CHA_CMS_CLOCKTICKS",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0xf2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.ANY_ONE",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Core Cross Snoops Issued : Any Single Snoop : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0xf1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "Core Cross Snoops Issued : Multiple Core Requests",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Core Cross Snoops Issued : Multiple Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x42",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "Core Cross Snoops Issued : Single Core Requests",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.CORE_ONE",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Core Cross Snoops Issued : Single Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x41",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "Core Cross Snoops Issued : Multiple Eviction",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Core Cross Snoops Issued : Multiple Eviction : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x82",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "Core Cross Snoops Issued : Single Eviction",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "Core Cross Snoops Issued : Single Eviction : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x81",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "Core Cross Snoops Issued : Multiple External Snoops",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "Core Cross Snoops Issued : Multiple External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x22",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "Core Cross Snoops Issued : Single External Snoops",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.EXT_ONE",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "Core Cross Snoops Issued : Single External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "Core Cross Snoops Issued : Multiple Snoop Targets from Remote",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.REMOTE_GTONE",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "Core Cross Snoops Issued : Multiple Snoop Targets from Remote : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x22",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number requests PCIe makes of the main die : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL",
-        "FCMask": "0x07",
+        "BriefDescription": "Core Cross Snoops Issued : Single Snoop Target from Remote",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.REMOTE_ONE",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Core Cross Snoops Issued : Single Snoop Target from Remote : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "Counter 0 Occupancy",
+        "EventCode": "0x1F",
+        "EventName": "UNC_CHA_COUNTER0_OCCUPANCY",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counter 0 Occupancy : Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0.   The filtering available is found in the control register - threshold, invert and edge detect.   E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "Direct GO",
+        "EventCode": "0x6E",
+        "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "Direct GO",
+        "EventCode": "0x6E",
+        "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "Direct GO",
+        "EventCode": "0x6E",
+        "EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "Direct GO",
+        "EventCode": "0x6D",
+        "EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "Direct GO",
+        "EventCode": "0x6D",
+        "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "Direct GO",
+        "EventCode": "0x6D",
+        "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "Direct GO",
+        "EventCode": "0x6D",
+        "EventName": "UNC_CHA_DIRECT_GO_OPC.GO",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "Direct GO",
+        "EventCode": "0x6D",
+        "EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "Direct GO",
+        "EventCode": "0x6D",
+        "EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "Direct GO",
+        "EventCode": "0x6D",
+        "EventName": "UNC_CHA_DIRECT_GO_OPC.NOP",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "Direct GO",
+        "EventCode": "0x6D",
+        "EventName": "UNC_CHA_DIRECT_GO_OPC.PULL",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "Multi-socket cacheline directory state lookups : Snoop Not Needed",
+        "EventCode": "0x53",
+        "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Multi-socket cacheline directory state lookups : Snoop Not Needed : Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to. : Filters for transactions that did not have to send any snoops because the directory was clean.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "Multi-socket cacheline directory state lookups : Snoop Needed",
+        "EventCode": "0x53",
+        "EventName": "UNC_CHA_DIR_LOOKUP.SNP",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Multi-socket cacheline directory state lookups : Snoop Needed : Counts the number of transactions that looked up the directory.  Can be filtered by requests that had to snoop and those that did not have to. : Filters for transactions that had to send one or more snoops because the directory was not clean.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "Multi-socket cacheline directory state updates; memory write due to directory update from the home agent (HA) pipe",
+        "EventCode": "0x54",
+        "EventName": "UNC_CHA_DIR_UPDATE.HA",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Counts only multi-socket cacheline directory state updates memory writes issued from the home agent (HA) pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "Multi-socket cacheline directory state updates; memory write due to directory update from (table of requests) TOR pipe",
+        "EventCode": "0x54",
+        "EventName": "UNC_CHA_DIR_UPDATE.TOR",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Counts only multi-socket cacheline directory state updates due to memory writes issued from the table of requests (TOR) pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "Distress signal asserted : DPT Local",
+        "EventCode": "0xAF",
+        "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_LOCAL",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "Distress signal asserted : DPT Remote",
+        "EventCode": "0xAF",
+        "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_NONLOCAL",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
+        "EventCode": "0xAF",
+        "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_IV",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "Distress signal asserted : DPT Stalled -  No Credit",
+        "EventCode": "0xAF",
+        "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
         "PerPkg": "1",
-        "PortMask": "0x80",
+        "PublicDescription": "Distress signal asserted : DPT Stalled -  No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
         "UMask": "0x80",
-        "Unit": "IIO"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0f",
-        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
+        "BriefDescription": "Distress signal asserted : Horizontal",
+        "EventCode": "0xAF",
+        "EventName": "UNC_CHA_DISTRESS_ASSERTED.HORZ",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "IRP"
+        "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
+        "BriefDescription": "Distress signal asserted : PMM Local",
+        "EventCode": "0xAF",
+        "EventName": "UNC_CHA_DISTRESS_ASSERTED.PMM_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "IRP"
+        "PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Inbound write (fast path) requests received by the IRP",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
+        "BriefDescription": "Distress signal asserted : PMM Remote",
+        "EventCode": "0xAF",
+        "EventName": "UNC_CHA_DISTRESS_ASSERTED.PMM_NONLOCAL",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "IRP"
+        "PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Received : All Data",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
+        "BriefDescription": "Distress signal asserted : Vertical",
+        "EventCode": "0xAF",
+        "EventName": "UNC_CHA_DISTRESS_ASSERTED.VERT",
         "PerPkg": "1",
-        "UMask": "0x0F",
-        "Unit": "UPI LL"
+        "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Received : All Non Data",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
+        "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+        "EventCode": "0xBA",
+        "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
         "PerPkg": "1",
-        "UMask": "0x97",
-        "Unit": "UPI LL"
+        "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Sent : All Data",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
+        "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+        "EventCode": "0xBA",
+        "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
         "PerPkg": "1",
-        "UMask": "0x0F",
-        "Unit": "UPI LL"
+        "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Sent : All Non Data",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
+        "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state",
+        "EventCode": "0x5F",
+        "EventName": "UNC_CHA_HITME_HIT.EX_RDS",
         "PerPkg": "1",
-        "UMask": "0x97",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state.  This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*).",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Clockticks",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_CHA_CMS_CLOCKTICKS",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket ownership read requests that hit in S state.",
+        "EventCode": "0x5F",
+        "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ",
         "PerPkg": "1",
+        "PublicDescription": "Counts Number of Hits in HitMe Cache : Remote socket ownership read requests that hit in S state. : Shared hit and op is RdInvOwn, RdInv, Inv*",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Clockticks of the IO coherency tracker (IRP)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x01",
-        "EventName": "UNC_I_CLOCKTICKS",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket WBMtoE requests",
+        "EventCode": "0x5F",
+        "EventName": "UNC_CHA_HITME_HIT.WBMTOE",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "FAF RF full",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x17",
-        "EventName": "UNC_I_FAF_FULL",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket writeback to I or S requests",
+        "EventCode": "0x5F",
+        "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Counts Number of Hits in HitMe Cache : Remote socket writeback to I or S requests : op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_I_FAF_INSERTS",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed : Remote socket read requests",
+        "EventCode": "0x5E",
+        "EventName": "UNC_CHA_HITME_LOOKUP.READ",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Counts Number of times HitMe Cache is accessed : Remote socket read requests : op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Occupancy of the IRP FAF queue",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_I_FAF_OCCUPANCY",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed : Remote socket write (i.e. writeback) requests",
+        "EventCode": "0x5E",
+        "EventName": "UNC_CHA_HITME_LOOKUP.WRITE",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Counts Number of times HitMe Cache is accessed : Remote socket write (i.e. writeback) requests : op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "FAF allocation -- sent to ADQ",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x16",
-        "EventName": "UNC_I_FAF_TRANSACTIONS",
+        "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests that are not to shared line",
+        "EventCode": "0x60",
+        "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests that are not to shared line : No SF/LLC HitS/F and op is RdInvOwn",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Clockticks",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_M2M_CMS_CLOCKTICKS",
+        "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket read or invalidate requests",
+        "EventCode": "0x60",
+        "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Counts Number of Misses in HitMe Cache : Remote socket read or invalidate requests : op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Clockticks of the mesh to PCI (M2P)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x01",
-        "EventName": "UNC_M2P_CLOCKTICKS",
+        "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests to shared line",
+        "EventCode": "0x60",
+        "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN",
         "PerPkg": "1",
-        "Unit": "M2PCIe"
+        "PublicDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests to shared line : SF/LLC HitS/F and op is RdInvOwn",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Clockticks",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_M2P_CMS_CLOCKTICKS",
+        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Deallocate HtiME$ on Reads without RspFwdI*",
+        "EventCode": "0x61",
+        "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE",
         "PerPkg": "1",
-        "Unit": "M2PCIe"
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Clockticks of the mesh to UPI (M3UPI)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x01",
-        "EventName": "UNC_M3UPI_CLOCKTICKS",
+        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request",
+        "EventCode": "0x61",
+        "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
         "PerPkg": "1",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request : Received RspFwdI* for a local request, but converted HitME$ to SF entry",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number of kfclks",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x01",
-        "EventName": "UNC_UPI_CLOCKTICKS",
+        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache on RdInvOwn even if not RspFwdI*",
+        "EventCode": "0x61",
+        "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles in L1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_UPI_L1_POWER_CYCLES",
+        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request",
+        "EventCode": "0x61",
+        "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request : Updated HitME$ on RspFwdI* or local HitM/E received for a remote request",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles in L0p",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x27",
-        "EventName": "UNC_UPI_TxL0P_POWER_CYCLES",
+        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache to SHARed",
+        "EventCode": "0x61",
+        "EventName": "UNC_CHA_HITME_UPDATE.SHARED",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF",
+        "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
+        "EventCode": "0xB6",
+        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC88FFD01",
-        "UMaskExt": "0xC88FFD",
+        "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF",
+        "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
+        "EventCode": "0xB6",
+        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0xC897FD01",
-        "UMaskExt": "0xC897FD",
+        "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF",
+        "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
+        "EventCode": "0xB6",
+        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC887FD01",
-        "UMaskExt": "0xC887FD",
+        "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF",
+        "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
+        "EventCode": "0xB6",
+        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0xC88FFE01",
-        "UMaskExt": "0xC88FFE",
+        "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+        "EventCode": "0xBB",
+        "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC897FE01",
-        "UMaskExt": "0xC897FE",
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+        "EventCode": "0xBB",
+        "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0xC887FE01",
-        "UMaskExt": "0xC887FE",
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+        "EventCode": "0xBB",
+        "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0xCC43FD04",
-        "UMaskExt": "0xCC43FD",
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
-        "Counter": "FIXED",
-        "CounterType": "FIXED",
-        "EventCode": "0xff",
-        "EventName": "UNC_U_CLOCKTICKS",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+        "EventCode": "0xBB",
+        "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "Unit": "UBOX"
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+        "EventCode": "0xB7",
+        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0xCC43FF04",
-        "UMaskExt": "0xCC43FF",
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+        "EventCode": "0xB7",
+        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0xC887FF01",
-        "UMaskExt": "0xC887FF",
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+        "EventCode": "0xB7",
+        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC807FF01",
-        "UMaskExt": "0xC807FF",
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+        "EventCode": "0xB7",
+        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0xCCC7FF01",
-        "UMaskExt": "0xCCC7FF",
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF",
+        "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
+        "EventCode": "0xB8",
+        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC897FF01",
-        "UMaskExt": "0xC897FF",
+        "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : CRDs issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD",
+        "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
+        "EventCode": "0xB8",
+        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0xC80FFF01",
-        "UMaskExt": "0xC80FFF",
+        "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO",
+        "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
+        "EventCode": "0xB8",
+        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC807FF01",
-        "UMaskExt": "0xC807FF",
+        "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD",
+        "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
+        "EventCode": "0xB8",
+        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0xC817FF01",
-        "UMaskExt": "0xC817FF",
+        "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD",
+        "BriefDescription": "Horizontal IV Ring in Use : Left",
+        "EventCode": "0xB9",
+        "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT",
         "PerPkg": "1",
-        "UMask": "0xC80FFF01",
-        "UMaskExt": "0xC80FFF",
+        "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Sent : Null FLITs transmitted to any slot",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
+        "BriefDescription": "Horizontal IV Ring in Use : Right",
+        "EventCode": "0xB9",
+        "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT",
         "PerPkg": "1",
-        "UMask": "0x27",
-        "Unit": "UPI LL"
+        "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Received : Null FLITs received from any slot",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
+        "BriefDescription": "Normal priority reads issued to the memory controller from the CHA",
+        "EventCode": "0x59",
+        "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL",
         "PerPkg": "1",
-        "UMask": "0x27",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL",
+        "BriefDescription": "HA to iMC Reads Issued : ISOCH",
+        "EventCode": "0x59",
+        "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY",
         "PerPkg": "1",
-        "UMask": "0xC816FE01",
-        "UMaskExt": "0xC816FE",
+        "PublicDescription": "HA to iMC Reads Issued : ISOCH : Count of the number of reads issued to any of the memory controller channels.  This can be filtered by the priority of the reads.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE",
+        "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH",
+        "EventCode": "0x5B",
+        "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL",
         "PerPkg": "1",
-        "UMask": "0xC8177E01",
-        "UMaskExt": "0xC8177E",
+        "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to any of the memory controller channels.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL",
+        "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line",
+        "EventCode": "0x5B",
+        "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
         "PerPkg": "1",
-        "UMask": "0xC816FE01",
-        "UMaskExt": "0xC816FE",
+        "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line : Counts the total number of full line writes issued from the HA into the memory controller.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE",
+        "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH",
+        "EventCode": "0x5B",
+        "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
         "PerPkg": "1",
-        "UMask": "0xC8177E01",
-        "UMaskExt": "0xC8177E",
+        "PublicDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH : Counts the total number of full line writes issued from the HA into the memory controller.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; DRd Pref misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL",
+        "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial",
+        "EventCode": "0x5B",
+        "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
         "PerPkg": "1",
-        "UMask": "0xC896FE01",
-        "UMaskExt": "0xC896FE",
+        "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial : Counts the total number of full line writes issued from the HA into the memory controller.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; DRd Pref misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE",
+        "BriefDescription": "Cache and Snoop Filter Lookups; Any Request",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.ALL",
         "PerPkg": "1",
-        "UMask": "0xC8977E01",
-        "UMaskExt": "0xC8977E",
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ.  This does not include lookups originating from the ISMQ.",
+        "UMask": "0x1fffff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL",
+        "BriefDescription": "Cache Lookups : All transactions from Remote Agents",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.ALL_REMOTE",
         "PerPkg": "1",
-        "UMask": "0xC806FE01",
-        "UMaskExt": "0xC806FE",
+        "PublicDescription": "Cache Lookups : All transactions from Remote Agents : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x1e20ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE",
+        "BriefDescription": "Cache Lookups : All Request Filter",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.ANY_F",
         "PerPkg": "1",
-        "UMask": "0xC8077E01",
-        "UMaskExt": "0xC8077E",
+        "PublicDescription": "Cache Lookups : All Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Any local or remote transaction to the LLC, including prefetch.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.CODE",
         "PerPkg": "1",
-        "UMask": "0xC886FE01",
-        "UMaskExt": "0xC886FE",
+        "UMask": "0x1bd0ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.CODE_LOCAL",
         "PerPkg": "1",
-        "UMask": "0xC8877E01",
-        "UMaskExt": "0xC8877E",
+        "UMask": "0x19d0ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH",
+        "BriefDescription": "Cache Lookups : Code Reads",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ",
         "PerPkg": "1",
-        "UMask": "0xC8C7FF01",
-        "UMaskExt": "0xC8C7FF",
+        "PublicDescription": "Cache Lookups : Code Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x1bd0ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM",
+        "BriefDescription": "Cache Lookups : CRd Request Filter",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F",
         "PerPkg": "1",
-        "UMask": "0xCC57FF01",
-        "UMaskExt": "0xCC57FF",
+        "PublicDescription": "Cache Lookups : CRd Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC.  This includes CRd prefetch.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR",
+        "BriefDescription": "Cache Lookups : CRd Requests that come from the local socket (usually the core)",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL",
         "PerPkg": "1",
-        "UMask": "0xCD43FF04",
-        "UMaskExt": "0xCD43FF",
+        "PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC.  This includes CRd prefetch.",
+        "UMask": "0x19d0ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR",
+        "BriefDescription": "Cache Lookups : Code Read Misses",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_MISS",
         "PerPkg": "1",
-        "UMask": "0xCD43FD04",
-        "UMaskExt": "0xCD43FD",
+        "PublicDescription": "Cache Lookups : Code Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x1bd001",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR",
+        "BriefDescription": "Cache Lookups : CRd Requests that come from a Remote socket.",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE",
         "PerPkg": "1",
-        "UMask": "0xCD43FE04",
-        "UMaskExt": "0xCD43FE",
+        "PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC.  This includes CRd prefetch.",
+        "UMask": "0x1a10ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.CODE_REMOTE",
         "PerPkg": "1",
-        "UMask": "0xC8178A01",
-        "UMaskExt": "0xC8178A",
+        "UMask": "0x1a10ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM",
+        "BriefDescription": "Cache Lookups : Local request Filter",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F",
         "PerPkg": "1",
-        "UMask": "0xC8168A01",
-        "UMaskExt": "0xC8168A",
+        "PublicDescription": "Cache Lookups : Local request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Any local transaction to the LLC, including prefetches from the Core",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD",
         "PerPkg": "1",
-        "UMask": "0xC8170A01",
-        "UMaskExt": "0xC8170A",
+        "UMask": "0x1bc1ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR",
+        "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ",
         "PerPkg": "1",
-        "UMask": "0xc867fe01",
-        "UMaskExt": "0xc867fe",
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
+        "UMask": "0x1bc1ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; WCiL misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL",
         "PerPkg": "1",
-        "UMask": "0xc86ffe01",
-        "UMaskExt": "0xc86ffe",
+        "UMask": "0x1fc1ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM",
+        "BriefDescription": "Cache Lookups : Data Read Request Filter",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F",
         "PerPkg": "1",
-        "UMask": "0xC8178A01",
-        "UMaskExt": "0xC8178A",
+        "PublicDescription": "Cache Lookups : Data Read Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Read transactions.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Free running counter that increments for IIO clocktick",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_CLOCKTICKS_FREERUN",
+        "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request that come from the local socket (usually the core)",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
+        "UMask": "0x19c1ff",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : PMM - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.TO_PMM",
+        "BriefDescription": "Cache Lookups : Data Read Misses",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS",
         "PerPkg": "1",
-        "UMask": "0x0720",
-        "UMaskExt": "0x07",
-        "Unit": "M2M"
+        "PublicDescription": "Cache Lookups : Data Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x1bc101",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : PMM - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.TO_PMM",
+        "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Requests that come from a Remote socket",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x1C80",
-        "UMaskExt": "0x1C",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
+        "UMask": "0x1a01ff",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.DMND_READ_LOCAL",
         "PerPkg": "1",
-        "UMask": "0xCCD7FE01",
-        "UMaskExt": "0xCCD7FE",
+        "UMask": "0x841ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR",
+        "BriefDescription": "Cache Lookups : E State",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.E",
         "PerPkg": "1",
-        "UMask": "0xC8F3FE04",
-        "UMaskExt": "0xC8F3FE",
+        "PublicDescription": "Cache Lookups : E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Hit Exclusive State",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR",
+        "BriefDescription": "Cache Lookups : F State",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.F",
         "PerPkg": "1",
-        "UMask": "0xc8f3fe04",
-        "UMaskExt": "0xc8f3fe",
+        "PublicDescription": "Cache Lookups : F State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Hit Forward State",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR",
+        "BriefDescription": "Cache Lookups : Flush or Invalidate Requests",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV",
         "PerPkg": "1",
-        "UMask": "0xC8178601",
-        "UMaskExt": "0xC81786",
+        "PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x1a44ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR",
+        "BriefDescription": "Cache Lookups : Flush or Invalidate Requests that come from the local socket (usually the core)",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV_LOCAL",
         "PerPkg": "1",
-        "UMask": "0xC8168601",
-        "UMaskExt": "0xC81686",
+        "PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x1844ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR",
+        "BriefDescription": "Cache Lookups : Flush or Invalidate requests that come from a Remote socket.",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV_REMOTE",
         "PerPkg": "1",
-        "UMask": "0xC8170601",
-        "UMaskExt": "0xC81706",
+        "PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x1a04ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR",
+        "BriefDescription": "Cache Lookups : Flush or Invalidate Filter",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F",
         "PerPkg": "1",
-        "UMask": "0xC8178601",
-        "UMaskExt": "0xC81786",
+        "PublicDescription": "Cache Lookups : Flush or Invalidate Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR",
+        "BriefDescription": "Cache Lookups : I State",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.I",
         "PerPkg": "1",
-        "UMask": "0xC8F3FD04",
-        "UMaskExt": "0xC8F3FD",
+        "PublicDescription": "Cache Lookups : I State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Miss",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR",
+        "BriefDescription": "Cache and Snoop Filter Lookups; Prefetch requests to the LLC that come from the local socket (usually the core)",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL",
         "PerPkg": "1",
-        "UMask": "0xC8F3FF04",
-        "UMaskExt": "0xC8F3FF",
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
+        "UMask": "0x189dff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA",
+        "BriefDescription": "Cache Lookups : Local LLC prefetch requests (from LLC) Filter",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL_F",
         "PerPkg": "1",
-        "UMask": "0xCCD7FF01",
-        "UMaskExt": "0xCCD7FF",
+        "PublicDescription": "Cache Lookups : Local LLC prefetch requests (from LLC) Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Any local LLC prefetch to the LLC",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.LLC_PF_LOCAL",
         "PerPkg": "1",
-        "UMask": "0xC8F3FF04",
-        "UMaskExt": "0xC8F3FF",
+        "UMask": "0x189dff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOC_HOM",
+        "Deprecated": "1",
         "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ",
+        "EventName": "UNC_CHA_LLC_LOOKUP.LOCALLY_HOMED_ADDRESS",
         "PerPkg": "1",
-        "UMask": "0x1BC1FF",
-        "UMaskExt": "0x1BC1",
+        "UMask": "0xbdfff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
-        "FCMask": "0x04",
+        "BriefDescription": "Cache Lookups : Transactions homed locally Filter",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "PublicDescription": "Cache Lookups : Transactions homed locally Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Transaction whose address resides in the local MC.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
-        "FCMask": "0x04",
+        "BriefDescription": "Cache Lookups : Transactions homed locally",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.LOC_HOM",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "PublicDescription": "Cache Lookups : Transactions homed locally : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Transaction whose address resides in the local MC.",
+        "UMask": "0xbdfff",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
-        "FCMask": "0x04",
+        "BriefDescription": "Cache Lookups : M State",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.M",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "PublicDescription": "Cache Lookups : M State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Hit Modified State",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
-        "FCMask": "0x04",
+        "BriefDescription": "Cache Lookups : All Misses",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "PublicDescription": "Cache Lookups : All Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x1fe001",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4",
-        "FCMask": "0x04",
+        "BriefDescription": "Cache Lookups : Write Request Filter",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "PublicDescription": "Cache Lookups : Write Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Writeback transactions to the LLC  This includes all write transactions -- both Cacheable and UC.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5",
-        "FCMask": "0x04",
+        "BriefDescription": "Cache Lookups : Remote non-snoop request Filter",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.PREF_OR_DMND_REMOTE_F",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "PublicDescription": "Cache Lookups : Remote non-snoop request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Non-snoop transactions to the LLC from remote agent",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6",
-        "FCMask": "0x04",
+        "BriefDescription": "Cache Lookups : Reads",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.READ",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "PublicDescription": "Cache Lookups : Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x1bd9ff",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7",
-        "FCMask": "0x04",
+        "BriefDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_LOC_HOM",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "PublicDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x9d9ff",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
-        "FCMask": "0x04",
+        "BriefDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_REM_HOM",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x11d9ff",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 7",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7",
-        "FCMask": "0x04",
+        "BriefDescription": "Cache Lookups : Read Misses",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "Cache Lookups : Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x1bd901",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 6",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6",
-        "FCMask": "0x04",
+        "BriefDescription": "Cache Lookups : Locally HOMed Read Misses",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_LOC_HOM",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "Cache Lookups : Locally HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0xbd901",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 5",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5",
-        "FCMask": "0x04",
+        "BriefDescription": "Cache Lookups : Remotely HOMed Read Misses",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_REM_HOM",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Cache Lookups : Remotely HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x13d901",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4",
-        "FCMask": "0x04",
+        "BriefDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.READ_OR_SNOOP_REMOTE_MISS_REM_HOM",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x161901",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 3",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
-        "FCMask": "0x04",
+        "BriefDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.READ_REMOTE_LOC_HOM",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0xa19ff",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 2",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
-        "FCMask": "0x04",
+        "BriefDescription": "Cache Lookups : Reads that Hit the Snoop Filter",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.READ_SF_HIT",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Cache Lookups : Reads that Hit the Snoop Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x1bd90e",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 1",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
-        "FCMask": "0x04",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REM_HOM",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.REMOTELY_HOMED_ADDRESS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "UMask": "0x15dfff",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M",
+        "BriefDescription": "Cache Lookups : Transactions homed remotely Filter",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_F",
         "PerPkg": "1",
-        "UMask": "0x78",
-        "Unit": "IRP"
+        "PublicDescription": "Cache Lookups : Transactions homed remotely Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",
-        "FCMask": "0x04",
+        "BriefDescription": "Cache Lookups : Remote snoop request Filter",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP_F",
         "PerPkg": "1",
-        "PortMask": "0xff",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "PublicDescription": "Cache Lookups : Remote snoop request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Snoop transactions to the LLC from remote agent",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
-        "FCMask": "0x04",
+        "BriefDescription": "Cache and Snoop Filter Lookups; Snoop Requests from a Remote Socket",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP",
         "PerPkg": "1",
-        "UMask": "0xff",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ.  This does not include lookups originating from the ISMQ.",
+        "UMask": "0x1c19ff",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to locally HOMed memory",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL",
+        "BriefDescription": "Cache Lookups : Transactions homed remotely",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.REM_HOM",
         "PerPkg": "1",
-        "UMask": "0xCC42FF04",
-        "UMaskExt": "0xCC42FF",
+        "PublicDescription": "Cache Lookups : Transactions homed remotely : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC",
+        "UMask": "0x15dfff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to remotely HOMed memory",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE",
+        "BriefDescription": "Cache Lookups : RFO Requests",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.RFO",
         "PerPkg": "1",
-        "UMask": "0xCC437F04",
-        "UMaskExt": "0xCC437F",
+        "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC.  This includes RFO prefetch.",
+        "UMask": "0x1bc8ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to locally HOMed memory",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL",
+        "BriefDescription": "Cache Lookups : RFO Request Filter",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.RFO_F",
         "PerPkg": "1",
-        "UMask": "0xCD42FF04",
-        "UMaskExt": "0xCD42FF",
+        "PublicDescription": "Cache Lookups : RFO Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC.  This includes RFO prefetch.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to remotely HOMed memory",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE",
+        "BriefDescription": "Cache Lookups : RFO Requests that come from the local socket (usually the core)",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.RFO_LOCAL",
         "PerPkg": "1",
-        "UMask": "0xCD437F04",
-        "UMaskExt": "0xCD437F",
+        "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC.  This includes RFO prefetch.",
+        "UMask": "0x19c8ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline directory state lookups : Snoop Not Needed",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x53",
-        "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP",
+        "BriefDescription": "Cache Lookups : RFO Misses",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.RFO_MISS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cache Lookups : RFO Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x1bc801",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline directory state lookups : Snoop Needed",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x53",
-        "EventName": "UNC_CHA_DIR_LOOKUP.SNP",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.RFO_LOCAL",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.RFO_PREF_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x888ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x54",
-        "EventName": "UNC_CHA_DIR_UPDATE.HA",
+        "BriefDescription": "Cache Lookups : RFO Requests that come from a Remote socket.",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.RFO_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC.  This includes RFO prefetch.",
+        "UMask": "0x1a08ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline directory state updates : Directory Updated memory write from TOR pipe",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x54",
-        "EventName": "UNC_CHA_DIR_UPDATE.TOR",
+        "BriefDescription": "Cache Lookups : S State",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.S",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cache Lookups : S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Hit Shared State",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5F",
-        "EventName": "UNC_CHA_HITME_HIT.EX_RDS",
+        "BriefDescription": "Cache Lookups : SnoopFilter - E State",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.SF_E",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cache Lookups : SnoopFilter - E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : SF Hit Exclusive State",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized : Local - All Lines",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
+        "BriefDescription": "Cache Lookups : SnoopFilter - H State",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.SF_H",
         "PerPkg": "1",
-        "UMask": "0x200F",
-        "UMaskExt": "0x20",
+        "PublicDescription": "Cache Lookups : SnoopFilter - H State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : SF Hit HitMe State",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized : Remote - All Lines",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
+        "BriefDescription": "Cache Lookups : SnoopFilter - S State",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.SF_S",
         "PerPkg": "1",
-        "UMask": "0x800F",
-        "UMaskExt": "0x80",
+        "PublicDescription": "Cache Lookups : SnoopFilter - S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : SF Hit Shared State",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x64",
-        "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.TOR",
+        "BriefDescription": "Cache Lookups : Filters Requests for those that write info into the cache",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cache Lookups : Write Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Writeback transactions from L2 to the LLC  This includes all write transactions -- both Cacheable and UC.",
+        "UMask": "0x1a42ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
         "Deprecated": "1",
-        "EventCode": "0x64",
-        "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.SF",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x842ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
         "Deprecated": "1",
-        "EventCode": "0x64",
-        "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.LLC",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x17c2ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counter 0 Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1F",
-        "EventName": "UNC_CHA_COUNTER0_OCCUPANCY",
+        "BriefDescription": "Lines Victimized : All Lines Victimized",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.ALL",
         "PerPkg": "1",
+        "PublicDescription": "Lines Victimized : All Lines Victimized : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0xf",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number of times that an RFO hit in S state",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x39",
-        "EventName": "UNC_CHA_MISC.RFO_HIT_S",
+        "BriefDescription": "Lines Victimized : Lines in E state",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Lines Victimized : Lines in E state : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and remote INVITOE requests sent to the CHA's home agent",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.INVITOE",
+        "BriefDescription": "Lines Victimized : Local - All Lines",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
         "PerPkg": "1",
-        "UMask": "0x30",
+        "PublicDescription": "Lines Victimized : Local - All Lines : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x200f",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
+        "BriefDescription": "Lines Victimized : Local - Lines in E State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Lines Victimized : Local - Lines in E State : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x2002",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received : RspI",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5C",
-        "EventName": "UNC_CHA_SNOOP_RESP.RSPI",
+        "BriefDescription": "Lines Victimized : Local - Lines in M State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Lines Victimized : Local - Lines in M State : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x2001",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received : RspIFwd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5C",
-        "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD",
+        "BriefDescription": "Lines Victimized : Local Only",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Lines Victimized : Local Only : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received : RspS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5C",
-        "EventName": "UNC_CHA_SNOOP_RESP.RSPS",
+        "BriefDescription": "Lines Victimized : Local - Lines in S State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Lines Victimized : Local - Lines in S State : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x2004",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received : RspSFwd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5C",
-        "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD",
+        "BriefDescription": "Lines Victimized : Lines in M state",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Lines Victimized : Lines in M state : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.ALL",
+        "BriefDescription": "Lines Victimized : Remote - All Lines",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
         "PerPkg": "1",
-        "UMask": "0xC001FFff",
-        "UMaskExt": "0xC001FF",
+        "PublicDescription": "Lines Victimized : Remote - All Lines : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x800f",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCRD",
+        "BriefDescription": "Lines Victimized : Remote - Lines in E State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E",
         "PerPkg": "1",
-        "UMask": "0xcccffd01",
-        "UMaskExt": "0xcccffd",
+        "PublicDescription": "Lines Victimized : Remote - Lines in E State : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x8002",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDRD",
+        "BriefDescription": "Lines Victimized : Remote - Lines in M State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M",
         "PerPkg": "1",
-        "UMask": "0xccd7fd01",
-        "UMaskExt": "0xccd7fd",
+        "PublicDescription": "Lines Victimized : Remote - Lines in M State : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x8001",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
+        "BriefDescription": "Lines Victimized : Remote Only",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ONLY",
         "PerPkg": "1",
-        "UMask": "0xC80FFD01",
-        "UMaskExt": "0xC80FFD",
+        "PublicDescription": "Lines Victimized : Remote Only : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
+        "BriefDescription": "Lines Victimized : Remote - Lines in S State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S",
         "PerPkg": "1",
-        "UMask": "0xC817FD01",
-        "UMaskExt": "0xC817FD",
+        "PublicDescription": "Lines Victimized : Remote - Lines in S State : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x8004",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO",
+        "BriefDescription": "Lines Victimized : Lines in S State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE",
         "PerPkg": "1",
-        "UMask": "0xCCC7FD01",
-        "UMaskExt": "0xCCC7FD",
+        "PublicDescription": "Lines Victimized : Lines in S State : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
+        "BriefDescription": "Cbo Misc : CV0 Prefetch Miss",
+        "EventCode": "0x39",
+        "EventName": "UNC_CHA_MISC.CV0_PREF_MISS",
         "PerPkg": "1",
-        "UMask": "0xC807FD01",
-        "UMaskExt": "0xC807FD",
+        "PublicDescription": "Cbo Misc : CV0 Prefetch Miss : Miscellaneous events in the Cbo.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO",
+        "BriefDescription": "Cbo Misc : CV0 Prefetch Victim",
+        "EventCode": "0x39",
+        "EventName": "UNC_CHA_MISC.CV0_PREF_VIC",
         "PerPkg": "1",
-        "UMask": "0xCCC7FE01",
-        "UMaskExt": "0xCCC7FE",
+        "PublicDescription": "Cbo Misc : CV0 Prefetch Victim : Miscellaneous events in the Cbo.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
+        "BriefDescription": "Number of times that an RFO hit in S state.",
+        "EventCode": "0x39",
+        "EventName": "UNC_CHA_MISC.RFO_HIT_S",
         "PerPkg": "1",
-        "UMask": "0xc803fe04",
-        "UMaskExt": "0xc803fe",
+        "PublicDescription": "Counts when a RFO (the Read for Ownership issued before a  write) request hit a cacheline in the S (Shared) state.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
+        "BriefDescription": "Cbo Misc : Silent Snoop Eviction",
+        "EventCode": "0x39",
+        "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE",
         "PerPkg": "1",
-        "UMask": "0xc803fe04",
-        "UMaskExt": "0xc803fe",
+        "PublicDescription": "Cbo Misc : Silent Snoop Eviction : Miscellaneous events in the Cbo. : Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction.  This is useful because this information is lost in the PRE encodings.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
+        "BriefDescription": "Cbo Misc : Write Combining Aliasing",
+        "EventCode": "0x39",
+        "EventName": "UNC_CHA_MISC.WC_ALIASING",
         "PerPkg": "1",
-        "UMask": "0xcc43fe04",
-        "UMaskExt": "0xcc43fe",
+        "PublicDescription": "Cbo Misc : Write Combining Aliasing : Miscellaneous events in the Cbo. : Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write.  This occurs when there is WC aliasing.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
+        "EventCode": "0xE6",
+        "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST0",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
+        "EventCode": "0xE6",
+        "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST1",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "OSB Snoop Broadcast : Local InvItoE",
+        "EventCode": "0x55",
+        "EventName": "UNC_CHA_OSB.LOCAL_INVITOE",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "OSB Snoop Broadcast : Local InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "OSB Snoop Broadcast : Local Rd",
+        "EventCode": "0x55",
+        "EventName": "UNC_CHA_OSB.LOCAL_READ",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "OSB Snoop Broadcast : Local Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "OSB Snoop Broadcast : Off",
+        "EventCode": "0x55",
+        "EventName": "UNC_CHA_OSB.OFF_PWRHEURISTIC",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "OSB Snoop Broadcast : Off : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "OSB Snoop Broadcast : Remote Rd",
+        "EventCode": "0x55",
+        "EventName": "UNC_CHA_OSB.REMOTE_READ",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "OSB Snoop Broadcast : Remote Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "OSB Snoop Broadcast : Remote Rd InvItoE",
+        "EventCode": "0x55",
+        "EventName": "UNC_CHA_OSB.REMOTE_READINVITOE",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "OSB Snoop Broadcast : Remote Rd InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast",
+        "EventCode": "0x55",
+        "EventName": "UNC_CHA_OSB.RFO_HITS_SNP_BCAST",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.ADEGRCREDIT",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.AKEGRCREDIT",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.ALLRSFWAYS_RES",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.BLEGRCREDIT",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.FSF_VICP",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLOWSNP",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLWAYRSV",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_PAMATCH",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses : Hit M",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.HIT_M",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_WAYMATCH",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "IRP"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.RFO",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.HACREDIT",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "IRP"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x28",
-        "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.IDX_INPIPE",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles when Direct2UPI was Disabled",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x27",
-        "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.IPQ_SETMATCH_VICP",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x29",
-        "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.IRQ_PMM",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.NI",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.IRQ_SETMATCH_VICP",
         "PerPkg": "1",
-        "UMaskExt": "0x1E",
-        "Unit": "M2M"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tag Hit : Clean NearMem Underfill Hit",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.ISMQ_SETMATCH_VICP",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tag Hit : Dirty NearMem Underfill Hit",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.IVEGRCREDIT",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tag Miss",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x61",
-        "EventName": "UNC_M2M_TAG_MISS",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.LLC_WAYS_RES",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M to iMC Bypass : Not Taken",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x22",
-        "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.NOT_TAKEN",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.NOTALLOWSNOOP",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.ONE_FSF_VIC",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number of reads in which direct to core transaction was overridden",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x25",
-        "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.ONE_RSP_CON",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.ALL",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.PMM_MEMMODE_TORMATCH_MULTI",
         "PerPkg": "1",
-        "UMask": "0x0704",
-        "UMaskExt": "0x07",
-        "Unit": "M2M"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.NORMAL",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.PMM_MEMMODE_TOR_MATCH",
         "PerPkg": "1",
-        "UMask": "0x0701",
-        "UMaskExt": "0x07",
-        "Unit": "M2M"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : All Writes - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.ALL",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.PRQ_PMM",
         "PerPkg": "1",
-        "UMask": "0x1C10",
-        "UMaskExt": "0x1C",
-        "Unit": "M2M"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.FULL",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.PTL_INPIPE",
         "PerPkg": "1",
-        "UMask": "0x1C01",
-        "UMaskExt": "0x1C",
-        "Unit": "M2M"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.PARTIAL",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.RMW_SETMATCH",
         "PerPkg": "1",
-        "UMask": "0x1C02",
-        "UMaskExt": "0x1C",
-        "Unit": "M2M"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AD Ingress (from CMS) Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x01",
-        "EventName": "UNC_M2M_RxC_AD_INSERTS",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.RRQ_SETMATCH_VICP",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AD Ingress (from CMS) Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.SETMATCHENTRYWSCT",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Ingress (from CMS) Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_M2M_RxC_BL_INSERTS",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.SF_WAYS_RES",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Ingress (from CMS) Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x06",
-        "EventName": "UNC_M2M_RxC_BL_OCCUPANCY",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.TOPA_MATCH",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x09",
-        "EventName": "UNC_M2M_TxC_AD_INSERTS",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.TORID_MATCH_GO_P",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0A",
-        "EventName": "UNC_M2M_TxC_AD_OCCUPANCY",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_REQ",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Allocations : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x65",
-        "EventName": "UNC_CHA_2LM_NM_INVITOX.LOCAL",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x65",
-        "EventName": "UNC_CHA_2LM_NM_INVITOX.REMOTE",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x65",
-        "EventName": "UNC_CHA_2LM_NM_INVITOX.SETCONFLICT",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x70",
-        "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS2.MEMWR",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_WB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x70",
-        "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS2.MEMWRNI",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.WAY_MATCH",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA to iMC Bypass : Taken",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x57",
-        "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN",
+        "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL",
+        "EventCode": "0x65",
+        "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x57",
-        "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
+        "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE",
+        "EventCode": "0x65",
+        "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA to iMC Bypass : Not Taken",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x57",
-        "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
+        "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT",
+        "EventCode": "0x65",
+        "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued : Single Snoop Target from Remote",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.REMOTE_ONE",
+        "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC",
+        "EventCode": "0x64",
+        "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC : NM evictions due to another read to the same near memory set in the LLC.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued : Single External Snoops",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.EXT_ONE",
+        "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC",
+        "EventCode": "0x64",
+        "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC : NM evictions due to another read to the same near memory set in the SF.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued : Single Core Requests",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.CORE_ONE",
+        "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in TOR",
+        "EventCode": "0x64",
+        "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR",
         "PerPkg": "1",
-        "UMask": "0x41",
+        "PublicDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in TOR : No Reject in the CHA due to a pending read to the same near memory set in the TOR.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued : Single Eviction",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE",
+        "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC",
+        "EventCode": "0x70",
+        "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC",
         "PerPkg": "1",
-        "UMask": "0x81",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.ANY_ONE",
+        "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR",
+        "EventCode": "0x70",
+        "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR",
         "PerPkg": "1",
-        "UMask": "0xF1",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued : Multiple Snoop Targets from Remote",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.REMOTE_GTONE",
+        "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI",
+        "EventCode": "0x70",
+        "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI",
         "PerPkg": "1",
-        "UMask": "0x22",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued : Multiple External Snoops",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE",
+        "BriefDescription": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT",
+        "EventCode": "0x66",
+        "EventName": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT",
         "PerPkg": "1",
-        "UMask": "0x22",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued : Multiple Core Requests",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE",
+        "BriefDescription": "UNC_CHA_PMM_QOS.REJ_IRQ",
+        "EventCode": "0x66",
+        "EventName": "UNC_CHA_PMM_QOS.REJ_IRQ",
         "PerPkg": "1",
-        "UMask": "0x42",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued : Multiple Eviction",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE",
+        "BriefDescription": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP",
+        "EventCode": "0x66",
+        "EventName": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP",
         "PerPkg": "1",
-        "UMask": "0x82",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE",
+        "BriefDescription": "UNC_CHA_PMM_QOS.SLOW_INSERT",
+        "EventCode": "0x66",
+        "EventName": "UNC_CHA_PMM_QOS.SLOW_INSERT",
         "PerPkg": "1",
-        "UMask": "0xF2",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Direct GO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC",
+        "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE",
+        "EventCode": "0x66",
+        "EventName": "UNC_CHA_PMM_QOS.THROTTLE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Direct GO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C",
+        "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_IRQ",
+        "EventCode": "0x66",
+        "EventName": "UNC_CHA_PMM_QOS.THROTTLE_IRQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Direct GO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD",
+        "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_PRQ",
+        "EventCode": "0x66",
+        "EventName": "UNC_CHA_PMM_QOS.THROTTLE_PRQ",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Direct GO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP",
+        "BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO",
+        "EventCode": "0x67",
+        "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": ": count # of FAST TOR Request inserted to ha_tor_req_fifo",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Direct GO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_CHA_DIRECT_GO_OPC.PULL",
+        "BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO",
+        "EventCode": "0x67",
+        "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": ": count # of SLOW TOR Request inserted to ha_pmm_tor_req_fifo",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Direct GO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_CHA_DIRECT_GO_OPC.GO",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC0 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 0 only.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Direct GO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC1 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 1 only.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Direct GO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC10",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC10",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC10 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 10 only.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Direct GO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC11",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC11",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC11 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 11 only.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Direct GO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_CHA_DIRECT_GO_OPC.NOP",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC12",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC12",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC12 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 12 only.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Direct GO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC13",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC13",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC13 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 13 only.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket ownership read requests that hit in S state",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5F",
-        "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC2 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 2 only.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket WBMtoE requests",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5F",
-        "EventName": "UNC_CHA_HITME_HIT.WBMTOE",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC3 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 3 only.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket writeback to I or S requests",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5F",
-        "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC4",
         "PerPkg": "1",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC4 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 4 only.",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed : Remote socket read requests",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5E",
-        "EventName": "UNC_CHA_HITME_LOOKUP.READ",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC5",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC5 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 5 only.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed : Remote socket write (i.e. writeback) requests",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5E",
-        "EventName": "UNC_CHA_HITME_LOOKUP.WRITE",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC6",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC6",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC6 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 6 only.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests to shared line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x60",
-        "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC7",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC7",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC7 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 7 only.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests that are not to shared line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x60",
-        "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC8",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC8",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC8 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 8 only.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket read or invalidate requests",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x60",
-        "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC9",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC9",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC9 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 9 only.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x61",
-        "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
+        "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and remote INVITOE requests sent to the CHA's home agent",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.INVITOE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
+        "UMask": "0x30",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x61",
-        "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM",
+        "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and are sent to the CHA's home agent",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache to SHARed",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x61",
-        "EventName": "UNC_CHA_HITME_UPDATE.SHARED",
+        "BriefDescription": "Remote INVITOE requests (exclusive ownership of a cache line without receiving data) sent to the CHA's home agent",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache on RdInvOwn even if not RspFwdI*",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x61",
-        "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN",
+        "BriefDescription": "Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.READS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a  write) .",
+        "UMask": "0x3",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Deallocate HtiME$ on Reads without RspFwdI*",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x61",
-        "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE",
+        "BriefDescription": "Local read requests that miss the SF/LLC and are sent to the CHA's home agent",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.READS_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a  write).",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "HA to iMC Reads Issued : ISOCH",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x59",
-        "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY",
+        "BriefDescription": "Remote read requests sent to the CHA's home agent",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.READS_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a  write).",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5B",
-        "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
+        "BriefDescription": "Local write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.WRITES",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
+        "UMask": "0xc",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5B",
-        "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
+        "BriefDescription": "Local write requests that miss the SF/LLC and are sent to the CHA's home agent",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts  write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5B",
-        "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
+        "BriefDescription": "Remote write requests sent to the CHA's home agent",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized : Lines in M state",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
+        "EventCode": "0xAC",
+        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized : Lines in E state",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
+        "EventCode": "0xAC",
+        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized : Lines in S State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
+        "EventCode": "0xAC",
+        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized : Local Only",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
+        "EventCode": "0xAC",
+        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV",
         "PerPkg": "1",
-        "UMaskExt": "0x20",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized : Remote Only",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ONLY",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
+        "EventCode": "0xAA",
+        "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD",
         "PerPkg": "1",
-        "UMaskExt": "0x80",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized : Local - Lines in M State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
+        "EventCode": "0xAA",
+        "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x2001",
-        "UMaskExt": "0x20",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized : Local - Lines in E State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.",
+        "EventCode": "0xAA",
+        "EventName": "UNC_CHA_RING_BOUNCES_VERT.AKC",
         "PerPkg": "1",
-        "UMask": "0x2002",
-        "UMaskExt": "0x20",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized : Local - Lines in S State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
+        "EventCode": "0xAA",
+        "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x2004",
-        "UMaskExt": "0x20",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized : Remote - Lines in M State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
+        "EventCode": "0xAA",
+        "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x8001",
-        "UMaskExt": "0x80",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized : Remote - Lines in E State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
+        "EventCode": "0xAD",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x8002",
-        "UMaskExt": "0x80",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized : Remote - Lines in S State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
+        "EventCode": "0xAD",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x8004",
-        "UMaskExt": "0x80",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cbo Misc : Silent Snoop Eviction",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x39",
-        "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
+        "EventCode": "0xAD",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cbo Misc : Write Combining Aliasing",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x39",
-        "EventName": "UNC_CHA_MISC.WC_ALIASING",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
+        "EventCode": "0xAD",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cbo Misc : CV0 Prefetch Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x39",
-        "EventName": "UNC_CHA_MISC.CV0_PREF_VIC",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
+        "EventCode": "0xAD",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cbo Misc : CV0 Prefetch Miss",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x39",
-        "EventName": "UNC_CHA_MISC.CV0_PREF_MISS",
+        "BriefDescription": "Sink Starvation on Vertical Ring : AD",
+        "EventCode": "0xAB",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "OSB Snoop Broadcast : Local InvItoE",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_CHA_OSB.LOCAL_INVITOE",
+        "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
+        "EventCode": "0xAB",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "OSB Snoop Broadcast : Local Rd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_CHA_OSB.LOCAL_READ",
+        "BriefDescription": "Sink Starvation on Vertical Ring",
+        "EventCode": "0xAB",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AKC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "OSB Snoop Broadcast : Remote Rd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_CHA_OSB.REMOTE_READ",
+        "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
+        "EventCode": "0xAB",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "OSB Snoop Broadcast : Remote Rd InvItoE",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_CHA_OSB.REMOTE_READINVITOE",
+        "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
+        "EventCode": "0xAB",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_CHA_OSB.RFO_HITS_SNP_BCAST",
+        "BriefDescription": "Source Throttle",
+        "EventCode": "0xae",
+        "EventName": "UNC_CHA_RING_SRC_THRTL",
         "PerPkg": "1",
-        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "OSB Snoop Broadcast : Off",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_CHA_OSB.OFF_PWRHEURISTIC",
+        "BriefDescription": "Ingress (from CMS) Allocations : IPQ",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.IPQ",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Ingress (from CMS) Allocations : IPQ : Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.RMW_SETMATCH",
+        "BriefDescription": "Ingress (from CMS) Allocations : IRQ",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.IRQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Ingress (from CMS) Allocations : IRQ : Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_PAMATCH",
+        "BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Ingress (from CMS) Allocations : IRQ Rejected : Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLOWSNP",
+        "BriefDescription": "Ingress (from CMS) Allocations : PRQ",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.PRQ",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_WAYMATCH",
+        "BriefDescription": "Ingress (from CMS) Allocations : PRQ",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLWAYRSV",
+        "BriefDescription": "Ingress (from CMS) Allocations : RRQ",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.RRQ",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Ingress (from CMS) Allocations : RRQ : Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.PTL_INPIPE",
+        "BriefDescription": "Ingress (from CMS) Allocations : WBQ",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.WBQ",
         "PerPkg": "1",
+        "PublicDescription": "Ingress (from CMS) Allocations : WBQ : Counts number of allocations per cycle into the specified Ingress queue.",
         "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.IRQ_SETMATCH_VICP",
+        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
+        "EventCode": "0x22",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMaskExt": "0x01",
+        "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.FSF_VICP",
+        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
+        "EventCode": "0x22",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMaskExt": "0x02",
+        "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.ONE_FSF_VIC",
+        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
+        "EventCode": "0x22",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
-        "UMaskExt": "0x04",
+        "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.TORID_MATCH_GO_P",
+        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
+        "EventCode": "0x22",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
-        "UMaskExt": "0x10",
+        "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.IPQ_SETMATCH_VICP",
+        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
+        "EventCode": "0x22",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMaskExt": "0x20",
+        "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.WAY_MATCH",
+        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
+        "EventCode": "0x22",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMaskExt": "0x40",
+        "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.ONE_RSP_CON",
+        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
+        "EventCode": "0x22",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMaskExt": "0x80",
+        "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.IDX_INPIPE",
+        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
+        "EventCode": "0x22",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
-        "UMaskExt": "0x100",
+        "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.SETMATCHENTRYWSCT",
+        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
-        "UMaskExt": "0x200",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.ALLRSFWAYS_RES",
+        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : ANY0",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0",
         "PerPkg": "1",
-        "UMaskExt": "0x800",
+        "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IPQ0 Reject counter was true",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.RRQ_SETMATCH_VICP",
+        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : HA",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA",
         "PerPkg": "1",
-        "UMaskExt": "0x1000",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.ISMQ_SETMATCH_VICP",
+        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMaskExt": "0x2000",
+        "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.SF_WAYS_RES",
+        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM",
         "PerPkg": "1",
-        "UMaskExt": "0x4000",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.LLC_WAYS_RES",
+        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
-        "UMaskExt": "0x8000",
+        "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.NOTALLOWSNOOP",
+        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : SF Victim",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
-        "UMaskExt": "0x10000",
+        "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.TOPA_MATCH",
+        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Victim",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM",
         "PerPkg": "1",
-        "UMaskExt": "0x20000",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.IVEGRCREDIT",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMaskExt": "0x40000",
+        "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.BLEGRCREDIT",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMaskExt": "0x80000",
+        "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.ADEGRCREDIT",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
-        "UMaskExt": "0x100000",
+        "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.AKEGRCREDIT",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
-        "UMaskExt": "0x200000",
+        "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.HACREDIT",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMaskExt": "0x400000",
+        "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_REQ",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMaskExt": "0x800000",
+        "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_RSP",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMaskExt": "0x1000000",
+        "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_RSP",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
-        "UMaskExt": "0x2000000",
+        "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_WB",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
-        "UMaskExt": "0x4000000",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCB",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0",
         "PerPkg": "1",
-        "UMaskExt": "0x8000000",
+        "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IRQ0 Reject counter was true",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCS",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA",
         "PerPkg": "1",
-        "UMaskExt": "0x10000000",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC0",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way : Way conflict with another request that caused the reject",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC1",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC2",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC3",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC4",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Victim",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC5",
+        "BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC6",
+        "BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC7",
+        "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC8",
+        "BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
-        "UMaskExt": "0x01",
+        "PublicDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC9",
+        "BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMaskExt": "0x02",
+        "PublicDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC10",
+        "BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMaskExt": "0x04",
+        "PublicDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC11",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC11",
+        "BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMaskExt": "0x08",
+        "PublicDescription": "ISMQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC12",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC12",
+        "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
-        "UMaskExt": "0x10",
+        "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC13",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC13",
+        "BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMaskExt": "0x20",
+        "PublicDescription": "ISMQ Retries - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations : IRQ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.IRQ",
+        "BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "ISMQ Retries - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ",
+        "BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "ISMQ Retries - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations : IPQ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.IPQ",
+        "BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "ISMQ Retries - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations : PRQ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.PRQ",
+        "BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "ISMQ Retries - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations : PRQ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ",
+        "BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "ISMQ Retries - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations : RRQ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.RRQ",
+        "BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "ISMQ Retries - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations : WBQ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.WBQ",
+        "BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI",
         "PerPkg": "1",
+        "PublicDescription": "ISMQ Retries - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message",
         "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0",
+        "BriefDescription": "ISMQ Rejects - Set 1 : ANY0",
+        "EventCode": "0x25",
+        "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "ISMQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0",
+        "BriefDescription": "ISMQ Rejects - Set 1 : HA",
+        "EventCode": "0x25",
+        "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "ISMQ Rejects - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0",
+        "BriefDescription": "ISMQ Retries - Set 1 : ANY0",
+        "EventCode": "0x2D",
+        "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "ISMQ Retries - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0",
+        "BriefDescription": "ISMQ Retries - Set 1 : HA",
+        "EventCode": "0x2D",
+        "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "ISMQ Retries - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0",
+        "BriefDescription": "Ingress (from CMS) Occupancy : IPQ",
+        "EventCode": "0x11",
+        "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Ingress (from CMS) Occupancy : IPQ : Counts number of entries in the specified Ingress queue in each cycle.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0",
+        "BriefDescription": "Ingress (from CMS) Occupancy : IRQ",
+        "EventCode": "0x11",
+        "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Ingress (from CMS) Occupancy : IRQ : Counts number of entries in the specified Ingress queue in each cycle.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI",
+        "BriefDescription": "Ingress (from CMS) Occupancy : RRQ",
+        "EventCode": "0x11",
+        "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ",
         "PerPkg": "1",
+        "PublicDescription": "Ingress (from CMS) Occupancy : RRQ : Counts number of entries in the specified Ingress queue in each cycle.",
         "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI",
+        "BriefDescription": "Ingress (from CMS) Occupancy : WBQ",
+        "EventCode": "0x11",
+        "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ",
         "PerPkg": "1",
+        "PublicDescription": "Ingress (from CMS) Occupancy : WBQ : Counts number of entries in the specified Ingress queue in each cycle.",
         "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : ANY0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : HA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA",
+        "BriefDescription": "Other Retries - Set 0 : AD REQ on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Other Retries - Set 0 : AD REQ on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a request",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM",
+        "BriefDescription": "Other Retries - Set 0 : AD RSP on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Other Retries - Set 0 : AD RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a response",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : SF Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM",
+        "BriefDescription": "Other Retries - Set 0 : Non UPI AK Request",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Other Retries - Set 0 : Non UPI AK Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject AK ring message",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM",
+        "BriefDescription": "Other Retries - Set 0 : BL NCB on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
         "PerPkg": "1",
+        "PublicDescription": "Other Retries - Set 0 : BL NCB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCB",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
+        "BriefDescription": "Other Retries - Set 0 : BL NCS on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
         "PerPkg": "1",
+        "PublicDescription": "Other Retries - Set 0 : BL NCS on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCS",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP",
+        "BriefDescription": "Other Retries - Set 0 : BL RSP on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Other Retries - Set 0 : BL RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a response",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH",
+        "BriefDescription": "Other Retries - Set 0 : BL WB on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Other Retries - Set 0 : BL WB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a writeback",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
+        "BriefDescription": "Other Retries - Set 0 : Non UPI IV Request",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Other Retries - Set 0 : Non UPI IV Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject IV ring message",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
+        "BriefDescription": "Other Retries - Set 1 : Allow Snoop",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Other Retries - Set 1 : Allow Snoop : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
+        "BriefDescription": "Other Retries - Set 1 : ANY0",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Other Retries - Set 1 : ANY0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Any condition listed in the Other0 Reject counter was true",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
+        "BriefDescription": "Other Retries - Set 1 : HA",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Other Retries - Set 1 : HA : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
+        "BriefDescription": "Other Retries - Set 1 : LLC OR SF Way",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Other Retries - Set 1 : LLC OR SF Way : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Way conflict with another request that caused the reject",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
+        "BriefDescription": "Other Retries - Set 1 : LLC Victim",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Other Retries - Set 1 : LLC Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI",
+        "BriefDescription": "Other Retries - Set 1 : PhyAddr Match",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Other Retries - Set 1 : PhyAddr Match : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Address match with an outstanding request that was rejected.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI",
+        "BriefDescription": "Other Retries - Set 1 : SF Victim",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Other Retries - Set 1 : SF Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Requests did not generate Snoop filter victim",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0",
+        "BriefDescription": "Other Retries - Set 1 : Victim",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Other Retries - Set 1 : Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the PRQ0 Reject counter was true",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
         "PerPkg": "1",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected.",
         "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Victim",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
+        "BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Request Queue Retries - Set 0 : AD REQ on VN0 : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a request",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
+        "BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Request Queue Retries - Set 0 : AD RSP on VN0 : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a response",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
+        "BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Request",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI",
+        "PerPkg": "1",
+        "PublicDescription": "Request Queue Retries - Set 0 : Non UPI AK Request : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject AK ring message",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
         "PerPkg": "1",
+        "PublicDescription": "Request Queue Retries - Set 0 : BL NCB on VN0 : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCB",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
+        "BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
         "PerPkg": "1",
+        "PublicDescription": "Request Queue Retries - Set 0 : BL NCS on VN0 : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCS",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI",
+        "BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Request Queue Retries - Set 0 : BL RSP on VN0 : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a response",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI",
+        "BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Request Queue Retries - Set 0 : BL WB on VN0 : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a writeback",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects - Set 1 : ANY0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x25",
-        "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
+        "BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Request",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Request Queue Retries - Set 0 : Non UPI IV Request : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject IV ring message",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects - Set 1 : HA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x25",
-        "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA",
+        "BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Request Queue Retries - Set 1 : Allow Snoop : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries - Set 1 : ANY0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2D",
-        "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
+        "BriefDescription": "Request Queue Retries - Set 1 : ANY0",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Request Queue Retries - Set 1 : ANY0 : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Any condition listed in the WBQ0 Reject counter was true",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries - Set 1 : HA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2D",
-        "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA",
+        "BriefDescription": "Request Queue Retries - Set 1 : HA",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Request Queue Retries - Set 1 : HA : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Occupancy : IRQ",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ",
+        "BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Request Queue Retries - Set 1 : LLC OR SF Way : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Way conflict with another request that caused the reject",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Occupancy : IPQ",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ",
+        "BriefDescription": "Request Queue Retries - Set 1 : LLC Victim",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Request Queue Retries - Set 1 : LLC Victim : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Occupancy : RRQ",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ",
+        "BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Request Queue Retries - Set 1 : PhyAddr Match : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Address match with an outstanding request that was rejected.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Occupancy : WBQ",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ",
+        "BriefDescription": "Request Queue Retries - Set 1 : SF Victim",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Request Queue Retries - Set 1 : SF Victim : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Requests did not generate Snoop filter victim",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 0 : AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
+        "BriefDescription": "Request Queue Retries - Set 1 : Victim",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Request Queue Retries - Set 1 : Victim : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 0 : AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
+        "BriefDescription": "RRQ Rejects - Set 0 : AD REQ on VN0",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "RRQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No AD VN0 credit for generating a request",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 0 : BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
+        "BriefDescription": "RRQ Rejects - Set 0 : AD RSP on VN0",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "RRQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No AD VN0 credit for generating a response",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 0 : BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
+        "BriefDescription": "RRQ Rejects - Set 0 : Non UPI AK Request",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "RRQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Can't inject AK ring message",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 0 : BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
+        "BriefDescription": "RRQ Rejects - Set 0 : BL NCB on VN0",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
+        "PublicDescription": "RRQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for NCB",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 0 : BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
+        "BriefDescription": "RRQ Rejects - Set 0 : BL NCS on VN0",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
+        "PublicDescription": "RRQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for NCS",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 0 : Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI",
+        "BriefDescription": "RRQ Rejects - Set 0 : BL RSP on VN0",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "RRQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for generating a response",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 0 : Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI",
+        "BriefDescription": "RRQ Rejects - Set 0 : BL WB on VN0",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "RRQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for generating a writeback",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 1 : ANY0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0",
+        "BriefDescription": "RRQ Rejects - Set 0 : Non UPI IV Request",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "RRQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Can't inject IV ring message",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 1 : HA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA",
+        "BriefDescription": "RRQ Rejects - Set 1 : Allow Snoop",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "RRQ Rejects - Set 1 : Allow Snoop : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 1 : LLC Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
+        "BriefDescription": "RRQ Rejects - Set 1 : ANY0",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "RRQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Any condition listed in the RRQ0 Reject counter was true",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 1 : SF Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
+        "BriefDescription": "RRQ Rejects - Set 1 : HA",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "RRQ Rejects - Set 1 : HA : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 1 : Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
+        "BriefDescription": "RRQ Rejects - Set 1 : LLC OR SF Way",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "RRQ Rejects - Set 1 : LLC OR SF Way : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Way conflict with another request that caused the reject",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 1 : LLC OR SF Way",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
+        "BriefDescription": "RRQ Rejects - Set 1 : LLC Victim",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "RRQ Rejects - Set 1 : LLC Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 1 : Allow Snoop",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
+        "BriefDescription": "RRQ Rejects - Set 1 : PhyAddr Match",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "RRQ Rejects - Set 1 : PhyAddr Match : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Address match with an outstanding request that was rejected.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 1 : PhyAddr Match",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
+        "BriefDescription": "RRQ Rejects - Set 1 : SF Victim",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "RRQ Rejects - Set 1 : SF Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Requests did not generate Snoop filter victim",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
+        "BriefDescription": "RRQ Rejects - Set 1 : Victim",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "RRQ Rejects - Set 1 : Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
+        "BriefDescription": "WBQ Rejects - Set 0 : AD REQ on VN0",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "WBQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No AD VN0 credit for generating a request",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
+        "BriefDescription": "WBQ Rejects - Set 0 : AD RSP on VN0",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "WBQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No AD VN0 credit for generating a response",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
+        "BriefDescription": "WBQ Rejects - Set 0 : Non UPI AK Request",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "WBQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Can't inject AK ring message",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
+        "BriefDescription": "WBQ Rejects - Set 0 : BL NCB on VN0",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
+        "PublicDescription": "WBQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for NCB",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
+        "BriefDescription": "WBQ Rejects - Set 0 : BL NCS on VN0",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
+        "PublicDescription": "WBQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for NCS",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI",
+        "BriefDescription": "WBQ Rejects - Set 0 : BL RSP on VN0",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "WBQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for generating a response",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI",
+        "BriefDescription": "WBQ Rejects - Set 0 : BL WB on VN0",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "WBQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for generating a writeback",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0",
+        "BriefDescription": "WBQ Rejects - Set 0 : Non UPI IV Request",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "WBQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Can't inject IV ring message",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA",
+        "BriefDescription": "WBQ Rejects - Set 1 : Allow Snoop",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "WBQ Rejects - Set 1 : Allow Snoop : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
+        "BriefDescription": "WBQ Rejects - Set 1 : ANY0",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "WBQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Any condition listed in the WBQ0 Reject counter was true",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
+        "BriefDescription": "WBQ Rejects - Set 1 : HA",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "WBQ Rejects - Set 1 : HA : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
+        "BriefDescription": "WBQ Rejects - Set 1 : LLC OR SF Way",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
         "PerPkg": "1",
+        "PublicDescription": "WBQ Rejects - Set 1 : LLC OR SF Way : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Way conflict with another request that caused the reject",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
+        "BriefDescription": "WBQ Rejects - Set 1 : LLC Victim",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "WBQ Rejects - Set 1 : LLC Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
+        "BriefDescription": "WBQ Rejects - Set 1 : PhyAddr Match",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
+        "PublicDescription": "WBQ Rejects - Set 1 : PhyAddr Match : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Address match with an outstanding request that was rejected.",
         "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
+        "BriefDescription": "WBQ Rejects - Set 1 : SF Victim",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "WBQ Rejects - Set 1 : SF Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Requests did not generate Snoop filter victim",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
+        "BriefDescription": "WBQ Rejects - Set 1 : Victim",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "WBQ Rejects - Set 1 : Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
+        "BriefDescription": "Transgress Injection Starvation : AD - All",
+        "EventCode": "0xE5",
+        "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
+        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+        "EventCode": "0xE5",
+        "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
+        "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+        "EventCode": "0xE5",
+        "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
+        "BriefDescription": "Transgress Injection Starvation : BL - All",
+        "EventCode": "0xE5",
+        "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI",
+        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
+        "EventCode": "0xE5",
+        "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
         "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI",
+        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+        "EventCode": "0xE5",
+        "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 1 : ANY0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
+        "BriefDescription": "Transgress Ingress Bypass : AD - All",
+        "EventCode": "0xE2",
+        "EventName": "UNC_CHA_RxR_BYPASS.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 1 : HA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA",
+        "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
+        "EventCode": "0xE2",
+        "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 1 : LLC Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
+        "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
+        "EventCode": "0xE2",
+        "EventName": "UNC_CHA_RxR_BYPASS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 1 : SF Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
+        "BriefDescription": "Transgress Ingress Bypass : AK",
+        "EventCode": "0xE2",
+        "EventName": "UNC_CHA_RxR_BYPASS.AK",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 1 : Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
+        "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
+        "EventCode": "0xE2",
+        "EventName": "UNC_CHA_RxR_BYPASS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
+        "BriefDescription": "Transgress Ingress Bypass : BL - All",
+        "EventCode": "0xE2",
+        "EventName": "UNC_CHA_RxR_BYPASS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
+        "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
+        "EventCode": "0xE2",
+        "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
         "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
+        "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
+        "EventCode": "0xE2",
+        "EventName": "UNC_CHA_RxR_BYPASS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects - Set 0 : AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0",
+        "BriefDescription": "Transgress Ingress Bypass : IV",
+        "EventCode": "0xE2",
+        "EventName": "UNC_CHA_RxR_BYPASS.IV",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects - Set 0 : AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0",
+        "BriefDescription": "Transgress Injection Starvation : AD - All",
+        "EventCode": "0xE3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects - Set 0 : BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0",
+        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+        "EventCode": "0xE3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects - Set 0 : BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0",
+        "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+        "EventCode": "0xE3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects - Set 0 : BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0",
+        "BriefDescription": "Transgress Injection Starvation : AK",
+        "EventCode": "0xE3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.AK",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects - Set 0 : BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0",
+        "BriefDescription": "Transgress Injection Starvation : BL - All",
+        "EventCode": "0xE3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects - Set 0 : Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI",
+        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
+        "EventCode": "0xE3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
         "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects - Set 0 : Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI",
+        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+        "EventCode": "0xE3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects - Set 1 : ANY0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0",
+        "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
+        "EventCode": "0xE3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects - Set 1 : HA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA",
+        "BriefDescription": "Transgress Injection Starvation : IV",
+        "EventCode": "0xE3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.IV",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects - Set 1 : LLC Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM",
+        "BriefDescription": "Transgress Injection Starvation",
+        "EventCode": "0xe4",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED_1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects - Set 1 : SF Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM",
+        "BriefDescription": "Transgress Ingress Allocations : AD - All",
+        "EventCode": "0xE1",
+        "EventName": "UNC_CHA_RxR_INSERTS.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects - Set 1 : Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM",
+        "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
+        "EventCode": "0xE1",
+        "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects - Set 1 : LLC OR SF Way",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
+        "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
+        "EventCode": "0xE1",
+        "EventName": "UNC_CHA_RxR_INSERTS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects - Set 1 : Allow Snoop",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP",
+        "BriefDescription": "Transgress Ingress Allocations : AK",
+        "EventCode": "0xE1",
+        "EventName": "UNC_CHA_RxR_INSERTS.AK",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects - Set 1 : PhyAddr Match",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH",
+        "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
+        "EventCode": "0xE1",
+        "EventName": "UNC_CHA_RxR_INSERTS.AKC_UNCRD",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
         "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects - Set 0 : AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0",
+        "BriefDescription": "Transgress Ingress Allocations : BL - All",
+        "EventCode": "0xE1",
+        "EventName": "UNC_CHA_RxR_INSERTS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects - Set 0 : AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0",
+        "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
+        "EventCode": "0xE1",
+        "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects - Set 0 : BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0",
-        "PerPkg": "1",
-        "UMask": "0x04",
+        "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
+        "EventCode": "0xE1",
+        "EventName": "UNC_CHA_RxR_INSERTS.BL_UNCRD",
+        "PerPkg": "1",
+        "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects - Set 0 : BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0",
+        "BriefDescription": "Transgress Ingress Allocations : IV",
+        "EventCode": "0xE1",
+        "EventName": "UNC_CHA_RxR_INSERTS.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects - Set 0 : BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0",
+        "BriefDescription": "Transgress Ingress Occupancy : AD - All",
+        "EventCode": "0xE0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects - Set 0 : BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0",
+        "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
+        "EventCode": "0xE0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects - Set 0 : Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI",
+        "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
+        "EventCode": "0xE0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects - Set 0 : Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI",
+        "BriefDescription": "Transgress Ingress Occupancy : AK",
+        "EventCode": "0xE0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.AK",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects - Set 1 : ANY0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0",
+        "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
+        "EventCode": "0xE0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects - Set 1 : HA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA",
+        "BriefDescription": "Transgress Ingress Occupancy : BL - All",
+        "EventCode": "0xE0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects - Set 1 : LLC Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM",
+        "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
+        "EventCode": "0xE0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects - Set 1 : SF Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM",
+        "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
+        "EventCode": "0xE0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects - Set 1 : Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM",
+        "BriefDescription": "Transgress Ingress Occupancy : IV",
+        "EventCode": "0xE0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.IV",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects - Set 1 : LLC OR SF Way",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
+        "BriefDescription": "Snoop filter capacity evictions for E-state entries.",
+        "EventCode": "0x3D",
+        "EventName": "UNC_CHA_SF_EVICTION.E_STATE",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects - Set 1 : Allow Snoop",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP",
+        "BriefDescription": "Snoop filter capacity evictions for M-state entries.",
+        "EventCode": "0x3D",
+        "EventName": "UNC_CHA_SF_EVICTION.M_STATE",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects - Set 1 : PhyAddr Match",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH",
+        "BriefDescription": "Snoop filter capacity evictions for S-state entries.",
+        "EventCode": "0x3D",
+        "EventName": "UNC_CHA_SF_EVICTION.S_STATE",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Counts snoop filter capacity evictions for entries tracking shared lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Snoops Sent : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x51",
         "EventName": "UNC_CHA_SNOOPS_SENT.ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Snoops Sent : Snoops sent for Local Requests",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x51",
-        "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL",
-        "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Snoops Sent : Snoops sent for Remote Requests",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x51",
-        "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE",
-        "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Snoops Sent : All : Counts the number of snoops issued by the HA.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Snoops Sent : Broadcast snoops for Local Requests",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x51",
         "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
         "PerPkg": "1",
+        "PublicDescription": "Snoops Sent : Broadcast snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA responding to local requests",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Snoops Sent : Broadcast snoops for Remote Requests",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x51",
         "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE",
         "PerPkg": "1",
+        "PublicDescription": "Snoops Sent : Broadcast snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA responding to remote requests",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Snoops Sent : Directed snoops for Local Requests",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x51",
         "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
         "PerPkg": "1",
+        "PublicDescription": "Snoops Sent : Directed snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA responding to local requests",
         "UMask": "0x40",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Snoops Sent : Directed snoops for Remote Requests",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x51",
         "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE",
         "PerPkg": "1",
+        "PublicDescription": "Snoops Sent : Directed snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA responding to remote requests",
         "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received : Rsp*WB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5C",
-        "EventName": "UNC_CHA_SNOOP_RESP.RSPWB",
+        "BriefDescription": "Snoops Sent : Snoops sent for Local Requests",
+        "EventCode": "0x51",
+        "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Snoops Sent : Snoops sent for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA responding to local requests",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received : Rsp*Fwd*WB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5C",
-        "EventName": "UNC_CHA_SNOOP_RESP.RSPFWDWB",
+        "BriefDescription": "Snoops Sent : Snoops sent for Remote Requests",
+        "EventCode": "0x51",
+        "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Snoops Sent : Snoops sent for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA responding to remote requests",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Snoop Responses Received : RSPCNFLCT*",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x5C",
         "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCT",
         "PerPkg": "1",
+        "PublicDescription": "Snoop Responses Received : RSPCNFLCT* : Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for snoops responses of RspConflict.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI.",
         "UMask": "0x40",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Snoop Responses Received : RspFwd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x5C",
         "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD",
         "PerPkg": "1",
+        "PublicDescription": "Snoop Responses Received : RspFwd : Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of RspFwd to a CA request.  This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.",
         "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local : RspI",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
+        "BriefDescription": "Snoop Responses Received : Rsp*Fwd*WB",
+        "EventCode": "0x5C",
+        "EventName": "UNC_CHA_SNOOP_RESP.RSPFWDWB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Snoop Responses Received : Rsp*Fwd*WB : Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of Rsp*Fwd*WB.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local : RspS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
+        "BriefDescription": "Snoop Responses Received : RspI",
+        "EventCode": "0x5C",
+        "EventName": "UNC_CHA_SNOOP_RESP.RSPI",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data).",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local : RspIFwd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
+        "BriefDescription": "Snoop Responses Received : RspIFwd",
+        "EventCode": "0x5C",
+        "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states.  This is commonly returned with RFO (the Read for Ownership issued before a write) transactions.  The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward)  states.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local : RspSFwd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
+        "BriefDescription": "Snoop Responses Received : RspS",
+        "EventCode": "0x5C",
+        "EventName": "UNC_CHA_SNOOP_RESP.RSPS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts when a transaction with the opcode type RspS Snoop Response was received which indicates when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local : Rsp*WB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB",
+        "BriefDescription": "Snoop Responses Received : RspSFwd",
+        "EventCode": "0x5C",
+        "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy.  This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB",
+        "BriefDescription": "Snoop Responses Received : Rsp*WB",
+        "EventCode": "0x5C",
+        "EventName": "UNC_CHA_SNOOP_RESP.RSPWB",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Snoop Responses Received : Rsp*WB : Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of RspIWB or RspSWB.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Snoop Responses Received Local : RspCnflct",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x5D",
         "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
         "PerPkg": "1",
+        "PublicDescription": "Snoop Responses Received Local : RspCnflct : Number of snoop responses received for a Local  request : Filters for snoops responses of RspConflict to local CA requests.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI.",
         "UMask": "0x40",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Snoop Responses Received Local : RspFwd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x5D",
         "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
         "PerPkg": "1",
+        "PublicDescription": "Snoop Responses Received Local : RspFwd : Number of snoop responses received for a Local  request : Filters for a snoop response of RspFwd to local CA requests.  This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.",
         "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6B",
-        "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM",
+        "BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Snoop Responses Received Local : Rsp*FWD*WB : Number of snoop responses received for a Local  request : Filters for a snoop response of Rsp*Fwd*WB to local CA requests.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Misc Snoop Responses Received : MtoI RspIDataM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6B",
-        "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM",
+        "BriefDescription": "Snoop Responses Received Local : RspI",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Snoop Responses Received Local : RspI : Number of snoop responses received for a Local  request : Filters for snoops responses of RspI to local CA requests.  RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit SF",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6B",
-        "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF",
+        "BriefDescription": "Snoop Responses Received Local : RspIFwd",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Snoop Responses Received Local : RspIFwd : Number of snoop responses received for a Local  request : Filters for snoop responses of RspIFwd to local CA requests.  This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states.  This is commonly returned with RFO transactions.  It can be either a HitM or a HitFE.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6B",
-        "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC",
+        "BriefDescription": "Snoop Responses Received Local : RspS",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Snoop Responses Received Local : RspS : Number of snoop responses received for a Local  request : Filters for snoop responses of RspS to local CA requests.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit SF",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6B",
-        "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF",
+        "BriefDescription": "Snoop Responses Received Local : RspSFwd",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
+        "PerPkg": "1",
+        "PublicDescription": "Snoop Responses Received Local : RspSFwd : Number of snoop responses received for a Local  request : Filters for a snoop response of RspSFwd to local CA requests.  This is returned when a remote caching agent forwards data but holds on to its currently copy.  This is common for data and code reads that hit in a remote socket in E or F state.",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "Snoop Responses Received Local : Rsp*WB",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB",
         "PerPkg": "1",
+        "PublicDescription": "Snoop Responses Received Local : Rsp*WB : Number of snoop responses received for a Local  request : Filters for a snoop response of RspIWB or RspSWB to local CA requests.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership.",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Misc Snoop Responses Received : MtoI RspIDataM",
         "EventCode": "0x6B",
-        "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC",
+        "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WbPushMtoI : Pushed to LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x56",
-        "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC",
+        "BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM",
+        "EventCode": "0x6B",
+        "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WbPushMtoI : Pushed to Memory",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x56",
-        "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM",
+        "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit LLC",
+        "EventCode": "0x6B",
+        "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0",
+        "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit SF",
+        "EventCode": "0x6B",
+        "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1",
+        "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit LLC",
+        "EventCode": "0x6B",
+        "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2",
+        "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit SF",
+        "EventCode": "0x6B",
+        "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC6",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC7",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC8",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
         "PerPkg": "1",
-        "UMaskExt": "0x01",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC9",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
         "PerPkg": "1",
-        "UMaskExt": "0x02",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC10",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
         "PerPkg": "1",
-        "UMaskExt": "0x04",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC11",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC11",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
         "PerPkg": "1",
-        "UMaskExt": "0x08",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC12",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC12",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
         "PerPkg": "1",
-        "UMaskExt": "0x10",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC13",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC13",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
         "PerPkg": "1",
-        "UMaskExt": "0x20",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "XPT Prefetches : Sent (on 0?)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6f",
-        "EventName": "UNC_CHA_XPT_PREF.SENT0",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6f",
-        "EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6f",
-        "EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "XPT Prefetches : Sent (on 1?)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6f",
-        "EventName": "UNC_CHA_XPT_PREF.SENT1",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6f",
-        "EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6f",
-        "EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
         "PerPkg": "1",
-        "PortMask": "0x08",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x10",
-        "Unit": "IIO"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART7",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
+        "EventCode": "0xD1",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
+        "EventCode": "0xD1",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
+        "EventCode": "0xD1",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
+        "EventCode": "0xD3",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
+        "EventCode": "0xD3",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
+        "EventCode": "0xD3",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
+        "EventCode": "0xD5",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
+        "EventCode": "0xD5",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
+        "EventCode": "0xD5",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
+        "EventCode": "0xD7",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
+        "EventCode": "0xD7",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
+        "EventCode": "0xD7",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : All",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.ALL",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : All : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001ffff",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DDR4 Access",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.DDR",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DDR4 Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.DDR",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.DDR4",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : SF/LLC Evictions",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.EVICT",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : SF/LLC Evictions : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : Just Hits",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.HIT",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : Just Hits : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : All requests from iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : All requests from iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : CLFlushes issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8c7ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : CLFlushOpts issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : CLFlushOpts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8d7ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : CRDs issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : CRDs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc80fff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; CRd Pref from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc88fff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRds issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRds issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc817ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART6",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE",
+        "PerPkg": "1",
+        "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc837ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc827ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8a7ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc897ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc80ffd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc88ffd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc817fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to page walks that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc837fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc827fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8a7fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc897fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc47fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcccffd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCRD",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "UMask": "0xcccffd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xccd7fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDRD",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "UMask": "0xccd7fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xccc7fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Messages",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc807fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Messages",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc887fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Messages",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores that hit in the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_SPECITOM",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc57fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Messages",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc47ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Messages",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcd47ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Messages",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x40",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested of the CPU : Messages",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART6",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x40",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested of the CPU : Messages",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART7",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x40",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": IOTLB lookups first",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": IOTLB lookups all",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS",
-        "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": IOTLB Hits to a 4K Page",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_IIO_IOMMU0.4K_HITS",
-        "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": IOTLB Hits to a 2M Page",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_IIO_IOMMU0.2M_HITS",
-        "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": IOTLB Hits to a 1G Page",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_IIO_IOMMU0.1G_HITS",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": IOTLB Fills (same as IOTLB miss)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_IIO_IOMMU0.MISSES",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": Context cache lookups",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS",
-        "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": Context cache hits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS",
-        "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": PageWalk cache lookup",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": IOMMU memory access",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES",
-        "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": Cycles PWT full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_IOMMU1.CYC_PWT_FULL",
-        "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": Interrupt Entry cache lookup",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS",
-        "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": Interrupt Entry cache hit",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS",
-        "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "AND Mask/match for debug bus : PCIE bus",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1",
-        "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1",
-        "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1",
-        "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "OR Mask/match for debug bus : PCIE bus",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1",
-        "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1",
-        "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1",
-        "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number requests PCIe makes of the main die : Drop request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_IIO_NUM_REQ_OF_CPU.ALL.DROP",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x02",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x02",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x02",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x02",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x02",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x02",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x02",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x02",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x02",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x08",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x08",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x08",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x08",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART4",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x08",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART5",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x08",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART6",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x08",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART7",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x08",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x10",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x10",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x10",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x10",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART4",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x10",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART5",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x10",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART6",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x10",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART7",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x10",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x20",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x20",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x20",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x20",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART4",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x20",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART5",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x20",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART6",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x20",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART7",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x20",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x40",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcccfff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xccd7ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xccc7ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc80ffe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc80efe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc88ffe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc88efe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc88f7e01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc80f7e01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc817fe01",
+        "Unit": "CHA"
     },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART4",
-        "FCMask": "0x07",
+    {
+        "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc837fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8178601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc816fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8168601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8168a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc827fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8a7fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8178a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc897fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_DDR",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8978601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; DRd Pref misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts; Data read prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc896fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_DDR",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8968601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_PMM",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8968a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_PMM",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8978a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; DRd Pref misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts; Data read prefetch from remote IA that misses in the snoop filter",
+        "UMask": "0xc8977e01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_DDR",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8970601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_PMM",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8970a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8177e01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8170601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8170a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc867fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_DDR",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc8678601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_DRAM",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "UMask": "0xc8678601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_DDR",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc8668601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_DRAM",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "UMask": "0xc8668601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_PMM",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc8668a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_PMM",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc8678a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_DDR",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc8670601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_DRAM",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "UMask": "0xc8670601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_PMM",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc8670a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc47fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcccffe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xccd7fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xccc7fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8668601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8668a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Total Write Cache Occupancy : Any Source",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0F",
-        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
+        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86e8601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Total Write Cache Occupancy : Snoops",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0F",
-        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q",
+        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86e8a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Coherent Ops : CLFlush",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
+        "BriefDescription": "TOR Inserts; WCiL misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc86ffe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS",
+        "BriefDescription": "TOR Inserts; WCiL misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_DDR",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc86f8601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_I_IRP_ALL.EVICTS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_DRAM",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "IRP"
+        "UMask": "0xc86f8601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1e",
-        "EventName": "UNC_I_MISC0.FAST_REQ",
+        "BriefDescription": "TOR Inserts; WCiL misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc86e8601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1E",
-        "EventName": "UNC_I_MISC0.FAST_REJ",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DRAM",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IRP"
+        "UMask": "0xc86e8601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1e",
-        "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
+        "BriefDescription": "TOR Inserts; WCiL misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc86e8a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1e",
-        "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
+        "BriefDescription": "TOR Inserts; WCiL misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_PMM",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc86f8a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1E",
-        "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
+        "BriefDescription": "TOR Inserts; WCiL misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc86f0601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1E",
-        "EventName": "UNC_I_MISC0.FAST_XFER",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DRAM",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IRP"
+        "UMask": "0xc86f0601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1E",
-        "EventName": "UNC_I_MISC0.PF_ACK_HINT",
+        "BriefDescription": "TOR Inserts; WCiL misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc86f0a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1E",
-        "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF",
+        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR",
+        "PerPkg": "1",
+        "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8670601",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remote memory",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8670a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1f",
-        "EventName": "UNC_I_MISC1.SLOW_I",
+        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86f0601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1f",
-        "EventName": "UNC_I_MISC1.SLOW_S",
+        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86f0a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1f",
-        "EventName": "UNC_I_MISC1.SLOW_E",
+        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc807fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1f",
-        "EventName": "UNC_I_MISC1.SLOW_M",
+        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc806fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Misc Events - Set 1 : Received Invalid",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1F",
-        "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
+        "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc887fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Misc Events - Set 1 : Received Valid",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1F",
-        "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
+        "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc886fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "P2P Transactions : P2P reads",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.RD",
+        "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8877e01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "P2P Transactions : P2P Writes",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.WR",
+        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8077e01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "P2P Transactions : P2P Message",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.MSG",
+        "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_SPECITOM",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc57fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "P2P Transactions : P2P completions",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL",
+        "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc877de01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "P2P Transactions : Match if remote only",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.REM",
+        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86ffe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "P2P Transactions : match if remote and target matches",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH",
+        "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc867fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "P2P Transactions : match if local only",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.LOC",
+        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8678601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "P2P Transactions : match if local and target matches",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH",
+        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8678a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses : Miss",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.MISS",
+        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86f8601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses : Hit I",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.HIT_I",
+        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86f8a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses : Hit E or S",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
+        "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc87fde01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses : SnpCode",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
+        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts : RFOs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc807ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses : SnpData",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
+        "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc887ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses : SnpInv",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.SNPINV",
+        "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc57ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Inbound Transaction Count : Writes",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_I_TRANSACTIONS.WRITES",
+        "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core.  Non Modified Write Backs",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IRP"
+        "PublicDescription": "WbEFtoEs issued by iA Cores .  (Non Modified Write Backs)  :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.  Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc3fff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Inbound Transaction Count : Atomic",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
+        "BriefDescription": "TOR Inserts : WBEFtoIs issued by an IA Core.  Non Modified Write Backs",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IRP"
+        "PublicDescription": "WbEFtoIs issued by iA Cores .  (Non Modified Write Backs)  :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.  Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc37ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Inbound Transaction Count : Other",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_I_TRANSACTIONS.OTHER",
+        "BriefDescription": "TOR Inserts : WBMtoEs issued by an IA Core.  Non Modified Write Backs",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IRP"
+        "PublicDescription": "WbMtoEs issued by iA Cores .  (Non Modified Write Backs)  :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.  Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc2fff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Inbound Transaction Count : Select Source",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ",
+        "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "IRP"
+        "PublicDescription": "WbMtoIs issued by iA Cores .  (Modified Write Backs)  :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.  Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc27ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M to iMC Bypass : Taken",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x22",
-        "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.TAKEN",
+        "BriefDescription": "TOR Inserts : WBStoIs issued by an IA Core.  Non Modified Write Backs",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "WbStoIs issued by iA Cores .  (Non Modified Write Backs)  :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.  Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc67ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M to iMC Bypass : Taken",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN",
+        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86fff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M to iMC Bypass : Not Taken",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN",
+        "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc867ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Hit : On Dirty Line in I State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I",
+        "BriefDescription": "TOR Inserts : All requests from IO Devices",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : All requests from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Hit : On Dirty Line in S State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S",
+        "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : CLFlushes issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8c3ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Hit : On Dirty Line in L State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P",
+        "BriefDescription": "TOR Inserts : All requests from IO Devices that hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : All requests from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fd04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Hit : On Dirty Line in A State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A",
+        "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc43fd04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Hit : On NonDirty Line in I State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I",
+        "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcd43fd04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Hit : On NonDirty Line in S State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S",
+        "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8f3fd04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Hit : On NonDirty Line in L State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P",
+        "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc803fd04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Hit : On NonDirty Line in A State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A",
+        "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc43ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Miss : On Dirty Line in I State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I",
+        "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcd43ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Miss : On Dirty Line in S State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S",
+        "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to locally HOMed memory",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcd42ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Miss : On Dirty Line in L State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P",
+        "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to remotely HOMed memory",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcd437f04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Miss : On Dirty Line in A State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A",
+        "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to locally HOMed memory",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc42ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Miss : On NonDirty Line in I State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I",
+        "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to remotely HOMed memory",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc437f04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Miss : On NonDirty Line in S State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S",
+        "BriefDescription": "TOR Inserts : All requests from IO Devices that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : All requests from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fe04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Miss : On NonDirty Line in L State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P",
+        "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc43fe04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Directory Miss : On NonDirty Line in A State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A",
+        "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcd43fe04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL",
+        "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR",
         "PerPkg": "1",
-        "UMask": "0x0101",
-        "UMaskExt": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8f3fe04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH",
+        "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
         "PerPkg": "1",
-        "UMask": "0x0102",
-        "UMaskExt": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc803fe04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.CH0_ALL",
+        "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR",
         "PerPkg": "1",
-        "UMask": "0x0104",
-        "UMaskExt": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8f3ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR",
+        "BriefDescription": "TOR Inserts : RFOs issued by IO Devices",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO",
         "PerPkg": "1",
-        "UMask": "0x0140",
-        "UMaskExt": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc803ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL",
+        "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI",
         "PerPkg": "1",
-        "UMask": "0x0201",
-        "UMaskExt": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : WbMtoIs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc23ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH",
+        "BriefDescription": "TOR Inserts : IPQ",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IPQ",
         "PerPkg": "1",
-        "UMask": "0x0202",
-        "UMaskExt": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : IPQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.CH1_ALL",
+        "BriefDescription": "TOR Inserts : IRQ - iA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA",
         "PerPkg": "1",
-        "UMask": "0x0204",
-        "UMaskExt": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : IRQ - iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts. : From an iA Core",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR",
+        "BriefDescription": "TOR Inserts : IRQ - Non iA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA",
         "PerPkg": "1",
-        "UMask": "0x0240",
-        "UMaskExt": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : IRQ - Non iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.CH2_FROM_TGR",
+        "BriefDescription": "TOR Inserts : Just ISOC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.ISOC",
         "PerPkg": "1",
-        "UMask": "0x0440",
-        "UMaskExt": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : Just ISOC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL",
+        "BriefDescription": "TOR Inserts : Just Local Targets",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT",
         "PerPkg": "1",
-        "UMask": "0x0401",
-        "UMaskExt": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : Just Local Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL",
+        "BriefDescription": "TOR Inserts : All from Local iA and IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
         "PerPkg": "1",
-        "UMask": "0x0402",
-        "UMaskExt": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : All from Local iA and IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts. : All locally initiated requests",
+        "UMask": "0xc000ff05",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH",
+        "BriefDescription": "TOR Inserts : All from Local iA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA",
         "PerPkg": "1",
-        "UMask": "0x0404",
-        "UMaskExt": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : All from Local iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores",
+        "UMask": "0xc000ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH",
+        "BriefDescription": "TOR Inserts : All from Local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO",
         "PerPkg": "1",
-        "UMask": "0x0408",
-        "UMaskExt": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : All from Local IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic",
+        "UMask": "0xc000ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL",
+        "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC",
         "PerPkg": "1",
-        "UMask": "0x0410",
-        "UMaskExt": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR",
+        "BriefDescription": "TOR Inserts : Just Misses",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.MISS",
         "PerPkg": "1",
-        "UMaskExt": "0x05",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : Just Misses : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH0_NI",
+        "BriefDescription": "TOR Inserts : MMCFG Access",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.MMCFG",
         "PerPkg": "1",
-        "UMaskExt": "0x06",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : MMCFG Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL",
+        "BriefDescription": "TOR Inserts : Just NearMem",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.NEARMEM",
         "PerPkg": "1",
-        "UMask": "0x0801",
-        "UMaskExt": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : Just NearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL",
+        "BriefDescription": "TOR Inserts : Just NonCoherent",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.NONCOH",
         "PerPkg": "1",
-        "UMask": "0x0802",
-        "UMaskExt": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : Just NonCoherent : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH",
+        "BriefDescription": "TOR Inserts : Just NotNearMem",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM",
         "PerPkg": "1",
-        "UMask": "0x0804",
-        "UMaskExt": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : Just NotNearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH",
+        "BriefDescription": "TOR Inserts : PMM Access",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.PMM",
         "PerPkg": "1",
-        "UMask": "0x0808",
-        "UMaskExt": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : PMM Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL",
+        "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC",
         "PerPkg": "1",
-        "UMask": "0x0810",
-        "UMaskExt": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR",
+        "BriefDescription": "TOR Inserts : PRQ - IOSF",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF",
         "PerPkg": "1",
-        "UMaskExt": "0x09",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : PRQ - IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts. : From a PCIe Device",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH1_NI",
+        "BriefDescription": "TOR Inserts : PRQ - Non IOSF",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF",
         "PerPkg": "1",
-        "UMaskExt": "0x0A",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : PRQ - Non IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Packet Header Matches : Mesh Match",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M2M_PKT_MATCH.MESH",
+        "BriefDescription": "TOR Inserts : Just Remote Targets",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.REMOTE_TGT",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : Just Remote Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Packet Header Matches : MC Match",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M2M_PKT_MATCH.MC",
+        "BriefDescription": "TOR Inserts : RRQ",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.RRQ",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : RRQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH0",
+        "BriefDescription": "TOR Inserts : WBQ",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.WBQ",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts : WBQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH1",
+        "BriefDescription": "TOR Occupancy : DDR4 Access",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DDR4 Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH2",
+        "BriefDescription": "TOR Occupancy : SF/LLC Evictions",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : SF/LLC Evictions : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH0",
+        "BriefDescription": "TOR Occupancy : Just Hits",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : Just Hits : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH1",
+        "BriefDescription": "TOR Occupancy : All requests from iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH2",
+        "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8c7ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Cycles Full : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M2M_TRACKER_FULL.CH0",
+        "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8d7ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Cycles Full : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M2M_TRACKER_FULL.CH1",
+        "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : CRDs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc80fff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Cycles Full : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M2M_TRACKER_FULL.CH2",
+        "BriefDescription": "TOR Occupancy; CRd Pref from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc88fff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Inserts : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x49",
-        "EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
+        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRds issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc817ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Inserts : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x49",
-        "EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
+        "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc837ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Inserts : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x49",
-        "EventName": "UNC_M2M_TRACKER_INSERTS.CH2",
+        "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc827ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Cycles Not Empty : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2M_TRACKER_NE.CH0",
+        "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8a7ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Cycles Not Empty : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2M_TRACKER_NE.CH1",
+        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc897ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Cycles Not Empty : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2M_TRACKER_NE.CH2",
+        "BriefDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Occupancy : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
+        "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc80ffd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Occupancy : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
+        "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc88ffd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Occupancy : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2",
+        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc817fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Outbound Ring Transactions on AK : NDR Transactions",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x39",
-        "EventName": "UNC_M2M_TxC_AK.NDR",
+        "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc837fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Outbound Ring Transactions on AK : CRD Transactions to Cbo",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x39",
-        "EventName": "UNC_M2M_TxC_AK.CRD_CBO",
+        "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc827fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0",
+        "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8a7fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1",
+        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF",
+        "PerPkg": "1",
+        "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc897fd01",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc47fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0",
+        "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcccffd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1",
+        "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xccd7fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0",
+        "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xccc7fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0",
+        "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc807fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0",
+        "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc887fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1",
+        "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM",
         "PerPkg": "1",
-        "UMask": "0x88",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc47ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1",
+        "BriefDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR",
         "PerPkg": "1",
-        "UMask": "0x90",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcd47ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1",
+        "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE",
         "PerPkg": "1",
-        "UMask": "0xA0",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcccfff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL",
+        "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xccd7ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0",
+        "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xccc7ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1",
+        "BriefDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD",
+        "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc80ffe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD",
+        "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc80efe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP",
+        "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc88ffe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL",
+        "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc88efe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0",
+        "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc88f7e01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1",
+        "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc80f7e01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD",
+        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc817fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD",
+        "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc837fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP",
+        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8178601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT",
+        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc816fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL",
+        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8168601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1F",
-        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0",
+        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8168a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1F",
-        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1",
+        "BriefDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc827fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0",
+        "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8a7fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1",
+        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8178a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0",
+        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc897fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1",
+        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_DDR",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8978601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD",
+        "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc896fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD",
+        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_DDR",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8968601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP",
+        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_PMM",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8968a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL",
+        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_PMM",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8978a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Cache",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2M_TxC_BL.DRS_CACHE",
+        "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc8977e01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2M_TxC_BL.DRS_CORE",
+        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_DDR",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8970601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to QPI",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2M_TxC_BL.DRS_UPI",
+        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_PMM",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8970a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0",
+        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8177e01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1",
+        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8170601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0",
+        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8170a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1",
+        "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc867fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Full : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL",
+        "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_DDR",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc8678601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x17",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0",
+        "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_LOCAL_DDR",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc8668601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x17",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1",
+        "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_LOCAL_PMM",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc8668a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Not Empty : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x17",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL",
+        "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_PMM",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc8678a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0",
+        "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_REMOTE_DDR",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc8670601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1",
+        "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_REMOTE_PMM",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc8670a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1B",
-        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0",
+        "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc47fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1B",
-        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1",
+        "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcccffe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0",
+        "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xccd7fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1",
+        "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xccc7fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "WPQ Flush : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_M2M_WPQ_FLUSH.CH0",
+        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8668601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "WPQ Flush : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_M2M_WPQ_FLUSH.CH1",
+        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8668a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "WPQ Flush : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_M2M_WPQ_FLUSH.CH2",
+        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86e8601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0",
+        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86e8a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1",
+        "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc86ffe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN2",
+        "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_DDR",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc86f8601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0",
+        "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc86e8601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1",
+        "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc86e8a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN2",
+        "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_PMM",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc86f8a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Full : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M2M_WR_TRACKER_FULL.CH0",
+        "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc86f0601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Full : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M2M_WR_TRACKER_FULL.CH1",
+        "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc86f0a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Full : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M2M_WR_TRACKER_FULL.CH2",
+        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8670601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Full : Mirror",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M2M_WR_TRACKER_FULL.MIRR",
+        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8670a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Inserts : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x56",
-        "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0",
+        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86f0601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Inserts : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x56",
-        "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1",
+        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86f0a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Inserts : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x56",
-        "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH2",
+        "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc807fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M2M_WR_TRACKER_NE.CH0",
+        "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc806fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M2M_WR_TRACKER_NE.CH1",
+        "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc887fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Not Empty : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M2M_WR_TRACKER_NE.CH2",
+        "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc886fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Not Empty : Mirror",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR",
+        "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8877e01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x63",
-        "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0",
+        "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8077e01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x63",
-        "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1",
+        "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_SPECITOM",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores that missed the LLC: For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc57fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x63",
-        "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH2",
+        "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc877de01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x62",
-        "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0",
+        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86ffe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x62",
-        "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1",
+        "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc867fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x62",
-        "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH2",
+        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8678601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Occupancy : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH0",
+        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8678a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Occupancy : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH1",
+        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86f8601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Occupancy : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH2",
+        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86f8a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Occupancy : Mirror",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR",
+        "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc87fde01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Posted Inserts : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5E",
-        "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0",
+        "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc807ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Posted Inserts : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5E",
-        "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1",
+        "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc887ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Posted Inserts : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5E",
-        "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH2",
+        "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc57ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Posted Occupancy : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0",
+        "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc27ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Posted Occupancy : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1",
+        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86fff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Tracker Posted Occupancy : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH2",
+        "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc867ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0",
+        "BriefDescription": "TOR Occupancy : All requests from IO Devices",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1",
+        "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Devices",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8c3ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0",
+        "BriefDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fd04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1",
+        "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc43fd04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0",
+        "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcd43fd04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1",
+        "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8f3fd04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS",
+        "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc803fd04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB",
+        "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc43ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS",
+        "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcd43ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x32",
-        "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0",
+        "BriefDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fe04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x32",
-        "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1",
+        "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc43fe04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x32",
-        "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0",
+        "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcd43fe04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x32",
-        "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1",
+        "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8f3fe04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x32",
-        "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0",
+        "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc803fe04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x32",
-        "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1",
+        "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8f3ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB",
+        "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc803ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS",
+        "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc23ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL",
+        "BriefDescription": "TOR Occupancy : IPQ",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : IPQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Inserts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB",
+        "BriefDescription": "TOR Occupancy : IRQ - iA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : IRQ - iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts. : From an iA Core",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Inserts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS",
+        "BriefDescription": "TOR Occupancy : IRQ - Non iA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : IRQ - Non iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Inserts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2P_RxC_INSERTS.ALL",
+        "BriefDescription": "TOR Occupancy : Just ISOC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : Just ISOC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x25",
-        "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_0",
+        "BriefDescription": "TOR Occupancy : Just Local Targets",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : Just Local Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x25",
-        "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_0",
+        "BriefDescription": "TOR Occupancy : All from Local iA and IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : All from Local iA and IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts. : All locally initiated requests",
+        "UMask": "0xc000ff05",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x25",
-        "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_0",
+        "BriefDescription": "TOR Occupancy : All from Local iA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : All from Local iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores",
+        "UMask": "0xc000ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x25",
-        "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_1",
+        "BriefDescription": "TOR Occupancy : All from Local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : All from Local IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic",
+        "UMask": "0xc000ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x25",
-        "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_1",
+        "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x25",
-        "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_1",
+        "BriefDescription": "TOR Occupancy : Just Misses",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : Just Misses : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_0",
+        "BriefDescription": "TOR Occupancy : MMCFG Access",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : MMCFG Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_0",
+        "BriefDescription": "TOR Occupancy : Just NearMem",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : Just NearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_0",
+        "BriefDescription": "TOR Occupancy : Just NonCoherent",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : Just NonCoherent : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_1",
+        "BriefDescription": "TOR Occupancy : Just NotNearMem",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : Just NotNearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_1",
+        "BriefDescription": "TOR Occupancy : PMM Access",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.PMM",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : PMM Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_1",
+        "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress (to CMS) Ingress",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_M2P_TxC_INSERTS.AD_0",
+        "BriefDescription": "TOR Occupancy : PRQ - IOSF",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : PRQ - IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts. : From a PCIe Device",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress (to CMS) Ingress",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_M2P_TxC_INSERTS.BL_0",
+        "BriefDescription": "TOR Occupancy : PRQ - Non IOSF",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : PRQ - Non IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress (to CMS) Ingress",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_0",
+        "BriefDescription": "TOR Occupancy : Just Remote Targets",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.REMOTE_TGT",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "PublicDescription": "TOR Occupancy : Just Remote Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress (to CMS) Ingress",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_M2P_TxC_INSERTS.AD_1",
+        "BriefDescription": "CMS Horizontal ADS Used : AD - All",
+        "EventCode": "0xA6",
+        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress (to CMS) Ingress",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_M2P_TxC_INSERTS.BL_1",
+        "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
+        "EventCode": "0xA6",
+        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress (to CMS) Ingress",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_1",
+        "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
+        "EventCode": "0xA6",
+        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CBox AD Credits Empty : VNA Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x22",
-        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA",
+        "BriefDescription": "CMS Horizontal ADS Used : BL - All",
+        "EventCode": "0xA6",
+        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x44",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CBox AD Credits Empty : Writebacks",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x22",
-        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB",
+        "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
+        "EventCode": "0xA6",
+        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CBox AD Credits Empty : Requests",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x22",
-        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ",
+        "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
+        "EventCode": "0xA6",
+        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CBox AD Credits Empty : Snoops",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x22",
-        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP",
+        "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
+        "EventCode": "0xA7",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2 BL Credits Empty : IIO2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB",
+        "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
+        "EventCode": "0xA7",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2 BL Credits Empty : IIO3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB",
+        "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
+        "EventCode": "0xA7",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2 BL Credits Empty : IIO4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB",
+        "BriefDescription": "CMS Horizontal Bypass Used : AK",
+        "EventCode": "0xA7",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2 BL Credits Empty : IIO5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB",
+        "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
+        "EventCode": "0xA7",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS",
+        "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
+        "EventCode": "0xA7",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x44",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2 BL Credits Empty : Selected M2p BL NCS credits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL",
+        "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
+        "EventCode": "0xA7",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi Slot Flit Received : AD - Slot 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x3E",
-        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0",
+        "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
+        "EventCode": "0xA7",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi Slot Flit Received : AD - Slot 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x3E",
-        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1",
+        "BriefDescription": "CMS Horizontal Bypass Used : IV",
+        "EventCode": "0xA7",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi Slot Flit Received : AD - Slot 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x3E",
-        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
+        "EventCode": "0xA2",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi Slot Flit Received : BL - Slot 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x3E",
-        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
+        "EventCode": "0xA2",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi Slot Flit Received : AK - Slot 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x3E",
-        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
+        "EventCode": "0xA2",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi Slot Flit Received : AK - Slot 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x3E",
-        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
+        "EventCode": "0xA2",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lost Arb for VN0 : REQ on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
+        "EventCode": "0xA2",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lost Arb for VN0 : SNP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
+        "EventCode": "0xA2",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lost Arb for VN0 : RSP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
+        "EventCode": "0xA2",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lost Arb for VN0 : RSP on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
+        "EventCode": "0xA2",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lost Arb for VN0 : WB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
+        "EventCode": "0xA2",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lost Arb for VN0 : NCB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
+        "EventCode": "0xA3",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lost Arb for VN0 : NCS on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
+        "EventCode": "0xA3",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lost Arb for VN1 : REQ on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
+        "EventCode": "0xA3",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lost Arb for VN1 : SNP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
+        "EventCode": "0xA3",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lost Arb for VN1 : RSP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
+        "EventCode": "0xA3",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lost Arb for VN1 : RSP on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
+        "EventCode": "0xA3",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lost Arb for VN1 : WB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
+        "EventCode": "0xA3",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lost Arb for VN1 : NCB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
+        "EventCode": "0xA3",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lost Arb for VN1 : NCS on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
+        "EventCode": "0xA3",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
+        "EventCode": "0xA1",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
+        "EventCode": "0xA1",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
+        "EventCode": "0xA1",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AK",
+        "EventCode": "0xA1",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN0",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
+        "EventCode": "0xA1",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN1",
+        "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
+        "EventCode": "0xA1",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M3UPI_RxC_ARB_MISC.VN01_PARALLEL_WIN",
+        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
+        "EventCode": "0xA1",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x40",
-        "Unit": "M3UPI"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Arb Miscellaneous : Max Parallel Win",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M3UPI_RxC_ARB_MISC.ALL_PARALLEL_WIN",
+        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
+        "EventCode": "0xA1",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN0 : REQ on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_REQ",
+        "BriefDescription": "CMS Horizontal Egress Inserts : IV",
+        "EventCode": "0xA1",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN0 : SNP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_SNP",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
+        "EventCode": "0xA4",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN0 : RSP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_RSP",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
+        "EventCode": "0xA4",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN0 : RSP on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_RSP",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
+        "EventCode": "0xA4",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN0 : WB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_WB",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AK",
+        "EventCode": "0xA4",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.AK",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN0 : NCB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCB",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
+        "EventCode": "0xA4",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN0 : NCS on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCS",
+        "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
+        "EventCode": "0xA4",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+        "UMask": "0x44",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN1 : REQ on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x48",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_REQ",
+        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
+        "EventCode": "0xA4",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN1 : SNP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x48",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_SNP",
+        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
+        "EventCode": "0xA4",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN1 : RSP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x48",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_RSP",
+        "BriefDescription": "CMS Horizontal Egress NACKs : IV",
+        "EventCode": "0xA4",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.IV",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN1 : RSP on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x48",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_RSP",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
+        "EventCode": "0xA0",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN1 : WB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x48",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_WB",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
+        "EventCode": "0xA0",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x10",
-        "Unit": "M3UPI"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN1 : NCB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x48",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCB",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
+        "EventCode": "0xA0",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN1 : NCS on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x48",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCS",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
+        "EventCode": "0xA0",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
-    {
-        "BriefDescription": "Can't Arb for VN0 : REQ on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x49",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_REQ",
+    {
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
+        "EventCode": "0xA0",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Can't Arb for VN0 : SNP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x49",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_SNP",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
+        "EventCode": "0xA0",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Can't Arb for VN0 : RSP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x49",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_RSP",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
+        "EventCode": "0xA0",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Can't Arb for VN0 : RSP on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x49",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_RSP",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
+        "EventCode": "0xA0",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Can't Arb for VN0 : WB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x49",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_WB",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
+        "EventCode": "0xA0",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Can't Arb for VN0 : NCB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x49",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCB",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
+        "EventCode": "0xA5",
+        "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Can't Arb for VN0 : NCS on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x49",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCS",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
+        "EventCode": "0xA5",
+        "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Can't Arb for VN1 : REQ on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_REQ",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
+        "EventCode": "0xA5",
+        "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Can't Arb for VN1 : SNP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_SNP",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
+        "EventCode": "0xA5",
+        "EventName": "UNC_CHA_TxR_HORZ_STARVED.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Can't Arb for VN1 : RSP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_RSP",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
+        "EventCode": "0xA5",
+        "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Can't Arb for VN1 : RSP on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_RSP",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
+        "EventCode": "0xA5",
+        "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Can't Arb for VN1 : WB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_WB",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
+        "EventCode": "0xA5",
+        "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Can't Arb for VN1 : NCB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCB",
+        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+        "EventCode": "0x9C",
+        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Can't Arb for VN1 : NCS on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCS",
+        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+        "EventCode": "0x9C",
+        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL Arb",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 1",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT",
+        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+        "EventCode": "0x9D",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 2",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT",
+        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Miscellaneous Credit Events : Any In BGF FIFO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5F",
-        "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO",
+        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
+        "EventCode": "0x9D",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Miscellaneous Credit Events : Any in BGF Path",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5F",
-        "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH",
+        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Miscellaneous Credit Events : No D2K For Arb",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5F",
-        "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN0_NO_D2K_FOR_ARB",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+        "EventCode": "0x9D",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Miscellaneous Credit Events",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5F",
-        "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN1_NO_D2K_FOR_ARB",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Miscellaneous Credit Events",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5F",
-        "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT1_FOR_D2K",
+        "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV_AG1",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Miscellaneous Credit Events",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5F",
-        "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT2_FOR_D2K",
+        "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
+        "EventCode": "0x9E",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Credit Occupancy : VNA In Use",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x60",
-        "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE",
+        "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Credit Occupancy : Packets in BGF FIFO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x60",
-        "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
+        "EventCode": "0x94",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Credit Occupancy : Packets in BGF Path",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x60",
-        "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
+        "EventCode": "0x94",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Credit Occupancy : Transmit Credits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x60",
-        "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
+        "EventCode": "0x94",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Credit Occupancy : D2K Credits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x60",
-        "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
+        "EventCode": "0x94",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Credit Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x60",
-        "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
+        "EventCode": "0x94",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Credit Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x60",
-        "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
+        "EventCode": "0x94",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
         "UMask": "0x40",
-        "Unit": "M3UPI"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Credit Occupancy : Credits Consumed",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x60",
-        "EventName": "UNC_M3UPI_RxC_CRD_OCC.CONSUMED",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
+        "EventCode": "0x94",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
+        "EventCode": "0x95",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
+        "EventCode": "0x95",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
+        "EventCode": "0x96",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
+        "EventCode": "0x96",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
+        "EventCode": "0x96",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
+        "EventCode": "0x96",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
         "UMask": "0x20",
-        "Unit": "M3UPI"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
+        "EventCode": "0x96",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG0",
+        "PerPkg": "1",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
+        "EventCode": "0x96",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
         "UMask": "0x40",
-        "Unit": "M3UPI"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
+        "EventCode": "0x96",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
+        "EventCode": "0x97",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
+        "EventCode": "0x97",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP",
+        "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB",
+        "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
         "UMask": "0x10",
-        "Unit": "M3UPI"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB",
+        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG0",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
         "UMask": "0x20",
-        "Unit": "M3UPI"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS",
+        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG0",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
         "UMask": "0x40",
-        "Unit": "M3UPI"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data Flit Not Sent : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.ALL",
+        "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data Flit Not Sent : TSV High",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.TSV_HI",
+        "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
+        "EventCode": "0x93",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data Flit Not Sent : Cycle valid for Flit",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.VALID_FOR_FLIT",
+        "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
+        "EventCode": "0x93",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data Flit Not Sent : No BGF Credits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_BGF",
+        "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data Flit Not Sent : No TxQ Credits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_TXQ",
+        "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
         "UMask": "0x10",
-        "Unit": "M3UPI"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x57",
-        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT",
+        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x57",
-        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT",
+        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Generating BL Data Flit Sequence",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x57",
-        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO",
+        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Generating BL Data Flit Sequence",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x57",
-        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY",
+        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Generating BL Data Flit Sequence",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x57",
-        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT",
+        "BriefDescription": "CMS Vertical Egress NACKs : IV",
+        "EventCode": "0x98",
+        "EventName": "UNC_CHA_TxR_VERT_NACK0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Generating BL Data Flit Sequence",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x57",
-        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0",
+        "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
+        "EventCode": "0x99",
+        "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Generating BL Data Flit Sequence",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x57",
-        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL",
+        "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
+        "EventCode": "0x99",
+        "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED",
+        "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN",
+        "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF",
+        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE",
+        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Slotting BL Message Into Header Flit : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x56",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL",
+        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Slotting BL Message Into Header Flit : Needs Data Flit",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x56",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA",
+        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x56",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT",
+        "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x56",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT",
+        "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
+        "EventCode": "0x91",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x56",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ",
+        "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
+        "EventCode": "0x91",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x56",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x56",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1 : Accumulate",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x51",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1 : Accumulate Ready",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x51",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1 : Accumulate Wasted",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x51",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x51",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Message",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x51",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_DURING",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
+        "EventCode": "0x9A",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x51",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_AFTER",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+        "EventCode": "0x9B",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x51",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_SENT",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
+        "EventCode": "0x9B",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x51",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_AFTER",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+        "EventCode": "0x9B",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED1.TGC",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M3UPI"
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x52",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL",
+        "BriefDescription": "Vertical AD Ring In Use : Down and Even",
+        "EventCode": "0xB0",
+        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall - No Message",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x52",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG",
+        "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
+        "EventCode": "0xB0",
+        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Flit Gen - Header 2 : Parallel Ok",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x52",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR",
+        "BriefDescription": "Vertical AD Ring In Use : Up and Even",
+        "EventCode": "0xB0",
+        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Flit Gen - Header 2 : Parallel Message",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x52",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_MSG",
+        "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
+        "EventCode": "0xB0",
+        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Flit Gen - Header 2 : Parallel Flit Finished",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x52",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_FLIT",
+        "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
+        "EventCode": "0xB4",
+        "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sent Header Flit : One Message",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x54",
-        "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG",
+        "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
+        "EventCode": "0xB4",
+        "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sent Header Flit : Two Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x54",
-        "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.2_MSGS",
+        "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
+        "EventCode": "0xB4",
+        "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sent Header Flit : Three Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x54",
-        "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.3_MSGS",
+        "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
+        "EventCode": "0xB4",
+        "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sent Header Flit : One Message in non-VNA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x54",
-        "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG_VNX",
+        "BriefDescription": "Vertical AK Ring In Use : Down and Even",
+        "EventCode": "0xB1",
+        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sent Header Flit : One Slot Taken",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x54",
-        "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_1",
+        "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
+        "EventCode": "0xB1",
+        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sent Header Flit : Two Slots Taken",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x54",
-        "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_2",
+        "BriefDescription": "Vertical AK Ring In Use : Up and Even",
+        "EventCode": "0xB1",
+        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sent Header Flit : All Slots Taken",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x54",
-        "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_3",
+        "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
+        "EventCode": "0xB1",
+        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Header Not Sent : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x53",
-        "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.ALL",
+        "BriefDescription": "Vertical BL Ring in Use : Down and Even",
+        "EventCode": "0xB2",
+        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Header Not Sent : TSV High",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x53",
-        "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.TSV_HI",
+        "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
+        "EventCode": "0xB2",
+        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Header Not Sent : Cycle valid for Flit",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x53",
-        "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.VALID_FOR_FLIT",
+        "BriefDescription": "Vertical BL Ring in Use : Up and Even",
+        "EventCode": "0xB2",
+        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Header Not Sent : No BGF Credits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x53",
-        "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_CRD",
+        "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
+        "EventCode": "0xB2",
+        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Header Not Sent : No TxQ Credits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x53",
-        "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_CRD",
+        "BriefDescription": "Vertical IV Ring in Use : Down",
+        "EventCode": "0xB3",
+        "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Header Not Sent : No BGF Credits + No Extra Message Slotted",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x53",
-        "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_NO_MSG",
+        "BriefDescription": "Vertical IV Ring in Use : Up",
+        "EventCode": "0xB3",
+        "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Header Not Sent : No TxQ Credits + No Extra Message Slotted",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x53",
-        "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_NO_MSG",
+        "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
+        "EventCode": "0xB5",
+        "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Message Held : VN0",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_M3UPI_RxC_HELD.VN0",
+        "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
+        "EventCode": "0xB5",
+        "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Message Held : VN1",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_M3UPI_RxC_HELD.VN1",
+        "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
+        "EventCode": "0xB5",
+        "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Message Held : Parallel Attempt",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT",
+        "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
+        "EventCode": "0xB5",
+        "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Message Held : Parallel Success",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS",
+        "BriefDescription": "WbPushMtoI : Pushed to LLC",
+        "EventCode": "0x56",
+        "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "WbPushMtoI : Pushed to LLC : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was able to push WbPushMToI to LLC",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Message Held : Can't Slot AD",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD",
+        "BriefDescription": "WbPushMtoI : Pushed to Memory",
+        "EventCode": "0x56",
+        "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "WbPushMtoI : Pushed to Memory : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM)",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Message Held : Can't Slot BL",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC0 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 0 only.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : REQ on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC1 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 1 only.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : SNP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC10",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC10",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC10 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 10 only.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC11",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC11",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC11 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 11 only.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC12",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC12",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC12 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 12 only.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : WB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC13",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC13",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC13 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 13 only.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC2 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 2 only.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCS on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC3 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 3 only.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : REQ on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC4 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 4 only.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : SNP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC5 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 5 only.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC6",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC6",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC6 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 6 only.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC7",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC7",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC7 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 7 only.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : WB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC8",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC8",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC8 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 8 only.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC9",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC9",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC9 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 9 only.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCS on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS",
+        "BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict",
+        "EventCode": "0x6f",
+        "EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "XPT Prefetches : Dropped (on 0?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ",
+        "BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits",
+        "EventCode": "0x6f",
+        "EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "XPT Prefetches : Dropped (on 0?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP",
+        "BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict",
+        "EventCode": "0x6f",
+        "EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "XPT Prefetches : Dropped (on 1?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP",
+        "BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits",
+        "EventCode": "0x6f",
+        "EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "XPT Prefetches : Dropped (on 1?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP",
+        "BriefDescription": "XPT Prefetches : Sent (on 0?)",
+        "EventCode": "0x6f",
+        "EventName": "UNC_CHA_XPT_PREF.SENT0",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "XPT Prefetches : Sent (on 0?) : Number of XPT prefetches sent",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : WB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB",
+        "BriefDescription": "XPT Prefetches : Sent (on 1?)",
+        "EventCode": "0x6f",
+        "EventName": "UNC_CHA_XPT_PREF.SENT1",
         "PerPkg": "1",
+        "PublicDescription": "XPT Prefetches : Sent (on 1?) : Number of XPT prefetches sent",
         "UMask": "0x10",
-        "Unit": "M3UPI"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : WB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART0_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN0 message can't slot into flit : REQ on AD",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART1_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN0 message can't slot into flit : SNP on AD",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART2_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN0 message can't slot into flit : RSP on AD",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART3_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN0 message can't slot into flit : RSP on BL",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART4_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN0 message can't slot into flit : WB on BL",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART5_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN0 message can't slot into flit : NCB on BL",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART6_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN0 message can't slot into flit : NCS on BL",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART7_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 message can't slot into flit : REQ on AD",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ",
+        "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller",
+        "EventCode": "0x01",
+        "EventName": "UNC_IIO_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Clockticks of the integrated IO (IIO) traffic controller : Increments counter once every Traffic Controller clock, the LSCLK (500MHz)",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 message can't slot into flit : SNP on AD",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP",
+        "BriefDescription": "Free running counter that increments for IIO clocktick",
+        "EventName": "UNC_IIO_CLOCKTICKS_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Free running counter that increments for integrated IO (IIO) traffic controller clockticks",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 message can't slot into flit : RSP on AD",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP",
+        "BriefDescription": "PCIe Completion Buffer Inserts : All Ports",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PortMask": "0xFF",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 message can't slot into flit : RSP on BL",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PortMask": "0xff",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 message can't slot into flit : WB on BL",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PortMask": "0x01",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 message can't slot into flit : NCB on BL",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PortMask": "0x02",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 message can't slot into flit : NCS on BL",
-        "Counter": "0,1,2",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PortMask": "0x04",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Remote VNA Credits : Corrected",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PortMask": "0x08",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Remote VNA Credits : Level < 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PortMask": "0x10",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Remote VNA Credits : Level < 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PortMask": "0x20",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Remote VNA Credits : Level < 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6",
+        "FCMask": "0x04",
+        "PerPkg": "1",
+        "PortMask": "0x40",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6",
+        "UMask": "0x3",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PortMask": "0x80",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Remote VNA Credits : Level < 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT10",
+        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
+        "EventCode": "0xD5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7",
+        "UMask": "0xff",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Remote VNA Credits : Any In Use",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE",
+        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
+        "EventCode": "0xd5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7",
+        "UMask": "0xff",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x59",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10",
+        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0",
+        "EventCode": "0xd5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x59",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5",
+        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 1",
+        "EventCode": "0xd5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "PCIe Completion Buffer Occupancy : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x59",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY",
+        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 2",
+        "EventCode": "0xd5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "PCIe Completion Buffer Occupancy : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x59",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY",
+        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 3",
+        "EventCode": "0xd5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "PCIe Completion Buffer Occupancy : Part 3 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x59",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD",
+        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4",
+        "EventCode": "0xd5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4",
+        "FCMask": "0x04",
         "PerPkg": "1",
+        "PublicDescription": "PCIe Completion Buffer Occupancy : Part 4 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4",
         "UMask": "0x10",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x59",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL",
+        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 5",
+        "EventCode": "0xd5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5",
+        "FCMask": "0x04",
         "PerPkg": "1",
+        "PublicDescription": "PCIe Completion Buffer Occupancy : Part 5 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5",
         "UMask": "0x20",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x59",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD",
+        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 6",
+        "EventCode": "0xd5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6",
+        "FCMask": "0x04",
         "PerPkg": "1",
+        "PublicDescription": "PCIe Completion Buffer Occupancy : Part 6 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6",
         "UMask": "0x40",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x59",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL",
+        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 7",
+        "EventCode": "0xd5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7",
+        "FCMask": "0x04",
         "PerPkg": "1",
+        "PublicDescription": "PCIe Completion Buffer Occupancy : Part 7 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7",
         "UMask": "0x80",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Failed ARB for AD : VN0 REQ Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Failed ARB for AD : VN0 SNP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Failed ARB for AD : VN0 RSP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Failed ARB for AD : VN0 WB Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PortMask": "0x02",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Failed ARB for AD : VN1 REQ Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PortMask": "0x04",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Failed ARB for AD : VN1 SNP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PortMask": "0x08",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Failed ARB for AD : VN1 RSP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
         "UMask": "0x40",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Failed ARB for AD : VN1 WB Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M3UPI"
+        "PortMask": "0x20",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD FlowQ Bypass",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PortMask": "0x40",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD FlowQ Bypass",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PortMask": "0x80",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD FlowQ Bypass",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD FlowQ Bypass",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty : VN0 REQ Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty : VN0 SNP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PortMask": "0x02",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty : VN0 RSP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PortMask": "0x04",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty : VN0 WB Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PortMask": "0x08",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty : VN1 REQ Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
         "UMask": "0x10",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty : VN1 SNP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PortMask": "0x20",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty : VN1 RSP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PortMask": "0x40",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty : VN1 WB Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M3UPI"
+        "PortMask": "0x80",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD Flow Q Inserts : VN0 REQ Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD Flow Q Inserts : VN0 SNP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD Flow Q Inserts : VN0 RSP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD Flow Q Inserts : VN0 WB Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PortMask": "0x02",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD Flow Q Inserts : VN1 REQ Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PortMask": "0x04",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD Flow Q Inserts : VN1 SNP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PortMask": "0x08",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD Flow Q Inserts : VN1 RSP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PortMask": "0x10",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD Flow Q Occupancy : VN0 REQ Messages",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PortMask": "0x20",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD Flow Q Occupancy : VN0 SNP Messages",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PortMask": "0x40",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD Flow Q Occupancy : VN0 RSP Messages",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PortMask": "0x80",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD Flow Q Occupancy : VN0 WB Messages",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD Flow Q Occupancy : VN1 REQ Messages",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD Flow Q Occupancy : VN1 SNP Messages",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
         "UMask": "0x20",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AD Flow Q Occupancy : VN1 RSP Messages",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PortMask": "0x02",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Failed ARB for BL : VN0 RSP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PortMask": "0x04",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Failed ARB for BL : VN0 WB Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PortMask": "0x08",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Failed ARB for BL : VN0 NCB Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PortMask": "0x10",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Failed ARB for BL : VN0 NCS Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PortMask": "0x20",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Failed ARB for BL : VN1 RSP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PortMask": "0x40",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Failed ARB for BL : VN1 WB Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x80",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
         "UMask": "0x20",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Failed ARB for BL : VN1 NCS Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB",
+        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Failed ARB for BL : VN1 NCB Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS",
+        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M3UPI"
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty : VN0 REQ Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ",
+        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty : VN0 SNP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP",
+        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PortMask": "0x02",
+        "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty : VN0 RSP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP",
+        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PortMask": "0x04",
+        "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty : VN0 WB Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB",
+        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PortMask": "0x08",
+        "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty : VN1 REQ Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ",
+        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PortMask": "0x10",
+        "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty : VN1 SNP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP",
+        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PortMask": "0x20",
+        "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty : VN1 RSP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP",
+        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PortMask": "0x40",
+        "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty : VN1 WB Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB",
+        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M3UPI"
+        "PortMask": "0x80",
+        "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts : VN0 RSP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts : VN0 WB Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts : VN0 NCB Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts : VN0 NCS Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PortMask": "0x02",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts : VN1 RSP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PortMask": "0x04",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts : VN1 WB Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PortMask": "0x08",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts : VN1_NCS Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PortMask": "0x10",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts : VN1_NCB Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M3UPI"
+        "PortMask": "0x20",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PortMask": "0x40",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PortMask": "0x80",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy : VN0 NCS Messages",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PortMask": "0x02",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PortMask": "0x04",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PortMask": "0x08",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy : VN1_NCB Messages",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M3UPI"
+        "PortMask": "0x10",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1F",
-        "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_LOCAL",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PortMask": "0x20",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1F",
-        "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_THROUGH",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PortMask": "0x40",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1F",
-        "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_WRPULL",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PortMask": "0x80",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1F",
-        "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_LOCAL",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1F",
-        "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_THROUGH",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1F",
-        "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_WRPULL",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UPI0 AD Credits Empty : VNA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PortMask": "0x02",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UPI0 AD Credits Empty : VN0 REQ Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PortMask": "0x04",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UPI0 AD Credits Empty : VN0 SNP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PortMask": "0x08",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UPI0 AD Credits Empty : VN0 RSP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PortMask": "0x10",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UPI0 AD Credits Empty : VN1 REQ Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PortMask": "0x20",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UPI0 AD Credits Empty : VN1 SNP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PortMask": "0x40",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UPI0 AD Credits Empty : VN1 RSP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PortMask": "0x80",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UPI0 BL Credits Empty : VNA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA",
+        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UPI0 BL Credits Empty : VN0 REQ Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP",
+        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UPI0 BL Credits Empty : VN0 RSP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB",
+        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UPI0 BL Credits Empty : VN0 SNP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB",
+        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PortMask": "0x02",
+        "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UPI0 BL Credits Empty : VN1 REQ Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP",
+        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
         "UMask": "0x10",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UPI0 BL Credits Empty : VN1 RSP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB",
+        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PortMask": "0x08",
+        "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UPI0 BL Credits Empty : VN1 SNP Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB",
+        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PortMask": "0x10",
+        "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN0 Credit Used : REQ on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5B",
-        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ",
+        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PortMask": "0x20",
+        "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN0 Credit Used : SNP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5B",
-        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP",
+        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PortMask": "0x40",
+        "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN0 Credit Used : RSP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5B",
-        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP",
+        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PortMask": "0x80",
+        "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN0 Credit Used : RSP on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5B",
-        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN0 Credit Used : WB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5B",
-        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN0 Credit Used : NCB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5B",
-        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN0 No Credits : REQ on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PortMask": "0x02",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN0 No Credits : SNP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PortMask": "0x04",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN0 No Credits : RSP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PortMask": "0x08",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN0 No Credits : RSP on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PortMask": "0x10",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN0 No Credits : WB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PortMask": "0x20",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN0 No Credits : NCB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PortMask": "0x40",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 Credit Used : REQ on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5C",
-        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PortMask": "0x80",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 Credit Used : SNP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5C",
-        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP",
+        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 Credit Used : RSP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5C",
-        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP",
+        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 Credit Used : RSP on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5C",
-        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB",
+        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 Credit Used : WB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5C",
-        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB",
+        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PortMask": "0x02",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 Credit Used : NCB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5C",
-        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS",
+        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PortMask": "0x04",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 No Credits : REQ on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5E",
-        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ",
+        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PortMask": "0x08",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 No Credits : SNP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5E",
-        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP",
+        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PortMask": "0x10",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 No Credits : RSP on AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5E",
-        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP",
+        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PortMask": "0x20",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 No Credits : RSP on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5E",
-        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB",
+        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PortMask": "0x40",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 No Credits : WB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5E",
-        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB",
+        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PortMask": "0x80",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "VN1 No Credits : NCB on BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5E",
-        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS",
+        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7E",
-        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0",
+        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7E",
-        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0",
+        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7E",
-        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0",
+        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PortMask": "0x02",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7E",
-        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1",
+        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PortMask": "0x04",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7E",
-        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1",
+        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PortMask": "0x08",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7E",
-        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1",
+        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PortMask": "0x10",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7E",
-        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0",
+        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x81",
-        "Unit": "M3UPI"
+        "PortMask": "0x20",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7E",
-        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0",
+        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x82",
-        "Unit": "M3UPI"
+        "PortMask": "0x40",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7E",
-        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0",
+        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x84",
-        "Unit": "M3UPI"
+        "PortMask": "0x80",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7E",
-        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1",
+        "BriefDescription": "Data requested of the CPU : Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x90",
-        "Unit": "M3UPI"
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7E",
-        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1",
+        "BriefDescription": "Data requested of the CPU : Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0xA0",
-        "Unit": "M3UPI"
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7E",
-        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1",
+        "BriefDescription": "Data requested of the CPU : Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0xC0",
-        "Unit": "M3UPI"
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7D",
-        "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0",
+        "BriefDescription": "Data requested of the CPU : Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PortMask": "0x02",
+        "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7D",
-        "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0",
+        "BriefDescription": "Data requested of the CPU : Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PortMask": "0x04",
+        "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7D",
-        "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0",
+        "BriefDescription": "Data requested of the CPU : Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PortMask": "0x08",
+        "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7D",
-        "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0",
+        "BriefDescription": "Data requested of the CPU : Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PortMask": "0x10",
+        "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7D",
-        "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1",
+        "BriefDescription": "Data requested of the CPU : Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PortMask": "0x20",
+        "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7D",
-        "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1",
+        "BriefDescription": "Data requested of the CPU : Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PortMask": "0x40",
+        "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7D",
-        "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1",
+        "BriefDescription": "Data requested of the CPU : Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x80",
+        "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
         "UMask": "0x40",
-        "Unit": "M3UPI"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7D",
-        "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1",
+        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M3UPI"
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARRIVED",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x61",
-        "EventName": "UNC_M3UPI_XPT_PFTCH.ARRIVED",
+        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_XPT_PFTCH.BYPASS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x61",
-        "EventName": "UNC_M3UPI_XPT_PFTCH.BYPASS",
+        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x61",
-        "EventName": "UNC_M3UPI_XPT_PFTCH.ARB",
+        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PortMask": "0x02",
+        "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_ARB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x61",
-        "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_ARB",
+        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PortMask": "0x04",
+        "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_XPT_PFTCH.FLITTED",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x61",
-        "EventName": "UNC_M3UPI_XPT_PFTCH.FLITTED",
+        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PortMask": "0x08",
+        "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_OLD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x61",
-        "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_OLD",
+        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PortMask": "0x10",
+        "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x61",
-        "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL",
+        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PortMask": "0x20",
+        "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Message Received : VLW",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
+        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "UBOX"
+        "PortMask": "0x40",
+        "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Message Received : MSI",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
+        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "UBOX"
+        "PortMask": "0x80",
+        "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Message Received : IPI",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "UBOX"
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Message Received : Doorbell",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "UBOX"
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Message Received : Interrupt",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_U_EVENT_MSG.INT_PRIO",
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "UBOX"
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "UBOX"
+        "PortMask": "0x02",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_U_RACU_DRNG.RDRAND",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4C",
-        "EventName": "UNC_U_RACU_DRNG.RDRAND",
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "UBOX"
+        "PortMask": "0x04",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_U_RACU_DRNG.RDSEED",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4C",
-        "EventName": "UNC_U_RACU_DRNG.RDSEED",
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "UBOX"
+        "PortMask": "0x08",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4C",
-        "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "UBOX"
+        "PortMask": "0x10",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Direct packet attempts : D2C",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C",
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "UPI LL"
+        "PortMask": "0x20",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Direct packet attempts : D2K",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K",
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "UPI LL"
+        "PortMask": "0x40",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "UPI LL"
+        "PortMask": "0x80",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
+        "BriefDescription": "Incoming arbitration requests : Passing data to be written",
+        "EventCode": "0x86",
+        "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests : Passing data to be written : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
+        "BriefDescription": "Incoming arbitration requests : Issuing final read or write of line",
+        "EventCode": "0x86",
+        "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests : Issuing final read or write of line : How often different queues (e.g. channel / fc) ask to send request into pipeline",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
+        "BriefDescription": "Incoming arbitration requests : Processing response from IOMMU",
+        "EventCode": "0x86",
+        "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests : Processing response from IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
+        "BriefDescription": "Incoming arbitration requests : Issuing to IOMMU",
+        "EventCode": "0x86",
+        "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests : Issuing to IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
+        "BriefDescription": "Incoming arbitration requests : Request Ownership",
+        "EventCode": "0x86",
+        "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests : Request Ownership : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
+        "BriefDescription": "Incoming arbitration requests : Writing line",
+        "EventCode": "0x86",
+        "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests : Writing line : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
+        "BriefDescription": "Incoming arbitration requests granted : Passing data to be written",
+        "EventCode": "0x87",
+        "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests granted : Passing data to be written : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
+        "BriefDescription": "Incoming arbitration requests granted : Issuing final read or write of line",
+        "EventCode": "0x87",
+        "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests granted : Issuing final read or write of line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
+        "BriefDescription": "Incoming arbitration requests granted : Processing response from IOMMU",
+        "EventCode": "0x87",
+        "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests granted : Processing response from IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
+        "BriefDescription": "Incoming arbitration requests granted : Issuing to IOMMU",
+        "EventCode": "0x87",
+        "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests granted : Issuing to IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
+        "BriefDescription": "Incoming arbitration requests granted : Request Ownership",
+        "EventCode": "0x87",
+        "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests granted : Request Ownership : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
+        "BriefDescription": "Incoming arbitration requests granted : Writing line",
+        "EventCode": "0x87",
+        "EventName": "UNC_IIO_INBOUND_ARB_WON.WR",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests granted : Writing line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests",
         "UMask": "0x10",
-        "Unit": "UPI LL"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
+        "BriefDescription": ": IOTLB Hits to a 1G Page",
+        "EventCode": "0x40",
+        "EventName": "UNC_IIO_IOMMU0.1G_HITS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "UPI LL"
+        "PublicDescription": ": IOTLB Hits to a 1G Page : Counts if a transaction to a 1G page, on its first lookup, hits the IOTLB.",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
+        "BriefDescription": ": IOTLB Hits to a 2M Page",
+        "EventCode": "0x40",
+        "EventName": "UNC_IIO_IOMMU0.2M_HITS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "UPI LL"
+        "PublicDescription": ": IOTLB Hits to a 2M Page : Counts if a transaction to a 2M page, on its first lookup, hits the IOTLB.",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
+        "BriefDescription": ": IOTLB Hits to a 4K Page",
+        "EventCode": "0x40",
+        "EventName": "UNC_IIO_IOMMU0.4K_HITS",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "UPI LL"
+        "PublicDescription": ": IOTLB Hits to a 4K Page : Counts if a transaction to a 4K page, on its first lookup, hits the IOTLB.",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
+        "BriefDescription": ": IOTLB lookups all",
+        "EventCode": "0x40",
+        "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "UPI LL"
+        "PublicDescription": ": IOTLB lookups all : Some transactions have to look up IOTLB multiple times.  Counts every time a request looks up IOTLB.",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
+        "BriefDescription": ": Context cache hits",
+        "EventCode": "0x40",
+        "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "UPI LL"
+        "PublicDescription": ": Context cache hits : Counts each time a first look up of the transaction hits the RCC.",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
+        "BriefDescription": ": Context cache lookups",
+        "EventCode": "0x40",
+        "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "UPI LL"
+        "PublicDescription": ": Context cache lookups : Counts each time a transaction looks up root context cache.",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
+        "BriefDescription": ": IOTLB lookups first",
+        "EventCode": "0x40",
+        "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "UPI LL"
+        "PublicDescription": ": IOTLB lookups first : Some transactions have to look up IOTLB multiple times.  Counts the first time a request looks up IOTLB.",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
+        "BriefDescription": ": IOTLB Fills (same as IOTLB miss)",
+        "EventCode": "0x40",
+        "EventName": "UNC_IIO_IOMMU0.MISSES",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "UPI LL"
+        "PublicDescription": ": IOTLB Fills (same as IOTLB miss) : When a transaction misses IOTLB, it does a page walk to look up memory and bring in the relevant page translation. Counts when this page translation is written to IOTLB.",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
+        "BriefDescription": ": Cycles PWT full",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_IOMMU1.CYC_PWT_FULL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "UPI LL"
+        "PublicDescription": ": Cycles PWT full : Counts cycles the IOMMU has reached its maximum limit for outstanding page walks.",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
+        "BriefDescription": ": IOMMU memory access",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "UPI LL"
+        "PublicDescription": ": IOMMU memory access : IOMMU sends out memory fetches when it misses the cache look up which is indicated by this signal.  M2IOSF only uses low priority channel",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
+        "BriefDescription": ": PWC Hit to a 1G page",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "UPI LL"
+        "PublicDescription": ": PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port : Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
+        "BriefDescription": ": PWC Hit to a 2M page",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "UPI LL"
+        "PublicDescription": ": PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port : Request, Match Opcode",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC",
+        "BriefDescription": ": PWC Hit to a 4K page",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_IOMMU1.PWC_4K_HITS",
         "PerPkg": "1",
-        "UMask": "0x108",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PublicDescription": ": PWC Hit to a 4K page : Counts each time a transaction's first look up hits the SLPWC at the 4K level",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port : Snoop",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
+        "BriefDescription": ": PWT Hit to a 256T page",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS",
         "PerPkg": "1",
-        "UMask": "0x09",
-        "Unit": "UPI LL"
+        "PublicDescription": ": PWT Hit to a 256T page : Counts each time a transaction's first look up hits the SLPWC at the 512G level",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port : Snoop, Match Opcode",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC",
+        "BriefDescription": ": PageWalk cache fill",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS",
         "PerPkg": "1",
-        "UMask": "0x109",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PublicDescription": ": PageWalk cache fill : When a transaction misses SLPWC, it does a page walk to look up memory and bring in the relevant page translation. When this page translation is written to SLPWC, ObsPwcFillValid_nnnH is asserted.",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA",
+        "BriefDescription": ": PageWalk cache lookup",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS",
         "PerPkg": "1",
-        "UMask": "0x0A",
-        "Unit": "UPI LL"
+        "PublicDescription": ": PageWalk cache lookup : Counts each time a transaction looks up second level page walk cache.",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data, Match Opcode",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
+        "BriefDescription": ": Interrupt Entry cache hit",
+        "EventCode": "0x43",
+        "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS",
         "PerPkg": "1",
-        "UMask": "0x10A",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PublicDescription": ": Interrupt Entry cache hit : Counts each time a transaction's first look up hits the IEC.",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port : Response - Data",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
+        "BriefDescription": ": Interrupt Entry cache lookup",
+        "EventCode": "0x43",
+        "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS",
         "PerPkg": "1",
-        "UMask": "0x0C",
-        "Unit": "UPI LL"
+        "PublicDescription": ": Interrupt Entry cache lookup : Counts the number of transaction looks up that interrupt remapping cache.",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port : Response - Data, Match Opcode",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
+        "BriefDescription": ": Device-selective Context cache invalidation cycles",
+        "EventCode": "0x43",
+        "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DEVICE",
         "PerPkg": "1",
-        "UMask": "0x10C",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PublicDescription": ": Device-selective Context cache invalidation cycles : Counts number of Device selective context cache invalidation events",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port : Writeback",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
+        "BriefDescription": ": Domain-selective Context cache invalidation cycles",
+        "EventCode": "0x43",
+        "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DOMAIN",
         "PerPkg": "1",
-        "UMask": "0x0D",
-        "Unit": "UPI LL"
+        "PublicDescription": ": Domain-selective Context cache invalidation cycles : Counts number of Domain selective context cache invalidation events",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port : Writeback, Match Opcode",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC",
+        "BriefDescription": ": Context cache global invalidation cycles",
+        "EventCode": "0x43",
+        "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_GBL",
         "PerPkg": "1",
-        "UMask": "0x10D",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PublicDescription": ": Context cache global invalidation cycles : Counts number of Context Cache global invalidation events",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
+        "BriefDescription": ": Domain-selective IOTLB invalidation cycles",
+        "EventCode": "0x43",
+        "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_DOMAIN",
         "PerPkg": "1",
-        "UMask": "0x0E",
-        "Unit": "UPI LL"
+        "PublicDescription": ": Domain-selective IOTLB invalidation cycles : Counts number of Domain selective invalidation events",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
+        "BriefDescription": ": Global IOTLB invalidation cycles",
+        "EventCode": "0x43",
+        "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_GBL",
         "PerPkg": "1",
-        "UMask": "0x10E",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PublicDescription": ": Global IOTLB invalidation cycles : Indicates that IOMMU is doing global invalidation.",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
+        "BriefDescription": ": Page-selective IOTLB invalidation cycles",
+        "EventCode": "0x43",
+        "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PAGE",
         "PerPkg": "1",
-        "UMask": "0x0F",
-        "Unit": "UPI LL"
+        "PublicDescription": ": Page-selective IOTLB invalidation cycles : Counts number of Page-selective within Domain Invalidation events",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
+        "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus",
+        "EventCode": "0x02",
+        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0",
         "PerPkg": "1",
-        "UMask": "0x10F",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus : Asserted if all bits specified by mask match",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
-    {
-        "BriefDescription": "Matches on Receive path of a UPI Port : Response - Conflict",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT",
+    {
+        "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus",
+        "EventCode": "0x02",
+        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1",
         "PerPkg": "1",
-        "UMask": "0x1AA",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if all bits specified by mask match",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port : Response - Invalid",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI",
+        "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
+        "EventCode": "0x02",
+        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1",
         "PerPkg": "1",
-        "UMask": "0x12A",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if all bits specified by mask match",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x31",
-        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0",
+        "BriefDescription": "AND Mask/match for debug bus : PCIE bus",
+        "EventCode": "0x02",
+        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "UPI LL"
+        "PublicDescription": "AND Mask/match for debug bus : PCIE bus : Asserted if all bits specified by mask match",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x31",
-        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1",
+        "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
+        "EventCode": "0x02",
+        "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "UPI LL"
+        "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if all bits specified by mask match",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x31",
-        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2",
+        "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
+        "EventCode": "0x02",
+        "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "UPI LL"
+        "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if all bits specified by mask match",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Valid Flits Received : Slot 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus",
         "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.SLOT0",
+        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "UPI LL"
+        "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus : Asserted if any bits specified by mask match",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Valid Flits Received : Slot 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus",
         "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.SLOT1",
+        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "UPI LL"
+        "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if any bits specified by mask match",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Valid Flits Received : Slot 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
         "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.SLOT2",
+        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "UPI LL"
+        "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if any bits specified by mask match",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Valid Flits Received : Data",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "OR Mask/match for debug bus : PCIE bus",
         "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.DATA",
+        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "UPI LL"
+        "PublicDescription": "OR Mask/match for debug bus : PCIE bus : Asserted if any bits specified by mask match",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Valid Flits Received : LLCRD Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
         "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.LLCRD",
+        "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1",
         "PerPkg": "1",
+        "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if any bits specified by mask match",
         "UMask": "0x10",
-        "Unit": "UPI LL"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
         "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.NULL",
+        "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1",
         "PerPkg": "1",
+        "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if any bits specified by mask match",
         "UMask": "0x20",
-        "Unit": "UPI LL"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Valid Flits Received : LLCTRL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.LLCTRL",
+        "BriefDescription": "Counting disabled",
+        "EventCode": "0x80",
+        "EventName": "UNC_IIO_NOTHING",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "UPI LL"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Valid Flits Received : Protocol Header",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.PROTHDR",
+        "BriefDescription": "Occupancy of outbound request queue : To device",
+        "EventCode": "0xC5",
+        "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "Occupancy of outbound request queue : To device : Counts number of outbound requests/completions IIO is currently processing",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Valid Flits Received : Null FLITs received from any slot",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.IDLE",
+        "BriefDescription": ": Passing data to be written",
+        "EventCode": "0x88",
+        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x47",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": ": Passing data to be written : Only for posted requests",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "RxQ Flit Buffer Allocations : Slot 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x30",
-        "EventName": "UNC_UPI_RxL_INSERTS.SLOT0",
+        "BriefDescription": ": Issuing final read or write of line",
+        "EventCode": "0x88",
+        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "RxQ Flit Buffer Allocations : Slot 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x30",
-        "EventName": "UNC_UPI_RxL_INSERTS.SLOT1",
+        "BriefDescription": ": Processing response from IOMMU",
+        "EventCode": "0x88",
+        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "RxQ Flit Buffer Allocations : Slot 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x30",
-        "EventName": "UNC_UPI_RxL_INSERTS.SLOT2",
+        "BriefDescription": ": Issuing to IOMMU",
+        "EventCode": "0x88",
+        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "RxQ Occupancy - All Packets : Slot 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x32",
-        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0",
+        "BriefDescription": ": Request Ownership",
+        "EventCode": "0x88",
+        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": ": Request Ownership : Only for posted requests",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "RxQ Occupancy - All Packets : Slot 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x32",
-        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1",
+        "BriefDescription": ": Writing line",
+        "EventCode": "0x88",
+        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": ": Writing line : Only for posted requests",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "RxQ Occupancy - All Packets : Slot 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x32",
-        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2",
+        "BriefDescription": "Number requests sent to PCIe from main die : From IRP",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.IRP",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "Number requests sent to PCIe from main die : From IRP : Captures Posted/Non-posted allocations from IRP. i.e. either non-confined P2P traffic or from the CPU",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
+        "BriefDescription": "Number requests sent to PCIe from main die : From ITC",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.ITC",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "Number requests sent to PCIe from main die : From ITC : Confined P2P",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
+        "BriefDescription": "Number requests sent to PCIe from main die : Completion allocations",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.PREALLOC",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
+        "BriefDescription": "Number requests PCIe makes of the main die : Drop request",
+        "EventCode": "0x85",
+        "EventName": "UNC_IIO_NUM_REQ_OF_CPU.ALL.DROP",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "Number requests PCIe makes of the main die : Drop request : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU. : Packet error detected, must be dropped",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
+        "BriefDescription": "Number requests PCIe makes of the main die : All",
+        "EventCode": "0x85",
+        "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU.",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
+        "BriefDescription": "Num requests sent by PCIe - by target : Abort",
+        "EventCode": "0x8E",
+        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
+        "BriefDescription": "Num requests sent by PCIe - by target : Confined P2P",
+        "EventCode": "0x8E",
+        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0xFF",
+        "UMask": "0x40",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Num requests sent by PCIe - by target : Local P2P",
+        "EventCode": "0x8E",
+        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0xFF",
         "UMask": "0x20",
-        "Unit": "UPI LL"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
+        "BriefDescription": "Num requests sent by PCIe - by target : Multi-cast",
+        "EventCode": "0x8E",
+        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0xFF",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Num requests sent by PCIe - by target : Memory",
+        "EventCode": "0x8E",
+        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
+        "BriefDescription": "Num requests sent by PCIe - by target : MsgB",
+        "EventCode": "0x8E",
+        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
+        "BriefDescription": "Num requests sent by PCIe - by target : Remote P2P",
+        "EventCode": "0x8E",
+        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
+        "BriefDescription": "Num requests sent by PCIe - by target : Ubox",
+        "EventCode": "0x8E",
+        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
+        "BriefDescription": "ITC address map 1",
+        "EventCode": "0x8F",
+        "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "UPI LL"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
+        "BriefDescription": "Outbound cacheline requests issued : 64B requests issued to device",
+        "EventCode": "0xD0",
+        "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "Outbound cacheline requests issued : 64B requests issued to device : Each outbound cacheline granular request may need to make multiple passes through the pipeline.  Each time a cacheline completes all its passes it advances line",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
+        "BriefDescription": "Outbound TLP (transaction layer packet) requests issued : To device",
+        "EventCode": "0xD1",
+        "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "Outbound TLP (transaction layer packet) requests issued : To device : Each time an outbound completes all its passes it advances the pointer",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
+        "BriefDescription": "PWT occupancy",
+        "EventCode": "0x42",
+        "EventName": "UNC_IIO_PWT_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "UPI LL"
+        "PublicDescription": "PWT occupancy : Indicates how many page walks are outstanding at any point in time.",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port : Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
+        "BriefDescription": "PCIe Request - cacheline complete : Passing data to be written",
+        "EventCode": "0x91",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request - cacheline complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port : Request, Match Opcode",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC",
+        "BriefDescription": "PCIe Request - cacheline complete : Issuing final read or write of line",
+        "EventCode": "0x91",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x108",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request - cacheline complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port : Snoop",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
+        "BriefDescription": "PCIe Request - cacheline complete : Request Ownership",
+        "EventCode": "0x91",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x09",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request - cacheline complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port : Snoop, Match Opcode",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC",
+        "BriefDescription": "PCIe Request - cacheline complete : Writing line",
+        "EventCode": "0x91",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x109",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request - cacheline complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
+        "BriefDescription": "PCIe Request complete : Passing data to be written",
+        "EventCode": "0x92",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.DATA",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x0A",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
+        "BriefDescription": "PCIe Request complete : Issuing final read or write of line",
+        "EventCode": "0x92",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10A",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
+        "BriefDescription": "PCIe Request complete : Processing response from IOMMU",
+        "EventCode": "0x92",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x0C",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request complete : Processing response from IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data, Match Opcode",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
+        "BriefDescription": "PCIe Request complete : Issuing to IOMMU",
+        "EventCode": "0x92",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10C",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request complete : Issuing to IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port : Writeback",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
+        "BriefDescription": "PCIe Request complete : Request Ownership",
+        "EventCode": "0x92",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x0D",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port : Writeback, Match Opcode",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC",
+        "BriefDescription": "PCIe Request complete : Writing line",
+        "EventCode": "0x92",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.WR",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10D",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
+        "BriefDescription": "PCIe Request - pass complete : Passing data to be written",
+        "EventCode": "0x90",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x0E",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request - pass complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
+        "BriefDescription": "PCIe Request - pass complete : Issuing final read or write of line",
+        "EventCode": "0x90",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10E",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request - pass complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
+        "BriefDescription": "PCIe Request - pass complete : Request Ownership",
+        "EventCode": "0x90",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x0F",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request - pass complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
+        "BriefDescription": "PCIe Request - pass complete : Writing line",
+        "EventCode": "0x90",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10F",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request - pass complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Conflict",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT",
+        "BriefDescription": "Symbol Times on Link",
+        "EventCode": "0x82",
+        "EventName": "UNC_IIO_SYMBOL_TIMES",
         "PerPkg": "1",
-        "UMask": "0x1AA",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Symbol Times on Link : Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Invalid",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x12A",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "PortMask": "0x100",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Valid Flits Sent : Slot 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.SLOT0",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "UPI LL"
+        "PortMask": "0x200",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Valid Flits Sent : Slot 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.SLOT1",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "UPI LL"
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Valid Flits Sent : Slot 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.SLOT2",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "UPI LL"
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Valid Flits Sent : Data",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.DATA",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "UPI LL"
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Valid Flits Sent : LLCRD Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.LLCRD",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "UPI LL"
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.NULL",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "UPI LL"
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Valid Flits Sent : LLCTRL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.LLCTRL",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
         "UMask": "0x40",
-        "Unit": "UPI LL"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Valid Flits Sent : Protocol Header",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.PROTHDR",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "UPI LL"
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Valid Flits Sent : Idle",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.IDLE",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x47",
-        "Unit": "UPI LL"
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : I State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.I",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PortMask": "0x100",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : SnoopFilter - S State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.SF_S",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PortMask": "0x200",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : SnoopFilter - E State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.SF_E",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : SnoopFilter - H State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.SF_H",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : S State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.S",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
         "UMask": "0x10",
-        "Unit": "CHA"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : E State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.E",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : M State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.M",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : F State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.F",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : RFO Requests",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.RFO",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x1BC8FF",
-        "UMaskExt": "0x1BC8",
-        "Unit": "CHA"
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : IRQ - iA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : SF/LLC Evictions",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.EVICT",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PortMask": "0x100",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : PRQ - IOSF",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PortMask": "0x200",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : IPQ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IPQ",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : IRQ - Non iA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : PRQ - Non IOSF",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x80",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : RRQ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.RRQ",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : WBQ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.WBQ",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
         "UMask": "0x80",
-        "Unit": "CHA"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : All from Local IO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0xC000FF04",
-        "UMaskExt": "0xC000FF",
-        "Unit": "CHA"
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : All from Local iA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0xC000FF01",
-        "UMaskExt": "0xC000FF",
-        "Unit": "CHA"
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : All from Local iA and IO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0xC000FF05",
-        "UMaskExt": "0xC000FF",
-        "Unit": "CHA"
+        "PortMask": "0x100",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : Just Hits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.HIT",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x01",
-        "Unit": "CHA"
+        "PortMask": "0x200",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : Just Misses",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.MISS",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x02",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.DDR",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.DDR4",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x04",
-        "Unit": "CHA"
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : MMCFG Access",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.MMCFG",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x20",
-        "Unit": "CHA"
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : Just Local Targets",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x80",
-        "Unit": "CHA"
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : Just Remote Targets",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.REMOTE_TGT",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x100",
-        "Unit": "CHA"
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x200",
-        "Unit": "CHA"
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x400",
-        "Unit": "CHA"
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : Just NearMem",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.NEARMEM",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x400000",
-        "Unit": "CHA"
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : Just NotNearMem",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x800000",
-        "Unit": "CHA"
+        "PortMask": "0x100",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : Just NonCoherent",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.NONCOH",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x1000000",
-        "Unit": "CHA"
+        "PortMask": "0x200",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : Just ISOC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.ISOC",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x2000000",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : IRQ - iA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : SF/LLC Evictions",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : PRQ - IOSF",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : IPQ",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : IRQ - Non iA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : PRQ - Non IOSF",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : All from Local IO",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0xC000FF04",
-        "UMaskExt": "0xC000FF",
-        "Unit": "CHA"
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : All from Local iA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0xC000FF01",
-        "UMaskExt": "0xC000FF",
-        "Unit": "CHA"
+        "PortMask": "0x100",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : All from Local iA and IO",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0xC000FF05",
-        "UMaskExt": "0xC000FF",
-        "Unit": "CHA"
+        "PortMask": "0x200",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : Just Hits",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x01",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : Just Misses",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x02",
-        "Unit": "CHA"
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : MMCFG Access",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x20",
-        "Unit": "CHA"
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : Just Local Targets",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x80",
-        "Unit": "CHA"
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : Just Remote Targets",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.REMOTE_TGT",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x100",
-        "Unit": "CHA"
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x200",
-        "Unit": "CHA"
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x400",
-        "Unit": "CHA"
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : Just NearMem",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x400000",
-        "Unit": "CHA"
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : Just NotNearMem",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x800000",
-        "Unit": "CHA"
+        "PortMask": "0x100",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : Just NonCoherent",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x1000000",
-        "Unit": "CHA"
+        "PortMask": "0x200",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : Just ISOC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x2000000",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x01",
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x01",
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU0",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x02",
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU1",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x02",
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU0",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x04",
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU1",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x04",
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU0",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x08",
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU1",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.IOMMU0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x200",
-        "UMask": "0x08",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU0",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x10",
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU1",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x10",
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU0",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x20",
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU1",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x20",
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU0",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x40",
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU1",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x40",
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU0",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x80",
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU1",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x80",
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU0",
+        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x100",
-        "UMask": "0x01",
+        "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU1",
+        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x200",
-        "UMask": "0x01",
+        "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU0",
+        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x02",
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU1",
+        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x02",
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU0",
+        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x04",
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU1",
+        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x04",
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU0",
+        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x08",
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU1",
+        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x08",
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU0",
+        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU1",
+        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Messages",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU0",
+        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x100",
-        "UMask": "0x40",
+        "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Messages",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU1",
+        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x200",
-        "UMask": "0x40",
+        "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU0",
+        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
         "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU1",
+        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
         "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU0",
+        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x01",
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU1",
+        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x01",
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.IOMMU0",
+        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x02",
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU0",
+        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x04",
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU1",
+        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x04",
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU0",
+        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x80",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x100",
-        "UMask": "0x08",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU1",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x200",
-        "UMask": "0x08",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU0",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x10",
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU1",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x10",
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU0",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x20",
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU1",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x20",
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU0",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x40",
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU1",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x40",
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU0",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x80",
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU1",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x80",
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x84",
         "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x100",
-        "UMask": "0x01",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x84",
         "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x200",
-        "UMask": "0x01",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
         "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU0",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x02",
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
         "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU1",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x02",
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
         "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU0",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x04",
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
         "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU1",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x04",
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
         "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU0",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x08",
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
         "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU1",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x08",
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
         "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU0",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x10",
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
         "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU1",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x10",
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "Number Transactions requested of the CPU : Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x84",
         "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x100",
+        "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
         "UMask": "0x40",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "Number Transactions requested of the CPU : Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x84",
         "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x200",
+        "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
         "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Number Transactions requested of the CPU : Messages",
         "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU0",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x80",
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Number Transactions requested of the CPU : Messages",
         "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU1",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x80",
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS",
-        "PerPkg": "1",
-        "UMaskExt": "0x20",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS",
-        "PerPkg": "1",
-        "UMaskExt": "0x0C",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "Prefetch CAM Cycles Full : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6B",
-        "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH0",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "Prefetch CAM Cycles Full : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6B",
-        "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH1",
-        "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "Prefetch CAM Cycles Full : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6B",
-        "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH2",
-        "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6C",
-        "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH0",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6C",
-        "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH1",
-        "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6C",
-        "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH2",
-        "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "Prefetch CAM Deallocs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA0_INVAL",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "Prefetch CAM Deallocs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA1_INVAL",
-        "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "Prefetch CAM Deallocs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_MISS_INVAL",
+        "BriefDescription": "Number Transactions requested of the CPU : Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Prefetch CAM Deallocs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_RSP_PDRESET",
+        "BriefDescription": "Number Transactions requested of the CPU : Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Prefetch CAM Deallocs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA0_INVAL",
+        "BriefDescription": "Number Transactions requested of the CPU : Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Prefetch CAM Deallocs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA1_INVAL",
+        "BriefDescription": "Number Transactions requested of the CPU : Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Prefetch CAM Deallocs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_MISS_INVAL",
+        "BriefDescription": "Number Transactions requested of the CPU : Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
         "UMask": "0x40",
-        "Unit": "M2M"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Prefetch CAM Deallocs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_RSP_PDRESET",
+        "BriefDescription": "Number Transactions requested of the CPU : Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M2M"
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Prefetch CAM Deallocs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA0_INVAL",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x01",
-        "Unit": "M2M"
+        "PortMask": "0x100",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Prefetch CAM Deallocs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA1_INVAL",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x02",
-        "Unit": "M2M"
+        "PortMask": "0x200",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Prefetch CAM Deallocs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_MISS_INVAL",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x04",
-        "Unit": "M2M"
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Prefetch CAM Deallocs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_RSP_PDRESET",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x08",
-        "Unit": "M2M"
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped : XPT - Ch 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6F",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped : UPI - Ch 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6F",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_UPI",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped : XPT - Ch 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6F",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped : UPI - Ch 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6F",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_UPI",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped : XPT - Ch 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6F",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_XPT",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped : UPI - Ch 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6F",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_UPI",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_SECURE_DROP",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PortMask": "0x100",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.NOT_PF_SAD_REGION",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PortMask": "0x200",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_HIT",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.STOP_B2B",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.ERRORBLK_RxC",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_AD_CRD",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_FULL",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.WPQ_PROXY",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M2M"
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.RPQ_PROXY",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x01",
-        "Unit": "M2M"
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.XPT_THRESH",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x02",
-        "Unit": "M2M"
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.UPI_THRESH",
+        "BriefDescription": "Total Write Cache Occupancy : Any Source",
+        "EventCode": "0x0F",
+        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
         "PerPkg": "1",
-        "UMaskExt": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Total Write Cache Occupancy : Any Source : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events. : Tracks all requests from any source port.",
+        "UMask": "0x1",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x71",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_SECURE_DROP",
+        "BriefDescription": "Total Write Cache Occupancy : Snoops",
+        "EventCode": "0x0F",
+        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Total Write Cache Occupancy : Snoops : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.",
+        "UMask": "0x2",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x71",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.NOT_PF_SAD_REGION",
+        "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.",
+        "EventCode": "0x0f",
+        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.  This is effectively the sum of read occupancy and write occupancy.",
+        "UMask": "0x4",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x71",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_HIT",
+        "BriefDescription": "Clockticks of the IO coherency tracker (IRP)",
+        "EventCode": "0x01",
+        "EventName": "UNC_I_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x71",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.STOP_B2B",
+        "BriefDescription": "Coherent Ops : CLFlush",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Coherent Ops : CLFlush : Counts the number of coherency related operations servied by the IRP",
+        "UMask": "0x80",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x71",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.ERRORBLK_RxC",
+        "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.PCITOM",
         "PerPkg": "1",
+        "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO.  PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x71",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_AD_CRD",
+        "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.RFO",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory.  RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.",
+        "UMask": "0x8",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x71",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_FULL",
+        "BriefDescription": "Coherent Ops : WbMtoI",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
         "PerPkg": "1",
+        "PublicDescription": "Coherent Ops : WbMtoI : Counts the number of coherency related operations servied by the IRP",
         "UMask": "0x40",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x71",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.WPQ_PROXY",
-        "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M2M"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x71",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.RPQ_PROXY",
+        "BriefDescription": "FAF RF full",
+        "EventCode": "0x17",
+        "EventName": "UNC_I_FAF_FULL",
         "PerPkg": "1",
-        "UMaskExt": "0x01",
-        "Unit": "M2M"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x71",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.XPT_THRESH",
+        "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.",
+        "EventCode": "0x18",
+        "EventName": "UNC_I_FAF_INSERTS",
         "PerPkg": "1",
-        "UMaskExt": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x71",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.UPI_THRESH",
+        "BriefDescription": "Occupancy of the IRP FAF queue.",
+        "EventCode": "0x19",
+        "EventName": "UNC_I_FAF_OCCUPANCY",
         "PerPkg": "1",
-        "UMaskExt": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x72",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_SECURE_DROP",
+        "BriefDescription": "FAF allocation -- sent to ADQ",
+        "EventCode": "0x16",
+        "EventName": "UNC_I_FAF_TRANSACTIONS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x72",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.NOT_PF_SAD_REGION",
+        "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
+        "EventCode": "0x20",
+        "EventName": "UNC_I_IRP_ALL.EVICTS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x4",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x72",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_HIT",
+        "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)",
+        "EventCode": "0x20",
+        "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "UMask": "0x1",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x72",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.STOP_B2B",
+        "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
+        "EventCode": "0x20",
+        "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "UMask": "0x2",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x72",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.ERRORBLK_RxC",
+        "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
+        "EventCode": "0x1E",
+        "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
         "PerPkg": "1",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x72",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_AD_CRD",
+        "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
+        "EventCode": "0x1e",
+        "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "UMask": "0x4",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x72",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_FULL",
+        "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
+        "EventCode": "0x1e",
+        "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "UMask": "0x8",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x72",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.WPQ_PROXY",
+        "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
+        "EventCode": "0x1E",
+        "EventName": "UNC_I_MISC0.FAST_REJ",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M2M"
+        "UMask": "0x2",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x72",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.RPQ_PROXY",
+        "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
+        "EventCode": "0x1e",
+        "EventName": "UNC_I_MISC0.FAST_REQ",
         "PerPkg": "1",
-        "UMaskExt": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x1",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x72",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.XPT_THRESH",
+        "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
+        "EventCode": "0x1E",
+        "EventName": "UNC_I_MISC0.FAST_XFER",
         "PerPkg": "1",
-        "UMaskExt": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x20",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x72",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.UPI_THRESH",
+        "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary",
+        "EventCode": "0x1E",
+        "EventName": "UNC_I_MISC0.PF_ACK_HINT",
         "PerPkg": "1",
-        "UMaskExt": "0x04",
-        "Unit": "M2M"
+        "UMask": "0x40",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT",
+        "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch",
+        "EventCode": "0x1E",
+        "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x80",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_UPI",
+        "BriefDescription": "Misc Events - Set 1 : Lost Forward",
+        "EventCode": "0x1F",
+        "EventName": "UNC_I_MISC1.LOST_FWD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed",
+        "UMask": "0x10",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT",
+        "BriefDescription": "Misc Events - Set 1 : Received Invalid",
+        "EventCode": "0x1F",
+        "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Misc Events - Set 1 : Received Invalid : Secondary received a transfer that did not have sufficient MESI state",
+        "UMask": "0x20",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_UPI",
+        "BriefDescription": "Misc Events - Set 1 : Received Valid",
+        "EventCode": "0x1F",
+        "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Misc Events - Set 1 : Received Valid : Secondary received a transfer that did have sufficient MESI state",
+        "UMask": "0x40",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_XPT",
+        "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line",
+        "EventCode": "0x1f",
+        "EventName": "UNC_I_MISC1.SLOW_E",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "Misc Events - Set 1 : Slow Transfer of E Line : Secondary received a transfer that did have sufficient MESI state",
+        "UMask": "0x4",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_UPI",
+        "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line",
+        "EventCode": "0x1f",
+        "EventName": "UNC_I_MISC1.SLOW_I",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "Misc Events - Set 1 : Slow Transfer of I Line : Snoop took cacheline ownership before write from data was committed.",
+        "UMask": "0x1",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Prefetch CAM Occupancy : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6A",
-        "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0",
+        "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line",
+        "EventCode": "0x1f",
+        "EventName": "UNC_I_MISC1.SLOW_M",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Misc Events - Set 1 : Slow Transfer of M Line : Snoop took cacheline ownership before write from data was committed.",
+        "UMask": "0x8",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Prefetch CAM Occupancy : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6A",
-        "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1",
+        "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line",
+        "EventCode": "0x1f",
+        "EventName": "UNC_I_MISC1.SLOW_S",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Misc Events - Set 1 : Slow Transfer of S Line : Secondary received a transfer that did not have sufficient MESI state",
+        "UMask": "0x2",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Prefetch CAM Occupancy : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6A",
-        "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH2",
+        "BriefDescription": "P2P Requests",
+        "EventCode": "0x14",
+        "EventName": "UNC_I_P2P_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "P2P Requests : P2P requests from the ITC",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": ": Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x76",
-        "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0",
+        "BriefDescription": "P2P Occupancy",
+        "EventCode": "0x15",
+        "EventName": "UNC_I_P2P_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "P2P Occupancy : P2P B & S Queue Occupancy",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": ": Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x76",
-        "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1",
+        "BriefDescription": "P2P Transactions : P2P completions",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x8",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": ": Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x76",
-        "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH2",
+        "BriefDescription": "P2P Transactions : match if local only",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.LOC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "UMask": "0x40",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7A",
-        "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
+        "BriefDescription": "P2P Transactions : match if local and target matches",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x80",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7A",
-        "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
+        "BriefDescription": "P2P Transactions : P2P Message",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.MSG",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x4",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7A",
-        "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
+        "BriefDescription": "P2P Transactions : P2P reads",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.RD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "UMask": "0x1",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR",
+        "BriefDescription": "P2P Transactions : Match if remote only",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.REM",
         "PerPkg": "1",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR",
+        "BriefDescription": "P2P Transactions : match if remote and target matches",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH",
         "PerPkg": "1",
         "UMask": "0x20",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "Write Tracker Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_NONTGR",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Write Tracker Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_PWR",
+        "BriefDescription": "P2P Transactions : P2P Writes",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.WR",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "UMask": "0x2",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
+        "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO",
+        "UMask": "0x7e",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
+        "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache",
+        "UMask": "0x74",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
+        "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache",
+        "UMask": "0x72",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
+        "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache",
+        "UMask": "0x78",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
+        "BriefDescription": "Responses to snoops of any type that miss the IIO cache",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.ALL_MISS",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that miss the IIO cache",
+        "UMask": "0x71",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
+        "BriefDescription": "Snoop Responses : Hit E or S",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "UMask": "0x4",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
+        "BriefDescription": "Snoop Responses : Hit I",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.HIT_I",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2PCIe"
+        "UMask": "0x2",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
+        "BriefDescription": "Snoop Responses : Hit M",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.HIT_M",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M2PCIe"
+        "UMask": "0x8",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
+        "BriefDescription": "Snoop Responses : Miss",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.MISS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "UMask": "0x1",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
+        "BriefDescription": "Snoop Responses : SnpCode",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "UMask": "0x10",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
+        "BriefDescription": "Snoop Responses : SnpData",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "UMask": "0x20",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
+        "BriefDescription": "Snoop Responses : SnpInv",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.SNPINV",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "UMask": "0x40",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB",
+        "BriefDescription": "Inbound Transaction Count : Atomic",
+        "EventCode": "0x11",
+        "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "Inbound Transaction Count : Atomic : Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of atomic transactions",
+        "UMask": "0x10",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS",
+        "BriefDescription": "Inbound Transaction Count : Other",
+        "EventCode": "0x11",
+        "EventName": "UNC_I_TRANSACTIONS.OTHER",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "Inbound Transaction Count : Other : Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of 'other' kinds of transactions.",
+        "UMask": "0x20",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB",
+        "BriefDescription": "Inbound Transaction Count : Writes",
+        "EventCode": "0x11",
+        "EventName": "UNC_I_TRANSACTIONS.WRITES",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "Inbound Transaction Count : Writes : Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Trackes only write requests.  Each write request should have a prefetch, so there is no need to explicitly track these requests.  For writes that are tickled and have to retry, the counter will be incremented for each retry.",
+        "UMask": "0x2",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS",
+        "BriefDescription": "Inbound write (fast path) requests received by the IRP.",
+        "EventCode": "0x11",
+        "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.",
+        "UMask": "0x8",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB",
+        "BriefDescription": "AK Egress Allocations",
+        "EventCode": "0x0B",
+        "EventName": "UNC_I_TxC_AK_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS",
+        "BriefDescription": "BL DRS Egress Cycles Full",
+        "EventCode": "0x05",
+        "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB",
+        "BriefDescription": "BL DRS Egress Inserts",
+        "EventCode": "0x02",
+        "EventName": "UNC_I_TxC_BL_DRS_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS",
+        "BriefDescription": "BL DRS Egress Occupancy",
+        "EventCode": "0x08",
+        "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1a",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB",
+        "BriefDescription": "BL NCB Egress Cycles Full",
+        "EventCode": "0x06",
+        "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1a",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS",
+        "BriefDescription": "BL NCB Egress Inserts",
+        "EventCode": "0x03",
+        "EventName": "UNC_I_TxC_BL_NCB_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1a",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB",
+        "BriefDescription": "BL NCB Egress Occupancy",
+        "EventCode": "0x09",
+        "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1a",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS",
+        "BriefDescription": "BL NCS Egress Cycles Full",
+        "EventCode": "0x07",
+        "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local P2P Shared Credits Returned : Agent0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x17",
-        "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0",
+        "BriefDescription": "BL NCS Egress Inserts",
+        "EventCode": "0x04",
+        "EventName": "UNC_I_TxC_BL_NCS_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local P2P Shared Credits Returned : Agent1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x17",
-        "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1",
+        "BriefDescription": "BL NCS Egress Occupancy",
+        "EventCode": "0x0A",
+        "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local P2P Shared Credits Returned : Agent2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x17",
-        "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2",
+        "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
+        "EventCode": "0x1C",
+        "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": ": Counts the number times when it is not possible to issue a request to the M2PCIe because there are no Egress Credits available on AD0, A1 or AD0&AD1 both. Stalls on both AD0 and AD1 will count as 2",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0",
+        "BriefDescription": "No AD0 Egress Credits Stalls",
+        "EventCode": "0x1A",
+        "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "No AD0 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD0 Egress Credits available.",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1",
+        "BriefDescription": "No AD1 Egress Credits Stalls",
+        "EventCode": "0x1B",
+        "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "No AD1 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD1 Egress Credits available.",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2",
+        "BriefDescription": "No BL Egress Credit Stalls",
+        "EventCode": "0x1D",
+        "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "No BL Egress Credit Stalls : Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3",
+        "BriefDescription": "Outbound Read Requests",
+        "EventCode": "0x0D",
+        "EventName": "UNC_I_TxS_DATA_INSERTS_NCB",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "BriefDescription": "Outbound Read Requests",
+        "EventCode": "0x0E",
+        "EventName": "UNC_I_TxS_DATA_INSERTS_NCS",
+        "PerPkg": "1",
+        "PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5",
+        "BriefDescription": "Outbound Request Queue Occupancy",
+        "EventCode": "0x0C",
+        "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "PublicDescription": "Outbound Request Queue Occupancy : Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices).  This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x40",
-        "Unit": "M2PCIe"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x80",
-        "Unit": "M2PCIe"
-    },
-    {
-        "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
+        "EventCode": "0x81",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
+        "EventCode": "0x81",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
+        "EventCode": "0x81",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4a",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4a",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4a",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4a",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4a",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4a",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4a",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x40",
-        "Unit": "M2PCIe"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4a",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x80",
-        "Unit": "M2PCIe"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4b",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
+        "EventCode": "0x83",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4b",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
+        "EventCode": "0x83",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4b",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
+        "EventCode": "0x83",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4b",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "P2P Credit Occupancy : Local NCB",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "P2P Credit Occupancy : Local NCS",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "P2P Credit Occupancy : Remote NCB",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR4",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR5",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR6",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x40",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR7",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x80",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "P2P Credit Occupancy : Remote NCS",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
+        "EventCode": "0x89",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "P2P Credit Occupancy : All",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
+        "EventCode": "0x89",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Dedicated Credits Received : Local NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x16",
-        "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
+        "EventCode": "0x89",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Dedicated Credits Received : Local NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x16",
-        "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Dedicated Credits Received : Remote NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x16",
-        "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Dedicated Credits Received : Remote NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x16",
-        "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Dedicated Credits Received : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x16",
-        "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Shared Credits  Received : Local NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Shared Credits  Received : Local NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Shared Credits  Received : Remote NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Shared Credits  Received : Remote NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x80",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Shared Credits  Received : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
+        "EventCode": "0x8B",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - DRS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x48",
-        "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_DRS",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
+        "EventCode": "0x8B",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x48",
-        "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCB",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
+        "EventCode": "0x8B",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x48",
-        "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCS",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - DRS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x48",
-        "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_DRS",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x48",
-        "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCB",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x48",
-        "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCS",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - DRS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x49",
-        "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_DRS",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x49",
-        "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCB",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x49",
-        "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCS",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1b",
-        "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCB",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x80",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1b",
-        "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCS",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
+        "EventCode": "0x85",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1b",
-        "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCB",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
+        "EventCode": "0x85",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1b",
-        "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCS",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
+        "EventCode": "0x85",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1b",
-        "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCB",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1b",
-        "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCS",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote P2P Shared Credits Returned : Agent0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote P2P Shared Credits Returned : Agent1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote P2P Shared Credits Returned : Agent2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x80",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - DRS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_DRS",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
+        "EventCode": "0x87",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCB",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
+        "EventCode": "0x87",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCS",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
+        "EventCode": "0x87",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - DRS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_DRS",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCB",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCS",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - DRS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_DRS",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCB",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCS",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - DRS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4c",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_DRS",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4c",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCB",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x80",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4c",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCS",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
+        "EventCode": "0x8D",
+        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - DRS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4c",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_DRS",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
+        "EventCode": "0x8D",
+        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4c",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCB",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
+        "EventCode": "0x8D",
+        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4c",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCS",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - DRS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4d",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_DRS",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4d",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCB",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4d",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCS",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Inserts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x80",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Inserts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
+        "EventCode": "0x8F",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Inserts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
+        "EventCode": "0x8F",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2d",
-        "EventName": "UNC_M2P_TxC_CREDITS.PRQ",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
+        "EventCode": "0x8F",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4D",
-        "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB",
+        "BriefDescription": "M2M to iMC Bypass : Not Taken",
+        "EventCode": "0x22",
+        "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.NOT_TAKEN",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "UBOX"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4D",
-        "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS",
+        "BriefDescription": "M2M to iMC Bypass : Taken",
+        "EventCode": "0x22",
+        "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.TAKEN",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "UBOX"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4D",
-        "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB",
+        "BriefDescription": "M2M to iMC Bypass : Not Taken",
+        "EventCode": "0x21",
+        "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "UBOX"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4D",
-        "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS",
+        "BriefDescription": "M2M to iMC Bypass : Taken",
+        "EventCode": "0x21",
+        "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "UBOX"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4D",
-        "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB",
+        "BriefDescription": "Clockticks of the mesh to memory (M2M)",
+        "EventName": "UNC_M2M_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "UBOX"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4D",
-        "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS",
+        "BriefDescription": "CMS Clockticks",
+        "EventCode": "0xc0",
+        "EventName": "UNC_M2M_CMS_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "UBOX"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4D",
-        "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB",
+        "BriefDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled",
+        "EventCode": "0x24",
+        "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "UBOX"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4D",
-        "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS",
+        "BriefDescription": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
+        "EventCode": "0x60",
+        "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "UBOX"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4E",
-        "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
+        "BriefDescription": "Number of reads in which direct to core transaction was overridden",
+        "EventCode": "0x25",
+        "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "UBOX"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4E",
-        "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
+        "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden",
+        "EventCode": "0x28",
+        "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "UBOX"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4E",
-        "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB",
+        "BriefDescription": "Cycles when Direct2UPI was Disabled",
+        "EventCode": "0x27",
+        "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "UBOX"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4E",
-        "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS",
+        "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden",
+        "EventCode": "0x29",
+        "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "UBOX"
+        "PublicDescription": "Clockticks of the mesh to PCI (M2P)",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4E",
-        "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
+        "BriefDescription": "Directory Hit : On NonDirty Line in A State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "UBOX"
+        "UMask": "0x80",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4E",
-        "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK",
+        "BriefDescription": "Directory Hit : On NonDirty Line in I State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "UBOX"
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4E",
-        "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC",
+        "BriefDescription": "Directory Hit : On NonDirty Line in L State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P",
         "PerPkg": "1",
         "UMask": "0x40",
-        "Unit": "UBOX"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4E",
-        "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL",
+        "BriefDescription": "Directory Hit : On NonDirty Line in S State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "UBOX"
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4F",
-        "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK",
+        "BriefDescription": "Directory Hit : On Dirty Line in A State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "UBOX"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4F",
-        "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC",
+        "BriefDescription": "Directory Hit : On Dirty Line in I State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "UBOX"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "Directory Hit : On Dirty Line in L State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR1",
+        "BriefDescription": "Directory Hit : On Dirty Line in S State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in any state",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in A state",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in I state",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in S state",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "Directory Miss : On NonDirty Line in A State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "UMask": "0x80",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "Directory Miss : On NonDirty Line in I State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x81",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "Directory Miss : On NonDirty Line in L State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x81",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "Directory Miss : On NonDirty Line in S State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x81",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "Directory Miss : On Dirty Line in A State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR0",
+        "BriefDescription": "Directory Miss : On Dirty Line in I State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "Directory Miss : On Dirty Line in L State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "Directory Miss : On Dirty Line in S State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode.",
+        "EventCode": "0x2e",
+        "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "Distress signal asserted : DPT Local",
+        "EventCode": "0xAF",
+        "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "Distress signal asserted : DPT Remote",
+        "EventCode": "0xAF",
+        "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_NONLOCAL",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
+        "EventCode": "0xAF",
+        "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_IV",
         "PerPkg": "1",
+        "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
         "UMask": "0x40",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "Distress signal asserted : DPT Stalled -  No Credit",
+        "EventCode": "0xAF",
+        "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
         "PerPkg": "1",
+        "PublicDescription": "Distress signal asserted : DPT Stalled -  No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
         "UMask": "0x80",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "Distress signal asserted : Horizontal",
+        "EventCode": "0xAF",
+        "EventName": "UNC_M2M_DISTRESS_ASSERTED.HORZ",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "Distress signal asserted : PMM Local",
+        "EventCode": "0xAF",
+        "EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "Distress signal asserted : PMM Remote",
+        "EventCode": "0xAF",
+        "EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_NONLOCAL",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "Distress signal asserted : Vertical",
+        "EventCode": "0xAF",
+        "EventName": "UNC_M2M_DISTRESS_ASSERTED.VERT",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR1",
+        "BriefDescription": "UNC_M2M_DISTRESS_PMM",
+        "EventCode": "0xF2",
+        "EventName": "UNC_M2M_DISTRESS_PMM",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "UNC_M2M_DISTRESS_PMM_MEMMODE",
+        "EventCode": "0xF1",
+        "EventName": "UNC_M2M_DISTRESS_PMM_MEMMODE",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+        "EventCode": "0xBA",
+        "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+        "EventCode": "0xBA",
+        "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
+        "EventCode": "0xB6",
+        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
+        "EventCode": "0xB6",
+        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
+        "EventCode": "0xB6",
+        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x89",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
+        "EventCode": "0xB6",
+        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x89",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+        "EventCode": "0xBB",
+        "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x89",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+        "EventCode": "0xBB",
+        "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR0",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+        "EventCode": "0xBB",
+        "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+        "EventCode": "0xBB",
+        "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+        "EventCode": "0xB7",
+        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+        "EventCode": "0xB7",
+        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+        "EventCode": "0xB7",
+        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+        "EventCode": "0xB7",
+        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8B",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8B",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8B",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "Horizontal IV Ring in Use : Left",
+        "EventCode": "0xB9",
+        "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "Horizontal IV Ring in Use : Right",
+        "EventCode": "0xB9",
+        "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR1",
+        "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - All Channels",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x704",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch0",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.CH0_ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x104",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch0",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "UMask": "0x140",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch0",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "UMask": "0x102",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch0",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "UMask": "0x101",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - Ch0",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "UMask": "0x110",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "M2M Reads Issued to iMC : DDR - Ch0",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "UMask": "0x108",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "M2M Reads Issued to iMC : PMM - Ch0",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.CH0_TO_PMM",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "M2M Reads Issued to iMC : PMM - Ch0 : Counts all PMM dimm read requests(full line) sent from M2M to iMC",
+        "UMask": "0x120",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch1",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.CH1_ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x204",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch1",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x240",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR0",
+        "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch1",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x202",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch1",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x201",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - Ch1",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x210",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "M2M Reads Issued to iMC : DDR - Ch1",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "UMask": "0x208",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "M2M Reads Issued to iMC : PMM - Ch1",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.CH1_TO_PMM",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PublicDescription": "M2M Reads Issued to iMC : PMM - Ch1 : Counts all PMM dimm read requests(full line) sent from M2M to iMC",
+        "UMask": "0x220",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch2",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.CH2_FROM_TGR",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "UMask": "0x440",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "M2M Reads Issued to iMC : From TGR - All Channels",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.FROM_TGR",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "UMask": "0x740",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - All Channels",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.ISOCH",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "UMask": "0x702",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - All Channels",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.NORMAL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x701",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - All Channels",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_CACHE",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x710",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "M2M Reads Issued to iMC : DDR - All Channels",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_MEM",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x708",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "M2M Reads Issued to iMC : PMM - All Channels",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.TO_PMM",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x720",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR1",
+        "BriefDescription": "M2M Writes Issued to iMC : All Writes - All Channels",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x1c10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch0",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x410",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch0",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch0",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "UMask": "0x401",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch0",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "UMask": "0x404",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch0",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH0_NI",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch0",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8D",
-        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch0",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x402",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8D",
-        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch0",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x408",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8D",
-        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - Ch0",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_CACHE",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x440",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR0",
+        "BriefDescription": "M2M Writes Issued to iMC : DDR - Ch0",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x420",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "M2M Writes Issued to iMC : PMM - Ch0",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_PMM",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PublicDescription": "M2M Writes Issued to iMC : PMM - Ch0 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC",
+        "UMask": "0x480",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch1",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x810",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch1",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch1",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "UMask": "0x801",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch1",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "UMask": "0x804",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch1",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH1_NI",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch1",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8F",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch1",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x802",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8F",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch1",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x808",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8F",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - Ch1",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_CACHE",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x840",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Distress signal asserted : Vertical",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_CHA_DISTRESS_ASSERTED.VERT",
+        "BriefDescription": "M2M Writes Issued to iMC : DDR - Ch1",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_MEM",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x820",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Distress signal asserted : Horizontal",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_CHA_DISTRESS_ASSERTED.HORZ",
+        "BriefDescription": "M2M Writes Issued to iMC : PMM - Ch1",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_PMM",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PublicDescription": "M2M Writes Issued to iMC : PMM - Ch1 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC",
+        "UMask": "0x880",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Local",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_LOCAL",
+        "BriefDescription": "M2M Writes Issued to iMC : From TGR - All Channels",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Remote",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_NONLOCAL",
+        "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - All Channels",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.FULL",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "UMask": "0x1c01",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_IV",
+        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - All Channels",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "UMask": "0x1c04",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Stalled -  No Credit",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
+        "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - All Channels",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.NI",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBA",
-        "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
+        "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - All Channels",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.NI_MISS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBA",
-        "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
+        "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - All Channels",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.PARTIAL",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x1c02",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB6",
-        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - All Channels",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x1c08",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB6",
-        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD",
+        "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - All Channels",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_CACHE",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x1c40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB6",
-        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "M2M Writes Issued to iMC : DDR - All Channels",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_MEM",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x1c20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB6",
-        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+        "BriefDescription": "M2M Writes Issued to iMC : PMM - All Channels",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.TO_PMM",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "UMask": "0x1c80",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBB",
-        "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Write Tracker Inserts",
+        "EventCode": "0x64",
+        "EventName": "UNC_M2M_MIRR_WRQ_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBB",
-        "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_ODD",
+        "BriefDescription": "Write Tracker Occupancy",
+        "EventCode": "0x65",
+        "EventName": "UNC_M2M_MIRR_WRQ_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBB",
-        "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
+        "EventCode": "0xE6",
+        "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBB",
-        "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
+        "EventCode": "0xE6",
+        "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB7",
-        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Number Packet Header Matches : MC Match",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M2M_PKT_MATCH.MC",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB7",
-        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD",
+        "BriefDescription": "Number Packet Header Matches : Mesh Match",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M2M_PKT_MATCH.MESH",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB7",
-        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS",
+        "EventCode": "0x73",
+        "EventName": "UNC_M2M_PREFCAM_CIS_DROPS",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB7",
-        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Prefetch CAM Cycles Full : All Channels",
+        "EventCode": "0x6B",
+        "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.ALLCH",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "UMask": "0x7",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB8",
-        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Prefetch CAM Cycles Full : Channel 0",
+        "EventCode": "0x6B",
+        "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB8",
-        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD",
+        "BriefDescription": "Prefetch CAM Cycles Full : Channel 1",
+        "EventCode": "0x6B",
+        "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB8",
-        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Prefetch CAM Cycles Full : Channel 2",
+        "EventCode": "0x6B",
+        "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH2",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB8",
-        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Prefetch CAM Cycles Not Empty : All Channels",
+        "EventCode": "0x6C",
+        "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.ALLCH",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "UMask": "0x7",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use : Left",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB9",
-        "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT",
+        "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 0",
+        "EventCode": "0x6C",
+        "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use : Right",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB9",
-        "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT",
+        "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 1",
+        "EventCode": "0x6C",
+        "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH1",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE6",
-        "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST0",
+        "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 2",
+        "EventCode": "0x6C",
+        "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH2",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE6",
-        "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST1",
+        "BriefDescription": "Prefetch CAM Deallocs",
+        "EventCode": "0x6E",
+        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA0_INVAL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAC",
-        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD",
+        "BriefDescription": "Prefetch CAM Deallocs",
+        "EventCode": "0x6E",
+        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA1_INVAL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAC",
-        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK",
+        "BriefDescription": "Prefetch CAM Deallocs",
+        "EventCode": "0x6E",
+        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_MISS_INVAL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAC",
-        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL",
+        "BriefDescription": "Prefetch CAM Deallocs",
+        "EventCode": "0x6E",
+        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_RSP_PDRESET",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAC",
-        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV",
+        "BriefDescription": "Prefetch CAM Deallocs",
+        "EventCode": "0x6E",
+        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA0_INVAL",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAA",
-        "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD",
+        "BriefDescription": "Prefetch CAM Deallocs",
+        "EventCode": "0x6E",
+        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA1_INVAL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAA",
-        "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK",
+        "BriefDescription": "Prefetch CAM Deallocs",
+        "EventCode": "0x6E",
+        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_MISS_INVAL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAA",
-        "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL",
+        "BriefDescription": "Prefetch CAM Deallocs",
+        "EventCode": "0x6E",
+        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_RSP_PDRESET",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x80",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAA",
-        "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV",
+        "BriefDescription": "Prefetch CAM Deallocs",
+        "EventCode": "0x6E",
+        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA0_INVAL",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAA",
-        "EventName": "UNC_CHA_RING_BOUNCES_VERT.AKC",
+        "BriefDescription": "Prefetch CAM Deallocs",
+        "EventCode": "0x6E",
+        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA1_INVAL",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAD",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD",
+        "BriefDescription": "Prefetch CAM Deallocs",
+        "EventCode": "0x6E",
+        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_MISS_INVAL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAD",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK",
+        "BriefDescription": "Prefetch CAM Deallocs",
+        "EventCode": "0x6E",
+        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_RSP_PDRESET",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAD",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL",
+        "BriefDescription": "Data Prefetches Dropped : UPI - Ch 0",
+        "EventCode": "0x6F",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_UPI",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAD",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV",
+        "BriefDescription": "Data Prefetches Dropped : XPT - Ch 0",
+        "EventCode": "0x6F",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAD",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1",
+        "BriefDescription": "Data Prefetches Dropped : UPI - Ch 1",
+        "EventCode": "0x6F",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_UPI",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAB",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD",
+        "BriefDescription": "Data Prefetches Dropped : XPT - Ch 1",
+        "EventCode": "0x6F",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAB",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK",
+        "BriefDescription": "Data Prefetches Dropped : UPI - Ch 2",
+        "EventCode": "0x6F",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_UPI",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAB",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL",
+        "BriefDescription": "Data Prefetches Dropped : XPT - Ch 2",
+        "EventCode": "0x6F",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_XPT",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAB",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV",
+        "BriefDescription": "Data Prefetches Dropped : UPI - All Channels",
+        "EventCode": "0x6f",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.UPI_ALLCH",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "UMask": "0x2a",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAB",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AKC",
+        "BriefDescription": "Data Prefetches Dropped : XPT - All Channels",
+        "EventCode": "0x6f",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "UMask": "0x15",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_UNCRD",
+        "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 0",
+        "EventCode": "0x74",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPTUPI",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 0",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_UNCRD",
+        "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 1",
+        "EventCode": "0x74",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPTUPI",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 1",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD",
+        "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 2",
+        "EventCode": "0x74",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH2_XPTUPI",
         "PerPkg": "1",
+        "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 2",
         "UMask": "0x10",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD",
+        "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- All Channels",
+        "EventCode": "0x74",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPTUPI_ALLCH",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - All Channels",
+        "UMask": "0x15",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_ALL",
+        "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 0",
+        "EventCode": "0x75",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPTUPI",
         "PerPkg": "1",
-        "UMask": "0x11",
-        "Unit": "CHA"
+        "PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 0",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_ALL",
+        "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 1",
+        "EventCode": "0x75",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPTUPI",
         "PerPkg": "1",
-        "UMask": "0x44",
-        "Unit": "CHA"
+        "PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 1",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_CHA_RxR_BYPASS.AD_UNCRD",
+        "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 2",
+        "EventCode": "0x75",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH2_XPTUPI",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_CHA_RxR_BYPASS.AK",
+        "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - All Channels",
+        "EventCode": "0x75",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPTUPI_ALLCH",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x15",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_CHA_RxR_BYPASS.BL_UNCRD",
+        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+        "EventCode": "0x70",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.ERRORBLK_RxC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_CHA_RxR_BYPASS.IV",
+        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+        "EventCode": "0x70",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.NOT_PF_SAD_REGION",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD",
+        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+        "EventCode": "0x70",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD",
+        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+        "EventCode": "0x70",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_FULL",
         "PerPkg": "1",
         "UMask": "0x40",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_CHA_RxR_BYPASS.AKC_UNCRD",
+        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+        "EventCode": "0x70",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_HIT",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_CHA_RxR_BYPASS.AD_ALL",
+        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+        "EventCode": "0x70",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_SECURE_DROP",
         "PerPkg": "1",
-        "UMask": "0x11",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_CHA_RxR_BYPASS.BL_ALL",
+        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+        "EventCode": "0x70",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.RPQ_PROXY",
         "PerPkg": "1",
-        "UMask": "0x44",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_UNCRD",
+        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+        "EventCode": "0x70",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.STOP_B2B",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.AK",
+        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+        "EventCode": "0x70",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.UPI_THRESH",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_UNCRD",
+        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+        "EventCode": "0x70",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.WPQ_PROXY",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x80",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.IV",
+        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+        "EventCode": "0x70",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.XPT_THRESH",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD",
+        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+        "EventCode": "0x71",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.ERRORBLK_RxC",
         "PerPkg": "1",
         "UMask": "0x10",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD",
+        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+        "EventCode": "0x71",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.NOT_PF_SAD_REGION",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV",
+        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+        "EventCode": "0x71",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_ALL",
+        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+        "EventCode": "0x71",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_FULL",
         "PerPkg": "1",
-        "UMask": "0x11",
-        "Unit": "CHA"
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_ALL",
+        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+        "EventCode": "0x71",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_HIT",
         "PerPkg": "1",
-        "UMask": "0x44",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_CHA_RxR_INSERTS.AD_UNCRD",
+        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+        "EventCode": "0x71",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_SECURE_DROP",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_CHA_RxR_INSERTS.AK",
+        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+        "EventCode": "0x71",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.RPQ_PROXY",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_CHA_RxR_INSERTS.BL_UNCRD",
+        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+        "EventCode": "0x71",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.STOP_B2B",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_CHA_RxR_INSERTS.IV",
+        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+        "EventCode": "0x71",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.UPI_THRESH",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD",
+        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+        "EventCode": "0x71",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.WPQ_PROXY",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "UMask": "0x80",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD",
+        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+        "EventCode": "0x71",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.XPT_THRESH",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_CHA_RxR_INSERTS.AKC_UNCRD",
+        "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+        "EventCode": "0x72",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.ERRORBLK_RxC",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_CHA_RxR_INSERTS.AD_ALL",
+        "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+        "EventCode": "0x72",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.NOT_PF_SAD_REGION",
         "PerPkg": "1",
-        "UMask": "0x11",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_CHA_RxR_INSERTS.BL_ALL",
+        "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+        "EventCode": "0x72",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
-        "Unit": "CHA"
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_UNCRD",
+        "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+        "EventCode": "0x72",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_FULL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.AK",
+        "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+        "EventCode": "0x72",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_HIT",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_UNCRD",
+        "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+        "EventCode": "0x72",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_SECURE_DROP",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.IV",
+        "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+        "EventCode": "0x72",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.RPQ_PROXY",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD",
+        "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+        "EventCode": "0x72",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.STOP_B2B",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD",
+        "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+        "EventCode": "0x72",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.UPI_THRESH",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.AKC_UNCRD",
+        "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+        "EventCode": "0x72",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.WPQ_PROXY",
         "PerPkg": "1",
         "UMask": "0x80",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_ALL",
+        "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+        "EventCode": "0x72",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.XPT_THRESH",
         "PerPkg": "1",
-        "UMask": "0x11",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_ALL",
+        "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0",
+        "EventCode": "0x6D",
+        "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_UPI",
         "PerPkg": "1",
-        "UMask": "0x44",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+        "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0",
+        "EventCode": "0x6D",
+        "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+        "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 1",
+        "EventCode": "0x6D",
+        "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_UPI",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+        "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1",
+        "EventCode": "0x6D",
+        "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+        "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 2",
+        "EventCode": "0x6D",
+        "EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_UPI",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+        "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 2",
+        "EventCode": "0x6D",
+        "EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_XPT",
         "PerPkg": "1",
         "UMask": "0x10",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+        "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels",
+        "EventCode": "0x6d",
+        "EventName": "UNC_M2M_PREFCAM_INSERTS.UPI_ALLCH",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "UMask": "0x2a",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
+        "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels",
+        "EventCode": "0x6D",
+        "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "UMask": "0x15",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
+        "BriefDescription": "Prefetch CAM Occupancy : All Channels",
+        "EventCode": "0x6A",
+        "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "UMask": "0x7",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+        "BriefDescription": "Prefetch CAM Occupancy : Channel 0",
+        "EventCode": "0x6A",
+        "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+        "BriefDescription": "Prefetch CAM Occupancy : Channel 1",
+        "EventCode": "0x6A",
+        "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+        "BriefDescription": "Prefetch CAM Occupancy : Channel 2",
+        "EventCode": "0x6A",
+        "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH2",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+        "BriefDescription": ": All Channels",
+        "EventCode": "0x76",
+        "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "UMask": "0x7",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+        "BriefDescription": ": Channel 0",
+        "EventCode": "0x76",
+        "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+        "BriefDescription": ": Channel 1",
+        "EventCode": "0x76",
+        "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
+        "BriefDescription": ": Channel 2",
+        "EventCode": "0x76",
+        "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH2",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
+        "BriefDescription": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
+        "EventCode": "0x79",
+        "EventName": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+        "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
+        "EventCode": "0x7A",
+        "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+        "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
+        "EventCode": "0x7A",
+        "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT",
+        "EventCode": "0x7A",
+        "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+        "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
+        "EventCode": "0x7A",
+        "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+        "BriefDescription": "UNC_M2M_PREFCAM_RxC_INSERTS",
+        "EventCode": "0x78",
+        "EventName": "UNC_M2M_PREFCAM_RxC_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+        "BriefDescription": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
+        "EventCode": "0x77",
+        "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
+        "EventCode": "0xAC",
+        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
+        "EventCode": "0xAC",
+        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
+        "EventCode": "0xAC",
+        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
+        "EventCode": "0xAC",
+        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M2M_RING_BOUNCES_VERT.AKC",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
+        "EventCode": "0xAD",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
+        "EventCode": "0xAD",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD1",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
+        "EventCode": "0xAD",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD1",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
+        "EventCode": "0xAD",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD1",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
+        "EventCode": "0xAD",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD3",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+        "BriefDescription": "Sink Starvation on Vertical Ring : AD",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD3",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+        "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD3",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+        "BriefDescription": "Sink Starvation on Vertical Ring",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AKC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD5",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+        "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD5",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+        "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD5",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+        "BriefDescription": "Source Throttle",
+        "EventCode": "0xae",
+        "EventName": "UNC_M2M_RING_SRC_THRTL",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD7",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 0",
+        "EventCode": "0x43",
+        "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD7",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 1",
+        "EventCode": "0x43",
+        "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD7",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 2",
+        "EventCode": "0x43",
+        "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH2",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_UNCRD",
+        "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 0",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_UNCRD",
+        "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 1",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN1",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD",
+        "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 2",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN2",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD",
+        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 0",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH0",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_ALL",
+        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 1",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH1",
         "PerPkg": "1",
-        "UMask": "0x11",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_ALL",
+        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 2",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH2",
         "PerPkg": "1",
-        "UMask": "0x44",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_UNCRD",
+        "BriefDescription": "AD Ingress (from CMS) Full",
+        "EventCode": "0x04",
+        "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK",
+        "BriefDescription": "AD Ingress (from CMS) Not Empty",
+        "EventCode": "0x03",
+        "EventName": "UNC_M2M_RxC_AD_CYCLES_NE",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_UNCRD",
+        "BriefDescription": "AD Ingress (from CMS) Allocations",
+        "EventCode": "0x01",
+        "EventName": "UNC_M2M_RxC_AD_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV",
+        "BriefDescription": "AD Ingress (from CMS) Occupancy",
+        "EventCode": "0x02",
+        "EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD",
+        "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches",
+        "EventCode": "0x77",
+        "EventName": "UNC_M2M_RxC_AD_PREF_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD",
+        "BriefDescription": "AK Egress (to CMS) Allocations",
+        "EventCode": "0x5C",
+        "EventName": "UNC_M2M_RxC_AK_WR_CMP",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AKC_UNCRD",
+        "BriefDescription": "BL Ingress (from CMS) Full",
+        "EventCode": "0x08",
+        "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_ALL",
+        "BriefDescription": "BL Ingress (from CMS) Not Empty",
+        "EventCode": "0x07",
+        "EventName": "UNC_M2M_RxC_BL_CYCLES_NE",
         "PerPkg": "1",
-        "UMask": "0x11",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_ALL",
+        "BriefDescription": "BL Ingress (from CMS) Allocations",
+        "EventCode": "0x05",
+        "EventName": "UNC_M2M_RxC_BL_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x44",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
+        "BriefDescription": "BL Ingress (from CMS) Occupancy",
+        "EventCode": "0x06",
+        "EventName": "UNC_M2M_RxC_BL_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK",
+        "BriefDescription": "Transgress Injection Starvation : AD - All",
+        "EventCode": "0xE5",
+        "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+        "UMask": "0x11",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
+        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+        "EventCode": "0xE5",
+        "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV",
+        "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+        "EventCode": "0xE5",
+        "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD",
+        "BriefDescription": "Transgress Injection Starvation : BL - All",
+        "EventCode": "0xE5",
+        "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+        "UMask": "0x44",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD",
+        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
+        "EventCode": "0xE5",
+        "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
         "UMask": "0x40",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
+        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+        "EventCode": "0xE5",
+        "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_ALL",
+        "BriefDescription": "Transgress Ingress Bypass : AD - All",
+        "EventCode": "0xE2",
+        "EventName": "UNC_M2M_RxR_BYPASS.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
         "UMask": "0x11",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_ALL",
-        "PerPkg": "1",
-        "UMask": "0x44",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_UNCRD",
+        "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
+        "EventCode": "0xE2",
+        "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK",
+        "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
+        "EventCode": "0xE2",
+        "EventName": "UNC_M2M_RxR_BYPASS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_UNCRD",
+        "BriefDescription": "Transgress Ingress Bypass : AK",
+        "EventCode": "0xE2",
+        "EventName": "UNC_M2M_RxR_BYPASS.AK",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV",
+        "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
+        "EventCode": "0xE2",
+        "EventName": "UNC_M2M_RxR_BYPASS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x80",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD",
+        "BriefDescription": "Transgress Ingress Bypass : BL - All",
+        "EventCode": "0xE2",
+        "EventName": "UNC_M2M_RxR_BYPASS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+        "UMask": "0x44",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD",
+        "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
+        "EventCode": "0xE2",
+        "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
         "UMask": "0x40",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
+        "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
+        "EventCode": "0xE2",
+        "EventName": "UNC_M2M_RxR_BYPASS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_ALL",
+        "BriefDescription": "Transgress Ingress Bypass : IV",
+        "EventCode": "0xE2",
+        "EventName": "UNC_M2M_RxR_BYPASS.IV",
         "PerPkg": "1",
-        "UMask": "0x11",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_ALL",
+        "BriefDescription": "Transgress Injection Starvation : AD - All",
+        "EventCode": "0xE3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x44",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+        "UMask": "0x11",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_UNCRD",
+        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+        "EventCode": "0xE3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK",
+        "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+        "EventCode": "0xE3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_UNCRD",
+        "BriefDescription": "Transgress Injection Starvation : AK",
+        "EventCode": "0xE3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.AK",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV",
+        "BriefDescription": "Transgress Injection Starvation : BL - All",
+        "EventCode": "0xE3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+        "UMask": "0x44",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD",
+        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
+        "EventCode": "0xE3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD",
+        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+        "EventCode": "0xE3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AKC_UNCRD",
+        "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
+        "EventCode": "0xE3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
         "UMask": "0x80",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_ALL",
+        "BriefDescription": "Transgress Injection Starvation : IV",
+        "EventCode": "0xE3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.IV",
         "PerPkg": "1",
-        "UMask": "0x11",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_ALL",
+        "BriefDescription": "Transgress Injection Starvation",
+        "EventCode": "0xe4",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED_1",
         "PerPkg": "1",
-        "UMask": "0x44",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_UNCRD",
+        "BriefDescription": "Transgress Ingress Allocations : AD - All",
+        "EventCode": "0xE1",
+        "EventName": "UNC_M2M_RxR_INSERTS.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x11",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.AK",
+        "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
+        "EventCode": "0xE1",
+        "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_UNCRD",
+        "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
+        "EventCode": "0xE1",
+        "EventName": "UNC_M2M_RxR_INSERTS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.IV",
+        "BriefDescription": "Transgress Ingress Allocations : AK",
+        "EventCode": "0xE1",
+        "EventName": "UNC_M2M_RxR_INSERTS.AK",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD",
+        "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
+        "EventCode": "0xE1",
+        "EventName": "UNC_M2M_RxR_INSERTS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x80",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD",
+        "BriefDescription": "Transgress Ingress Allocations : BL - All",
+        "EventCode": "0xE1",
+        "EventName": "UNC_M2M_RxR_INSERTS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x44",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.AKC_UNCRD",
+        "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
+        "EventCode": "0xE1",
+        "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_ALL",
+        "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
+        "EventCode": "0xE1",
+        "EventName": "UNC_M2M_RxR_INSERTS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x11",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_ALL",
+        "BriefDescription": "Transgress Ingress Allocations : IV",
+        "EventCode": "0xE1",
+        "EventName": "UNC_M2M_RxR_INSERTS.IV",
         "PerPkg": "1",
-        "UMask": "0x44",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_UNCRD",
+        "BriefDescription": "Transgress Ingress Occupancy : AD - All",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x11",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK",
+        "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_UNCRD",
+        "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV",
+        "BriefDescription": "Transgress Ingress Occupancy : AK",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.AK",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD",
+        "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x80",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD",
+        "BriefDescription": "Transgress Ingress Occupancy : BL - All",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x44",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
+        "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_ALL",
+        "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x11",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_ALL",
+        "BriefDescription": "Transgress Ingress Occupancy : IV",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.IV",
         "PerPkg": "1",
-        "UMask": "0x44",
-        "Unit": "CHA"
+        "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_UNCRD",
+        "BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS",
+        "EventCode": "0x33",
+        "EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK",
+        "BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS",
+        "EventCode": "0x34",
+        "EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_UNCRD",
+        "BriefDescription": "Retry - Mem Mirroring Mode",
+        "EventCode": "0x35",
+        "EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_ACCEPTS",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV",
+        "BriefDescription": "Retry - Mem Mirroring Mode",
+        "EventCode": "0x36",
+        "EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_REJECTS",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_CHA_TxR_HORZ_STARVED.AKC_UNCRD",
+        "BriefDescription": "Scoreboard Accepts",
+        "EventCode": "0x2F",
+        "EventName": "UNC_M2M_SCOREBOARD_RD_ACCEPTS",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_ALL",
+        "BriefDescription": "Scoreboard Rejects",
+        "EventCode": "0x30",
+        "EventName": "UNC_M2M_SCOREBOARD_RD_REJECTS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_ALL",
+        "BriefDescription": "Scoreboard Accepts",
+        "EventCode": "0x31",
+        "EventName": "UNC_M2M_SCOREBOARD_WR_ACCEPTS",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9C",
-        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0",
+        "BriefDescription": "Scoreboard Rejects",
+        "EventCode": "0x32",
+        "EventName": "UNC_M2M_SCOREBOARD_WR_REJECTS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9C",
-        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9C",
-        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9C",
-        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV_AG1",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x80",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9E",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG0",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9E",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG1",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG0",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG0",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG0",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.IV_AG0",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x80",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG1",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG1",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG1",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x95",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG0",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x95",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG1",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG0",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG0",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG0",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x80",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.IV_AG0",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG1",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG1",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG1",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x97",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG0",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x97",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG1",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG0",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x80",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG0",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
+        "EventCode": "0xD1",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG0",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
+        "EventCode": "0xD1",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.IV_AG0",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
+        "EventCode": "0xD1",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG1",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
+        "EventCode": "0xD3",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG1",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
+        "EventCode": "0xD3",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG1",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
+        "EventCode": "0xD3",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x93",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG0",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
+        "EventCode": "0xD5",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x93",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG1",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
+        "EventCode": "0xD5",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG0",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
+        "EventCode": "0xD5",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG0",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
+        "EventCode": "0xD7",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG0",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
+        "EventCode": "0xD7",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK0.IV_AG0",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
+        "EventCode": "0xD7",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG1",
+        "BriefDescription": "Tag Hit : Clean NearMem Read Hit",
+        "EventCode": "0x2C",
+        "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PublicDescription": "Tag Hit : Clean NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean full line read hits (reads and RFOs).",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG1",
+        "BriefDescription": "Tag Hit : Dirty NearMem Read Hit",
+        "EventCode": "0x2C",
+        "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "PublicDescription": "Tag Hit : Dirty NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty full line read hits (reads and RFOs).",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG1",
+        "BriefDescription": "Tag Hit : Clean NearMem Underfill Hit",
+        "EventCode": "0x2C",
+        "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "PublicDescription": "Tag Hit : Clean NearMem Underfill Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean underfill hits due to a partial write",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x99",
-        "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG0",
+        "BriefDescription": "Tag Hit : Dirty NearMem Underfill Hit",
+        "EventCode": "0x2C",
+        "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "Tag Hit : Dirty NearMem Underfill Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty underfill read hits due to a partial write",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x99",
-        "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG1",
+        "BriefDescription": "Tag Miss",
+        "EventCode": "0x61",
+        "EventName": "UNC_M2M_TAG_MISS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG0",
+        "BriefDescription": "Number AD Ingress Credits",
+        "EventCode": "0x41",
+        "EventName": "UNC_M2M_TGR_AD_CREDITS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG0",
+        "BriefDescription": "Number BL Ingress Credits",
+        "EventCode": "0x42",
+        "EventName": "UNC_M2M_TGR_BL_CREDITS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG0",
+        "BriefDescription": "Tracker Cycles Full : Channel 0",
+        "EventCode": "0x45",
+        "EventName": "UNC_M2M_TRACKER_FULL.CH0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.IV_AG0",
+        "BriefDescription": "Tracker Cycles Full : Channel 1",
+        "EventCode": "0x45",
+        "EventName": "UNC_M2M_TRACKER_FULL.CH1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG1",
+        "BriefDescription": "Tracker Cycles Full : Channel 2",
+        "EventCode": "0x45",
+        "EventName": "UNC_M2M_TRACKER_FULL.CH2",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG1",
+        "BriefDescription": "Tracker Inserts : Channel 0",
+        "EventCode": "0x49",
+        "EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG1",
+        "BriefDescription": "Tracker Inserts : Channel 1",
+        "EventCode": "0x49",
+        "EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x91",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG0",
+        "BriefDescription": "Tracker Inserts : Channel 2",
+        "EventCode": "0x49",
+        "EventName": "UNC_M2M_TRACKER_INSERTS.CH2",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x91",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG1",
+        "BriefDescription": "Tracker Cycles Not Empty : Channel 0",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2M_TRACKER_NE.CH0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG0",
+        "BriefDescription": "Tracker Cycles Not Empty : Channel 1",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2M_TRACKER_NE.CH1",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG0",
+        "BriefDescription": "Tracker Cycles Not Empty : Channel 2",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2M_TRACKER_NE.CH2",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG0",
+        "BriefDescription": "Tracker Occupancy : Channel 0",
+        "EventCode": "0x47",
+        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED0.IV_AG0",
+        "BriefDescription": "Tracker Occupancy : Channel 1",
+        "EventCode": "0x47",
+        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG1",
+        "BriefDescription": "Tracker Occupancy : Channel 2",
+        "EventCode": "0x47",
+        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG1",
+        "BriefDescription": "AD Egress (to CMS) Credit Acquired",
+        "EventCode": "0x0d",
+        "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG1",
+        "BriefDescription": "AD Egress (to CMS) Credits Occupancy",
+        "EventCode": "0x0e",
+        "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9B",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG0",
+        "BriefDescription": "AD Egress (to CMS) Full",
+        "EventCode": "0x0c",
+        "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9B",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG1",
+        "BriefDescription": "AD Egress (to CMS) Not Empty",
+        "EventCode": "0x0b",
+        "EventName": "UNC_M2M_TxC_AD_CYCLES_NE",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9B",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED1.TGC",
+        "BriefDescription": "AD Egress (to CMS) Allocations",
+        "EventCode": "0x09",
+        "EventName": "UNC_M2M_TxC_AD_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB0",
-        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN",
+        "BriefDescription": "Cycles with No AD Egress (to CMS) Credits",
+        "EventCode": "0x0f",
+        "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB0",
-        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD",
+        "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits",
+        "EventCode": "0x10",
+        "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB0",
-        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN",
+        "BriefDescription": "AD Egress (to CMS) Occupancy",
+        "EventCode": "0x0A",
+        "EventName": "UNC_M2M_TxC_AD_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB0",
-        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD",
+        "BriefDescription": "Outbound Ring Transactions on AK : CRD Transactions to Cbo",
+        "EventCode": "0x39",
+        "EventName": "UNC_M2M_TxC_AK.CRD_CBO",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB4",
-        "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_EVEN",
+        "BriefDescription": "Outbound Ring Transactions on AK : NDR Transactions",
+        "EventCode": "0x39",
+        "EventName": "UNC_M2M_TxC_AK.NDR",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB4",
-        "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_ODD",
+        "BriefDescription": "AKC Credits",
+        "EventCode": "0x5F",
+        "EventName": "UNC_M2M_TxC_AKC_CREDITS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB4",
-        "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_EVEN",
+        "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB4",
-        "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_ODD",
+        "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB1",
-        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN",
+        "BriefDescription": "AK Egress (to CMS) Full : All",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x3",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB1",
-        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD",
+        "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Near Side",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB1",
-        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN",
+        "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Far Side",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB1",
-        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD",
+        "BriefDescription": "AK Egress (to CMS) Full",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB2",
-        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN",
+        "BriefDescription": "AK Egress (to CMS) Full",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x88",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB2",
-        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD",
+        "BriefDescription": "AK Egress (to CMS) Full",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB2",
-        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN",
+        "BriefDescription": "AK Egress (to CMS) Full",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0xa0",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB2",
-        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD",
+        "BriefDescription": "AK Egress (to CMS) Full",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical IV Ring in Use : Up",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB3",
-        "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP",
+        "BriefDescription": "AK Egress (to CMS) Full",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x90",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical IV Ring in Use : Down",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB3",
-        "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN",
+        "BriefDescription": "AK Egress (to CMS) Not Empty : All",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x3",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB5",
-        "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_EVEN",
+        "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB5",
-        "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_ODD",
+        "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB5",
-        "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_EVEN",
+        "BriefDescription": "AK Egress (to CMS) Not Empty",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB5",
-        "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_ODD",
+        "BriefDescription": "AK Egress (to CMS) Not Empty",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "AK Egress (to CMS) Not Empty",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR1",
+        "BriefDescription": "AK Egress (to CMS) Allocations : All",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x3",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "AK Egress (to CMS) Allocations",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "AK Egress (to CMS) Allocations",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "AK Egress (to CMS) Allocations",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "AK Egress (to CMS) Allocations",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x81",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+        "EventCode": "0x1F",
+        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x81",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+        "EventCode": "0x1F",
+        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x81",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+        "EventCode": "0x20",
+        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR0",
+        "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+        "EventCode": "0x20",
+        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "AK Egress (to CMS) Occupancy : All",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x3",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Near Side",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Far Side",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "AK Egress (to CMS) Occupancy",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "AK Egress (to CMS) Occupancy",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP",
         "PerPkg": "1",
         "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "AK Egress (to CMS) Occupancy",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Cache",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2M_TxC_BL.DRS_CACHE",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Core",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2M_TxC_BL.DRS_CORE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to QPI",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2M_TxC_BL.DRS_UPI",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR1",
+        "BriefDescription": "BL Egress (to CMS) Full : All",
+        "EventCode": "0x18",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x3",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Near Side",
+        "EventCode": "0x18",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Far Side",
+        "EventCode": "0x18",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "BL Egress (to CMS) Not Empty : All",
+        "EventCode": "0x17",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x3",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
+        "EventCode": "0x17",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
+        "EventCode": "0x17",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "BL Egress (to CMS) Allocations : All",
+        "EventCode": "0x15",
+        "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x3",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x89",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
+        "EventCode": "0x15",
+        "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x89",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
+        "EventCode": "0x15",
+        "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x89",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+        "EventCode": "0x1B",
+        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
-    {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR0",
+    {
+        "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+        "EventCode": "0x1B",
+        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "CMS Horizontal ADS Used : AD - All",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
         "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "CMS Horizontal ADS Used : BL - All",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8B",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8B",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8B",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR1",
+        "BriefDescription": "CMS Horizontal Bypass Used : AK",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "CMS Horizontal Bypass Used : IV",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR0",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR1",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AK",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AKC_UNCRD",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8D",
-        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8D",
-        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8D",
-        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR0",
+        "BriefDescription": "CMS Horizontal Egress Inserts : IV",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AK",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.AK",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8F",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8F",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "CMS Horizontal Egress NACKs : IV",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.IV",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8F",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Distress signal asserted : Vertical",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_M2M_DISTRESS_ASSERTED.VERT",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Distress signal asserted : Horizontal",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_M2M_DISTRESS_ASSERTED.HORZ",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Local",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_LOCAL",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Remote",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_NONLOCAL",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_IV",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Stalled -  No Credit",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBA",
-        "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBA",
-        "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB6",
-        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB6",
-        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB6",
-        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB6",
-        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBB",
-        "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBB",
-        "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_ODD",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBB",
-        "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBB",
-        "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
+        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB7",
-        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB7",
-        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB7",
-        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB7",
-        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD",
+        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use : Left",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB9",
-        "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use : Right",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB9",
-        "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT",
+        "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE6",
-        "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST0",
+        "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE6",
-        "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST1",
+        "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAC",
-        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAC",
-        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAC",
-        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAC",
-        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAA",
-        "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAA",
-        "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAA",
-        "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAA",
-        "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
+        "EventCode": "0x95",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAA",
-        "EventName": "UNC_M2M_RING_BOUNCES_VERT.AKC",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
+        "EventCode": "0x95",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAD",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAD",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAD",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAD",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAD",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
+        "EventCode": "0x97",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
+        "EventCode": "0x97",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AKC",
+        "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_UNCRD",
+        "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_UNCRD",
+        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD",
+        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD",
+        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_ALL",
+        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_ALL",
+        "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_M2M_RxR_BYPASS.AD_UNCRD",
+        "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
+        "EventCode": "0x93",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_M2M_RxR_BYPASS.AK",
+        "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
+        "EventCode": "0x93",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_M2M_RxR_BYPASS.BL_UNCRD",
+        "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_M2M_RxR_BYPASS.IV",
+        "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD",
+        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD",
+        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_M2M_RxR_BYPASS.AKC_UNCRD",
+        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_M2M_RxR_BYPASS.AD_ALL",
+        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_M2M_RxR_BYPASS.BL_ALL",
+        "BriefDescription": "CMS Vertical Egress NACKs : IV",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_UNCRD",
+        "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
+        "EventCode": "0x99",
+        "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.AK",
+        "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
+        "EventCode": "0x99",
+        "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_UNCRD",
+        "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.IV",
+        "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD",
+        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD",
+        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV",
+        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_ALL",
+        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_ALL",
+        "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_M2M_RxR_INSERTS.AD_UNCRD",
+        "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
+        "EventCode": "0x91",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_M2M_RxR_INSERTS.AK",
+        "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
+        "EventCode": "0x91",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_M2M_RxR_INSERTS.BL_UNCRD",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_M2M_RxR_INSERTS.IV",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_M2M_RxR_INSERTS.AKC_UNCRD",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_M2M_RxR_INSERTS.AD_ALL",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_M2M_RxR_INSERTS.BL_ALL",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_UNCRD",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.AK",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_UNCRD",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED1.TGC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.IV",
+        "BriefDescription": "Vertical AD Ring In Use : Down and Even",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD",
+        "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD",
+        "BriefDescription": "Vertical AD Ring In Use : Up and Even",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.AKC_UNCRD",
+        "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_ALL",
+        "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_ALL",
+        "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+        "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+        "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+        "BriefDescription": "Vertical AK Ring In Use : Down and Even",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+        "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+        "BriefDescription": "Vertical AK Ring In Use : Up and Even",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+        "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
+        "BriefDescription": "Vertical BL Ring in Use : Down and Even",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
+        "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+        "BriefDescription": "Vertical BL Ring in Use : Up and Even",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+        "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+        "BriefDescription": "Vertical IV Ring in Use : Down",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+        "BriefDescription": "Vertical IV Ring in Use : Up",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+        "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
+        "EventCode": "0xB5",
+        "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+        "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
+        "EventCode": "0xB5",
+        "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
+        "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
+        "EventCode": "0xB5",
+        "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
+        "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
+        "EventCode": "0xB5",
+        "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+        "BriefDescription": "WPQ Flush : Channel 0",
+        "EventCode": "0x58",
+        "EventName": "UNC_M2M_WPQ_FLUSH.CH0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+        "BriefDescription": "WPQ Flush : Channel 1",
+        "EventCode": "0x58",
+        "EventName": "UNC_M2M_WPQ_FLUSH.CH1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+        "BriefDescription": "WPQ Flush : Channel 2",
+        "EventCode": "0x58",
+        "EventName": "UNC_M2M_WPQ_FLUSH.CH2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 2",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN2",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
+        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 0",
+        "EventCode": "0x51",
+        "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 1",
+        "EventCode": "0x51",
+        "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN1",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 2",
+        "EventCode": "0x51",
+        "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN2",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 0",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 1",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 2",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN2",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+        "BriefDescription": "Write Tracker Cycles Full : Channel 0",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M2M_WR_TRACKER_FULL.CH0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+        "BriefDescription": "Write Tracker Cycles Full : Channel 1",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M2M_WR_TRACKER_FULL.CH1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+        "BriefDescription": "Write Tracker Cycles Full : Channel 2",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M2M_WR_TRACKER_FULL.CH2",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+        "BriefDescription": "Write Tracker Cycles Full : Mirror",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M2M_WR_TRACKER_FULL.MIRR",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD1",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+        "BriefDescription": "Write Tracker Inserts : Channel 0",
+        "EventCode": "0x56",
+        "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD1",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+        "BriefDescription": "Write Tracker Inserts : Channel 1",
+        "EventCode": "0x56",
+        "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD1",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+        "BriefDescription": "Write Tracker Inserts : Channel 2",
+        "EventCode": "0x56",
+        "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD3",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+        "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M2M_WR_TRACKER_NE.CH0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD3",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+        "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M2M_WR_TRACKER_NE.CH1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD3",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+        "BriefDescription": "Write Tracker Cycles Not Empty : Channel 2",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M2M_WR_TRACKER_NE.CH2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD5",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+        "BriefDescription": "Write Tracker Cycles Not Empty : Mirror",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD5",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+        "BriefDescription": "Write Tracker Cycles Not Empty",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD5",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+        "BriefDescription": "Write Tracker Cycles Not Empty",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD7",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+        "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0",
+        "EventCode": "0x63",
+        "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD7",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+        "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1",
+        "EventCode": "0x63",
+        "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD7",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+        "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 2",
+        "EventCode": "0x63",
+        "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_UNCRD",
+        "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 0",
+        "EventCode": "0x62",
+        "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_UNCRD",
+        "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 1",
+        "EventCode": "0x62",
+        "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD",
+        "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 2",
+        "EventCode": "0x62",
+        "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH2",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD",
+        "BriefDescription": "Write Tracker Occupancy : Channel 0",
+        "EventCode": "0x55",
+        "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_ALL",
+        "BriefDescription": "Write Tracker Occupancy : Channel 1",
+        "EventCode": "0x55",
+        "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH1",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_ALL",
+        "BriefDescription": "Write Tracker Occupancy : Channel 2",
+        "EventCode": "0x55",
+        "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH2",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_UNCRD",
+        "BriefDescription": "Write Tracker Occupancy : Mirror",
+        "EventCode": "0x55",
+        "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK",
+        "BriefDescription": "Write Tracker Occupancy",
+        "EventCode": "0x55",
+        "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_NONTGR",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_UNCRD",
+        "BriefDescription": "Write Tracker Occupancy",
+        "EventCode": "0x55",
+        "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_PWR",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV",
+        "BriefDescription": "Write Tracker Posted Inserts : Channel 0",
+        "EventCode": "0x5E",
+        "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD",
+        "BriefDescription": "Write Tracker Posted Inserts : Channel 1",
+        "EventCode": "0x5E",
+        "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD",
+        "BriefDescription": "Write Tracker Posted Inserts : Channel 2",
+        "EventCode": "0x5E",
+        "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH2",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AKC_UNCRD",
+        "BriefDescription": "Write Tracker Posted Occupancy : Channel 0",
+        "EventCode": "0x5D",
+        "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_ALL",
+        "BriefDescription": "Write Tracker Posted Occupancy : Channel 1",
+        "EventCode": "0x5D",
+        "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_ALL",
+        "BriefDescription": "Write Tracker Posted Occupancy : Channel 2",
+        "EventCode": "0x5D",
+        "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH2",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR5",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x40",
-        "Unit": "M2M"
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x80",
-        "Unit": "M2M"
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_ALL",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
+        "EventCode": "0x81",
+        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x11",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_ALL",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
+        "EventCode": "0x81",
+        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x44",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_UNCRD",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
+        "EventCode": "0x81",
+        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_UNCRD",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR3",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR5",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x40",
-        "Unit": "M2M"
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x80",
-        "Unit": "M2M"
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_ALL",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
+        "EventCode": "0x83",
+        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x11",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_ALL",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
+        "EventCode": "0x83",
+        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x44",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_UNCRD",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
+        "EventCode": "0x83",
+        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR0",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR1",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_UNCRD",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x40",
-        "Unit": "M2M"
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AKC_UNCRD",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x80",
-        "Unit": "M2M"
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_ALL",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
+        "EventCode": "0x89",
+        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x11",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_ALL",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
+        "EventCode": "0x89",
+        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x44",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_UNCRD",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
+        "EventCode": "0x89",
+        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.AK",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
+        "EventCode": "0x8a",
+        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_UNCRD",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
+        "EventCode": "0x8a",
+        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.IV",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
+        "EventCode": "0x8a",
+        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
+        "EventCode": "0x8a",
+        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR3",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
+        "EventCode": "0x8a",
+        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
+        "EventCode": "0x8a",
+        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR5",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
+        "EventCode": "0x8a",
+        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
         "UMask": "0x40",
-        "Unit": "M2M"
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.AKC_UNCRD",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
+        "EventCode": "0x8a",
+        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
         "UMask": "0x80",
-        "Unit": "M2M"
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_ALL",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
+        "EventCode": "0x8b",
+        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x11",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_ALL",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
+        "EventCode": "0x8b",
+        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x44",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_UNCRD",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
+        "EventCode": "0x8b",
+        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_UNCRD",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR3",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x40",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_ALL",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x11",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x80",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_ALL",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
+        "EventCode": "0x85",
+        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x44",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_UNCRD",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
+        "EventCode": "0x85",
+        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
+        "EventCode": "0x85",
+        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_UNCRD",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AKC_UNCRD",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_ALL",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_ALL",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x40",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x80",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
+        "EventCode": "0x87",
+        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
+        "EventCode": "0x87",
+        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
+        "EventCode": "0x87",
+        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
+        "EventCode": "0x8c",
+        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV_AG1",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
+        "EventCode": "0x8c",
+        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
+        "EventCode": "0x8c",
+        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
+        "EventCode": "0x8c",
+        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+        "EventCode": "0x8c",
+        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG0",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+        "EventCode": "0x8c",
+        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG1",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+        "EventCode": "0x8c",
+        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x40",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG0",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+        "EventCode": "0x8c",
+        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x80",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG0",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
+        "EventCode": "0x8d",
+        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG0",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
+        "EventCode": "0x8d",
+        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.IV_AG0",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
+        "EventCode": "0x8d",
+        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG1",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
+        "EventCode": "0x8e",
+        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG1",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
+        "EventCode": "0x8e",
+        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG1",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
+        "EventCode": "0x8e",
+        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x95",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG0",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
+        "EventCode": "0x8e",
+        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x95",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG1",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
+        "EventCode": "0x8e",
+        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG0",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
+        "EventCode": "0x8e",
+        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG0",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
+        "EventCode": "0x8e",
+        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x40",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG0",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
+        "EventCode": "0x8e",
+        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x80",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.IV_AG0",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
+        "EventCode": "0x8f",
+        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG1",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
+        "EventCode": "0x8f",
+        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG1",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
+        "EventCode": "0x8f",
+        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG1",
+        "BriefDescription": "Clockticks of the mesh to PCI (M2P)",
+        "EventCode": "0x01",
+        "EventName": "UNC_M2P_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "Clockticks of the mesh to PCI (M2P) : Counts the number of uclks in the M3 uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x97",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG0",
+        "BriefDescription": "CMS Clockticks",
+        "EventCode": "0xc0",
+        "EventName": "UNC_M2P_CMS_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x97",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG1",
+        "BriefDescription": "Distress signal asserted : DPT Local",
+        "EventCode": "0xaf",
+        "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG0",
+        "BriefDescription": "Distress signal asserted : DPT Remote",
+        "EventCode": "0xaf",
+        "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_NONLOCAL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG0",
+        "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
+        "EventCode": "0xaf",
+        "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_IV",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
+        "UMask": "0x40",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG0",
+        "BriefDescription": "Distress signal asserted : DPT Stalled -  No Credit",
+        "EventCode": "0xaf",
+        "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Distress signal asserted : DPT Stalled -  No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
+        "UMask": "0x80",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.IV_AG0",
+        "BriefDescription": "Distress signal asserted : Horizontal",
+        "EventCode": "0xaf",
+        "EventName": "UNC_M2P_DISTRESS_ASSERTED.HORZ",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG1",
+        "BriefDescription": "Distress signal asserted : PMM Local",
+        "EventCode": "0xAF",
+        "EventName": "UNC_M2P_DISTRESS_ASSERTED.PMM_LOCAL",
         "PerPkg": "1",
+        "PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG1",
+        "BriefDescription": "Distress signal asserted : PMM Remote",
+        "EventCode": "0xAF",
+        "EventName": "UNC_M2P_DISTRESS_ASSERTED.PMM_NONLOCAL",
         "PerPkg": "1",
+        "PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
         "UMask": "0x20",
-        "Unit": "M2M"
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG1",
+        "BriefDescription": "Distress signal asserted : Vertical",
+        "EventCode": "0xaf",
+        "EventName": "UNC_M2P_DISTRESS_ASSERTED.VERT",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x93",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG0",
+        "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+        "EventCode": "0xba",
+        "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x93",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG1",
+        "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+        "EventCode": "0xba",
+        "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG0",
+        "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
+        "EventCode": "0xb6",
+        "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG0",
+        "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
+        "EventCode": "0xb6",
+        "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG0",
+        "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
+        "EventCode": "0xb6",
+        "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK0.IV_AG0",
+        "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
+        "EventCode": "0xb6",
+        "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG1",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+        "EventCode": "0xbb",
+        "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG1",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+        "EventCode": "0xbb",
+        "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG1",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+        "EventCode": "0xbb",
+        "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x99",
-        "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG0",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+        "EventCode": "0xbb",
+        "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x99",
-        "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG1",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+        "EventCode": "0xb7",
+        "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG0",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+        "EventCode": "0xb7",
+        "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG0",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+        "EventCode": "0xb7",
+        "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG0",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+        "EventCode": "0xb7",
+        "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.IV_AG0",
+        "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
+        "EventCode": "0xb8",
+        "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG1",
+        "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
+        "EventCode": "0xb8",
+        "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG1",
+        "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
+        "EventCode": "0xb8",
+        "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG1",
+        "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
+        "EventCode": "0xb8",
+        "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x91",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG0",
+        "BriefDescription": "Horizontal IV Ring in Use : Left",
+        "EventCode": "0xb9",
+        "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.LEFT",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x91",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG1",
+        "BriefDescription": "Horizontal IV Ring in Use : Right",
+        "EventCode": "0xb9",
+        "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.RIGHT",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG0",
+        "BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
+        "EventCode": "0x33",
+        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG0",
+        "BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
+        "EventCode": "0x33",
+        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG0",
+        "BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
+        "EventCode": "0x33",
+        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED0.IV_AG0",
+        "BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
+        "EventCode": "0x33",
+        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG1",
+        "BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
+        "EventCode": "0x33",
+        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0",
         "PerPkg": "1",
+        "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG1",
+        "BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
+        "EventCode": "0x33",
+        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1",
         "PerPkg": "1",
+        "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.",
         "UMask": "0x20",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG1",
-        "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9B",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG0",
+        "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS",
+        "EventCode": "0x34",
+        "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the DRS message class.",
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9B",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG1",
+        "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB",
+        "EventCode": "0x34",
+        "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCB message class.",
+        "UMask": "0x10",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9B",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED1.TGC",
+        "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS",
+        "EventCode": "0x34",
+        "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCS message class.",
+        "UMask": "0x20",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN",
+        "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0",
+        "EventCode": "0x32",
+        "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD",
+        "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1",
+        "EventCode": "0x32",
+        "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN",
+        "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0",
+        "EventCode": "0x32",
+        "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD",
+        "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1",
+        "EventCode": "0x32",
+        "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_EVEN",
+        "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0",
+        "EventCode": "0x32",
+        "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.",
+        "UMask": "0x10",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_ODD",
+        "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1",
+        "EventCode": "0x32",
+        "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.",
+        "UMask": "0x20",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_EVEN",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCB",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_ODD",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCS",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCB",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCS",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCB",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "UMask": "0x10",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCS",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "UMask": "0x20",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCB",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x40",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCS",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x80",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCB",
+        "EventCode": "0x47",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCS",
+        "EventCode": "0x47",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical IV Ring in Use : Up",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCB",
+        "EventCode": "0x47",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical IV Ring in Use : Down",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCS",
+        "EventCode": "0x47",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB5",
-        "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_EVEN",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCB",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB5",
-        "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_ODD",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCS",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB5",
-        "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_EVEN",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCB",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB5",
-        "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_ODD",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCS",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCB",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR1",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCS",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCB",
+        "EventCode": "0x1a",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCS",
+        "EventCode": "0x1a",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCB",
+        "EventCode": "0x1a",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCS",
+        "EventCode": "0x1a",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x81",
-        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "Local P2P Shared Credits Returned : Agent0",
+        "EventCode": "0x17",
+        "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x81",
-        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "Local P2P Shared Credits Returned : Agent1",
+        "EventCode": "0x17",
+        "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x81",
-        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "Local P2P Shared Credits Returned : Agent2",
+        "EventCode": "0x17",
+        "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR0",
+        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent0",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent1",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent2",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent3",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent4",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent5",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5",
         "PerPkg": "1",
         "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCB",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCS",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCB",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCS",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCB",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCS",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR1",
+        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCB",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCS",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCB",
+        "EventCode": "0x41",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCS",
+        "EventCode": "0x41",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCB",
+        "EventCode": "0x41",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCS",
+        "EventCode": "0x41",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCB",
+        "EventCode": "0x4a",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x89",
-        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCS",
+        "EventCode": "0x4a",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x89",
-        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCB",
+        "EventCode": "0x4a",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x89",
-        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCS",
+        "EventCode": "0x4a",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8a",
-        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR0",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCB",
+        "EventCode": "0x4a",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8a",
-        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCS",
+        "EventCode": "0x4a",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8a",
-        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCB",
+        "EventCode": "0x4a",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8a",
-        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCS",
+        "EventCode": "0x4a",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8a",
-        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCB",
+        "EventCode": "0x4b",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8a",
-        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCS",
+        "EventCode": "0x4b",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8a",
-        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCB",
+        "EventCode": "0x4b",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8a",
-        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCS",
+        "EventCode": "0x4b",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8b",
-        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
+        "EventCode": "0xe6",
+        "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8b",
-        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
+        "EventCode": "0xe6",
+        "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8b",
-        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "P2P Credit Occupancy : All",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "P2P Credit Occupancy : Local NCB",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR1",
+        "BriefDescription": "P2P Credit Occupancy : Local NCS",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "P2P Credit Occupancy : Remote NCB",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "P2P Credit Occupancy : Remote NCS",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "Dedicated Credits Received : All",
+        "EventCode": "0x16",
+        "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "Dedicated Credits Received : Local NCB",
+        "EventCode": "0x16",
+        "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "Dedicated Credits Received : Local NCS",
+        "EventCode": "0x16",
+        "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "Dedicated Credits Received : Remote NCB",
+        "EventCode": "0x16",
+        "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "Dedicated Credits Received : Remote NCS",
+        "EventCode": "0x16",
+        "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "Shared Credits  Received : All",
+        "EventCode": "0x15",
+        "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "Shared Credits  Received : Local NCB",
+        "EventCode": "0x15",
+        "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR0",
+        "BriefDescription": "Shared Credits  Received : Local NCS",
+        "EventCode": "0x15",
+        "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "Shared Credits  Received : Remote NCB",
+        "EventCode": "0x15",
+        "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "Shared Credits  Received : Remote NCS",
+        "EventCode": "0x15",
+        "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - DRS",
+        "EventCode": "0x48",
+        "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_DRS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCB",
+        "EventCode": "0x48",
+        "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCB",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCS",
+        "EventCode": "0x48",
+        "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCS",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - DRS",
+        "EventCode": "0x48",
+        "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_DRS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCB",
+        "EventCode": "0x48",
+        "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCB",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCS",
+        "EventCode": "0x48",
+        "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - DRS",
+        "EventCode": "0x49",
+        "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_DRS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCB",
+        "EventCode": "0x49",
+        "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8c",
-        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCS",
+        "EventCode": "0x49",
+        "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8c",
-        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR1",
+        "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCB",
+        "EventCode": "0x1b",
+        "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8c",
-        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCS",
+        "EventCode": "0x1b",
+        "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8c",
-        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCB",
+        "EventCode": "0x1b",
+        "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8c",
-        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCS",
+        "EventCode": "0x1b",
+        "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCS",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8c",
-        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCB",
+        "EventCode": "0x1b",
+        "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCB",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8c",
-        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCS",
+        "EventCode": "0x1b",
+        "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8c",
-        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "Remote P2P Shared Credits Returned : Agent0",
+        "EventCode": "0x18",
+        "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8d",
-        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "Remote P2P Shared Credits Returned : Agent1",
+        "EventCode": "0x18",
+        "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8d",
-        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "Remote P2P Shared Credits Returned : Agent2",
+        "EventCode": "0x18",
+        "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8d",
-        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent0",
+        "EventCode": "0x45",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8e",
-        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR0",
+        "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent1",
+        "EventCode": "0x45",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8e",
-        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent2",
+        "EventCode": "0x45",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8e",
-        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - DRS",
+        "EventCode": "0x42",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_DRS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8e",
-        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCB",
+        "EventCode": "0x42",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8e",
-        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCS",
+        "EventCode": "0x42",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCS",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8e",
-        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - DRS",
+        "EventCode": "0x42",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_DRS",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8e",
-        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCB",
+        "EventCode": "0x42",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCB",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8e",
-        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCS",
+        "EventCode": "0x42",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCS",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8f",
-        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - DRS",
+        "EventCode": "0x43",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_DRS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8f",
-        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCB",
+        "EventCode": "0x43",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8f",
-        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCS",
+        "EventCode": "0x43",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Distress signal asserted : Vertical",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xaf",
-        "EventName": "UNC_M2P_DISTRESS_ASSERTED.VERT",
+        "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - DRS",
+        "EventCode": "0x4c",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_DRS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Distress signal asserted : Horizontal",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xaf",
-        "EventName": "UNC_M2P_DISTRESS_ASSERTED.HORZ",
+        "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCB",
+        "EventCode": "0x4c",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Local",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xaf",
-        "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_LOCAL",
+        "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCS",
+        "EventCode": "0x4c",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Remote",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xaf",
-        "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_NONLOCAL",
+        "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - DRS",
+        "EventCode": "0x4c",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_DRS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xaf",
-        "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_IV",
+        "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCB",
+        "EventCode": "0x4c",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCB",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Stalled -  No Credit",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xaf",
-        "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
+        "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCS",
+        "EventCode": "0x4c",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCS",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xba",
-        "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP",
+        "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - DRS",
+        "EventCode": "0x4d",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_DRS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xba",
-        "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN",
+        "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCB",
+        "EventCode": "0x4d",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb6",
-        "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCS",
+        "EventCode": "0x4d",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb6",
-        "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_ODD",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
+        "EventCode": "0xac",
+        "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb6",
-        "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
+        "EventCode": "0xac",
+        "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb6",
-        "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
+        "EventCode": "0xac",
+        "EventName": "UNC_M2P_RING_BOUNCES_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xbb",
-        "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
+        "EventCode": "0xac",
+        "EventName": "UNC_M2P_RING_BOUNCES_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xbb",
-        "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_ODD",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
+        "EventCode": "0xaa",
+        "EventName": "UNC_M2P_RING_BOUNCES_VERT.AD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xbb",
-        "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
+        "EventCode": "0xaa",
+        "EventName": "UNC_M2P_RING_BOUNCES_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xbb",
-        "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.",
+        "EventCode": "0xaa",
+        "EventName": "UNC_M2P_RING_BOUNCES_VERT.AKC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb7",
-        "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
+        "EventCode": "0xaa",
+        "EventName": "UNC_M2P_RING_BOUNCES_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb7",
-        "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_ODD",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
+        "EventCode": "0xaa",
+        "EventName": "UNC_M2P_RING_BOUNCES_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb7",
-        "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
+        "EventCode": "0xad",
+        "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb7",
-        "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
+        "EventCode": "0xad",
+        "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb8",
-        "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
+        "EventCode": "0xad",
+        "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb8",
-        "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_ODD",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
+        "EventCode": "0xad",
+        "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb8",
-        "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
+        "EventCode": "0xad",
+        "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb8",
-        "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Sink Starvation on Vertical Ring : AD",
+        "EventCode": "0xab",
+        "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use : Left",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb9",
-        "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.LEFT",
+        "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
+        "EventCode": "0xab",
+        "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use : Right",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb9",
-        "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.RIGHT",
+        "BriefDescription": "Sink Starvation on Vertical Ring",
+        "EventCode": "0xab",
+        "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AKC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe6",
-        "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST0",
+        "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
+        "EventCode": "0xab",
+        "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe6",
-        "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST1",
+        "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
+        "EventCode": "0xab",
+        "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xac",
-        "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AD",
+        "BriefDescription": "Source Throttle",
+        "EventCode": "0xae",
+        "EventName": "UNC_M2P_RING_SRC_THRTL",
         "PerPkg": "1",
-        "UMask": "0x01",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xac",
-        "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AK",
+        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+        "EventCode": "0x10",
+        "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xac",
-        "EventName": "UNC_M2P_RING_BOUNCES_HORZ.BL",
+        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+        "EventCode": "0x10",
+        "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xac",
-        "EventName": "UNC_M2P_RING_BOUNCES_HORZ.IV",
+        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+        "EventCode": "0x10",
+        "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xaa",
-        "EventName": "UNC_M2P_RING_BOUNCES_VERT.AD",
+        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+        "EventCode": "0x10",
+        "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xaa",
-        "EventName": "UNC_M2P_RING_BOUNCES_VERT.AK",
+        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+        "EventCode": "0x10",
+        "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xaa",
-        "EventName": "UNC_M2P_RING_BOUNCES_VERT.BL",
+        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+        "EventCode": "0x10",
+        "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xaa",
-        "EventName": "UNC_M2P_RING_BOUNCES_VERT.IV",
+        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+        "EventCode": "0x10",
+        "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xaa",
-        "EventName": "UNC_M2P_RING_BOUNCES_VERT.AKC",
+        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+        "EventCode": "0x10",
+        "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCS",
         "PerPkg": "1",
+        "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
         "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xad",
-        "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AD",
+        "BriefDescription": "Ingress (from CMS) Queue Inserts",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2P_RxC_INSERTS.ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xad",
-        "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK",
+        "BriefDescription": "Ingress (from CMS) Queue Inserts",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xad",
-        "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.BL",
+        "BriefDescription": "Ingress (from CMS) Queue Inserts",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xad",
-        "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.IV",
+        "BriefDescription": "Ingress (from CMS) Queue Inserts",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xad",
-        "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK_AG1",
+        "BriefDescription": "Ingress (from CMS) Queue Inserts",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB",
         "PerPkg": "1",
+        "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
         "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xab",
-        "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AD",
+        "BriefDescription": "Ingress (from CMS) Queue Inserts",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xab",
-        "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AK",
+        "BriefDescription": "Ingress (from CMS) Queue Inserts",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xab",
-        "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.BL",
+        "BriefDescription": "Ingress (from CMS) Queue Inserts",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xab",
-        "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.IV",
+        "BriefDescription": "Transgress Injection Starvation : AD - All",
+        "EventCode": "0xe5",
+        "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xab",
-        "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AKC",
+        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+        "EventCode": "0xe5",
+        "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
         "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xe5",
         "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Injection Starvation : BL - All",
         "EventCode": "0xe5",
-        "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_UNCRD",
+        "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
         "EventCode": "0xe5",
-        "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_CRD",
+        "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
         "EventCode": "0xe5",
-        "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_CRD",
+        "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe5",
-        "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_ALL",
+        "BriefDescription": "Transgress Ingress Bypass : AD - All",
+        "EventCode": "0xe2",
+        "EventName": "UNC_M2P_RxR_BYPASS.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe5",
-        "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_ALL",
+        "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
+        "EventCode": "0xe2",
+        "EventName": "UNC_M2P_RxR_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xe2",
         "EventName": "UNC_M2P_RxR_BYPASS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Transgress Ingress Bypass : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xe2",
         "EventName": "UNC_M2P_RxR_BYPASS.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
         "EventCode": "0xe2",
-        "EventName": "UNC_M2P_RxR_BYPASS.BL_UNCRD",
+        "EventName": "UNC_M2P_RxR_BYPASS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Bypass : BL - All",
         "EventCode": "0xe2",
-        "EventName": "UNC_M2P_RxR_BYPASS.IV",
+        "EventName": "UNC_M2P_RxR_BYPASS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
         "EventCode": "0xe2",
-        "EventName": "UNC_M2P_RxR_BYPASS.AD_CRD",
+        "EventName": "UNC_M2P_RxR_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
         "EventCode": "0xe2",
-        "EventName": "UNC_M2P_RxR_BYPASS.BL_CRD",
+        "EventName": "UNC_M2P_RxR_BYPASS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Bypass : IV",
         "EventCode": "0xe2",
-        "EventName": "UNC_M2P_RxR_BYPASS.AKC_UNCRD",
+        "EventName": "UNC_M2P_RxR_BYPASS.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe2",
-        "EventName": "UNC_M2P_RxR_BYPASS.AD_ALL",
+        "BriefDescription": "Transgress Injection Starvation : AD - All",
+        "EventCode": "0xe3",
+        "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe2",
-        "EventName": "UNC_M2P_RxR_BYPASS.BL_ALL",
+        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+        "EventCode": "0xe3",
+        "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xe3",
         "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Transgress Injection Starvation : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xe3",
         "EventName": "UNC_M2P_RxR_CRD_STARVED.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Injection Starvation : BL - All",
         "EventCode": "0xe3",
-        "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_UNCRD",
+        "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
         "EventCode": "0xe3",
-        "EventName": "UNC_M2P_RxR_CRD_STARVED.IV",
+        "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
         "EventCode": "0xe3",
-        "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_CRD",
+        "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
         "EventCode": "0xe3",
-        "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_CRD",
+        "EventName": "UNC_M2P_RxR_CRD_STARVED.IFV",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Injection Starvation : IV",
         "EventCode": "0xe3",
-        "EventName": "UNC_M2P_RxR_CRD_STARVED.IFV",
+        "EventName": "UNC_M2P_RxR_CRD_STARVED.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe3",
-        "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_ALL",
+        "BriefDescription": "Transgress Injection Starvation",
+        "EventCode": "0xe4",
+        "EventName": "UNC_M2P_RxR_CRD_STARVED_1",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe3",
-        "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_ALL",
+        "BriefDescription": "Transgress Ingress Allocations : AD - All",
+        "EventCode": "0xe1",
+        "EventName": "UNC_M2P_RxR_INSERTS.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
         "EventCode": "0xe1",
-        "EventName": "UNC_M2P_RxR_INSERTS.AD_UNCRD",
+        "EventName": "UNC_M2P_RxR_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
         "EventCode": "0xe1",
-        "EventName": "UNC_M2P_RxR_INSERTS.AK",
+        "EventName": "UNC_M2P_RxR_INSERTS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Allocations : AK",
         "EventCode": "0xe1",
-        "EventName": "UNC_M2P_RxR_INSERTS.BL_UNCRD",
+        "EventName": "UNC_M2P_RxR_INSERTS.AK",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
         "EventCode": "0xe1",
-        "EventName": "UNC_M2P_RxR_INSERTS.IV",
+        "EventName": "UNC_M2P_RxR_INSERTS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Allocations : BL - All",
         "EventCode": "0xe1",
-        "EventName": "UNC_M2P_RxR_INSERTS.AD_CRD",
+        "EventName": "UNC_M2P_RxR_INSERTS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xe1",
         "EventName": "UNC_M2P_RxR_INSERTS.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
         "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
         "EventCode": "0xe1",
-        "EventName": "UNC_M2P_RxR_INSERTS.AKC_UNCRD",
+        "EventName": "UNC_M2P_RxR_INSERTS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Allocations : IV",
         "EventCode": "0xe1",
-        "EventName": "UNC_M2P_RxR_INSERTS.AD_ALL",
+        "EventName": "UNC_M2P_RxR_INSERTS.IV",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe1",
-        "EventName": "UNC_M2P_RxR_INSERTS.BL_ALL",
+        "BriefDescription": "Transgress Ingress Occupancy : AD - All",
+        "EventCode": "0xe0",
+        "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
         "EventCode": "0xe0",
-        "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_UNCRD",
+        "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
         "EventCode": "0xe0",
-        "EventName": "UNC_M2P_RxR_OCCUPANCY.AK",
+        "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Occupancy : AK",
         "EventCode": "0xe0",
-        "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_UNCRD",
+        "EventName": "UNC_M2P_RxR_OCCUPANCY.AK",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
         "EventCode": "0xe0",
-        "EventName": "UNC_M2P_RxR_OCCUPANCY.IV",
+        "EventName": "UNC_M2P_RxR_OCCUPANCY.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Occupancy : BL - All",
         "EventCode": "0xe0",
-        "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_CRD",
+        "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xe0",
         "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
         "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe0",
-        "EventName": "UNC_M2P_RxR_OCCUPANCY.AKC_UNCRD",
-        "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M2PCIe"
-    },
-    {
-        "BriefDescription": "Transgress Ingress Occupancy : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
         "EventCode": "0xe0",
-        "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_ALL",
+        "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Occupancy : IV",
         "EventCode": "0xe0",
-        "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_ALL",
+        "EventName": "UNC_M2P_RxR_OCCUPANCY.IV",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd0",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd0",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd0",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd0",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd0",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd0",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd0",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd0",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd2",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd2",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd2",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd2",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd2",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd2",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd2",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd2",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd4",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd4",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd4",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd4",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd4",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd4",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd4",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd4",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd6",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd6",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd6",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd6",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd6",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd6",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
+        "EventCode": "0xd6",
+        "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x40",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
+        "EventCode": "0xd6",
+        "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x80",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
+        "EventCode": "0xd1",
+        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
+        "EventCode": "0xd1",
+        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
+        "EventCode": "0xd1",
+        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
+        "EventCode": "0xd3",
+        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
+        "EventCode": "0xd3",
+        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
+        "EventCode": "0xd3",
+        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
+        "EventCode": "0xd5",
+        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
+        "EventCode": "0xd5",
+        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
+        "EventCode": "0xd5",
+        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
+        "EventCode": "0xd7",
+        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
+        "EventCode": "0xd7",
+        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
+        "EventCode": "0xd7",
+        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "UNC_M2P_TxC_CREDITS.PMM",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M2P_TxC_CREDITS.PMM",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ",
+        "EventCode": "0x2d",
+        "EventName": "UNC_M2P_TxC_CREDITS.PRQ",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Egress (to CMS) Cycles Full",
+        "EventCode": "0x25",
+        "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_0",
+        "PerPkg": "1",
+        "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Egress (to CMS) Cycles Full",
+        "EventCode": "0x25",
+        "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_1",
+        "PerPkg": "1",
+        "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+        "UMask": "0x10",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Egress (to CMS) Cycles Full",
+        "EventCode": "0x25",
+        "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_0",
+        "PerPkg": "1",
+        "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Egress (to CMS) Cycles Full",
+        "EventCode": "0x25",
+        "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_1",
+        "PerPkg": "1",
+        "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
         "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd6",
-        "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+        "BriefDescription": "Egress (to CMS) Cycles Full",
+        "EventCode": "0x25",
+        "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_0",
+        "PerPkg": "1",
+        "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Egress (to CMS) Cycles Full",
+        "EventCode": "0x25",
+        "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_1",
+        "PerPkg": "1",
+        "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+        "UMask": "0x40",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Egress (to CMS) Cycles Full",
+        "EventCode": "0x25",
+        "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_0",
+        "PerPkg": "1",
+        "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+        "UMask": "0x80",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Egress (to CMS) Cycles Full",
+        "EventCode": "0x25",
+        "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_1",
+        "PerPkg": "1",
+        "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+        "EventCode": "0x23",
+        "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_0",
+        "PerPkg": "1",
+        "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple egress buffers can be tracked at a given time using multiple counters.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+        "EventCode": "0x23",
+        "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple egress buffers can be tracked at a given time using multiple counters.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd6",
-        "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+        "EventCode": "0x23",
+        "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple egress buffers can be tracked at a given time using multiple counters.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd1",
-        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+        "EventCode": "0x23",
+        "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple egress buffers can be tracked at a given time using multiple counters.",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd1",
-        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+        "EventCode": "0x23",
+        "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple egress buffers can be tracked at a given time using multiple counters.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd1",
-        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+        "EventCode": "0x23",
+        "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple egress buffers can be tracked at a given time using multiple counters.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd3",
-        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+        "EventCode": "0x23",
+        "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple egress buffers can be tracked at a given time using multiple counters.",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd3",
-        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+        "EventCode": "0x23",
+        "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple egress buffers can be tracked at a given time using multiple counters.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd3",
-        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+        "BriefDescription": "Egress (to CMS) Ingress",
+        "EventCode": "0x24",
+        "EventName": "UNC_M2P_TxC_INSERTS.AD_0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the  the M2PCIe Egress queue.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+        "BriefDescription": "Egress (to CMS) Ingress",
+        "EventCode": "0x24",
+        "EventName": "UNC_M2P_TxC_INSERTS.AD_1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the  the M2PCIe Egress queue.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+        "BriefDescription": "Egress (to CMS) Ingress",
+        "EventCode": "0x24",
+        "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the  the M2PCIe Egress queue.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+        "BriefDescription": "Egress (to CMS) Ingress",
+        "EventCode": "0x24",
+        "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the  the M2PCIe Egress queue.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd7",
-        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+        "BriefDescription": "Egress (to CMS) Ingress",
+        "EventCode": "0x24",
+        "EventName": "UNC_M2P_TxC_INSERTS.BL_0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the  the M2PCIe Egress queue.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd7",
-        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+        "BriefDescription": "Egress (to CMS) Ingress",
+        "EventCode": "0x24",
+        "EventName": "UNC_M2P_TxC_INSERTS.BL_1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the  the M2PCIe Egress queue.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd7",
-        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+        "BriefDescription": "CMS Horizontal ADS Used : AD - All",
+        "EventCode": "0xa6",
+        "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
         "EventCode": "0xa6",
-        "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
         "EventCode": "0xa6",
-        "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal ADS Used : BL - All",
         "EventCode": "0xa6",
-        "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa6",
         "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
         "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
         "EventCode": "0xa6",
-        "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_ALL",
+        "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_UNCRD",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
+        "EventCode": "0xa7",
+        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa6",
-        "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_ALL",
+        "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
+        "EventCode": "0xa7",
+        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa7",
         "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal Bypass Used : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa7",
         "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
         "EventCode": "0xa7",
-        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
         "EventCode": "0xa7",
-        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.IV",
+        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
         "EventCode": "0xa7",
-        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
         "EventCode": "0xa7",
-        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Bypass Used : IV",
         "EventCode": "0xa7",
-        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AKC_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa7",
-        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_ALL",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
+        "EventCode": "0xa2",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa7",
-        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_ALL",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
+        "EventCode": "0xa2",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa2",
         "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa2",
         "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
         "EventCode": "0xa2",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
         "EventCode": "0xa2",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.IV",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
         "EventCode": "0xa2",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
         "EventCode": "0xa2",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
         "EventCode": "0xa2",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa2",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_ALL",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
+        "EventCode": "0xa3",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa2",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_ALL",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
+        "EventCode": "0xa3",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa3",
         "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa3",
         "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
         "EventCode": "0xa3",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
         "EventCode": "0xa3",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.IV",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
         "EventCode": "0xa3",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
         "EventCode": "0xa3",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
         "EventCode": "0xa3",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa3",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_ALL",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
+        "EventCode": "0xa1",
+        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa3",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_ALL",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
+        "EventCode": "0xa1",
+        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa1",
         "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Inserts : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa1",
         "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa1",
-        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_UNCRD",
-        "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
-    },
-    {
-        "BriefDescription": "CMS Horizontal Egress Inserts : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
         "EventCode": "0xa1",
-        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.IV",
+        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
         "EventCode": "0xa1",
-        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa1",
         "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
         "EventCode": "0xa1",
-        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AKC_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Inserts : IV",
         "EventCode": "0xa1",
-        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_ALL",
+        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.IV",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
+        "EventCode": "0xa4",
+        "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa1",
-        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_ALL",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
+        "EventCode": "0xa4",
+        "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa4",
         "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal Egress NACKs : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa4",
         "EventName": "UNC_M2P_TxR_HORZ_NACK.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
         "EventCode": "0xa4",
-        "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_NACK.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
         "EventCode": "0xa4",
-        "EventName": "UNC_M2P_TxR_HORZ_NACK.IV",
+        "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
         "EventCode": "0xa4",
-        "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
         "EventCode": "0xa4",
-        "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress NACKs : IV",
         "EventCode": "0xa4",
-        "EventName": "UNC_M2P_TxR_HORZ_NACK.AKC_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_NACK.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa4",
-        "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_ALL",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
+        "EventCode": "0xa0",
+        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa4",
-        "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_ALL",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
+        "EventCode": "0xa0",
+        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa0",
         "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa0",
         "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
-    },
-    {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa0",
-        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_UNCRD",
-        "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
         "EventCode": "0xa0",
-        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.IV",
+        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
         "EventCode": "0xa0",
-        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa0",
         "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
         "EventCode": "0xa0",
-        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
         "EventCode": "0xa0",
-        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_ALL",
+        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.IV",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa0",
-        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_ALL",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
+        "EventCode": "0xa5",
+        "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa5",
         "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa5",
         "EventName": "UNC_M2P_TxR_HORZ_STARVED.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
-    },
-    {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa5",
-        "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_UNCRD",
-        "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
         "EventCode": "0xa5",
-        "EventName": "UNC_M2P_TxR_HORZ_STARVED.IV",
+        "EventName": "UNC_M2P_TxR_HORZ_STARVED.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
         "EventCode": "0xa5",
-        "EventName": "UNC_M2P_TxR_HORZ_STARVED.AKC_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
         "EventCode": "0xa5",
-        "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_ALL",
+        "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
         "EventCode": "0xa5",
-        "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_ALL",
+        "EventName": "UNC_M2P_TxR_HORZ_STARVED.IV",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9c",
         "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
         "EventCode": "0x9c",
-        "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
         "EventCode": "0x9c",
-        "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9c",
         "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
         "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9d",
         "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
         "EventCode": "0x9d",
-        "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
         "EventCode": "0x9d",
-        "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
         "EventCode": "0x9d",
-        "EventName": "UNC_M2P_TxR_VERT_BYPASS.IV_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
         "EventCode": "0x9d",
-        "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
         "EventCode": "0x9d",
-        "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
         "EventCode": "0x9d",
-        "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_BYPASS.IV_AG1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9e",
         "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9e",
         "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x94",
         "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
         "EventCode": "0x94",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
         "EventCode": "0x94",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
         "EventCode": "0x94",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.IV_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
         "EventCode": "0x94",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
         "EventCode": "0x94",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
         "EventCode": "0x94",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x95",
         "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x95",
         "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x96",
         "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
         "EventCode": "0x96",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
         "EventCode": "0x96",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
         "EventCode": "0x96",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.IV_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
         "EventCode": "0x96",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
         "EventCode": "0x96",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
         "EventCode": "0x96",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x97",
         "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x97",
         "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG0",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
-    },
-    {
-        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG0",
-        "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
-    },
-    {
-        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x92",
-        "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG0",
-        "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
-    },
-    {
-        "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2P_TxR_VERT_INSERTS0.IV_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x92",
         "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
         "UMask": "0x10",
         "Unit": "M2PCIe"
     },
+    {
+        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG0",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
+    },
     {
         "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x92",
         "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
         "UMask": "0x20",
         "Unit": "M2PCIe"
     },
+    {
+        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG0",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
+    },
     {
         "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x92",
         "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
         "UMask": "0x40",
         "Unit": "M2PCIe"
     },
+    {
+        "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2P_TxR_VERT_INSERTS0.IV_AG0",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
+    },
     {
         "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x93",
         "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x93",
         "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x98",
         "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
         "EventCode": "0x98",
-        "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
         "EventCode": "0x98",
-        "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
         "EventCode": "0x98",
-        "EventName": "UNC_M2P_TxR_VERT_NACK0.IV_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
         "EventCode": "0x98",
-        "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
         "EventCode": "0x98",
-        "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress NACKs : IV",
         "EventCode": "0x98",
-        "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_NACK0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x99",
         "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x99",
         "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x90",
         "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
         "EventCode": "0x90",
-        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
         "EventCode": "0x90",
-        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
         "EventCode": "0x90",
-        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.IV_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
         "EventCode": "0x90",
-        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
         "EventCode": "0x90",
-        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
         "EventCode": "0x90",
-        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x91",
         "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x91",
         "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9a",
         "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
         "EventCode": "0x9a",
-        "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
         "EventCode": "0x9a",
-        "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
         "EventCode": "0x9a",
-        "EventName": "UNC_M2P_TxR_VERT_STARVED0.IV_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
         "EventCode": "0x9a",
-        "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
         "EventCode": "0x9a",
-        "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
         "EventCode": "0x9a",
-        "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_STARVED0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9b",
         "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9b",
         "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9b",
         "EventName": "UNC_M2P_TxR_VERT_STARVED1.TGC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
-    },
-    {
-        "BriefDescription": "Vertical AD Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb0",
-        "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_EVEN",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
-    },
-    {
-        "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb0",
-        "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_ODD",
-        "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Vertical AD Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xb0",
         "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xb0",
         "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb4",
-        "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_EVEN",
+        "BriefDescription": "Vertical AD Ring In Use : Up and Even",
+        "EventCode": "0xb0",
+        "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb4",
-        "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_ODD",
+        "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
+        "EventCode": "0xb0",
+        "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xb4",
         "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xb4",
         "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb1",
-        "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_EVEN",
+        "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
+        "EventCode": "0xb4",
+        "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb1",
-        "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_ODD",
+        "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
+        "EventCode": "0xb4",
+        "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Vertical AK Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xb1",
         "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xb1",
         "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb2",
-        "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_EVEN",
+        "BriefDescription": "Vertical AK Ring In Use : Up and Even",
+        "EventCode": "0xb1",
+        "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb2",
-        "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_ODD",
+        "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
+        "EventCode": "0xb1",
+        "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Vertical BL Ring in Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xb2",
         "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xb2",
         "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical IV Ring in Use : Up",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb3",
-        "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.UP",
+        "BriefDescription": "Vertical BL Ring in Use : Up and Even",
+        "EventCode": "0xb2",
+        "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
+        "EventCode": "0xb2",
+        "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_ODD",
+        "PerPkg": "1",
+        "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Vertical IV Ring in Use : Down",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xb3",
         "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.DN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Vertical IV Ring in Use : Up",
+        "EventCode": "0xb3",
+        "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.UP",
+        "PerPkg": "1",
+        "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
         "EventCode": "0xb5",
-        "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_EVEN",
+        "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
         "EventCode": "0xb5",
-        "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_ODD",
+        "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
         "EventCode": "0xb5",
-        "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_EVEN",
+        "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
         "EventCode": "0xb5",
-        "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_ODD",
+        "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x80",
         "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x80",
         "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x80",
         "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x80",
         "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x80",
         "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x80",
         "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x80",
         "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x80",
         "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
         "EventCode": "0x81",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR8",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
         "EventCode": "0x81",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR9",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
         "EventCode": "0x81",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR10",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x82",
         "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x82",
         "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x82",
         "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x82",
         "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x82",
         "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x82",
         "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x82",
         "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x82",
         "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
         "EventCode": "0x83",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR8",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
         "EventCode": "0x83",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR9",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
         "EventCode": "0x83",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR10",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x88",
         "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x88",
         "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x88",
         "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x88",
         "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x88",
         "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x88",
         "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x88",
         "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x88",
         "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
         "EventCode": "0x89",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR8",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
         "EventCode": "0x89",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR9",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
         "EventCode": "0x89",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR10",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8A",
         "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8A",
         "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8A",
         "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8A",
         "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8A",
         "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8A",
         "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8A",
         "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8A",
         "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
         "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
         "EventCode": "0x8B",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR8",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
         "EventCode": "0x8B",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR9",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
         "EventCode": "0x8B",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR10",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x84",
         "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x84",
         "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x84",
         "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x84",
         "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x84",
         "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x84",
         "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x84",
         "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x84",
         "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
         "EventCode": "0x85",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR8",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
         "EventCode": "0x85",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR9",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
         "EventCode": "0x85",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR10",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x86",
         "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x86",
         "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x86",
         "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x86",
         "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x86",
         "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x86",
         "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x86",
         "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x86",
         "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
         "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
         "EventCode": "0x87",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR8",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
         "EventCode": "0x87",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR9",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
         "EventCode": "0x87",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR10",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8C",
         "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8C",
         "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8C",
         "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8C",
         "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8C",
         "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8C",
         "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8C",
         "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8C",
         "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
         "EventCode": "0x8D",
-        "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR8",
+        "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
         "EventCode": "0x8D",
-        "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR9",
+        "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
         "EventCode": "0x8D",
-        "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR10",
+        "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8E",
         "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8E",
         "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8E",
         "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8E",
         "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8E",
         "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8E",
         "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8E",
         "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8E",
         "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
         "UMask": "0x80",
         "Unit": "M3UPI"
     },
+    {
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
+        "EventCode": "0x8F",
+        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR10",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
+    },
     {
         "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8F",
         "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x8F",
         "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8F",
-        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "CBox AD Credits Empty : Requests",
+        "EventCode": "0x22",
+        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CBox AD Credits Empty : Requests : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Distress signal asserted : Vertical",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.VERT",
+        "BriefDescription": "CBox AD Credits Empty : Snoops",
+        "EventCode": "0x22",
+        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CBox AD Credits Empty : Snoops : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Distress signal asserted : Horizontal",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.HORZ",
+        "BriefDescription": "CBox AD Credits Empty : VNA Messages",
+        "EventCode": "0x22",
+        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA",
+        "PerPkg": "1",
+        "PublicDescription": "CBox AD Credits Empty : VNA Messages : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "CBox AD Credits Empty : Writebacks",
+        "EventCode": "0x22",
+        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB",
+        "PerPkg": "1",
+        "PublicDescription": "CBox AD Credits Empty : Writebacks : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "Clockticks of the mesh to UPI (M3UPI)",
+        "EventCode": "0x01",
+        "EventName": "UNC_M3UPI_CLOCKTICKS",
+        "PerPkg": "1",
+        "PublicDescription": "Clockticks of the mesh to UPI (M3UPI) : Counts the number of uclks in the M3 uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "CMS Clockticks",
+        "EventCode": "0xc0",
+        "EventName": "UNC_M3UPI_CMS_CLOCKTICKS",
+        "PerPkg": "1",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "D2C Sent",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M3UPI_D2C_SENT",
+        "PerPkg": "1",
+        "PublicDescription": "D2C Sent : Count cases BL sends direct to core",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "D2U Sent",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M3UPI_D2U_SENT",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "D2U Sent : Cases where SMI3 sends D2U command",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Distress signal asserted : DPT Local",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xAF",
         "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Distress signal asserted : DPT Remote",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xAF",
         "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_NONLOCAL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xAF",
         "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_STALL_IV",
         "PerPkg": "1",
+        "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Distress signal asserted : DPT Stalled -  No Credit",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xAF",
         "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
         "PerPkg": "1",
+        "PublicDescription": "Distress signal asserted : DPT Stalled -  No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
         "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBA",
-        "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP",
+        "BriefDescription": "Distress signal asserted : Horizontal",
+        "EventCode": "0xAF",
+        "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.HORZ",
+        "PerPkg": "1",
+        "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "Distress signal asserted : PMM Local",
+        "EventCode": "0xAF",
+        "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_LOCAL",
+        "PerPkg": "1",
+        "PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "Distress signal asserted : PMM Remote",
+        "EventCode": "0xAF",
+        "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_NONLOCAL",
+        "PerPkg": "1",
+        "PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "Distress signal asserted : Vertical",
+        "EventCode": "0xAF",
+        "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.VERT",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xBA",
         "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+        "EventCode": "0xBA",
+        "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP",
+        "PerPkg": "1",
+        "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB6",
         "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB6",
         "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB6",
         "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB6",
         "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xBB",
         "EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xBB",
         "EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xBB",
         "EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xBB",
         "EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB7",
         "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB7",
         "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB7",
         "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB7",
         "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB8",
         "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB8",
         "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB8",
         "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB8",
         "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Horizontal IV Ring in Use : Left",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB9",
         "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Horizontal IV Ring in Use : Right",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB9",
         "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)",
+        "EventCode": "0x23",
+        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO1_NCB",
+        "PerPkg": "1",
+        "PublicDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only) : No vn0 and vna credits available to send to M2",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "M2 BL Credits Empty : IIO2",
+        "EventCode": "0x23",
+        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB",
+        "PerPkg": "1",
+        "PublicDescription": "M2 BL Credits Empty : IIO2 : No vn0 and vna credits available to send to M2",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "M2 BL Credits Empty : IIO3",
+        "EventCode": "0x23",
+        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB",
+        "PerPkg": "1",
+        "PublicDescription": "M2 BL Credits Empty : IIO3 : No vn0 and vna credits available to send to M2",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "M2 BL Credits Empty : IIO4",
+        "EventCode": "0x23",
+        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB",
+        "PerPkg": "1",
+        "PublicDescription": "M2 BL Credits Empty : IIO4 : No vn0 and vna credits available to send to M2",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "M2 BL Credits Empty : IIO5",
+        "EventCode": "0x23",
+        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB",
+        "PerPkg": "1",
+        "PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together",
+        "EventCode": "0x23",
+        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS",
+        "PerPkg": "1",
+        "PublicDescription": "M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together : No vn0 and vna credits available to send to M2",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "M2 BL Credits Empty : Selected M2p BL NCS credits",
+        "EventCode": "0x23",
+        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL",
+        "PerPkg": "1",
+        "PublicDescription": "M2 BL Credits Empty : Selected M2p BL NCS credits : No vn0 and vna credits available to send to M2",
+        "UMask": "0x80",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "M2 BL Credits Empty : IIO5",
+        "EventCode": "0x23",
+        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.UBOX_NCB",
+        "PerPkg": "1",
+        "PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xE6",
         "EventName": "UNC_M3UPI_MISC_EXTERNAL.MBE_INST0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xE6",
         "EventName": "UNC_M3UPI_MISC_EXTERNAL.MBE_INST1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "Multi Slot Flit Received : AD - Slot 0",
+        "EventCode": "0x3E",
+        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0",
+        "PerPkg": "1",
+        "PublicDescription": "Multi Slot Flit Received : AD - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "Multi Slot Flit Received : AD - Slot 1",
+        "EventCode": "0x3E",
+        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1",
+        "PerPkg": "1",
+        "PublicDescription": "Multi Slot Flit Received : AD - Slot 1 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "Multi Slot Flit Received : AD - Slot 2",
+        "EventCode": "0x3E",
+        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2",
+        "PerPkg": "1",
+        "PublicDescription": "Multi Slot Flit Received : AD - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "Multi Slot Flit Received : AK - Slot 0",
+        "EventCode": "0x3E",
+        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0",
+        "PerPkg": "1",
+        "PublicDescription": "Multi Slot Flit Received : AK - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "Multi Slot Flit Received : AK - Slot 2",
+        "EventCode": "0x3E",
+        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2",
+        "PerPkg": "1",
+        "PublicDescription": "Multi Slot Flit Received : AK - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "Multi Slot Flit Received : BL - Slot 0",
+        "EventCode": "0x3E",
+        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0",
+        "PerPkg": "1",
+        "PublicDescription": "Multi Slot Flit Received : BL - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xAC",
         "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xAC",
         "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xAC",
         "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xAC",
         "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xAA",
         "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xAA",
         "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.",
         "EventCode": "0xAA",
-        "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL",
+        "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AKC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
         "EventCode": "0xAA",
-        "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV",
+        "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
         "EventCode": "0xAA",
-        "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AKC",
+        "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xAD",
         "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xAD",
         "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
         "EventCode": "0xAD",
-        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL",
+        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
         "EventCode": "0xAD",
-        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV",
+        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
         "EventCode": "0xAD",
-        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1",
+        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Sink Starvation on Vertical Ring : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xAB",
         "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xAB",
         "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "Sink Starvation on Vertical Ring",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AKC",
+        "PerPkg": "1",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
         "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xAB",
         "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
         "EventCode": "0xAB",
         "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AKC",
+        "BriefDescription": "Source Throttle",
+        "EventCode": "0xae",
+        "EventName": "UNC_M3UPI_RING_SRC_THRTL",
         "PerPkg": "1",
-        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_UNCRD",
+        "BriefDescription": "Lost Arb for VN0 : REQ on AD",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Lost Arb for VN0 : REQ on AD : VN0 message requested but lost arbitration : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_UNCRD",
+        "BriefDescription": "Lost Arb for VN0 : RSP on AD",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Lost Arb for VN0 : RSP on AD : VN0 message requested but lost arbitration : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD",
+        "BriefDescription": "Lost Arb for VN0 : SNP on AD",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Lost Arb for VN0 : SNP on AD : VN0 message requested but lost arbitration : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD",
+        "BriefDescription": "Lost Arb for VN0 : NCB on BL",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Lost Arb for VN0 : NCB on BL : VN0 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_ALL",
+        "BriefDescription": "Lost Arb for VN0 : NCS on BL",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Lost Arb for VN0 : NCS on BL : VN0 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_ALL",
+        "BriefDescription": "Lost Arb for VN0 : RSP on BL",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Lost Arb for VN0 : RSP on BL : VN0 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_M3UPI_RxR_BYPASS.AD_UNCRD",
+        "BriefDescription": "Lost Arb for VN0 : WB on BL",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Lost Arb for VN0 : WB on BL : VN0 message requested but lost arbitration : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_M3UPI_RxR_BYPASS.AK",
+        "BriefDescription": "Lost Arb for VN1 : REQ on AD",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Lost Arb for VN1 : REQ on AD : VN1 message requested but lost arbitration : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_M3UPI_RxR_BYPASS.BL_UNCRD",
+        "BriefDescription": "Lost Arb for VN1 : RSP on AD",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Lost Arb for VN1 : RSP on AD : VN1 message requested but lost arbitration : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_M3UPI_RxR_BYPASS.IV",
+        "BriefDescription": "Lost Arb for VN1 : SNP on AD",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Lost Arb for VN1 : SNP on AD : VN1 message requested but lost arbitration : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD",
+        "BriefDescription": "Lost Arb for VN1 : NCB on BL",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Lost Arb for VN1 : NCB on BL : VN1 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD",
+        "BriefDescription": "Lost Arb for VN1 : NCS on BL",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS",
         "PerPkg": "1",
+        "PublicDescription": "Lost Arb for VN1 : NCS on BL : VN1 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_M3UPI_RxR_BYPASS.AKC_UNCRD",
+        "BriefDescription": "Lost Arb for VN1 : RSP on BL",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Lost Arb for VN1 : RSP on BL : VN1 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_M3UPI_RxR_BYPASS.AD_ALL",
+        "BriefDescription": "Lost Arb for VN1 : WB on BL",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Lost Arb for VN1 : WB on BL : VN1 message requested but lost arbitration : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_M3UPI_RxR_BYPASS.BL_ALL",
+        "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN0",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0 : AD and BL messages won arbitration concurrently / in parallel",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_UNCRD",
+        "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1 : AD and BL messages won arbitration concurrently / in parallel",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK",
+        "BriefDescription": "Arb Miscellaneous : Max Parallel Win",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M3UPI_RxC_ARB_MISC.ALL_PARALLEL_WIN",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Arb Miscellaneous : Max Parallel Win : VN0 and VN1 arbitration sub-pipelines both produced AD and BL winners (maximum possible parallel winners)",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_UNCRD",
+        "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN0",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Arb Miscellaneous : No Progress on Pending AD VN0 : Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV",
+        "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN1",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Arb Miscellaneous : No Progress on Pending AD VN1 : Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD",
+        "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN0",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Arb Miscellaneous : No Progress on Pending BL VN0 : Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD",
+        "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN1",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Arb Miscellaneous : No Progress on Pending BL VN1 : Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV",
+        "BriefDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M3UPI_RxC_ARB_MISC.VN01_PARALLEL_WIN",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win : VN0 and VN1 arbitration sub-pipelines had parallel winners (at least one AD or BL on each side)",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_ALL",
+        "BriefDescription": "No Credits to Arb for VN0 : REQ on AD",
+        "EventCode": "0x47",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "No Credits to Arb for VN0 : REQ on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_ALL",
+        "BriefDescription": "No Credits to Arb for VN0 : RSP on AD",
+        "EventCode": "0x47",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "No Credits to Arb for VN0 : RSP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_M3UPI_RxR_INSERTS.AD_UNCRD",
+        "BriefDescription": "No Credits to Arb for VN0 : SNP on AD",
+        "EventCode": "0x47",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "No Credits to Arb for VN0 : SNP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_M3UPI_RxR_INSERTS.AK",
+        "BriefDescription": "No Credits to Arb for VN0 : NCB on BL",
+        "EventCode": "0x47",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "No Credits to Arb for VN0 : NCB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_M3UPI_RxR_INSERTS.BL_UNCRD",
+        "BriefDescription": "No Credits to Arb for VN0 : NCS on BL",
+        "EventCode": "0x47",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "No Credits to Arb for VN0 : NCS on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_M3UPI_RxR_INSERTS.IV",
+        "BriefDescription": "No Credits to Arb for VN0 : RSP on BL",
+        "EventCode": "0x47",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "No Credits to Arb for VN0 : RSP on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD",
+        "BriefDescription": "No Credits to Arb for VN0 : WB on BL",
+        "EventCode": "0x47",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_WB",
         "PerPkg": "1",
+        "PublicDescription": "No Credits to Arb for VN0 : WB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD",
-        "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
-    },
-    {
-        "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_M3UPI_RxR_INSERTS.AKC_UNCRD",
+        "BriefDescription": "No Credits to Arb for VN1 : REQ on AD",
+        "EventCode": "0x48",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "No Credits to Arb for VN1 : REQ on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_M3UPI_RxR_INSERTS.AD_ALL",
+        "BriefDescription": "No Credits to Arb for VN1 : RSP on AD",
+        "EventCode": "0x48",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "No Credits to Arb for VN1 : RSP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_M3UPI_RxR_INSERTS.BL_ALL",
+        "BriefDescription": "No Credits to Arb for VN1 : SNP on AD",
+        "EventCode": "0x48",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "No Credits to Arb for VN1 : SNP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_UNCRD",
+        "BriefDescription": "No Credits to Arb for VN1 : NCB on BL",
+        "EventCode": "0x48",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "No Credits to Arb for VN1 : NCB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK",
+        "BriefDescription": "No Credits to Arb for VN1 : NCS on BL",
+        "EventCode": "0x48",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "No Credits to Arb for VN1 : NCS on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_UNCRD",
+        "BriefDescription": "No Credits to Arb for VN1 : RSP on BL",
+        "EventCode": "0x48",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "No Credits to Arb for VN1 : RSP on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV",
+        "BriefDescription": "No Credits to Arb for VN1 : WB on BL",
+        "EventCode": "0x48",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "No Credits to Arb for VN1 : WB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD",
+        "BriefDescription": "Can't Arb for VN0 : REQ on AD",
+        "EventCode": "0x49",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Can't Arb for VN0 : REQ on AD : VN0 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD",
+        "BriefDescription": "Can't Arb for VN0 : RSP on AD",
+        "EventCode": "0x49",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Can't Arb for VN0 : RSP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AKC_UNCRD",
+        "BriefDescription": "Can't Arb for VN0 : SNP on AD",
+        "EventCode": "0x49",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Can't Arb for VN0 : SNP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_ALL",
+        "BriefDescription": "Can't Arb for VN0 : NCB on BL",
+        "EventCode": "0x49",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Can't Arb for VN0 : NCB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_ALL",
+        "BriefDescription": "Can't Arb for VN0 : NCS on BL",
+        "EventCode": "0x49",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Can't Arb for VN0 : NCS on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+        "BriefDescription": "Can't Arb for VN0 : RSP on BL",
+        "EventCode": "0x49",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Can't Arb for VN0 : RSP on BL : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+        "BriefDescription": "Can't Arb for VN0 : WB on BL",
+        "EventCode": "0x49",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Can't Arb for VN0 : WB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+        "BriefDescription": "Can't Arb for VN1 : REQ on AD",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Can't Arb for VN1 : REQ on AD : VN1 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+        "BriefDescription": "Can't Arb for VN1 : RSP on AD",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Can't Arb for VN1 : RSP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+        "BriefDescription": "Can't Arb for VN1 : SNP on AD",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Can't Arb for VN1 : SNP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+        "BriefDescription": "Can't Arb for VN1 : NCB on BL",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCB",
         "PerPkg": "1",
+        "PublicDescription": "Can't Arb for VN1 : NCB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
+        "BriefDescription": "Can't Arb for VN1 : NCS on BL",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCS",
         "PerPkg": "1",
+        "PublicDescription": "Can't Arb for VN1 : NCS on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL.",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
+        "BriefDescription": "Can't Arb for VN1 : RSP on BL",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Can't Arb for VN1 : RSP on BL : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+        "BriefDescription": "Can't Arb for VN1 : WB on BL",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Can't Arb for VN1 : WB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+        "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL Arb",
+        "EventCode": "0x40",
+        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL Arb : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while bl message is in arbitration",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+        "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle",
+        "EventCode": "0x40",
+        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while pipeline is idle",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+        "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 1",
+        "EventCode": "0x40",
+        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 1 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 1 while merging with bl message in same flit",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+        "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 2",
+        "EventCode": "0x40",
+        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 2 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 2 while merging with bl message in same flit",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+        "BriefDescription": "Miscellaneous Credit Events : Any In BGF FIFO",
+        "EventCode": "0x5F",
+        "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Miscellaneous Credit Events : Any In BGF FIFO : Indication that at least one packet (flit) is in the bgf (fifo only)",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
+        "BriefDescription": "Miscellaneous Credit Events : Any in BGF Path",
+        "EventCode": "0x5F",
+        "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Miscellaneous Credit Events : Any in BGF Path : Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo)",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
+        "BriefDescription": "Miscellaneous Credit Events",
+        "EventCode": "0x5F",
+        "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT1_FOR_D2K",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Miscellaneous Credit Events : d2k credit count is less than 1",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+        "BriefDescription": "Miscellaneous Credit Events",
+        "EventCode": "0x5F",
+        "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT2_FOR_D2K",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Miscellaneous Credit Events : d2k credit count is less than 2",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+        "BriefDescription": "Miscellaneous Credit Events : No D2K For Arb",
+        "EventCode": "0x5F",
+        "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN0_NO_D2K_FOR_ARB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Miscellaneous Credit Events : No D2K For Arb : VN0 BL RSP message was blocked from arbitration request due to lack of D2K CMP credit",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+        "BriefDescription": "Miscellaneous Credit Events",
+        "EventCode": "0x5F",
+        "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN1_NO_D2K_FOR_ARB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Miscellaneous Credit Events : VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+        "BriefDescription": "Credit Occupancy : Credits Consumed",
+        "EventCode": "0x60",
+        "EventName": "UNC_M3UPI_RxC_CRD_OCC.CONSUMED",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Credit Occupancy : Credits Consumed : number of remote vna credits consumed per cycle",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+        "BriefDescription": "Credit Occupancy : D2K Credits",
+        "EventCode": "0x60",
+        "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Credit Occupancy : D2K Credits : D2K completion fifo credit occupancy (credits in use), accumulated across all cycles",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+        "BriefDescription": "Credit Occupancy : Packets in BGF FIFO",
+        "EventCode": "0x60",
+        "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Credit Occupancy : Packets in BGF FIFO : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
+        "BriefDescription": "Credit Occupancy : Packets in BGF Path",
+        "EventCode": "0x60",
+        "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH",
+        "PerPkg": "1",
+        "PublicDescription": "Credit Occupancy : Packets in BGF Path : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo)",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "Credit Occupancy",
+        "EventCode": "0x60",
+        "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO",
         "PerPkg": "1",
+        "PublicDescription": "Credit Occupancy : count of bl messages in pump-1-pending state, in completion fifo only",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+        "BriefDescription": "Credit Occupancy",
+        "EventCode": "0x60",
+        "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Credit Occupancy : count of bl messages in pump-1-pending state, in marker table and in fifo",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+        "BriefDescription": "Credit Occupancy : Transmit Credits",
+        "EventCode": "0x60",
+        "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Credit Occupancy : Transmit Credits : Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+        "BriefDescription": "Credit Occupancy : VNA In Use",
+        "EventCode": "0x60",
+        "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Credit Occupancy : VNA In Use : Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD",
+        "EventCode": "0x43",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD : Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD",
+        "EventCode": "0x43",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD : Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD",
+        "EventCode": "0x43",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD : Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL",
+        "EventCode": "0x43",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB",
         "PerPkg": "1",
+        "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL : Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL",
+        "EventCode": "0x43",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS",
         "PerPkg": "1",
+        "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL : Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL",
+        "EventCode": "0x43",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL : Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD1",
-        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL",
+        "EventCode": "0x43",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL : Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD1",
-        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD",
+        "EventCode": "0x44",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD1",
-        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD",
+        "EventCode": "0x44",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD3",
-        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD",
+        "EventCode": "0x44",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD3",
-        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL",
+        "EventCode": "0x44",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD3",
-        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL",
+        "EventCode": "0x44",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD5",
-        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL",
+        "EventCode": "0x44",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD5",
-        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL",
+        "EventCode": "0x44",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD5",
-        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+        "BriefDescription": "Data Flit Not Sent : All",
+        "EventCode": "0x55",
+        "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Data Flit Not Sent : All : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but could not be sent for any reason, e.g. low credits, low tsv, stall injection",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD7",
-        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+        "BriefDescription": "Data Flit Not Sent : No BGF Credits",
+        "EventCode": "0x55",
+        "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_BGF",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Data Flit Not Sent : No BGF Credits : Data flit is ready for transmission but could not be sent",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD7",
-        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+        "BriefDescription": "Data Flit Not Sent : No TxQ Credits",
+        "EventCode": "0x55",
+        "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_TXQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Data Flit Not Sent : No TxQ Credits : Data flit is ready for transmission but could not be sent",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD7",
-        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+        "BriefDescription": "Data Flit Not Sent : TSV High",
+        "EventCode": "0x55",
+        "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.TSV_HI",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Data Flit Not Sent : TSV High : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while tsv high",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_UNCRD",
+        "BriefDescription": "Data Flit Not Sent : Cycle valid for Flit",
+        "EventCode": "0x55",
+        "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.VALID_FOR_FLIT",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Data Flit Not Sent : Cycle valid for Flit : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while cycle is valid for flit transmission",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_UNCRD",
+        "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 0",
+        "EventCode": "0x57",
+        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Generating BL Data Flit Sequence : Wait on Pump 0 : generating bl data flit sequence; waiting for data pump 0",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD",
+        "BriefDescription": "Generating BL Data Flit Sequence",
+        "EventCode": "0x57",
+        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT",
         "PerPkg": "1",
+        "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is at capacity (pending table plus completion fifo at limit)",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD",
+        "BriefDescription": "Generating BL Data Flit Sequence",
+        "EventCode": "0x57",
+        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is tracking at least one message",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_ALL",
+        "BriefDescription": "Generating BL Data Flit Sequence",
+        "EventCode": "0x57",
+        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending completion fifo is full",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_ALL",
+        "BriefDescription": "Generating BL Data Flit Sequence",
+        "EventCode": "0x57",
+        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_UNCRD",
+        "BriefDescription": "Generating BL Data Flit Sequence",
+        "EventCode": "0x57",
+        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Generating BL Data Flit Sequence : a bl message finished but is in limbo and moved to pump-1-pending logic",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK",
+        "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 1",
+        "EventCode": "0x57",
+        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Generating BL Data Flit Sequence : Wait on Pump 1 : generating bl data flit sequence; waiting for data pump 1",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_UNCRD",
+        "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF",
+        "EventCode": "0x58",
+        "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": ": slot 2 request naturally serviced during hold-off period",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV",
+        "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE",
+        "EventCode": "0x58",
+        "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": ": slot 2 request forcibly serviced during service window",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD",
+        "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED",
+        "EventCode": "0x58",
+        "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": ": slot 2 request received from link layer while idle (with no slot 2 request active immediately prior)",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD",
+        "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN",
+        "EventCode": "0x58",
+        "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": ": slot 2 request withdrawn during hold-off period or service window",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AKC_UNCRD",
+        "BriefDescription": "Slotting BL Message Into Header Flit : All",
+        "EventCode": "0x56",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_ALL",
+        "BriefDescription": "Slotting BL Message Into Header Flit : Needs Data Flit",
+        "EventCode": "0x56",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Slotting BL Message Into Header Flit : Needs Data Flit : BL message requires data flit sequence",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_ALL",
+        "BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 0",
+        "EventCode": "0x56",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Slotting BL Message Into Header Flit : Wait on Pump 0 : Waiting for header pump 0",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
+        "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1",
+        "EventCode": "0x56",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 : Header pump 1 is not required for flit",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK",
+        "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble",
+        "EventCode": "0x56",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble : Header pump 1 is not required for flit but flit transmission delayed",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
+        "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail",
+        "EventCode": "0x56",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail : Header pump 1 is not required for flit and not available",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV",
+        "BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 1",
+        "EventCode": "0x56",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Slotting BL Message Into Header Flit : Wait on Pump 1 : Waiting for header pump 1",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD",
+        "BriefDescription": "Flit Gen - Header 1 : Accumulate",
+        "EventCode": "0x51",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Flit Gen - Header 1 : Accumulate : Events related to Header Flit Generation - Set 1 : Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD",
+        "BriefDescription": "Flit Gen - Header 1 : Accumulate Ready",
+        "EventCode": "0x51",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Flit Gen - Header 1 : Accumulate Ready : Events related to Header Flit Generation - Set 1 : header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
+        "BriefDescription": "Flit Gen - Header 1 : Accumulate Wasted",
+        "EventCode": "0x51",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Flit Gen - Header 1 : Accumulate Wasted : Events related to Header Flit Generation - Set 1 : Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_ALL",
+        "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked",
+        "EventCode": "0x51",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked : Events related to Header Flit Generation - Set 1 : Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_ALL",
+        "BriefDescription": "Flit Gen - Header 1",
+        "EventCode": "0x51",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_AFTER",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: message was slotted only after run-ahead was over; run-ahead mode definitely wasted",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_UNCRD",
+        "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Message",
+        "EventCode": "0x51",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_DURING",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Message : Events related to Header Flit Generation - Set 1 : run-ahead mode: one message slotted during run-ahead",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK",
+        "BriefDescription": "Flit Gen - Header 1",
+        "EventCode": "0x51",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_AFTER",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: second message slotted immediately after run-ahead; potential run-ahead success",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_UNCRD",
+        "BriefDescription": "Flit Gen - Header 1",
+        "EventCode": "0x51",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_SENT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: two (or three) message flit sent immediately after run-ahead; complete run-ahead success",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV",
+        "BriefDescription": "Flit Gen - Header 2 : Parallel Ok",
+        "EventCode": "0x52",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Flit Gen - Header 2 : Parallel Ok : Events related to Header Flit Generation - Set 2 : new header flit construction may proceed in parallel with data flit sequence",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD",
+        "BriefDescription": "Flit Gen - Header 2 : Parallel Flit Finished",
+        "EventCode": "0x52",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_FLIT",
         "PerPkg": "1",
+        "PublicDescription": "Flit Gen - Header 2 : Parallel Flit Finished : Events related to Header Flit Generation - Set 2 : header flit finished assembly in parallel with data flit sequence",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD",
+        "BriefDescription": "Flit Gen - Header 2 : Parallel Message",
+        "EventCode": "0x52",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_MSG",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Flit Gen - Header 2 : Parallel Message : Events related to Header Flit Generation - Set 2 : message is slotted into header flit in parallel with data flit sequence",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
+        "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall",
+        "EventCode": "0x52",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall : Events related to Header Flit Generation - Set 2 : Rate-matching stall injected",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_ALL",
+        "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall - No Message",
+        "EventCode": "0x52",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall - No Message : Events related to Header Flit Generation - Set 2 : Rate matching stall injected, but no additional message slotted during stall cycle",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_ALL",
+        "BriefDescription": "Sent Header Flit : One Message",
+        "EventCode": "0x54",
+        "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Sent Header Flit : One Message : One message in flit; VNA or non-VNA flit",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_UNCRD",
+        "BriefDescription": "Sent Header Flit : One Message in non-VNA",
+        "EventCode": "0x54",
+        "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG_VNX",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Sent Header Flit : One Message in non-VNA : One message in flit; non-VNA flit",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK",
+        "BriefDescription": "Sent Header Flit : Two Messages",
+        "EventCode": "0x54",
+        "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.2_MSGS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Sent Header Flit : Two Messages : Two messages in flit; VNA flit",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_UNCRD",
+        "BriefDescription": "Sent Header Flit : Three Messages",
+        "EventCode": "0x54",
+        "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.3_MSGS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Sent Header Flit : Three Messages : Three messages in flit; VNA flit",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV",
+        "BriefDescription": "Sent Header Flit : One Slot Taken",
+        "EventCode": "0x54",
+        "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD",
+        "BriefDescription": "Sent Header Flit : Two Slots Taken",
+        "EventCode": "0x54",
+        "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_2",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD",
+        "BriefDescription": "Sent Header Flit : All Slots Taken",
+        "EventCode": "0x54",
+        "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_3",
         "PerPkg": "1",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AKC_UNCRD",
+        "BriefDescription": "Header Not Sent : All",
+        "EventCode": "0x53",
+        "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.ALL",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Header Not Sent : All : header flit is ready for transmission but could not be sent : header flit is ready for transmission but could not be sent for any reason, e.g. no credits, low tsv, stall injection",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_ALL",
+        "BriefDescription": "Header Not Sent : No BGF Credits",
+        "EventCode": "0x53",
+        "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_CRD",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Header Not Sent : No BGF Credits : header flit is ready for transmission but could not be sent : No BGF credits available",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_ALL",
+        "BriefDescription": "Header Not Sent : No BGF Credits + No Extra Message Slotted",
+        "EventCode": "0x53",
+        "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_NO_MSG",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Header Not Sent : No BGF Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No BGF credits available; no additional message slotted into flit",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_UNCRD",
+        "BriefDescription": "Header Not Sent : No TxQ Credits",
+        "EventCode": "0x53",
+        "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Header Not Sent : No TxQ Credits : header flit is ready for transmission but could not be sent : No TxQ credits available",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK",
+        "BriefDescription": "Header Not Sent : No TxQ Credits + No Extra Message Slotted",
+        "EventCode": "0x53",
+        "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_NO_MSG",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Header Not Sent : No TxQ Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No TxQ credits available; no additional message slotted into flit",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_UNCRD",
+        "BriefDescription": "Header Not Sent : TSV High",
+        "EventCode": "0x53",
+        "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.TSV_HI",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Header Not Sent : TSV High : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while tsv high",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV",
+        "BriefDescription": "Header Not Sent : Cycle valid for Flit",
+        "EventCode": "0x53",
+        "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.VALID_FOR_FLIT",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Header Not Sent : Cycle valid for Flit : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while cycle is valid for flit transmission",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD",
+        "BriefDescription": "Message Held : Can't Slot AD",
+        "EventCode": "0x50",
+        "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD",
         "PerPkg": "1",
+        "PublicDescription": "Message Held : Can't Slot AD : some AD message could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1})",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD",
+        "BriefDescription": "Message Held : Can't Slot BL",
+        "EventCode": "0x50",
+        "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Message Held : Can't Slot BL : some BL message could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1})",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AKC_UNCRD",
+        "BriefDescription": "Message Held : Parallel Attempt",
+        "EventCode": "0x50",
+        "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Message Held : Parallel Attempt : ad and bl messages attempted to slot into the same flit in parallel",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_ALL",
+        "BriefDescription": "Message Held : Parallel Success",
+        "EventCode": "0x50",
+        "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Message Held : Parallel Success : ad and bl messages were actually slotted into the same flit in paralle",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_ALL",
+        "BriefDescription": "Message Held : VN0",
+        "EventCode": "0x50",
+        "EventName": "UNC_M3UPI_RxC_HELD.VN0",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Message Held : VN0 : vn0 message(s) that couldn't be slotted into last vn0 flit are held in slotting stage while processing vn1 flit",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_UNCRD",
+        "BriefDescription": "Message Held : VN1",
+        "EventCode": "0x50",
+        "EventName": "UNC_M3UPI_RxC_HELD.VN1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Message Held : VN1 : vn1 message(s) that couldn't be slotted into last vn1 flit are held in slotting stage while processing vn0 flit",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : REQ on AD",
+        "EventCode": "0x41",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : REQ on AD : Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_UNCRD",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on AD",
+        "EventCode": "0x41",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on AD : Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : SNP on AD",
+        "EventCode": "0x41",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : SNP on AD : Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCB on BL",
+        "EventCode": "0x41",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCB on BL : Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCS on BL",
+        "EventCode": "0x41",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS",
         "PerPkg": "1",
+        "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCS on BL : Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on BL",
+        "EventCode": "0x41",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on BL : Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_ALL",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : WB on BL",
+        "EventCode": "0x41",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : WB on BL : Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_ALL",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : REQ on AD",
+        "EventCode": "0x42",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : REQ on AD : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_UNCRD",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on AD",
+        "EventCode": "0x42",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on AD : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : SNP on AD",
+        "EventCode": "0x42",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : SNP on AD : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_UNCRD",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCB on BL",
+        "EventCode": "0x42",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCB on BL : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCS on BL",
+        "EventCode": "0x42",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCS on BL : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AKC_UNCRD",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on BL",
+        "EventCode": "0x42",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on BL : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_ALL",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : WB on BL",
+        "EventCode": "0x42",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : WB on BL : Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_ALL",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD",
+        "EventCode": "0x45",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD",
+        "EventCode": "0x45",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD",
+        "EventCode": "0x45",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL",
+        "EventCode": "0x45",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL",
+        "EventCode": "0x45",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS",
         "PerPkg": "1",
+        "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Standard (NCS) messages on BL.",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL",
+        "EventCode": "0x45",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : WB on BL",
+        "EventCode": "0x45",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : WB on BL : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD",
+        "EventCode": "0x46",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV_AG1",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD",
+        "EventCode": "0x46",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD",
+        "EventCode": "0x46",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL",
+        "EventCode": "0x46",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB",
         "PerPkg": "1",
+        "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL",
+        "EventCode": "0x46",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS",
         "PerPkg": "1",
+        "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Standard (NCS) messages on BL.",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG0",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL",
+        "EventCode": "0x46",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG1",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : WB on BL",
+        "EventCode": "0x46",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : WB on BL : Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency. : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG0",
+        "BriefDescription": "VN0 message can't slot into flit : REQ on AD",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "VN0 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG0",
+        "BriefDescription": "VN0 message can't slot into flit : RSP on AD",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "VN0 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG0",
+        "BriefDescription": "VN0 message can't slot into flit : SNP on AD",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "VN0 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.IV_AG0",
+        "BriefDescription": "VN0 message can't slot into flit : NCB on BL",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "VN0 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG1",
+        "BriefDescription": "VN0 message can't slot into flit : NCS on BL",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "VN0 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG1",
+        "BriefDescription": "VN0 message can't slot into flit : RSP on BL",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "VN0 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG1",
+        "BriefDescription": "VN0 message can't slot into flit : WB on BL",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "VN0 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x95",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG0",
+        "BriefDescription": "VN1 message can't slot into flit : REQ on AD",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "VN1 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x95",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG1",
+        "BriefDescription": "VN1 message can't slot into flit : RSP on AD",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "VN1 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG0",
+        "BriefDescription": "VN1 message can't slot into flit : SNP on AD",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "VN1 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG0",
+        "BriefDescription": "VN1 message can't slot into flit : NCB on BL",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "VN1 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG0",
+        "BriefDescription": "VN1 message can't slot into flit : NCS on BL",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "VN1 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.IV_AG0",
+        "BriefDescription": "VN1 message can't slot into flit : RSP on BL",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "VN1 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG1",
+        "BriefDescription": "VN1 message can't slot into flit : WB on BL",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB",
         "PerPkg": "1",
+        "PublicDescription": "VN1 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG1",
+        "BriefDescription": "Remote VNA Credits : Any In Use",
+        "EventCode": "0x5A",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE",
         "PerPkg": "1",
+        "PublicDescription": "Remote VNA Credits : Any In Use : At least one remote vna credit is in use",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG1",
+        "BriefDescription": "Remote VNA Credits : Corrected",
+        "EventCode": "0x5A",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Remote VNA Credits : Corrected : Number of remote vna credits corrected (local return) per cycle",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x97",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG0",
+        "BriefDescription": "Remote VNA Credits : Level < 1",
+        "EventCode": "0x5A",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Remote VNA Credits : Level < 1 : Remote vna credit level is less than 1 (i.e. no vna credits available)",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x97",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG1",
+        "BriefDescription": "Remote VNA Credits : Level < 10",
+        "EventCode": "0x5A",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT10",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Remote VNA Credits : Level < 10 : remote vna credit level is less than 10; parallel vn0/vn1 arb not possible",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG0",
+        "BriefDescription": "Remote VNA Credits : Level < 4",
+        "EventCode": "0x5A",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Remote VNA Credits : Level < 4 : Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG0",
+        "BriefDescription": "Remote VNA Credits : Level < 5",
+        "EventCode": "0x5A",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Remote VNA Credits : Level < 5 : Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG0",
+        "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5",
+        "EventCode": "0x59",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": ": remote vna credit count was less than 5 and allocation to ad or bl messages was required",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.IV_AG0",
+        "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10",
+        "EventCode": "0x59",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": ": remote vna credit count was less than 10 and allocation to vn0 or vn1 was required",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG1",
+        "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD",
+        "EventCode": "0x59",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD",
+        "PerPkg": "1",
+        "PublicDescription": ": on vn0, remote vna credits were allocated only to ad messages, not to bl",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL",
+        "EventCode": "0x59",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": ": on vn0, remote vna credits were allocated only to bl messages, not to ad",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG1",
+        "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY",
+        "EventCode": "0x59",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": ": remote vna credits were allocated only to vn0, not to vn1",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG1",
+        "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD",
+        "EventCode": "0x59",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD",
         "PerPkg": "1",
+        "PublicDescription": ": on vn1, remote vna credits were allocated only to ad messages, not to bl",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x93",
-        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG0",
+        "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL",
+        "EventCode": "0x59",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": ": on vn1, remote vna credits were allocated only to bl messages, not to ad",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x93",
-        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG1",
+        "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY",
+        "EventCode": "0x59",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": ": remote vna credits were allocated only to vn1, not to vn0",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG0",
+        "BriefDescription": "Transgress Injection Starvation : AD - All",
+        "EventCode": "0xE5",
+        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG0",
+        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+        "EventCode": "0xE5",
+        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG0",
+        "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+        "EventCode": "0xE5",
+        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_M3UPI_TxR_VERT_NACK0.IV_AG0",
+        "BriefDescription": "Transgress Injection Starvation : BL - All",
+        "EventCode": "0xE5",
+        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG1",
+        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
+        "EventCode": "0xE5",
+        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG1",
+        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+        "EventCode": "0xE5",
+        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG1",
+        "BriefDescription": "Transgress Ingress Bypass : AD - All",
+        "EventCode": "0xE2",
+        "EventName": "UNC_M3UPI_RxR_BYPASS.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x99",
-        "EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG0",
+        "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
+        "EventCode": "0xE2",
+        "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x99",
-        "EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG1",
+        "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
+        "EventCode": "0xE2",
+        "EventName": "UNC_M3UPI_RxR_BYPASS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG0",
+        "BriefDescription": "Transgress Ingress Bypass : AK",
+        "EventCode": "0xE2",
+        "EventName": "UNC_M3UPI_RxR_BYPASS.AK",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG0",
+        "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
+        "EventCode": "0xE2",
+        "EventName": "UNC_M3UPI_RxR_BYPASS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG0",
+        "BriefDescription": "Transgress Ingress Bypass : BL - All",
+        "EventCode": "0xE2",
+        "EventName": "UNC_M3UPI_RxR_BYPASS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.IV_AG0",
+        "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
+        "EventCode": "0xE2",
+        "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG1",
+        "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
+        "EventCode": "0xE2",
+        "EventName": "UNC_M3UPI_RxR_BYPASS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG1",
+        "BriefDescription": "Transgress Ingress Bypass : IV",
+        "EventCode": "0xE2",
+        "EventName": "UNC_M3UPI_RxR_BYPASS.IV",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG1",
+        "BriefDescription": "Transgress Injection Starvation : AD - All",
+        "EventCode": "0xE3",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x91",
-        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG0",
+        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+        "EventCode": "0xE3",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x91",
-        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG1",
+        "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+        "EventCode": "0xE3",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG0",
+        "BriefDescription": "Transgress Injection Starvation : AK",
+        "EventCode": "0xE3",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG0",
+        "BriefDescription": "Transgress Injection Starvation : BL - All",
+        "EventCode": "0xE3",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG0",
+        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
+        "EventCode": "0xE3",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.IV_AG0",
+        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+        "EventCode": "0xE3",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG1",
+        "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
+        "EventCode": "0xE3",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG1",
+        "BriefDescription": "Transgress Injection Starvation : IV",
+        "EventCode": "0xE3",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG1",
+        "BriefDescription": "Transgress Injection Starvation",
+        "EventCode": "0xe4",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED_1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9B",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG0",
+        "BriefDescription": "Transgress Ingress Allocations : AD - All",
+        "EventCode": "0xE1",
+        "EventName": "UNC_M3UPI_RxR_INSERTS.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9B",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG1",
+        "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
+        "EventCode": "0xE1",
+        "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9B",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.TGC",
+        "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
+        "EventCode": "0xE1",
+        "EventName": "UNC_M3UPI_RxR_INSERTS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN",
+        "BriefDescription": "Transgress Ingress Allocations : AK",
+        "EventCode": "0xE1",
+        "EventName": "UNC_M3UPI_RxR_INSERTS.AK",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD",
+        "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
+        "EventCode": "0xE1",
+        "EventName": "UNC_M3UPI_RxR_INSERTS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN",
+        "BriefDescription": "Transgress Ingress Allocations : BL - All",
+        "EventCode": "0xE1",
+        "EventName": "UNC_M3UPI_RxR_INSERTS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD",
+        "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
+        "EventCode": "0xE1",
+        "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_EVEN",
+        "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
+        "EventCode": "0xE1",
+        "EventName": "UNC_M3UPI_RxR_INSERTS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_ODD",
+        "BriefDescription": "Transgress Ingress Allocations : IV",
+        "EventCode": "0xE1",
+        "EventName": "UNC_M3UPI_RxR_INSERTS.IV",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_EVEN",
+        "BriefDescription": "Transgress Ingress Occupancy : AD - All",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_ODD",
+        "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN",
+        "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD",
+        "BriefDescription": "Transgress Ingress Occupancy : AK",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN",
+        "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD",
+        "BriefDescription": "Transgress Ingress Occupancy : BL - All",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN",
+        "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD",
+        "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN",
+        "BriefDescription": "Transgress Ingress Occupancy : IV",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical IV Ring in Use : Up",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical IV Ring in Use : Down",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB5",
-        "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_EVEN",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB5",
-        "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_ODD",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB5",
-        "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_EVEN",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB5",
-        "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_ODD",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Source Throttle",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xae",
-        "EventName": "UNC_CHA_RING_SRC_THRTL",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
         "PerPkg": "1",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x80",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe4",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED_1",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
         "PerPkg": "1",
-        "Unit": "CHA"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Counting disabled",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_IIO_NOTHING",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "PWT occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_IIO_PWT_OCCUPANCY",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Symbol Times on Link",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_IIO_SYMBOL_TIMES",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "P2P Requests",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_I_P2P_INSERTS",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "P2P Occupancy",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_I_P2P_OCCUPANCY",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress Allocations",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0B",
-        "EventName": "UNC_I_TxC_AK_INSERTS",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL DRS Egress Cycles Full",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x80",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL DRS Egress Inserts",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_I_TxC_BL_DRS_INSERTS",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL DRS Egress Occupancy",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x08",
-        "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL NCB Egress Cycles Full",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x06",
-        "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL NCB Egress Inserts",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_I_TxC_BL_NCB_INSERTS",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL NCB Egress Occupancy",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x09",
-        "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL NCS Egress Cycles Full",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x07",
-        "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL NCS Egress Inserts",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_I_TxC_BL_NCS_INSERTS",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL NCS Egress Occupancy",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0A",
-        "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x80",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1C",
-        "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No AD0 Egress Credits Stalls",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1A",
-        "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No AD1 Egress Credits Stalls",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1B",
-        "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No BL Egress Credit Stalls",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1D",
-        "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Outbound Read Requests",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0D",
-        "EventName": "UNC_I_TxS_DATA_INSERTS_NCB",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Outbound Read Requests",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0E",
-        "EventName": "UNC_I_TxS_DATA_INSERTS_NCS",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Outbound Request Queue Occupancy",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0C",
-        "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x80",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x60",
-        "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
+        "EventCode": "0xD1",
+        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Write Tracker Inserts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x64",
-        "EventName": "UNC_M2M_MIRR_WRQ_INSERTS",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
+        "EventCode": "0xD1",
+        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Write Tracker Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x65",
-        "EventName": "UNC_M2M_MIRR_WRQ_OCCUPANCY",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
+        "EventCode": "0xD1",
+        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x73",
-        "EventName": "UNC_M2M_PREFCAM_CIS_DROPS",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
+        "EventCode": "0xD3",
+        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x79",
-        "EventName": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
+        "EventCode": "0xD3",
+        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_M2M_PREFCAM_RxC_INSERTS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x78",
-        "EventName": "UNC_M2M_PREFCAM_RxC_INSERTS",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
+        "EventCode": "0xD3",
+        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x77",
-        "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
+        "EventCode": "0xD5",
+        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Source Throttle",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xae",
-        "EventName": "UNC_M2M_RING_SRC_THRTL",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
+        "EventCode": "0xD5",
+        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Ingress (from CMS) Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
+        "EventCode": "0xD5",
+        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Ingress (from CMS) Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_M2M_RxC_AD_CYCLES_NE",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
+        "EventCode": "0xD7",
+        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5C",
-        "EventName": "UNC_M2M_RxC_AK_WR_CMP",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
+        "EventCode": "0xD7",
+        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Ingress (from CMS) Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x08",
-        "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
+        "EventCode": "0xD7",
+        "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Ingress (from CMS) Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x07",
-        "EventName": "UNC_M2M_RxC_BL_CYCLES_NE",
+        "BriefDescription": "Failed ARB for AD : VN0 REQ Messages",
+        "EventCode": "0x30",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Failed ARB for AD : VN0 REQ Messages : AD arb but no win; arb request asserted but not won",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe4",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED_1",
+        "BriefDescription": "Failed ARB for AD : VN0 RSP Messages",
+        "EventCode": "0x30",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Failed ARB for AD : VN0 RSP Messages : AD arb but no win; arb request asserted but not won",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS",
+        "BriefDescription": "Failed ARB for AD : VN0 SNP Messages",
+        "EventCode": "0x30",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Failed ARB for AD : VN0 SNP Messages : AD arb but no win; arb request asserted but not won",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS",
+        "BriefDescription": "Failed ARB for AD : VN0 WB Messages",
+        "EventCode": "0x30",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Failed ARB for AD : VN0 WB Messages : AD arb but no win; arb request asserted but not won",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Retry - Mem Mirroring Mode",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_ACCEPTS",
+        "BriefDescription": "Failed ARB for AD : VN1 REQ Messages",
+        "EventCode": "0x30",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Failed ARB for AD : VN1 REQ Messages : AD arb but no win; arb request asserted but not won",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Retry - Mem Mirroring Mode",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_REJECTS",
+        "BriefDescription": "Failed ARB for AD : VN1 RSP Messages",
+        "EventCode": "0x30",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Failed ARB for AD : VN1 RSP Messages : AD arb but no win; arb request asserted but not won",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Scoreboard Accepts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2F",
-        "EventName": "UNC_M2M_SCOREBOARD_RD_ACCEPTS",
+        "BriefDescription": "Failed ARB for AD : VN1 SNP Messages",
+        "EventCode": "0x30",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Failed ARB for AD : VN1 SNP Messages : AD arb but no win; arb request asserted but not won",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Scoreboard Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Failed ARB for AD : VN1 WB Messages",
         "EventCode": "0x30",
-        "EventName": "UNC_M2M_SCOREBOARD_RD_REJECTS",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Failed ARB for AD : VN1 WB Messages : AD arb but no win; arb request asserted but not won",
+        "UMask": "0x80",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Scoreboard Accepts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x31",
-        "EventName": "UNC_M2M_SCOREBOARD_WR_ACCEPTS",
+        "BriefDescription": "AD FlowQ Bypass",
+        "EventCode": "0x2C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Scoreboard Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x32",
-        "EventName": "UNC_M2M_SCOREBOARD_WR_REJECTS",
+        "BriefDescription": "AD FlowQ Bypass",
+        "EventCode": "0x2C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Number AD Ingress Credits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_M2M_TGR_AD_CREDITS",
+        "BriefDescription": "AD FlowQ Bypass",
+        "EventCode": "0x2C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Number BL Ingress Credits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_M2M_TGR_BL_CREDITS",
+        "BriefDescription": "AD FlowQ Bypass",
+        "EventCode": "0x2C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Credit Acquired",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0d",
-        "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED",
+        "BriefDescription": "AD Flow Q Not Empty : VN0 REQ Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "AD Flow Q Not Empty : VN0 REQ Messages : Number of cycles the AD Egress queue is Not Empty",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Credits Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0e",
-        "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY",
+        "BriefDescription": "AD Flow Q Not Empty : VN0 RSP Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "AD Flow Q Not Empty : VN0 RSP Messages : Number of cycles the AD Egress queue is Not Empty",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0c",
-        "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL",
+        "BriefDescription": "AD Flow Q Not Empty : VN0 SNP Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "AD Flow Q Not Empty : VN0 SNP Messages : Number of cycles the AD Egress queue is Not Empty",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0b",
-        "EventName": "UNC_M2M_TxC_AD_CYCLES_NE",
+        "BriefDescription": "AD Flow Q Not Empty : VN0 WB Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "AD Flow Q Not Empty : VN0 WB Messages : Number of cycles the AD Egress queue is Not Empty",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles with No AD Egress (to CMS) Credits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0f",
-        "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES",
+        "BriefDescription": "AD Flow Q Not Empty : VN1 REQ Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "AD Flow Q Not Empty : VN1 REQ Messages : Number of cycles the AD Egress queue is Not Empty",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED",
+        "BriefDescription": "AD Flow Q Not Empty : VN1 RSP Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "AD Flow Q Not Empty : VN1 RSP Messages : Number of cycles the AD Egress queue is Not Empty",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AKC Credits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5F",
-        "EventName": "UNC_M2M_TxC_AKC_CREDITS",
+        "BriefDescription": "AD Flow Q Not Empty : VN1 SNP Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "AD Flow Q Not Empty : VN1 SNP Messages : Number of cycles the AD Egress queue is Not Empty",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Source Throttle",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xae",
-        "EventName": "UNC_M2P_RING_SRC_THRTL",
+        "BriefDescription": "AD Flow Q Not Empty : VN1 WB Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB",
         "PerPkg": "1",
-        "Unit": "M2PCIe"
+        "PublicDescription": "AD Flow Q Not Empty : VN1 WB Messages : Number of cycles the AD Egress queue is Not Empty",
+        "UMask": "0x80",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe4",
-        "EventName": "UNC_M2P_RxR_CRD_STARVED_1",
+        "BriefDescription": "AD Flow Q Inserts : VN0 REQ Messages",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ",
         "PerPkg": "1",
-        "Unit": "M2PCIe"
+        "PublicDescription": "AD Flow Q Inserts : VN0 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Clockticks",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_M3UPI_CMS_CLOCKTICKS",
+        "BriefDescription": "AD Flow Q Inserts : VN0 RSP Messages",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP",
         "PerPkg": "1",
+        "PublicDescription": "AD Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "D2C Sent",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M3UPI_D2C_SENT",
+        "BriefDescription": "AD Flow Q Inserts : VN0 SNP Messages",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP",
         "PerPkg": "1",
+        "PublicDescription": "AD Flow Q Inserts : VN0 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "D2U Sent",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M3UPI_D2U_SENT",
+        "BriefDescription": "AD Flow Q Inserts : VN0 WB Messages",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB",
         "PerPkg": "1",
+        "PublicDescription": "AD Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Source Throttle",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xae",
-        "EventName": "UNC_M3UPI_RING_SRC_THRTL",
+        "BriefDescription": "AD Flow Q Inserts : VN1 REQ Messages",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ",
         "PerPkg": "1",
+        "PublicDescription": "AD Flow Q Inserts : VN1 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe4",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED_1",
+        "BriefDescription": "AD Flow Q Inserts : VN1 RSP Messages",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP",
         "PerPkg": "1",
+        "PublicDescription": "AD Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Flow Q Inserts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2F",
-        "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS",
+        "BriefDescription": "AD Flow Q Inserts : VN1 SNP Messages",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP",
         "PerPkg": "1",
+        "PublicDescription": "AD Flow Q Inserts : VN1 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Flow Q Occupancy",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1E",
-        "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY",
+        "BriefDescription": "AD Flow Q Occupancy : VN0 REQ Messages",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ",
         "PerPkg": "1",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "FlowQ Generated Prefetch",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x29",
-        "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN",
+        "BriefDescription": "AD Flow Q Occupancy : VN0 RSP Messages",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP",
         "PerPkg": "1",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "IDI Lock/SplitLock Cycles",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_U_LOCK_CYCLES",
+        "BriefDescription": "AD Flow Q Occupancy : VN0 SNP Messages",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP",
         "PerPkg": "1",
-        "Unit": "UBOX"
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "RACU Request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_U_RACU_REQUESTS",
+        "BriefDescription": "AD Flow Q Occupancy : VN0 WB Messages",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB",
         "PerPkg": "1",
-        "Unit": "UBOX"
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x16",
-        "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
+        "BriefDescription": "AD Flow Q Occupancy : VN1 REQ Messages",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_UPI_PHY_INIT_CYCLES",
+        "BriefDescription": "AD Flow Q Occupancy : VN1 RSP Messages",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "L1 Req Nack",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_UPI_POWER_L1_NACK",
+        "BriefDescription": "AD Flow Q Occupancy : VN1 SNP Messages",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "L1 Req (same as L1 Ack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x22",
-        "EventName": "UNC_UPI_POWER_L1_REQ",
+        "BriefDescription": "AK Flow Q Inserts",
+        "EventCode": "0x2F",
+        "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles in L0p",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x25",
-        "EventName": "UNC_UPI_RxL0P_POWER_CYCLES",
+        "BriefDescription": "AK Flow Q Occupancy",
+        "EventCode": "0x1E",
+        "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles in L0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_UPI_RxL0_POWER_CYCLES",
+        "BriefDescription": "Failed ARB for BL : VN0 NCB Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Failed ARB for BL : VN0 NCB Messages : BL arb but no win; arb request asserted but not won",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CRC Errors Detected",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0B",
-        "EventName": "UNC_UPI_RxL_CRC_ERRORS",
+        "BriefDescription": "Failed ARB for BL : VN0 NCS Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Failed ARB for BL : VN0 NCS Messages : BL arb but no win; arb request asserted but not won",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "LLR Requests Sent",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x08",
-        "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT",
+        "BriefDescription": "Failed ARB for BL : VN0 RSP Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Failed ARB for BL : VN0 RSP Messages : BL arb but no win; arb request asserted but not won",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Credit Consumed",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x39",
-        "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0",
+        "BriefDescription": "Failed ARB for BL : VN0 WB Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Failed ARB for BL : VN0 WB Messages : BL arb but no win; arb request asserted but not won",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Credit Consumed",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x3A",
-        "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1",
+        "BriefDescription": "Failed ARB for BL : VN1 NCS Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Failed ARB for BL : VN1 NCS Messages : BL arb but no win; arb request asserted but not won",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VNA Credit Consumed",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA",
+        "BriefDescription": "Failed ARB for BL : VN1 NCB Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Failed ARB for BL : VN1 NCB Messages : BL arb but no win; arb request asserted but not won",
+        "UMask": "0x80",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x28",
-        "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
+        "BriefDescription": "Failed ARB for BL : VN1 RSP Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Failed ARB for BL : VN1 RSP Messages : BL arb but no win; arb request asserted but not won",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x29",
-        "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
+        "BriefDescription": "Failed ARB for BL : VN1 WB Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Failed ARB for BL : VN1 WB Messages : BL arb but no win; arb request asserted but not won",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles in L0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x26",
-        "EventName": "UNC_UPI_TxL0_POWER_CYCLES",
+        "BriefDescription": "BL Flow Q Not Empty : VN0 REQ Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "BL Flow Q Not Empty : VN0 REQ Messages : Number of cycles the BL Egress queue is Not Empty",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Tx Flit Buffer Bypassed",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_UPI_TxL_BYPASSED",
+        "BriefDescription": "BL Flow Q Not Empty : VN0 RSP Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "BL Flow Q Not Empty : VN0 RSP Messages : Number of cycles the BL Egress queue is Not Empty",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Tx Flit Buffer Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_UPI_TxL_INSERTS",
+        "BriefDescription": "BL Flow Q Not Empty : VN0 SNP Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "BL Flow Q Not Empty : VN0 SNP Messages : Number of cycles the BL Egress queue is Not Empty",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Tx Flit Buffer Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_UPI_TxL_OCCUPANCY",
+        "BriefDescription": "BL Flow Q Not Empty : VN0 WB Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "BL Flow Q Not Empty : VN0 WB Messages : Number of cycles the BL Egress queue is Not Empty",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
+        "BriefDescription": "BL Flow Q Not Empty : VN1 REQ Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "BL Flow Q Not Empty : VN1 REQ Messages : Number of cycles the BL Egress queue is Not Empty",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VNA Credits Pending Return - Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY",
+        "BriefDescription": "BL Flow Q Not Empty : VN1 RSP Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "BL Flow Q Not Empty : VN1 RSP Messages : Number of cycles the BL Egress queue is Not Empty",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache and Snoop Filter Lookups; Any Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.ALL",
+        "BriefDescription": "BL Flow Q Not Empty : VN1 SNP Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP",
         "PerPkg": "1",
-        "UMask": "0x1FFFFF",
-        "UMaskExt": "0x1FFF",
-        "Unit": "CHA"
+        "PublicDescription": "BL Flow Q Not Empty : VN1 SNP Messages : Number of cycles the BL Egress queue is Not Empty",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD",
+        "BriefDescription": "BL Flow Q Not Empty : VN1 WB Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB",
         "PerPkg": "1",
-        "UMask": "0x1bc1ff",
-        "UMaskExt": "0x1bc1",
-        "Unit": "CHA"
+        "PublicDescription": "BL Flow Q Not Empty : VN1 WB Messages : Number of cycles the BL Egress queue is Not Empty",
+        "UMask": "0x80",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache Lookups : Flush or Invalidate Requests",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV",
+        "BriefDescription": "BL Flow Q Inserts : VN0 RSP Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB",
         "PerPkg": "1",
-        "UMask": "0x1A44FF",
-        "UMaskExt": "0x1A44",
-        "Unit": "CHA"
+        "PublicDescription": "BL Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.CODE",
+        "BriefDescription": "BL Flow Q Inserts : VN0 WB Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS",
         "PerPkg": "1",
-        "UMask": "0x1bd0ff",
-        "UMaskExt": "0x1bd0",
-        "Unit": "CHA"
+        "PublicDescription": "BL Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOC_HOM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.LOCALLY_HOMED_ADDRESS",
+        "BriefDescription": "BL Flow Q Inserts : VN0 NCS Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x0bdfff",
-        "UMaskExt": "0x0bdf",
-        "Unit": "CHA"
+        "PublicDescription": "BL Flow Q Inserts : VN0 NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REM_HOM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.REMOTELY_HOMED_ADDRESS",
+        "BriefDescription": "BL Flow Q Inserts : VN0 NCB Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x15dfff",
-        "UMaskExt": "0x15df",
-        "Unit": "CHA"
+        "PublicDescription": "BL Flow Q Inserts : VN0 NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache Lookups : Flush or Invalidate requests that come from a Remote socket",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV_REMOTE",
+        "BriefDescription": "BL Flow Q Inserts : VN1 RSP Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB",
         "PerPkg": "1",
-        "UMask": "0x1A04FF",
-        "UMaskExt": "0x1A04",
-        "Unit": "CHA"
+        "PublicDescription": "BL Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Requests that come from a Remote socket",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_REMOTE",
+        "BriefDescription": "BL Flow Q Inserts : VN1 WB Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS",
         "PerPkg": "1",
-        "UMask": "0x1A01FF",
-        "UMaskExt": "0x1A01",
-        "Unit": "CHA"
+        "PublicDescription": "BL Flow Q Inserts : VN1 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache Lookups : RFO Requests that come from a Remote socket",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.RFO_REMOTE",
+        "BriefDescription": "BL Flow Q Inserts : VN1_NCB Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP",
         "PerPkg": "1",
-        "UMask": "0x1A08FF",
-        "UMaskExt": "0x1A08",
-        "Unit": "CHA"
+        "PublicDescription": "BL Flow Q Inserts : VN1_NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x80",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.CODE_REMOTE",
+        "BriefDescription": "BL Flow Q Inserts : VN1_NCS Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB",
         "PerPkg": "1",
-        "UMask": "0x1a10ff",
-        "UMaskExt": "0x1a10",
-        "Unit": "CHA"
+        "PublicDescription": "BL Flow Q Inserts : VN1_NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache and Snoop Filter Lookups; Snoop Requests from a Remote Socket",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP",
+        "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB",
         "PerPkg": "1",
-        "UMask": "0x1C19FF",
-        "UMaskExt": "0x1C19",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache Lookups : Flush or Invalidate Requests that come from the local socket (usually the core)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV_LOCAL",
+        "BriefDescription": "BL Flow Q Occupancy : VN0 NCS Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS",
         "PerPkg": "1",
-        "UMask": "0x1844FF",
-        "UMaskExt": "0x1844",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request that come from the local socket (usually the core)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL",
+        "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x19C1FF",
-        "UMaskExt": "0x19C1",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache Lookups : RFO Requests that come from the local socket (usually the core)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.RFO_LOCAL",
+        "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x19C8FF",
-        "UMaskExt": "0x19C8",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.CODE_LOCAL",
+        "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB",
         "PerPkg": "1",
-        "UMask": "0x19d0ff",
-        "UMaskExt": "0x19d0",
-        "Unit": "CHA"
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.LLC_PF_LOCAL",
+        "BriefDescription": "BL Flow Q Occupancy : VN1_NCB Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS",
         "PerPkg": "1",
-        "UMask": "0x189dff",
-        "UMaskExt": "0x189d",
-        "Unit": "CHA"
+        "UMask": "0x80",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT",
+        "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP",
         "PerPkg": "1",
-        "UMask": "0xC827FD01",
-        "UMaskExt": "0xC827FD",
-        "Unit": "CHA"
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF",
+        "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB",
         "PerPkg": "1",
-        "UMask": "0xC8A7FD01",
-        "UMaskExt": "0xC8A7FD",
-        "Unit": "CHA"
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT",
+        "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages",
+        "EventCode": "0x1F",
+        "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_LOCAL",
         "PerPkg": "1",
-        "UMask": "0xC827FE01",
-        "UMaskExt": "0xC827FE",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF",
+        "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages",
+        "EventCode": "0x1F",
+        "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_THROUGH",
         "PerPkg": "1",
-        "UMask": "0xC8A7FE01",
-        "UMaskExt": "0xC8A7FE",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF",
+        "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages",
+        "EventCode": "0x1F",
+        "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_WRPULL",
         "PerPkg": "1",
-        "UMask": "0xC88FFD01",
-        "UMaskExt": "0xC88FFD",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF",
+        "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages",
+        "EventCode": "0x1F",
+        "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_LOCAL",
         "PerPkg": "1",
-        "UMask": "0xC897FD01",
-        "UMaskExt": "0xC897FD",
-        "Unit": "CHA"
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT",
+        "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages",
+        "EventCode": "0x1F",
+        "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_THROUGH",
         "PerPkg": "1",
-        "UMask": "0xC827FD01",
-        "UMaskExt": "0xC827FD",
-        "Unit": "CHA"
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF",
+        "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages",
+        "EventCode": "0x1F",
+        "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_WRPULL",
         "PerPkg": "1",
-        "UMask": "0xC8A7FD01",
-        "UMaskExt": "0xC8A7FD",
-        "Unit": "CHA"
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF",
+        "BriefDescription": "CMS Horizontal ADS Used : AD - All",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0xC887FD01",
-        "UMaskExt": "0xC887FD",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x11",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF",
+        "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0xC88FFE01",
-        "UMaskExt": "0xC88FFE",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF",
+        "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0xC897FE01",
-        "UMaskExt": "0xC897FE",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT",
+        "BriefDescription": "CMS Horizontal ADS Used : BL - All",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0xC827FE01",
-        "UMaskExt": "0xC827FE",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x44",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF",
+        "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0xC8A7FE01",
-        "UMaskExt": "0xC8A7FE",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF",
+        "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0xC887FE01",
-        "UMaskExt": "0xC887FE",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO",
+        "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0xC803FD04",
-        "UMaskExt": "0xC803FD",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x11",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM",
+        "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0xCC43FD04",
-        "UMaskExt": "0xCC43FD",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO",
+        "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0xC803FD04",
-        "UMaskExt": "0xC803FD",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : RFOs issued by IO Devices",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO",
+        "BriefDescription": "CMS Horizontal Bypass Used : AK",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK",
         "PerPkg": "1",
-        "UMask": "0xC803FF04",
-        "UMaskExt": "0xC803FF",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : DRds issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD",
+        "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0xC817FF01",
-        "UMaskExt": "0xC817FF",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x80",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT",
+        "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0xC827FF01",
-        "UMaskExt": "0xC827FF",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x44",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF",
+        "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0xC8A7FF01",
-        "UMaskExt": "0xC8A7FF",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts; CRd Pref from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF",
+        "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0xC88FFF01",
-        "UMaskExt": "0xC88FFF",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO",
+        "BriefDescription": "CMS Horizontal Bypass Used : IV",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV",
         "PerPkg": "1",
-        "UMask": "0xC803FF04",
-        "UMaskExt": "0xC803FF",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0xCC43FF04",
-        "UMaskExt": "0xCC43FF",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x11",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0xC887FF01",
-        "UMaskExt": "0xC887FF",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0xCCC7FF01",
-        "UMaskExt": "0xCCC7FF",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK",
         "PerPkg": "1",
-        "UMask": "0xC827FF01",
-        "UMaskExt": "0xC827FF",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0xC8A7FF01",
-        "UMaskExt": "0xC8A7FF",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy; CRd Pref from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0xC88FFF01",
-        "UMaskExt": "0xC88FFF",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0xC897FF01",
-        "UMaskExt": "0xC897FF",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0xC896FE01",
-        "UMaskExt": "0xC896FE",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV",
         "PerPkg": "1",
-        "UMask": "0xC8977E01",
-        "UMaskExt": "0xC8977E",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0xC806FE01",
-        "UMaskExt": "0xC806FE",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x11",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0xC8077E01",
-        "UMaskExt": "0xC8077E",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0xC886FE01",
-        "UMaskExt": "0xC886FE",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK",
         "PerPkg": "1",
-        "UMask": "0xC8877E01",
-        "UMaskExt": "0xC8877E",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : CLFlushOpts issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0xC8D7FF01",
-        "UMaskExt": "0xC8D7FF",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0xCC47FF01",
-        "UMaskExt": "0xCC47FF",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0xCC23FF04",
-        "UMaskExt": "0xCC23FF",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0xC8C3FF04",
-        "UMaskExt": "0xC8C3FF",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV",
         "PerPkg": "1",
-        "UMask": "0xcc27ff01",
-        "UMaskExt": "0xcc27ff",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_PMM",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0xC8978A01",
-        "UMaskExt": "0xC8978A",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x11",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_PMM",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0xC8968A01",
-        "UMaskExt": "0xC8968A",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_PMM",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0xC8970A01",
-        "UMaskExt": "0xC8970A",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_PMM",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AK",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK",
         "PerPkg": "1",
-        "UMask": "0xc8678a01",
-        "UMaskExt": "0xc8678a",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_PMM",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0xc8668a01",
-        "UMaskExt": "0xc8668a",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_PMM",
+        "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0xc8670a01",
-        "UMaskExt": "0xc8670a",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_DRAM",
+        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0xC8678601",
-        "UMaskExt": "0xC86786",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_DRAM",
+        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0xC8668601",
-        "UMaskExt": "0xC86686",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts; WCiL misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_PMM",
+        "BriefDescription": "CMS Horizontal Egress Inserts : IV",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV",
         "PerPkg": "1",
-        "UMask": "0xc86f8a01",
-        "UMaskExt": "0xc86f8a",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts; WCiL misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0xc86e8a01",
-        "UMaskExt": "0xc86e8a",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+        "UMask": "0x11",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts; WCiL misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0xc86f0a01",
-        "UMaskExt": "0xc86f0a",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_DRAM",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0xC86F8601",
-        "UMaskExt": "0xC86F86",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DRAM",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AK",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK",
         "PerPkg": "1",
-        "UMask": "0xC86E8601",
-        "UMaskExt": "0xC86E86",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0xC8168A01",
-        "UMaskExt": "0xC8168A",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x80",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM",
+        "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0xC8170A01",
-        "UMaskExt": "0xC8170A",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+        "UMask": "0x44",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_PMM",
+        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0xC8978A01",
-        "UMaskExt": "0xC8978A",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_PMM",
+        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0xC8968A01",
-        "UMaskExt": "0xC8968A",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_PMM",
+        "BriefDescription": "CMS Horizontal Egress NACKs : IV",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV",
         "PerPkg": "1",
-        "UMask": "0xC8970A01",
-        "UMaskExt": "0xC8970A",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0xc867fe01",
-        "UMaskExt": "0xc867fe",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x11",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_PMM",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0xc8678a01",
-        "UMaskExt": "0xc8678a",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_LOCAL_PMM",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0xc8668a01",
-        "UMaskExt": "0xc8668a",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_REMOTE_PMM",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK",
         "PerPkg": "1",
-        "UMask": "0xc8670a01",
-        "UMaskExt": "0xc8670a",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0xc86ffe01",
-        "UMaskExt": "0xc86ffe",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
+        "Unit": "M3UPI"
     },
-    {
-        "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_PMM",
+    {
+        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0xc86f8a01",
-        "UMaskExt": "0xc86f8a",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0xc86e8a01",
-        "UMaskExt": "0xc86e8a",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0xc86f0a01",
-        "UMaskExt": "0xc86f0a",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "1",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "2",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_ALL",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "3",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_UNCRD",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "4",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "5",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AKC_UNCRD",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x80",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "6",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_ALL",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "7",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_UNCRD",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "8",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "9",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART0_FREERUN",
+        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "13",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART4_FREERUN",
+        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "12",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART3_FREERUN",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "11",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART2_FREERUN",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "10",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART1_FREERUN",
+        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "15",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART6_FREERUN",
+        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "14",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART5_FREERUN",
+        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "16",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART7_FREERUN",
+        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0xC86FFE01",
-        "UMaskExt": "0xC86FFE",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCB",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCS",
+        "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV_AG1",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Inserts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCB",
+        "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Inserts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCS",
+        "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_M2P_TxC_CREDITS.PMM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M2P_TxC_CREDITS.PMM",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
+        "EventCode": "0x94",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x25",
-        "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_1",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
+        "EventCode": "0x94",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x25",
-        "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_0",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
+        "EventCode": "0x94",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M2PCIe"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_1",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
+        "EventCode": "0x94",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_0",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
+        "EventCode": "0x94",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M2PCIe"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Distress signal asserted : PMM Local",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_M2P_DISTRESS_ASSERTED.PMM_LOCAL",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
+        "EventCode": "0x94",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Distress signal asserted : PMM Remote",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_M2P_DISTRESS_ASSERTED.PMM_NONLOCAL",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
+        "EventCode": "0x94",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache Lookups : RFO Request Filter",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.RFO_F",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
+        "EventCode": "0x95",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG0",
         "PerPkg": "1",
-        "UMaskExt": "0x08",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache Lookups : Transactions homed locally Filter",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
+        "EventCode": "0x95",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG1",
         "PerPkg": "1",
-        "UMaskExt": "0x800",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache Lookups : Transactions homed remotely Filter",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_F",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
+        "EventCode": "0x96",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG0",
         "PerPkg": "1",
-        "UMaskExt": "0x1000",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache Lookups : Remote snoop request Filter",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP_F",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
+        "EventCode": "0x96",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG1",
         "PerPkg": "1",
-        "UMaskExt": "0x400",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache Lookups : All Request Filter",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.ANY_F",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
+        "EventCode": "0x96",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG0",
         "PerPkg": "1",
-        "UMaskExt": "0x20",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache Lookups : Data Read Request Filter",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
+        "EventCode": "0x96",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG1",
         "PerPkg": "1",
-        "UMaskExt": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache Lookups : Write Request Filter",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
+        "EventCode": "0x96",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG0",
         "PerPkg": "1",
-        "UMaskExt": "0x02",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache Lookups : Flush or Invalidate Filter",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
+        "EventCode": "0x96",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG1",
         "PerPkg": "1",
-        "UMaskExt": "0x04",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache Lookups : CRd Request Filter",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
+        "EventCode": "0x96",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.IV_AG0",
         "PerPkg": "1",
-        "UMaskExt": "0x10",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache Lookups : Local request Filter",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
+        "EventCode": "0x97",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG0",
         "PerPkg": "1",
-        "UMaskExt": "0x40",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache Lookups : Local LLC prefetch requests (from LLC) Filter",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL_F",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
+        "EventCode": "0x97",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG1",
         "PerPkg": "1",
-        "UMaskExt": "0x80",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache Lookups : Remote non-snoop request Filter",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.PREF_OR_DMND_REMOTE_F",
+        "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG0",
         "PerPkg": "1",
-        "UMaskExt": "0x200",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache Lookups : All Misses",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL",
+        "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x1fe001",
-        "UMaskExt": "0x1fe0",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL",
+        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x1fc1ff",
-        "UMaskExt": "0x1fc1",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache Lookups : Data Read Misses",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS",
+        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x1bc101",
-        "UMaskExt": "0x1bc1",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.DMND_READ_LOCAL",
+        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x841ff",
-        "UMaskExt": "0x841",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL",
+        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x842ff",
-        "UMaskExt": "0x842",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.RFO_LOCAL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.RFO_PREF_LOCAL",
+        "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x888ff",
-        "UMaskExt": "0x888",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_REMOTE",
+        "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
+        "EventCode": "0x93",
+        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x17c2ff",
-        "UMaskExt": "0x17c2",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cache Lookups : All transactions from Remote Agents",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.ALL_REMOTE",
+        "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
+        "EventCode": "0x93",
+        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x1e20ff",
-        "UMaskExt": "0x1e20",
-        "Unit": "CHA"
+        "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Distress signal asserted : PMM Local",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_LOCAL",
+        "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Distress signal asserted : PMM Remote",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_NONLOCAL",
+        "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO1_NCB",
+        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2 BL Credits Empty : IIO5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.UBOX_NCB",
+        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_M2M_DISTRESS_PMM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xF2",
-        "EventName": "UNC_M2M_DISTRESS_PMM",
+        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG0",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_M2M_DISTRESS_PMM_MEMMODE",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xF1",
-        "EventName": "UNC_M2M_DISTRESS_PMM_MEMMODE",
+        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG1",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.ISOCH",
+        "BriefDescription": "CMS Vertical Egress NACKs : IV",
+        "EventCode": "0x98",
+        "EventName": "UNC_M3UPI_TxR_VERT_NACK0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x0702",
-        "UMaskExt": "0x07",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : From TGR - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.FROM_TGR",
+        "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
+        "EventCode": "0x99",
+        "EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x0740",
-        "UMaskExt": "0x07",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH",
+        "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
+        "EventCode": "0x99",
+        "EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x1C04",
-        "UMaskExt": "0x1C",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH",
+        "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x1C08",
-        "UMaskExt": "0x1C",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : DDR - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_MEM",
+        "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x1C20",
-        "UMaskExt": "0x1C",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_CACHE",
+        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x1C40",
-        "UMaskExt": "0x1C",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : From TGR - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR",
+        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG1",
         "PerPkg": "1",
-        "UMaskExt": "0x1D",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.NI_MISS",
+        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG0",
         "PerPkg": "1",
-        "UMaskExt": "0x1C",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Prefetch CAM Cycles Full : All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6B",
-        "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.ALLCH",
+        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x07",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Prefetch CAM Cycles Not Empty : All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6C",
-        "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.ALLCH",
+        "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x07",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped : XPT - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6f",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH",
+        "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
+        "EventCode": "0x91",
+        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x15",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped : UPI - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6f",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.UPI_ALLCH",
+        "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
+        "EventCode": "0x91",
+        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x2a",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Prefetch CAM Occupancy : All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6A",
-        "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x07",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": ": All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x76",
-        "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x07",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : PMM - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.CH0_TO_PMM",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x0120",
-        "UMaskExt": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : DDR - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x0108",
-        "UMaskExt": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x0110",
-        "UMaskExt": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : PMM - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.CH1_TO_PMM",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x0220",
-        "UMaskExt": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : DDR - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x0208",
-        "UMaskExt": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x0210",
-        "UMaskExt": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : DDR - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_MEM",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x0708",
-        "UMaskExt": "0x07",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_CACHE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.TGC",
         "PerPkg": "1",
-        "UMask": "0x0710",
-        "UMaskExt": "0x07",
-        "Unit": "M2M"
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : PMM - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_PMM",
+        "BriefDescription": "UPI0 AD Credits Empty : VN0 REQ Messages",
+        "EventCode": "0x20",
+        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ",
         "PerPkg": "1",
-        "UMask": "0x0480",
-        "UMaskExt": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "UPI0 AD Credits Empty : VN0 REQ Messages : No credits available to send to UPIs on the AD Ring",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : DDR - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM",
+        "BriefDescription": "UPI0 AD Credits Empty : VN0 RSP Messages",
+        "EventCode": "0x20",
+        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x0420",
-        "UMaskExt": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "UPI0 AD Credits Empty : VN0 RSP Messages : No credits available to send to UPIs on the AD Ring",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_CACHE",
+        "BriefDescription": "UPI0 AD Credits Empty : VN0 SNP Messages",
+        "EventCode": "0x20",
+        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP",
         "PerPkg": "1",
-        "UMask": "0x0440",
-        "UMaskExt": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "UPI0 AD Credits Empty : VN0 SNP Messages : No credits available to send to UPIs on the AD Ring",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : PMM - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_PMM",
+        "BriefDescription": "UPI0 AD Credits Empty : VN1 REQ Messages",
+        "EventCode": "0x20",
+        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ",
         "PerPkg": "1",
-        "UMask": "0x0880",
-        "UMaskExt": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "UPI0 AD Credits Empty : VN1 REQ Messages : No credits available to send to UPIs on the AD Ring",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : DDR - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_MEM",
+        "BriefDescription": "UPI0 AD Credits Empty : VN1 RSP Messages",
+        "EventCode": "0x20",
+        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP",
         "PerPkg": "1",
-        "UMask": "0x0820",
-        "UMaskExt": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "UPI0 AD Credits Empty : VN1 RSP Messages : No credits available to send to UPIs on the AD Ring",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_CACHE",
+        "BriefDescription": "UPI0 AD Credits Empty : VN1 SNP Messages",
+        "EventCode": "0x20",
+        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP",
         "PerPkg": "1",
-        "UMask": "0x0840",
-        "UMaskExt": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "UPI0 AD Credits Empty : VN1 SNP Messages : No credits available to send to UPIs on the AD Ring",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN0",
+        "BriefDescription": "UPI0 AD Credits Empty : VNA",
+        "EventCode": "0x20",
+        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "UPI0 AD Credits Empty : VNA : No credits available to send to UPIs on the AD Ring",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN1",
+        "BriefDescription": "UPI0 BL Credits Empty : VN0 RSP Messages",
+        "EventCode": "0x21",
+        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "UPI0 BL Credits Empty : VN0 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN2",
+        "BriefDescription": "UPI0 BL Credits Empty : VN0 REQ Messages",
+        "EventCode": "0x21",
+        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "UPI0 BL Credits Empty : VN0 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x51",
-        "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN0",
+        "BriefDescription": "UPI0 BL Credits Empty : VN0 SNP Messages",
+        "EventCode": "0x21",
+        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "UPI0 BL Credits Empty : VN0 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x51",
-        "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN1",
+        "BriefDescription": "UPI0 BL Credits Empty : VN1 RSP Messages",
+        "EventCode": "0x21",
+        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "UPI0 BL Credits Empty : VN1 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x51",
-        "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN2",
+        "BriefDescription": "UPI0 BL Credits Empty : VN1 REQ Messages",
+        "EventCode": "0x21",
+        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "UPI0 BL Credits Empty : VN1 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7A",
-        "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT",
+        "BriefDescription": "UPI0 BL Credits Empty : VN1 SNP Messages",
+        "EventCode": "0x21",
+        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB",
+        "PerPkg": "1",
+        "PublicDescription": "UPI0 BL Credits Empty : VN1 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "UPI0 BL Credits Empty : VNA",
+        "EventCode": "0x21",
+        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "UPI0 BL Credits Empty : VNA : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Distress signal asserted : PMM Local",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_LOCAL",
+        "BriefDescription": "FlowQ Generated Prefetch",
+        "EventCode": "0x29",
+        "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "FlowQ Generated Prefetch : Count cases where FlowQ causes spawn of Prefetch to iMC/SMI3 target",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Distress signal asserted : PMM Remote",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_NONLOCAL",
+        "BriefDescription": "Vertical AD Ring In Use : Down and Even",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6d",
-        "EventName": "UNC_M2M_PREFCAM_INSERTS.UPI_ALLCH",
+        "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x2a",
-        "Unit": "M2M"
+        "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH",
+        "BriefDescription": "Vertical AD Ring In Use : Up and Even",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x15",
-        "Unit": "M2M"
+        "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": ": PWC Hit to a 4K page",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_IOMMU1.PWC_4K_HITS",
+        "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": ": PWC Hit to a 2M page",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS",
+        "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": ": PWC Hit to a 1G page",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS",
+        "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": ": PWT Hit to a 256T page",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS",
+        "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": ": PageWalk cache fill",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS",
+        "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": ": Global IOTLB invalidation cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_GBL",
+        "BriefDescription": "Vertical AK Ring In Use : Down and Even",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": ": Domain-selective IOTLB invalidation cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_DOMAIN",
+        "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": ": Page-selective IOTLB invalidation cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PAGE",
+        "BriefDescription": "Vertical AK Ring In Use : Up and Even",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": ": Context cache global invalidation cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_GBL",
+        "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": ": Domain-selective Context cache invalidation cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DOMAIN",
+        "BriefDescription": "Vertical BL Ring in Use : Down and Even",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": ": Device-selective Context cache invalidation cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DEVICE",
+        "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Num requests sent by PCIe - by target : MsgB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB",
-        "FCMask": "0x07",
+        "BriefDescription": "Vertical BL Ring in Use : Up and Even",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Num requests sent by PCIe - by target : Multi-cast",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST",
-        "FCMask": "0x07",
+        "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Num requests sent by PCIe - by target : Ubox",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX",
-        "FCMask": "0x07",
+        "BriefDescription": "Vertical IV Ring in Use : Down",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Num requests sent by PCIe - by target : Memory",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM",
-        "FCMask": "0x07",
+        "BriefDescription": "Vertical IV Ring in Use : Up",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Num requests sent by PCIe - by target : Remote P2P",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P",
-        "FCMask": "0x07",
+        "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
+        "EventCode": "0xB5",
+        "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Num requests sent by PCIe - by target : Local P2P",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P",
-        "FCMask": "0x07",
+        "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
+        "EventCode": "0xB5",
+        "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Num requests sent by PCIe - by target : Confined P2P",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P",
-        "FCMask": "0x07",
+        "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
+        "EventCode": "0xB5",
+        "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Num requests sent by PCIe - by target : Abort",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT",
-        "FCMask": "0x07",
+        "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
+        "EventCode": "0xB5",
+        "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "ITC address map 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8F",
-        "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU",
+        "BriefDescription": "VN0 Credit Used : WB on BL",
+        "EventCode": "0x5B",
+        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "VN0 Credit Used : WB on BL : Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": ": Issuing to IOMMU",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ",
-        "FCMask": "0x07",
+        "BriefDescription": "VN0 Credit Used : NCB on BL",
+        "EventCode": "0x5B",
+        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "VN0 Credit Used : NCB on BL : Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": ": Processing response from IOMMU",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT",
-        "FCMask": "0x07",
+        "BriefDescription": "VN0 Credit Used : REQ on AD",
+        "EventCode": "0x5B",
+        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "VN0 Credit Used : REQ on AD : Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": ": Request Ownership",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN",
-        "FCMask": "0x07",
+        "BriefDescription": "VN0 Credit Used : RSP on AD",
+        "EventCode": "0x5B",
+        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP",
+        "PerPkg": "1",
+        "PublicDescription": "VN0 Credit Used : RSP on AD : Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "VN0 Credit Used : SNP on AD",
+        "EventCode": "0x5B",
+        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "VN0 Credit Used : SNP on AD : Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": ": Issuing final read or write of line",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR",
-        "FCMask": "0x07",
+        "BriefDescription": "VN0 Credit Used : RSP on BL",
+        "EventCode": "0x5B",
+        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "VN0 Credit Used : RSP on BL : Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": ": Writing line",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR",
-        "FCMask": "0x07",
+        "BriefDescription": "VN0 No Credits : WB on BL",
+        "EventCode": "0x5D",
+        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB",
         "PerPkg": "1",
-        "PortMask": "0xFF",
+        "PublicDescription": "VN0 No Credits : WB on BL : Number of Cycles there were no VN0 Credits : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
         "UMask": "0x10",
-        "Unit": "IIO"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": ": Passing data to be written",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA",
-        "FCMask": "0x07",
+        "BriefDescription": "VN0 No Credits : NCB on BL",
+        "EventCode": "0x5D",
+        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS",
         "PerPkg": "1",
-        "PortMask": "0xFF",
+        "PublicDescription": "VN0 No Credits : NCB on BL : Number of Cycles there were no VN0 Credits : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x20",
-        "Unit": "IIO"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Occupancy of outbound request queue : To device",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC5",
-        "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO",
-        "FCMask": "0x07",
+        "BriefDescription": "VN0 No Credits : REQ on AD",
+        "EventCode": "0x5D",
+        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "VN0 No Credits : REQ on AD : Number of Cycles there were no VN0 Credits : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "PCIe Request - cacheline complete : Request Ownership",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x91",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN",
-        "FCMask": "0x07",
+        "BriefDescription": "VN0 No Credits : RSP on AD",
+        "EventCode": "0x5D",
+        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "VN0 No Credits : RSP on AD : Number of Cycles there were no VN0 Credits : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "PCIe Request - cacheline complete : Issuing final read or write of line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x91",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR",
-        "FCMask": "0x07",
+        "BriefDescription": "VN0 No Credits : SNP on AD",
+        "EventCode": "0x5D",
+        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "VN0 No Credits : SNP on AD : Number of Cycles there were no VN0 Credits : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "PCIe Request - cacheline complete : Writing line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x91",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR",
-        "FCMask": "0x07",
+        "BriefDescription": "VN0 No Credits : RSP on BL",
+        "EventCode": "0x5D",
+        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB",
         "PerPkg": "1",
-        "PortMask": "0xFF",
+        "PublicDescription": "VN0 No Credits : RSP on BL : Number of Cycles there were no VN0 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "VN1 Credit Used : WB on BL",
+        "EventCode": "0x5C",
+        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB",
+        "PerPkg": "1",
+        "PublicDescription": "VN1 Credit Used : WB on BL : Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
         "UMask": "0x10",
-        "Unit": "IIO"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "PCIe Request - cacheline complete : Passing data to be written",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x91",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA",
-        "FCMask": "0x07",
+        "BriefDescription": "VN1 Credit Used : NCB on BL",
+        "EventCode": "0x5C",
+        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS",
         "PerPkg": "1",
-        "PortMask": "0xFF",
+        "PublicDescription": "VN1 Credit Used : NCB on BL : Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x20",
-        "Unit": "IIO"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "PCIe Request complete : Issuing to IOMMU",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ",
-        "FCMask": "0x07",
+        "BriefDescription": "VN1 Credit Used : REQ on AD",
+        "EventCode": "0x5C",
+        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "VN1 Credit Used : REQ on AD : Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "PCIe Request complete : Processing response from IOMMU",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT",
-        "FCMask": "0x07",
+        "BriefDescription": "VN1 Credit Used : RSP on AD",
+        "EventCode": "0x5C",
+        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "VN1 Credit Used : RSP on AD : Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "PCIe Request complete : Request Ownership",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN",
-        "FCMask": "0x07",
+        "BriefDescription": "VN1 Credit Used : SNP on AD",
+        "EventCode": "0x5C",
+        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "VN1 Credit Used : SNP on AD : Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "PCIe Request complete : Issuing final read or write of line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR",
-        "FCMask": "0x07",
+        "BriefDescription": "VN1 Credit Used : RSP on BL",
+        "EventCode": "0x5C",
+        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "VN1 Credit Used : RSP on BL : Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "PCIe Request complete : Writing line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.WR",
-        "FCMask": "0x07",
+        "BriefDescription": "VN1 No Credits : WB on BL",
+        "EventCode": "0x5E",
+        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB",
         "PerPkg": "1",
-        "PortMask": "0xFF",
+        "PublicDescription": "VN1 No Credits : WB on BL : Number of Cycles there were no VN1 Credits : Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
         "UMask": "0x10",
-        "Unit": "IIO"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "PCIe Request complete : Passing data to be written",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.DATA",
-        "FCMask": "0x07",
+        "BriefDescription": "VN1 No Credits : NCB on BL",
+        "EventCode": "0x5E",
+        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS",
         "PerPkg": "1",
-        "PortMask": "0xFF",
+        "PublicDescription": "VN1 No Credits : NCB on BL : Number of Cycles there were no VN1 Credits : Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x20",
-        "Unit": "IIO"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "PCIe Request - pass complete : Request Ownership",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN",
-        "FCMask": "0x07",
+        "BriefDescription": "VN1 No Credits : REQ on AD",
+        "EventCode": "0x5E",
+        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "VN1 No Credits : REQ on AD : Number of Cycles there were no VN1 Credits : Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "PCIe Request - pass complete : Issuing final read or write of line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR",
-        "FCMask": "0x07",
+        "BriefDescription": "VN1 No Credits : RSP on AD",
+        "EventCode": "0x5E",
+        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "VN1 No Credits : RSP on AD : Number of Cycles there were no VN1 Credits : Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "PCIe Request - pass complete : Writing line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR",
-        "FCMask": "0x07",
+        "BriefDescription": "VN1 No Credits : SNP on AD",
+        "EventCode": "0x5E",
+        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "VN1 No Credits : SNP on AD : Number of Cycles there were no VN1 Credits : Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "PCIe Request - pass complete : Passing data to be written",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA",
-        "FCMask": "0x07",
+        "BriefDescription": "VN1 No Credits : RSP on BL",
+        "EventCode": "0x5E",
+        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "VN1 No Credits : RSP on BL : Number of Cycles there were no VN1 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Incoming arbitration requests : Issuing to IOMMU",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ",
-        "FCMask": "0x07",
+        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0",
+        "EventCode": "0x7E",
+        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "UMask": "0x82",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Incoming arbitration requests : Processing response from IOMMU",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT",
-        "FCMask": "0x07",
+        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1",
+        "EventCode": "0x7E",
+        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "UMask": "0xa0",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Incoming arbitration requests : Request Ownership",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN",
-        "FCMask": "0x07",
+        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0",
+        "EventCode": "0x7E",
+        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "UMask": "0x81",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Incoming arbitration requests : Issuing final read or write of line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR",
-        "FCMask": "0x07",
+        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1",
+        "EventCode": "0x7E",
+        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "UMask": "0x90",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0",
+        "EventCode": "0x7E",
+        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0",
+        "PerPkg": "1",
+        "UMask": "0x84",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1",
+        "EventCode": "0x7E",
+        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1",
+        "PerPkg": "1",
+        "UMask": "0xc0",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Incoming arbitration requests : Writing line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR",
-        "FCMask": "0x07",
+        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0",
+        "EventCode": "0x7E",
+        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Incoming arbitration requests : Passing data to be written",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA",
-        "FCMask": "0x07",
+        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1",
+        "EventCode": "0x7E",
+        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1",
         "PerPkg": "1",
-        "PortMask": "0xFF",
         "UMask": "0x20",
-        "Unit": "IIO"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Incoming arbitration requests granted : Issuing to IOMMU",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ",
-        "FCMask": "0x07",
+        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0",
+        "EventCode": "0x7E",
+        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Incoming arbitration requests granted : Processing response from IOMMU",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT",
-        "FCMask": "0x07",
+        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1",
+        "EventCode": "0x7E",
+        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Incoming arbitration requests granted : Request Ownership",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN",
-        "FCMask": "0x07",
+        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0",
+        "EventCode": "0x7E",
+        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Incoming arbitration requests granted : Issuing final read or write of line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR",
-        "FCMask": "0x07",
+        "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1",
+        "EventCode": "0x7E",
+        "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Incoming arbitration requests granted : Writing line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_IIO_INBOUND_ARB_WON.WR",
-        "FCMask": "0x07",
+        "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0",
+        "EventCode": "0x7D",
+        "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1",
+        "EventCode": "0x7D",
+        "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1",
         "PerPkg": "1",
-        "PortMask": "0xFF",
         "UMask": "0x10",
-        "Unit": "IIO"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Incoming arbitration requests granted : Passing data to be written",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA",
-        "FCMask": "0x07",
+        "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0",
+        "EventCode": "0x7D",
+        "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Outbound cacheline requests issued : 64B requests issued to device",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO",
-        "FCMask": "0x07",
+        "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1",
+        "EventCode": "0x7D",
+        "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Outbound TLP (transaction layer packet) requests issued : To device",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD1",
-        "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO",
-        "FCMask": "0x07",
+        "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0",
+        "EventCode": "0x7D",
+        "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Number requests sent to PCIe from main die : From IRP",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.IRP",
-        "FCMask": "0x07",
+        "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1",
+        "EventCode": "0x7D",
+        "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Number requests sent to PCIe from main die : From ITC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.ITC",
-        "FCMask": "0x07",
+        "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0",
+        "EventCode": "0x7D",
+        "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Number requests sent to PCIe from main die : Completion allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.PREALLOC",
-        "FCMask": "0x07",
+        "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1",
+        "EventCode": "0x7D",
+        "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "UMask": "0x80",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF",
+        "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARB",
+        "EventCode": "0x61",
+        "EventName": "UNC_M3UPI_XPT_PFTCH.ARB",
         "PerPkg": "1",
-        "UMask": "0xC867FF01",
-        "UMaskExt": "0xC867FF",
-        "Unit": "CHA"
+        "PublicDescription": ": xpt prefetch message is making arbitration request",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL",
+        "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARRIVED",
+        "EventCode": "0x61",
+        "EventName": "UNC_M3UPI_XPT_PFTCH.ARRIVED",
         "PerPkg": "1",
-        "UMask": "0xC86FFF01",
-        "UMaskExt": "0xC86FFF",
-        "Unit": "CHA"
+        "PublicDescription": ": xpt prefetch message arrived in ingress pipeline",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL",
+        "BriefDescription": "UNC_M3UPI_XPT_PFTCH.BYPASS",
+        "EventCode": "0x61",
+        "EventName": "UNC_M3UPI_XPT_PFTCH.BYPASS",
         "PerPkg": "1",
-        "UMask": "0xC87FDE01",
-        "UMaskExt": "0xC87FDE",
-        "Unit": "CHA"
+        "PublicDescription": ": xpt prefetch message took bypass path",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL",
+        "BriefDescription": "UNC_M3UPI_XPT_PFTCH.FLITTED",
+        "EventCode": "0x61",
+        "EventName": "UNC_M3UPI_XPT_PFTCH.FLITTED",
         "PerPkg": "1",
-        "UMask": "0xC80EFE01",
-        "UMaskExt": "0xC80EFE",
-        "Unit": "CHA"
+        "PublicDescription": ": xpt prefetch message was slotted into flit (non bypass)",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE",
+        "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_ARB",
+        "EventCode": "0x61",
+        "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_ARB",
         "PerPkg": "1",
-        "UMask": "0xC80F7E01",
-        "UMaskExt": "0xC80F7E",
-        "Unit": "CHA"
+        "PublicDescription": ": xpt prefetch message lost arbitration",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL",
+        "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_OLD",
+        "EventCode": "0x61",
+        "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_OLD",
         "PerPkg": "1",
-        "UMask": "0xC88EFE01",
-        "UMaskExt": "0xC88EFE",
-        "Unit": "CHA"
+        "PublicDescription": ": xpt prefetch message was dropped because it became too old",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE",
+        "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL",
+        "EventCode": "0x61",
+        "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL",
         "PerPkg": "1",
-        "UMask": "0xC88F7E01",
-        "UMaskExt": "0xC88F7E",
-        "Unit": "CHA"
+        "PublicDescription": ": xpt prefetch message was dropped because it was overwritten by new message while prefetch queue was full",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR",
+        "BriefDescription": "Number of kfclks",
+        "EventCode": "0x01",
+        "EventName": "UNC_UPI_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0xCD47FF01",
-        "UMaskExt": "0xCD47FF",
-        "Unit": "CHA"
+        "PublicDescription": "Number of kfclks : Counts the number of clocks in the UPI LL.  This clock runs at 1/8th the GT/s speed of the UPI link.  For example, a 8GT/s link will have qfclk or 1GHz.  Current products do not support dynamic link speeds, so this frequency is fixed.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM",
+        "BriefDescription": "Direct packet attempts : D2C",
+        "EventCode": "0x12",
+        "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C",
         "PerPkg": "1",
-        "UMask": "0xCC47FD01",
-        "UMaskExt": "0xCC47FD",
-        "Unit": "CHA"
+        "PublicDescription": "Direct packet attempts : D2C : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM",
+        "BriefDescription": "Direct packet attempts : D2K",
+        "EventCode": "0x12",
+        "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K",
         "PerPkg": "1",
-        "UMask": "0xCC47FE01",
-        "UMaskExt": "0xCC47FE",
-        "Unit": "CHA"
+        "PublicDescription": "Direct packet attempts : D2K : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF",
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
         "PerPkg": "1",
-        "UMask": "0xC877DE01",
-        "UMaskExt": "0xC877DE",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE",
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
         "PerPkg": "1",
-        "UMask": "0xCCCFFF01",
-        "UMaskExt": "0xCCCFFF",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in TOR",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x64",
-        "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR",
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x64",
-        "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF",
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x10",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x64",
-        "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC",
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x20",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE",
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
         "PerPkg": "1",
-        "UMask": "0xCCCFFD01",
-        "UMaskExt": "0xCCCFFD",
-        "Unit": "CHA"
+        "UMask": "0x40",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA",
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
         "PerPkg": "1",
-        "UMask": "0xCCD7FD01",
-        "UMaskExt": "0xCCD7FD",
-        "Unit": "CHA"
+        "UMask": "0x80",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE",
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
         "PerPkg": "1",
-        "UMask": "0xCCCFFE01",
-        "UMaskExt": "0xCCCFFE",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE",
+        "BriefDescription": "Cycles in L1",
+        "EventCode": "0x21",
+        "EventName": "UNC_UPI_L1_POWER_CYCLES",
         "PerPkg": "1",
-        "UMask": "0xCCCFFD01",
-        "UMaskExt": "0xCCCFFD",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode.  L1 is a mode that totally shuts down a UPI link.  Use edge detect to count the number of instances when the UPI link entered L1.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA",
+        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
+        "EventCode": "0x14",
+        "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
         "PerPkg": "1",
-        "UMask": "0xCCD7FD01",
-        "UMaskExt": "0xCCD7FD",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE",
+        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
+        "EventCode": "0x14",
+        "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
         "PerPkg": "1",
-        "UMask": "0xCCCFFE01",
-        "UMaskExt": "0xCCCFFE",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA",
+        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
+        "EventCode": "0x14",
+        "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
         "PerPkg": "1",
-        "UMask": "0xCCD7FE01",
-        "UMaskExt": "0xCCD7FE",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x65",
-        "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL",
+        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
+        "EventCode": "0x14",
+        "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x65",
-        "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE",
+        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
+        "EventCode": "0x14",
+        "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x10",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x65",
-        "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT",
+        "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
+        "EventCode": "0x16",
+        "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC",
+        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
+        "EventCode": "0x15",
+        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x20",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR",
+        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
+        "EventCode": "0x15",
+        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI",
+        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
+        "EventCode": "0x15",
+        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UNC_CHA_PMM_QOS.SLOW_INSERT",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x66",
-        "EventName": "UNC_CHA_PMM_QOS.SLOW_INSERT",
+        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
+        "EventCode": "0x15",
+        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x10",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x66",
-        "EventName": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT",
+        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
+        "EventCode": "0x15",
+        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x66",
-        "EventName": "UNC_CHA_PMM_QOS.THROTTLE",
+        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
+        "EventCode": "0x15",
+        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UNC_CHA_PMM_QOS.REJ_IRQ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x66",
-        "EventName": "UNC_CHA_PMM_QOS.REJ_IRQ",
+        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
+        "EventCode": "0x15",
+        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "UMask": "0x40",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_PRQ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x66",
-        "EventName": "UNC_CHA_PMM_QOS.THROTTLE_PRQ",
+        "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1",
+        "EventCode": "0x20",
+        "EventName": "UNC_UPI_PHY_INIT_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_IRQ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x66",
-        "EventName": "UNC_CHA_PMM_QOS.THROTTLE_IRQ",
+        "BriefDescription": "L1 Req Nack",
+        "EventCode": "0x23",
+        "EventName": "UNC_UPI_POWER_L1_NACK",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "PublicDescription": "L1 Req Nack : Counts the number of times a link sends/receives a LinkReqNAck.  When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states.  This requests can either be accepted or denied.  If the Rx side replies with an Ack, the power mode will change.  If it replies with NAck, no change will take place.  This can be filtered based on Rx and Tx.  An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change).  A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x66",
-        "EventName": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP",
+        "BriefDescription": "L1 Req (same as L1 Ack).",
+        "EventCode": "0x22",
+        "EventName": "UNC_UPI_POWER_L1_REQ",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "PublicDescription": "L1 Req (same as L1 Ack). : Counts the number of times a link sends/receives a LinkReqAck.  When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states.  This requests can either be accepted or denied.  If the Rx side replies with an Ack, the power mode will change.  If it replies with NAck, no change will take place.  This can be filtered based on Rx and Tx.  An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change).  A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x67",
-        "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO",
+        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
+        "EventCode": "0x46",
+        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x67",
-        "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO",
+        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
+        "EventCode": "0x46",
+        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.IRQ_PMM",
+        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
+        "EventCode": "0x46",
+        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.PRQ_PMM",
+        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
+        "EventCode": "0x46",
+        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.PMM_MEMMODE_TOR_MATCH",
+        "BriefDescription": "Cycles in L0p",
+        "EventCode": "0x25",
+        "EventName": "UNC_UPI_RxL0P_POWER_CYCLES",
         "PerPkg": "1",
-        "UMaskExt": "0x08",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses.  Use edge detect to count the number of instances when the UPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.PMM_MEMMODE_TORMATCH_MULTI",
+        "BriefDescription": "Cycles in L0",
+        "EventCode": "0x24",
+        "EventName": "UNC_UPI_RxL0_POWER_CYCLES",
         "PerPkg": "1",
-        "UMaskExt": "0x400",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : PMM Access",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.PMM",
+        "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass",
+        "EventCode": "0x05",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
         "PerPkg": "1",
-        "UMaskExt": "0x08",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0xe",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : PMM Access",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.PMM",
+        "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode",
+        "EventCode": "0x05",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
         "PerPkg": "1",
-        "UMaskExt": "0x08",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x10e",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Distress signal asserted : PMM Local",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_CHA_DISTRESS_ASSERTED.PMM_LOCAL",
+        "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard",
+        "EventCode": "0x05",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0xf",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Distress signal asserted : PMM Remote",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_CHA_DISTRESS_ASSERTED.PMM_NONLOCAL",
+        "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode",
+        "EventCode": "0x05",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x10f",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM",
+        "BriefDescription": "Matches on Receive path of a UPI Port : Request",
+        "EventCode": "0x05",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
         "PerPkg": "1",
-        "UMask": "0xC8678A01",
-        "UMaskExt": "0xC8678A",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Receive path of a UPI Port : Request : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM",
+        "BriefDescription": "Matches on Receive path of a UPI Port : Request, Match Opcode",
+        "EventCode": "0x05",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC",
         "PerPkg": "1",
-        "UMask": "0xC8668A01",
-        "UMaskExt": "0xC8668A",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Receive path of a UPI Port : Request, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x108",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remote memory",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM",
+        "BriefDescription": "Matches on Receive path of a UPI Port : Response - Conflict",
+        "EventCode": "0x05",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT",
         "PerPkg": "1",
-        "UMask": "0xC8670A01",
-        "UMaskExt": "0xC8670A",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Receive path of a UPI Port : Response - Conflict : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x1aa",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM",
+        "BriefDescription": "Matches on Receive path of a UPI Port : Response - Invalid",
+        "EventCode": "0x05",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI",
         "PerPkg": "1",
-        "UMask": "0xC86F8A01",
-        "UMaskExt": "0xC86F8A",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Receive path of a UPI Port : Response - Invalid : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x12a",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM",
+        "BriefDescription": "Matches on Receive path of a UPI Port : Response - Data",
+        "EventCode": "0x05",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
         "PerPkg": "1",
-        "UMask": "0xC86E8A01",
-        "UMaskExt": "0xC86E8A",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Receive path of a UPI Port : Response - Data : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0xc",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM",
+        "BriefDescription": "Matches on Receive path of a UPI Port : Response - Data, Match Opcode",
+        "EventCode": "0x05",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
         "PerPkg": "1",
-        "UMask": "0xC86F0A01",
-        "UMaskExt": "0xC86F0A",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Receive path of a UPI Port : Response - Data, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x10c",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM",
+        "BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data",
+        "EventCode": "0x05",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA",
         "PerPkg": "1",
-        "UMask": "0xC8678A01",
-        "UMaskExt": "0xC8678A",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Receive path of a UPI Port : Response - No Data : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0xa",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM",
+        "BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data, Match Opcode",
+        "EventCode": "0x05",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
         "PerPkg": "1",
-        "UMask": "0xC8668A01",
-        "UMaskExt": "0xC8668A",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Receive path of a UPI Port : Response - No Data, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x10a",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM",
+        "BriefDescription": "Matches on Receive path of a UPI Port : Snoop",
+        "EventCode": "0x05",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
         "PerPkg": "1",
-        "UMask": "0xC8670A01",
-        "UMaskExt": "0xC8670A",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Receive path of a UPI Port : Snoop : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x9",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM",
+        "BriefDescription": "Matches on Receive path of a UPI Port : Snoop, Match Opcode",
+        "EventCode": "0x05",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC",
         "PerPkg": "1",
-        "UMask": "0xC86F8A01",
-        "UMaskExt": "0xC86F8A",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Receive path of a UPI Port : Snoop, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x109",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM",
+        "BriefDescription": "Matches on Receive path of a UPI Port : Writeback",
+        "EventCode": "0x05",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
         "PerPkg": "1",
-        "UMask": "0xC86E8A01",
-        "UMaskExt": "0xC86E8A",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Receive path of a UPI Port : Writeback : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0xd",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM",
+        "BriefDescription": "Matches on Receive path of a UPI Port : Writeback, Match Opcode",
+        "EventCode": "0x05",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC",
         "PerPkg": "1",
-        "UMask": "0xC86F0A01",
-        "UMaskExt": "0xC86F0A",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Receive path of a UPI Port : Writeback, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x10d",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : DDR4 Access",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.DDR",
+        "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 0",
+        "EventCode": "0x31",
+        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0",
         "PerPkg": "1",
-        "UMaskExt": "0x04",
-        "Unit": "CHA"
+        "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 0 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : DDR4 Access",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR",
+        "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 1",
+        "EventCode": "0x31",
+        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1",
         "PerPkg": "1",
-        "UMaskExt": "0x04",
-        "Unit": "CHA"
+        "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 1 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_DDR",
+        "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 2",
+        "EventCode": "0x31",
+        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2",
         "PerPkg": "1",
-        "UMask": "0xC8978601",
-        "UMaskExt": "0xC89786",
-        "Unit": "CHA"
+        "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 2 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_DDR",
+        "BriefDescription": "CRC Errors Detected",
+        "EventCode": "0x0B",
+        "EventName": "UNC_UPI_RxL_CRC_ERRORS",
         "PerPkg": "1",
-        "UMask": "0xC8968601",
-        "UMaskExt": "0xC89686",
-        "Unit": "CHA"
+        "PublicDescription": "CRC Errors Detected : Number of CRC errors detected in the UPI Agent.  Each UPI flit incorporates 8 bits of CRC for error detection.  This counts the number of flits where the CRC was able to detect an error.  After an error has been detected, the UPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_DDR",
+        "BriefDescription": "LLR Requests Sent",
+        "EventCode": "0x08",
+        "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT",
         "PerPkg": "1",
-        "UMask": "0xC8970601",
-        "UMaskExt": "0xC89706",
-        "Unit": "CHA"
+        "PublicDescription": "LLR Requests Sent : Number of LLR Requests were transmitted.  This should generally be <= the number of CRC errors detected.  If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR",
+        "BriefDescription": "VN0 Credit Consumed",
+        "EventCode": "0x39",
+        "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0",
         "PerPkg": "1",
-        "UMask": "0xC8678601",
-        "UMaskExt": "0xC86786",
-        "Unit": "CHA"
+        "PublicDescription": "VN0 Credit Consumed : Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR",
+        "BriefDescription": "VN1 Credit Consumed",
+        "EventCode": "0x3A",
+        "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1",
         "PerPkg": "1",
-        "UMask": "0xC8668601",
-        "UMaskExt": "0xC86686",
-        "Unit": "CHA"
+        "PublicDescription": "VN1 Credit Consumed : Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR",
+        "BriefDescription": "VNA Credit Consumed",
+        "EventCode": "0x38",
+        "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA",
         "PerPkg": "1",
-        "UMask": "0xC8670601",
-        "UMaskExt": "0xC86706",
-        "Unit": "CHA"
+        "PublicDescription": "VNA Credit Consumed : Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR",
+        "BriefDescription": "Valid Flits Received : All Data",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
         "PerPkg": "1",
-        "UMask": "0xC86F8601",
-        "UMaskExt": "0xC86F86",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c).",
+        "UMask": "0xf",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR",
+        "BriefDescription": "Valid Flits Received : Null FLITs received from any slot",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
         "PerPkg": "1",
-        "UMask": "0xC86E8601",
-        "UMaskExt": "0xC86E86",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Received : Null FLITs received from any slot : Shows legal flit time (hides impact of L0p and L0c).",
+        "UMask": "0x27",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR",
+        "BriefDescription": "Valid Flits Received : Data",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.DATA",
         "PerPkg": "1",
-        "UMask": "0xC86F0601",
-        "UMaskExt": "0xC86F06",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Received : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR",
+        "BriefDescription": "Valid Flits Received : Null FLITs received from any slot",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.IDLE",
         "PerPkg": "1",
-        "UMask": "0xC8168601",
-        "UMaskExt": "0xC81686",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Received : Null FLITs received from any slot : Shows legal flit time (hides impact of L0p and L0c).",
+        "UMask": "0x47",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR",
+        "BriefDescription": "Valid Flits Received : LLCRD Not Empty",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.LLCRD",
         "PerPkg": "1",
-        "UMask": "0xC8170601",
-        "UMaskExt": "0xC81706",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Received : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
+        "UMask": "0x10",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_DDR",
+        "BriefDescription": "Valid Flits Received : LLCTRL",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.LLCTRL",
         "PerPkg": "1",
-        "UMask": "0xC8978601",
-        "UMaskExt": "0xC89786",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Received : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet.  Enables counting of slot 0 LLCTRL messages.",
+        "UMask": "0x40",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_DDR",
+        "BriefDescription": "Valid Flits Received : All Non Data",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
         "PerPkg": "1",
-        "UMask": "0xC8968601",
-        "UMaskExt": "0xC89686",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c).",
+        "UMask": "0x97",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_DDR",
+        "BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Empty",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.NULL",
         "PerPkg": "1",
-        "UMask": "0xC8970601",
-        "UMaskExt": "0xC89706",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Received : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.",
+        "UMask": "0x20",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR",
+        "BriefDescription": "Valid Flits Received : Protocol Header",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.PROTHDR",
         "PerPkg": "1",
-        "UMask": "0xC8678601",
-        "UMaskExt": "0xC86786",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Received : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
+        "UMask": "0x80",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR",
+        "BriefDescription": "Valid Flits Received : Slot 0",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.SLOT0",
         "PerPkg": "1",
-        "UMask": "0xC8668601",
-        "UMaskExt": "0xC86686",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Received : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR",
+        "BriefDescription": "Valid Flits Received : Slot 1",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.SLOT1",
         "PerPkg": "1",
-        "UMask": "0xC8670601",
-        "UMaskExt": "0xC86706",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Received : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR",
+        "BriefDescription": "Valid Flits Received : Slot 2",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.SLOT2",
         "PerPkg": "1",
-        "UMask": "0xC86F8601",
-        "UMaskExt": "0xC86F86",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Received : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.",
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR",
+        "BriefDescription": "RxQ Flit Buffer Allocations : Slot 0",
+        "EventCode": "0x30",
+        "EventName": "UNC_UPI_RxL_INSERTS.SLOT0",
         "PerPkg": "1",
-        "UMask": "0xC86E8601",
-        "UMaskExt": "0xC86E86",
-        "Unit": "CHA"
+        "PublicDescription": "RxQ Flit Buffer Allocations : Slot 0 : Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR",
+        "BriefDescription": "RxQ Flit Buffer Allocations : Slot 1",
+        "EventCode": "0x30",
+        "EventName": "UNC_UPI_RxL_INSERTS.SLOT1",
         "PerPkg": "1",
-        "UMask": "0xC86F0601",
-        "UMaskExt": "0xC86F06",
-        "Unit": "CHA"
+        "PublicDescription": "RxQ Flit Buffer Allocations : Slot 1 : Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR",
+        "BriefDescription": "RxQ Flit Buffer Allocations : Slot 2",
+        "EventCode": "0x30",
+        "EventName": "UNC_UPI_RxL_INSERTS.SLOT2",
         "PerPkg": "1",
-        "UMask": "0xC8F3FD04",
-        "UMaskExt": "0xC8F3FD",
-        "Unit": "CHA"
+        "PublicDescription": "RxQ Flit Buffer Allocations : Slot 2 : Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA",
+        "BriefDescription": "RxQ Occupancy - All Packets : Slot 0",
+        "EventCode": "0x32",
+        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0",
         "PerPkg": "1",
-        "UMask": "0xCCD7FF01",
-        "UMaskExt": "0xCCD7FF",
-        "Unit": "CHA"
+        "PublicDescription": "RxQ Occupancy - All Packets : Slot 0 : Accumulates the number of elements in the UPI RxQ in each cycle.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF",
+        "BriefDescription": "RxQ Occupancy - All Packets : Slot 1",
+        "EventCode": "0x32",
+        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1",
         "PerPkg": "1",
-        "UMask": "0xC867FE01",
-        "UMaskExt": "0xC867FE",
-        "Unit": "CHA"
+        "PublicDescription": "RxQ Occupancy - All Packets : Slot 1 : Accumulates the number of elements in the UPI RxQ in each cycle.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF",
+        "BriefDescription": "RxQ Occupancy - All Packets : Slot 2",
+        "EventCode": "0x32",
+        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2",
         "PerPkg": "1",
-        "UMask": "0xC867FE01",
-        "UMaskExt": "0xC867FE",
-        "Unit": "CHA"
+        "PublicDescription": "RxQ Occupancy - All Packets : Slot 2 : Accumulates the number of elements in the UPI RxQ in each cycle.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL",
+        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
+        "EventCode": "0x33",
+        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
         "PerPkg": "1",
-        "UMask": "0xC86FFE01",
-        "UMaskExt": "0xC86FFE",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL",
+        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
+        "EventCode": "0x33",
+        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
         "PerPkg": "1",
-        "UMask": "0xC80EFE01",
-        "UMaskExt": "0xC80EFE",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE",
+        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
+        "EventCode": "0x33",
+        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
         "PerPkg": "1",
-        "UMask": "0xC80F7E01",
-        "UMaskExt": "0xC80F7E",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL",
+        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
+        "EventCode": "0x33",
+        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
         "PerPkg": "1",
-        "UMask": "0xC88EFE01",
-        "UMaskExt": "0xC88EFE",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE",
+        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
+        "EventCode": "0x33",
+        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
         "PerPkg": "1",
-        "UMask": "0xC88F7E01",
-        "UMaskExt": "0xC88F7E",
-        "Unit": "CHA"
+        "UMask": "0x10",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH",
+        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
+        "EventCode": "0x33",
+        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
         "PerPkg": "1",
-        "UMask": "0xC8C7FF01",
-        "UMaskExt": "0xC8C7FF",
-        "Unit": "CHA"
+        "UMask": "0x20",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
         "PerPkg": "1",
-        "UMask": "0xC8D7FF01",
-        "UMaskExt": "0xC8D7FF",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
         "PerPkg": "1",
-        "UMask": "0xCD47FF01",
-        "UMaskExt": "0xCD47FF",
-        "Unit": "CHA"
+        "UMask": "0x40",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
         "PerPkg": "1",
-        "UMask": "0xCC57FF01",
-        "UMaskExt": "0xCC57FF",
-        "Unit": "CHA"
+        "UMask": "0x20",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
         "PerPkg": "1",
-        "UMask": "0xCC27FF01",
-        "UMaskExt": "0xCC27FF",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
         "PerPkg": "1",
-        "UMask": "0xCC47FF01",
-        "UMaskExt": "0xCC47FF",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
         "PerPkg": "1",
-        "UMask": "0xCC47FD01",
-        "UMaskExt": "0xCC47FD",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
         "PerPkg": "1",
-        "UMask": "0xCC47FE01",
-        "UMaskExt": "0xCC47FE",
-        "Unit": "CHA"
+        "UMask": "0x80",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
         "PerPkg": "1",
-        "UMask": "0xC877DE01",
-        "UMaskExt": "0xC877DE",
-        "Unit": "CHA"
+        "UMask": "0x10",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL",
+        "BriefDescription": "Cycles in L0p",
+        "EventCode": "0x27",
+        "EventName": "UNC_UPI_TxL0P_POWER_CYCLES",
         "PerPkg": "1",
-        "UMask": "0xC87FDE01",
-        "UMaskExt": "0xC87FDE",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses.  Use edge detect to count the number of instances when the UPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF",
+        "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
+        "EventCode": "0x28",
+        "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
         "PerPkg": "1",
-        "UMask": "0xC867FF01",
-        "UMaskExt": "0xC867FF",
-        "Unit": "CHA"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL",
+        "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
+        "EventCode": "0x29",
+        "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
         "PerPkg": "1",
-        "UMask": "0xC86FFF01",
-        "UMaskExt": "0xC86FFF",
-        "Unit": "CHA"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE",
+        "BriefDescription": "Cycles in L0",
+        "EventCode": "0x26",
+        "EventName": "UNC_UPI_TxL0_POWER_CYCLES",
         "PerPkg": "1",
-        "UMask": "0xCCCFFF01",
-        "UMaskExt": "0xCCCFFF",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI",
+        "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass",
+        "EventCode": "0x04",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
         "PerPkg": "1",
-        "UMask": "0xCC23FF04",
-        "UMaskExt": "0xCC23FF",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0xe",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Devices",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH",
+        "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode",
+        "EventCode": "0x04",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
         "PerPkg": "1",
-        "UMask": "0xC8C3FF04",
-        "UMaskExt": "0xC8C3FF",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x10e",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR",
+        "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard",
+        "EventCode": "0x04",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
         "PerPkg": "1",
-        "UMask": "0xCD43FF04",
-        "UMaskExt": "0xCD43FF",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0xf",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR",
+        "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode",
+        "EventCode": "0x04",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
         "PerPkg": "1",
-        "UMask": "0xCD43FD04",
-        "UMaskExt": "0xCD43FD",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x10f",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR",
+        "BriefDescription": "Matches on Transmit path of a UPI Port : Request",
+        "EventCode": "0x04",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
         "PerPkg": "1",
-        "UMask": "0xCD43FE04",
-        "UMaskExt": "0xCD43FE",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Transmit path of a UPI Port : Request : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_DDR",
+        "BriefDescription": "Matches on Transmit path of a UPI Port : Request, Match Opcode",
+        "EventCode": "0x04",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC",
         "PerPkg": "1",
-        "UMask": "0xc8678601",
-        "UMaskExt": "0xc86786",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Transmit path of a UPI Port : Request, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x108",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_DDR",
+        "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Conflict",
+        "EventCode": "0x04",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT",
         "PerPkg": "1",
-        "UMask": "0xc8668601",
-        "UMaskExt": "0xc86686",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Transmit path of a UPI Port : Response - Conflict : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x1aa",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_DDR",
+        "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Invalid",
+        "EventCode": "0x04",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI",
         "PerPkg": "1",
-        "UMask": "0xc8670601",
-        "UMaskExt": "0xc86706",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Transmit path of a UPI Port : Response - Invalid : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x12a",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts; WCiL misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_DDR",
+        "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data",
+        "EventCode": "0x04",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
         "PerPkg": "1",
-        "UMask": "0xc86f8601",
-        "UMaskExt": "0xc86f86",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Transmit path of a UPI Port : Response - Data : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0xc",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts; WCiL misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR",
+        "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data, Match Opcode",
+        "EventCode": "0x04",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
         "PerPkg": "1",
-        "UMask": "0xc86e8601",
-        "UMaskExt": "0xc86e86",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Transmit path of a UPI Port : Response - Data, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x10c",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts; WCiL misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR",
+        "BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data",
+        "EventCode": "0x04",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
         "PerPkg": "1",
-        "UMask": "0xc86f0601",
-        "UMaskExt": "0xc86f06",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Transmit path of a UPI Port : Response - No Data : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0xa",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_DDR",
+        "BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode",
+        "EventCode": "0x04",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
         "PerPkg": "1",
-        "UMask": "0xc8678601",
-        "UMaskExt": "0xc86786",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x10a",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_LOCAL_DDR",
+        "BriefDescription": "Matches on Transmit path of a UPI Port : Snoop",
+        "EventCode": "0x04",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
         "PerPkg": "1",
-        "UMask": "0xc8668601",
-        "UMaskExt": "0xc86686",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Transmit path of a UPI Port : Snoop : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x9",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_REMOTE_DDR",
+        "BriefDescription": "Matches on Transmit path of a UPI Port : Snoop, Match Opcode",
+        "EventCode": "0x04",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC",
         "PerPkg": "1",
-        "UMask": "0xc8670601",
-        "UMaskExt": "0xc86706",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Transmit path of a UPI Port : Snoop, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x109",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_DDR",
+        "BriefDescription": "Matches on Transmit path of a UPI Port : Writeback",
+        "EventCode": "0x04",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
         "PerPkg": "1",
-        "UMask": "0xc86f8601",
-        "UMaskExt": "0xc86f86",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Transmit path of a UPI Port : Writeback : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0xd",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR",
+        "BriefDescription": "Matches on Transmit path of a UPI Port : Writeback, Match Opcode",
+        "EventCode": "0x04",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC",
         "PerPkg": "1",
-        "UMask": "0xc86e8601",
-        "UMaskExt": "0xc86e86",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Transmit path of a UPI Port : Writeback, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x10d",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR",
+        "BriefDescription": "Tx Flit Buffer Bypassed",
+        "EventCode": "0x41",
+        "EventName": "UNC_UPI_TxL_BYPASSED",
         "PerPkg": "1",
-        "UMask": "0xc86f0601",
-        "UMaskExt": "0xc86f06",
-        "Unit": "CHA"
+        "PublicDescription": "Tx Flit Buffer Bypassed : Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the UPI Link. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core.  Non Modified Write Backs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE",
+        "BriefDescription": "Valid Flits Sent : All Data",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
         "PerPkg": "1",
-        "UMask": "0xcc3fff01",
-        "UMaskExt": "0xcc3fff",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Sent : All Data : Shows legal flit time (hides impact of L0p and L0c).",
+        "UMask": "0xf",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Responses to snoops of any type that miss the IIO cache",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.ALL_MISS",
+        "BriefDescription": "Valid Flits Sent : Null FLITs transmitted to any slot",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
         "PerPkg": "1",
-        "UMask": "0x71",
-        "Unit": "IRP"
+        "PublicDescription": "Valid Flits Sent : Null FLITs transmitted to any slot : Shows legal flit time (hides impact of L0p and L0c).",
+        "UMask": "0x27",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT",
+        "BriefDescription": "Valid Flits Sent : Data",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.DATA",
         "PerPkg": "1",
-        "UMask": "0x7e",
-        "Unit": "IRP"
+        "PublicDescription": "Valid Flits Sent : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES",
+        "BriefDescription": "Valid Flits Sent : Idle",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.IDLE",
         "PerPkg": "1",
-        "UMask": "0x74",
-        "Unit": "IRP"
+        "PublicDescription": "Valid Flits Sent : Idle : Shows legal flit time (hides impact of L0p and L0c).",
+        "UMask": "0x47",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I",
+        "BriefDescription": "Valid Flits Sent : LLCRD Not Empty",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.LLCRD",
         "PerPkg": "1",
-        "UMask": "0x72",
-        "Unit": "IRP"
+        "PublicDescription": "Valid Flits Sent : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
+        "UMask": "0x10",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_SPECITOM",
+        "BriefDescription": "Valid Flits Sent : LLCTRL",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.LLCTRL",
         "PerPkg": "1",
-        "UMask": "0xcc57fe01",
-        "UMaskExt": "0xcc57fe",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Sent : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet.  Enables counting of slot 0 LLCTRL messages.",
+        "UMask": "0x40",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_SPECITOM",
+        "BriefDescription": "Valid Flits Sent : All Non Data",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
         "PerPkg": "1",
-        "UMask": "0xcc57fe01",
-        "UMaskExt": "0xcc57fe",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c).",
+        "UMask": "0x97",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE",
+        "BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.NULL",
         "PerPkg": "1",
-        "UMask": "0xC837FE01",
-        "UMaskExt": "0xC837FE",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.",
+        "UMask": "0x20",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE",
+        "BriefDescription": "Valid Flits Sent : Protocol Header",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.PROTHDR",
         "PerPkg": "1",
-        "UMask": "0xC837FD01",
-        "UMaskExt": "0xC837FD",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Sent : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
+        "UMask": "0x80",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE",
+        "BriefDescription": "Valid Flits Sent : Slot 0",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.SLOT0",
         "PerPkg": "1",
-        "UMask": "0xC837FF01",
-        "UMaskExt": "0xC837FF",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Sent : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores that hit in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_SPECITOM",
+        "BriefDescription": "Valid Flits Sent : Slot 1",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.SLOT1",
         "PerPkg": "1",
-        "UMask": "0xcc57fd01",
-        "UMaskExt": "0xcc57fd",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Sent : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : WBStoIs issued by an IA Core.  Non Modified Write Backs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI",
+        "BriefDescription": "Valid Flits Sent : Slot 2",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.SLOT2",
         "PerPkg": "1",
-        "UMask": "0xcc67ff01",
-        "UMaskExt": "0xcc67ff",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Sent : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.",
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : WBEFtoIs issued by an IA Core.  Non Modified Write Backs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI",
+        "BriefDescription": "Tx Flit Buffer Allocations",
+        "EventCode": "0x40",
+        "EventName": "UNC_UPI_TxL_INSERTS",
         "PerPkg": "1",
-        "UMask": "0xcc37ff01",
-        "UMaskExt": "0xcc37ff",
-        "Unit": "CHA"
+        "PublicDescription": "Tx Flit Buffer Allocations : Number of allocations into the UPI Tx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : WBMtoEs issued by an IA Core.  Non Modified Write Backs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE",
+        "BriefDescription": "Tx Flit Buffer Occupancy",
+        "EventCode": "0x42",
+        "EventName": "UNC_UPI_TxL_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0xcc2fff01",
-        "UMaskExt": "0xcc2fff",
-        "Unit": "CHA"
+        "PublicDescription": "Tx Flit Buffer Occupancy : Accumulates the number of flits in the TxQ.  Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE",
+        "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
+        "EventCode": "0x45",
+        "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
         "PerPkg": "1",
-        "UMask": "0xC837FF01",
-        "UMaskExt": "0xC837FF",
-        "Unit": "CHA"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE",
+        "BriefDescription": "VNA Credits Pending Return - Occupancy",
+        "EventCode": "0x44",
+        "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0xC837FD01",
-        "UMaskExt": "0xC837FD",
-        "Unit": "CHA"
+        "PublicDescription": "VNA Credits Pending Return - Occupancy : Number of VNA credits in the Rx side that are waitng to be returned back across the link.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE",
+        "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
+        "EventCode": "0xff",
+        "EventName": "UNC_U_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0xC837FE01",
-        "UMaskExt": "0xC837FE",
-        "Unit": "CHA"
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x77",
-        "EventName": "UNC_M2M_RxC_AD_PREF_OCCUPANCY",
+        "BriefDescription": "Message Received : Doorbell",
+        "EventCode": "0x42",
+        "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "UMask": "0x8",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Cache Lookups : Code Read Misses",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_MISS",
+        "BriefDescription": "Message Received : Interrupt",
+        "EventCode": "0x42",
+        "EventName": "UNC_U_EVENT_MSG.INT_PRIO",
         "PerPkg": "1",
-        "UMask": "0x1BD001",
-        "UMaskExt": "0x1BD0",
-        "Unit": "CHA"
+        "PublicDescription": "Message Received : Interrupt : Interrupts",
+        "UMask": "0x10",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Cache Lookups : RFO Misses",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.RFO_MISS",
+        "BriefDescription": "Message Received : IPI",
+        "EventCode": "0x42",
+        "EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
         "PerPkg": "1",
-        "UMask": "0x1BC801",
-        "UMaskExt": "0x1BC8",
-        "Unit": "CHA"
+        "PublicDescription": "Message Received : IPI : Inter Processor Interrupts",
+        "UMask": "0x4",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Cache Lookups : Reads",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.READ",
+        "BriefDescription": "Message Received : MSI",
+        "EventCode": "0x42",
+        "EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
         "PerPkg": "1",
-        "UMask": "0x1BD9FF",
-        "UMaskExt": "0x1BD9",
-        "Unit": "CHA"
+        "PublicDescription": "Message Received : MSI : Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)",
+        "UMask": "0x2",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Cache Lookups : Read Misses",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS",
+        "BriefDescription": "Message Received : VLW",
+        "EventCode": "0x42",
+        "EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
         "PerPkg": "1",
-        "UMask": "0x1BD901",
-        "UMaskExt": "0x1BD9",
-        "Unit": "CHA"
+        "PublicDescription": "Message Received : VLW : Virtual Logical Wire (legacy) message were received from Uncore.",
+        "UMask": "0x1",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Cache Lookups : Locally HOMed Read Misses",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_LOC_HOM",
+        "BriefDescription": "IDI Lock/SplitLock Cycles",
+        "EventCode": "0x44",
+        "EventName": "UNC_U_LOCK_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x0BD901",
-        "UMaskExt": "0x0BD9",
-        "Unit": "CHA"
+        "PublicDescription": "IDI Lock/SplitLock Cycles : Number of times an IDI Lock/SplitLock sequence was started",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Cache Lookups : Remotely HOMed Read Misses",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_REM_HOM",
+        "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB",
+        "EventCode": "0x4D",
+        "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB",
         "PerPkg": "1",
-        "UMask": "0x13D901",
-        "UMaskExt": "0x13D9",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_LOC_HOM",
+        "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS",
+        "EventCode": "0x4D",
+        "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS",
         "PerPkg": "1",
-        "UMask": "0x09D9FF",
-        "UMaskExt": "0x09D9",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.READ_REMOTE_LOC_HOM",
+        "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB",
+        "EventCode": "0x4D",
+        "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB",
         "PerPkg": "1",
-        "UMask": "0x0A19FF",
-        "UMaskExt": "0x0A19",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_REM_HOM",
+        "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS",
+        "EventCode": "0x4D",
+        "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS",
         "PerPkg": "1",
-        "UMask": "0x11D9FF",
-        "UMaskExt": "0x11D9",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Cache Lookups : Reads that Hit the Snoop Filter",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.READ_SF_HIT",
+        "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB",
+        "EventCode": "0x4D",
+        "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB",
         "PerPkg": "1",
-        "UMask": "0x1BD90E",
-        "UMaskExt": "0x1BD9",
-        "Unit": "CHA"
+        "UMask": "0x10",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.READ_OR_SNOOP_REMOTE_MISS_REM_HOM",
+        "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS",
+        "EventCode": "0x4D",
+        "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS",
         "PerPkg": "1",
-        "UMask": "0x161901",
-        "UMaskExt": "0x1619",
-        "Unit": "CHA"
+        "UMask": "0x20",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts : All Ports",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL",
-        "FCMask": "0x04",
+        "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB",
+        "EventCode": "0x4D",
+        "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "UMask": "0x40",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Cache Lookups : Filters Requests for those that write info into the cache",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
+        "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS",
+        "EventCode": "0x4D",
+        "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS",
         "PerPkg": "1",
-        "UMask": "0x1A42FF",
-        "UMaskExt": "0x1A42",
-        "Unit": "CHA"
+        "UMask": "0x80",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Cache Lookups : Transactions homed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.LOC_HOM",
+        "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
+        "EventCode": "0x4E",
+        "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
         "PerPkg": "1",
-        "UMask": "0x0BDFFF",
-        "UMaskExt": "0x0BDF",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Cache Lookups : Transactions homed remotely",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.REM_HOM",
+        "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
+        "EventCode": "0x4E",
+        "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
         "PerPkg": "1",
-        "UMask": "0x15DFFF",
-        "UMaskExt": "0x15DF",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Cache Lookups : CRd Requests that come from a Remote socket",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE",
+        "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB",
+        "EventCode": "0x4E",
+        "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB",
         "PerPkg": "1",
-        "UMask": "0x1A10FF",
-        "UMaskExt": "0x1A10",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Cache Lookups : CRd Requests that come from the local socket (usually the core)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL",
+        "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS",
+        "EventCode": "0x4E",
+        "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS",
         "PerPkg": "1",
-        "UMask": "0x19D0FF",
-        "UMaskExt": "0x19D0",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Cache and Snoop Filter Lookups; Prefetch requests to the LLC that come from the local socket (usually the core)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL",
+        "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK",
+        "EventCode": "0x4E",
+        "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK",
         "PerPkg": "1",
-        "UMask": "0x189DFF",
-        "UMaskExt": "0x189D",
-        "Unit": "CHA"
+        "UMask": "0x20",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Cache Lookups : Code Reads",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ",
+        "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC",
+        "EventCode": "0x4E",
+        "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC",
         "PerPkg": "1",
-        "UMask": "0x1BD0FF",
-        "UMaskExt": "0x1BD0",
-        "Unit": "CHA"
+        "UMask": "0x40",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x74",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPTUPI",
+        "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
+        "EventCode": "0x4E",
+        "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x10",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL",
-        "FCMask": "0x04",
+        "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL",
+        "EventCode": "0x4E",
+        "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL",
         "PerPkg": "1",
-        "UMask": "0xFF",
-        "Unit": "IIO"
+        "UMask": "0x80",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x75",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPTUPI_ALLCH",
+        "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK",
+        "EventCode": "0x4F",
+        "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK",
         "PerPkg": "1",
-        "UMask": "0x15",
-        "Unit": "M2M"
+        "UMask": "0x1",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x75",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH2_XPTUPI",
+        "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC",
+        "EventCode": "0x4F",
+        "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "UMask": "0x2",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x75",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPTUPI",
+        "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK",
+        "EventCode": "0x45",
+        "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Cycles PHOLD Assert to Ack : Assert to ACK : PHOLD cycles.",
+        "UMask": "0x1",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x75",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPTUPI",
+        "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+        "EventCode": "0x4C",
+        "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x4",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x74",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPTUPI_ALLCH",
+        "BriefDescription": "UNC_U_RACU_DRNG.RDRAND",
+        "EventCode": "0x4C",
+        "EventName": "UNC_U_RACU_DRNG.RDRAND",
         "PerPkg": "1",
-        "UMask": "0x15",
-        "Unit": "M2M"
+        "UMask": "0x1",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x74",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH2_XPTUPI",
+        "BriefDescription": "UNC_U_RACU_DRNG.RDSEED",
+        "EventCode": "0x4C",
+        "EventName": "UNC_U_RACU_DRNG.RDSEED",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "UMask": "0x2",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x74",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPTUPI",
+        "BriefDescription": "RACU Request",
+        "EventCode": "0x46",
+        "EventName": "UNC_U_RACU_REQUESTS",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "RACU Request : Number outstanding register requests within message channel tracker",
+        "Unit": "UBOX"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json
index 281f3605881d2..ee4dac6fc7971 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json
@@ -1,16 +1,13 @@
 [
     {
         "BriefDescription": "Clockticks of the power control unit (PCU)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventName": "UNC_P_CLOCKTICKS",
         "PerPkg": "1",
+        "PublicDescription": "Clockticks of the power control unit (PCU) : The PCU runs off a fixed 1 GHz clock.  This event counts the number of pclk cycles measured while the counter was enabled.  The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x60",
         "EventName": "UNC_P_CORE_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -18,8 +15,6 @@
     },
     {
         "BriefDescription": "UNC_P_DEMOTIONS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x30",
         "EventName": "UNC_P_DEMOTIONS",
         "PerPkg": "1",
@@ -27,44 +22,38 @@
     },
     {
         "BriefDescription": "Phase Shed 0 Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x75",
         "EventName": "UNC_P_FIVR_PS_PS0_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Phase Shed 1 Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x76",
         "EventName": "UNC_P_FIVR_PS_PS1_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Phase Shed 2 Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x77",
         "EventName": "UNC_P_FIVR_PS_PS2_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Phase Shed 3 Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x78",
         "EventName": "UNC_P_FIVR_PS_PS3_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "AVX256 Frequency Clipping",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x49",
         "EventName": "UNC_P_FREQ_CLIP_AVX256",
         "PerPkg": "1",
@@ -72,8 +61,6 @@
     },
     {
         "BriefDescription": "AVX512 Frequency Clipping",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x4a",
         "EventName": "UNC_P_FREQ_CLIP_AVX512",
         "PerPkg": "1",
@@ -81,155 +68,137 @@
     },
     {
         "BriefDescription": "Thermal Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x04",
         "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Thermal Strongest Upper Limit Cycles : Number of cycles any frequency is reduced due to a thermal limit.  Count only if throttling is occurring.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Power Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x05",
         "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Power Strongest Upper Limit Cycles : Counts the number of cycles when power is the upper limit on frequency.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x73",
         "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "IO P Limit Strongest Lower Limit Cycles : Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower.  This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW.  This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Cycles spent changing Frequency",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x74",
         "EventName": "UNC_P_FREQ_TRANS_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Cycles spent changing Frequency : Counts the number of cycles when the system is changing frequency.  This can not be filtered by thread ID.  One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Memory Phase Shedding Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x2F",
         "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has triggered memory phase shedding.  This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x2A",
         "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Package C State Residency - C0 : Counts the number of cycles when the package was in C0.  This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C2E",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x2B",
         "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Package C State Residency - C2E : Counts the number of cycles when the package was in C2E.  This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x2C",
         "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Package C State Residency - C3 : Counts the number of cycles when the package was in C3.  This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x2D",
         "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Package C State Residency - C6 : Counts the number of cycles when the package was in C6.  This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x06",
         "EventName": "UNC_P_PMAX_THROTTLED_CYCLES",
         "PerPkg": "1",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "External Prochot",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0A",
-        "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
+        "BriefDescription": "Number of cores in C-State : C0 and C1",
+        "EventCode": "0x80",
+        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
         "PerPkg": "1",
+        "PublicDescription": "Number of cores in C-State : C0 and C1 : This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "Internal Prochot",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x09",
-        "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
+        "BriefDescription": "Number of cores in C-State : C3",
+        "EventCode": "0x80",
+        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
         "PerPkg": "1",
+        "PublicDescription": "Number of cores in C-State : C3 : This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "Total Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x72",
-        "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
+        "BriefDescription": "Number of cores in C-State : C6 and C7",
+        "EventCode": "0x80",
+        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
         "PerPkg": "1",
+        "PublicDescription": "Number of cores in C-State : C6 and C7 : This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "VR Hot",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_P_VR_HOT_CYCLES",
+        "BriefDescription": "External Prochot",
+        "EventCode": "0x0A",
+        "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "External Prochot : Counts the number of cycles that we are in external PROCHOT mode.  This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "Number of cores in C-State : C0 and C1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
+        "BriefDescription": "Internal Prochot",
+        "EventCode": "0x09",
+        "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Internal Prochot : Counts the number of cycles that we are in Internal PROCHOT mode.  This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "Number of cores in C-State : C3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
+        "BriefDescription": "Total Core C State Transition Cycles",
+        "EventCode": "0x72",
+        "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Total Core C State Transition Cycles : Number of cycles spent performing core C state transitions across all cores.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "Number of cores in C-State : C6 and C7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
+        "BriefDescription": "VR Hot",
+        "EventCode": "0x42",
+        "EventName": "UNC_P_VR_HOT_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR is hot.  Does not cover DRAM VRs",
         "Unit": "PCU"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json b/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json
index d70864da5c672..e3227c7f2fe99 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json
@@ -1,269 +1,181 @@
 [
     {
         "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0xe"
     },
     {
         "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0xe"
     },
     {
         "BriefDescription": "Page walks completed due to a demand data store to a 1G page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_ACTIVE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0xe"
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_PENDING",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "DTLB flush attempts of the thread-specific entries",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.DTLB_THREAD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
         "SampleAfterValue": "100007",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "STLB flush attempts",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.STLB_ANY",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
         "SampleAfterValue": "100007",
-        "Speculative": "1",
         "UMask": "0x20"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 8949b58f89be9..7e489749a0d42 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -12,7 +12,7 @@ GenuineIntel-6-7A,v1.01,goldmontplus,core
 GenuineIntel-6-(3C|45|46),v32,haswell,core
 GenuineIntel-6-3F,v26,haswellx,core
 GenuineIntel-6-(7D|7E|A7),v1.15,icelake,core
-GenuineIntel-6-6[AC],v1.16,icelakex,core
+GenuineIntel-6-6[AC],v1.17,icelakex,core
 GenuineIntel-6-3A,v22,ivybridge,core
 GenuineIntel-6-3E,v22,ivytown,core
 GenuineIntel-6-2D,v21,jaketown,core
-- 
GitLab


From d86ac8d7cd31d9fc79aaac26cf2441e2fdfb6f3e Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:54:54 -0800
Subject: [PATCH 578/875] perf vendor events intel: Refresh ivybridge metrics
 and events

Update the ivybridge metrics and events using the new tooling from:

  https://github.com/intel/perfmon

The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1".  The
events are unchanged but the version number is 23 to match the perfmon
version. In the events unused json values are removed. The formatting
changes increase consistency across the json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-8-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../pmu-events/arch/x86/ivybridge/cache.json  | 235 ----------------
 .../arch/x86/ivybridge/floating-point.json    |  34 ---
 .../arch/x86/ivybridge/frontend.json          |  60 -----
 .../arch/x86/ivybridge/ivb-metrics.json       | 119 +++++----
 .../pmu-events/arch/x86/ivybridge/memory.json |  54 ----
 .../pmu-events/arch/x86/ivybridge/other.json  |   8 -
 .../arch/x86/ivybridge/pipeline.json          | 250 ------------------
 .../arch/x86/ivybridge/uncore-cache.json      |  50 ----
 .../arch/x86/ivybridge/uncore-other.json      |  28 +-
 .../arch/x86/ivybridge/virtual-memory.json    |  36 ---
 tools/perf/pmu-events/arch/x86/mapfile.csv    |   2 +-
 11 files changed, 76 insertions(+), 800 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/cache.json b/tools/perf/pmu-events/arch/x86/ivybridge/cache.json
index 8adb2e45e23df..6ddc7d1c61d51 100644
--- a/tools/perf/pmu-events/arch/x86/ivybridge/cache.json
+++ b/tools/perf/pmu-events/arch/x86/ivybridge/cache.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "L1D data line replacements",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x51",
         "EventName": "L1D.REPLACEMENT",
         "PublicDescription": "Counts the number of lines brought into the L1 data cache.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.FB_FULL",
@@ -22,8 +18,6 @@
     },
     {
         "BriefDescription": "L1D miss oustandings duration in cycles",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING",
         "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
@@ -32,8 +26,6 @@
     },
     {
         "BriefDescription": "Cycles with L1D load Misses outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -43,8 +35,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -54,8 +44,6 @@
     },
     {
         "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "L2_L1D_WB_RQSTS.ALL",
         "SampleAfterValue": "200003",
@@ -63,8 +51,6 @@
     },
     {
         "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "L2_L1D_WB_RQSTS.HIT_E",
         "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
@@ -73,8 +59,6 @@
     },
     {
         "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "L2_L1D_WB_RQSTS.HIT_M",
         "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
@@ -83,8 +67,6 @@
     },
     {
         "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "L2_L1D_WB_RQSTS.MISS",
         "PublicDescription": "Not rejected writebacks that missed LLC.",
@@ -93,8 +75,6 @@
     },
     {
         "BriefDescription": "L2 cache lines filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.ALL",
         "PublicDescription": "L2 cache lines filling L2.",
@@ -103,8 +83,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in E state filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.E",
         "PublicDescription": "L2 cache lines in E state filling L2.",
@@ -113,8 +91,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in I state filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.I",
         "PublicDescription": "L2 cache lines in I state filling L2.",
@@ -123,8 +99,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in S state filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.S",
         "PublicDescription": "L2 cache lines in S state filling L2.",
@@ -133,8 +107,6 @@
     },
     {
         "BriefDescription": "Clean L2 cache lines evicted by demand",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
         "PublicDescription": "Clean L2 cache lines evicted by demand.",
@@ -143,8 +115,6 @@
     },
     {
         "BriefDescription": "Dirty L2 cache lines evicted by demand",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
         "PublicDescription": "Dirty L2 cache lines evicted by demand.",
@@ -153,8 +123,6 @@
     },
     {
         "BriefDescription": "Dirty L2 cache lines filling the L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DIRTY_ALL",
         "PublicDescription": "Dirty L2 cache lines filling the L2.",
@@ -163,8 +131,6 @@
     },
     {
         "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.PF_CLEAN",
         "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.",
@@ -173,8 +139,6 @@
     },
     {
         "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.PF_DIRTY",
         "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.",
@@ -183,8 +147,6 @@
     },
     {
         "BriefDescription": "L2 code requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_CODE_RD",
         "PublicDescription": "Counts all L2 code requests.",
@@ -193,8 +155,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
         "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
@@ -203,8 +163,6 @@
     },
     {
         "BriefDescription": "Requests from L2 hardware prefetchers",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_PF",
         "PublicDescription": "Counts all L2 HW prefetcher requests.",
@@ -213,8 +171,6 @@
     },
     {
         "BriefDescription": "RFO requests to L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_RFO",
         "PublicDescription": "Counts all L2 store RFO requests.",
@@ -223,8 +179,6 @@
     },
     {
         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_HIT",
         "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
@@ -233,8 +187,6 @@
     },
     {
         "BriefDescription": "L2 cache misses when fetching instructions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_MISS",
         "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
@@ -243,8 +195,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
         "PublicDescription": "Demand Data Read requests that hit L2 cache.",
@@ -253,8 +203,6 @@
     },
     {
         "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PF_HIT",
         "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
@@ -263,8 +211,6 @@
     },
     {
         "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PF_MISS",
         "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
@@ -273,8 +219,6 @@
     },
     {
         "BriefDescription": "RFO requests that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_HIT",
         "PublicDescription": "RFO requests that hit L2 cache.",
@@ -283,8 +227,6 @@
     },
     {
         "BriefDescription": "RFO requests that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_MISS",
         "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
@@ -293,8 +235,6 @@
     },
     {
         "BriefDescription": "RFOs that access cache lines in any state",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x27",
         "EventName": "L2_STORE_LOCK_RQSTS.ALL",
         "PublicDescription": "RFOs that access cache lines in any state.",
@@ -303,8 +243,6 @@
     },
     {
         "BriefDescription": "RFOs that hit cache lines in M state",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x27",
         "EventName": "L2_STORE_LOCK_RQSTS.HIT_M",
         "PublicDescription": "RFOs that hit cache lines in M state.",
@@ -313,8 +251,6 @@
     },
     {
         "BriefDescription": "RFOs that miss cache lines",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x27",
         "EventName": "L2_STORE_LOCK_RQSTS.MISS",
         "PublicDescription": "RFOs that miss cache lines.",
@@ -323,8 +259,6 @@
     },
     {
         "BriefDescription": "L2 or LLC HW prefetches that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.ALL_PF",
         "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.",
@@ -333,8 +267,6 @@
     },
     {
         "BriefDescription": "Transactions accessing L2 pipe",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.ALL_REQUESTS",
         "PublicDescription": "Transactions accessing L2 pipe.",
@@ -343,8 +275,6 @@
     },
     {
         "BriefDescription": "L2 cache accesses when fetching instructions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.CODE_RD",
         "PublicDescription": "L2 cache accesses when fetching instructions.",
@@ -353,8 +283,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.DEMAND_DATA_RD",
         "PublicDescription": "Demand Data Read requests that access L2 cache.",
@@ -363,8 +291,6 @@
     },
     {
         "BriefDescription": "L1D writebacks that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L1D_WB",
         "PublicDescription": "L1D writebacks that access L2 cache.",
@@ -373,8 +299,6 @@
     },
     {
         "BriefDescription": "L2 fill requests that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L2_FILL",
         "PublicDescription": "L2 fill requests that access L2 cache.",
@@ -383,8 +307,6 @@
     },
     {
         "BriefDescription": "L2 writebacks that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L2_WB",
         "PublicDescription": "L2 writebacks that access L2 cache.",
@@ -393,8 +315,6 @@
     },
     {
         "BriefDescription": "RFO requests that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.RFO",
         "PublicDescription": "RFO requests that access L2 cache.",
@@ -403,8 +323,6 @@
     },
     {
         "BriefDescription": "Cycles when L1D is locked",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x63",
         "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
         "PublicDescription": "Cycles in which the L1D is locked.",
@@ -413,8 +331,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests missed LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.MISS",
         "PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
@@ -423,8 +339,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests that refer to LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
         "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
@@ -433,8 +347,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",
         "PEBS": "1",
@@ -443,8 +355,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",
         "PEBS": "1",
@@ -453,8 +363,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",
         "PEBS": "1",
@@ -463,8 +371,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",
         "PEBS": "1",
@@ -473,8 +379,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD3",
         "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",
         "PublicDescription": "Retired load uops whose data source was local memory (cross-socket snoop not needed or missed).",
@@ -483,8 +387,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
         "PEBS": "1",
@@ -493,8 +395,6 @@
     },
     {
         "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
         "PEBS": "1",
@@ -503,8 +403,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources following L1 data-cache miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
         "PEBS": "1",
@@ -513,8 +411,6 @@
     },
     {
         "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
         "PEBS": "1",
@@ -523,8 +419,6 @@
     },
     {
         "BriefDescription": "Retired load uops with L2 cache misses as data sources.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
         "PEBS": "1",
@@ -533,8 +427,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",
         "PEBS": "1",
@@ -543,8 +435,6 @@
     },
     {
         "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS",
         "PEBS": "1",
@@ -553,8 +443,6 @@
     },
     {
         "BriefDescription": "All retired load uops. (Precise Event)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
         "PEBS": "1",
@@ -563,8 +451,6 @@
     },
     {
         "BriefDescription": "All retired store uops. (Precise Event)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
         "PEBS": "1",
@@ -573,8 +459,6 @@
     },
     {
         "BriefDescription": "Retired load uops with locked access. (Precise Event)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
         "PEBS": "1",
@@ -583,8 +467,6 @@
     },
     {
         "BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
         "PEBS": "1",
@@ -593,8 +475,6 @@
     },
     {
         "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
         "PEBS": "1",
@@ -603,8 +483,6 @@
     },
     {
         "BriefDescription": "Retired load uops that miss the STLB. (Precise Event)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
         "PEBS": "1",
@@ -613,8 +491,6 @@
     },
     {
         "BriefDescription": "Retired store uops that miss the STLB. (Precise Event)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
         "PEBS": "1",
@@ -623,8 +499,6 @@
     },
     {
         "BriefDescription": "Demand and prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
         "PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
@@ -633,8 +507,6 @@
     },
     {
         "BriefDescription": "Cacheable and noncachaeble code read requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
         "PublicDescription": "Demand code read requests sent to uncore.",
@@ -643,8 +515,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests sent to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
         "PublicDescription": "Demand data read requests sent to uncore.",
@@ -653,8 +523,6 @@
     },
     {
         "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
         "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
@@ -663,8 +531,6 @@
     },
     {
         "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB2",
         "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
         "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.",
@@ -673,8 +539,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
         "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
@@ -683,8 +547,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
@@ -694,8 +556,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
@@ -705,8 +565,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
@@ -716,8 +574,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
@@ -727,8 +583,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
         "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
@@ -737,8 +591,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
         "PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
@@ -747,8 +599,6 @@
     },
     {
         "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "6",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
@@ -758,8 +608,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
         "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",
@@ -768,332 +616,249 @@
     },
     {
         "BriefDescription": "Counts all demand & prefetch code reads that hit in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0244",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0244",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x000105B3",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo references (demand & prefetch)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x000107F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00010122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all writebacks from the core to the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10008",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00010004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that hit in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00010001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data reads that hit in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand rfo's",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00010002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x18000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts non-temporal stores",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10800",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Split locks in SQ",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF4",
         "EventName": "SQ_MISC.SPLIT_LOCK",
         "SampleAfterValue": "100003",
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json b/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json
index 4c2ac010cf55d..87c958213c7a7 100644
--- a/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Cycles with any input/output SSE or FP assist",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.ANY",
@@ -12,8 +10,6 @@
     },
     {
         "BriefDescription": "Number of SIMD FP assists due to input values",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.SIMD_INPUT",
         "PublicDescription": "Number of SIMD FP assists due to input values.",
@@ -22,8 +18,6 @@
     },
     {
         "BriefDescription": "Number of SIMD FP assists due to Output values",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.SIMD_OUTPUT",
         "PublicDescription": "Number of SIMD FP assists due to output values.",
@@ -32,8 +26,6 @@
     },
     {
         "BriefDescription": "Number of X87 assists due to input value.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.X87_INPUT",
         "PublicDescription": "Number of X87 FP assists due to input values.",
@@ -42,8 +34,6 @@
     },
     {
         "BriefDescription": "Number of X87 assists due to output value.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.X87_OUTPUT",
         "PublicDescription": "Number of X87 FP assists due to output values.",
@@ -52,8 +42,6 @@
     },
     {
         "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",
         "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",
@@ -62,8 +50,6 @@
     },
     {
         "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",
         "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",
@@ -72,8 +58,6 @@
     },
     {
         "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",
         "PublicDescription": "Counts number of SSE* or AVX-128 double precision FP scalar uops executed.",
@@ -82,8 +66,6 @@
     },
     {
         "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",
         "PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",
@@ -92,8 +74,6 @@
     },
     {
         "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.X87",
         "PublicDescription": "Counts number of X87 uops executed.",
@@ -102,8 +82,6 @@
     },
     {
         "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
         "SampleAfterValue": "1000003",
@@ -111,8 +89,6 @@
     },
     {
         "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
         "SampleAfterValue": "1000003",
@@ -120,8 +96,6 @@
     },
     {
         "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.AVX_STORE",
         "PublicDescription": "Number of assists associated with 256-bit AVX store operations.",
@@ -130,8 +104,6 @@
     },
     {
         "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.AVX_TO_SSE",
         "SampleAfterValue": "100003",
@@ -139,8 +111,6 @@
     },
     {
         "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.SSE_TO_AVX",
         "SampleAfterValue": "100003",
@@ -148,8 +118,6 @@
     },
     {
         "BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x11",
         "EventName": "SIMD_FP_256.PACKED_DOUBLE",
         "PublicDescription": "Counts 256-bit packed double-precision floating-point instructions.",
@@ -158,8 +126,6 @@
     },
     {
         "BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x11",
         "EventName": "SIMD_FP_256.PACKED_SINGLE",
         "PublicDescription": "Counts 256-bit packed single-precision floating-point instructions.",
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json b/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json
index 2b1a82dd86abc..89004a6c9ed1a 100644
--- a/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xE6",
         "EventName": "BACLEARS.ANY",
         "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAB",
         "EventName": "DSB2MITE_SWITCHES.COUNT",
         "PublicDescription": "Number of DSB to MITE switches.",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAB",
         "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
         "PublicDescription": "Cycles DSB to MITE switches caused delay.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAC",
         "EventName": "DSB_FILL.EXCEED_DSB_LINES",
         "PublicDescription": "DSB Fill encountered > 3 DSB lines.",
@@ -41,8 +33,6 @@
     },
     {
         "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.HIT",
         "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
@@ -51,8 +41,6 @@
     },
     {
         "BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.IFETCH_STALL",
         "PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.",
@@ -61,8 +49,6 @@
     },
     {
         "BriefDescription": "Instruction cache, streaming buffer and victim cache misses",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.MISSES",
         "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.",
@@ -71,8 +57,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -82,8 +66,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -93,8 +75,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering 4 Uops",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -104,8 +84,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering any Uop",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -115,8 +93,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_CYCLES",
@@ -126,8 +102,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_UOPS",
         "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
@@ -136,8 +110,6 @@
     },
     {
         "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0x79",
         "EventName": "IDQ.EMPTY",
         "PublicDescription": "Counts cycles the IDQ is empty.",
@@ -146,8 +118,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_ALL_UOPS",
         "PublicDescription": "Number of uops delivered to IDQ from any path.",
@@ -156,8 +126,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_CYCLES",
@@ -167,8 +135,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_UOPS",
         "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",
@@ -177,8 +143,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_CYCLES",
@@ -188,8 +152,6 @@
     },
     {
         "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_DSB_CYCLES",
@@ -199,8 +161,6 @@
     },
     {
         "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
@@ -211,8 +171,6 @@
     },
     {
         "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_DSB_UOPS",
         "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
@@ -221,8 +179,6 @@
     },
     {
         "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_MITE_UOPS",
         "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
@@ -231,8 +187,6 @@
     },
     {
         "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
@@ -243,8 +197,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_UOPS",
         "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.",
@@ -253,8 +205,6 @@
     },
     {
         "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
         "PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.",
@@ -263,8 +213,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -273,8 +221,6 @@
     },
     {
         "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@@ -284,8 +230,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "3",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@@ -294,8 +238,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@@ -304,8 +246,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json b/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json
index 63db3397af0f9..88980c1a3a643 100644
--- a/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json
@@ -88,7 +88,7 @@
     },
     {
         "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
-        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
         "MetricGroup": "TopdownL1;tma_L1_group",
         "MetricName": "tma_bad_speculation",
         "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
@@ -96,7 +96,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
-        "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
+        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
         "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
         "MetricName": "tma_branch_mispredicts",
         "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
@@ -120,7 +120,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
-        "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB)) * tma_backend_bound",
+        "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) * tma_backend_bound",
         "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
         "MetricName": "tma_memory_bound",
         "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@@ -152,7 +152,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
-        "MetricExpr": "(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
+        "MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
         "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
         "MetricName": "tma_lock_latency",
         "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS",
@@ -192,7 +192,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
-        "MetricExpr": "(MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
+        "MetricExpr": "MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
         "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_l3_bound",
         "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
@@ -200,7 +200,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
-        "MetricExpr": "(60 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) + 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.LLC_MISS)))) / CLKS",
+        "MetricExpr": "(60 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) + 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS)))) / CLKS",
         "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_contested_accesses",
         "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
@@ -208,7 +208,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
-        "MetricExpr": "43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) / CLKS",
+        "MetricExpr": "43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) / CLKS",
         "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_data_sharing",
         "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
@@ -216,7 +216,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
-        "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.LLC_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) / CLKS",
+        "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.LLC_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) / CLKS",
         "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_l3_hit_latency",
         "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
@@ -224,7 +224,7 @@
     },
     {
         "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
-        "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
+        "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
         "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_sq_full",
         "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
@@ -232,7 +232,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
-        "MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS))) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
+        "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
         "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_dram_bound",
         "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS",
@@ -264,7 +264,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
-        "MetricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES))) + (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
+        "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
         "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
         "MetricName": "tma_store_latency",
         "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
@@ -312,7 +312,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
-        "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / CLKS",
+        "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / CLKS",
         "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
         "MetricName": "tma_ports_utilization",
         "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@@ -320,7 +320,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@) / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else 0) / CORE_CLKS",
+        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) / CORE_CLKS)",
         "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
         "MetricName": "tma_ports_utilized_0",
         "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
@@ -328,7 +328,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS",
+        "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS)",
         "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
         "MetricName": "tma_ports_utilized_1",
         "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
@@ -336,7 +336,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
+        "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS)",
         "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
         "MetricName": "tma_ports_utilized_2",
         "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
@@ -344,7 +344,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
-        "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
+        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
         "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
         "MetricName": "tma_ports_utilized_3m",
         "ScaleUnit": "100%"
@@ -400,7 +400,7 @@
     },
     {
         "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
+        "MetricExpr": "tma_port_4",
         "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
         "MetricName": "tma_store_op_utilization",
         "ScaleUnit": "100%"
@@ -470,7 +470,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
-        "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
         "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
         "MetricName": "tma_microcode_sequencer",
         "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
@@ -543,19 +543,19 @@
     },
     {
         "BriefDescription": "Floating Point Operations Per Cycle",
-        "MetricExpr": "(1 * (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / CORE_CLKS",
+        "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / CORE_CLKS",
         "MetricGroup": "Flops;Ret",
         "MetricName": "FLOPc"
     },
     {
         "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
         "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
         "MetricName": "ILP"
     },
     {
         "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
-        "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
+        "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
         "MetricGroup": "SMT",
         "MetricName": "CORE_CLKS"
     },
@@ -622,7 +622,7 @@
     },
     {
         "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
-        "MetricExpr": "IDQ.DSB_UOPS / ((IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS))",
+        "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
         "MetricGroup": "DSB;Fed;FetchBW",
         "MetricName": "DSB_Coverage"
     },
@@ -634,7 +634,7 @@
     },
     {
         "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
-        "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb)",
+        "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)",
         "MetricGroup": "Mem;MemoryBound;MemoryLat",
         "MetricName": "Load_Miss_Real_Latency"
     },
@@ -646,19 +646,19 @@
     },
     {
         "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L1MPKI"
     },
     {
         "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
         "MetricGroup": "Backend;CacheMisses;Mem",
         "MetricName": "L2MPKI"
     },
     {
         "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L3MPKI"
     },
@@ -671,19 +671,19 @@
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
-        "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
+        "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L1D_Cache_Fill_BW"
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
-        "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
+        "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L2_Cache_Fill_BW"
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
+        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L3_Cache_Fill_BW"
     },
@@ -713,19 +713,19 @@
     },
     {
         "BriefDescription": "Average CPU Utilization",
-        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
+        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
         "MetricGroup": "HPC;Summary",
         "MetricName": "CPU_Utilization"
     },
     {
         "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
-        "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
+        "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
         "MetricGroup": "Power;Summary",
         "MetricName": "Average_Frequency"
     },
     {
         "BriefDescription": "Giga Floating Point Operations Per Second",
-        "MetricExpr": "((1 * (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1000000000) / duration_time",
+        "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1e9 / duration_time",
         "MetricGroup": "Cor;Flops;HPC",
         "MetricName": "GFLOPs",
         "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
@@ -738,7 +738,7 @@
     },
     {
         "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
-        "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
+        "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
         "MetricGroup": "SMT",
         "MetricName": "SMT_2T_Utilization"
     },
@@ -756,68 +756,87 @@
     },
     {
         "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
-        "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1000000 / duration_time / 1000",
+        "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3",
         "MetricGroup": "HPC;Mem;MemoryBW;SoC",
         "MetricName": "DRAM_BW_Use"
     },
     {
         "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)",
-        "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
+        "MetricExpr": "MEM_Parallel_Requests",
         "MetricGroup": "Mem;SoC",
         "MetricName": "MEM_Request_Latency"
     },
     {
         "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests",
-        "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
+        "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL",
         "MetricGroup": "Mem;SoC",
         "MetricName": "MEM_Parallel_Requests"
     },
+    {
+        "BriefDescription": "Socket actual clocks when any core is active on that socket",
+        "MetricExpr": "UNC_CLOCK.SOCKET",
+        "MetricGroup": "SoC",
+        "MetricName": "Socket_CLKS"
+    },
     {
         "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
         "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
         "MetricGroup": "Branches;OS",
         "MetricName": "IpFarBranch"
     },
+    {
+        "BriefDescription": "Uncore frequency per die [GHZ]",
+        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+        "MetricGroup": "SoC",
+        "MetricName": "UNCORE_FREQ"
+    },
     {
         "BriefDescription": "C3 residency percent per core",
-        "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C3_Core_Residency"
+        "MetricName": "C3_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C6 residency percent per core",
-        "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C6_Core_Residency"
+        "MetricName": "C6_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C7 residency percent per core",
-        "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C7_Core_Residency"
+        "MetricName": "C7_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C2 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C2_Pkg_Residency"
+        "MetricName": "C2_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C3 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C3_Pkg_Residency"
+        "MetricName": "C3_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C6 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C6_Pkg_Residency"
+        "MetricName": "C6_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C7 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C7_Pkg_Residency"
+        "MetricName": "C7_Pkg_Residency",
+        "ScaleUnit": "100%"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/memory.json b/tools/perf/pmu-events/arch/x86/ivybridge/memory.json
index 30fc0af61eb37..fd1fe491c577b 100644
--- a/tools/perf/pmu-events/arch/x86/ivybridge/memory.json
+++ b/tools/perf/pmu-events/arch/x86/ivybridge/memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
         "SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
     },
     {
         "BriefDescription": "Loads with latency value being above 128",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
         "MSRIndex": "0x3F6",
@@ -19,13 +15,10 @@
         "PEBS": "2",
         "PublicDescription": "Loads with latency value being above 128.",
         "SampleAfterValue": "1009",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 16",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
         "MSRIndex": "0x3F6",
@@ -33,13 +26,10 @@
         "PEBS": "2",
         "PublicDescription": "Loads with latency value being above 16.",
         "SampleAfterValue": "20011",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 256",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
         "MSRIndex": "0x3F6",
@@ -47,13 +37,10 @@
         "PEBS": "2",
         "PublicDescription": "Loads with latency value being above 256.",
         "SampleAfterValue": "503",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 32",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
         "MSRIndex": "0x3F6",
@@ -61,13 +48,10 @@
         "PEBS": "2",
         "PublicDescription": "Loads with latency value being above 32.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 4",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
         "MSRIndex": "0x3F6",
@@ -75,13 +59,10 @@
         "PEBS": "2",
         "PublicDescription": "Loads with latency value being above 4.",
         "SampleAfterValue": "100003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 512",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
         "MSRIndex": "0x3F6",
@@ -89,13 +70,10 @@
         "PEBS": "2",
         "PublicDescription": "Loads with latency value being above 512.",
         "SampleAfterValue": "101",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 64",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
         "MSRIndex": "0x3F6",
@@ -103,13 +81,10 @@
         "PEBS": "2",
         "PublicDescription": "Loads with latency value being above 64.",
         "SampleAfterValue": "2003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 8",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
         "MSRIndex": "0x3F6",
@@ -117,25 +92,18 @@
         "PEBS": "2",
         "PublicDescription": "Loads with latency value being above 8.",
         "SampleAfterValue": "50021",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
         "PEBS": "2",
-        "PRECISE_STORE": "1",
         "SampleAfterValue": "2000003",
-        "TakenAlone": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x05",
         "EventName": "MISALIGN_MEM_REF.LOADS",
         "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.",
@@ -144,8 +112,6 @@
     },
     {
         "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x05",
         "EventName": "MISALIGN_MEM_REF.STORES",
         "PublicDescription": "Speculative cache-line split Store-address uops dispatched to L1D.",
@@ -154,80 +120,60 @@
     },
     {
         "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC  and the data returned from dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x300400244",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC  and the data returned from dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x300400091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3004003f7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts LLC replacements",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x6004001b3",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x300400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x300400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of any page walk that had a miss in LLC.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBE",
         "EventName": "PAGE_WALKS.LLC_MISS",
         "SampleAfterValue": "100003",
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/other.json b/tools/perf/pmu-events/arch/x86/ivybridge/other.json
index 2d62521791d8c..e80e99d064ba5 100644
--- a/tools/perf/pmu-events/arch/x86/ivybridge/other.json
+++ b/tools/perf/pmu-events/arch/x86/ivybridge/other.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5C",
         "EventName": "CPL_CYCLES.RING0",
         "PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5C",
@@ -23,8 +19,6 @@
     },
     {
         "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5C",
         "EventName": "CPL_CYCLES.RING123",
         "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
@@ -33,8 +27,6 @@
     },
     {
         "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x63",
         "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
         "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json b/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json
index d89d3f8db1905..d1e64e0d683e4 100644
--- a/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Divide operations executed",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x14",
@@ -13,8 +11,6 @@
     },
     {
         "BriefDescription": "Cycles when divider is busy executing divide operations",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x14",
         "EventName": "ARITH.FPU_DIV_ACTIVE",
         "PublicDescription": "Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides.",
@@ -23,8 +19,6 @@
     },
     {
         "BriefDescription": "Speculative and retired  branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_BRANCHES",
         "PublicDescription": "Counts all near executed branches (not necessarily retired).",
@@ -33,8 +27,6 @@
     },
     {
         "BriefDescription": "Speculative and retired macro-conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
         "PublicDescription": "Speculative and retired macro-conditional branches.",
@@ -43,8 +35,6 @@
     },
     {
         "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
         "PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.",
@@ -53,8 +43,6 @@
     },
     {
         "BriefDescription": "Speculative and retired direct near calls",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
         "PublicDescription": "Speculative and retired direct near calls.",
@@ -63,8 +51,6 @@
     },
     {
         "BriefDescription": "Speculative and retired indirect branches excluding calls and returns",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
         "PublicDescription": "Speculative and retired indirect branches excluding calls and returns.",
@@ -73,8 +59,6 @@
     },
     {
         "BriefDescription": "Speculative and retired indirect return branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
         "SampleAfterValue": "200003",
@@ -82,8 +66,6 @@
     },
     {
         "BriefDescription": "Not taken macro-conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
         "PublicDescription": "Not taken macro-conditional branches.",
@@ -92,8 +74,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired macro-conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
         "PublicDescription": "Taken speculative and retired macro-conditional branches.",
@@ -102,8 +82,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
         "PublicDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.",
@@ -112,8 +90,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired direct near calls",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
         "PublicDescription": "Taken speculative and retired direct near calls.",
@@ -122,8 +98,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
         "PublicDescription": "Taken speculative and retired indirect branches excluding calls and returns.",
@@ -132,8 +106,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect calls",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
         "PublicDescription": "Taken speculative and retired indirect calls.",
@@ -142,8 +114,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
         "PublicDescription": "Taken speculative and retired indirect branches with return mnemonic.",
@@ -152,8 +122,6 @@
     },
     {
         "BriefDescription": "All (macro) branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "PublicDescription": "Branch instructions at retirement.",
@@ -161,8 +129,6 @@
     },
     {
         "BriefDescription": "All (macro) branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
         "PEBS": "2",
@@ -171,8 +137,6 @@
     },
     {
         "BriefDescription": "Conditional branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -181,8 +145,6 @@
     },
     {
         "BriefDescription": "Far branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.FAR_BRANCH",
         "PublicDescription": "Number of far branches retired.",
@@ -191,8 +153,6 @@
     },
     {
         "BriefDescription": "Direct and indirect near call instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -201,8 +161,6 @@
     },
     {
         "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
         "PEBS": "1",
@@ -211,8 +169,6 @@
     },
     {
         "BriefDescription": "Return instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_RETURN",
         "PEBS": "1",
@@ -221,8 +177,6 @@
     },
     {
         "BriefDescription": "Taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
@@ -231,8 +185,6 @@
     },
     {
         "BriefDescription": "Not taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NOT_TAKEN",
         "PublicDescription": "Counts the number of not taken branch instructions retired.",
@@ -241,8 +193,6 @@
     },
     {
         "BriefDescription": "Speculative and retired mispredicted macro conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_BRANCHES",
         "PublicDescription": "Counts all near executed branches (not necessarily retired).",
@@ -251,8 +201,6 @@
     },
     {
         "BriefDescription": "Speculative and retired mispredicted macro conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
         "PublicDescription": "Speculative and retired mispredicted macro conditional branches.",
@@ -261,8 +209,6 @@
     },
     {
         "BriefDescription": "Mispredicted indirect branches excluding calls and returns",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
         "PublicDescription": "Mispredicted indirect branches excluding calls and returns.",
@@ -271,8 +217,6 @@
     },
     {
         "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
         "PublicDescription": "Not taken speculative and retired mispredicted macro conditional branches.",
@@ -281,8 +225,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
         "PublicDescription": "Taken speculative and retired mispredicted macro conditional branches.",
@@ -291,8 +233,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
         "PublicDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.",
@@ -301,8 +241,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect calls",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
         "PublicDescription": "Taken speculative and retired mispredicted indirect calls.",
@@ -311,8 +249,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
         "PublicDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.",
@@ -321,8 +257,6 @@
     },
     {
         "BriefDescription": "All mispredicted macro branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PublicDescription": "Mispredicted branch instructions at retirement.",
@@ -330,8 +264,6 @@
     },
     {
         "BriefDescription": "Mispredicted macro branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
         "PEBS": "2",
@@ -340,8 +272,6 @@
     },
     {
         "BriefDescription": "Mispredicted conditional branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -350,8 +280,6 @@
     },
     {
         "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
@@ -360,8 +288,6 @@
     },
     {
         "BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "2000003",
@@ -369,8 +295,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
         "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.",
@@ -380,8 +304,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
         "SampleAfterValue": "2000003",
@@ -389,8 +311,6 @@
     },
     {
         "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "2000003",
@@ -398,16 +318,12 @@
     },
     {
         "BriefDescription": "Reference cycles when the core is not in halt state.",
-        "Counter": "Fixed counter 2",
-        "CounterHTOff": "Fixed counter 2",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
         "SampleAfterValue": "2000003",
         "UMask": "0x3"
     },
     {
         "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
         "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)",
@@ -417,8 +333,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
         "SampleAfterValue": "2000003",
@@ -426,8 +340,6 @@
     },
     {
         "BriefDescription": "Core cycles when the thread is not in halt state.",
-        "Counter": "Fixed counter 1",
-        "CounterHTOff": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
@@ -435,8 +347,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",
-        "Counter": "Fixed counter 1",
-        "CounterHTOff": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
         "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
         "SampleAfterValue": "2000003",
@@ -444,8 +354,6 @@
     },
     {
         "BriefDescription": "Thread cycles when thread is not in halt state",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
         "PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.",
@@ -454,8 +362,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
         "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
@@ -463,8 +369,6 @@
     },
     {
         "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "8",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
@@ -473,8 +377,6 @@
     },
     {
         "BriefDescription": "Cycles with pending L1 cache miss loads.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "8",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
@@ -484,8 +386,6 @@
     },
     {
         "BriefDescription": "Cycles while L2 cache miss load* is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
@@ -494,8 +394,6 @@
     },
     {
         "BriefDescription": "Cycles with pending L2 cache miss loads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
@@ -505,8 +403,6 @@
     },
     {
         "BriefDescription": "Cycles with pending memory loads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
@@ -516,8 +412,6 @@
     },
     {
         "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
@@ -526,8 +420,6 @@
     },
     {
         "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
@@ -537,8 +429,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "12",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
@@ -547,8 +437,6 @@
     },
     {
         "BriefDescription": "Execution stalls due to L1 data cache misses",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "12",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
@@ -558,8 +446,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L2 cache miss load* is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "5",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
@@ -568,8 +454,6 @@
     },
     {
         "BriefDescription": "Execution stalls due to L2 cache misses.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "5",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
@@ -579,8 +463,6 @@
     },
     {
         "BriefDescription": "Execution stalls due to memory subsystem.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "6",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",
@@ -589,8 +471,6 @@
     },
     {
         "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "6",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
@@ -599,8 +479,6 @@
     },
     {
         "BriefDescription": "Total execution stalls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
@@ -609,8 +487,6 @@
     },
     {
         "BriefDescription": "Stall cycles because IQ is full",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.IQ_FULL",
         "PublicDescription": "Stall cycles due to IQ is full.",
@@ -619,8 +495,6 @@
     },
     {
         "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.LCP",
         "SampleAfterValue": "2000003",
@@ -628,16 +502,12 @@
     },
     {
         "BriefDescription": "Instructions retired from execution.",
-        "Counter": "Fixed counter 0",
-        "CounterHTOff": "Fixed counter 0",
         "EventName": "INST_RETIRED.ANY",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of instructions retired. General Counter   - architectural event",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.ANY_P",
         "PublicDescription": "Number of instructions at retirement.",
@@ -645,8 +515,6 @@
     },
     {
         "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
-        "Counter": "1",
-        "CounterHTOff": "1",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.PREC_DIST",
         "PEBS": "2",
@@ -656,8 +524,6 @@
     },
     {
         "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES",
@@ -667,8 +533,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
@@ -677,8 +541,6 @@
     },
     {
         "BriefDescription": "Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x0D",
@@ -688,8 +550,6 @@
     },
     {
         "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.NO_SR",
         "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
@@ -698,8 +558,6 @@
     },
     {
         "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.STORE_FORWARD",
         "PublicDescription": "Loads blocked by overlapping with store buffer that cannot be forwarded.",
@@ -708,8 +566,6 @@
     },
     {
         "BriefDescription": "False dependencies in MOB due to partial compare on address",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x07",
         "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
         "PublicDescription": "False dependencies in MOB due to partial compare on address.",
@@ -718,8 +574,6 @@
     },
     {
         "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4C",
         "EventName": "LOAD_HIT_PRE.HW_PF",
         "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.",
@@ -728,8 +582,6 @@
     },
     {
         "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4C",
         "EventName": "LOAD_HIT_PRE.SW_PF",
         "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.",
@@ -738,8 +590,6 @@
     },
     {
         "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_4_UOPS",
@@ -749,8 +599,6 @@
     },
     {
         "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_ACTIVE",
@@ -760,8 +608,6 @@
     },
     {
         "BriefDescription": "Number of Uops delivered by the LSD.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA8",
         "EventName": "LSD.UOPS",
         "SampleAfterValue": "2000003",
@@ -769,8 +615,6 @@
     },
     {
         "BriefDescription": "Number of machine clears (nukes) of any type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xC3",
@@ -780,8 +624,6 @@
     },
     {
         "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MASKMOV",
         "PublicDescription": "Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
@@ -790,8 +632,6 @@
     },
     {
         "BriefDescription": "Self-modifying code (SMC) detected.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.SMC",
         "PublicDescription": "Number of self-modifying-code machine clears detected.",
@@ -800,8 +640,6 @@
     },
     {
         "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.INT_ELIMINATED",
         "SampleAfterValue": "1000003",
@@ -809,8 +647,6 @@
     },
     {
         "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",
         "SampleAfterValue": "1000003",
@@ -818,8 +654,6 @@
     },
     {
         "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",
         "SampleAfterValue": "100003",
@@ -827,8 +661,6 @@
     },
     {
         "BriefDescription": "Resource-related stall cycles",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ANY",
         "PublicDescription": "Cycles Allocation is stalled due to Resource Related reason.",
@@ -837,8 +669,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to re-order buffer full.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ROB",
         "SampleAfterValue": "2000003",
@@ -846,8 +676,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no eligible RS entry available.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.RS",
         "SampleAfterValue": "2000003",
@@ -855,8 +683,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.SB",
         "PublicDescription": "Cycles stalled due to no store buffers available (not including draining form sync).",
@@ -865,8 +691,6 @@
     },
     {
         "BriefDescription": "Count cases of saving new LBR",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCC",
         "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
         "PublicDescription": "Count cases of saving new LBR records by hardware.",
@@ -875,8 +699,6 @@
     },
     {
         "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5E",
         "EventName": "RS_EVENTS.EMPTY_CYCLES",
         "PublicDescription": "Cycles the RS is empty for the thread.",
@@ -885,8 +707,6 @@
     },
     {
         "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5E",
@@ -897,8 +717,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are dispatched to port 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_0",
         "PublicDescription": "Cycles which a Uop is dispatched on port 0.",
@@ -908,8 +726,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE",
         "PublicDescription": "Cycles per core when uops are dispatched to port 0.",
@@ -918,8 +734,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are dispatched to port 1",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_1",
         "PublicDescription": "Cycles which a Uop is dispatched on port 1.",
@@ -929,8 +743,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 1",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE",
         "PublicDescription": "Cycles per core when uops are dispatched to port 1.",
@@ -939,8 +751,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_2",
         "PublicDescription": "Cycles which a Uop is dispatched on port 2.",
@@ -950,8 +760,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops dispatched to port 2, loads and stores per core (speculative and retired).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE",
         "SampleAfterValue": "2000003",
@@ -959,8 +767,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_3",
         "PublicDescription": "Cycles which a Uop is dispatched on port 3.",
@@ -970,8 +776,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE",
         "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3.",
@@ -980,8 +784,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are dispatched to port 4",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_4",
         "PublicDescription": "Cycles which a Uop is dispatched on port 4.",
@@ -991,8 +793,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 4",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE",
         "PublicDescription": "Cycles per core when uops are dispatched to port 4.",
@@ -1001,8 +801,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are dispatched to port 5",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_5",
         "PublicDescription": "Cycles which a Uop is dispatched on port 5.",
@@ -1012,8 +810,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 5",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE",
         "PublicDescription": "Cycles per core when uops are dispatched to port 5.",
@@ -1022,8 +818,6 @@
     },
     {
         "BriefDescription": "Number of uops executed on the core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE",
         "PublicDescription": "Counts total number of uops to be executed per-core each cycle.",
@@ -1032,8 +826,6 @@
     },
     {
         "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@@ -1043,8 +835,6 @@
     },
     {
         "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@@ -1054,8 +844,6 @@
     },
     {
         "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@@ -1065,8 +853,6 @@
     },
     {
         "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@@ -1076,8 +862,6 @@
     },
     {
         "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
         "Invert": "1",
@@ -1087,8 +871,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
@@ -1098,8 +880,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
@@ -1109,8 +889,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
@@ -1120,8 +898,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
@@ -1131,8 +907,6 @@
     },
     {
         "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.STALL_CYCLES",
@@ -1142,8 +916,6 @@
     },
     {
         "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.THREAD",
         "PublicDescription": "Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles.",
@@ -1152,8 +924,6 @@
     },
     {
         "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.ANY",
         "PublicDescription": "Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.",
@@ -1163,8 +933,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -1175,8 +943,6 @@
     },
     {
         "BriefDescription": "Number of flags-merge uops being allocated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.FLAGS_MERGE",
         "PublicDescription": "Number of flags-merge uops allocated. Such uops adds delay.",
@@ -1185,8 +951,6 @@
     },
     {
         "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.SINGLE_MUL",
         "PublicDescription": "Number of multiply packed/scalar single precision uops allocated.",
@@ -1195,8 +959,6 @@
     },
     {
         "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.SLOW_LEA",
         "PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
@@ -1205,8 +967,6 @@
     },
     {
         "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -1217,8 +977,6 @@
     },
     {
         "BriefDescription": "Retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ALL",
         "PEBS": "1",
@@ -1228,8 +986,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles without actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",
@@ -1239,8 +995,6 @@
     },
     {
         "BriefDescription": "Retirement slots used.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
         "PEBS": "1",
@@ -1249,8 +1003,6 @@
     },
     {
         "BriefDescription": "Cycles without actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -1260,8 +1012,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 10 actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "10",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json
index 6b0639944d78f..c538557ba4c09 100644
--- a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json
@@ -1,251 +1,201 @@
 [
     {
         "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
         "UMask": "0x86",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
         "UMask": "0x88",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
         "UMask": "0x81",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
         "UMask": "0x8f",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
         "UMask": "0x46",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
         "UMask": "0x48",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
         "UMask": "0x41",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
         "UMask": "0x4f",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
         "UMask": "0x16",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup read request that access cache and found line in I-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",
         "UMask": "0x18",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup read request that access cache and found line in M-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup read request that access cache and found line in M-state.",
         "UMask": "0x11",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
         "UMask": "0x1f",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
         "UMask": "0x26",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup write request that access cache and found line in I-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup write request that access cache and found line in I-state.",
         "UMask": "0x28",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup write request that access cache and found line in M-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",
         "UMask": "0x21",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
         "UMask": "0x2f",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
         "UMask": "0x88",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "An external snoop hits a modified line in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL",
         "PerPkg": "1",
-        "PublicDescription": "An external snoop hits a modified line in some processor core.",
         "UMask": "0x28",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
         "UMask": "0x48",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
         "UMask": "0x84",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "An external snoop hits a non-modified line in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL",
         "PerPkg": "1",
-        "PublicDescription": "An external snoop hits a non-modified line in some processor core.",
         "UMask": "0x24",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
         "UMask": "0x44",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
         "UMask": "0x81",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "An external snoop misses in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL",
         "PerPkg": "1",
-        "PublicDescription": "An external snoop misses in some processor core.",
         "UMask": "0x21",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
         "UMask": "0x41",
         "Unit": "CBO"
     }
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json
index 88f1e326205fa..c3252c094a9cc 100644
--- a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json
@@ -4,18 +4,15 @@
         "EventCode": "0x83",
         "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "PublicDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Number of requests allocated in Coherency Tracker.",
-        "Counter": "0,1",
         "EventCode": "0x84",
         "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
         "PerPkg": "1",
-        "PublicDescription": "Number of requests allocated in Coherency Tracker.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
@@ -23,69 +20,56 @@
         "EventCode": "0x80",
         "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "PublicDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
-        "Counter": "0,1",
         "CounterMask": "10",
         "EventCode": "0x80",
         "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL",
         "PerPkg": "1",
-        "PublicDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
-        "Counter": "0,1",
         "CounterMask": "1",
         "EventCode": "0x80",
         "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
         "PerPkg": "1",
-        "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
-        "Counter": "0,1",
         "EventCode": "0x81",
         "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
         "PerPkg": "1",
-        "PublicDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Counts the number of LLC evictions allocated.",
-        "Counter": "0,1",
         "EventCode": "0x81",
         "EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS",
         "PerPkg": "1",
-        "PublicDescription": "Counts the number of LLC evictions allocated.",
         "UMask": "0x80",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
-        "Counter": "0,1",
         "EventCode": "0x81",
         "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
         "PerPkg": "1",
-        "PublicDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
         "UMask": "0x20",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
-        "Counter": "Fixed",
         "EventCode": "0xff",
         "EventName": "UNC_CLOCK.SOCKET",
         "PerPkg": "1",
-        "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
         "Unit": "ARB"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json b/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json
index a5e387bbb1345..b97f15cb20fcb 100644
--- a/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Page walk for a large page completed for Demand load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED",
         "SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
     },
     {
         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
         "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand loads.",
@@ -20,8 +16,6 @@
     },
     {
         "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5F",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
         "PublicDescription": "Counts load operations that missed 1st level DTLB but hit the 2nd level.",
@@ -30,8 +24,6 @@
     },
     {
         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
         "PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by demand loads.",
@@ -40,8 +32,6 @@
     },
     {
         "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
         "PublicDescription": "Cycle PMH is busy with a walk due to demand loads.",
@@ -50,8 +40,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
         "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
@@ -60,8 +48,6 @@
     },
     {
         "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT",
         "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
@@ -70,8 +56,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
         "PublicDescription": "Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G).",
@@ -80,8 +64,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_DURATION",
         "PublicDescription": "Cycles PMH is busy with this walk.",
@@ -90,8 +72,6 @@
     },
     {
         "BriefDescription": "Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4F",
         "EventName": "EPT.WALK_CYCLES",
         "SampleAfterValue": "2000003",
@@ -99,8 +79,6 @@
     },
     {
         "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAE",
         "EventName": "ITLB.ITLB_FLUSH",
         "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.",
@@ -109,8 +87,6 @@
     },
     {
         "BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED",
         "PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.",
@@ -119,8 +95,6 @@
     },
     {
         "BriefDescription": "Misses at all ITLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
         "PublicDescription": "Misses in all ITLB levels that cause page walks.",
@@ -129,8 +103,6 @@
     },
     {
         "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT",
         "PublicDescription": "Number of cache load STLB hits. No page walk.",
@@ -139,8 +111,6 @@
     },
     {
         "BriefDescription": "Misses in all ITLB levels that cause completed page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
         "PublicDescription": "Misses in all ITLB levels that cause completed page walks.",
@@ -149,8 +119,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_DURATION",
         "PublicDescription": "Cycle PMH is busy with a walk.",
@@ -159,8 +127,6 @@
     },
     {
         "BriefDescription": "DTLB flush attempts of the thread-specific entries",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.DTLB_THREAD",
         "PublicDescription": "DTLB flush attempts of the thread-specific entries.",
@@ -169,8 +135,6 @@
     },
     {
         "BriefDescription": "STLB flush attempts",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.STLB_ANY",
         "PublicDescription": "Count number of STLB flush attempts.",
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 7e489749a0d42..de3f9dd4e6f73 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -13,7 +13,7 @@ GenuineIntel-6-(3C|45|46),v32,haswell,core
 GenuineIntel-6-3F,v26,haswellx,core
 GenuineIntel-6-(7D|7E|A7),v1.15,icelake,core
 GenuineIntel-6-6[AC],v1.17,icelakex,core
-GenuineIntel-6-3A,v22,ivybridge,core
+GenuineIntel-6-3A,v23,ivybridge,core
 GenuineIntel-6-3E,v22,ivytown,core
 GenuineIntel-6-2D,v21,jaketown,core
 GenuineIntel-6-(57|85),v9,knightslanding,core
-- 
GitLab


From 8ee37818a0574fac9d42344595236099c153a494 Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:54:55 -0800
Subject: [PATCH 579/875] perf vendor events intel: Refresh ivytown metrics and
 events

Update the ivytown metrics and events using the new tooling from:

  https://github.com/intel/perfmon

The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1".  The
events are unchanged but unused json values are removed. The
formatting changes increase consistency across the json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-9-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../pmu-events/arch/x86/ivytown/cache.json    | 274 ----------
 .../arch/x86/ivytown/floating-point.json      |  34 --
 .../pmu-events/arch/x86/ivytown/frontend.json |  60 ---
 .../arch/x86/ivytown/ivt-metrics.json         | 133 +++--
 .../pmu-events/arch/x86/ivytown/memory.json   | 121 -----
 .../pmu-events/arch/x86/ivytown/other.json    |   8 -
 .../pmu-events/arch/x86/ivytown/pipeline.json | 250 ---------
 .../arch/x86/ivytown/uncore-cache.json        | 388 ++------------
 .../arch/x86/ivytown/uncore-interconnect.json | 505 +++++++-----------
 .../arch/x86/ivytown/uncore-memory.json       | 209 +-------
 .../arch/x86/ivytown/uncore-other.json        | 254 +--------
 .../arch/x86/ivytown/uncore-power.json        |  95 ----
 .../arch/x86/ivytown/virtual-memory.json      |  40 --
 13 files changed, 346 insertions(+), 2025 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/ivytown/cache.json b/tools/perf/pmu-events/arch/x86/ivytown/cache.json
index d95b98c839143..c8f7d5e66504c 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/cache.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/cache.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "L1D data line replacements",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x51",
         "EventName": "L1D.REPLACEMENT",
         "PublicDescription": "Counts the number of lines brought into the L1 data cache.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.FB_FULL",
@@ -22,8 +18,6 @@
     },
     {
         "BriefDescription": "L1D miss outstanding duration in cycles",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING",
         "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
@@ -32,8 +26,6 @@
     },
     {
         "BriefDescription": "Cycles with L1D load Misses outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -43,8 +35,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -54,8 +44,6 @@
     },
     {
         "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "L2_L1D_WB_RQSTS.ALL",
         "SampleAfterValue": "200003",
@@ -63,8 +51,6 @@
     },
     {
         "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "L2_L1D_WB_RQSTS.HIT_E",
         "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
@@ -73,8 +59,6 @@
     },
     {
         "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "L2_L1D_WB_RQSTS.HIT_M",
         "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
@@ -83,8 +67,6 @@
     },
     {
         "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "L2_L1D_WB_RQSTS.MISS",
         "PublicDescription": "Not rejected writebacks that missed LLC.",
@@ -93,8 +75,6 @@
     },
     {
         "BriefDescription": "L2 cache lines filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.ALL",
         "PublicDescription": "L2 cache lines filling L2.",
@@ -103,8 +83,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in E state filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.E",
         "PublicDescription": "L2 cache lines in E state filling L2.",
@@ -113,8 +91,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in I state filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.I",
         "PublicDescription": "L2 cache lines in I state filling L2.",
@@ -123,8 +99,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in S state filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.S",
         "PublicDescription": "L2 cache lines in S state filling L2.",
@@ -133,8 +107,6 @@
     },
     {
         "BriefDescription": "Clean L2 cache lines evicted by demand",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
         "PublicDescription": "Clean L2 cache lines evicted by demand.",
@@ -143,8 +115,6 @@
     },
     {
         "BriefDescription": "Dirty L2 cache lines evicted by demand",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
         "PublicDescription": "Dirty L2 cache lines evicted by demand.",
@@ -153,8 +123,6 @@
     },
     {
         "BriefDescription": "Dirty L2 cache lines filling the L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DIRTY_ALL",
         "PublicDescription": "Dirty L2 cache lines filling the L2.",
@@ -163,8 +131,6 @@
     },
     {
         "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.PF_CLEAN",
         "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.",
@@ -173,8 +139,6 @@
     },
     {
         "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.PF_DIRTY",
         "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.",
@@ -183,8 +147,6 @@
     },
     {
         "BriefDescription": "L2 code requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_CODE_RD",
         "PublicDescription": "Counts all L2 code requests.",
@@ -193,8 +155,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
         "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
@@ -203,8 +163,6 @@
     },
     {
         "BriefDescription": "Requests from L2 hardware prefetchers",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_PF",
         "PublicDescription": "Counts all L2 HW prefetcher requests.",
@@ -213,8 +171,6 @@
     },
     {
         "BriefDescription": "RFO requests to L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_RFO",
         "PublicDescription": "Counts all L2 store RFO requests.",
@@ -223,8 +179,6 @@
     },
     {
         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_HIT",
         "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
@@ -233,8 +187,6 @@
     },
     {
         "BriefDescription": "L2 cache misses when fetching instructions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_MISS",
         "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
@@ -243,8 +195,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
         "PublicDescription": "Demand Data Read requests that hit L2 cache.",
@@ -253,8 +203,6 @@
     },
     {
         "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PF_HIT",
         "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
@@ -263,8 +211,6 @@
     },
     {
         "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PF_MISS",
         "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
@@ -273,8 +219,6 @@
     },
     {
         "BriefDescription": "RFO requests that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_HIT",
         "PublicDescription": "RFO requests that hit L2 cache.",
@@ -283,8 +227,6 @@
     },
     {
         "BriefDescription": "RFO requests that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_MISS",
         "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
@@ -293,8 +235,6 @@
     },
     {
         "BriefDescription": "RFOs that access cache lines in any state",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x27",
         "EventName": "L2_STORE_LOCK_RQSTS.ALL",
         "PublicDescription": "RFOs that access cache lines in any state.",
@@ -303,8 +243,6 @@
     },
     {
         "BriefDescription": "RFOs that hit cache lines in M state",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x27",
         "EventName": "L2_STORE_LOCK_RQSTS.HIT_M",
         "PublicDescription": "RFOs that hit cache lines in M state.",
@@ -313,8 +251,6 @@
     },
     {
         "BriefDescription": "RFOs that miss cache lines",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x27",
         "EventName": "L2_STORE_LOCK_RQSTS.MISS",
         "PublicDescription": "RFOs that miss cache lines.",
@@ -323,8 +259,6 @@
     },
     {
         "BriefDescription": "L2 or LLC HW prefetches that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.ALL_PF",
         "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.",
@@ -333,8 +267,6 @@
     },
     {
         "BriefDescription": "Transactions accessing L2 pipe",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.ALL_REQUESTS",
         "PublicDescription": "Transactions accessing L2 pipe.",
@@ -343,8 +275,6 @@
     },
     {
         "BriefDescription": "L2 cache accesses when fetching instructions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.CODE_RD",
         "PublicDescription": "L2 cache accesses when fetching instructions.",
@@ -353,8 +283,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.DEMAND_DATA_RD",
         "PublicDescription": "Demand Data Read requests that access L2 cache.",
@@ -363,8 +291,6 @@
     },
     {
         "BriefDescription": "L1D writebacks that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L1D_WB",
         "PublicDescription": "L1D writebacks that access L2 cache.",
@@ -373,8 +299,6 @@
     },
     {
         "BriefDescription": "L2 fill requests that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L2_FILL",
         "PublicDescription": "L2 fill requests that access L2 cache.",
@@ -383,8 +307,6 @@
     },
     {
         "BriefDescription": "L2 writebacks that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L2_WB",
         "PublicDescription": "L2 writebacks that access L2 cache.",
@@ -393,8 +315,6 @@
     },
     {
         "BriefDescription": "RFO requests that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.RFO",
         "PublicDescription": "RFO requests that access L2 cache.",
@@ -403,8 +323,6 @@
     },
     {
         "BriefDescription": "Cycles when L1D is locked",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x63",
         "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
         "PublicDescription": "Cycles in which the L1D is locked.",
@@ -413,8 +331,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests missed LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.MISS",
         "PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
@@ -423,8 +339,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests that refer to LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
         "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
@@ -433,8 +347,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",
         "PEBS": "1",
@@ -443,8 +355,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",
         "PEBS": "1",
@@ -453,8 +363,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",
         "PEBS": "1",
@@ -463,8 +371,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",
         "PEBS": "1",
@@ -473,8 +379,6 @@
     },
     {
         "BriefDescription": "Retired load uops whose data source was local DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD3",
         "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",
         "SampleAfterValue": "100007",
@@ -482,8 +386,6 @@
     },
     {
         "BriefDescription": "Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD3",
         "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM",
         "SampleAfterValue": "100007",
@@ -491,8 +393,6 @@
     },
     {
         "BriefDescription": "Data forwarded from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD3",
         "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD",
         "SampleAfterValue": "100007",
@@ -500,8 +400,6 @@
     },
     {
         "BriefDescription": "Remote cache HITM.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD3",
         "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM",
         "SampleAfterValue": "100007",
@@ -509,8 +407,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
         "PEBS": "1",
@@ -519,8 +415,6 @@
     },
     {
         "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
         "PEBS": "1",
@@ -529,8 +423,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources following L1 data-cache miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
         "PEBS": "1",
@@ -539,8 +431,6 @@
     },
     {
         "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
         "PEBS": "1",
@@ -549,8 +439,6 @@
     },
     {
         "BriefDescription": "Retired load uops with L2 cache misses as data sources.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
         "PEBS": "1",
@@ -559,8 +447,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",
         "PEBS": "1",
@@ -569,8 +455,6 @@
     },
     {
         "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS",
         "PEBS": "1",
@@ -579,8 +463,6 @@
     },
     {
         "BriefDescription": "All retired load uops. (Precise Event)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
         "PEBS": "1",
@@ -589,8 +471,6 @@
     },
     {
         "BriefDescription": "All retired store uops. (Precise Event)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
         "PEBS": "1",
@@ -599,8 +479,6 @@
     },
     {
         "BriefDescription": "Retired load uops with locked access. (Precise Event)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
         "PEBS": "1",
@@ -609,8 +487,6 @@
     },
     {
         "BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
         "PEBS": "1",
@@ -619,8 +495,6 @@
     },
     {
         "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
         "PEBS": "1",
@@ -629,8 +503,6 @@
     },
     {
         "BriefDescription": "Retired load uops that miss the STLB. (Precise Event)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
         "PEBS": "1",
@@ -639,8 +511,6 @@
     },
     {
         "BriefDescription": "Retired store uops that miss the STLB. (Precise Event)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
         "PEBS": "1",
@@ -649,8 +519,6 @@
     },
     {
         "BriefDescription": "Demand and prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
         "PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
@@ -659,8 +527,6 @@
     },
     {
         "BriefDescription": "Cacheable and noncacheable code read requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
         "PublicDescription": "Demand code read requests sent to uncore.",
@@ -669,8 +535,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests sent to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
         "PublicDescription": "Demand data read requests sent to uncore.",
@@ -679,8 +543,6 @@
     },
     {
         "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
         "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
@@ -689,8 +551,6 @@
     },
     {
         "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB2",
         "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
         "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.",
@@ -699,8 +559,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
         "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
@@ -709,8 +567,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
@@ -720,8 +576,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
@@ -731,8 +585,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
@@ -742,8 +594,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
@@ -753,8 +603,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
         "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
@@ -763,8 +611,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
         "PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
@@ -773,8 +619,6 @@
     },
     {
         "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "6",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
@@ -784,8 +628,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
         "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",
@@ -794,464 +636,348 @@
     },
     {
         "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads that hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0090",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0090",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0090",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0090",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0090",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c03f7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c03f7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c03f7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c03f7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c03f7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all writebacks from the core to the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10008",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that hit in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data reads that hit in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803c8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23ffc08000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0200",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts non-temporal stores",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10800",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Split locks in SQ",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF4",
         "EventName": "SQ_MISC.SPLIT_LOCK",
         "SampleAfterValue": "100003",
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json b/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json
index 88891cba54ec8..89c6d47cc0771 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Cycles with any input/output SSE or FP assist",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.ANY",
@@ -12,8 +10,6 @@
     },
     {
         "BriefDescription": "Number of SIMD FP assists due to input values",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.SIMD_INPUT",
         "PublicDescription": "Number of SIMD FP assists due to input values.",
@@ -22,8 +18,6 @@
     },
     {
         "BriefDescription": "Number of SIMD FP assists due to Output values",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.SIMD_OUTPUT",
         "PublicDescription": "Number of SIMD FP assists due to output values.",
@@ -32,8 +26,6 @@
     },
     {
         "BriefDescription": "Number of X87 assists due to input value.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.X87_INPUT",
         "PublicDescription": "Number of X87 FP assists due to input values.",
@@ -42,8 +34,6 @@
     },
     {
         "BriefDescription": "Number of X87 assists due to output value.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.X87_OUTPUT",
         "PublicDescription": "Number of X87 FP assists due to output values.",
@@ -52,8 +42,6 @@
     },
     {
         "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",
         "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",
@@ -62,8 +50,6 @@
     },
     {
         "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",
         "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",
@@ -72,8 +58,6 @@
     },
     {
         "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",
         "PublicDescription": "Counts number of SSE* or AVX-128 double precision FP scalar uops executed.",
@@ -82,8 +66,6 @@
     },
     {
         "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",
         "PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",
@@ -92,8 +74,6 @@
     },
     {
         "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.X87",
         "PublicDescription": "Counts number of X87 uops executed.",
@@ -102,8 +82,6 @@
     },
     {
         "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
         "SampleAfterValue": "1000003",
@@ -111,8 +89,6 @@
     },
     {
         "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
         "SampleAfterValue": "1000003",
@@ -120,8 +96,6 @@
     },
     {
         "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.AVX_STORE",
         "PublicDescription": "Number of assists associated with 256-bit AVX store operations.",
@@ -130,8 +104,6 @@
     },
     {
         "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.AVX_TO_SSE",
         "SampleAfterValue": "100003",
@@ -139,8 +111,6 @@
     },
     {
         "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.SSE_TO_AVX",
         "SampleAfterValue": "100003",
@@ -148,8 +118,6 @@
     },
     {
         "BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x11",
         "EventName": "SIMD_FP_256.PACKED_DOUBLE",
         "PublicDescription": "Counts 256-bit packed double-precision floating-point instructions.",
@@ -158,8 +126,6 @@
     },
     {
         "BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x11",
         "EventName": "SIMD_FP_256.PACKED_SINGLE",
         "PublicDescription": "Counts 256-bit packed single-precision floating-point instructions.",
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/frontend.json b/tools/perf/pmu-events/arch/x86/ivytown/frontend.json
index 0a295c4e093dd..4ee100024ca94 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/frontend.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xE6",
         "EventName": "BACLEARS.ANY",
         "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAB",
         "EventName": "DSB2MITE_SWITCHES.COUNT",
         "PublicDescription": "Number of DSB to MITE switches.",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAB",
         "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
         "PublicDescription": "Cycles DSB to MITE switches caused delay.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAC",
         "EventName": "DSB_FILL.EXCEED_DSB_LINES",
         "PublicDescription": "DSB Fill encountered > 3 DSB lines.",
@@ -41,8 +33,6 @@
     },
     {
         "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.HIT",
         "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
@@ -51,8 +41,6 @@
     },
     {
         "BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.IFETCH_STALL",
         "PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.",
@@ -61,8 +49,6 @@
     },
     {
         "BriefDescription": "Instruction cache, streaming buffer and victim cache misses",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.MISSES",
         "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.",
@@ -71,8 +57,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -82,8 +66,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -93,8 +75,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering 4 Uops",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -104,8 +84,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering any Uop",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -115,8 +93,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_CYCLES",
@@ -126,8 +102,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_UOPS",
         "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
@@ -136,8 +110,6 @@
     },
     {
         "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0x79",
         "EventName": "IDQ.EMPTY",
         "PublicDescription": "Counts cycles the IDQ is empty.",
@@ -146,8 +118,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_ALL_UOPS",
         "PublicDescription": "Number of uops delivered to IDQ from any path.",
@@ -156,8 +126,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_CYCLES",
@@ -167,8 +135,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_UOPS",
         "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",
@@ -177,8 +143,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_CYCLES",
@@ -188,8 +152,6 @@
     },
     {
         "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_DSB_CYCLES",
@@ -199,8 +161,6 @@
     },
     {
         "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
@@ -211,8 +171,6 @@
     },
     {
         "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_DSB_UOPS",
         "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
@@ -221,8 +179,6 @@
     },
     {
         "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_MITE_UOPS",
         "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
@@ -231,8 +187,6 @@
     },
     {
         "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
@@ -243,8 +197,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_UOPS",
         "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.",
@@ -253,8 +205,6 @@
     },
     {
         "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
         "PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.",
@@ -263,8 +213,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -273,8 +221,6 @@
     },
     {
         "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@@ -284,8 +230,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "3",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@@ -294,8 +238,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@@ -304,8 +246,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json b/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json
index 99a45c8d8ceeb..80444bc4e66e4 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json
@@ -88,7 +88,7 @@
     },
     {
         "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
-        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
         "MetricGroup": "TopdownL1;tma_L1_group",
         "MetricName": "tma_bad_speculation",
         "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
@@ -96,7 +96,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
-        "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
+        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
         "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
         "MetricName": "tma_branch_mispredicts",
         "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
@@ -120,7 +120,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
-        "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB)) * tma_backend_bound",
+        "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) * tma_backend_bound",
         "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
         "MetricName": "tma_memory_bound",
         "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@@ -152,7 +152,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
-        "MetricExpr": "(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
+        "MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
         "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
         "MetricName": "tma_lock_latency",
         "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS",
@@ -192,7 +192,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
-        "MetricExpr": "(MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
+        "MetricExpr": "MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
         "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_l3_bound",
         "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
@@ -200,7 +200,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
-        "MetricExpr": "(60 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD)))) / CLKS",
+        "MetricExpr": "(60 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD)))) / CLKS",
         "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_contested_accesses",
         "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
@@ -208,7 +208,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
-        "MetricExpr": "43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / CLKS",
+        "MetricExpr": "43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / CLKS",
         "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_data_sharing",
         "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
@@ -216,7 +216,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
-        "MetricExpr": "41 * (MEM_LOAD_UOPS_RETIRED.LLC_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / CLKS",
+        "MetricExpr": "41 * (MEM_LOAD_UOPS_RETIRED.LLC_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / CLKS",
         "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_l3_hit_latency",
         "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
@@ -224,7 +224,7 @@
     },
     {
         "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
-        "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
+        "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
         "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_sq_full",
         "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
@@ -232,7 +232,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
-        "MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS))) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
+        "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
         "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_dram_bound",
         "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS",
@@ -256,7 +256,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
-        "MetricExpr": "200 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / CLKS",
+        "MetricExpr": "200 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / CLKS",
         "MetricGroup": "Server;TopdownL5;tma_mem_latency_group",
         "MetricName": "tma_local_dram",
         "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS",
@@ -264,7 +264,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
-        "MetricExpr": "310 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / CLKS",
+        "MetricExpr": "310 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / CLKS",
         "MetricGroup": "Server;Snoop;TopdownL5;tma_mem_latency_group",
         "MetricName": "tma_remote_dram",
         "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS",
@@ -272,7 +272,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
-        "MetricExpr": "(200 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD)))) / CLKS",
+        "MetricExpr": "(200 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD)))) / CLKS",
         "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_mem_latency_group",
         "MetricName": "tma_remote_cache",
         "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS",
@@ -288,7 +288,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
-        "MetricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES))) + (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
+        "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
         "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
         "MetricName": "tma_store_latency",
         "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
@@ -336,7 +336,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
-        "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / CLKS",
+        "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / CLKS",
         "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
         "MetricName": "tma_ports_utilization",
         "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@@ -344,7 +344,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@) / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else 0) / CORE_CLKS",
+        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) / CORE_CLKS)",
         "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
         "MetricName": "tma_ports_utilized_0",
         "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
@@ -352,7 +352,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS",
+        "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS)",
         "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
         "MetricName": "tma_ports_utilized_1",
         "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
@@ -360,7 +360,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
+        "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS)",
         "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
         "MetricName": "tma_ports_utilized_2",
         "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
@@ -368,7 +368,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
-        "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
+        "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
         "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
         "MetricName": "tma_ports_utilized_3m",
         "ScaleUnit": "100%"
@@ -424,7 +424,7 @@
     },
     {
         "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
+        "MetricExpr": "tma_port_4",
         "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
         "MetricName": "tma_store_op_utilization",
         "ScaleUnit": "100%"
@@ -494,7 +494,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
-        "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
         "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
         "MetricName": "tma_microcode_sequencer",
         "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
@@ -567,19 +567,19 @@
     },
     {
         "BriefDescription": "Floating Point Operations Per Cycle",
-        "MetricExpr": "(1 * (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / CORE_CLKS",
+        "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / CORE_CLKS",
         "MetricGroup": "Flops;Ret",
         "MetricName": "FLOPc"
     },
     {
         "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
         "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
         "MetricName": "ILP"
     },
     {
         "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
-        "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
+        "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
         "MetricGroup": "SMT",
         "MetricName": "CORE_CLKS"
     },
@@ -646,7 +646,7 @@
     },
     {
         "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
-        "MetricExpr": "IDQ.DSB_UOPS / ((IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS))",
+        "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
         "MetricGroup": "DSB;Fed;FetchBW",
         "MetricName": "DSB_Coverage"
     },
@@ -658,7 +658,7 @@
     },
     {
         "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
-        "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb)",
+        "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)",
         "MetricGroup": "Mem;MemoryBound;MemoryLat",
         "MetricName": "Load_Miss_Real_Latency"
     },
@@ -670,19 +670,19 @@
     },
     {
         "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L1MPKI"
     },
     {
         "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
         "MetricGroup": "Backend;CacheMisses;Mem",
         "MetricName": "L2MPKI"
     },
     {
         "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L3MPKI"
     },
@@ -695,19 +695,19 @@
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
-        "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
+        "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L1D_Cache_Fill_BW"
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
-        "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
+        "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L2_Cache_Fill_BW"
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
+        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L3_Cache_Fill_BW"
     },
@@ -737,19 +737,19 @@
     },
     {
         "BriefDescription": "Average CPU Utilization",
-        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
+        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
         "MetricGroup": "HPC;Summary",
         "MetricName": "CPU_Utilization"
     },
     {
         "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
-        "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
+        "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
         "MetricGroup": "Power;Summary",
         "MetricName": "Average_Frequency"
     },
     {
         "BriefDescription": "Giga Floating Point Operations Per Second",
-        "MetricExpr": "((1 * (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1000000000) / duration_time",
+        "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1e9 / duration_time",
         "MetricGroup": "Cor;Flops;HPC",
         "MetricName": "GFLOPs",
         "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
@@ -762,7 +762,7 @@
     },
     {
         "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
-        "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
+        "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
         "MetricGroup": "SMT",
         "MetricName": "SMT_2T_Utilization"
     },
@@ -780,10 +780,22 @@
     },
     {
         "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
-        "MetricExpr": "(64 * (uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@) / 1000000000) / duration_time",
+        "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time",
         "MetricGroup": "HPC;Mem;MemoryBW;SoC",
         "MetricName": "DRAM_BW_Use"
     },
+    {
+        "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
+        "MetricExpr": "1e9 * (UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_INSERTS.MISS_OPCODE@filter_opc\\=0x182@) / (Socket_CLKS / duration_time)",
+        "MetricGroup": "Mem;MemoryLat;SoC",
+        "MetricName": "MEM_Read_Latency"
+    },
+    {
+        "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
+        "MetricExpr": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182\\,thresh\\=1@",
+        "MetricGroup": "Mem;MemoryBW;SoC",
+        "MetricName": "MEM_Parallel_Reads"
+    },
     {
         "BriefDescription": "Socket actual clocks when any core is active on that socket",
         "MetricExpr": "cbox_0@event\\=0x0@",
@@ -796,52 +808,59 @@
         "MetricGroup": "Branches;OS",
         "MetricName": "IpFarBranch"
     },
+    {
+        "BriefDescription": "Uncore frequency per die [GHZ]",
+        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+        "MetricGroup": "SoC",
+        "MetricName": "UNCORE_FREQ"
+    },
     {
         "BriefDescription": "C3 residency percent per core",
-        "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C3_Core_Residency"
+        "MetricName": "C3_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C6 residency percent per core",
-        "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C6_Core_Residency"
+        "MetricName": "C6_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C7 residency percent per core",
-        "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C7_Core_Residency"
+        "MetricName": "C7_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C2 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C2_Pkg_Residency"
+        "MetricName": "C2_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C3 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C3_Pkg_Residency"
+        "MetricName": "C3_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C6 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C6_Pkg_Residency"
+        "MetricName": "C6_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C7 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C7_Pkg_Residency"
-    },
-    {
-        "BriefDescription": "Uncore frequency per die [GHZ]",
-        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000",
-        "MetricGroup": "SoC",
-        "MetricName": "UNCORE_FREQ"
+        "MetricName": "C7_Pkg_Residency",
+        "ScaleUnit": "100%"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/memory.json b/tools/perf/pmu-events/arch/x86/ivytown/memory.json
index 99b71e43acadc..138d1aa0b32d8 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/memory.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
         "SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
     },
     {
         "BriefDescription": "Loads with latency value being above 128",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
         "MSRIndex": "0x3F6",
@@ -19,13 +15,10 @@
         "PEBS": "2",
         "PublicDescription": "Loads with latency value being above 128.",
         "SampleAfterValue": "1009",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 16",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
         "MSRIndex": "0x3F6",
@@ -33,13 +26,10 @@
         "PEBS": "2",
         "PublicDescription": "Loads with latency value being above 16.",
         "SampleAfterValue": "20011",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 256",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
         "MSRIndex": "0x3F6",
@@ -47,13 +37,10 @@
         "PEBS": "2",
         "PublicDescription": "Loads with latency value being above 256.",
         "SampleAfterValue": "503",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 32",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
         "MSRIndex": "0x3F6",
@@ -61,13 +48,10 @@
         "PEBS": "2",
         "PublicDescription": "Loads with latency value being above 32.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 4",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
         "MSRIndex": "0x3F6",
@@ -75,13 +59,10 @@
         "PEBS": "2",
         "PublicDescription": "Loads with latency value being above 4.",
         "SampleAfterValue": "100003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 512",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
         "MSRIndex": "0x3F6",
@@ -89,13 +70,10 @@
         "PEBS": "2",
         "PublicDescription": "Loads with latency value being above 512.",
         "SampleAfterValue": "101",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 64",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
         "MSRIndex": "0x3F6",
@@ -103,13 +81,10 @@
         "PEBS": "2",
         "PublicDescription": "Loads with latency value being above 64.",
         "SampleAfterValue": "2003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 8",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
         "MSRIndex": "0x3F6",
@@ -117,25 +92,18 @@
         "PEBS": "2",
         "PublicDescription": "Loads with latency value being above 8.",
         "SampleAfterValue": "50021",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
         "PEBS": "2",
-        "PRECISE_STORE": "1",
         "SampleAfterValue": "2000003",
-        "TakenAlone": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x05",
         "EventName": "MISALIGN_MEM_REF.LOADS",
         "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.",
@@ -144,8 +112,6 @@
     },
     {
         "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x05",
         "EventName": "MISALIGN_MEM_REF.STORES",
         "PublicDescription": "Speculative cache-line split Store-address uops dispatched to L1D.",
@@ -154,349 +120,262 @@
     },
     {
         "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3fffc00244",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC  and the data returned from remote dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x67f800244",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC  and the data forwarded from remote cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x87f800244",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads that hits the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3fffc20091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3fffc203f7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x6004003f7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  the data is found in M state in remote cache and forwarded from there",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x107fc003f7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data forwarded from remote cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x87f8203f7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that miss the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3fffc20004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that miss the LLC  and the data returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x600400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that miss the LLC  and the data returned from remote dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x67f800004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x107fc00004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that miss the LLC  and the data forwarded from remote cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x87f820004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that miss the LLC  and the data returned from remote & local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x67fc00001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that miss in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3fffc20001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that miss the LLC  and the data returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x600400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that miss the LLC  and the data returned from remote dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x67f800001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x107fc00001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that miss the LLC  and the data forwarded from remote cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x87f820001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) that miss the LLC and the data is found in M state in remote cache and forwarded from there.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x107fc20002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from remote & local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3fffc20040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from remote & local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x67fc00010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3fffc20010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x600400010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  that miss the LLC  and the data returned from remote dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x67f800010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x107fc00010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data forwarded from remote cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x87f820010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3fffc20200",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that miss in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3fffc20080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     }
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/other.json b/tools/perf/pmu-events/arch/x86/ivytown/other.json
index 2d62521791d8c..e80e99d064ba5 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/other.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/other.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5C",
         "EventName": "CPL_CYCLES.RING0",
         "PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5C",
@@ -23,8 +19,6 @@
     },
     {
         "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5C",
         "EventName": "CPL_CYCLES.RING123",
         "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
@@ -33,8 +27,6 @@
     },
     {
         "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x63",
         "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
         "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json b/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json
index d89d3f8db1905..d1e64e0d683e4 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Divide operations executed",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x14",
@@ -13,8 +11,6 @@
     },
     {
         "BriefDescription": "Cycles when divider is busy executing divide operations",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x14",
         "EventName": "ARITH.FPU_DIV_ACTIVE",
         "PublicDescription": "Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides.",
@@ -23,8 +19,6 @@
     },
     {
         "BriefDescription": "Speculative and retired  branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_BRANCHES",
         "PublicDescription": "Counts all near executed branches (not necessarily retired).",
@@ -33,8 +27,6 @@
     },
     {
         "BriefDescription": "Speculative and retired macro-conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
         "PublicDescription": "Speculative and retired macro-conditional branches.",
@@ -43,8 +35,6 @@
     },
     {
         "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
         "PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.",
@@ -53,8 +43,6 @@
     },
     {
         "BriefDescription": "Speculative and retired direct near calls",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
         "PublicDescription": "Speculative and retired direct near calls.",
@@ -63,8 +51,6 @@
     },
     {
         "BriefDescription": "Speculative and retired indirect branches excluding calls and returns",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
         "PublicDescription": "Speculative and retired indirect branches excluding calls and returns.",
@@ -73,8 +59,6 @@
     },
     {
         "BriefDescription": "Speculative and retired indirect return branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
         "SampleAfterValue": "200003",
@@ -82,8 +66,6 @@
     },
     {
         "BriefDescription": "Not taken macro-conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
         "PublicDescription": "Not taken macro-conditional branches.",
@@ -92,8 +74,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired macro-conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
         "PublicDescription": "Taken speculative and retired macro-conditional branches.",
@@ -102,8 +82,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
         "PublicDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.",
@@ -112,8 +90,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired direct near calls",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
         "PublicDescription": "Taken speculative and retired direct near calls.",
@@ -122,8 +98,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
         "PublicDescription": "Taken speculative and retired indirect branches excluding calls and returns.",
@@ -132,8 +106,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect calls",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
         "PublicDescription": "Taken speculative and retired indirect calls.",
@@ -142,8 +114,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
         "PublicDescription": "Taken speculative and retired indirect branches with return mnemonic.",
@@ -152,8 +122,6 @@
     },
     {
         "BriefDescription": "All (macro) branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "PublicDescription": "Branch instructions at retirement.",
@@ -161,8 +129,6 @@
     },
     {
         "BriefDescription": "All (macro) branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
         "PEBS": "2",
@@ -171,8 +137,6 @@
     },
     {
         "BriefDescription": "Conditional branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -181,8 +145,6 @@
     },
     {
         "BriefDescription": "Far branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.FAR_BRANCH",
         "PublicDescription": "Number of far branches retired.",
@@ -191,8 +153,6 @@
     },
     {
         "BriefDescription": "Direct and indirect near call instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -201,8 +161,6 @@
     },
     {
         "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
         "PEBS": "1",
@@ -211,8 +169,6 @@
     },
     {
         "BriefDescription": "Return instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_RETURN",
         "PEBS": "1",
@@ -221,8 +177,6 @@
     },
     {
         "BriefDescription": "Taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
@@ -231,8 +185,6 @@
     },
     {
         "BriefDescription": "Not taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NOT_TAKEN",
         "PublicDescription": "Counts the number of not taken branch instructions retired.",
@@ -241,8 +193,6 @@
     },
     {
         "BriefDescription": "Speculative and retired mispredicted macro conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_BRANCHES",
         "PublicDescription": "Counts all near executed branches (not necessarily retired).",
@@ -251,8 +201,6 @@
     },
     {
         "BriefDescription": "Speculative and retired mispredicted macro conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
         "PublicDescription": "Speculative and retired mispredicted macro conditional branches.",
@@ -261,8 +209,6 @@
     },
     {
         "BriefDescription": "Mispredicted indirect branches excluding calls and returns",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
         "PublicDescription": "Mispredicted indirect branches excluding calls and returns.",
@@ -271,8 +217,6 @@
     },
     {
         "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
         "PublicDescription": "Not taken speculative and retired mispredicted macro conditional branches.",
@@ -281,8 +225,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
         "PublicDescription": "Taken speculative and retired mispredicted macro conditional branches.",
@@ -291,8 +233,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
         "PublicDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.",
@@ -301,8 +241,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect calls",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
         "PublicDescription": "Taken speculative and retired mispredicted indirect calls.",
@@ -311,8 +249,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
         "PublicDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.",
@@ -321,8 +257,6 @@
     },
     {
         "BriefDescription": "All mispredicted macro branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PublicDescription": "Mispredicted branch instructions at retirement.",
@@ -330,8 +264,6 @@
     },
     {
         "BriefDescription": "Mispredicted macro branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
         "PEBS": "2",
@@ -340,8 +272,6 @@
     },
     {
         "BriefDescription": "Mispredicted conditional branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -350,8 +280,6 @@
     },
     {
         "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
@@ -360,8 +288,6 @@
     },
     {
         "BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "2000003",
@@ -369,8 +295,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
         "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.",
@@ -380,8 +304,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
         "SampleAfterValue": "2000003",
@@ -389,8 +311,6 @@
     },
     {
         "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "2000003",
@@ -398,16 +318,12 @@
     },
     {
         "BriefDescription": "Reference cycles when the core is not in halt state.",
-        "Counter": "Fixed counter 2",
-        "CounterHTOff": "Fixed counter 2",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
         "SampleAfterValue": "2000003",
         "UMask": "0x3"
     },
     {
         "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
         "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)",
@@ -417,8 +333,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
         "SampleAfterValue": "2000003",
@@ -426,8 +340,6 @@
     },
     {
         "BriefDescription": "Core cycles when the thread is not in halt state.",
-        "Counter": "Fixed counter 1",
-        "CounterHTOff": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
@@ -435,8 +347,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",
-        "Counter": "Fixed counter 1",
-        "CounterHTOff": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
         "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
         "SampleAfterValue": "2000003",
@@ -444,8 +354,6 @@
     },
     {
         "BriefDescription": "Thread cycles when thread is not in halt state",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
         "PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.",
@@ -454,8 +362,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
         "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
@@ -463,8 +369,6 @@
     },
     {
         "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "8",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
@@ -473,8 +377,6 @@
     },
     {
         "BriefDescription": "Cycles with pending L1 cache miss loads.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "8",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
@@ -484,8 +386,6 @@
     },
     {
         "BriefDescription": "Cycles while L2 cache miss load* is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
@@ -494,8 +394,6 @@
     },
     {
         "BriefDescription": "Cycles with pending L2 cache miss loads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
@@ -505,8 +403,6 @@
     },
     {
         "BriefDescription": "Cycles with pending memory loads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
@@ -516,8 +412,6 @@
     },
     {
         "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
@@ -526,8 +420,6 @@
     },
     {
         "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
@@ -537,8 +429,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "12",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
@@ -547,8 +437,6 @@
     },
     {
         "BriefDescription": "Execution stalls due to L1 data cache misses",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "12",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
@@ -558,8 +446,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L2 cache miss load* is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "5",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
@@ -568,8 +454,6 @@
     },
     {
         "BriefDescription": "Execution stalls due to L2 cache misses.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "5",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
@@ -579,8 +463,6 @@
     },
     {
         "BriefDescription": "Execution stalls due to memory subsystem.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "6",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",
@@ -589,8 +471,6 @@
     },
     {
         "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "6",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
@@ -599,8 +479,6 @@
     },
     {
         "BriefDescription": "Total execution stalls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
@@ -609,8 +487,6 @@
     },
     {
         "BriefDescription": "Stall cycles because IQ is full",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.IQ_FULL",
         "PublicDescription": "Stall cycles due to IQ is full.",
@@ -619,8 +495,6 @@
     },
     {
         "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.LCP",
         "SampleAfterValue": "2000003",
@@ -628,16 +502,12 @@
     },
     {
         "BriefDescription": "Instructions retired from execution.",
-        "Counter": "Fixed counter 0",
-        "CounterHTOff": "Fixed counter 0",
         "EventName": "INST_RETIRED.ANY",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of instructions retired. General Counter   - architectural event",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.ANY_P",
         "PublicDescription": "Number of instructions at retirement.",
@@ -645,8 +515,6 @@
     },
     {
         "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
-        "Counter": "1",
-        "CounterHTOff": "1",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.PREC_DIST",
         "PEBS": "2",
@@ -656,8 +524,6 @@
     },
     {
         "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES",
@@ -667,8 +533,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
@@ -677,8 +541,6 @@
     },
     {
         "BriefDescription": "Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x0D",
@@ -688,8 +550,6 @@
     },
     {
         "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.NO_SR",
         "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
@@ -698,8 +558,6 @@
     },
     {
         "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.STORE_FORWARD",
         "PublicDescription": "Loads blocked by overlapping with store buffer that cannot be forwarded.",
@@ -708,8 +566,6 @@
     },
     {
         "BriefDescription": "False dependencies in MOB due to partial compare on address",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x07",
         "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
         "PublicDescription": "False dependencies in MOB due to partial compare on address.",
@@ -718,8 +574,6 @@
     },
     {
         "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4C",
         "EventName": "LOAD_HIT_PRE.HW_PF",
         "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.",
@@ -728,8 +582,6 @@
     },
     {
         "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4C",
         "EventName": "LOAD_HIT_PRE.SW_PF",
         "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.",
@@ -738,8 +590,6 @@
     },
     {
         "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_4_UOPS",
@@ -749,8 +599,6 @@
     },
     {
         "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_ACTIVE",
@@ -760,8 +608,6 @@
     },
     {
         "BriefDescription": "Number of Uops delivered by the LSD.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA8",
         "EventName": "LSD.UOPS",
         "SampleAfterValue": "2000003",
@@ -769,8 +615,6 @@
     },
     {
         "BriefDescription": "Number of machine clears (nukes) of any type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xC3",
@@ -780,8 +624,6 @@
     },
     {
         "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MASKMOV",
         "PublicDescription": "Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
@@ -790,8 +632,6 @@
     },
     {
         "BriefDescription": "Self-modifying code (SMC) detected.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.SMC",
         "PublicDescription": "Number of self-modifying-code machine clears detected.",
@@ -800,8 +640,6 @@
     },
     {
         "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.INT_ELIMINATED",
         "SampleAfterValue": "1000003",
@@ -809,8 +647,6 @@
     },
     {
         "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x58",
         "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",
         "SampleAfterValue": "1000003",
@@ -818,8 +654,6 @@
     },
     {
         "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",
         "SampleAfterValue": "100003",
@@ -827,8 +661,6 @@
     },
     {
         "BriefDescription": "Resource-related stall cycles",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ANY",
         "PublicDescription": "Cycles Allocation is stalled due to Resource Related reason.",
@@ -837,8 +669,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to re-order buffer full.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ROB",
         "SampleAfterValue": "2000003",
@@ -846,8 +676,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no eligible RS entry available.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.RS",
         "SampleAfterValue": "2000003",
@@ -855,8 +683,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.SB",
         "PublicDescription": "Cycles stalled due to no store buffers available (not including draining form sync).",
@@ -865,8 +691,6 @@
     },
     {
         "BriefDescription": "Count cases of saving new LBR",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCC",
         "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
         "PublicDescription": "Count cases of saving new LBR records by hardware.",
@@ -875,8 +699,6 @@
     },
     {
         "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5E",
         "EventName": "RS_EVENTS.EMPTY_CYCLES",
         "PublicDescription": "Cycles the RS is empty for the thread.",
@@ -885,8 +707,6 @@
     },
     {
         "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5E",
@@ -897,8 +717,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are dispatched to port 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_0",
         "PublicDescription": "Cycles which a Uop is dispatched on port 0.",
@@ -908,8 +726,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE",
         "PublicDescription": "Cycles per core when uops are dispatched to port 0.",
@@ -918,8 +734,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are dispatched to port 1",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_1",
         "PublicDescription": "Cycles which a Uop is dispatched on port 1.",
@@ -929,8 +743,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 1",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE",
         "PublicDescription": "Cycles per core when uops are dispatched to port 1.",
@@ -939,8 +751,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_2",
         "PublicDescription": "Cycles which a Uop is dispatched on port 2.",
@@ -950,8 +760,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops dispatched to port 2, loads and stores per core (speculative and retired).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE",
         "SampleAfterValue": "2000003",
@@ -959,8 +767,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_3",
         "PublicDescription": "Cycles which a Uop is dispatched on port 3.",
@@ -970,8 +776,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE",
         "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3.",
@@ -980,8 +784,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are dispatched to port 4",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_4",
         "PublicDescription": "Cycles which a Uop is dispatched on port 4.",
@@ -991,8 +793,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 4",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE",
         "PublicDescription": "Cycles per core when uops are dispatched to port 4.",
@@ -1001,8 +801,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are dispatched to port 5",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_5",
         "PublicDescription": "Cycles which a Uop is dispatched on port 5.",
@@ -1012,8 +810,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 5",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE",
         "PublicDescription": "Cycles per core when uops are dispatched to port 5.",
@@ -1022,8 +818,6 @@
     },
     {
         "BriefDescription": "Number of uops executed on the core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE",
         "PublicDescription": "Counts total number of uops to be executed per-core each cycle.",
@@ -1032,8 +826,6 @@
     },
     {
         "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@@ -1043,8 +835,6 @@
     },
     {
         "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@@ -1054,8 +844,6 @@
     },
     {
         "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@@ -1065,8 +853,6 @@
     },
     {
         "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@@ -1076,8 +862,6 @@
     },
     {
         "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
         "Invert": "1",
@@ -1087,8 +871,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
@@ -1098,8 +880,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
@@ -1109,8 +889,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
@@ -1120,8 +898,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
@@ -1131,8 +907,6 @@
     },
     {
         "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.STALL_CYCLES",
@@ -1142,8 +916,6 @@
     },
     {
         "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.THREAD",
         "PublicDescription": "Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles.",
@@ -1152,8 +924,6 @@
     },
     {
         "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.ANY",
         "PublicDescription": "Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.",
@@ -1163,8 +933,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -1175,8 +943,6 @@
     },
     {
         "BriefDescription": "Number of flags-merge uops being allocated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.FLAGS_MERGE",
         "PublicDescription": "Number of flags-merge uops allocated. Such uops adds delay.",
@@ -1185,8 +951,6 @@
     },
     {
         "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.SINGLE_MUL",
         "PublicDescription": "Number of multiply packed/scalar single precision uops allocated.",
@@ -1195,8 +959,6 @@
     },
     {
         "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.SLOW_LEA",
         "PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
@@ -1205,8 +967,6 @@
     },
     {
         "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -1217,8 +977,6 @@
     },
     {
         "BriefDescription": "Retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ALL",
         "PEBS": "1",
@@ -1228,8 +986,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles without actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",
@@ -1239,8 +995,6 @@
     },
     {
         "BriefDescription": "Retirement slots used.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
         "PEBS": "1",
@@ -1249,8 +1003,6 @@
     },
     {
         "BriefDescription": "Cycles without actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -1260,8 +1012,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 10 actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "10",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-cache.json b/tools/perf/pmu-events/arch/x86/ivytown/uncore-cache.json
index c118ff54c30eb..521175881173a 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-cache.json
@@ -1,14 +1,12 @@
 [
     {
         "BriefDescription": "Uncore Clocks",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_C_CLOCKTICKS",
         "PerPkg": "1",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Counter 0 Occupancy",
-        "Counter": "1,2,3",
         "EventCode": "0x1f",
         "EventName": "UNC_C_COUNTER0_OCCUPANCY",
         "PerPkg": "1",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "Cache Lookups; Any Request",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_C_LLC_LOOKUP.ANY",
         "PerPkg": "1",
@@ -27,7 +24,6 @@
     },
     {
         "BriefDescription": "Cache Lookups; Data Read Request",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
         "PerPkg": "1",
@@ -37,7 +33,6 @@
     },
     {
         "BriefDescription": "Cache Lookups; Lookups that Match NID",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_C_LLC_LOOKUP.NID",
         "PerPkg": "1",
@@ -47,7 +42,6 @@
     },
     {
         "BriefDescription": "Cache Lookups; External Snoop Request",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
         "PerPkg": "1",
@@ -57,7 +51,6 @@
     },
     {
         "BriefDescription": "Cache Lookups; Write Requests",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_C_LLC_LOOKUP.WRITE",
         "PerPkg": "1",
@@ -67,7 +60,6 @@
     },
     {
         "BriefDescription": "Lines Victimized; Lines in E state",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
         "PerPkg": "1",
@@ -77,7 +69,6 @@
     },
     {
         "BriefDescription": "Lines Victimized",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_C_LLC_VICTIMS.MISS",
         "PerPkg": "1",
@@ -87,7 +78,6 @@
     },
     {
         "BriefDescription": "Lines Victimized; Lines in M state",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
         "PerPkg": "1",
@@ -97,7 +87,6 @@
     },
     {
         "BriefDescription": "Lines Victimized; Victimized Lines that Match NID",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_C_LLC_VICTIMS.NID",
         "PerPkg": "1",
@@ -107,7 +96,6 @@
     },
     {
         "BriefDescription": "Lines Victimized; Lines in S State",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_C_LLC_VICTIMS.S_STATE",
         "PerPkg": "1",
@@ -117,7 +105,6 @@
     },
     {
         "BriefDescription": "Cbo Misc; RFO HitS",
-        "Counter": "0,1",
         "EventCode": "0x39",
         "EventName": "UNC_C_MISC.RFO_HIT_S",
         "PerPkg": "1",
@@ -127,7 +114,6 @@
     },
     {
         "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
-        "Counter": "0,1",
         "EventCode": "0x39",
         "EventName": "UNC_C_MISC.RSPI_WAS_FSE",
         "PerPkg": "1",
@@ -137,7 +123,6 @@
     },
     {
         "BriefDescription": "Cbo Misc",
-        "Counter": "0,1",
         "EventCode": "0x39",
         "EventName": "UNC_C_MISC.STARTED",
         "PerPkg": "1",
@@ -147,7 +132,6 @@
     },
     {
         "BriefDescription": "Cbo Misc; Write Combining Aliasing",
-        "Counter": "0,1",
         "EventCode": "0x39",
         "EventName": "UNC_C_MISC.WC_ALIASING",
         "PerPkg": "1",
@@ -157,7 +141,6 @@
     },
     {
         "BriefDescription": "LRU Queue; LRU Age 0",
-        "Counter": "0,1",
         "EventCode": "0x3c",
         "EventName": "UNC_C_QLRU.AGE0",
         "PerPkg": "1",
@@ -167,7 +150,6 @@
     },
     {
         "BriefDescription": "LRU Queue; LRU Age 1",
-        "Counter": "0,1",
         "EventCode": "0x3c",
         "EventName": "UNC_C_QLRU.AGE1",
         "PerPkg": "1",
@@ -177,7 +159,6 @@
     },
     {
         "BriefDescription": "LRU Queue; LRU Age 2",
-        "Counter": "0,1",
         "EventCode": "0x3c",
         "EventName": "UNC_C_QLRU.AGE2",
         "PerPkg": "1",
@@ -187,7 +168,6 @@
     },
     {
         "BriefDescription": "LRU Queue; LRU Age 3",
-        "Counter": "0,1",
         "EventCode": "0x3c",
         "EventName": "UNC_C_QLRU.AGE3",
         "PerPkg": "1",
@@ -197,7 +177,6 @@
     },
     {
         "BriefDescription": "LRU Queue; LRU Bits Decremented",
-        "Counter": "0,1",
         "EventCode": "0x3c",
         "EventName": "UNC_C_QLRU.LRU_DECREMENT",
         "PerPkg": "1",
@@ -207,7 +186,6 @@
     },
     {
         "BriefDescription": "LRU Queue; Non-0 Aged Victim",
-        "Counter": "0,1",
         "EventCode": "0x3c",
         "EventName": "UNC_C_QLRU.VICTIM_NON_ZERO",
         "PerPkg": "1",
@@ -217,17 +195,15 @@
     },
     {
         "BriefDescription": "AD Ring In Use; Counterclockwise",
-        "Counter": "2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_C_RING_AD_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "AD Ring In Use; Clockwise",
-        "Counter": "2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_C_RING_AD_USED.CW",
         "PerPkg": "1",
@@ -237,17 +213,15 @@
     },
     {
         "BriefDescription": "AD Ring In Use; Down",
-        "Counter": "2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_C_RING_AD_USED.DOWN",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
-        "UMask": "0xCC",
+        "UMask": "0xcc",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "AD Ring In Use; Down and Even on Vring 0",
-        "Counter": "2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_C_RING_AD_USED.DOWN_VR0_EVEN",
         "PerPkg": "1",
@@ -257,7 +231,6 @@
     },
     {
         "BriefDescription": "AD Ring In Use; Down and Odd on Vring 0",
-        "Counter": "2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_C_RING_AD_USED.DOWN_VR0_ODD",
         "PerPkg": "1",
@@ -267,7 +240,6 @@
     },
     {
         "BriefDescription": "AD Ring In Use; Down and Even on VRing 1",
-        "Counter": "2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_C_RING_AD_USED.DOWN_VR1_EVEN",
         "PerPkg": "1",
@@ -277,7 +249,6 @@
     },
     {
         "BriefDescription": "AD Ring In Use; Down and Odd on VRing 1",
-        "Counter": "2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_C_RING_AD_USED.DOWN_VR1_ODD",
         "PerPkg": "1",
@@ -287,7 +258,6 @@
     },
     {
         "BriefDescription": "AD Ring In Use; Up",
-        "Counter": "2,3",
         "EventCode": "0x1B",
         "EventName": "UNC_C_RING_AD_USED.UP",
         "PerPkg": "1",
@@ -297,7 +267,6 @@
     },
     {
         "BriefDescription": "AD Ring In Use; Up and Even on Vring 0",
-        "Counter": "2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_C_RING_AD_USED.UP_VR0_EVEN",
         "PerPkg": "1",
@@ -307,7 +276,6 @@
     },
     {
         "BriefDescription": "AD Ring In Use; Up and Odd on Vring 0",
-        "Counter": "2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_C_RING_AD_USED.UP_VR0_ODD",
         "PerPkg": "1",
@@ -317,7 +285,6 @@
     },
     {
         "BriefDescription": "AD Ring In Use; Up and Even on VRing 1",
-        "Counter": "2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_C_RING_AD_USED.UP_VR1_EVEN",
         "PerPkg": "1",
@@ -327,7 +294,6 @@
     },
     {
         "BriefDescription": "AD Ring In Use; Up and Odd on VRing 1",
-        "Counter": "2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_C_RING_AD_USED.UP_VR1_ODD",
         "PerPkg": "1",
@@ -337,17 +303,15 @@
     },
     {
         "BriefDescription": "AK Ring In Use; Counterclockwise",
-        "Counter": "2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_C_RING_AK_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "AK Ring In Use; Clockwise",
-        "Counter": "2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_C_RING_AK_USED.CW",
         "PerPkg": "1",
@@ -357,17 +321,15 @@
     },
     {
         "BriefDescription": "AK Ring In Use; Down",
-        "Counter": "2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_C_RING_AK_USED.DOWN",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
-        "UMask": "0xCC",
+        "UMask": "0xcc",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "AK Ring In Use; Down and Even on Vring 0",
-        "Counter": "2,3",
         "EventCode": "0x1c",
         "EventName": "UNC_C_RING_AK_USED.DOWN_VR0_EVEN",
         "PerPkg": "1",
@@ -377,7 +339,6 @@
     },
     {
         "BriefDescription": "AK Ring In Use; Down and Odd on Vring 0",
-        "Counter": "2,3",
         "EventCode": "0x1c",
         "EventName": "UNC_C_RING_AK_USED.DOWN_VR0_ODD",
         "PerPkg": "1",
@@ -387,7 +348,6 @@
     },
     {
         "BriefDescription": "AK Ring In Use; Down and Even on VRing 1",
-        "Counter": "2,3",
         "EventCode": "0x1c",
         "EventName": "UNC_C_RING_AK_USED.DOWN_VR1_EVEN",
         "PerPkg": "1",
@@ -397,7 +357,6 @@
     },
     {
         "BriefDescription": "AK Ring In Use; Down and Odd on VRing 1",
-        "Counter": "2,3",
         "EventCode": "0x1c",
         "EventName": "UNC_C_RING_AK_USED.DOWN_VR1_ODD",
         "PerPkg": "1",
@@ -407,7 +366,6 @@
     },
     {
         "BriefDescription": "AK Ring In Use; Up",
-        "Counter": "2,3",
         "EventCode": "0x1C",
         "EventName": "UNC_C_RING_AK_USED.UP",
         "PerPkg": "1",
@@ -417,7 +375,6 @@
     },
     {
         "BriefDescription": "AK Ring In Use; Up and Even on Vring 0",
-        "Counter": "2,3",
         "EventCode": "0x1c",
         "EventName": "UNC_C_RING_AK_USED.UP_VR0_EVEN",
         "PerPkg": "1",
@@ -427,7 +384,6 @@
     },
     {
         "BriefDescription": "AK Ring In Use; Up and Odd on Vring 0",
-        "Counter": "2,3",
         "EventCode": "0x1c",
         "EventName": "UNC_C_RING_AK_USED.UP_VR0_ODD",
         "PerPkg": "1",
@@ -437,7 +393,6 @@
     },
     {
         "BriefDescription": "AK Ring In Use; Up and Even on VRing 1",
-        "Counter": "2,3",
         "EventCode": "0x1c",
         "EventName": "UNC_C_RING_AK_USED.UP_VR1_EVEN",
         "PerPkg": "1",
@@ -447,7 +402,6 @@
     },
     {
         "BriefDescription": "AK Ring In Use; Up and Odd on VRing 1",
-        "Counter": "2,3",
         "EventCode": "0x1c",
         "EventName": "UNC_C_RING_AK_USED.UP_VR1_ODD",
         "PerPkg": "1",
@@ -457,17 +411,15 @@
     },
     {
         "BriefDescription": "BL Ring in Use; Counterclockwise",
-        "Counter": "2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_C_RING_BL_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Clockwise",
-        "Counter": "2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_C_RING_BL_USED.CW",
         "PerPkg": "1",
@@ -477,17 +429,15 @@
     },
     {
         "BriefDescription": "BL Ring in Use; Down",
-        "Counter": "2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_C_RING_BL_USED.DOWN",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
-        "UMask": "0xCC",
+        "UMask": "0xcc",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "BL Ring in Use; Down and Even on Vring 0",
-        "Counter": "2,3",
         "EventCode": "0x1d",
         "EventName": "UNC_C_RING_BL_USED.DOWN_VR0_EVEN",
         "PerPkg": "1",
@@ -497,7 +447,6 @@
     },
     {
         "BriefDescription": "BL Ring in Use; Down and Odd on Vring 0",
-        "Counter": "2,3",
         "EventCode": "0x1d",
         "EventName": "UNC_C_RING_BL_USED.DOWN_VR0_ODD",
         "PerPkg": "1",
@@ -507,7 +456,6 @@
     },
     {
         "BriefDescription": "BL Ring in Use; Down and Even on VRing 1",
-        "Counter": "2,3",
         "EventCode": "0x1d",
         "EventName": "UNC_C_RING_BL_USED.DOWN_VR1_EVEN",
         "PerPkg": "1",
@@ -517,7 +465,6 @@
     },
     {
         "BriefDescription": "BL Ring in Use; Down and Odd on VRing 1",
-        "Counter": "2,3",
         "EventCode": "0x1d",
         "EventName": "UNC_C_RING_BL_USED.DOWN_VR1_ODD",
         "PerPkg": "1",
@@ -527,7 +474,6 @@
     },
     {
         "BriefDescription": "BL Ring in Use; Up",
-        "Counter": "2,3",
         "EventCode": "0x1D",
         "EventName": "UNC_C_RING_BL_USED.UP",
         "PerPkg": "1",
@@ -537,7 +483,6 @@
     },
     {
         "BriefDescription": "BL Ring in Use; Up and Even on Vring 0",
-        "Counter": "2,3",
         "EventCode": "0x1d",
         "EventName": "UNC_C_RING_BL_USED.UP_VR0_EVEN",
         "PerPkg": "1",
@@ -547,7 +492,6 @@
     },
     {
         "BriefDescription": "BL Ring in Use; Up and Odd on Vring 0",
-        "Counter": "2,3",
         "EventCode": "0x1d",
         "EventName": "UNC_C_RING_BL_USED.UP_VR0_ODD",
         "PerPkg": "1",
@@ -557,7 +501,6 @@
     },
     {
         "BriefDescription": "BL Ring in Use; Up and Even on VRing 1",
-        "Counter": "2,3",
         "EventCode": "0x1d",
         "EventName": "UNC_C_RING_BL_USED.UP_VR1_EVEN",
         "PerPkg": "1",
@@ -567,7 +510,6 @@
     },
     {
         "BriefDescription": "BL Ring in Use; Up and Odd on VRing 1",
-        "Counter": "2,3",
         "EventCode": "0x1d",
         "EventName": "UNC_C_RING_BL_USED.UP_VR1_ODD",
         "PerPkg": "1",
@@ -577,7 +519,6 @@
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "UNC_C_RING_BOUNCES.AD_IRQ",
         "PerPkg": "1",
@@ -586,7 +527,6 @@
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.; Acknowledgements to core",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "UNC_C_RING_BOUNCES.AK",
         "PerPkg": "1",
@@ -595,7 +535,6 @@
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.: Acknowledgements to core",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "UNC_C_RING_BOUNCES.AK_CORE",
         "PerPkg": "1",
@@ -604,7 +543,6 @@
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.; Data Responses to core",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "UNC_C_RING_BOUNCES.BL",
         "PerPkg": "1",
@@ -613,7 +551,6 @@
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.: Data Responses to core",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "UNC_C_RING_BOUNCES.BL_CORE",
         "PerPkg": "1",
@@ -622,7 +559,6 @@
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "UNC_C_RING_BOUNCES.IV",
         "PerPkg": "1",
@@ -631,7 +567,6 @@
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.: Snoops of processor's cache.",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "UNC_C_RING_BOUNCES.IV_CORE",
         "PerPkg": "1",
@@ -640,27 +575,24 @@
     },
     {
         "BriefDescription": "IV Ring in Use; Any",
-        "Counter": "2,3",
         "EventCode": "0x1e",
         "EventName": "UNC_C_RING_IV_USED.ANY",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters any polarity",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "IV Ring in Use; Down",
-        "Counter": "2,3",
         "EventCode": "0x1e",
         "EventName": "UNC_C_RING_IV_USED.DOWN",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for Down polarity",
-        "UMask": "0xCC",
+        "UMask": "0xcc",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "IV Ring in Use; Up",
-        "Counter": "2,3",
         "EventCode": "0x1e",
         "EventName": "UNC_C_RING_IV_USED.UP",
         "PerPkg": "1",
@@ -668,9 +600,35 @@
         "UMask": "0x33",
         "Unit": "CBO"
     },
+    {
+        "EventCode": "0x6",
+        "EventName": "UNC_C_RING_SINK_STARVED.AD_IPQ",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CBO"
+    },
+    {
+        "EventCode": "0x6",
+        "EventName": "UNC_C_RING_SINK_STARVED.AD_IRQ",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CBO"
+    },
+    {
+        "EventCode": "0x6",
+        "EventName": "UNC_C_RING_SINK_STARVED.IV",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CBO"
+    },
+    {
+        "EventCode": "0x7",
+        "EventName": "UNC_C_RING_SRC_THRTL",
+        "PerPkg": "1",
+        "Unit": "CBO"
+    },
     {
         "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "UNC_C_RxR_EXT_STARVED.IPQ",
         "PerPkg": "1",
@@ -680,7 +638,6 @@
     },
     {
         "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "UNC_C_RxR_EXT_STARVED.IRQ",
         "PerPkg": "1",
@@ -690,7 +647,6 @@
     },
     {
         "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
         "PerPkg": "1",
@@ -700,7 +656,6 @@
     },
     {
         "BriefDescription": "Ingress Arbiter Blocking Cycles",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "UNC_C_RxR_EXT_STARVED.PRQ",
         "PerPkg": "1",
@@ -710,7 +665,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; IPQ",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_C_RxR_INSERTS.IPQ",
         "PerPkg": "1",
@@ -720,7 +674,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; IRQ",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_C_RxR_INSERTS.IRQ",
         "PerPkg": "1",
@@ -730,7 +683,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; IRQ Rejected",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_C_RxR_INSERTS.IRQ_REJ",
         "PerPkg": "1",
@@ -740,7 +692,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations: IRQ Rejected",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_C_RxR_INSERTS.IRQ_REJECTED",
         "PerPkg": "1",
@@ -750,7 +701,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; VFIFO",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_C_RxR_INSERTS.VFIFO",
         "PerPkg": "1",
@@ -760,7 +710,6 @@
     },
     {
         "BriefDescription": "Ingress Internal Starvation Cycles; IPQ",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_C_RxR_INT_STARVED.IPQ",
         "PerPkg": "1",
@@ -770,7 +719,6 @@
     },
     {
         "BriefDescription": "Ingress Internal Starvation Cycles; IRQ",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_C_RxR_INT_STARVED.IRQ",
         "PerPkg": "1",
@@ -780,7 +728,6 @@
     },
     {
         "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_C_RxR_INT_STARVED.ISMQ",
         "PerPkg": "1",
@@ -790,7 +737,6 @@
     },
     {
         "BriefDescription": "Probe Queue Retries; Address Conflict",
-        "Counter": "0,1",
         "EventCode": "0x31",
         "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
         "PerPkg": "1",
@@ -800,7 +746,6 @@
     },
     {
         "BriefDescription": "Probe Queue Retries; Any Reject",
-        "Counter": "0,1",
         "EventCode": "0x31",
         "EventName": "UNC_C_RxR_IPQ_RETRY.ANY",
         "PerPkg": "1",
@@ -810,7 +755,6 @@
     },
     {
         "BriefDescription": "Probe Queue Retries; No Egress Credits",
-        "Counter": "0,1",
         "EventCode": "0x31",
         "EventName": "UNC_C_RxR_IPQ_RETRY.FULL",
         "PerPkg": "1",
@@ -820,7 +764,6 @@
     },
     {
         "BriefDescription": "Probe Queue Retries; No QPI Credits",
-        "Counter": "0,1",
         "EventCode": "0x31",
         "EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS",
         "PerPkg": "1",
@@ -830,7 +773,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; Address Conflict",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
         "PerPkg": "1",
@@ -840,7 +782,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; Any Reject",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.ANY",
         "PerPkg": "1",
@@ -850,7 +791,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; No Egress Credits",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.FULL",
         "PerPkg": "1",
@@ -860,7 +800,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS",
         "PerPkg": "1",
@@ -870,7 +809,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS",
         "PerPkg": "1",
@@ -880,7 +818,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; No RTIDs",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.RTID",
         "PerPkg": "1",
@@ -890,7 +827,6 @@
     },
     {
         "BriefDescription": "ISMQ Retries; Any Reject",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_C_RxR_ISMQ_RETRY.ANY",
         "PerPkg": "1",
@@ -900,7 +836,6 @@
     },
     {
         "BriefDescription": "ISMQ Retries; No Egress Credits",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_C_RxR_ISMQ_RETRY.FULL",
         "PerPkg": "1",
@@ -910,7 +845,6 @@
     },
     {
         "BriefDescription": "ISMQ Retries; No IIO Credits",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
         "PerPkg": "1",
@@ -920,7 +854,6 @@
     },
     {
         "BriefDescription": "ISMQ Retries; No QPI Credits",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
         "PerPkg": "1",
@@ -930,7 +863,6 @@
     },
     {
         "BriefDescription": "ISMQ Retries; No RTIDs",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID",
         "PerPkg": "1",
@@ -940,7 +872,6 @@
     },
     {
         "BriefDescription": "ISMQ Retries; No WB Credits",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS",
         "PerPkg": "1",
@@ -995,7 +926,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; All",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.ALL",
         "PerPkg": "1",
@@ -1005,7 +935,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; Evictions",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.EVICTION",
         "PerPkg": "1",
@@ -1015,7 +944,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; Local Memory",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.LOCAL",
         "PerPkg": "1",
@@ -1025,7 +953,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE",
         "PerPkg": "1",
@@ -1035,17 +962,15 @@
     },
     {
         "BriefDescription": "TOR Inserts; Misses to Local Memory",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by locally HOMed memory.",
-        "UMask": "0x2A",
+        "UMask": "0x2a",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE",
         "PerPkg": "1",
@@ -1055,7 +980,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; Miss Opcode Match",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE",
         "PerPkg": "1",
@@ -1065,17 +989,15 @@
     },
     {
         "BriefDescription": "TOR Inserts; Misses to Remote Memory",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by remote caches or remote memory.",
-        "UMask": "0x8A",
+        "UMask": "0x8a",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE",
         "PerPkg": "1",
@@ -1085,7 +1007,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; NID Matched",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.NID_ALL",
         "PerPkg": "1",
@@ -1095,7 +1016,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; NID Matched Evictions",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION",
         "PerPkg": "1",
@@ -1105,17 +1025,15 @@
     },
     {
         "BriefDescription": "TOR Inserts; NID Matched Miss All",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent.  There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc  to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.",
-        "UMask": "0x4A",
+        "UMask": "0x4a",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
         "PerPkg": "1",
@@ -1125,7 +1043,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; NID and Opcode Matched",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE",
         "PerPkg": "1",
@@ -1135,7 +1052,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; NID Matched Writebacks",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.NID_WB",
         "PerPkg": "1",
@@ -1145,7 +1061,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; Opcode Match",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.OPCODE",
         "PerPkg": "1",
@@ -1155,7 +1070,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; Remote Memory",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.REMOTE",
         "PerPkg": "1",
@@ -1165,7 +1079,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE",
         "PerPkg": "1",
@@ -1175,7 +1088,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; Writebacks",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.WB",
         "PerPkg": "1",
@@ -1225,7 +1137,7 @@
         "EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL",
         "PerPkg": "1",
         "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR.  'Miss' means the allocation requires an RTID.  This generally means that the request was sent to memory or MMIO.",
-        "UMask": "0xA",
+        "UMask": "0xa",
         "Unit": "CBO"
     },
     {
@@ -1234,7 +1146,7 @@
         "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL",
         "PerPkg": "1",
         "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
-        "UMask": "0x2A",
+        "UMask": "0x2a",
         "Unit": "CBO"
     },
     {
@@ -1261,7 +1173,7 @@
         "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE",
         "PerPkg": "1",
         "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
-        "UMask": "0x8A",
+        "UMask": "0x8a",
         "Unit": "CBO"
     },
     {
@@ -1297,7 +1209,7 @@
         "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
         "PerPkg": "1",
         "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID.",
-        "UMask": "0x4A",
+        "UMask": "0x4a",
         "Unit": "CBO"
     },
     {
@@ -1365,7 +1277,6 @@
     },
     {
         "BriefDescription": "Onto AD Ring",
-        "Counter": "0,1",
         "EventCode": "0x4",
         "EventName": "UNC_C_TxR_ADS_USED.AD",
         "PerPkg": "1",
@@ -1374,7 +1285,6 @@
     },
     {
         "BriefDescription": "Onto AK Ring",
-        "Counter": "0,1",
         "EventCode": "0x4",
         "EventName": "UNC_C_TxR_ADS_USED.AK",
         "PerPkg": "1",
@@ -1383,7 +1293,6 @@
     },
     {
         "BriefDescription": "Onto BL Ring",
-        "Counter": "0,1",
         "EventCode": "0x4",
         "EventName": "UNC_C_TxR_ADS_USED.BL",
         "PerPkg": "1",
@@ -1392,7 +1301,6 @@
     },
     {
         "BriefDescription": "Egress Allocations; AD - Cachebo",
-        "Counter": "0,1",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.AD_CACHE",
         "PerPkg": "1",
@@ -1402,7 +1310,6 @@
     },
     {
         "BriefDescription": "Egress Allocations; AD - Corebo",
-        "Counter": "0,1",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.AD_CORE",
         "PerPkg": "1",
@@ -1412,7 +1319,6 @@
     },
     {
         "BriefDescription": "Egress Allocations; AK - Cachebo",
-        "Counter": "0,1",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.AK_CACHE",
         "PerPkg": "1",
@@ -1422,7 +1328,6 @@
     },
     {
         "BriefDescription": "Egress Allocations; AK - Corebo",
-        "Counter": "0,1",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.AK_CORE",
         "PerPkg": "1",
@@ -1432,7 +1337,6 @@
     },
     {
         "BriefDescription": "Egress Allocations; BL - Cacheno",
-        "Counter": "0,1",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.BL_CACHE",
         "PerPkg": "1",
@@ -1442,7 +1346,6 @@
     },
     {
         "BriefDescription": "Egress Allocations; BL - Corebo",
-        "Counter": "0,1",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.BL_CORE",
         "PerPkg": "1",
@@ -1452,7 +1355,6 @@
     },
     {
         "BriefDescription": "Egress Allocations; IV - Cachebo",
-        "Counter": "0,1",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.IV_CACHE",
         "PerPkg": "1",
@@ -1462,7 +1364,6 @@
     },
     {
         "BriefDescription": "Injection Starvation; Onto AD Ring (to core)",
-        "Counter": "0,1",
         "EventCode": "0x3",
         "EventName": "UNC_C_TxR_STARVED.AD_CORE",
         "PerPkg": "1",
@@ -1472,7 +1373,6 @@
     },
     {
         "BriefDescription": "Injection Starvation; Onto AK Ring",
-        "Counter": "0,1",
         "EventCode": "0x3",
         "EventName": "UNC_C_TxR_STARVED.AK_BOTH",
         "PerPkg": "1",
@@ -1482,7 +1382,6 @@
     },
     {
         "BriefDescription": "Injection Starvation; Onto IV Ring",
-        "Counter": "0,1",
         "EventCode": "0x3",
         "EventName": "UNC_C_TxR_STARVED.IV",
         "PerPkg": "1",
@@ -1492,7 +1391,6 @@
     },
     {
         "BriefDescription": "BT Bypass",
-        "Counter": "0,1,2,3",
         "EventCode": "0x52",
         "EventName": "UNC_H_BT_BYPASS",
         "PerPkg": "1",
@@ -1501,7 +1399,6 @@
     },
     {
         "BriefDescription": "BT Cycles Not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0x42",
         "EventName": "UNC_H_BT_CYCLES_NE",
         "PerPkg": "1",
@@ -1510,7 +1407,6 @@
     },
     {
         "BriefDescription": "BT Cycles Not Empty: Local",
-        "Counter": "0,1,2,3",
         "EventCode": "0x42",
         "EventName": "UNC_H_BT_CYCLES_NE.LOCAL",
         "PerPkg": "1",
@@ -1520,7 +1416,6 @@
     },
     {
         "BriefDescription": "BT Cycles Not Empty: Remote",
-        "Counter": "0,1,2,3",
         "EventCode": "0x42",
         "EventName": "UNC_H_BT_CYCLES_NE.REMOTE",
         "PerPkg": "1",
@@ -1530,7 +1425,6 @@
     },
     {
         "BriefDescription": "BT Occupancy; Local",
-        "Counter": "0,1,2,3",
         "EventCode": "0x43",
         "EventName": "UNC_H_BT_OCCUPANCY.LOCAL",
         "PerPkg": "1",
@@ -1540,7 +1434,6 @@
     },
     {
         "BriefDescription": "BT Occupancy; Reads Local",
-        "Counter": "0,1,2,3",
         "EventCode": "0x43",
         "EventName": "UNC_H_BT_OCCUPANCY.READS_LOCAL",
         "PerPkg": "1",
@@ -1550,7 +1443,6 @@
     },
     {
         "BriefDescription": "BT Occupancy; Reads Remote",
-        "Counter": "0,1,2,3",
         "EventCode": "0x43",
         "EventName": "UNC_H_BT_OCCUPANCY.READS_REMOTE",
         "PerPkg": "1",
@@ -1560,7 +1452,6 @@
     },
     {
         "BriefDescription": "BT Occupancy; Remote",
-        "Counter": "0,1,2,3",
         "EventCode": "0x43",
         "EventName": "UNC_H_BT_OCCUPANCY.REMOTE",
         "PerPkg": "1",
@@ -1570,7 +1461,6 @@
     },
     {
         "BriefDescription": "BT Occupancy; Writes Local",
-        "Counter": "0,1,2,3",
         "EventCode": "0x43",
         "EventName": "UNC_H_BT_OCCUPANCY.WRITES_LOCAL",
         "PerPkg": "1",
@@ -1580,7 +1470,6 @@
     },
     {
         "BriefDescription": "BT Occupancy; Writes Remote",
-        "Counter": "0,1,2,3",
         "EventCode": "0x43",
         "EventName": "UNC_H_BT_OCCUPANCY.WRITES_REMOTE",
         "PerPkg": "1",
@@ -1590,7 +1479,6 @@
     },
     {
         "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
-        "Counter": "0,1,2,3",
         "EventCode": "0x51",
         "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD",
         "PerPkg": "1",
@@ -1600,7 +1488,6 @@
     },
     {
         "BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard",
-        "Counter": "0,1,2,3",
         "EventCode": "0x51",
         "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD",
         "PerPkg": "1",
@@ -1610,7 +1497,6 @@
     },
     {
         "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
-        "Counter": "0,1,2,3",
         "EventCode": "0x51",
         "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD",
         "PerPkg": "1",
@@ -1620,7 +1506,6 @@
     },
     {
         "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
-        "Counter": "0,1,2,3",
         "EventCode": "0x51",
         "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD",
         "PerPkg": "1",
@@ -1630,7 +1515,6 @@
     },
     {
         "BriefDescription": "HA to iMC Bypass; Not Taken",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN",
         "PerPkg": "1",
@@ -1640,7 +1524,6 @@
     },
     {
         "BriefDescription": "HA to iMC Bypass; Taken",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_H_BYPASS_IMC.TAKEN",
         "PerPkg": "1",
@@ -1650,7 +1533,6 @@
     },
     {
         "BriefDescription": "uclks",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_H_CLOCKTICKS",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of uclks in the HA.  This will be slightly different than the count in the Ubox because of enable/freeze delays.  The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.",
@@ -1658,7 +1540,6 @@
     },
     {
         "BriefDescription": "Conflict Checks; Acknowledge Conflicts",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb",
         "EventName": "UNC_H_CONFLICT_CYCLES.ACKCNFLTS",
         "PerPkg": "1",
@@ -1668,7 +1549,6 @@
     },
     {
         "BriefDescription": "Conflict Checks; Cmp Fwds",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb",
         "EventName": "UNC_H_CONFLICT_CYCLES.CMP_FWDS",
         "PerPkg": "1",
@@ -1678,7 +1558,6 @@
     },
     {
         "BriefDescription": "Conflict Checks; Conflict Detected",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb",
         "EventName": "UNC_H_CONFLICT_CYCLES.CONFLICT",
         "PerPkg": "1",
@@ -1688,7 +1567,6 @@
     },
     {
         "BriefDescription": "Conflict Checks; Last in conflict chain",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb",
         "EventName": "UNC_H_CONFLICT_CYCLES.LAST",
         "PerPkg": "1",
@@ -1698,7 +1576,6 @@
     },
     {
         "BriefDescription": "Direct2Core Messages Sent",
-        "Counter": "0,1,2,3",
         "EventCode": "0x11",
         "EventName": "UNC_H_DIRECT2CORE_COUNT",
         "PerPkg": "1",
@@ -1707,7 +1584,6 @@
     },
     {
         "BriefDescription": "Cycles when Direct2Core was Disabled",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED",
         "PerPkg": "1",
@@ -1716,7 +1592,6 @@
     },
     {
         "BriefDescription": "Number of Reads that had Direct2Core Overridden",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE",
         "PerPkg": "1",
@@ -1725,7 +1600,6 @@
     },
     {
         "BriefDescription": "Directory Lat Opt Return",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_H_DIRECTORY_LAT_OPT",
         "PerPkg": "1",
@@ -1734,7 +1608,6 @@
     },
     {
         "BriefDescription": "Directory Lookups: Any state",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc",
         "EventName": "UNC_H_DIRECTORY_LOOKUP.ANY",
         "PerPkg": "1",
@@ -1744,7 +1617,6 @@
     },
     {
         "BriefDescription": "Directory Lookups; Snoop Not Needed",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc",
         "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP",
         "PerPkg": "1",
@@ -1754,7 +1626,6 @@
     },
     {
         "BriefDescription": "Directory Lookups: Snoop A",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc",
         "EventName": "UNC_H_DIRECTORY_LOOKUP.SNOOP_A",
         "PerPkg": "1",
@@ -1764,7 +1635,6 @@
     },
     {
         "BriefDescription": "Directory Lookups: Snoop S",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc",
         "EventName": "UNC_H_DIRECTORY_LOOKUP.SNOOP_S",
         "PerPkg": "1",
@@ -1774,7 +1644,6 @@
     },
     {
         "BriefDescription": "Directory Lookups; Snoop Needed",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc",
         "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP",
         "PerPkg": "1",
@@ -1784,7 +1653,6 @@
     },
     {
         "BriefDescription": "Directory Lookups: A State",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc",
         "EventName": "UNC_H_DIRECTORY_LOOKUP.STATE_A",
         "PerPkg": "1",
@@ -1794,7 +1662,6 @@
     },
     {
         "BriefDescription": "Directory Lookups: I State",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc",
         "EventName": "UNC_H_DIRECTORY_LOOKUP.STATE_I",
         "PerPkg": "1",
@@ -1804,7 +1671,6 @@
     },
     {
         "BriefDescription": "Directory Lookups: S State",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc",
         "EventName": "UNC_H_DIRECTORY_LOOKUP.STATE_S",
         "PerPkg": "1",
@@ -1814,7 +1680,6 @@
     },
     {
         "BriefDescription": "Directory Updates: A2I",
-        "Counter": "0,1,2,3",
         "EventCode": "0xd",
         "EventName": "UNC_H_DIRECTORY_UPDATE.A2I",
         "PerPkg": "1",
@@ -1824,7 +1689,6 @@
     },
     {
         "BriefDescription": "Directory Updates: A2S",
-        "Counter": "0,1,2,3",
         "EventCode": "0xd",
         "EventName": "UNC_H_DIRECTORY_UPDATE.A2S",
         "PerPkg": "1",
@@ -1834,7 +1698,6 @@
     },
     {
         "BriefDescription": "Directory Updates; Any Directory Update",
-        "Counter": "0,1,2,3",
         "EventCode": "0xd",
         "EventName": "UNC_H_DIRECTORY_UPDATE.ANY",
         "PerPkg": "1",
@@ -1844,7 +1707,6 @@
     },
     {
         "BriefDescription": "Directory Updates; Directory Clear",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD",
         "EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR",
         "PerPkg": "1",
@@ -1854,7 +1716,6 @@
     },
     {
         "BriefDescription": "Directory Updates: I2A",
-        "Counter": "0,1,2,3",
         "EventCode": "0xd",
         "EventName": "UNC_H_DIRECTORY_UPDATE.I2A",
         "PerPkg": "1",
@@ -1864,7 +1725,6 @@
     },
     {
         "BriefDescription": "Directory Updates: I2S",
-        "Counter": "0,1,2,3",
         "EventCode": "0xd",
         "EventName": "UNC_H_DIRECTORY_UPDATE.I2S",
         "PerPkg": "1",
@@ -1874,7 +1734,6 @@
     },
     {
         "BriefDescription": "Directory Updates: S2A",
-        "Counter": "0,1,2,3",
         "EventCode": "0xd",
         "EventName": "UNC_H_DIRECTORY_UPDATE.S2A",
         "PerPkg": "1",
@@ -1884,7 +1743,6 @@
     },
     {
         "BriefDescription": "Directory Updates: S2I",
-        "Counter": "0,1,2,3",
         "EventCode": "0xd",
         "EventName": "UNC_H_DIRECTORY_UPDATE.S2I",
         "PerPkg": "1",
@@ -1894,7 +1752,6 @@
     },
     {
         "BriefDescription": "Directory Updates; Directory Set",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD",
         "EventName": "UNC_H_DIRECTORY_UPDATE.SET",
         "PerPkg": "1",
@@ -1904,7 +1761,6 @@
     },
     {
         "BriefDescription": "AD QPI Link 2 Credit Accumulator",
-        "Counter": "0,1,2,3",
         "EventCode": "0x59",
         "EventName": "UNC_H_IGR_AD_QPI2_ACCUMULATOR",
         "PerPkg": "1",
@@ -1913,7 +1769,6 @@
     },
     {
         "BriefDescription": "BL QPI Link 2 Credit Accumulator",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5a",
         "EventName": "UNC_H_IGR_BL_QPI2_ACCUMULATOR",
         "PerPkg": "1",
@@ -1922,7 +1777,6 @@
     },
     {
         "BriefDescription": "AD QPI Link 2 Credit Accumulator",
-        "Counter": "0,1,2,3",
         "EventCode": "0x59",
         "EventName": "UNC_H_IGR_CREDITS_AD_QPI2",
         "PerPkg": "1",
@@ -1931,7 +1785,6 @@
     },
     {
         "BriefDescription": "BL QPI Link 2 Credit Accumulator",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5A",
         "EventName": "UNC_H_IGR_CREDITS_BL_QPI2",
         "PerPkg": "1",
@@ -1940,7 +1793,6 @@
     },
     {
         "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
         "PerPkg": "1",
@@ -1950,7 +1802,6 @@
     },
     {
         "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
         "PerPkg": "1",
@@ -1960,7 +1811,6 @@
     },
     {
         "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
         "PerPkg": "1",
@@ -1970,7 +1820,6 @@
     },
     {
         "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
         "PerPkg": "1",
@@ -1980,7 +1829,6 @@
     },
     {
         "BriefDescription": "HA to iMC Normal Priority Reads Issued; Normal Priority",
-        "Counter": "0,1,2,3",
         "EventCode": "0x17",
         "EventName": "UNC_H_IMC_READS.NORMAL",
         "PerPkg": "1",
@@ -1990,7 +1838,6 @@
     },
     {
         "BriefDescription": "Retry Events",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1e",
         "EventName": "UNC_H_IMC_RETRY",
         "PerPkg": "1",
@@ -1998,17 +1845,15 @@
     },
     {
         "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1a",
         "EventName": "UNC_H_IMC_WRITES.ALL",
         "PerPkg": "1",
         "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1a",
         "EventName": "UNC_H_IMC_WRITES.FULL",
         "PerPkg": "1",
@@ -2018,7 +1863,6 @@
     },
     {
         "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full Line",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1a",
         "EventName": "UNC_H_IMC_WRITES.FULL_ISOCH",
         "PerPkg": "1",
@@ -2028,7 +1872,6 @@
     },
     {
         "BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1a",
         "EventName": "UNC_H_IMC_WRITES.PARTIAL",
         "PerPkg": "1",
@@ -2038,7 +1881,6 @@
     },
     {
         "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1a",
         "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH",
         "PerPkg": "1",
@@ -2048,7 +1890,6 @@
     },
     {
         "BriefDescription": "IODC Conflicts; Any Conflict",
-        "Counter": "0,1,2,3",
         "EventCode": "0x57",
         "EventName": "UNC_H_IODC_CONFLICTS.ANY",
         "PerPkg": "1",
@@ -2057,7 +1898,6 @@
     },
     {
         "BriefDescription": "IODC Conflicts; Last Conflict",
-        "Counter": "0,1,2,3",
         "EventCode": "0x57",
         "EventName": "UNC_H_IODC_CONFLICTS.LAST",
         "PerPkg": "1",
@@ -2066,7 +1906,6 @@
     },
     {
         "BriefDescription": "IODC Conflicts: Remote InvItoE - Same RTID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x57",
         "EventName": "UNC_H_IODC_CONFLICTS.REMOTE_INVI2E_SAME_RTID",
         "PerPkg": "1",
@@ -2075,7 +1914,6 @@
     },
     {
         "BriefDescription": "IODC Conflicts: Remote (Other) - Same Addr",
-        "Counter": "0,1,2,3",
         "EventCode": "0x57",
         "EventName": "UNC_H_IODC_CONFLICTS.REMOTE_OTHER_SAME_ADDR",
         "PerPkg": "1",
@@ -2084,7 +1922,6 @@
     },
     {
         "BriefDescription": "IODC Inserts",
-        "Counter": "0,1,2,3",
         "EventCode": "0x56",
         "EventName": "UNC_H_IODC_INSERTS",
         "PerPkg": "1",
@@ -2093,7 +1930,6 @@
     },
     {
         "BriefDescription": "Num IODC 0 Length Writes",
-        "Counter": "0,1,2,3",
         "EventCode": "0x58",
         "EventName": "UNC_H_IODC_OLEN_WBMTOI",
         "PerPkg": "1",
@@ -2102,7 +1938,6 @@
     },
     {
         "BriefDescription": "OSB Snoop Broadcast; Local InvItoE",
-        "Counter": "0,1,2,3",
         "EventCode": "0x53",
         "EventName": "UNC_H_OSB.INVITOE_LOCAL",
         "PerPkg": "1",
@@ -2112,7 +1947,6 @@
     },
     {
         "BriefDescription": "OSB Snoop Broadcast; Local Reads",
-        "Counter": "0,1,2,3",
         "EventCode": "0x53",
         "EventName": "UNC_H_OSB.READS_LOCAL",
         "PerPkg": "1",
@@ -2122,7 +1956,6 @@
     },
     {
         "BriefDescription": "OSB Snoop Broadcast; Remote",
-        "Counter": "0,1,2,3",
         "EventCode": "0x53",
         "EventName": "UNC_H_OSB.REMOTE",
         "PerPkg": "1",
@@ -2132,7 +1965,6 @@
     },
     {
         "BriefDescription": "OSB Early Data Return; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "UNC_H_OSB_EDR.ALL",
         "PerPkg": "1",
@@ -2142,7 +1974,6 @@
     },
     {
         "BriefDescription": "OSB Early Data Return; Reads to Local  I",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "UNC_H_OSB_EDR.READS_LOCAL_I",
         "PerPkg": "1",
@@ -2152,7 +1983,6 @@
     },
     {
         "BriefDescription": "OSB Early Data Return; Reads to Local S",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "UNC_H_OSB_EDR.READS_LOCAL_S",
         "PerPkg": "1",
@@ -2162,7 +1992,6 @@
     },
     {
         "BriefDescription": "OSB Early Data Return; Reads to Remote I",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "UNC_H_OSB_EDR.READS_REMOTE_I",
         "PerPkg": "1",
@@ -2172,7 +2001,6 @@
     },
     {
         "BriefDescription": "OSB Early Data Return; Reads to Remote S",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "UNC_H_OSB_EDR.READS_REMOTE_S",
         "PerPkg": "1",
@@ -2182,7 +2010,6 @@
     },
     {
         "BriefDescription": "Read and Write Requests; Local InvItoEs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
         "PerPkg": "1",
@@ -2192,7 +2019,6 @@
     },
     {
         "BriefDescription": "Read and Write Requests; Remote InvItoEs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
         "PerPkg": "1",
@@ -2202,7 +2028,6 @@
     },
     {
         "BriefDescription": "Read and Write Requests; Reads",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_H_REQUESTS.READS",
         "PerPkg": "1",
@@ -2212,7 +2037,6 @@
     },
     {
         "BriefDescription": "Read and Write Requests; Local Reads",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_H_REQUESTS.READS_LOCAL",
         "PerPkg": "1",
@@ -2222,7 +2046,6 @@
     },
     {
         "BriefDescription": "Read and Write Requests; Remote Reads",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_H_REQUESTS.READS_REMOTE",
         "PerPkg": "1",
@@ -2232,17 +2055,15 @@
     },
     {
         "BriefDescription": "Read and Write Requests; Writes",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_H_REQUESTS.WRITES",
         "PerPkg": "1",
         "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).; Incoming write requests.",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Read and Write Requests; Local Writes",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
         "PerPkg": "1",
@@ -2252,7 +2073,6 @@
     },
     {
         "BriefDescription": "Read and Write Requests; Remote Writes",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_H_REQUESTS.WRITES_REMOTE",
         "PerPkg": "1",
@@ -2262,17 +2082,15 @@
     },
     {
         "BriefDescription": "HA AD Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3E",
         "EventName": "UNC_H_RING_AD_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
-        "UMask": "0xCC",
+        "UMask": "0xcc",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3e",
         "EventName": "UNC_H_RING_AD_USED.CCW_VR0_EVEN",
         "PerPkg": "1",
@@ -2282,7 +2100,6 @@
     },
     {
         "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3e",
         "EventName": "UNC_H_RING_AD_USED.CCW_VR0_ODD",
         "PerPkg": "1",
@@ -2292,7 +2109,6 @@
     },
     {
         "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3e",
         "EventName": "UNC_H_RING_AD_USED.CCW_VR1_EVEN",
         "PerPkg": "1",
@@ -2302,7 +2118,6 @@
     },
     {
         "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3e",
         "EventName": "UNC_H_RING_AD_USED.CCW_VR1_ODD",
         "PerPkg": "1",
@@ -2312,7 +2127,6 @@
     },
     {
         "BriefDescription": "HA AD Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3E",
         "EventName": "UNC_H_RING_AD_USED.CW",
         "PerPkg": "1",
@@ -2322,7 +2136,6 @@
     },
     {
         "BriefDescription": "HA AD Ring in Use; Clockwise and Even on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3e",
         "EventName": "UNC_H_RING_AD_USED.CW_VR0_EVEN",
         "PerPkg": "1",
@@ -2332,7 +2145,6 @@
     },
     {
         "BriefDescription": "HA AD Ring in Use; Clockwise and Odd on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3e",
         "EventName": "UNC_H_RING_AD_USED.CW_VR0_ODD",
         "PerPkg": "1",
@@ -2342,7 +2154,6 @@
     },
     {
         "BriefDescription": "HA AD Ring in Use; Clockwise and Even on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3e",
         "EventName": "UNC_H_RING_AD_USED.CW_VR1_EVEN",
         "PerPkg": "1",
@@ -2352,7 +2163,6 @@
     },
     {
         "BriefDescription": "HA AD Ring in Use; Clockwise and Odd on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3e",
         "EventName": "UNC_H_RING_AD_USED.CW_VR1_ODD",
         "PerPkg": "1",
@@ -2362,17 +2172,15 @@
     },
     {
         "BriefDescription": "HA AK Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3F",
         "EventName": "UNC_H_RING_AK_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
-        "UMask": "0xCC",
+        "UMask": "0xcc",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3f",
         "EventName": "UNC_H_RING_AK_USED.CCW_VR0_EVEN",
         "PerPkg": "1",
@@ -2382,7 +2190,6 @@
     },
     {
         "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3f",
         "EventName": "UNC_H_RING_AK_USED.CCW_VR0_ODD",
         "PerPkg": "1",
@@ -2392,7 +2199,6 @@
     },
     {
         "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3f",
         "EventName": "UNC_H_RING_AK_USED.CCW_VR1_EVEN",
         "PerPkg": "1",
@@ -2402,7 +2208,6 @@
     },
     {
         "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3f",
         "EventName": "UNC_H_RING_AK_USED.CCW_VR1_ODD",
         "PerPkg": "1",
@@ -2412,7 +2217,6 @@
     },
     {
         "BriefDescription": "HA AK Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3F",
         "EventName": "UNC_H_RING_AK_USED.CW",
         "PerPkg": "1",
@@ -2422,7 +2226,6 @@
     },
     {
         "BriefDescription": "HA AK Ring in Use; Clockwise and Even on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3f",
         "EventName": "UNC_H_RING_AK_USED.CW_VR0_EVEN",
         "PerPkg": "1",
@@ -2432,7 +2235,6 @@
     },
     {
         "BriefDescription": "HA AK Ring in Use; Clockwise and Odd on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3f",
         "EventName": "UNC_H_RING_AK_USED.CW_VR0_ODD",
         "PerPkg": "1",
@@ -2442,7 +2244,6 @@
     },
     {
         "BriefDescription": "HA AK Ring in Use; Clockwise and Even on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3f",
         "EventName": "UNC_H_RING_AK_USED.CW_VR1_EVEN",
         "PerPkg": "1",
@@ -2452,7 +2253,6 @@
     },
     {
         "BriefDescription": "HA AK Ring in Use; Clockwise and Odd on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3f",
         "EventName": "UNC_H_RING_AK_USED.CW_VR1_ODD",
         "PerPkg": "1",
@@ -2462,17 +2262,15 @@
     },
     {
         "BriefDescription": "HA BL Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
-        "UMask": "0xCC",
+        "UMask": "0xcc",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.CCW_VR0_EVEN",
         "PerPkg": "1",
@@ -2482,7 +2280,6 @@
     },
     {
         "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.CCW_VR0_ODD",
         "PerPkg": "1",
@@ -2492,7 +2289,6 @@
     },
     {
         "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.CCW_VR1_EVEN",
         "PerPkg": "1",
@@ -2502,7 +2298,6 @@
     },
     {
         "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.CCW_VR1_ODD",
         "PerPkg": "1",
@@ -2512,7 +2307,6 @@
     },
     {
         "BriefDescription": "HA BL Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.CW",
         "PerPkg": "1",
@@ -2522,7 +2316,6 @@
     },
     {
         "BriefDescription": "HA BL Ring in Use; Clockwise and Even on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.CW_VR0_EVEN",
         "PerPkg": "1",
@@ -2532,7 +2325,6 @@
     },
     {
         "BriefDescription": "HA BL Ring in Use; Clockwise and Odd on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.CW_VR0_ODD",
         "PerPkg": "1",
@@ -2542,7 +2334,6 @@
     },
     {
         "BriefDescription": "HA BL Ring in Use; Clockwise and Even on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.CW_VR1_EVEN",
         "PerPkg": "1",
@@ -2552,7 +2343,6 @@
     },
     {
         "BriefDescription": "HA BL Ring in Use; Clockwise and Odd on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.CW_VR1_ODD",
         "PerPkg": "1",
@@ -2562,7 +2352,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
         "PerPkg": "1",
@@ -2572,7 +2361,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
         "PerPkg": "1",
@@ -2582,7 +2370,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
         "PerPkg": "1",
@@ -2592,7 +2379,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
         "PerPkg": "1",
@@ -2602,7 +2388,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
         "PerPkg": "1",
@@ -2612,7 +2397,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
         "PerPkg": "1",
@@ -2622,7 +2406,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
         "PerPkg": "1",
@@ -2632,7 +2415,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
         "PerPkg": "1",
@@ -2642,7 +2424,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received; RSPCNFLCT*",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
         "PerPkg": "1",
@@ -2652,7 +2433,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received; RspI",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_H_SNOOP_RESP.RSPI",
         "PerPkg": "1",
@@ -2662,7 +2442,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received; RspIFwd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
         "PerPkg": "1",
@@ -2672,7 +2451,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received; RspS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_H_SNOOP_RESP.RSPS",
         "PerPkg": "1",
@@ -2682,7 +2460,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received; RspSFwd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
         "PerPkg": "1",
@@ -2692,7 +2469,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received; Rsp*Fwd*WB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
         "PerPkg": "1",
@@ -2702,7 +2478,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received; Rsp*WB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_H_SNOOP_RESP.RSP_WB",
         "PerPkg": "1",
@@ -2712,7 +2487,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received Local; Other",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER",
         "PerPkg": "1",
@@ -2722,7 +2496,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received Local; RspCnflct",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT",
         "PerPkg": "1",
@@ -2732,7 +2505,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received Local; RspI",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPI",
         "PerPkg": "1",
@@ -2742,7 +2514,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received Local; RspIFwd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD",
         "PerPkg": "1",
@@ -2752,7 +2523,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received Local; RspS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS",
         "PerPkg": "1",
@@ -2762,7 +2532,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received Local; RspSFwd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD",
         "PerPkg": "1",
@@ -2772,7 +2541,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB",
         "PerPkg": "1",
@@ -2782,7 +2550,6 @@
     },
     {
         "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB",
         "PerPkg": "1",
@@ -2792,7 +2559,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION0",
         "PerPkg": "1",
@@ -2802,7 +2568,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION1",
         "PerPkg": "1",
@@ -2812,7 +2577,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION2",
         "PerPkg": "1",
@@ -2822,7 +2586,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION3",
         "PerPkg": "1",
@@ -2832,7 +2595,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION4",
         "PerPkg": "1",
@@ -2842,7 +2604,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION5",
         "PerPkg": "1",
@@ -2852,7 +2613,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION6",
         "PerPkg": "1",
@@ -2862,7 +2622,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION7",
         "PerPkg": "1",
@@ -2872,7 +2631,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1c",
         "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10",
         "PerPkg": "1",
@@ -2882,7 +2640,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1c",
         "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11",
         "PerPkg": "1",
@@ -2892,7 +2649,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1c",
         "EventName": "UNC_H_TAD_REQUESTS_G1.REGION8",
         "PerPkg": "1",
@@ -2902,7 +2658,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1c",
         "EventName": "UNC_H_TAD_REQUESTS_G1.REGION9",
         "PerPkg": "1",
@@ -2912,7 +2667,6 @@
     },
     {
         "BriefDescription": "Tracker Cycles Not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_H_TRACKER_CYCLES_NE",
         "PerPkg": "1",
@@ -2921,7 +2675,6 @@
     },
     {
         "BriefDescription": "Outbound NDR Ring Transactions; Non-data Responses",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "UNC_H_TxR_AD.HOM",
         "PerPkg": "1",
@@ -2931,7 +2684,6 @@
     },
     {
         "BriefDescription": "AD Egress Full; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2a",
         "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL",
         "PerPkg": "1",
@@ -2941,7 +2693,6 @@
     },
     {
         "BriefDescription": "AD Egress Full; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2a",
         "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
         "PerPkg": "1",
@@ -2951,7 +2702,6 @@
     },
     {
         "BriefDescription": "AD Egress Full; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2a",
         "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
         "PerPkg": "1",
@@ -2961,7 +2711,6 @@
     },
     {
         "BriefDescription": "AD Egress Not Empty; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL",
         "PerPkg": "1",
@@ -2971,7 +2720,6 @@
     },
     {
         "BriefDescription": "AD Egress Not Empty; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0",
         "PerPkg": "1",
@@ -2981,7 +2729,6 @@
     },
     {
         "BriefDescription": "AD Egress Not Empty; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1",
         "PerPkg": "1",
@@ -2991,7 +2738,6 @@
     },
     {
         "BriefDescription": "AD Egress Allocations; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "UNC_H_TxR_AD_INSERTS.ALL",
         "PerPkg": "1",
@@ -3001,7 +2747,6 @@
     },
     {
         "BriefDescription": "AD Egress Allocations; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "UNC_H_TxR_AD_INSERTS.SCHED0",
         "PerPkg": "1",
@@ -3011,7 +2756,6 @@
     },
     {
         "BriefDescription": "AD Egress Allocations; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "UNC_H_TxR_AD_INSERTS.SCHED1",
         "PerPkg": "1",
@@ -3021,7 +2765,6 @@
     },
     {
         "BriefDescription": "AD Egress Occupancy; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "UNC_H_TxR_AD_OCCUPANCY.SCHED0",
         "PerPkg": "1",
@@ -3031,7 +2774,6 @@
     },
     {
         "BriefDescription": "AD Egress Occupancy; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "UNC_H_TxR_AD_OCCUPANCY.SCHED1",
         "PerPkg": "1",
@@ -3041,7 +2783,6 @@
     },
     {
         "BriefDescription": "Outbound Ring Transactions on AK: CRD Transactions to Cbo",
-        "Counter": "0,1,2,3",
         "EventCode": "0xe",
         "EventName": "UNC_H_TxR_AK.CRD_CBO",
         "PerPkg": "1",
@@ -3050,7 +2791,6 @@
     },
     {
         "BriefDescription": "AK Egress Full; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL",
         "PerPkg": "1",
@@ -3060,7 +2800,6 @@
     },
     {
         "BriefDescription": "AK Egress Full; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
         "PerPkg": "1",
@@ -3070,7 +2809,6 @@
     },
     {
         "BriefDescription": "AK Egress Full; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
         "PerPkg": "1",
@@ -3080,7 +2818,6 @@
     },
     {
         "BriefDescription": "AK Egress Not Empty; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL",
         "PerPkg": "1",
@@ -3090,7 +2827,6 @@
     },
     {
         "BriefDescription": "AK Egress Not Empty; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0",
         "PerPkg": "1",
@@ -3100,7 +2836,6 @@
     },
     {
         "BriefDescription": "AK Egress Not Empty; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1",
         "PerPkg": "1",
@@ -3110,7 +2845,6 @@
     },
     {
         "BriefDescription": "AK Egress Allocations; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2f",
         "EventName": "UNC_H_TxR_AK_INSERTS.ALL",
         "PerPkg": "1",
@@ -3120,7 +2854,6 @@
     },
     {
         "BriefDescription": "AK Egress Allocations; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2f",
         "EventName": "UNC_H_TxR_AK_INSERTS.SCHED0",
         "PerPkg": "1",
@@ -3130,7 +2863,6 @@
     },
     {
         "BriefDescription": "AK Egress Allocations; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2f",
         "EventName": "UNC_H_TxR_AK_INSERTS.SCHED1",
         "PerPkg": "1",
@@ -3140,7 +2872,6 @@
     },
     {
         "BriefDescription": "AK Egress Occupancy; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x30",
         "EventName": "UNC_H_TxR_AK_OCCUPANCY.SCHED0",
         "PerPkg": "1",
@@ -3150,7 +2881,6 @@
     },
     {
         "BriefDescription": "AK Egress Occupancy; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x30",
         "EventName": "UNC_H_TxR_AK_OCCUPANCY.SCHED1",
         "PerPkg": "1",
@@ -3160,7 +2890,6 @@
     },
     {
         "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_H_TxR_BL.DRS_CACHE",
         "PerPkg": "1",
@@ -3170,7 +2899,6 @@
     },
     {
         "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_H_TxR_BL.DRS_CORE",
         "PerPkg": "1",
@@ -3180,7 +2908,6 @@
     },
     {
         "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_H_TxR_BL.DRS_QPI",
         "PerPkg": "1",
@@ -3190,7 +2917,6 @@
     },
     {
         "BriefDescription": "BL Egress Full; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x36",
         "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL",
         "PerPkg": "1",
@@ -3200,7 +2926,6 @@
     },
     {
         "BriefDescription": "BL Egress Full; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x36",
         "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
         "PerPkg": "1",
@@ -3210,7 +2935,6 @@
     },
     {
         "BriefDescription": "BL Egress Full; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x36",
         "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
         "PerPkg": "1",
@@ -3220,7 +2944,6 @@
     },
     {
         "BriefDescription": "BL Egress Not Empty; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL",
         "PerPkg": "1",
@@ -3230,7 +2953,6 @@
     },
     {
         "BriefDescription": "BL Egress Not Empty; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0",
         "PerPkg": "1",
@@ -3240,7 +2962,6 @@
     },
     {
         "BriefDescription": "BL Egress Not Empty; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1",
         "PerPkg": "1",
@@ -3250,7 +2971,6 @@
     },
     {
         "BriefDescription": "BL Egress Allocations; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_H_TxR_BL_INSERTS.ALL",
         "PerPkg": "1",
@@ -3260,7 +2980,6 @@
     },
     {
         "BriefDescription": "BL Egress Allocations; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_H_TxR_BL_INSERTS.SCHED0",
         "PerPkg": "1",
@@ -3270,7 +2989,6 @@
     },
     {
         "BriefDescription": "BL Egress Allocations; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_H_TxR_BL_INSERTS.SCHED1",
         "PerPkg": "1",
@@ -3280,17 +2998,14 @@
     },
     {
         "BriefDescription": "BL Egress Occupancy: All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "UNC_H_TxR_BL_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "PublicDescription": "BL Egress Occupancy",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "BL Egress Occupancy; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "UNC_H_TxR_BL_OCCUPANCY.SCHED0",
         "PerPkg": "1",
@@ -3300,7 +3015,6 @@
     },
     {
         "BriefDescription": "BL Egress Occupancy; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "UNC_H_TxR_BL_OCCUPANCY.SCHED1",
         "PerPkg": "1",
@@ -3310,7 +3024,6 @@
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
         "PerPkg": "1",
@@ -3320,7 +3033,6 @@
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
         "PerPkg": "1",
@@ -3330,7 +3042,6 @@
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
         "PerPkg": "1",
@@ -3340,7 +3051,6 @@
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
         "PerPkg": "1",
@@ -3350,7 +3060,6 @@
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
         "PerPkg": "1",
@@ -3360,7 +3069,6 @@
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
         "PerPkg": "1",
@@ -3370,7 +3078,6 @@
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
         "PerPkg": "1",
@@ -3380,7 +3087,6 @@
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
         "PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.json
index 10ea4afeffc13..e1b9799e30365 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Number of qfclks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_Q_CLOCKTICKS",
         "PerPkg": "1",
@@ -10,17 +9,14 @@
     },
     {
         "BriefDescription": "Count of CTO Events",
-        "Counter": "0,1,2,3",
         "EventCode": "0x38",
         "EventName": "UNC_Q_CTO_COUNT",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots.  If both slots trigger in a given cycle, the event will increment by 2.  You can use edge detect to count the number of cases when both events triggered.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS",
         "PerPkg": "1",
@@ -30,7 +26,6 @@
     },
     {
         "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS",
         "PerPkg": "1",
@@ -40,7 +35,6 @@
     },
     {
         "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Invalid",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT",
         "PerPkg": "1",
@@ -50,7 +44,6 @@
     },
     {
         "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS",
         "PerPkg": "1",
@@ -60,7 +53,6 @@
     },
     {
         "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_DIRECT2CORE.FAILURE_MISS",
         "PerPkg": "1",
@@ -70,7 +62,6 @@
     },
     {
         "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Invalid",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT",
         "PerPkg": "1",
@@ -80,7 +71,6 @@
     },
     {
         "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss and Invalid",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS",
         "PerPkg": "1",
@@ -90,7 +80,6 @@
     },
     {
         "BriefDescription": "Direct 2 Core Spawning; Spawn Success",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT",
         "PerPkg": "1",
@@ -100,16 +89,212 @@
     },
     {
         "BriefDescription": "Cycles in L1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_Q_L1_POWER_CYCLES",
         "PerPkg": "1",
         "PublicDescription": "Number of QPI qfclk cycles spent in L1 power mode.  L1 is a mode that totally shuts down a QPI link.  Use edge detect to count the number of instances when the QPI link entered L1.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.",
         "Unit": "QPI LL"
     },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MATCH_MASK",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.DRS.AnyDataC",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.DRS.AnyResp",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.DRS.AnyResp11flits",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.DRS.AnyResp9flits",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.DRS.DataC_E",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.DRS.DataC_E_Cmp",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.DRS.DataC_E_FrcAckCnflt",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.DRS.DataC_F",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.DRS.DataC_F_Cmp",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.DRS.DataC_F_FrcAckCnflt",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.DRS.DataC_M",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.DRS.WbEData",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.DRS.WbIData",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.DRS.WbSData",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.HOM.AnyReq",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.HOM.AnyResp",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.HOM.RespFwd",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.HOM.RespFwdI",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.HOM.RespFwdIWb",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.HOM.RespFwdS",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.HOM.RespFwdSWb",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.HOM.RespIWb",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.HOM.RespSWb",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.NCB.AnyInt",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.NCB.AnyMsg",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.NCB.AnyMsg11flits",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.NCB.AnyMsg9flits",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.NCS.AnyMsg1or2flits",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.NCS.AnyMsg3flits",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.NCS.NcRd",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.NDR.AnyCmp",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
+    {
+        "EventCode": "0x38",
+        "EventName": "UNC_Q_MESSAGE.SNP.AnySnp",
+        "PerPkg": "1",
+        "Unit": "QPI LL"
+    },
     {
         "BriefDescription": "Cycles in L0p",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_Q_RxL0P_POWER_CYCLES",
         "PerPkg": "1",
@@ -118,7 +303,6 @@
     },
     {
         "BriefDescription": "Cycles in L0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xf",
         "EventName": "UNC_Q_RxL0_POWER_CYCLES",
         "PerPkg": "1",
@@ -127,7 +311,6 @@
     },
     {
         "BriefDescription": "Rx Flit Buffer Bypassed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_Q_RxL_BYPASSED",
         "PerPkg": "1",
@@ -136,7 +319,6 @@
     },
     {
         "BriefDescription": "CRC Errors Detected; LinkInit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT",
         "PerPkg": "1",
@@ -146,7 +328,6 @@
     },
     {
         "BriefDescription": "CRC Errors Detected; Normal Operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
         "PerPkg": "1",
@@ -156,10 +337,8 @@
     },
     {
         "BriefDescription": "VN0 Credit Consumed; DRS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1e",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the DRS message class.",
         "UMask": "0x1",
@@ -167,10 +346,8 @@
     },
     {
         "BriefDescription": "VN0 Credit Consumed; HOM",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1e",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the HOM message class.",
         "UMask": "0x8",
@@ -178,10 +355,8 @@
     },
     {
         "BriefDescription": "VN0 Credit Consumed; NCB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1e",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCB message class.",
         "UMask": "0x2",
@@ -189,10 +364,8 @@
     },
     {
         "BriefDescription": "VN0 Credit Consumed; NCS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1e",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCS message class.",
         "UMask": "0x4",
@@ -200,10 +373,8 @@
     },
     {
         "BriefDescription": "VN0 Credit Consumed; NDR",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1e",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NDR message class.",
         "UMask": "0x20",
@@ -211,10 +382,8 @@
     },
     {
         "BriefDescription": "VN0 Credit Consumed; SNP",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1e",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the SNP message class.",
         "UMask": "0x10",
@@ -222,10 +391,8 @@
     },
     {
         "BriefDescription": "VN1 Credit Consumed; DRS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the DRS message class.",
         "UMask": "0x1",
@@ -233,10 +400,8 @@
     },
     {
         "BriefDescription": "VN1 Credit Consumed; HOM",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the HOM message class.",
         "UMask": "0x8",
@@ -244,10 +409,8 @@
     },
     {
         "BriefDescription": "VN1 Credit Consumed; NCB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCB message class.",
         "UMask": "0x2",
@@ -255,10 +418,8 @@
     },
     {
         "BriefDescription": "VN1 Credit Consumed; NCS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCS message class.",
         "UMask": "0x4",
@@ -266,10 +427,8 @@
     },
     {
         "BriefDescription": "VN1 Credit Consumed; NDR",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NDR message class.",
         "UMask": "0x20",
@@ -277,10 +436,8 @@
     },
     {
         "BriefDescription": "VN1 Credit Consumed; SNP",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the SNP message class.",
         "UMask": "0x10",
@@ -288,17 +445,14 @@
     },
     {
         "BriefDescription": "VNA Credit Consumed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1d",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0xa",
         "EventName": "UNC_Q_RxL_CYCLES_NE",
         "PerPkg": "1",
@@ -307,10 +461,8 @@
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors DRS flits only.",
         "UMask": "0x1",
@@ -318,10 +470,8 @@
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors DRS flits only.",
         "UMask": "0x2",
@@ -329,10 +479,8 @@
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors HOM flits only.",
         "UMask": "0x1",
@@ -340,10 +488,8 @@
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors HOM flits only.",
         "UMask": "0x2",
@@ -351,10 +497,8 @@
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCB flits only.",
         "UMask": "0x1",
@@ -362,10 +506,8 @@
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCB flits only.",
         "UMask": "0x2",
@@ -373,10 +515,8 @@
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x11",
         "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCS flits only.",
         "UMask": "0x1",
@@ -384,10 +524,8 @@
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x11",
         "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NCS flits only.",
         "UMask": "0x2",
@@ -395,10 +533,8 @@
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NDR flits only.",
         "UMask": "0x1",
@@ -406,10 +542,8 @@
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors NDR flits only.",
         "UMask": "0x2",
@@ -417,10 +551,8 @@
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors SNP flits only.",
         "UMask": "0x1",
@@ -428,10 +560,8 @@
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.  This monitors SNP flits only.",
         "UMask": "0x2",
@@ -439,7 +569,6 @@
     },
     {
         "BriefDescription": "Flits Received - Group 0; Data Tx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_Q_RxL_FLITS_G0.DATA",
         "PerPkg": "1",
@@ -449,7 +578,6 @@
     },
     {
         "BriefDescription": "Flits Received - Group 0; Idle and Null Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_Q_RxL_FLITS_G0.IDLE",
         "PerPkg": "1",
@@ -459,7 +587,6 @@
     },
     {
         "BriefDescription": "Flits Received - Group 0; Non-Data protocol Tx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_Q_RxL_FLITS_G0.NON_DATA",
         "PerPkg": "1",
@@ -469,10 +596,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_Q_RxL_FLITS_G1.DRS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits received over the NCB channel which transmits non-coherent data.",
         "UMask": "0x18",
@@ -480,10 +605,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 1; DRS Data Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits received over the NCB channel which transmits non-coherent data.  This includes only the data flits (not the header).",
         "UMask": "0x8",
@@ -491,10 +614,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 1; DRS Header Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits received over the NCB channel which transmits non-coherent data.  This includes only the header flits (not the data).  This includes extended headers.",
         "UMask": "0x10",
@@ -502,10 +623,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 1; HOM Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_Q_RxL_FLITS_G1.HOM",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel.",
         "UMask": "0x6",
@@ -513,10 +632,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel.  These are most commonly snoop responses, and this event can be used as a proxy for that.",
         "UMask": "0x4",
@@ -524,10 +641,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 1; HOM Request Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel.  This basically counts the number of remote memory requests received over QPI.  In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.",
         "UMask": "0x2",
@@ -535,10 +650,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 1; SNP Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_Q_RxL_FLITS_G1.SNP",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI.  These requests are contained in the snoop channel.  This does not include snoop responses, which are received on the home channel.",
         "UMask": "0x1",
@@ -546,21 +659,17 @@
     },
     {
         "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_Q_RxL_FLITS_G2.NCB",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits.  These packets are generally used to transmit non-coherent data across QPI.",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Flits Received - Group 2; Non-Coherent data Rx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits.  These flits are generally used to transmit non-coherent data across QPI.  This does not include a count of the DRS (coherent) data flits.  This only counts the data flits, not the NCB headers.",
         "UMask": "0x4",
@@ -568,10 +677,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 2; Non-Coherent non-data Rx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits.  These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits.  This includes extended headers.",
         "UMask": "0x8",
@@ -579,10 +686,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_Q_RxL_FLITS_G2.NCS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI.    This includes extended headers.",
         "UMask": "0x10",
@@ -590,10 +695,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets to the local socket which use the AK ring.",
         "UMask": "0x1",
@@ -601,10 +704,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets destined for Route-thru to a remote socket.",
         "UMask": "0x2",
@@ -612,7 +713,6 @@
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_Q_RxL_INSERTS",
         "PerPkg": "1",
@@ -621,20 +721,16 @@
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - DRS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_Q_RxL_INSERTS_DRS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only DRS flits.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_Q_RxL_INSERTS_DRS.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only DRS flits.",
         "UMask": "0x1",
@@ -642,10 +738,8 @@
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_Q_RxL_INSERTS_DRS.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only DRS flits.",
         "UMask": "0x2",
@@ -653,20 +747,16 @@
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - HOM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc",
         "EventName": "UNC_Q_RxL_INSERTS_HOM",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only HOM flits.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC",
         "EventName": "UNC_Q_RxL_INSERTS_HOM.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only HOM flits.",
         "UMask": "0x1",
@@ -674,10 +764,8 @@
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC",
         "EventName": "UNC_Q_RxL_INSERTS_HOM.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only HOM flits.",
         "UMask": "0x2",
@@ -685,20 +773,16 @@
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - NCB",
-        "Counter": "0,1,2,3",
         "EventCode": "0xa",
         "EventName": "UNC_Q_RxL_INSERTS_NCB",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCB flits.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_Q_RxL_INSERTS_NCB.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCB flits.",
         "UMask": "0x1",
@@ -706,10 +790,8 @@
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_Q_RxL_INSERTS_NCB.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCB flits.",
         "UMask": "0x2",
@@ -717,20 +799,16 @@
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - NCS",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb",
         "EventName": "UNC_Q_RxL_INSERTS_NCS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCS flits.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB",
         "EventName": "UNC_Q_RxL_INSERTS_NCS.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCS flits.",
         "UMask": "0x1",
@@ -738,10 +816,8 @@
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB",
         "EventName": "UNC_Q_RxL_INSERTS_NCS.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCS flits.",
         "UMask": "0x2",
@@ -749,20 +825,16 @@
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - NDR",
-        "Counter": "0,1,2,3",
         "EventCode": "0xe",
         "EventName": "UNC_Q_RxL_INSERTS_NDR",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NDR flits.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE",
         "EventName": "UNC_Q_RxL_INSERTS_NDR.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NDR flits.",
         "UMask": "0x1",
@@ -770,10 +842,8 @@
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE",
         "EventName": "UNC_Q_RxL_INSERTS_NDR.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NDR flits.",
         "UMask": "0x2",
@@ -781,20 +851,16 @@
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - SNP",
-        "Counter": "0,1,2,3",
         "EventCode": "0xd",
         "EventName": "UNC_Q_RxL_INSERTS_SNP",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only SNP flits.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD",
         "EventName": "UNC_Q_RxL_INSERTS_SNP.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only SNP flits.",
         "UMask": "0x1",
@@ -802,10 +868,8 @@
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD",
         "EventName": "UNC_Q_RxL_INSERTS_SNP.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only SNP flits.",
         "UMask": "0x2",
@@ -813,7 +877,6 @@
     },
     {
         "BriefDescription": "RxQ Occupancy - All Packets",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb",
         "EventName": "UNC_Q_RxL_OCCUPANCY",
         "PerPkg": "1",
@@ -822,20 +885,16 @@
     },
     {
         "BriefDescription": "RxQ Occupancy - DRS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_Q_RxL_OCCUPANCY_DRS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors DRS flits only.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - DRS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors DRS flits only.",
         "UMask": "0x1",
@@ -843,10 +902,8 @@
     },
     {
         "BriefDescription": "RxQ Occupancy - DRS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors DRS flits only.",
         "UMask": "0x2",
@@ -854,20 +911,16 @@
     },
     {
         "BriefDescription": "RxQ Occupancy - HOM",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_Q_RxL_OCCUPANCY_HOM",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors HOM flits only.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - HOM; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors HOM flits only.",
         "UMask": "0x1",
@@ -875,10 +928,8 @@
     },
     {
         "BriefDescription": "RxQ Occupancy - HOM; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors HOM flits only.",
         "UMask": "0x2",
@@ -886,20 +937,16 @@
     },
     {
         "BriefDescription": "RxQ Occupancy - NCB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NCB",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCB flits only.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - NCB; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCB flits only.",
         "UMask": "0x1",
@@ -907,10 +954,8 @@
     },
     {
         "BriefDescription": "RxQ Occupancy - NCB; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCB flits only.",
         "UMask": "0x2",
@@ -918,20 +963,16 @@
     },
     {
         "BriefDescription": "RxQ Occupancy - NCS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x17",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NCS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCS flits only.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - NCS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x17",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCS flits only.",
         "UMask": "0x1",
@@ -939,10 +980,8 @@
     },
     {
         "BriefDescription": "RxQ Occupancy - NCS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x17",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCS flits only.",
         "UMask": "0x2",
@@ -950,20 +989,16 @@
     },
     {
         "BriefDescription": "RxQ Occupancy - NDR",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1a",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NDR",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NDR flits only.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - NDR; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1A",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NDR flits only.",
         "UMask": "0x1",
@@ -971,10 +1006,8 @@
     },
     {
         "BriefDescription": "RxQ Occupancy - NDR; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1A",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NDR flits only.",
         "UMask": "0x2",
@@ -982,20 +1015,16 @@
     },
     {
         "BriefDescription": "RxQ Occupancy - SNP",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_Q_RxL_OCCUPANCY_SNP",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors SNP flits only.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - SNP; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors SNP flits only.",
         "UMask": "0x1",
@@ -1003,10 +1032,8 @@
     },
     {
         "BriefDescription": "RxQ Occupancy - SNP; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors SNP flits only.",
         "UMask": "0x2",
@@ -1014,10 +1041,8 @@
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - HOM",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_DRS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the HOM message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
         "UMask": "0x1",
@@ -1025,10 +1050,8 @@
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - DRS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the DRS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
         "UMask": "0x8",
@@ -1036,10 +1059,8 @@
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - SNP",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCB",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the SNP message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
         "UMask": "0x2",
@@ -1047,10 +1068,8 @@
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NDR",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NDR message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
         "UMask": "0x4",
@@ -1058,10 +1077,8 @@
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
         "UMask": "0x20",
@@ -1069,10 +1086,8 @@
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_SNP",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCB message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
         "UMask": "0x10",
@@ -1080,10 +1095,8 @@
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN0; Egress Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet because there were insufficient BGF credits.  For details on a message class granularity, use the Egress Credit Occupancy events.",
         "UMask": "0x40",
@@ -1091,10 +1104,8 @@
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN0; GV",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_Q_RxL_STALLS_VN0.GV",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled because a GV transition (frequency transition) was taking place.",
         "UMask": "0x80",
@@ -1102,10 +1113,8 @@
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - HOM",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3a",
         "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_DRS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the HOM message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
         "UMask": "0x1",
@@ -1113,10 +1122,8 @@
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - DRS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3a",
         "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the DRS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
         "UMask": "0x8",
@@ -1124,10 +1131,8 @@
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - SNP",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3a",
         "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCB",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the SNP message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
         "UMask": "0x2",
@@ -1135,10 +1140,8 @@
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NDR",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3a",
         "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NDR message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
         "UMask": "0x4",
@@ -1146,10 +1149,8 @@
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3a",
         "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCS message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
         "UMask": "0x20",
@@ -1157,10 +1158,8 @@
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3a",
         "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_SNP",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCB message class because there were not enough BGF credits.  In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
         "UMask": "0x10",
@@ -1168,7 +1167,6 @@
     },
     {
         "BriefDescription": "Cycles in L0p",
-        "Counter": "0,1,2,3",
         "EventCode": "0xd",
         "EventName": "UNC_Q_TxL0P_POWER_CYCLES",
         "PerPkg": "1",
@@ -1177,7 +1175,6 @@
     },
     {
         "BriefDescription": "Cycles in L0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc",
         "EventName": "UNC_Q_TxL0_POWER_CYCLES",
         "PerPkg": "1",
@@ -1186,7 +1183,6 @@
     },
     {
         "BriefDescription": "Tx Flit Buffer Bypassed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_Q_TxL_BYPASSED",
         "PerPkg": "1",
@@ -1195,7 +1191,6 @@
     },
     {
         "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL",
         "PerPkg": "1",
@@ -1205,7 +1200,6 @@
     },
     {
         "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL",
         "PerPkg": "1",
@@ -1215,7 +1209,6 @@
     },
     {
         "BriefDescription": "Tx Flit Buffer Cycles not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_Q_TxL_CYCLES_NE",
         "PerPkg": "1",
@@ -1224,7 +1217,6 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G0.DATA",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI.  Each flit contains 64b of data.  This includes both DRS and NCB data flits (coherent and non-coherent).  This can be used to calculate the data bandwidth of the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This does not include the header flits that go in data packets.",
@@ -1233,7 +1225,6 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI.  This basically tracks the protocol overhead on the QPI link.  One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits.  This includes the header flits for data packets.",
@@ -1242,9 +1233,7 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G1.DRS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.",
         "UMask": "0x18",
@@ -1252,9 +1241,7 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits transmitted over the NCB channel which transmits non-coherent data.  This includes only the data flits (not the header).",
         "UMask": "0x8",
@@ -1262,9 +1249,7 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel.  DRS flits are used to transmit data with coherency.  This does not count data flits transmitted over the NCB channel which transmits non-coherent data.  This includes only the header flits (not the data).  This includes extended headers.",
         "UMask": "0x10",
@@ -1272,9 +1257,7 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 1; HOM Flits",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G1.HOM",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel.",
         "UMask": "0x6",
@@ -1282,9 +1265,7 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel.  These are most commonly snoop responses, and this event can be used as a proxy for that.",
         "UMask": "0x4",
@@ -1292,9 +1273,7 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel.  This basically counts the number of remote memory requests transmitted over QPI.  In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.",
         "UMask": "0x2",
@@ -1302,9 +1281,7 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 1; SNP Flits",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G1.SNP",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI.  These requests are contained in the snoop channel.  This does not include snoop responses, which are transmitted on the home channel.",
         "UMask": "0x1",
@@ -1312,21 +1289,17 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_Q_TxL_FLITS_G2.NCB",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits.  These packets are generally used to transmit non-coherent data across QPI.",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Flits Transferred - Group 2; Non-Coherent data Tx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits.  These flits are generally used to transmit non-coherent data across QPI.  This does not include a count of the DRS (coherent) data flits.  This only counts the data flits, not the NCB headers.",
         "UMask": "0x4",
@@ -1334,10 +1307,8 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 2; Non-Coherent non-data Tx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits.  These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits.  This includes extended headers.",
         "UMask": "0x8",
@@ -1345,10 +1316,8 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_Q_TxL_FLITS_G2.NCS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI.    This includes extended headers.",
         "UMask": "0x10",
@@ -1356,10 +1325,8 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets to the local socket which use the AK ring.",
         "UMask": "0x1",
@@ -1367,10 +1334,8 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  This is one of three groups that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each flit is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits.  Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as data bandwidth.  For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information.  To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel.  This channel is used to send a variety of protocol flits including grants and completions.  This is only for NDR packets destined for Route-thru to a remote socket.",
         "UMask": "0x2",
@@ -1378,7 +1343,6 @@
     },
     {
         "BriefDescription": "Tx Flit Buffer Allocations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_Q_TxL_INSERTS",
         "PerPkg": "1",
@@ -1387,7 +1351,6 @@
     },
     {
         "BriefDescription": "Tx Flit Buffer Occupancy",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_Q_TxL_OCCUPANCY",
         "PerPkg": "1",
@@ -1396,10 +1359,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.",
         "UMask": "0x1",
@@ -1407,10 +1368,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.",
         "UMask": "0x2",
@@ -1418,10 +1377,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO for HOM messages on AD.",
         "UMask": "0x1",
@@ -1429,10 +1386,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO for HOM messages on AD.",
         "UMask": "0x2",
@@ -1440,10 +1395,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for NDR messages on AD.",
         "UMask": "0x1",
@@ -1451,10 +1404,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for NDR messages on AD.",
         "UMask": "0x2",
@@ -1462,10 +1413,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO  for NDR messages on AD.",
         "UMask": "0x1",
@@ -1473,10 +1422,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO  for NDR messages on AD.",
         "UMask": "0x2",
@@ -1484,10 +1431,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for Snoop messages on AD.",
         "UMask": "0x1",
@@ -1495,10 +1440,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle.  Flow Control FIFO for Snoop messages on AD.",
         "UMask": "0x2",
@@ -1506,10 +1449,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x23",
         "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO for Snoop messages on AD.",
         "UMask": "0x1",
@@ -1517,10 +1458,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x23",
         "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle.  Flow Control FIFO for Snoop messages on AD.",
         "UMask": "0x2",
@@ -1528,20 +1467,16 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.",
         "UMask": "0x1",
@@ -1549,10 +1484,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.",
         "UMask": "0x2",
@@ -1560,20 +1493,16 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR",
-        "Counter": "0,1,2,3",
         "EventCode": "0x25",
         "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  Local NDR message class to AK Egress.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x25",
         "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  Local NDR message class to AK Egress.",
         "UMask": "0x1",
@@ -1581,10 +1510,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x25",
         "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  Local NDR message class to AK Egress.",
         "UMask": "0x2",
@@ -1592,10 +1519,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2a",
         "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
         "UMask": "0x1",
@@ -1603,10 +1528,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2a",
         "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
         "UMask": "0x2",
@@ -1614,10 +1537,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for Shared VN",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2a",
         "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
         "UMask": "0x4",
@@ -1625,10 +1546,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1f",
         "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  DRS message class to BL Egress.",
         "UMask": "0x1",
@@ -1636,10 +1555,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1f",
         "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  DRS message class to BL Egress.",
         "UMask": "0x2",
@@ -1647,10 +1564,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for Shared VN",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1f",
         "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  DRS message class to BL Egress.",
         "UMask": "0x4",
@@ -1658,10 +1573,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2b",
         "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.",
         "UMask": "0x1",
@@ -1669,10 +1582,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2b",
         "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.",
         "UMask": "0x2",
@@ -1680,10 +1591,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCB message class to BL Egress.",
         "UMask": "0x1",
@@ -1691,10 +1600,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCB message class to BL Egress.",
         "UMask": "0x2",
@@ -1702,10 +1609,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2c",
         "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.",
         "UMask": "0x1",
@@ -1713,10 +1618,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2c",
         "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.",
         "UMask": "0x2",
@@ -1724,10 +1627,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCS message class to BL Egress.",
         "UMask": "0x1",
@@ -1735,10 +1636,8 @@
     },
     {
         "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle.  NCS message class to BL Egress.",
         "UMask": "0x2",
@@ -1746,20 +1645,16 @@
     },
     {
         "BriefDescription": "VNA Credits Returned",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1c",
         "EventName": "UNC_Q_VNA_CREDIT_RETURNS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of VNA credits returned.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "VNA Credits Pending Return - Occupancy",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.",
         "Unit": "QPI LL"
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-memory.json b/tools/perf/pmu-events/arch/x86/ivytown/uncore-memory.json
index ed60ebca35cb8..65509342d56a7 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-memory.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "DRAM Activate Count; Activate due to Write",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_M_ACT_COUNT.BYP",
         "PerPkg": "1",
@@ -11,7 +10,6 @@
     },
     {
         "BriefDescription": "DRAM Activate Count; Activate due to Read",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_M_ACT_COUNT.RD",
         "PerPkg": "1",
@@ -21,7 +19,6 @@
     },
     {
         "BriefDescription": "DRAM Activate Count; Activate due to Write",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_M_ACT_COUNT.WR",
         "PerPkg": "1",
@@ -31,7 +28,6 @@
     },
     {
         "BriefDescription": "ACT command issued by 2 cycle bypass",
-        "Counter": "0,1,2,3",
         "EventCode": "0xa1",
         "EventName": "UNC_M_BYP_CMDS.ACT",
         "PerPkg": "1",
@@ -40,7 +36,6 @@
     },
     {
         "BriefDescription": "CAS command issued by 2 cycle bypass",
-        "Counter": "0,1,2,3",
         "EventCode": "0xa1",
         "EventName": "UNC_M_BYP_CMDS.CAS",
         "PerPkg": "1",
@@ -49,7 +44,6 @@
     },
     {
         "BriefDescription": "PRE command issued by 2 cycle bypass",
-        "Counter": "0,1,2,3",
         "EventCode": "0xa1",
         "EventName": "UNC_M_BYP_CMDS.PRE",
         "PerPkg": "1",
@@ -58,17 +52,15 @@
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.ALL",
         "PerPkg": "1",
         "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS commands issued on this channel.",
-        "UMask": "0xF",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.RD",
         "PerPkg": "1",
@@ -78,7 +70,6 @@
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.RD_REG",
         "PerPkg": "1",
@@ -88,17 +79,14 @@
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.RD_RMM",
         "PerPkg": "1",
-        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
         "UMask": "0x20",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
         "PerPkg": "1",
@@ -108,27 +96,23 @@
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.RD_WMM",
         "PerPkg": "1",
-        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
         "UMask": "0x10",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.WR",
         "PerPkg": "1",
         "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel.",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.WR_RMM",
         "PerPkg": "1",
@@ -138,7 +122,6 @@
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.WR_WMM",
         "PerPkg": "1",
@@ -148,14 +131,12 @@
     },
     {
         "BriefDescription": "DRAM Clockticks",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_M_DCLOCKTICKS",
         "PerPkg": "1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM Precharge All Commands",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_M_DRAM_PRE_ALL",
         "PerPkg": "1",
@@ -164,7 +145,6 @@
     },
     {
         "BriefDescription": "Number of DRAM Refreshes Issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_M_DRAM_REFRESH.HIGH",
         "PerPkg": "1",
@@ -174,7 +154,6 @@
     },
     {
         "BriefDescription": "Number of DRAM Refreshes Issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_M_DRAM_REFRESH.PANIC",
         "PerPkg": "1",
@@ -184,7 +163,6 @@
     },
     {
         "BriefDescription": "ECC Correctable Errors",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
         "PerPkg": "1",
@@ -193,7 +171,6 @@
     },
     {
         "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_M_MAJOR_MODES.ISOCH",
         "PerPkg": "1",
@@ -203,7 +180,6 @@
     },
     {
         "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
         "PerPkg": "1",
@@ -213,7 +189,6 @@
     },
     {
         "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_M_MAJOR_MODES.READ",
         "PerPkg": "1",
@@ -223,7 +198,6 @@
     },
     {
         "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_M_MAJOR_MODES.WRITE",
         "PerPkg": "1",
@@ -233,7 +207,6 @@
     },
     {
         "BriefDescription": "Channel DLLOFF Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x84",
         "EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
         "PerPkg": "1",
@@ -242,7 +215,6 @@
     },
     {
         "BriefDescription": "Channel PPD Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "UNC_M_POWER_CHANNEL_PPD",
         "PerPkg": "1",
@@ -251,7 +223,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
         "PerPkg": "1",
@@ -261,7 +232,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
         "PerPkg": "1",
@@ -271,7 +241,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
         "PerPkg": "1",
@@ -281,7 +250,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
         "PerPkg": "1",
@@ -291,7 +259,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
         "PerPkg": "1",
@@ -301,7 +268,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
         "PerPkg": "1",
@@ -311,7 +277,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
         "PerPkg": "1",
@@ -321,7 +286,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
         "PerPkg": "1",
@@ -331,16 +295,20 @@
     },
     {
         "BriefDescription": "Critical Throttle Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x86",
         "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles when the iMC is in critical thermal throttling.  When this happens, all traffic is blocked.  This should be rare unless something bad is going on in the platform.  There is no filtering by rank for this event.",
         "Unit": "iMC"
     },
+    {
+        "EventCode": "0x42",
+        "EventName": "UNC_M_POWER_PCU_THROTTLING",
+        "PerPkg": "1",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "Clock-Enabled Self-Refresh",
-        "Counter": "0,1,2,3",
         "EventCode": "0x43",
         "EventName": "UNC_M_POWER_SELF_REFRESH",
         "PerPkg": "1",
@@ -349,7 +317,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
         "PerPkg": "1",
@@ -359,7 +326,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
         "PerPkg": "1",
@@ -369,7 +335,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
         "PerPkg": "1",
@@ -379,7 +344,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
         "PerPkg": "1",
@@ -389,7 +353,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
         "PerPkg": "1",
@@ -399,7 +362,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
         "PerPkg": "1",
@@ -409,7 +371,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
         "PerPkg": "1",
@@ -419,7 +380,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
         "PerPkg": "1",
@@ -429,7 +389,6 @@
     },
     {
         "BriefDescription": "Read Preemption Count; Read over Read Preemption",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
         "PerPkg": "1",
@@ -439,7 +398,6 @@
     },
     {
         "BriefDescription": "Read Preemption Count; Read over Write Preemption",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
         "PerPkg": "1",
@@ -449,7 +407,6 @@
     },
     {
         "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_M_PRE_COUNT.BYP",
         "PerPkg": "1",
@@ -459,7 +416,6 @@
     },
     {
         "BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
         "PerPkg": "1",
@@ -469,7 +425,6 @@
     },
     {
         "BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
         "PerPkg": "1",
@@ -479,7 +434,6 @@
     },
     {
         "BriefDescription": "DRAM Precharge commands.; Precharge due to read",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_M_PRE_COUNT.RD",
         "PerPkg": "1",
@@ -489,7 +443,6 @@
     },
     {
         "BriefDescription": "DRAM Precharge commands.; Precharge due to write",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_M_PRE_COUNT.WR",
         "PerPkg": "1",
@@ -499,7 +452,6 @@
     },
     {
         "BriefDescription": "Read CAS issued with HIGH priority",
-        "Counter": "0,1,2,3",
         "EventCode": "0xa0",
         "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
         "PerPkg": "1",
@@ -508,7 +460,6 @@
     },
     {
         "BriefDescription": "Read CAS issued with LOW priority",
-        "Counter": "0,1,2,3",
         "EventCode": "0xa0",
         "EventName": "UNC_M_RD_CAS_PRIO.LOW",
         "PerPkg": "1",
@@ -517,7 +468,6 @@
     },
     {
         "BriefDescription": "Read CAS issued with MEDIUM priority",
-        "Counter": "0,1,2,3",
         "EventCode": "0xa0",
         "EventName": "UNC_M_RD_CAS_PRIO.MED",
         "PerPkg": "1",
@@ -526,7 +476,6 @@
     },
     {
         "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xa0",
         "EventName": "UNC_M_RD_CAS_PRIO.PANIC",
         "PerPkg": "1",
@@ -535,7 +484,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK0",
         "PerPkg": "1",
@@ -544,7 +492,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK1",
         "PerPkg": "1",
@@ -553,7 +500,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK2",
         "PerPkg": "1",
@@ -562,7 +508,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK3",
         "PerPkg": "1",
@@ -571,7 +516,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK4",
         "PerPkg": "1",
@@ -580,7 +524,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK5",
         "PerPkg": "1",
@@ -589,7 +532,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK6",
         "PerPkg": "1",
@@ -598,7 +540,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK7",
         "PerPkg": "1",
@@ -607,7 +548,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK0",
         "PerPkg": "1",
@@ -616,7 +556,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK1",
         "PerPkg": "1",
@@ -625,7 +564,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK2",
         "PerPkg": "1",
@@ -634,7 +572,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK3",
         "PerPkg": "1",
@@ -643,7 +580,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK4",
         "PerPkg": "1",
@@ -652,7 +588,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK5",
         "PerPkg": "1",
@@ -661,7 +596,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK6",
         "PerPkg": "1",
@@ -670,7 +604,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK7",
         "PerPkg": "1",
@@ -679,7 +612,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 2; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_M_RD_CAS_RANK2.BANK0",
         "PerPkg": "1",
@@ -688,7 +620,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 2; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_M_RD_CAS_RANK2.BANK1",
         "PerPkg": "1",
@@ -697,7 +628,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 2; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_M_RD_CAS_RANK2.BANK2",
         "PerPkg": "1",
@@ -706,7 +636,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 2; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_M_RD_CAS_RANK2.BANK3",
         "PerPkg": "1",
@@ -715,7 +644,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 2; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_M_RD_CAS_RANK2.BANK4",
         "PerPkg": "1",
@@ -724,7 +652,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 2; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_M_RD_CAS_RANK2.BANK5",
         "PerPkg": "1",
@@ -733,7 +660,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 2; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_M_RD_CAS_RANK2.BANK6",
         "PerPkg": "1",
@@ -742,7 +668,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 2; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_M_RD_CAS_RANK2.BANK7",
         "PerPkg": "1",
@@ -751,7 +676,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 3; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_M_RD_CAS_RANK3.BANK0",
         "PerPkg": "1",
@@ -760,7 +684,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 3; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_M_RD_CAS_RANK3.BANK1",
         "PerPkg": "1",
@@ -769,7 +692,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 3; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_M_RD_CAS_RANK3.BANK2",
         "PerPkg": "1",
@@ -778,7 +700,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 3; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_M_RD_CAS_RANK3.BANK3",
         "PerPkg": "1",
@@ -787,7 +708,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 3; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_M_RD_CAS_RANK3.BANK4",
         "PerPkg": "1",
@@ -796,7 +716,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 3; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_M_RD_CAS_RANK3.BANK5",
         "PerPkg": "1",
@@ -805,7 +724,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 3; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_M_RD_CAS_RANK3.BANK6",
         "PerPkg": "1",
@@ -814,7 +732,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 3; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_M_RD_CAS_RANK3.BANK7",
         "PerPkg": "1",
@@ -823,7 +740,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK0",
         "PerPkg": "1",
@@ -832,7 +748,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK1",
         "PerPkg": "1",
@@ -841,7 +756,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK2",
         "PerPkg": "1",
@@ -850,7 +764,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK3",
         "PerPkg": "1",
@@ -859,7 +772,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK4",
         "PerPkg": "1",
@@ -868,7 +780,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK5",
         "PerPkg": "1",
@@ -877,7 +788,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK6",
         "PerPkg": "1",
@@ -886,7 +796,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK7",
         "PerPkg": "1",
@@ -895,7 +804,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK0",
         "PerPkg": "1",
@@ -904,7 +812,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK1",
         "PerPkg": "1",
@@ -913,7 +820,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK2",
         "PerPkg": "1",
@@ -922,7 +828,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK3",
         "PerPkg": "1",
@@ -931,7 +836,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK4",
         "PerPkg": "1",
@@ -940,7 +844,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK5",
         "PerPkg": "1",
@@ -949,7 +852,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK6",
         "PerPkg": "1",
@@ -958,7 +860,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK7",
         "PerPkg": "1",
@@ -967,7 +868,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK0",
         "PerPkg": "1",
@@ -976,7 +876,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK1",
         "PerPkg": "1",
@@ -985,7 +884,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK2",
         "PerPkg": "1",
@@ -994,7 +892,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK3",
         "PerPkg": "1",
@@ -1003,7 +900,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK4",
         "PerPkg": "1",
@@ -1012,7 +908,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK5",
         "PerPkg": "1",
@@ -1021,7 +916,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK6",
         "PerPkg": "1",
@@ -1030,7 +924,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK7",
         "PerPkg": "1",
@@ -1039,7 +932,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK0",
         "PerPkg": "1",
@@ -1048,7 +940,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK1",
         "PerPkg": "1",
@@ -1057,7 +948,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK2",
         "PerPkg": "1",
@@ -1066,7 +956,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK3",
         "PerPkg": "1",
@@ -1075,7 +964,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK4",
         "PerPkg": "1",
@@ -1084,7 +972,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK5",
         "PerPkg": "1",
@@ -1093,7 +980,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK6",
         "PerPkg": "1",
@@ -1102,7 +988,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK7",
         "PerPkg": "1",
@@ -1111,7 +996,6 @@
     },
     {
         "BriefDescription": "Read Pending Queue Not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0x11",
         "EventName": "UNC_M_RPQ_CYCLES_NE",
         "PerPkg": "1",
@@ -1120,7 +1004,6 @@
     },
     {
         "BriefDescription": "Read Pending Queue Allocations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_M_RPQ_INSERTS",
         "PerPkg": "1",
@@ -1129,7 +1012,6 @@
     },
     {
         "BriefDescription": "VMSE MXB write buffer occupancy",
-        "Counter": "0,1,2,3",
         "EventCode": "0x91",
         "EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY",
         "PerPkg": "1",
@@ -1137,7 +1019,6 @@
     },
     {
         "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in RMM",
-        "Counter": "0,1,2,3",
         "EventCode": "0x90",
         "EventName": "UNC_M_VMSE_WR_PUSH.RMM",
         "PerPkg": "1",
@@ -1146,7 +1027,6 @@
     },
     {
         "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in WMM",
-        "Counter": "0,1,2,3",
         "EventCode": "0x90",
         "EventName": "UNC_M_VMSE_WR_PUSH.WMM",
         "PerPkg": "1",
@@ -1155,7 +1035,6 @@
     },
     {
         "BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc0",
         "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH",
         "PerPkg": "1",
@@ -1164,7 +1043,6 @@
     },
     {
         "BriefDescription": "Transition from WMM to RMM because of low threshold",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc0",
         "EventName": "UNC_M_WMM_TO_RMM.STARVE",
         "PerPkg": "1",
@@ -1173,7 +1051,6 @@
     },
     {
         "BriefDescription": "Transition from WMM to RMM because of low threshold",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc0",
         "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY",
         "PerPkg": "1",
@@ -1182,7 +1059,6 @@
     },
     {
         "BriefDescription": "Write Pending Queue Full Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_M_WPQ_CYCLES_FULL",
         "PerPkg": "1",
@@ -1191,7 +1067,6 @@
     },
     {
         "BriefDescription": "Write Pending Queue Not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_M_WPQ_CYCLES_NE",
         "PerPkg": "1",
@@ -1200,7 +1075,6 @@
     },
     {
         "BriefDescription": "Write Pending Queue Allocations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "UNC_M_WPQ_INSERTS",
         "PerPkg": "1",
@@ -1209,7 +1083,6 @@
     },
     {
         "BriefDescription": "Write Pending Queue CAM Match",
-        "Counter": "0,1,2,3",
         "EventCode": "0x23",
         "EventName": "UNC_M_WPQ_READ_HIT",
         "PerPkg": "1",
@@ -1218,7 +1091,6 @@
     },
     {
         "BriefDescription": "Write Pending Queue CAM Match",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_M_WPQ_WRITE_HIT",
         "PerPkg": "1",
@@ -1227,7 +1099,6 @@
     },
     {
         "BriefDescription": "Not getting the requested Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc1",
         "EventName": "UNC_M_WRONG_MM",
         "PerPkg": "1",
@@ -1235,7 +1106,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK0",
         "PerPkg": "1",
@@ -1244,7 +1114,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK1",
         "PerPkg": "1",
@@ -1253,7 +1122,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK2",
         "PerPkg": "1",
@@ -1262,7 +1130,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK3",
         "PerPkg": "1",
@@ -1271,7 +1138,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK4",
         "PerPkg": "1",
@@ -1280,7 +1146,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK5",
         "PerPkg": "1",
@@ -1289,7 +1154,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK6",
         "PerPkg": "1",
@@ -1298,7 +1162,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANK7",
         "PerPkg": "1",
@@ -1307,7 +1170,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK0",
         "PerPkg": "1",
@@ -1316,7 +1178,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK1",
         "PerPkg": "1",
@@ -1325,7 +1186,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK2",
         "PerPkg": "1",
@@ -1334,7 +1194,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK3",
         "PerPkg": "1",
@@ -1343,7 +1202,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK4",
         "PerPkg": "1",
@@ -1352,7 +1210,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK5",
         "PerPkg": "1",
@@ -1361,7 +1218,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK6",
         "PerPkg": "1",
@@ -1370,7 +1226,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANK7",
         "PerPkg": "1",
@@ -1379,7 +1234,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK0",
         "PerPkg": "1",
@@ -1388,7 +1242,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK1",
         "PerPkg": "1",
@@ -1397,7 +1250,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK2",
         "PerPkg": "1",
@@ -1406,7 +1258,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK3",
         "PerPkg": "1",
@@ -1415,7 +1266,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK4",
         "PerPkg": "1",
@@ -1424,7 +1274,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK5",
         "PerPkg": "1",
@@ -1433,7 +1282,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK6",
         "PerPkg": "1",
@@ -1442,7 +1290,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK7",
         "PerPkg": "1",
@@ -1451,7 +1298,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK0",
         "PerPkg": "1",
@@ -1460,7 +1306,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK1",
         "PerPkg": "1",
@@ -1469,7 +1314,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK2",
         "PerPkg": "1",
@@ -1478,7 +1322,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK3",
         "PerPkg": "1",
@@ -1487,7 +1330,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK4",
         "PerPkg": "1",
@@ -1496,7 +1338,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK5",
         "PerPkg": "1",
@@ -1505,7 +1346,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK6",
         "PerPkg": "1",
@@ -1514,7 +1354,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK7",
         "PerPkg": "1",
@@ -1523,7 +1362,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK0",
         "PerPkg": "1",
@@ -1532,7 +1370,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK1",
         "PerPkg": "1",
@@ -1541,7 +1378,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK2",
         "PerPkg": "1",
@@ -1550,7 +1386,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK3",
         "PerPkg": "1",
@@ -1559,7 +1394,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK4",
         "PerPkg": "1",
@@ -1568,7 +1402,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK5",
         "PerPkg": "1",
@@ -1577,7 +1410,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK6",
         "PerPkg": "1",
@@ -1586,7 +1418,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK7",
         "PerPkg": "1",
@@ -1595,7 +1426,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK0",
         "PerPkg": "1",
@@ -1604,7 +1434,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK1",
         "PerPkg": "1",
@@ -1613,7 +1442,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK2",
         "PerPkg": "1",
@@ -1622,7 +1450,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK3",
         "PerPkg": "1",
@@ -1631,7 +1458,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK4",
         "PerPkg": "1",
@@ -1640,7 +1466,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK5",
         "PerPkg": "1",
@@ -1649,7 +1474,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK6",
         "PerPkg": "1",
@@ -1658,7 +1482,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK7",
         "PerPkg": "1",
@@ -1667,7 +1490,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK0",
         "PerPkg": "1",
@@ -1676,7 +1498,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK1",
         "PerPkg": "1",
@@ -1685,7 +1506,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK2",
         "PerPkg": "1",
@@ -1694,7 +1514,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK3",
         "PerPkg": "1",
@@ -1703,7 +1522,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK4",
         "PerPkg": "1",
@@ -1712,7 +1530,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK5",
         "PerPkg": "1",
@@ -1721,7 +1538,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK6",
         "PerPkg": "1",
@@ -1730,7 +1546,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK7",
         "PerPkg": "1",
@@ -1739,7 +1554,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK0",
         "PerPkg": "1",
@@ -1748,7 +1562,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK1",
         "PerPkg": "1",
@@ -1757,7 +1570,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK2",
         "PerPkg": "1",
@@ -1766,7 +1578,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK3",
         "PerPkg": "1",
@@ -1775,7 +1586,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK4",
         "PerPkg": "1",
@@ -1784,7 +1594,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK5",
         "PerPkg": "1",
@@ -1793,7 +1602,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK6",
         "PerPkg": "1",
@@ -1802,7 +1610,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK7",
         "PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-other.json b/tools/perf/pmu-events/arch/x86/ivytown/uncore-other.json
index 6c7ddf642fc38..af9d14a6d1457 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-other.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Address Match (Conflict) Count; Conflict Merges",
-        "Counter": "0,1",
         "EventCode": "0x17",
         "EventName": "UNC_I_ADDRESS_MATCH.MERGE_COUNT",
         "PerPkg": "1",
@@ -11,7 +10,6 @@
     },
     {
         "BriefDescription": "Address Match (Conflict) Count; Conflict Stalls",
-        "Counter": "0,1",
         "EventCode": "0x17",
         "EventName": "UNC_I_ADDRESS_MATCH.STALL_COUNT",
         "PerPkg": "1",
@@ -21,7 +19,6 @@
     },
     {
         "BriefDescription": "Write Ack Pending Occupancy; Any Source",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.ANY",
         "PerPkg": "1",
@@ -31,7 +28,6 @@
     },
     {
         "BriefDescription": "Write Ack Pending Occupancy; Select Source",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.SOURCE",
         "PerPkg": "1",
@@ -41,7 +37,6 @@
     },
     {
         "BriefDescription": "Outstanding Write Ownership Occupancy; Any Source",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.ANY",
         "PerPkg": "1",
@@ -51,7 +46,6 @@
     },
     {
         "BriefDescription": "Outstanding Write Ownership Occupancy; Select Source",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.SOURCE",
         "PerPkg": "1",
@@ -61,7 +55,6 @@
     },
     {
         "BriefDescription": "Outstanding Read Occupancy; Any Source",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_I_CACHE_READ_OCCUPANCY.ANY",
         "PerPkg": "1",
@@ -71,7 +64,6 @@
     },
     {
         "BriefDescription": "Outstanding Read Occupancy; Select Source",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_I_CACHE_READ_OCCUPANCY.SOURCE",
         "PerPkg": "1",
@@ -81,7 +73,6 @@
     },
     {
         "BriefDescription": "Total Write Cache Occupancy; Any Source",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
         "PerPkg": "1",
@@ -91,7 +82,6 @@
     },
     {
         "BriefDescription": "Total Write Cache Occupancy; Select Source",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
         "PerPkg": "1",
@@ -101,7 +91,6 @@
     },
     {
         "BriefDescription": "Outstanding Write Occupancy; Any Source",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.ANY",
         "PerPkg": "1",
@@ -111,7 +100,6 @@
     },
     {
         "BriefDescription": "Outstanding Write Occupancy; Select Source",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.SOURCE",
         "PerPkg": "1",
@@ -121,14 +109,12 @@
     },
     {
         "BriefDescription": "Clocks in the IRP",
-        "Counter": "0,1",
         "EventName": "UNC_I_CLOCKTICKS",
         "PerPkg": "1",
         "PublicDescription": "Number of clocks in the IRP.",
         "Unit": "IRP"
     },
     {
-        "Counter": "0,1",
         "EventCode": "0xb",
         "EventName": "UNC_I_RxR_AK_CYCLES_FULL",
         "PerPkg": "1",
@@ -137,7 +123,6 @@
     },
     {
         "BriefDescription": "AK Ingress Occupancy",
-        "Counter": "0,1",
         "EventCode": "0xa",
         "EventName": "UNC_I_RxR_AK_INSERTS",
         "PerPkg": "1",
@@ -145,7 +130,6 @@
         "Unit": "IRP"
     },
     {
-        "Counter": "0,1",
         "EventCode": "0xc",
         "EventName": "UNC_I_RxR_AK_OCCUPANCY",
         "PerPkg": "1",
@@ -153,7 +137,6 @@
         "Unit": "IRP"
     },
     {
-        "Counter": "0,1",
         "EventCode": "0x4",
         "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
         "PerPkg": "1",
@@ -162,7 +145,6 @@
     },
     {
         "BriefDescription": "BL Ingress Occupancy - DRS",
-        "Counter": "0,1",
         "EventCode": "0x1",
         "EventName": "UNC_I_RxR_BL_DRS_INSERTS",
         "PerPkg": "1",
@@ -170,7 +152,6 @@
         "Unit": "IRP"
     },
     {
-        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY",
         "PerPkg": "1",
@@ -178,7 +159,6 @@
         "Unit": "IRP"
     },
     {
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
         "PerPkg": "1",
@@ -187,7 +167,6 @@
     },
     {
         "BriefDescription": "BL Ingress Occupancy - NCB",
-        "Counter": "0,1",
         "EventCode": "0x2",
         "EventName": "UNC_I_RxR_BL_NCB_INSERTS",
         "PerPkg": "1",
@@ -195,7 +174,6 @@
         "Unit": "IRP"
     },
     {
-        "Counter": "0,1",
         "EventCode": "0x8",
         "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY",
         "PerPkg": "1",
@@ -203,7 +181,6 @@
         "Unit": "IRP"
     },
     {
-        "Counter": "0,1",
         "EventCode": "0x6",
         "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
         "PerPkg": "1",
@@ -212,7 +189,6 @@
     },
     {
         "BriefDescription": "BL Ingress Occupancy - NCS",
-        "Counter": "0,1",
         "EventCode": "0x3",
         "EventName": "UNC_I_RxR_BL_NCS_INSERTS",
         "PerPkg": "1",
@@ -220,7 +196,6 @@
         "Unit": "IRP"
     },
     {
-        "Counter": "0,1",
         "EventCode": "0x9",
         "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY",
         "PerPkg": "1",
@@ -229,7 +204,6 @@
     },
     {
         "BriefDescription": "Tickle Count; Ownership Lost",
-        "Counter": "0,1",
         "EventCode": "0x16",
         "EventName": "UNC_I_TICKLES.LOST_OWNERSHIP",
         "PerPkg": "1",
@@ -239,7 +213,6 @@
     },
     {
         "BriefDescription": "Tickle Count; Data Returned",
-        "Counter": "0,1",
         "EventCode": "0x16",
         "EventName": "UNC_I_TICKLES.TOP_OF_QUEUE",
         "PerPkg": "1",
@@ -249,7 +222,6 @@
     },
     {
         "BriefDescription": "Inbound Transaction Count: Read Prefetches",
-        "Counter": "0,1",
         "EventCode": "0x15",
         "EventName": "UNC_I_TRANSACTIONS.PD_PREFETCHES",
         "PerPkg": "1",
@@ -259,7 +231,6 @@
     },
     {
         "BriefDescription": "Inbound Transaction Count; Read Prefetches",
-        "Counter": "0,1",
         "EventCode": "0x15",
         "EventName": "UNC_I_TRANSACTIONS.RD_PREFETCHES",
         "PerPkg": "1",
@@ -269,7 +240,6 @@
     },
     {
         "BriefDescription": "Inbound Transaction Count; Reads",
-        "Counter": "0,1",
         "EventCode": "0x15",
         "EventName": "UNC_I_TRANSACTIONS.READS",
         "PerPkg": "1",
@@ -279,7 +249,6 @@
     },
     {
         "BriefDescription": "Inbound Transaction Count; Writes",
-        "Counter": "0,1",
         "EventCode": "0x15",
         "EventName": "UNC_I_TRANSACTIONS.WRITES",
         "PerPkg": "1",
@@ -289,7 +258,6 @@
     },
     {
         "BriefDescription": "No AD Egress Credit Stalls",
-        "Counter": "0,1",
         "EventCode": "0x18",
         "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
         "PerPkg": "1",
@@ -298,7 +266,6 @@
     },
     {
         "BriefDescription": "No BL Egress Credit Stalls",
-        "Counter": "0,1",
         "EventCode": "0x19",
         "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
         "PerPkg": "1",
@@ -307,7 +274,6 @@
     },
     {
         "BriefDescription": "Outbound Read Requests",
-        "Counter": "0,1",
         "EventCode": "0xe",
         "EventName": "UNC_I_TxR_DATA_INSERTS_NCB",
         "PerPkg": "1",
@@ -316,7 +282,6 @@
     },
     {
         "BriefDescription": "Outbound Read Requests",
-        "Counter": "0,1",
         "EventCode": "0xf",
         "EventName": "UNC_I_TxR_DATA_INSERTS_NCS",
         "PerPkg": "1",
@@ -325,7 +290,6 @@
     },
     {
         "BriefDescription": "Outbound Request Queue Occupancy",
-        "Counter": "0,1",
         "EventCode": "0xd",
         "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY",
         "PerPkg": "1",
@@ -334,7 +298,6 @@
     },
     {
         "BriefDescription": "Write Ordering Stalls",
-        "Counter": "0,1",
         "EventCode": "0x1a",
         "EventName": "UNC_I_WRITE_ORDERING_STALL_CYCLES",
         "PerPkg": "1",
@@ -343,7 +306,6 @@
     },
     {
         "BriefDescription": "Number of uclks in domain",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_R2_CLOCKTICKS",
         "PerPkg": "1",
@@ -352,7 +314,6 @@
     },
     {
         "BriefDescription": "R2PCIe IIO Credit Acquired; DRS",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
         "PerPkg": "1",
@@ -362,7 +323,6 @@
     },
     {
         "BriefDescription": "R2PCIe IIO Credit Acquired; NCB",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
         "PerPkg": "1",
@@ -372,7 +332,6 @@
     },
     {
         "BriefDescription": "R2PCIe IIO Credit Acquired; NCS",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
         "PerPkg": "1",
@@ -382,7 +341,6 @@
     },
     {
         "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; DRS",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_R2_IIO_CREDITS_REJECT.DRS",
         "PerPkg": "1",
@@ -392,7 +350,6 @@
     },
     {
         "BriefDescription": "R2PCIe IIO Credits in Use; DRS",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_R2_IIO_CREDITS_USED.DRS",
         "PerPkg": "1",
@@ -402,7 +359,6 @@
     },
     {
         "BriefDescription": "R2PCIe IIO Credits in Use; NCB",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_R2_IIO_CREDITS_USED.NCB",
         "PerPkg": "1",
@@ -412,7 +368,6 @@
     },
     {
         "BriefDescription": "R2PCIe IIO Credits in Use; NCS",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_R2_IIO_CREDITS_USED.NCS",
         "PerPkg": "1",
@@ -422,17 +377,15 @@
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
-        "UMask": "0xCC",
+        "UMask": "0xcc",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CCW_VR0_EVEN",
         "PerPkg": "1",
@@ -442,7 +395,6 @@
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CCW_VR0_ODD",
         "PerPkg": "1",
@@ -452,7 +404,6 @@
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CCW_VR1_EVEN",
         "PerPkg": "1",
@@ -462,7 +413,6 @@
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CCW_VR1_ODD",
         "PerPkg": "1",
@@ -472,7 +422,6 @@
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CW",
         "PerPkg": "1",
@@ -482,7 +431,6 @@
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Clockwise and Even on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CW_VR0_EVEN",
         "PerPkg": "1",
@@ -492,7 +440,6 @@
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CW_VR0_ODD",
         "PerPkg": "1",
@@ -502,7 +449,6 @@
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Clockwise and Even on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CW_VR1_EVEN",
         "PerPkg": "1",
@@ -512,7 +458,6 @@
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CW_VR1_ODD",
         "PerPkg": "1",
@@ -522,17 +467,15 @@
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
-        "UMask": "0xCC",
+        "UMask": "0xcc",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CCW_VR0_EVEN",
         "PerPkg": "1",
@@ -542,7 +485,6 @@
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CCW_VR0_ODD",
         "PerPkg": "1",
@@ -552,7 +494,6 @@
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CCW_VR1_EVEN",
         "PerPkg": "1",
@@ -562,7 +503,6 @@
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CCW_VR1_ODD",
         "PerPkg": "1",
@@ -572,7 +512,6 @@
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CW",
         "PerPkg": "1",
@@ -582,7 +521,6 @@
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Clockwise and Even on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CW_VR0_EVEN",
         "PerPkg": "1",
@@ -592,7 +530,6 @@
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CW_VR0_ODD",
         "PerPkg": "1",
@@ -602,7 +539,6 @@
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Clockwise and Even on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CW_VR1_EVEN",
         "PerPkg": "1",
@@ -612,7 +548,6 @@
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CW_VR1_ODD",
         "PerPkg": "1",
@@ -622,17 +557,15 @@
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
-        "UMask": "0xCC",
+        "UMask": "0xcc",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CCW_VR0_EVEN",
         "PerPkg": "1",
@@ -642,7 +575,6 @@
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CCW_VR0_ODD",
         "PerPkg": "1",
@@ -652,7 +584,6 @@
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CCW_VR1_EVEN",
         "PerPkg": "1",
@@ -662,7 +593,6 @@
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CCW_VR1_ODD",
         "PerPkg": "1",
@@ -672,7 +602,6 @@
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CW",
         "PerPkg": "1",
@@ -682,7 +611,6 @@
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Clockwise and Even on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CW_VR0_EVEN",
         "PerPkg": "1",
@@ -692,7 +620,6 @@
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd on VRing 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CW_VR0_ODD",
         "PerPkg": "1",
@@ -702,7 +629,6 @@
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Clockwise and Even on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CW_VR1_EVEN",
         "PerPkg": "1",
@@ -712,7 +638,6 @@
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd on VRing 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CW_VR1_ODD",
         "PerPkg": "1",
@@ -722,27 +647,24 @@
     },
     {
         "BriefDescription": "R2 IV Ring in Use; Any",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_R2_RING_IV_USED.ANY",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity",
-        "UMask": "0xFF",
+        "UMask": "0xff",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 IV Ring in Use; Counterclockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0xa",
         "EventName": "UNC_R2_RING_IV_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity",
-        "UMask": "0xCC",
+        "UMask": "0xcc",
         "Unit": "R2PCIe"
     },
     {
         "BriefDescription": "R2 IV Ring in Use; Clockwise",
-        "Counter": "0,1,2,3",
         "EventCode": "0xa",
         "EventName": "UNC_R2_RING_IV_USED.CW",
         "PerPkg": "1",
@@ -778,7 +700,6 @@
     },
     {
         "BriefDescription": "Ingress Cycles Not Empty; NCB",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R2_RxR_CYCLES_NE.NCB",
         "PerPkg": "1",
@@ -788,7 +709,6 @@
     },
     {
         "BriefDescription": "Ingress Cycles Not Empty; NCS",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R2_RxR_CYCLES_NE.NCS",
         "PerPkg": "1",
@@ -798,7 +718,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; NCB",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R2_RxR_INSERTS.NCB",
         "PerPkg": "1",
@@ -808,7 +727,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; NCS",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R2_RxR_INSERTS.NCS",
         "PerPkg": "1",
@@ -881,7 +799,6 @@
     },
     {
         "BriefDescription": "Egress CCW NACK; AD CCW",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "UNC_R2_TxR_NACK_CCW.AD",
         "PerPkg": "1",
@@ -891,7 +808,6 @@
     },
     {
         "BriefDescription": "Egress CCW NACK; AK CCW",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "UNC_R2_TxR_NACK_CCW.AK",
         "PerPkg": "1",
@@ -901,7 +817,6 @@
     },
     {
         "BriefDescription": "Egress CCW NACK; BL CCW",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "UNC_R2_TxR_NACK_CCW.BL",
         "PerPkg": "1",
@@ -911,7 +826,6 @@
     },
     {
         "BriefDescription": "Egress CW NACK; AD CW",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R2_TxR_NACK_CW.AD",
         "PerPkg": "1",
@@ -921,7 +835,6 @@
     },
     {
         "BriefDescription": "Egress CW NACK; AK CW",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R2_TxR_NACK_CW.AK",
         "PerPkg": "1",
@@ -931,7 +844,6 @@
     },
     {
         "BriefDescription": "Egress CW NACK; BL CW",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R2_TxR_NACK_CW.BL",
         "PerPkg": "1",
@@ -941,7 +853,6 @@
     },
     {
         "BriefDescription": "Number of uclks in domain",
-        "Counter": "0,1,2",
         "EventCode": "0x1",
         "EventName": "UNC_R3_CLOCKTICKS",
         "PerPkg": "1",
@@ -950,7 +861,6 @@
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2c",
         "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10",
         "PerPkg": "1",
@@ -960,7 +870,6 @@
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2c",
         "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11",
         "PerPkg": "1",
@@ -970,7 +879,6 @@
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2c",
         "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12",
         "PerPkg": "1",
@@ -980,7 +888,6 @@
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2c",
         "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13",
         "PerPkg": "1",
@@ -990,7 +897,6 @@
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2c",
         "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14",
         "PerPkg": "1",
@@ -1000,7 +906,6 @@
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2c",
         "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8",
         "PerPkg": "1",
@@ -1010,7 +915,6 @@
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2c",
         "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9",
         "PerPkg": "1",
@@ -1020,7 +924,6 @@
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2b",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0",
         "PerPkg": "1",
@@ -1030,7 +933,6 @@
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2b",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1",
         "PerPkg": "1",
@@ -1040,7 +942,6 @@
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2b",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2",
         "PerPkg": "1",
@@ -1050,7 +951,6 @@
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2b",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3",
         "PerPkg": "1",
@@ -1060,7 +960,6 @@
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2b",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4",
         "PerPkg": "1",
@@ -1070,7 +969,6 @@
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2b",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5",
         "PerPkg": "1",
@@ -1080,7 +978,6 @@
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2b",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6",
         "PerPkg": "1",
@@ -1090,7 +987,6 @@
     },
     {
         "BriefDescription": "CBox AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2b",
         "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7",
         "PerPkg": "1",
@@ -1100,7 +996,6 @@
     },
     {
         "BriefDescription": "HA/R2 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2f",
         "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0",
         "PerPkg": "1",
@@ -1110,7 +1005,6 @@
     },
     {
         "BriefDescription": "HA/R2 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2f",
         "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1",
         "PerPkg": "1",
@@ -1120,7 +1014,6 @@
     },
     {
         "BriefDescription": "HA/R2 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2f",
         "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB",
         "PerPkg": "1",
@@ -1130,7 +1023,6 @@
     },
     {
         "BriefDescription": "HA/R2 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2f",
         "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS",
         "PerPkg": "1",
@@ -1140,7 +1032,6 @@
     },
     {
         "BriefDescription": "QPI0 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM",
         "PerPkg": "1",
@@ -1150,7 +1041,6 @@
     },
     {
         "BriefDescription": "QPI0 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR",
         "PerPkg": "1",
@@ -1160,7 +1050,6 @@
     },
     {
         "BriefDescription": "QPI0 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP",
         "PerPkg": "1",
@@ -1170,7 +1059,6 @@
     },
     {
         "BriefDescription": "QPI0 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM",
         "PerPkg": "1",
@@ -1180,7 +1068,6 @@
     },
     {
         "BriefDescription": "QPI0 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR",
         "PerPkg": "1",
@@ -1190,7 +1077,6 @@
     },
     {
         "BriefDescription": "QPI0 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP",
         "PerPkg": "1",
@@ -1200,7 +1086,6 @@
     },
     {
         "BriefDescription": "QPI0 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA",
         "PerPkg": "1",
@@ -1210,7 +1095,6 @@
     },
     {
         "BriefDescription": "QPI0 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2d",
         "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_HOM",
         "PerPkg": "1",
@@ -1220,7 +1104,6 @@
     },
     {
         "BriefDescription": "QPI0 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2d",
         "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_NDR",
         "PerPkg": "1",
@@ -1230,7 +1113,6 @@
     },
     {
         "BriefDescription": "QPI0 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2d",
         "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_SNP",
         "PerPkg": "1",
@@ -1240,7 +1122,6 @@
     },
     {
         "BriefDescription": "QPI0 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2d",
         "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM",
         "PerPkg": "1",
@@ -1250,7 +1131,6 @@
     },
     {
         "BriefDescription": "QPI0 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2d",
         "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR",
         "PerPkg": "1",
@@ -1260,7 +1140,6 @@
     },
     {
         "BriefDescription": "QPI0 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2d",
         "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP",
         "PerPkg": "1",
@@ -1270,7 +1149,6 @@
     },
     {
         "BriefDescription": "QPI0 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2d",
         "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA",
         "PerPkg": "1",
@@ -1280,7 +1158,6 @@
     },
     {
         "BriefDescription": "QPI1 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2a",
         "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_HOM",
         "PerPkg": "1",
@@ -1290,7 +1167,6 @@
     },
     {
         "BriefDescription": "QPI1 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2a",
         "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_NDR",
         "PerPkg": "1",
@@ -1300,7 +1176,6 @@
     },
     {
         "BriefDescription": "QPI1 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2a",
         "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_SNP",
         "PerPkg": "1",
@@ -1310,7 +1185,6 @@
     },
     {
         "BriefDescription": "QPI1 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2a",
         "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM",
         "PerPkg": "1",
@@ -1320,7 +1194,6 @@
     },
     {
         "BriefDescription": "QPI1 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2a",
         "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR",
         "PerPkg": "1",
@@ -1330,7 +1203,6 @@
     },
     {
         "BriefDescription": "QPI1 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2a",
         "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP",
         "PerPkg": "1",
@@ -1340,7 +1212,6 @@
     },
     {
         "BriefDescription": "QPI1 AD Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2a",
         "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA",
         "PerPkg": "1",
@@ -1350,7 +1221,6 @@
     },
     {
         "BriefDescription": "QPI1 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2e",
         "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM",
         "PerPkg": "1",
@@ -1360,7 +1230,6 @@
     },
     {
         "BriefDescription": "QPI1 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2e",
         "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR",
         "PerPkg": "1",
@@ -1370,7 +1239,6 @@
     },
     {
         "BriefDescription": "QPI1 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2e",
         "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP",
         "PerPkg": "1",
@@ -1380,7 +1248,6 @@
     },
     {
         "BriefDescription": "QPI1 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2e",
         "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM",
         "PerPkg": "1",
@@ -1390,7 +1257,6 @@
     },
     {
         "BriefDescription": "QPI1 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2e",
         "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR",
         "PerPkg": "1",
@@ -1400,7 +1266,6 @@
     },
     {
         "BriefDescription": "QPI1 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2e",
         "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP",
         "PerPkg": "1",
@@ -1410,7 +1275,6 @@
     },
     {
         "BriefDescription": "QPI1 BL Credits Empty",
-        "Counter": "0,1",
         "EventCode": "0x2e",
         "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA",
         "PerPkg": "1",
@@ -1420,17 +1284,15 @@
     },
     {
         "BriefDescription": "R3 AD Ring in Use; Counterclockwise",
-        "Counter": "0,1,2",
         "EventCode": "0x7",
         "EventName": "UNC_R3_RING_AD_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
-        "UMask": "0xCC",
+        "UMask": "0xcc",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even on VRing 0",
-        "Counter": "0,1,2",
         "EventCode": "0x7",
         "EventName": "UNC_R3_RING_AD_USED.CCW_VR0_EVEN",
         "PerPkg": "1",
@@ -1440,7 +1302,6 @@
     },
     {
         "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd on VRing 0",
-        "Counter": "0,1,2",
         "EventCode": "0x7",
         "EventName": "UNC_R3_RING_AD_USED.CCW_VR0_ODD",
         "PerPkg": "1",
@@ -1450,7 +1311,6 @@
     },
     {
         "BriefDescription": "R3 AD Ring in Use; Clockwise",
-        "Counter": "0,1,2",
         "EventCode": "0x7",
         "EventName": "UNC_R3_RING_AD_USED.CW",
         "PerPkg": "1",
@@ -1460,7 +1320,6 @@
     },
     {
         "BriefDescription": "R3 AD Ring in Use; Clockwise and Even on VRing 0",
-        "Counter": "0,1,2",
         "EventCode": "0x7",
         "EventName": "UNC_R3_RING_AD_USED.CW_VR0_EVEN",
         "PerPkg": "1",
@@ -1470,7 +1329,6 @@
     },
     {
         "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd on VRing 0",
-        "Counter": "0,1,2",
         "EventCode": "0x7",
         "EventName": "UNC_R3_RING_AD_USED.CW_VR0_ODD",
         "PerPkg": "1",
@@ -1480,17 +1338,15 @@
     },
     {
         "BriefDescription": "R3 AK Ring in Use; Counterclockwise",
-        "Counter": "0,1,2",
         "EventCode": "0x8",
         "EventName": "UNC_R3_RING_AK_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
-        "UMask": "0xCC",
+        "UMask": "0xcc",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even on VRing 0",
-        "Counter": "0,1,2",
         "EventCode": "0x8",
         "EventName": "UNC_R3_RING_AK_USED.CCW_VR0_EVEN",
         "PerPkg": "1",
@@ -1500,7 +1356,6 @@
     },
     {
         "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd on VRing 0",
-        "Counter": "0,1,2",
         "EventCode": "0x8",
         "EventName": "UNC_R3_RING_AK_USED.CCW_VR0_ODD",
         "PerPkg": "1",
@@ -1510,7 +1365,6 @@
     },
     {
         "BriefDescription": "R3 AK Ring in Use; Clockwise",
-        "Counter": "0,1,2",
         "EventCode": "0x8",
         "EventName": "UNC_R3_RING_AK_USED.CW",
         "PerPkg": "1",
@@ -1520,7 +1374,6 @@
     },
     {
         "BriefDescription": "R3 AK Ring in Use; Clockwise and Even on VRing 0",
-        "Counter": "0,1,2",
         "EventCode": "0x8",
         "EventName": "UNC_R3_RING_AK_USED.CW_VR0_EVEN",
         "PerPkg": "1",
@@ -1530,7 +1383,6 @@
     },
     {
         "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd on VRing 0",
-        "Counter": "0,1,2",
         "EventCode": "0x8",
         "EventName": "UNC_R3_RING_AK_USED.CW_VR0_ODD",
         "PerPkg": "1",
@@ -1540,17 +1392,15 @@
     },
     {
         "BriefDescription": "R3 BL Ring in Use; Counterclockwise",
-        "Counter": "0,1,2",
         "EventCode": "0x9",
         "EventName": "UNC_R3_RING_BL_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
-        "UMask": "0xCC",
+        "UMask": "0xcc",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even on VRing 0",
-        "Counter": "0,1,2",
         "EventCode": "0x9",
         "EventName": "UNC_R3_RING_BL_USED.CCW_VR0_EVEN",
         "PerPkg": "1",
@@ -1560,7 +1410,6 @@
     },
     {
         "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd on VRing 0",
-        "Counter": "0,1,2",
         "EventCode": "0x9",
         "EventName": "UNC_R3_RING_BL_USED.CCW_VR0_ODD",
         "PerPkg": "1",
@@ -1570,7 +1419,6 @@
     },
     {
         "BriefDescription": "R3 BL Ring in Use; Clockwise",
-        "Counter": "0,1,2",
         "EventCode": "0x9",
         "EventName": "UNC_R3_RING_BL_USED.CW",
         "PerPkg": "1",
@@ -1580,7 +1428,6 @@
     },
     {
         "BriefDescription": "R3 BL Ring in Use; Clockwise and Even on VRing 0",
-        "Counter": "0,1,2",
         "EventCode": "0x9",
         "EventName": "UNC_R3_RING_BL_USED.CW_VR0_EVEN",
         "PerPkg": "1",
@@ -1590,7 +1437,6 @@
     },
     {
         "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd on VRing 0",
-        "Counter": "0,1,2",
         "EventCode": "0x9",
         "EventName": "UNC_R3_RING_BL_USED.CW_VR0_ODD",
         "PerPkg": "1",
@@ -1600,27 +1446,24 @@
     },
     {
         "BriefDescription": "R2 IV Ring in Use; Any",
-        "Counter": "0,1,2",
         "EventCode": "0xA",
         "EventName": "UNC_R3_RING_IV_USED.ANY",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity",
-        "UMask": "0xFF",
+        "UMask": "0xff",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R2 IV Ring in Use; Counterclockwise",
-        "Counter": "0,1,2",
         "EventCode": "0xa",
         "EventName": "UNC_R3_RING_IV_USED.CCW",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.  The IV ring is unidirectional.  Whether UP or DN is used is dependent on the system programming.  Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity",
-        "UMask": "0xCC",
+        "UMask": "0xcc",
         "Unit": "R3QPI"
     },
     {
         "BriefDescription": "R2 IV Ring in Use; Clockwise",
-        "Counter": "0,1,2",
         "EventCode": "0xa",
         "EventName": "UNC_R3_RING_IV_USED.CW",
         "PerPkg": "1",
@@ -1630,7 +1473,6 @@
     },
     {
         "BriefDescription": "AD Ingress Bypassed",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "UNC_R3_RxR_AD_BYPASSED",
         "PerPkg": "1",
@@ -1639,7 +1481,6 @@
     },
     {
         "BriefDescription": "Ingress Bypassed",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "UNC_R3_RxR_BYPASSED.AD",
         "PerPkg": "1",
@@ -1649,7 +1490,6 @@
     },
     {
         "BriefDescription": "Ingress Cycles Not Empty; HOM",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R3_RxR_CYCLES_NE.HOM",
         "PerPkg": "1",
@@ -1659,7 +1499,6 @@
     },
     {
         "BriefDescription": "Ingress Cycles Not Empty; NDR",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R3_RxR_CYCLES_NE.NDR",
         "PerPkg": "1",
@@ -1669,7 +1508,6 @@
     },
     {
         "BriefDescription": "Ingress Cycles Not Empty; SNP",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R3_RxR_CYCLES_NE.SNP",
         "PerPkg": "1",
@@ -1679,7 +1517,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; DRS",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R3_RxR_INSERTS.DRS",
         "PerPkg": "1",
@@ -1689,7 +1526,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; HOM",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R3_RxR_INSERTS.HOM",
         "PerPkg": "1",
@@ -1699,7 +1535,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; NCB",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R3_RxR_INSERTS.NCB",
         "PerPkg": "1",
@@ -1709,7 +1544,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; NCS",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R3_RxR_INSERTS.NCS",
         "PerPkg": "1",
@@ -1719,7 +1553,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; NDR",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R3_RxR_INSERTS.NDR",
         "PerPkg": "1",
@@ -1729,7 +1562,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; SNP",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R3_RxR_INSERTS.SNP",
         "PerPkg": "1",
@@ -1793,7 +1625,6 @@
     },
     {
         "BriefDescription": "Egress NACK; AK CCW",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "UNC_R3_TxR_NACK_CCW.AD",
         "PerPkg": "1",
@@ -1803,7 +1634,6 @@
     },
     {
         "BriefDescription": "Egress NACK; BL CW",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "UNC_R3_TxR_NACK_CCW.AK",
         "PerPkg": "1",
@@ -1813,7 +1643,6 @@
     },
     {
         "BriefDescription": "Egress NACK; BL CCW",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "UNC_R3_TxR_NACK_CCW.BL",
         "PerPkg": "1",
@@ -1823,7 +1652,6 @@
     },
     {
         "BriefDescription": "Egress NACK; AD CW",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R3_TxR_NACK_CW.AD",
         "PerPkg": "1",
@@ -1833,7 +1661,6 @@
     },
     {
         "BriefDescription": "Egress NACK; AD CCW",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R3_TxR_NACK_CW.AK",
         "PerPkg": "1",
@@ -1843,7 +1670,6 @@
     },
     {
         "BriefDescription": "Egress NACK; AK CW",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R3_TxR_NACK_CW.BL",
         "PerPkg": "1",
@@ -1853,7 +1679,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS",
         "PerPkg": "1",
@@ -1863,7 +1688,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM",
         "PerPkg": "1",
@@ -1873,7 +1697,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Message Class",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB",
         "PerPkg": "1",
@@ -1883,7 +1706,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS",
         "PerPkg": "1",
@@ -1893,7 +1715,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR",
         "PerPkg": "1",
@@ -1903,7 +1724,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP",
         "PerPkg": "1",
@@ -1913,7 +1733,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Used; DRS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x36",
         "EventName": "UNC_R3_VN0_CREDITS_USED.DRS",
         "PerPkg": "1",
@@ -1923,7 +1742,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Used; HOM Message Class",
-        "Counter": "0,1",
         "EventCode": "0x36",
         "EventName": "UNC_R3_VN0_CREDITS_USED.HOM",
         "PerPkg": "1",
@@ -1933,7 +1751,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Used; NCB Message Class",
-        "Counter": "0,1",
         "EventCode": "0x36",
         "EventName": "UNC_R3_VN0_CREDITS_USED.NCB",
         "PerPkg": "1",
@@ -1943,7 +1760,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Used; NCS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x36",
         "EventName": "UNC_R3_VN0_CREDITS_USED.NCS",
         "PerPkg": "1",
@@ -1953,7 +1769,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Used; NDR Message Class",
-        "Counter": "0,1",
         "EventCode": "0x36",
         "EventName": "UNC_R3_VN0_CREDITS_USED.NDR",
         "PerPkg": "1",
@@ -1963,7 +1778,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Used; SNP Message Class",
-        "Counter": "0,1",
         "EventCode": "0x36",
         "EventName": "UNC_R3_VN0_CREDITS_USED.SNP",
         "PerPkg": "1",
@@ -1973,7 +1787,6 @@
     },
     {
         "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x39",
         "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS",
         "PerPkg": "1",
@@ -1983,7 +1796,6 @@
     },
     {
         "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Message Class",
-        "Counter": "0,1",
         "EventCode": "0x39",
         "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM",
         "PerPkg": "1",
@@ -1993,7 +1805,6 @@
     },
     {
         "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCB Message Class",
-        "Counter": "0,1",
         "EventCode": "0x39",
         "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCB",
         "PerPkg": "1",
@@ -2003,7 +1814,6 @@
     },
     {
         "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x39",
         "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCS",
         "PerPkg": "1",
@@ -2013,7 +1823,6 @@
     },
     {
         "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Message Class",
-        "Counter": "0,1",
         "EventCode": "0x39",
         "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR",
         "PerPkg": "1",
@@ -2023,7 +1832,6 @@
     },
     {
         "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Message Class",
-        "Counter": "0,1",
         "EventCode": "0x39",
         "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP",
         "PerPkg": "1",
@@ -2033,7 +1841,6 @@
     },
     {
         "BriefDescription": "VN1 Credit Used; DRS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x38",
         "EventName": "UNC_R3_VN1_CREDITS_USED.DRS",
         "PerPkg": "1",
@@ -2043,7 +1850,6 @@
     },
     {
         "BriefDescription": "VN1 Credit Used; HOM Message Class",
-        "Counter": "0,1",
         "EventCode": "0x38",
         "EventName": "UNC_R3_VN1_CREDITS_USED.HOM",
         "PerPkg": "1",
@@ -2053,7 +1859,6 @@
     },
     {
         "BriefDescription": "VN1 Credit Used; NCB Message Class",
-        "Counter": "0,1",
         "EventCode": "0x38",
         "EventName": "UNC_R3_VN1_CREDITS_USED.NCB",
         "PerPkg": "1",
@@ -2063,7 +1868,6 @@
     },
     {
         "BriefDescription": "VN1 Credit Used; NCS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x38",
         "EventName": "UNC_R3_VN1_CREDITS_USED.NCS",
         "PerPkg": "1",
@@ -2073,7 +1877,6 @@
     },
     {
         "BriefDescription": "VN1 Credit Used; NDR Message Class",
-        "Counter": "0,1",
         "EventCode": "0x38",
         "EventName": "UNC_R3_VN1_CREDITS_USED.NDR",
         "PerPkg": "1",
@@ -2083,7 +1886,6 @@
     },
     {
         "BriefDescription": "VN1 Credit Used; SNP Message Class",
-        "Counter": "0,1",
         "EventCode": "0x38",
         "EventName": "UNC_R3_VN1_CREDITS_USED.SNP",
         "PerPkg": "1",
@@ -2093,7 +1895,6 @@
     },
     {
         "BriefDescription": "VNA credit Acquisitions",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED",
         "PerPkg": "1",
@@ -2102,7 +1903,6 @@
     },
     {
         "BriefDescription": "VNA credit Acquisitions; HOM Message Class",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD",
         "PerPkg": "1",
@@ -2112,7 +1912,6 @@
     },
     {
         "BriefDescription": "VNA credit Acquisitions; HOM Message Class",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL",
         "PerPkg": "1",
@@ -2122,7 +1921,6 @@
     },
     {
         "BriefDescription": "VNA Credit Reject; DRS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS",
         "PerPkg": "1",
@@ -2132,7 +1930,6 @@
     },
     {
         "BriefDescription": "VNA Credit Reject; HOM Message Class",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM",
         "PerPkg": "1",
@@ -2142,7 +1939,6 @@
     },
     {
         "BriefDescription": "VNA Credit Reject; NCB Message Class",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB",
         "PerPkg": "1",
@@ -2152,7 +1948,6 @@
     },
     {
         "BriefDescription": "VNA Credit Reject; NCS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS",
         "PerPkg": "1",
@@ -2162,7 +1957,6 @@
     },
     {
         "BriefDescription": "VNA Credit Reject; NDR Message Class",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR",
         "PerPkg": "1",
@@ -2172,7 +1966,6 @@
     },
     {
         "BriefDescription": "VNA Credit Reject; SNP Message Class",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP",
         "PerPkg": "1",
@@ -2182,7 +1975,6 @@
     },
     {
         "BriefDescription": "Cycles with no VNA credits available",
-        "Counter": "0,1",
         "EventCode": "0x31",
         "EventName": "UNC_R3_VNA_CREDIT_CYCLES_OUT",
         "PerPkg": "1",
@@ -2191,16 +1983,19 @@
     },
     {
         "BriefDescription": "Cycles with 1 or more VNA credits in use",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_R3_VNA_CREDIT_CYCLES_USED",
         "PerPkg": "1",
         "PublicDescription": "Number of QPI uclk cycles with one or more VNA credits in use.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average number of used VNA credits.",
         "Unit": "R3QPI"
     },
+    {
+        "EventName": "UNC_U_CLOCKTICKS",
+        "PerPkg": "1",
+        "Unit": "UBOX"
+    },
     {
         "BriefDescription": "VLW Received",
-        "Counter": "0,1",
         "EventCode": "0x42",
         "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
         "PerPkg": "1",
@@ -2210,7 +2005,6 @@
     },
     {
         "BriefDescription": "VLW Received",
-        "Counter": "0,1",
         "EventCode": "0x42",
         "EventName": "UNC_U_EVENT_MSG.INT_PRIO",
         "PerPkg": "1",
@@ -2220,7 +2014,6 @@
     },
     {
         "BriefDescription": "VLW Received",
-        "Counter": "0,1",
         "EventCode": "0x42",
         "EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
         "PerPkg": "1",
@@ -2230,7 +2023,6 @@
     },
     {
         "BriefDescription": "VLW Received",
-        "Counter": "0,1",
         "EventCode": "0x42",
         "EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
         "PerPkg": "1",
@@ -2240,7 +2032,6 @@
     },
     {
         "BriefDescription": "VLW Received",
-        "Counter": "0,1",
         "EventCode": "0x42",
         "EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
         "PerPkg": "1",
@@ -2250,7 +2041,6 @@
     },
     {
         "BriefDescription": "Filter Match",
-        "Counter": "0,1",
         "EventCode": "0x41",
         "EventName": "UNC_U_FILTER_MATCH.DISABLE",
         "PerPkg": "1",
@@ -2260,7 +2050,6 @@
     },
     {
         "BriefDescription": "Filter Match",
-        "Counter": "0,1",
         "EventCode": "0x41",
         "EventName": "UNC_U_FILTER_MATCH.ENABLE",
         "PerPkg": "1",
@@ -2270,7 +2059,6 @@
     },
     {
         "BriefDescription": "Filter Match",
-        "Counter": "0,1",
         "EventCode": "0x41",
         "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
         "PerPkg": "1",
@@ -2280,7 +2068,6 @@
     },
     {
         "BriefDescription": "Filter Match",
-        "Counter": "0,1",
         "EventCode": "0x41",
         "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE",
         "PerPkg": "1",
@@ -2290,7 +2077,6 @@
     },
     {
         "BriefDescription": "IDI Lock/SplitLock Cycles",
-        "Counter": "0,1",
         "EventCode": "0x44",
         "EventName": "UNC_U_LOCK_CYCLES",
         "PerPkg": "1",
@@ -2299,7 +2085,6 @@
     },
     {
         "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
-        "Counter": "0,1",
         "EventCode": "0x45",
         "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
         "PerPkg": "1",
@@ -2309,7 +2094,6 @@
     },
     {
         "BriefDescription": "RACU Request",
-        "Counter": "0,1",
         "EventCode": "0x46",
         "EventName": "UNC_U_RACU_REQUESTS",
         "PerPkg": "1",
@@ -2317,7 +2101,6 @@
     },
     {
         "BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.CMC",
         "PerPkg": "1",
@@ -2327,7 +2110,6 @@
     },
     {
         "BriefDescription": "Monitor Sent to T0; Livelock",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.LIVELOCK",
         "PerPkg": "1",
@@ -2337,7 +2119,6 @@
     },
     {
         "BriefDescription": "Monitor Sent to T0; LTError",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.LTERROR",
         "PerPkg": "1",
@@ -2347,7 +2128,6 @@
     },
     {
         "BriefDescription": "Monitor Sent to T0; Monitor T0",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
         "PerPkg": "1",
@@ -2357,7 +2137,6 @@
     },
     {
         "BriefDescription": "Monitor Sent to T0; Monitor T1",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
         "PerPkg": "1",
@@ -2367,7 +2146,6 @@
     },
     {
         "BriefDescription": "Monitor Sent to T0; Other",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.OTHER",
         "PerPkg": "1",
@@ -2377,7 +2155,6 @@
     },
     {
         "BriefDescription": "Monitor Sent to T0; Trap",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.TRAP",
         "PerPkg": "1",
@@ -2387,7 +2164,6 @@
     },
     {
         "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.UMC",
         "PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-power.json b/tools/perf/pmu-events/arch/x86/ivytown/uncore-power.json
index 74c87217d75c9..5df1ebfb89ea3 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-power.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "pclk Cycles",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_P_CLOCKTICKS",
         "PerPkg": "1",
         "PublicDescription": "The PCU runs off a fixed 800 MHz clock.  This event counts the number of pclk cycles measured while the counter was enabled.  The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Core 0 C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x70",
         "EventName": "UNC_P_CORE0_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -18,7 +16,6 @@
     },
     {
         "BriefDescription": "Core 10 C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7a",
         "EventName": "UNC_P_CORE10_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -27,7 +24,6 @@
     },
     {
         "BriefDescription": "Core 11 C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7b",
         "EventName": "UNC_P_CORE11_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -36,7 +32,6 @@
     },
     {
         "BriefDescription": "Core 12 C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7c",
         "EventName": "UNC_P_CORE12_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -45,7 +40,6 @@
     },
     {
         "BriefDescription": "Core 13 C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7d",
         "EventName": "UNC_P_CORE13_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -54,7 +48,6 @@
     },
     {
         "BriefDescription": "Core 14 C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7e",
         "EventName": "UNC_P_CORE14_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -63,7 +56,6 @@
     },
     {
         "BriefDescription": "Core 1 C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "UNC_P_CORE1_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -72,7 +64,6 @@
     },
     {
         "BriefDescription": "Core 2 C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x72",
         "EventName": "UNC_P_CORE2_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -81,7 +72,6 @@
     },
     {
         "BriefDescription": "Core 3 C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x73",
         "EventName": "UNC_P_CORE3_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -90,7 +80,6 @@
     },
     {
         "BriefDescription": "Core 4 C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x74",
         "EventName": "UNC_P_CORE4_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -99,7 +88,6 @@
     },
     {
         "BriefDescription": "Core 5 C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x75",
         "EventName": "UNC_P_CORE5_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -108,7 +96,6 @@
     },
     {
         "BriefDescription": "Core 6 C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x76",
         "EventName": "UNC_P_CORE6_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -117,7 +104,6 @@
     },
     {
         "BriefDescription": "Core 7 C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x77",
         "EventName": "UNC_P_CORE7_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -126,7 +112,6 @@
     },
     {
         "BriefDescription": "Core 8 C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x78",
         "EventName": "UNC_P_CORE8_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -135,7 +120,6 @@
     },
     {
         "BriefDescription": "Core 9 C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x79",
         "EventName": "UNC_P_CORE9_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -144,157 +128,126 @@
     },
     {
         "BriefDescription": "Deep C State Rejection - Core 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x17",
         "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE0",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Deep C State Rejection - Core 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE1",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Deep C State Rejection - Core 10",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE10",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Deep C State Rejection - Core 11",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE11",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Deep C State Rejection - Core 12",
-        "Counter": "0,1,2,3",
         "EventCode": "0x23",
         "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE12",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Deep C State Rejection - Core 13",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE13",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Deep C State Rejection - Core 14",
-        "Counter": "0,1,2,3",
         "EventCode": "0x25",
         "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE14",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Deep C State Rejection - Core 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE2",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Deep C State Rejection - Core 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1a",
         "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE3",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Deep C State Rejection - Core 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE4",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Deep C State Rejection - Core 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1c",
         "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE5",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Deep C State Rejection - Core 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1d",
         "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE6",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Deep C State Rejection - Core 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1e",
         "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE7",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Deep C State Rejection - Core 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1f",
         "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE8",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Deep C State Rejection - Core 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE9",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of times that a deep C state was requested, but the delayed C state algorithm rejected the deep sleep state.  In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core 0 C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1e",
         "EventName": "UNC_P_DEMOTIONS_CORE0",
         "PerPkg": "1",
@@ -303,7 +256,6 @@
     },
     {
         "BriefDescription": "Core 1 C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1f",
         "EventName": "UNC_P_DEMOTIONS_CORE1",
         "PerPkg": "1",
@@ -312,7 +264,6 @@
     },
     {
         "BriefDescription": "Core 10 C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x42",
         "EventName": "UNC_P_DEMOTIONS_CORE10",
         "PerPkg": "1",
@@ -321,7 +272,6 @@
     },
     {
         "BriefDescription": "Core 11 C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x43",
         "EventName": "UNC_P_DEMOTIONS_CORE11",
         "PerPkg": "1",
@@ -330,7 +280,6 @@
     },
     {
         "BriefDescription": "Core 12 C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x44",
         "EventName": "UNC_P_DEMOTIONS_CORE12",
         "PerPkg": "1",
@@ -339,7 +288,6 @@
     },
     {
         "BriefDescription": "Core 13 C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x45",
         "EventName": "UNC_P_DEMOTIONS_CORE13",
         "PerPkg": "1",
@@ -348,7 +296,6 @@
     },
     {
         "BriefDescription": "Core 14 C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x46",
         "EventName": "UNC_P_DEMOTIONS_CORE14",
         "PerPkg": "1",
@@ -357,7 +304,6 @@
     },
     {
         "BriefDescription": "Core 2 C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "UNC_P_DEMOTIONS_CORE2",
         "PerPkg": "1",
@@ -366,7 +312,6 @@
     },
     {
         "BriefDescription": "Core 3 C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_P_DEMOTIONS_CORE3",
         "PerPkg": "1",
@@ -375,7 +320,6 @@
     },
     {
         "BriefDescription": "Core 4 C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_P_DEMOTIONS_CORE4",
         "PerPkg": "1",
@@ -384,7 +328,6 @@
     },
     {
         "BriefDescription": "Core 5 C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x23",
         "EventName": "UNC_P_DEMOTIONS_CORE5",
         "PerPkg": "1",
@@ -393,7 +336,6 @@
     },
     {
         "BriefDescription": "Core 6 C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_P_DEMOTIONS_CORE6",
         "PerPkg": "1",
@@ -402,7 +344,6 @@
     },
     {
         "BriefDescription": "Core 7 C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x25",
         "EventName": "UNC_P_DEMOTIONS_CORE7",
         "PerPkg": "1",
@@ -411,7 +352,6 @@
     },
     {
         "BriefDescription": "Core 8 C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_P_DEMOTIONS_CORE8",
         "PerPkg": "1",
@@ -420,7 +360,6 @@
     },
     {
         "BriefDescription": "Core 9 C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_P_DEMOTIONS_CORE9",
         "PerPkg": "1",
@@ -429,7 +368,6 @@
     },
     {
         "BriefDescription": "Frequency Residency",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb",
         "EventName": "UNC_P_FREQ_BAND0_CYCLES",
         "PerPkg": "1",
@@ -438,7 +376,6 @@
     },
     {
         "BriefDescription": "Frequency Residency",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc",
         "EventName": "UNC_P_FREQ_BAND1_CYCLES",
         "PerPkg": "1",
@@ -447,7 +384,6 @@
     },
     {
         "BriefDescription": "Frequency Residency",
-        "Counter": "0,1,2,3",
         "EventCode": "0xd",
         "EventName": "UNC_P_FREQ_BAND2_CYCLES",
         "PerPkg": "1",
@@ -456,7 +392,6 @@
     },
     {
         "BriefDescription": "Frequency Residency",
-        "Counter": "0,1,2,3",
         "EventCode": "0xe",
         "EventName": "UNC_P_FREQ_BAND3_CYCLES",
         "PerPkg": "1",
@@ -465,7 +400,6 @@
     },
     {
         "BriefDescription": "Current Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_P_FREQ_MAX_CURRENT_CYCLES",
         "PerPkg": "1",
@@ -474,7 +408,6 @@
     },
     {
         "BriefDescription": "Thermal Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
         "PerPkg": "1",
@@ -483,7 +416,6 @@
     },
     {
         "BriefDescription": "OS Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_P_FREQ_MAX_OS_CYCLES",
         "PerPkg": "1",
@@ -492,7 +424,6 @@
     },
     {
         "BriefDescription": "Power Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
         "PerPkg": "1",
@@ -501,7 +432,6 @@
     },
     {
         "BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x61",
         "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
         "PerPkg": "1",
@@ -510,7 +440,6 @@
     },
     {
         "BriefDescription": "Perf P Limit Strongest Lower Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x62",
         "EventName": "UNC_P_FREQ_MIN_PERF_P_CYCLES",
         "PerPkg": "1",
@@ -519,7 +448,6 @@
     },
     {
         "BriefDescription": "Cycles spent changing Frequency",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_P_FREQ_TRANS_CYCLES",
         "PerPkg": "1",
@@ -528,7 +456,6 @@
     },
     {
         "BriefDescription": "Memory Phase Shedding Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2f",
         "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
         "PerPkg": "1",
@@ -537,67 +464,54 @@
     },
     {
         "BriefDescription": "Package C State Exit Latency",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "UNC_P_PKG_C_EXIT_LATENCY",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the package is transitioning from package C2 to C3.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Exit Latency",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "UNC_P_PKG_C_EXIT_LATENCY_SEL",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the package is transitioning from package C2 to C3.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2a",
         "EventName": "UNC_P_PKG_C_STATE_RESIDENCY_C0_CYCLES",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the package is in C0",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2b",
         "EventName": "UNC_P_PKG_C_STATE_RESIDENCY_C2_CYCLES",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the package is in C2",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2c",
         "EventName": "UNC_P_PKG_C_STATE_RESIDENCY_C3_CYCLES",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the package is in C3",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C6",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2d",
         "EventName": "UNC_P_PKG_C_STATE_RESIDENCY_C6_CYCLES",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles that the package is in C6",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Number of cores in C-State; C0 and C1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
         "PerPkg": "1",
@@ -606,7 +520,6 @@
     },
     {
         "BriefDescription": "Number of cores in C-State; C3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
         "PerPkg": "1",
@@ -615,7 +528,6 @@
     },
     {
         "BriefDescription": "Number of cores in C-State; C6 and C7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
         "PerPkg": "1",
@@ -624,7 +536,6 @@
     },
     {
         "BriefDescription": "External Prochot",
-        "Counter": "0,1,2,3",
         "EventCode": "0xa",
         "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
         "PerPkg": "1",
@@ -633,7 +544,6 @@
     },
     {
         "BriefDescription": "Internal Prochot",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
         "PerPkg": "1",
@@ -642,7 +552,6 @@
     },
     {
         "BriefDescription": "Total Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x63",
         "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -651,7 +560,6 @@
     },
     {
         "BriefDescription": "Cycles Changing Voltage",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_P_VOLT_TRANS_CYCLES_CHANGE",
         "PerPkg": "1",
@@ -660,7 +568,6 @@
     },
     {
         "BriefDescription": "Cycles Decreasing Voltage",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_P_VOLT_TRANS_CYCLES_DECREASE",
         "PerPkg": "1",
@@ -669,7 +576,6 @@
     },
     {
         "BriefDescription": "Cycles Increasing Voltage",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_P_VOLT_TRANS_CYCLES_INCREASE",
         "PerPkg": "1",
@@ -678,7 +584,6 @@
     },
     {
         "BriefDescription": "VR Hot",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_P_VR_HOT_CYCLES",
         "PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json b/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json
index 6624d02ad7154..410763dd43949 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED",
         "SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
     },
     {
         "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION",
         "SampleAfterValue": "2000003",
@@ -19,8 +15,6 @@
     },
     {
         "BriefDescription": "Page walk for a large page completed for Demand load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED",
         "SampleAfterValue": "100003",
@@ -28,8 +22,6 @@
     },
     {
         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
         "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand loads.",
@@ -38,8 +30,6 @@
     },
     {
         "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5F",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
         "PublicDescription": "Counts load operations that missed 1st level DTLB but hit the 2nd level.",
@@ -48,8 +38,6 @@
     },
     {
         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
         "PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by demand loads.",
@@ -58,8 +46,6 @@
     },
     {
         "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
         "PublicDescription": "Cycle PMH is busy with a walk due to demand loads.",
@@ -68,8 +54,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
         "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
@@ -78,8 +62,6 @@
     },
     {
         "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT",
         "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
@@ -88,8 +70,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
         "PublicDescription": "Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G).",
@@ -98,8 +78,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_DURATION",
         "PublicDescription": "Cycles PMH is busy with this walk.",
@@ -108,8 +86,6 @@
     },
     {
         "BriefDescription": "Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4F",
         "EventName": "EPT.WALK_CYCLES",
         "SampleAfterValue": "2000003",
@@ -117,8 +93,6 @@
     },
     {
         "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAE",
         "EventName": "ITLB.ITLB_FLUSH",
         "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.",
@@ -127,8 +101,6 @@
     },
     {
         "BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED",
         "PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.",
@@ -137,8 +109,6 @@
     },
     {
         "BriefDescription": "Misses at all ITLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
         "PublicDescription": "Misses in all ITLB levels that cause page walks.",
@@ -147,8 +117,6 @@
     },
     {
         "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT",
         "PublicDescription": "Number of cache load STLB hits. No page walk.",
@@ -157,8 +125,6 @@
     },
     {
         "BriefDescription": "Misses in all ITLB levels that cause completed page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
         "PublicDescription": "Misses in all ITLB levels that cause completed page walks.",
@@ -167,8 +133,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_DURATION",
         "PublicDescription": "Cycle PMH is busy with a walk.",
@@ -177,8 +141,6 @@
     },
     {
         "BriefDescription": "DTLB flush attempts of the thread-specific entries",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.DTLB_THREAD",
         "PublicDescription": "DTLB flush attempts of the thread-specific entries.",
@@ -187,8 +149,6 @@
     },
     {
         "BriefDescription": "STLB flush attempts",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.STLB_ANY",
         "PublicDescription": "Count number of STLB flush attempts.",
-- 
GitLab


From e85af8a641ba3e8e4dab3e82f4a17f06378d47ff Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:54:56 -0800
Subject: [PATCH 580/875] perf vendor events intel: Refresh jaketown metrics
 and events

Update the jaketown metrics and events using the new tooling from:

  https://github.com/intel/perfmon

The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1".  The
events are unchanged but unused json values are removed. The
formatting changes increase consistency across the json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-10-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../pmu-events/arch/x86/jaketown/cache.json   | 289 ------------------
 .../arch/x86/jaketown/floating-point.json     |  30 --
 .../arch/x86/jaketown/frontend.json           |  64 ----
 .../arch/x86/jaketown/jkt-metrics.json        |  91 +++---
 .../pmu-events/arch/x86/jaketown/memory.json  | 103 -------
 .../pmu-events/arch/x86/jaketown/other.json   |  12 -
 .../arch/x86/jaketown/pipeline.json           | 255 ----------------
 .../arch/x86/jaketown/uncore-cache.json       | 266 +++-------------
 .../x86/jaketown/uncore-interconnect.json     | 132 --------
 .../arch/x86/jaketown/uncore-memory.json      |  58 ----
 .../arch/x86/jaketown/uncore-other.json       | 155 +---------
 .../arch/x86/jaketown/uncore-power.json       |  51 ----
 .../arch/x86/jaketown/virtual-memory.json     |  32 --
 13 files changed, 106 insertions(+), 1432 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/jaketown/cache.json b/tools/perf/pmu-events/arch/x86/jaketown/cache.json
index f98649fb92b4a..f1271039b6b23 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/cache.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/cache.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Allocated L1D data cache lines in M state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x51",
         "EventName": "L1D.ALLOCATED_IN_M",
         "SampleAfterValue": "2000003",
@@ -10,8 +8,6 @@
     },
     {
         "BriefDescription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x51",
         "EventName": "L1D.ALL_M_REPLACEMENT",
         "SampleAfterValue": "2000003",
@@ -19,8 +15,6 @@
     },
     {
         "BriefDescription": "L1D data cache lines in M state evicted due to replacement.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x51",
         "EventName": "L1D.EVICTION",
         "SampleAfterValue": "2000003",
@@ -28,8 +22,6 @@
     },
     {
         "BriefDescription": "L1D data line replacements.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x51",
         "EventName": "L1D.REPLACEMENT",
         "PublicDescription": "This event counts L1D data line replacements.  Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier.",
@@ -38,8 +30,6 @@
     },
     {
         "BriefDescription": "Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xBF",
         "EventName": "L1D_BLOCKS.BANK_CONFLICT_CYCLES",
@@ -48,8 +38,6 @@
     },
     {
         "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.FB_FULL",
@@ -58,8 +46,6 @@
     },
     {
         "BriefDescription": "L1D miss oustandings duration in cycles.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING",
         "SampleAfterValue": "2000003",
@@ -67,8 +53,6 @@
     },
     {
         "BriefDescription": "Cycles with L1D load Misses outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -78,8 +62,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -88,8 +70,6 @@
     },
     {
         "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "L2_L1D_WB_RQSTS.ALL",
         "SampleAfterValue": "200003",
@@ -97,8 +77,6 @@
     },
     {
         "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "L2_L1D_WB_RQSTS.HIT_E",
         "SampleAfterValue": "200003",
@@ -106,8 +84,6 @@
     },
     {
         "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "L2_L1D_WB_RQSTS.HIT_M",
         "SampleAfterValue": "200003",
@@ -115,8 +91,6 @@
     },
     {
         "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in S state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "L2_L1D_WB_RQSTS.HIT_S",
         "SampleAfterValue": "200003",
@@ -124,8 +98,6 @@
     },
     {
         "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "L2_L1D_WB_RQSTS.MISS",
         "SampleAfterValue": "200003",
@@ -133,8 +105,6 @@
     },
     {
         "BriefDescription": "L2 cache lines filling L2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.ALL",
         "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache.  Lines are filled into the L2 cache when there was an L2 miss.",
@@ -143,8 +113,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in E state filling L2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.E",
         "SampleAfterValue": "100003",
@@ -152,8 +120,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in I state filling L2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.I",
         "SampleAfterValue": "100003",
@@ -161,8 +127,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in S state filling L2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.S",
         "SampleAfterValue": "100003",
@@ -170,8 +134,6 @@
     },
     {
         "BriefDescription": "Clean L2 cache lines evicted by demand.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
         "SampleAfterValue": "100003",
@@ -179,8 +141,6 @@
     },
     {
         "BriefDescription": "Dirty L2 cache lines evicted by demand.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
         "SampleAfterValue": "100003",
@@ -188,8 +148,6 @@
     },
     {
         "BriefDescription": "Dirty L2 cache lines filling the L2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DIRTY_ALL",
         "SampleAfterValue": "100003",
@@ -197,8 +155,6 @@
     },
     {
         "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.PF_CLEAN",
         "SampleAfterValue": "100003",
@@ -206,8 +162,6 @@
     },
     {
         "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.PF_DIRTY",
         "SampleAfterValue": "100003",
@@ -215,8 +169,6 @@
     },
     {
         "BriefDescription": "L2 code requests.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_CODE_RD",
         "SampleAfterValue": "200003",
@@ -224,8 +176,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
         "SampleAfterValue": "200003",
@@ -233,8 +183,6 @@
     },
     {
         "BriefDescription": "Requests from L2 hardware prefetchers.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_PF",
         "SampleAfterValue": "200003",
@@ -242,8 +190,6 @@
     },
     {
         "BriefDescription": "RFO requests to L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_RFO",
         "SampleAfterValue": "200003",
@@ -251,8 +197,6 @@
     },
     {
         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_HIT",
         "SampleAfterValue": "200003",
@@ -260,8 +204,6 @@
     },
     {
         "BriefDescription": "L2 cache misses when fetching instructions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_MISS",
         "SampleAfterValue": "200003",
@@ -269,8 +211,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests that hit L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
         "SampleAfterValue": "200003",
@@ -278,8 +218,6 @@
     },
     {
         "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PF_HIT",
         "SampleAfterValue": "200003",
@@ -287,8 +225,6 @@
     },
     {
         "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PF_MISS",
         "SampleAfterValue": "200003",
@@ -296,8 +232,6 @@
     },
     {
         "BriefDescription": "RFO requests that hit L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_HIT",
         "SampleAfterValue": "200003",
@@ -305,8 +239,6 @@
     },
     {
         "BriefDescription": "RFO requests that miss L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_MISS",
         "SampleAfterValue": "200003",
@@ -314,8 +246,6 @@
     },
     {
         "BriefDescription": "RFOs that access cache lines in any state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x27",
         "EventName": "L2_STORE_LOCK_RQSTS.ALL",
         "SampleAfterValue": "200003",
@@ -323,8 +253,6 @@
     },
     {
         "BriefDescription": "RFOs that hit cache lines in E state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x27",
         "EventName": "L2_STORE_LOCK_RQSTS.HIT_E",
         "SampleAfterValue": "200003",
@@ -332,8 +260,6 @@
     },
     {
         "BriefDescription": "RFOs that hit cache lines in M state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x27",
         "EventName": "L2_STORE_LOCK_RQSTS.HIT_M",
         "SampleAfterValue": "200003",
@@ -341,8 +267,6 @@
     },
     {
         "BriefDescription": "RFOs that miss cache lines.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x27",
         "EventName": "L2_STORE_LOCK_RQSTS.MISS",
         "SampleAfterValue": "200003",
@@ -350,8 +274,6 @@
     },
     {
         "BriefDescription": "L2 or LLC HW prefetches that access L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.ALL_PF",
         "SampleAfterValue": "200003",
@@ -359,8 +281,6 @@
     },
     {
         "BriefDescription": "Transactions accessing L2 pipe.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.ALL_REQUESTS",
         "SampleAfterValue": "200003",
@@ -368,8 +288,6 @@
     },
     {
         "BriefDescription": "L2 cache accesses when fetching instructions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.CODE_RD",
         "SampleAfterValue": "200003",
@@ -377,8 +295,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests that access L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.DEMAND_DATA_RD",
         "SampleAfterValue": "200003",
@@ -386,8 +302,6 @@
     },
     {
         "BriefDescription": "L1D writebacks that access L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L1D_WB",
         "SampleAfterValue": "200003",
@@ -395,8 +309,6 @@
     },
     {
         "BriefDescription": "L2 fill requests that access L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L2_FILL",
         "SampleAfterValue": "200003",
@@ -404,8 +316,6 @@
     },
     {
         "BriefDescription": "L2 writebacks that access L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L2_WB",
         "SampleAfterValue": "200003",
@@ -413,8 +323,6 @@
     },
     {
         "BriefDescription": "RFO requests that access L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.RFO",
         "SampleAfterValue": "200003",
@@ -422,8 +330,6 @@
     },
     {
         "BriefDescription": "Cycles when L1D is locked.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x63",
         "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
         "SampleAfterValue": "2000003",
@@ -431,8 +337,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests missed LLC.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.MISS",
         "SampleAfterValue": "100003",
@@ -440,8 +344,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests that refer to LLC.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
         "SampleAfterValue": "100003",
@@ -449,8 +351,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",
         "PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package).  Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line.  In this case, a snoop was required, and another L2 had the line in a non-modified state.",
@@ -459,8 +359,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",
         "PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package).  Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line.  In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2.",
@@ -469,8 +367,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",
         "SampleAfterValue": "20011",
@@ -478,8 +374,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",
         "SampleAfterValue": "100003",
@@ -487,8 +381,6 @@
     },
     {
         "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD3",
         "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",
         "SampleAfterValue": "100007",
@@ -496,8 +388,6 @@
     },
     {
         "BriefDescription": "Data from remote DRAM either Snoop not needed or Snoop Miss (RspI)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD3",
         "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM",
         "SampleAfterValue": "100007",
@@ -505,8 +395,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
         "PEBS": "1",
@@ -515,8 +403,6 @@
     },
     {
         "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
         "PEBS": "1",
@@ -525,8 +411,6 @@
     },
     {
         "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
         "PEBS": "1",
@@ -535,8 +419,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",
         "PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache without snoops required.",
@@ -545,8 +427,6 @@
     },
     {
         "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS",
         "SampleAfterValue": "100007",
@@ -554,8 +434,6 @@
     },
     {
         "BriefDescription": "All retired load uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
         "PEBS": "1",
@@ -565,8 +443,6 @@
     },
     {
         "BriefDescription": "All retired store uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
         "PEBS": "1",
@@ -576,8 +452,6 @@
     },
     {
         "BriefDescription": "Retired load uops with locked access.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
         "PEBS": "1",
@@ -586,8 +460,6 @@
     },
     {
         "BriefDescription": "Retired load uops that split across a cacheline boundary.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
         "PEBS": "1",
@@ -597,8 +469,6 @@
     },
     {
         "BriefDescription": "Retired store uops that split across a cacheline boundary.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
         "PEBS": "1",
@@ -608,8 +478,6 @@
     },
     {
         "BriefDescription": "Retired load uops that miss the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
         "PEBS": "1",
@@ -618,8 +486,6 @@
     },
     {
         "BriefDescription": "Retired store uops that miss the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
         "PEBS": "1",
@@ -628,8 +494,6 @@
     },
     {
         "BriefDescription": "Demand and prefetch data reads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
         "SampleAfterValue": "100003",
@@ -637,8 +501,6 @@
     },
     {
         "BriefDescription": "Cacheable and noncachaeble code read requests.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
         "SampleAfterValue": "100003",
@@ -646,8 +508,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests sent to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
         "SampleAfterValue": "100003",
@@ -655,8 +515,6 @@
     },
     {
         "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
         "SampleAfterValue": "100003",
@@ -664,8 +522,6 @@
     },
     {
         "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB2",
         "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
         "SampleAfterValue": "2000003",
@@ -673,8 +529,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
         "SampleAfterValue": "2000003",
@@ -682,8 +536,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
@@ -692,8 +544,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
@@ -702,8 +552,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
@@ -712,8 +560,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
         "SampleAfterValue": "2000003",
@@ -721,8 +567,6 @@
     },
     {
         "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "6",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6",
@@ -731,8 +575,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
         "SampleAfterValue": "2000003",
@@ -740,524 +582,393 @@
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x000105B3",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads that hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0090",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0090",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0090",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0090",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0090",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo references (demand & prefetch)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x000107F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c03f7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c03f7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c03f7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c03f7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c03f7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch prefetch RFOs",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00010122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all writebacks from the core to the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10008",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00010004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that hit in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00010001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data reads that hit in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand rfo's",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00010002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803c8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23ffc08000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0200",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts non-temporal stores",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10800",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Split locks in SQ.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF4",
         "EventName": "SQ_MISC.SPLIT_LOCK",
         "SampleAfterValue": "100003",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json b/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json
index eb2ff2cfdf6b0..8c2a246adef97 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Cycles with any input/output SSE or FP assist.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.ANY",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Number of SIMD FP assists due to input values.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.SIMD_INPUT",
         "SampleAfterValue": "100003",
@@ -20,8 +16,6 @@
     },
     {
         "BriefDescription": "Number of SIMD FP assists due to Output values.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.SIMD_OUTPUT",
         "SampleAfterValue": "100003",
@@ -29,8 +23,6 @@
     },
     {
         "BriefDescription": "Number of X87 assists due to input value.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.X87_INPUT",
         "SampleAfterValue": "100003",
@@ -38,8 +30,6 @@
     },
     {
         "BriefDescription": "Number of X87 assists due to output value.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.X87_OUTPUT",
         "SampleAfterValue": "100003",
@@ -47,8 +37,6 @@
     },
     {
         "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",
         "SampleAfterValue": "2000003",
@@ -56,8 +44,6 @@
     },
     {
         "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",
         "SampleAfterValue": "2000003",
@@ -65,8 +51,6 @@
     },
     {
         "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",
         "SampleAfterValue": "2000003",
@@ -74,8 +58,6 @@
     },
     {
         "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",
         "SampleAfterValue": "2000003",
@@ -83,8 +65,6 @@
     },
     {
         "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.X87",
         "SampleAfterValue": "2000003",
@@ -92,8 +72,6 @@
     },
     {
         "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.AVX_STORE",
         "SampleAfterValue": "100003",
@@ -101,8 +79,6 @@
     },
     {
         "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.AVX_TO_SSE",
         "SampleAfterValue": "100003",
@@ -110,8 +86,6 @@
     },
     {
         "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.SSE_TO_AVX",
         "SampleAfterValue": "100003",
@@ -119,8 +93,6 @@
     },
     {
         "BriefDescription": "Number of AVX-256 Computational FP double precision uops issued this cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x11",
         "EventName": "SIMD_FP_256.PACKED_DOUBLE",
         "SampleAfterValue": "2000003",
@@ -128,8 +100,6 @@
     },
     {
         "BriefDescription": "Number of GSSE-256 Computational FP single precision uops issued this cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x11",
         "EventName": "SIMD_FP_256.PACKED_SINGLE",
         "SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/frontend.json b/tools/perf/pmu-events/arch/x86/jaketown/frontend.json
index 0b4dbce2f1c04..3f4fc34811127 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/frontend.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xE6",
         "EventName": "BACLEARS.ANY",
         "SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
     },
     {
         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAB",
         "EventName": "DSB2MITE_SWITCHES.COUNT",
         "SampleAfterValue": "2000003",
@@ -19,8 +15,6 @@
     },
     {
         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAB",
         "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
         "PublicDescription": "This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline.  It excludes cycles when the back-end cannot  accept new micro-ops.  The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.",
@@ -29,8 +23,6 @@
     },
     {
         "BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAC",
         "EventName": "DSB_FILL.ALL_CANCEL",
         "SampleAfterValue": "2000003",
@@ -38,8 +30,6 @@
     },
     {
         "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAC",
         "EventName": "DSB_FILL.EXCEED_DSB_LINES",
         "SampleAfterValue": "2000003",
@@ -47,8 +37,6 @@
     },
     {
         "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAC",
         "EventName": "DSB_FILL.OTHER_CANCEL",
         "SampleAfterValue": "2000003",
@@ -56,8 +44,6 @@
     },
     {
         "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.HIT",
         "SampleAfterValue": "2000003",
@@ -65,8 +51,6 @@
     },
     {
         "BriefDescription": "Instruction cache, streaming buffer and victim cache misses.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.MISSES",
         "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.",
@@ -75,8 +59,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -85,8 +67,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -95,8 +75,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering 4 Uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -105,8 +83,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering any Uop.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -115,8 +91,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_CYCLES",
@@ -125,8 +99,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_UOPS",
         "SampleAfterValue": "2000003",
@@ -134,8 +106,6 @@
     },
     {
         "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0x79",
         "EventName": "IDQ.EMPTY",
         "SampleAfterValue": "2000003",
@@ -143,8 +113,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_ALL_UOPS",
         "SampleAfterValue": "2000003",
@@ -152,8 +120,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_CYCLES",
@@ -162,8 +128,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_UOPS",
         "SampleAfterValue": "2000003",
@@ -171,8 +135,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_CYCLES",
@@ -182,8 +144,6 @@
     },
     {
         "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_DSB_CYCLES",
@@ -192,8 +152,6 @@
     },
     {
         "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
@@ -203,8 +161,6 @@
     },
     {
         "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_DSB_UOPS",
         "SampleAfterValue": "2000003",
@@ -212,8 +168,6 @@
     },
     {
         "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_MITE_UOPS",
         "SampleAfterValue": "2000003",
@@ -221,8 +175,6 @@
     },
     {
         "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
@@ -232,8 +184,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_UOPS",
         "SampleAfterValue": "2000003",
@@ -241,8 +191,6 @@
     },
     {
         "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled .",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
         "PublicDescription": "This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled.  In the ideal case 4 uops can be delivered each cycle.  The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them.  This event is used in determining the front-end bound category of the top-down pipeline slots characterization.",
@@ -251,8 +199,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -261,8 +207,6 @@
     },
     {
         "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@@ -272,8 +216,6 @@
     },
     {
         "BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE",
@@ -283,8 +225,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "3",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@@ -293,8 +233,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@@ -303,8 +241,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json b/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json
index 554f87c03c05f..cb1420df3768a 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json
@@ -65,7 +65,7 @@
     },
     {
         "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
-        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
         "MetricGroup": "TopdownL1;tma_L1_group",
         "MetricName": "tma_bad_speculation",
         "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
@@ -73,7 +73,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
-        "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
+        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
         "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
         "MetricName": "tma_branch_mispredicts",
         "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
@@ -97,7 +97,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
-        "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB)) * tma_backend_bound",
+        "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if IPC > 1.8 else (cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) * tma_backend_bound",
         "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
         "MetricName": "tma_memory_bound",
         "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@@ -113,7 +113,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
-        "MetricExpr": "(MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
+        "MetricExpr": "MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
         "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_l3_bound",
         "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
@@ -121,7 +121,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
-        "MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS))) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
+        "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
         "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_dram_bound",
         "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS",
@@ -169,7 +169,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
-        "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING)) / CLKS",
+        "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if IPC > 1.8 else (cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING)) / CLKS",
         "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
         "MetricName": "tma_ports_utilization",
         "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@@ -233,7 +233,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
-        "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
         "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
         "MetricName": "tma_microcode_sequencer",
         "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
@@ -284,19 +284,19 @@
     },
     {
         "BriefDescription": "Floating Point Operations Per Cycle",
-        "MetricExpr": "(1 * (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / CORE_CLKS",
+        "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / CORE_CLKS",
         "MetricGroup": "Flops;Ret",
         "MetricName": "FLOPc"
     },
     {
         "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
-        "MetricExpr": "UOPS_DISPATCHED.THREAD / ((cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@ / 2) if #SMT_on else cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@)",
+        "MetricExpr": "UOPS_DISPATCHED.THREAD / (cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@)",
         "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
         "MetricName": "ILP"
     },
     {
         "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
-        "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
+        "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
         "MetricGroup": "SMT",
         "MetricName": "CORE_CLKS"
     },
@@ -314,25 +314,25 @@
     },
     {
         "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
-        "MetricExpr": "IDQ.DSB_UOPS / ((IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS))",
+        "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
         "MetricGroup": "DSB;Fed;FetchBW",
         "MetricName": "DSB_Coverage"
     },
     {
         "BriefDescription": "Average CPU Utilization",
-        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
+        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
         "MetricGroup": "HPC;Summary",
         "MetricName": "CPU_Utilization"
     },
     {
         "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
-        "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
+        "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
         "MetricGroup": "Power;Summary",
         "MetricName": "Average_Frequency"
     },
     {
         "BriefDescription": "Giga Floating Point Operations Per Second",
-        "MetricExpr": "((1 * (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1000000000) / duration_time",
+        "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1e9 / duration_time",
         "MetricGroup": "Cor;Flops;HPC",
         "MetricName": "GFLOPs",
         "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
@@ -345,7 +345,7 @@
     },
     {
         "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
-        "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
+        "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
         "MetricGroup": "SMT",
         "MetricName": "SMT_2T_Utilization"
     },
@@ -363,10 +363,22 @@
     },
     {
         "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
-        "MetricExpr": "(64 * (uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@) / 1000000000) / duration_time",
+        "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time",
         "MetricGroup": "HPC;Mem;MemoryBW;SoC",
         "MetricName": "DRAM_BW_Use"
     },
+    {
+        "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
+        "MetricExpr": "1e9 * (UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_INSERTS.MISS_OPCODE@filter_opc\\=0x182@) / (Socket_CLKS / duration_time)",
+        "MetricGroup": "Mem;MemoryLat;SoC",
+        "MetricName": "MEM_Read_Latency"
+    },
+    {
+        "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
+        "MetricExpr": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182\\,thresh\\=1@",
+        "MetricGroup": "Mem;MemoryBW;SoC",
+        "MetricName": "MEM_Parallel_Reads"
+    },
     {
         "BriefDescription": "Socket actual clocks when any core is active on that socket",
         "MetricExpr": "cbox_0@event\\=0x0@",
@@ -379,52 +391,59 @@
         "MetricGroup": "Branches;OS",
         "MetricName": "IpFarBranch"
     },
+    {
+        "BriefDescription": "Uncore frequency per die [GHZ]",
+        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+        "MetricGroup": "SoC",
+        "MetricName": "UNCORE_FREQ"
+    },
     {
         "BriefDescription": "C3 residency percent per core",
-        "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C3_Core_Residency"
+        "MetricName": "C3_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C6 residency percent per core",
-        "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C6_Core_Residency"
+        "MetricName": "C6_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C7 residency percent per core",
-        "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C7_Core_Residency"
+        "MetricName": "C7_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C2 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C2_Pkg_Residency"
+        "MetricName": "C2_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C3 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C3_Pkg_Residency"
+        "MetricName": "C3_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C6 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C6_Pkg_Residency"
+        "MetricName": "C6_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C7 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C7_Pkg_Residency"
-    },
-    {
-        "BriefDescription": "Uncore frequency per die [GHZ]",
-        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000",
-        "MetricGroup": "SoC",
-        "MetricName": "UNCORE_FREQ"
+        "MetricName": "C7_Pkg_Residency",
+        "ScaleUnit": "100%"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/memory.json b/tools/perf/pmu-events/arch/x86/jaketown/memory.json
index 23756ca9b7da1..a71e630fd0308 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/memory.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
         "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers.  Machine clears can have a significant performance impact if they are happening frequently.",
@@ -11,124 +9,94 @@
     },
     {
         "BriefDescription": "Loads with latency value being above 128.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x80",
         "PEBS": "2",
         "SampleAfterValue": "1009",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 16.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x10",
         "PEBS": "2",
         "SampleAfterValue": "20011",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 256.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x100",
         "PEBS": "2",
         "SampleAfterValue": "503",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 32.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x20",
         "PEBS": "2",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 4 .",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x4",
         "PEBS": "2",
         "SampleAfterValue": "100003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 512.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x200",
         "PEBS": "2",
         "SampleAfterValue": "101",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 64.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x40",
         "PEBS": "2",
         "SampleAfterValue": "2003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 8.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x8",
         "PEBS": "2",
         "SampleAfterValue": "50021",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
         "PEBS": "2",
-        "PRECISE_STORE": "1",
         "SampleAfterValue": "2000003",
-        "TakenAlone": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x05",
         "EventName": "MISALIGN_MEM_REF.LOADS",
         "SampleAfterValue": "2000003",
@@ -136,8 +104,6 @@
     },
     {
         "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x05",
         "EventName": "MISALIGN_MEM_REF.STORES",
         "SampleAfterValue": "2000003",
@@ -145,277 +111,208 @@
     },
     {
         "BriefDescription": "This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFFC20077",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x600400077",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.REMOTE_HITM_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x187FC20077",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that miss the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3fffc20004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that miss the LLC  and the data returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x600400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that miss the LLC  and the data returned from remote dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x67f800004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x107fc00004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that miss the LLC  and the data forwarded from remote cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x87f820004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that miss the LLC  and the data returned from remote & local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x67fc00001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that miss in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3fffc20001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that miss the LLC  and the data returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x600400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that miss the LLC  and the data returned from remote dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x67f800001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x107fc00001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that miss the LLC  and the data forwarded from remote cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x87f820001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from remote & local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3fffc20040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from remote & local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x67fc00010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3fffc20010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x600400010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads  that miss the LLC  and the data returned from remote dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x67f800010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  the data is found in M state in remote cache and forwarded from there",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x107fc00010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data forwarded from remote cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x87f820010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3fffc20200",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3fffc20080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     }
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/other.json b/tools/perf/pmu-events/arch/x86/jaketown/other.json
index 2f873ab14156b..9f96121baef8e 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/other.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/other.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Unhalted core cycles when the thread is in ring 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5C",
         "EventName": "CPL_CYCLES.RING0",
         "SampleAfterValue": "2000003",
@@ -10,8 +8,6 @@
     },
     {
         "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5C",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5C",
         "EventName": "CPL_CYCLES.RING123",
         "SampleAfterValue": "2000003",
@@ -30,8 +24,6 @@
     },
     {
         "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4E",
         "EventName": "HW_PRE_REQ.DL1_MISS",
         "SampleAfterValue": "2000003",
@@ -39,8 +31,6 @@
     },
     {
         "BriefDescription": "Valid instructions written to IQ per cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x17",
         "EventName": "INSTS_WRITTEN_TO_IQ.INSTS",
         "SampleAfterValue": "2000003",
@@ -48,8 +38,6 @@
     },
     {
         "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x63",
         "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
         "SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json b/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json
index 61a3db4d67d51..11d41ce8c9225 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB6",
         "EventName": "AGU_BYPASS_CANCEL.COUNT",
         "SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
     },
     {
         "BriefDescription": "Divide operations executed.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x14",
@@ -22,8 +18,6 @@
     },
     {
         "BriefDescription": "Cycles when divider is busy executing divide operations.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x14",
         "EventName": "ARITH.FPU_DIV_ACTIVE",
         "SampleAfterValue": "2000003",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Speculative and retired  branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_BRANCHES",
         "SampleAfterValue": "200003",
@@ -40,8 +32,6 @@
     },
     {
         "BriefDescription": "Speculative and retired macro-conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -49,8 +39,6 @@
     },
     {
         "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
         "SampleAfterValue": "200003",
@@ -58,8 +46,6 @@
     },
     {
         "BriefDescription": "Speculative and retired direct near calls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
         "SampleAfterValue": "200003",
@@ -67,8 +53,6 @@
     },
     {
         "BriefDescription": "Speculative and retired indirect branches excluding calls and returns.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
         "SampleAfterValue": "200003",
@@ -76,8 +60,6 @@
     },
     {
         "BriefDescription": "Speculative and retired indirect return branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
         "SampleAfterValue": "200003",
@@ -85,8 +67,6 @@
     },
     {
         "BriefDescription": "Not taken macro-conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -94,8 +74,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired macro-conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -103,8 +81,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
         "SampleAfterValue": "200003",
@@ -112,8 +88,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired direct near calls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
         "SampleAfterValue": "200003",
@@ -121,8 +95,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
         "SampleAfterValue": "200003",
@@ -130,8 +102,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect calls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
         "SampleAfterValue": "200003",
@@ -139,8 +109,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
         "SampleAfterValue": "200003",
@@ -148,16 +116,12 @@
     },
     {
         "BriefDescription": "All (macro) branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "SampleAfterValue": "400009"
     },
     {
         "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
         "PEBS": "2",
@@ -166,8 +130,6 @@
     },
     {
         "BriefDescription": "Conditional branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -176,8 +138,6 @@
     },
     {
         "BriefDescription": "Far branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.FAR_BRANCH",
         "SampleAfterValue": "100007",
@@ -185,8 +145,6 @@
     },
     {
         "BriefDescription": "Direct and indirect near call instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -195,8 +153,6 @@
     },
     {
         "BriefDescription": "Return instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_RETURN",
         "PEBS": "1",
@@ -205,8 +161,6 @@
     },
     {
         "BriefDescription": "Taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
@@ -215,8 +169,6 @@
     },
     {
         "BriefDescription": "Not taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NOT_TAKEN",
         "SampleAfterValue": "400009",
@@ -224,8 +176,6 @@
     },
     {
         "BriefDescription": "Speculative and retired mispredicted macro conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_BRANCHES",
         "SampleAfterValue": "200003",
@@ -233,8 +183,6 @@
     },
     {
         "BriefDescription": "Speculative and retired mispredicted macro conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -242,8 +190,6 @@
     },
     {
         "BriefDescription": "Speculative and retired mispredicted direct near calls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL",
         "SampleAfterValue": "200003",
@@ -251,8 +197,6 @@
     },
     {
         "BriefDescription": "Mispredicted indirect branches excluding calls and returns.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
         "SampleAfterValue": "200003",
@@ -260,8 +204,6 @@
     },
     {
         "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -269,8 +211,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -278,8 +218,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted direct near calls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL",
         "SampleAfterValue": "200003",
@@ -287,8 +225,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
         "SampleAfterValue": "200003",
@@ -296,8 +232,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect calls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
         "SampleAfterValue": "200003",
@@ -305,8 +239,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
         "SampleAfterValue": "200003",
@@ -314,27 +246,20 @@
     },
     {
         "BriefDescription": "All mispredicted macro branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "SampleAfterValue": "400009"
     },
     {
         "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
         "PEBS": "2",
-        "PublicDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
         "SampleAfterValue": "400009",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Mispredicted conditional branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -343,8 +268,6 @@
     },
     {
         "BriefDescription": "Direct and indirect mispredicted near call instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -353,8 +276,6 @@
     },
     {
         "BriefDescription": "Mispredicted not taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NOT_TAKEN",
         "PEBS": "1",
@@ -363,8 +284,6 @@
     },
     {
         "BriefDescription": "Mispredicted taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.TAKEN",
         "PEBS": "1",
@@ -373,8 +292,6 @@
     },
     {
         "BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "2000003",
@@ -382,8 +299,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
         "SampleAfterValue": "2000003",
@@ -392,8 +307,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
         "SampleAfterValue": "2000003",
@@ -401,8 +314,6 @@
     },
     {
         "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "2000003",
@@ -410,8 +321,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the core is not in halt state.",
-        "Counter": "Fixed counter 2",
-        "CounterHTOff": "Fixed counter 2",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
         "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
         "SampleAfterValue": "2000003",
@@ -419,19 +328,14 @@
     },
     {
         "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
-        "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "AnyThread": "1",
         "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
         "SampleAfterValue": "2000003",
@@ -439,8 +343,6 @@
     },
     {
         "BriefDescription": "Core cycles when the thread is not in halt state.",
-        "Counter": "Fixed counter 1",
-        "CounterHTOff": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD",
         "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
         "SampleAfterValue": "2000003",
@@ -449,16 +351,12 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
-        "Counter": "Fixed counter 2",
-        "CounterHTOff": "Fixed counter 2",
         "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Thread cycles when thread is not in halt state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
         "SampleAfterValue": "2000003"
@@ -466,16 +364,12 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "2",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
@@ -484,8 +378,6 @@
     },
     {
         "BriefDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
@@ -494,8 +386,6 @@
     },
     {
         "BriefDescription": "Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_NO_DISPATCH",
@@ -504,8 +394,6 @@
     },
     {
         "BriefDescription": "Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "6",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
@@ -514,8 +402,6 @@
     },
     {
         "BriefDescription": "Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "5",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
@@ -524,8 +410,6 @@
     },
     {
         "BriefDescription": "Stall cycles because IQ is full.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.IQ_FULL",
         "SampleAfterValue": "2000003",
@@ -533,8 +417,6 @@
     },
     {
         "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.LCP",
         "SampleAfterValue": "2000003",
@@ -542,8 +424,6 @@
     },
     {
         "BriefDescription": "Instructions retired from execution.",
-        "Counter": "Fixed counter 0",
-        "CounterHTOff": "Fixed counter 0",
         "EventName": "INST_RETIRED.ANY",
         "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers.",
         "SampleAfterValue": "2000003",
@@ -551,27 +431,20 @@
     },
     {
         "BriefDescription": "Number of instructions retired. General Counter   - architectural event.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.ANY_P",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Instructions retired. (Precise Event - PEBS).",
-        "Counter": "1",
-        "CounterHTOff": "1",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.PREC_DIST",
         "PEBS": "2",
         "SampleAfterValue": "2000003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RAT_STALL_CYCLES",
         "SampleAfterValue": "2000003",
@@ -579,8 +452,6 @@
     },
     {
         "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES",
@@ -590,8 +461,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
@@ -600,8 +469,6 @@
     },
     {
         "BriefDescription": "Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x0D",
@@ -611,8 +478,6 @@
     },
     {
         "BriefDescription": "Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.ALL_BLOCK",
         "SampleAfterValue": "100003",
@@ -620,8 +485,6 @@
     },
     {
         "BriefDescription": "Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.DATA_UNKNOWN",
         "SampleAfterValue": "100003",
@@ -629,8 +492,6 @@
     },
     {
         "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.NO_SR",
         "SampleAfterValue": "100003",
@@ -638,8 +499,6 @@
     },
     {
         "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.STORE_FORWARD",
         "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load.  The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store.  See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual.  The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.",
@@ -648,8 +507,6 @@
     },
     {
         "BriefDescription": "False dependencies in MOB due to partial compare.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x07",
         "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
         "PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K.  This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline.  The enhanced address check typically has a performance penalty of 5 cycles.",
@@ -658,8 +515,6 @@
     },
     {
         "BriefDescription": "This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x07",
         "EventName": "LD_BLOCKS_PARTIAL.ALL_STA_BLOCK",
         "SampleAfterValue": "100003",
@@ -667,8 +522,6 @@
     },
     {
         "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4C",
         "EventName": "LOAD_HIT_PRE.HW_PF",
         "SampleAfterValue": "100003",
@@ -676,8 +529,6 @@
     },
     {
         "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4C",
         "EventName": "LOAD_HIT_PRE.SW_PF",
         "SampleAfterValue": "100003",
@@ -685,8 +536,6 @@
     },
     {
         "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_4_UOPS",
@@ -695,8 +544,6 @@
     },
     {
         "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_ACTIVE",
@@ -705,8 +552,6 @@
     },
     {
         "BriefDescription": "Number of Uops delivered by the LSD.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA8",
         "EventName": "LSD.UOPS",
         "SampleAfterValue": "2000003",
@@ -714,8 +559,6 @@
     },
     {
         "BriefDescription": "Number of machine clears (nukes) of any type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xc3",
@@ -725,8 +568,6 @@
     },
     {
         "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MASKMOV",
         "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",
@@ -735,8 +576,6 @@
     },
     {
         "BriefDescription": "Self-modifying code (SMC) detected.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.SMC",
         "PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear.  Machine clears can have a significant performance impact if they are happening frequently.",
@@ -745,8 +584,6 @@
     },
     {
         "BriefDescription": "Retired instructions experiencing ITLB misses.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.ITLB_MISS_RETIRED",
         "SampleAfterValue": "100003",
@@ -754,8 +591,6 @@
     },
     {
         "BriefDescription": "Increments the number of flags-merge uops in flight each cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x59",
         "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP",
         "SampleAfterValue": "2000003",
@@ -763,8 +598,6 @@
     },
     {
         "BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x59",
         "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES",
@@ -774,8 +607,6 @@
     },
     {
         "BriefDescription": "Multiply packed/scalar single precision uops allocated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x59",
         "EventName": "PARTIAL_RAT_STALLS.MUL_SINGLE_UOP",
         "SampleAfterValue": "2000003",
@@ -783,8 +614,6 @@
     },
     {
         "BriefDescription": "Cycles with at least one slow LEA uop being allocated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x59",
         "EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW",
         "PublicDescription": "This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.",
@@ -793,8 +622,6 @@
     },
     {
         "BriefDescription": "Resource-related stall cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ANY",
         "SampleAfterValue": "2000003",
@@ -802,8 +629,6 @@
     },
     {
         "BriefDescription": "Counts the cycles of stall due to lack of load buffers.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.LB",
         "SampleAfterValue": "2000003",
@@ -811,8 +636,6 @@
     },
     {
         "BriefDescription": "Resource stalls due to load or store buffers all being in use.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.LB_SB",
         "SampleAfterValue": "2000003",
@@ -820,8 +643,6 @@
     },
     {
         "BriefDescription": "Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.MEM_RS",
         "SampleAfterValue": "2000003",
@@ -829,8 +650,6 @@
     },
     {
         "BriefDescription": "Resource stalls due to Rob being full, FCSW, MXCSR and OTHER.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.OOO_RSRC",
         "SampleAfterValue": "2000003",
@@ -838,8 +657,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to re-order buffer full.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ROB",
         "SampleAfterValue": "2000003",
@@ -847,8 +664,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no eligible RS entry available.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.RS",
         "SampleAfterValue": "2000003",
@@ -856,8 +671,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.SB",
         "SampleAfterValue": "2000003",
@@ -865,8 +678,6 @@
     },
     {
         "BriefDescription": "Cycles with either free list is empty.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5B",
         "EventName": "RESOURCE_STALLS2.ALL_FL_EMPTY",
         "SampleAfterValue": "2000003",
@@ -874,8 +685,6 @@
     },
     {
         "BriefDescription": "Resource stalls2 control structures full for physical registers.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5B",
         "EventName": "RESOURCE_STALLS2.ALL_PRF_CONTROL",
         "SampleAfterValue": "2000003",
@@ -883,8 +692,6 @@
     },
     {
         "BriefDescription": "Cycles when Allocator is stalled if BOB is full and new branch needs it.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5B",
         "EventName": "RESOURCE_STALLS2.BOB_FULL",
         "SampleAfterValue": "2000003",
@@ -892,8 +699,6 @@
     },
     {
         "BriefDescription": "Resource stalls out of order resources full.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5B",
         "EventName": "RESOURCE_STALLS2.OOO_RSRC",
         "SampleAfterValue": "2000003",
@@ -901,8 +706,6 @@
     },
     {
         "BriefDescription": "Count cases of saving new LBR.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCC",
         "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
         "SampleAfterValue": "2000003",
@@ -910,8 +713,6 @@
     },
     {
         "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5E",
         "EventName": "RS_EVENTS.EMPTY_CYCLES",
         "SampleAfterValue": "2000003",
@@ -919,8 +720,6 @@
     },
     {
         "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5E",
@@ -931,8 +730,6 @@
     },
     {
         "BriefDescription": "Uops dispatched from any thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_DISPATCHED.CORE",
         "SampleAfterValue": "2000003",
@@ -940,8 +737,6 @@
     },
     {
         "BriefDescription": "Uops dispatched per thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_DISPATCHED.THREAD",
         "SampleAfterValue": "2000003",
@@ -949,8 +744,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are dispatched to port 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_0",
         "SampleAfterValue": "2000003",
@@ -959,8 +752,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE",
         "SampleAfterValue": "2000003",
@@ -968,8 +759,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are dispatched to port 1.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_1",
         "SampleAfterValue": "2000003",
@@ -978,8 +767,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 1.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE",
         "SampleAfterValue": "2000003",
@@ -987,8 +774,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_2",
         "SampleAfterValue": "2000003",
@@ -997,8 +782,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE",
         "SampleAfterValue": "2000003",
@@ -1006,8 +789,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_3",
         "SampleAfterValue": "2000003",
@@ -1016,8 +797,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE",
         "SampleAfterValue": "2000003",
@@ -1025,8 +804,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are dispatched to port 4.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_4",
         "SampleAfterValue": "2000003",
@@ -1035,8 +812,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 4.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE",
         "SampleAfterValue": "2000003",
@@ -1044,8 +819,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are dispatched to port 5.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_5",
         "SampleAfterValue": "2000003",
@@ -1054,8 +827,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 5.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE",
         "SampleAfterValue": "2000003",
@@ -1063,8 +834,6 @@
     },
     {
         "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@@ -1073,8 +842,6 @@
     },
     {
         "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@@ -1083,8 +850,6 @@
     },
     {
         "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@@ -1093,8 +858,6 @@
     },
     {
         "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@@ -1103,8 +866,6 @@
     },
     {
         "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
         "Invert": "1",
@@ -1113,8 +874,6 @@
     },
     {
         "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.ANY",
         "PublicDescription": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.",
@@ -1124,8 +883,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -1135,8 +892,6 @@
     },
     {
         "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -1146,8 +901,6 @@
     },
     {
         "BriefDescription": "Actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ALL",
         "PEBS": "1",
@@ -1157,8 +910,6 @@
     },
     {
         "BriefDescription": "Cycles without actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",
@@ -1168,8 +919,6 @@
     },
     {
         "BriefDescription": "Retirement slots used.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
         "PEBS": "1",
@@ -1179,8 +928,6 @@
     },
     {
         "BriefDescription": "Cycles without actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -1190,8 +937,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 10 actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "10",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json
index 351f8b040ed1f..b9e68f9f33ea6 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json
@@ -1,23 +1,26 @@
 [
     {
         "BriefDescription": "Uncore Clocks",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_C_CLOCKTICKS",
         "PerPkg": "1",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "Counter 0 Occupancy",
-        "Counter": "1,2,3",
         "EventCode": "0x1f",
         "EventName": "UNC_C_COUNTER0_OCCUPANCY",
         "PerPkg": "1",
         "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0.   The filtering available is found in the control register - threshold, invert and edge detect.   E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
         "Unit": "CBO"
     },
+    {
+        "EventCode": "0x21",
+        "EventName": "UNC_C_ISMQ_DRD_MISS_OCC",
+        "PerPkg": "1",
+        "Unit": "CBO"
+    },
     {
         "BriefDescription": "Cache Lookups; Data Read Request",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
         "PerPkg": "1",
@@ -27,7 +30,6 @@
     },
     {
         "BriefDescription": "Cache Lookups; RTID",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_C_LLC_LOOKUP.NID",
         "PerPkg": "1",
@@ -37,7 +39,6 @@
     },
     {
         "BriefDescription": "Cache Lookups; External Snoop Request",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
         "PerPkg": "1",
@@ -47,7 +48,6 @@
     },
     {
         "BriefDescription": "Cache Lookups; Write Requests",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_C_LLC_LOOKUP.WRITE",
         "PerPkg": "1",
@@ -57,7 +57,6 @@
     },
     {
         "BriefDescription": "Lines Victimized; Lines in E state",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
         "PerPkg": "1",
@@ -67,7 +66,6 @@
     },
     {
         "BriefDescription": "Lines Victimized",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_C_LLC_VICTIMS.MISS",
         "PerPkg": "1",
@@ -77,7 +75,6 @@
     },
     {
         "BriefDescription": "Lines Victimized; Lines in M state",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
         "PerPkg": "1",
@@ -87,7 +84,6 @@
     },
     {
         "BriefDescription": "Lines Victimized; Victimized Lines that Match NID",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_C_LLC_VICTIMS.NID",
         "PerPkg": "1",
@@ -97,7 +93,6 @@
     },
     {
         "BriefDescription": "Lines Victimized; Lines in S State",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_C_LLC_VICTIMS.S_STATE",
         "PerPkg": "1",
@@ -107,7 +102,6 @@
     },
     {
         "BriefDescription": "Cbo Misc; RFO HitS",
-        "Counter": "0,1",
         "EventCode": "0x39",
         "EventName": "UNC_C_MISC.RFO_HIT_S",
         "PerPkg": "1",
@@ -117,7 +111,6 @@
     },
     {
         "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
-        "Counter": "0,1",
         "EventCode": "0x39",
         "EventName": "UNC_C_MISC.RSPI_WAS_FSE",
         "PerPkg": "1",
@@ -127,7 +120,6 @@
     },
     {
         "BriefDescription": "Cbo Misc",
-        "Counter": "0,1",
         "EventCode": "0x39",
         "EventName": "UNC_C_MISC.STARTED",
         "PerPkg": "1",
@@ -137,7 +129,6 @@
     },
     {
         "BriefDescription": "Cbo Misc; Write Combining Aliasing",
-        "Counter": "0,1",
         "EventCode": "0x39",
         "EventName": "UNC_C_MISC.WC_ALIASING",
         "PerPkg": "1",
@@ -147,7 +138,6 @@
     },
     {
         "BriefDescription": "AD Ring In Use; Down and Even",
-        "Counter": "2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_C_RING_AD_USED.DOWN_EVEN",
         "PerPkg": "1",
@@ -157,7 +147,6 @@
     },
     {
         "BriefDescription": "AD Ring In Use; Down and Odd",
-        "Counter": "2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_C_RING_AD_USED.DOWN_ODD",
         "PerPkg": "1",
@@ -167,7 +156,6 @@
     },
     {
         "BriefDescription": "AD Ring In Use; Up and Even",
-        "Counter": "2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_C_RING_AD_USED.UP_EVEN",
         "PerPkg": "1",
@@ -177,7 +165,6 @@
     },
     {
         "BriefDescription": "AD Ring In Use; Up and Odd",
-        "Counter": "2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_C_RING_AD_USED.UP_ODD",
         "PerPkg": "1",
@@ -187,7 +174,6 @@
     },
     {
         "BriefDescription": "AK Ring In Use; Down and Even",
-        "Counter": "2,3",
         "EventCode": "0x1c",
         "EventName": "UNC_C_RING_AK_USED.DOWN_EVEN",
         "PerPkg": "1",
@@ -197,7 +183,6 @@
     },
     {
         "BriefDescription": "AK Ring In Use; Down and Odd",
-        "Counter": "2,3",
         "EventCode": "0x1c",
         "EventName": "UNC_C_RING_AK_USED.DOWN_ODD",
         "PerPkg": "1",
@@ -207,7 +192,6 @@
     },
     {
         "BriefDescription": "AK Ring In Use; Up and Even",
-        "Counter": "2,3",
         "EventCode": "0x1c",
         "EventName": "UNC_C_RING_AK_USED.UP_EVEN",
         "PerPkg": "1",
@@ -217,7 +201,6 @@
     },
     {
         "BriefDescription": "AK Ring In Use; Up and Odd",
-        "Counter": "2,3",
         "EventCode": "0x1c",
         "EventName": "UNC_C_RING_AK_USED.UP_ODD",
         "PerPkg": "1",
@@ -227,7 +210,6 @@
     },
     {
         "BriefDescription": "BL Ring in Use; Down and Even",
-        "Counter": "2,3",
         "EventCode": "0x1d",
         "EventName": "UNC_C_RING_BL_USED.DOWN_EVEN",
         "PerPkg": "1",
@@ -237,7 +219,6 @@
     },
     {
         "BriefDescription": "BL Ring in Use; Down and Odd",
-        "Counter": "2,3",
         "EventCode": "0x1d",
         "EventName": "UNC_C_RING_BL_USED.DOWN_ODD",
         "PerPkg": "1",
@@ -247,7 +228,6 @@
     },
     {
         "BriefDescription": "BL Ring in Use; Up and Even",
-        "Counter": "2,3",
         "EventCode": "0x1d",
         "EventName": "UNC_C_RING_BL_USED.UP_EVEN",
         "PerPkg": "1",
@@ -257,7 +237,6 @@
     },
     {
         "BriefDescription": "BL Ring in Use; Up and Odd",
-        "Counter": "2,3",
         "EventCode": "0x1d",
         "EventName": "UNC_C_RING_BL_USED.UP_ODD",
         "PerPkg": "1",
@@ -267,7 +246,6 @@
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.; Acknowledgements to core",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "UNC_C_RING_BOUNCES.AK_CORE",
         "PerPkg": "1",
@@ -276,7 +254,6 @@
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.; Data Responses to core",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "UNC_C_RING_BOUNCES.BL_CORE",
         "PerPkg": "1",
@@ -285,7 +262,6 @@
     },
     {
         "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "UNC_C_RING_BOUNCES.IV_CORE",
         "PerPkg": "1",
@@ -294,7 +270,6 @@
     },
     {
         "BriefDescription": "BL Ring in Use; Any",
-        "Counter": "2,3",
         "EventCode": "0x1e",
         "EventName": "UNC_C_RING_IV_USED.ANY",
         "PerPkg": "1",
@@ -302,9 +277,42 @@
         "UMask": "0xf",
         "Unit": "CBO"
     },
+    {
+        "EventCode": "0x6",
+        "EventName": "UNC_C_RING_SINK_STARVED.AD_CACHE",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CBO"
+    },
+    {
+        "EventCode": "0x6",
+        "EventName": "UNC_C_RING_SINK_STARVED.AK_CORE",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CBO"
+    },
+    {
+        "EventCode": "0x6",
+        "EventName": "UNC_C_RING_SINK_STARVED.BL_CORE",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CBO"
+    },
+    {
+        "EventCode": "0x6",
+        "EventName": "UNC_C_RING_SINK_STARVED.IV_CORE",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CBO"
+    },
+    {
+        "EventCode": "0x7",
+        "EventName": "UNC_C_RING_SRC_THRTL",
+        "PerPkg": "1",
+        "Unit": "CBO"
+    },
     {
         "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "UNC_C_RxR_EXT_STARVED.IPQ",
         "PerPkg": "1",
@@ -314,7 +322,6 @@
     },
     {
         "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "UNC_C_RxR_EXT_STARVED.IRQ",
         "PerPkg": "1",
@@ -324,7 +331,6 @@
     },
     {
         "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ",
         "PerPkg": "1",
@@ -334,7 +340,6 @@
     },
     {
         "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
         "PerPkg": "1",
@@ -344,7 +349,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; IPQ",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_C_RxR_INSERTS.IPQ",
         "PerPkg": "1",
@@ -354,7 +358,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; IRQ",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_C_RxR_INSERTS.IRQ",
         "PerPkg": "1",
@@ -364,7 +367,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; IRQ Rejected",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_C_RxR_INSERTS.IRQ_REJECTED",
         "PerPkg": "1",
@@ -374,7 +376,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; VFIFO",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_C_RxR_INSERTS.VFIFO",
         "PerPkg": "1",
@@ -384,7 +385,6 @@
     },
     {
         "BriefDescription": "Ingress Internal Starvation Cycles; IPQ",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_C_RxR_INT_STARVED.IPQ",
         "PerPkg": "1",
@@ -394,7 +394,6 @@
     },
     {
         "BriefDescription": "Ingress Internal Starvation Cycles; IRQ",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_C_RxR_INT_STARVED.IRQ",
         "PerPkg": "1",
@@ -404,7 +403,6 @@
     },
     {
         "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_C_RxR_INT_STARVED.ISMQ",
         "PerPkg": "1",
@@ -414,7 +412,6 @@
     },
     {
         "BriefDescription": "Probe Queue Retries; Address Conflict",
-        "Counter": "0,1",
         "EventCode": "0x31",
         "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
         "PerPkg": "1",
@@ -424,7 +421,6 @@
     },
     {
         "BriefDescription": "Probe Queue Retries; Any Reject",
-        "Counter": "0,1",
         "EventCode": "0x31",
         "EventName": "UNC_C_RxR_IPQ_RETRY.ANY",
         "PerPkg": "1",
@@ -434,7 +430,6 @@
     },
     {
         "BriefDescription": "Probe Queue Retries; No Egress Credits",
-        "Counter": "0,1",
         "EventCode": "0x31",
         "EventName": "UNC_C_RxR_IPQ_RETRY.FULL",
         "PerPkg": "1",
@@ -444,7 +439,6 @@
     },
     {
         "BriefDescription": "Probe Queue Retries; No QPI Credits",
-        "Counter": "0,1",
         "EventCode": "0x31",
         "EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS",
         "PerPkg": "1",
@@ -454,7 +448,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; Address Conflict",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
         "PerPkg": "1",
@@ -463,7 +456,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; Any Reject",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.ANY",
         "PerPkg": "1",
@@ -472,7 +464,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; No Egress Credits",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.FULL",
         "PerPkg": "1",
@@ -481,7 +472,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS",
         "PerPkg": "1",
@@ -490,7 +480,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects; No RTIDs",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_C_RxR_IRQ_RETRY.RTID",
         "PerPkg": "1",
@@ -499,7 +488,6 @@
     },
     {
         "BriefDescription": "ISMQ Retries; Any Reject",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_C_RxR_ISMQ_RETRY.ANY",
         "PerPkg": "1",
@@ -509,7 +497,6 @@
     },
     {
         "BriefDescription": "ISMQ Retries; No Egress Credits",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_C_RxR_ISMQ_RETRY.FULL",
         "PerPkg": "1",
@@ -519,7 +506,6 @@
     },
     {
         "BriefDescription": "ISMQ Retries; No IIO Credits",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
         "PerPkg": "1",
@@ -529,7 +515,6 @@
     },
     {
         "BriefDescription": "ISMQ Retries; No QPI Credits",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
         "PerPkg": "1",
@@ -539,7 +524,6 @@
     },
     {
         "BriefDescription": "ISMQ Retries; No RTIDs",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID",
         "PerPkg": "1",
@@ -585,7 +569,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; Evictions",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.EVICTION",
         "PerPkg": "1",
@@ -595,7 +578,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; Miss All",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.MISS_ALL",
         "PerPkg": "1",
@@ -605,7 +587,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; Miss Opcode Match",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE",
         "PerPkg": "1",
@@ -615,7 +596,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; NID Matched",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.NID_ALL",
         "PerPkg": "1",
@@ -625,7 +605,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; NID Matched Evictions",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION",
         "PerPkg": "1",
@@ -635,7 +614,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; NID Matched Miss All",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL",
         "PerPkg": "1",
@@ -645,7 +623,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
         "PerPkg": "1",
@@ -655,7 +632,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; NID and Opcode Matched",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE",
         "PerPkg": "1",
@@ -665,7 +641,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; NID Matched Writebacks",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.NID_WB",
         "PerPkg": "1",
@@ -675,7 +650,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; Opcode Match",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.OPCODE",
         "PerPkg": "1",
@@ -685,7 +659,6 @@
     },
     {
         "BriefDescription": "TOR Inserts; Writebacks",
-        "Counter": "0,1",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.WB",
         "PerPkg": "1",
@@ -783,9 +756,14 @@
         "UMask": "0x1",
         "Unit": "CBO"
     },
+    {
+        "EventCode": "0x4",
+        "EventName": "UNC_C_TxR_ADS_USED",
+        "PerPkg": "1",
+        "Unit": "CBO"
+    },
     {
         "BriefDescription": "Egress Allocations; AD - Cachebo",
-        "Counter": "0,1",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.AD_CACHE",
         "PerPkg": "1",
@@ -795,7 +773,6 @@
     },
     {
         "BriefDescription": "Egress Allocations; AD - Corebo",
-        "Counter": "0,1",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.AD_CORE",
         "PerPkg": "1",
@@ -805,7 +782,6 @@
     },
     {
         "BriefDescription": "Egress Allocations; AK - Cachebo",
-        "Counter": "0,1",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.AK_CACHE",
         "PerPkg": "1",
@@ -815,7 +791,6 @@
     },
     {
         "BriefDescription": "Egress Allocations; AK - Corebo",
-        "Counter": "0,1",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.AK_CORE",
         "PerPkg": "1",
@@ -825,7 +800,6 @@
     },
     {
         "BriefDescription": "Egress Allocations; BL - Cacheno",
-        "Counter": "0,1",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.BL_CACHE",
         "PerPkg": "1",
@@ -835,7 +809,6 @@
     },
     {
         "BriefDescription": "Egress Allocations; BL - Corebo",
-        "Counter": "0,1",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.BL_CORE",
         "PerPkg": "1",
@@ -845,7 +818,6 @@
     },
     {
         "BriefDescription": "Egress Allocations; IV - Cachebo",
-        "Counter": "0,1",
         "EventCode": "0x2",
         "EventName": "UNC_C_TxR_INSERTS.IV_CACHE",
         "PerPkg": "1",
@@ -855,7 +827,6 @@
     },
     {
         "BriefDescription": "Injection Starvation; Onto AK Ring",
-        "Counter": "0,1",
         "EventCode": "0x3",
         "EventName": "UNC_C_TxR_STARVED.AK",
         "PerPkg": "1",
@@ -865,7 +836,6 @@
     },
     {
         "BriefDescription": "Injection Starvation; Onto BL Ring",
-        "Counter": "0,1",
         "EventCode": "0x3",
         "EventName": "UNC_C_TxR_STARVED.BL",
         "PerPkg": "1",
@@ -875,7 +845,6 @@
     },
     {
         "BriefDescription": "HA to iMC Bypass; Not Taken",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN",
         "PerPkg": "1",
@@ -885,7 +854,6 @@
     },
     {
         "BriefDescription": "HA to iMC Bypass; Taken",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_H_BYPASS_IMC.TAKEN",
         "PerPkg": "1",
@@ -895,7 +863,6 @@
     },
     {
         "BriefDescription": "uclks",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_H_CLOCKTICKS",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of uclks in the HA.  This will be slightly different than the count in the Ubox because of enable/freeze delays.  The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.",
@@ -903,7 +870,6 @@
     },
     {
         "BriefDescription": "Conflict Checks; Conflict Detected",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb",
         "EventName": "UNC_H_CONFLICT_CYCLES.CONFLICT",
         "PerPkg": "1",
@@ -912,7 +878,6 @@
     },
     {
         "BriefDescription": "Conflict Checks; No Conflict",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb",
         "EventName": "UNC_H_CONFLICT_CYCLES.NO_CONFLICT",
         "PerPkg": "1",
@@ -921,7 +886,6 @@
     },
     {
         "BriefDescription": "Direct2Core Messages Sent",
-        "Counter": "0,1,2,3",
         "EventCode": "0x11",
         "EventName": "UNC_H_DIRECT2CORE_COUNT",
         "PerPkg": "1",
@@ -930,7 +894,6 @@
     },
     {
         "BriefDescription": "Cycles when Direct2Core was Disabled",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED",
         "PerPkg": "1",
@@ -939,7 +902,6 @@
     },
     {
         "BriefDescription": "Number of Reads that had Direct2Core Overridden",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE",
         "PerPkg": "1",
@@ -948,7 +910,6 @@
     },
     {
         "BriefDescription": "Directory Lookups; Snoop Not Needed",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc",
         "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP",
         "PerPkg": "1",
@@ -958,7 +919,6 @@
     },
     {
         "BriefDescription": "Directory Lookups; Snoop Needed",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc",
         "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP",
         "PerPkg": "1",
@@ -968,7 +928,6 @@
     },
     {
         "BriefDescription": "Directory Updates; Any Directory Update",
-        "Counter": "0,1,2,3",
         "EventCode": "0xd",
         "EventName": "UNC_H_DIRECTORY_UPDATE.ANY",
         "PerPkg": "1",
@@ -978,7 +937,6 @@
     },
     {
         "BriefDescription": "Directory Updates; Directory Clear",
-        "Counter": "0,1,2,3",
         "EventCode": "0xd",
         "EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR",
         "PerPkg": "1",
@@ -988,7 +946,6 @@
     },
     {
         "BriefDescription": "Directory Updates; Directory Set",
-        "Counter": "0,1,2,3",
         "EventCode": "0xd",
         "EventName": "UNC_H_DIRECTORY_UPDATE.SET",
         "PerPkg": "1",
@@ -998,7 +955,6 @@
     },
     {
         "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
         "PerPkg": "1",
@@ -1008,7 +964,6 @@
     },
     {
         "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
         "PerPkg": "1",
@@ -1018,7 +973,6 @@
     },
     {
         "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
         "PerPkg": "1",
@@ -1028,7 +982,6 @@
     },
     {
         "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
         "PerPkg": "1",
@@ -1038,7 +991,6 @@
     },
     {
         "BriefDescription": "Retry Events",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1e",
         "EventName": "UNC_H_IMC_RETRY",
         "PerPkg": "1",
@@ -1046,7 +998,6 @@
     },
     {
         "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1a",
         "EventName": "UNC_H_IMC_WRITES.ALL",
         "PerPkg": "1",
@@ -1056,7 +1007,6 @@
     },
     {
         "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1a",
         "EventName": "UNC_H_IMC_WRITES.FULL",
         "PerPkg": "1",
@@ -1066,7 +1016,6 @@
     },
     {
         "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full Line",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1a",
         "EventName": "UNC_H_IMC_WRITES.FULL_ISOCH",
         "PerPkg": "1",
@@ -1076,7 +1025,6 @@
     },
     {
         "BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1a",
         "EventName": "UNC_H_IMC_WRITES.PARTIAL",
         "PerPkg": "1",
@@ -1086,7 +1034,6 @@
     },
     {
         "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1a",
         "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH",
         "PerPkg": "1",
@@ -1096,7 +1043,6 @@
     },
     {
         "BriefDescription": "Read and Write Requests; Reads",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_H_REQUESTS.READS",
         "PerPkg": "1",
@@ -1106,7 +1052,6 @@
     },
     {
         "BriefDescription": "Read and Write Requests; Writes",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_H_REQUESTS.WRITES",
         "PerPkg": "1",
@@ -1116,7 +1061,6 @@
     },
     {
         "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3e",
         "EventName": "UNC_H_RING_AD_USED.CCW_EVEN",
         "PerPkg": "1",
@@ -1126,7 +1070,6 @@
     },
     {
         "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3e",
         "EventName": "UNC_H_RING_AD_USED.CCW_ODD",
         "PerPkg": "1",
@@ -1136,7 +1079,6 @@
     },
     {
         "BriefDescription": "HA AD Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3e",
         "EventName": "UNC_H_RING_AD_USED.CW_EVEN",
         "PerPkg": "1",
@@ -1146,7 +1088,6 @@
     },
     {
         "BriefDescription": "HA AD Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3e",
         "EventName": "UNC_H_RING_AD_USED.CW_ODD",
         "PerPkg": "1",
@@ -1156,7 +1097,6 @@
     },
     {
         "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3f",
         "EventName": "UNC_H_RING_AK_USED.CCW_EVEN",
         "PerPkg": "1",
@@ -1166,7 +1106,6 @@
     },
     {
         "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3f",
         "EventName": "UNC_H_RING_AK_USED.CCW_ODD",
         "PerPkg": "1",
@@ -1176,7 +1115,6 @@
     },
     {
         "BriefDescription": "HA AK Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3f",
         "EventName": "UNC_H_RING_AK_USED.CW_EVEN",
         "PerPkg": "1",
@@ -1186,7 +1124,6 @@
     },
     {
         "BriefDescription": "HA AK Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3f",
         "EventName": "UNC_H_RING_AK_USED.CW_ODD",
         "PerPkg": "1",
@@ -1196,7 +1133,6 @@
     },
     {
         "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.CCW_EVEN",
         "PerPkg": "1",
@@ -1206,7 +1142,6 @@
     },
     {
         "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.CCW_ODD",
         "PerPkg": "1",
@@ -1216,7 +1151,6 @@
     },
     {
         "BriefDescription": "HA BL Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.CW_EVEN",
         "PerPkg": "1",
@@ -1226,7 +1160,6 @@
     },
     {
         "BriefDescription": "HA BL Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "UNC_H_RING_BL_USED.CW_ODD",
         "PerPkg": "1",
@@ -1236,7 +1169,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
         "PerPkg": "1",
@@ -1246,7 +1178,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
         "PerPkg": "1",
@@ -1256,7 +1187,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
         "PerPkg": "1",
@@ -1266,7 +1196,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
         "PerPkg": "1",
@@ -1276,7 +1205,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
         "PerPkg": "1",
@@ -1286,7 +1214,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
         "PerPkg": "1",
@@ -1296,7 +1223,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
         "PerPkg": "1",
@@ -1306,7 +1232,6 @@
     },
     {
         "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
         "PerPkg": "1",
@@ -1316,7 +1241,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION0",
         "PerPkg": "1",
@@ -1326,7 +1250,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION1",
         "PerPkg": "1",
@@ -1336,7 +1259,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION2",
         "PerPkg": "1",
@@ -1346,7 +1268,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION3",
         "PerPkg": "1",
@@ -1356,7 +1277,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION4",
         "PerPkg": "1",
@@ -1366,7 +1286,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION5",
         "PerPkg": "1",
@@ -1376,7 +1295,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION6",
         "PerPkg": "1",
@@ -1386,7 +1304,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_H_TAD_REQUESTS_G0.REGION7",
         "PerPkg": "1",
@@ -1396,7 +1313,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1c",
         "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10",
         "PerPkg": "1",
@@ -1406,7 +1322,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1c",
         "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11",
         "PerPkg": "1",
@@ -1416,7 +1331,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1c",
         "EventName": "UNC_H_TAD_REQUESTS_G1.REGION8",
         "PerPkg": "1",
@@ -1426,7 +1340,6 @@
     },
     {
         "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1c",
         "EventName": "UNC_H_TAD_REQUESTS_G1.REGION9",
         "PerPkg": "1",
@@ -1436,7 +1349,6 @@
     },
     {
         "BriefDescription": "Tracker Allocations; All Requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_H_TRACKER_INSERTS.ALL",
         "PerPkg": "1",
@@ -1446,7 +1358,6 @@
     },
     {
         "BriefDescription": "Outbound NDR Ring Transactions; Non-data Responses",
-        "Counter": "0,1,2,3",
         "EventCode": "0xf",
         "EventName": "UNC_H_TxR_AD.NDR",
         "PerPkg": "1",
@@ -1456,7 +1367,6 @@
     },
     {
         "BriefDescription": "Outbound NDR Ring Transactions; Snoops",
-        "Counter": "0,1,2,3",
         "EventCode": "0xf",
         "EventName": "UNC_H_TxR_AD.SNP",
         "PerPkg": "1",
@@ -1466,217 +1376,174 @@
     },
     {
         "BriefDescription": "AD Egress Full; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2a",
         "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL",
         "PerPkg": "1",
-        "PublicDescription": "AD Egress Full",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AD Egress Full; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2a",
         "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
         "PerPkg": "1",
-        "PublicDescription": "AD Egress Full",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AD Egress Full; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2a",
         "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
         "PerPkg": "1",
-        "PublicDescription": "AD Egress Full",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AD Egress Not Empty; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL",
         "PerPkg": "1",
-        "PublicDescription": "AD Egress Not Empty",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AD Egress Not Empty; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0",
         "PerPkg": "1",
-        "PublicDescription": "AD Egress Not Empty",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AD Egress Not Empty; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x29",
         "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1",
         "PerPkg": "1",
-        "PublicDescription": "AD Egress Not Empty",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AD Egress Allocations; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "UNC_H_TxR_AD_INSERTS.ALL",
         "PerPkg": "1",
-        "PublicDescription": "AD Egress Allocations",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AD Egress Allocations; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "UNC_H_TxR_AD_INSERTS.SCHED0",
         "PerPkg": "1",
-        "PublicDescription": "AD Egress Allocations",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AD Egress Allocations; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "UNC_H_TxR_AD_INSERTS.SCHED1",
         "PerPkg": "1",
-        "PublicDescription": "AD Egress Allocations",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AD Egress Occupancy; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "UNC_H_TxR_AD_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "PublicDescription": "AD Egress Occupancy",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AD Egress Occupancy; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "UNC_H_TxR_AD_OCCUPANCY.SCHED0",
         "PerPkg": "1",
-        "PublicDescription": "AD Egress Occupancy",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AD Egress Occupancy; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "UNC_H_TxR_AD_OCCUPANCY.SCHED1",
         "PerPkg": "1",
-        "PublicDescription": "AD Egress Occupancy",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AK Egress Full; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL",
         "PerPkg": "1",
-        "PublicDescription": "AK Egress Full",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AK Egress Full; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
         "PerPkg": "1",
-        "PublicDescription": "AK Egress Full",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AK Egress Full; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
         "PerPkg": "1",
-        "PublicDescription": "AK Egress Full",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AK Egress Not Empty; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL",
         "PerPkg": "1",
-        "PublicDescription": "AK Egress Not Empty",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AK Egress Not Empty; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0",
         "PerPkg": "1",
-        "PublicDescription": "AK Egress Not Empty",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AK Egress Not Empty; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1",
         "PerPkg": "1",
-        "PublicDescription": "AK Egress Not Empty",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AK Egress Allocations; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2f",
         "EventName": "UNC_H_TxR_AK_INSERTS.ALL",
         "PerPkg": "1",
-        "PublicDescription": "AK Egress Allocations",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AK Egress Allocations; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2f",
         "EventName": "UNC_H_TxR_AK_INSERTS.SCHED0",
         "PerPkg": "1",
-        "PublicDescription": "AK Egress Allocations",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AK Egress Allocations; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2f",
         "EventName": "UNC_H_TxR_AK_INSERTS.SCHED1",
         "PerPkg": "1",
-        "PublicDescription": "AK Egress Allocations",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Outbound NDR Ring Transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xe",
         "EventName": "UNC_H_TxR_AK_NDR",
         "PerPkg": "1",
@@ -1685,37 +1552,30 @@
     },
     {
         "BriefDescription": "AK Egress Occupancy; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x30",
         "EventName": "UNC_H_TxR_AK_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "PublicDescription": "AK Egress Occupancy",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AK Egress Occupancy; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x30",
         "EventName": "UNC_H_TxR_AK_OCCUPANCY.SCHED0",
         "PerPkg": "1",
-        "PublicDescription": "AK Egress Occupancy",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "AK Egress Occupancy; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x30",
         "EventName": "UNC_H_TxR_AK_OCCUPANCY.SCHED1",
         "PerPkg": "1",
-        "PublicDescription": "AK Egress Occupancy",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_H_TxR_BL.DRS_CACHE",
         "PerPkg": "1",
@@ -1725,7 +1585,6 @@
     },
     {
         "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_H_TxR_BL.DRS_CORE",
         "PerPkg": "1",
@@ -1735,7 +1594,6 @@
     },
     {
         "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_H_TxR_BL.DRS_QPI",
         "PerPkg": "1",
@@ -1745,127 +1603,102 @@
     },
     {
         "BriefDescription": "BL Egress Full; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x36",
         "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL",
         "PerPkg": "1",
-        "PublicDescription": "BL Egress Full",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "BL Egress Full; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x36",
         "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
         "PerPkg": "1",
-        "PublicDescription": "BL Egress Full",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "BL Egress Full; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x36",
         "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
         "PerPkg": "1",
-        "PublicDescription": "BL Egress Full",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "BL Egress Not Empty; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL",
         "PerPkg": "1",
-        "PublicDescription": "BL Egress Not Empty",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "BL Egress Not Empty; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0",
         "PerPkg": "1",
-        "PublicDescription": "BL Egress Not Empty",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "BL Egress Not Empty; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1",
         "PerPkg": "1",
-        "PublicDescription": "BL Egress Not Empty",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "BL Egress Allocations; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_H_TxR_BL_INSERTS.ALL",
         "PerPkg": "1",
-        "PublicDescription": "BL Egress Allocations",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "BL Egress Allocations; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_H_TxR_BL_INSERTS.SCHED0",
         "PerPkg": "1",
-        "PublicDescription": "BL Egress Allocations",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "BL Egress Allocations; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x33",
         "EventName": "UNC_H_TxR_BL_INSERTS.SCHED1",
         "PerPkg": "1",
-        "PublicDescription": "BL Egress Allocations",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "BL Egress Occupancy; All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "UNC_H_TxR_BL_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "PublicDescription": "BL Egress Occupancy",
         "UMask": "0x3",
         "Unit": "HA"
     },
     {
         "BriefDescription": "BL Egress Occupancy; Scheduler 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "UNC_H_TxR_BL_OCCUPANCY.SCHED0",
         "PerPkg": "1",
-        "PublicDescription": "BL Egress Occupancy",
         "UMask": "0x1",
         "Unit": "HA"
     },
     {
         "BriefDescription": "BL Egress Occupancy; Scheduler 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "UNC_H_TxR_BL_OCCUPANCY.SCHED1",
         "PerPkg": "1",
-        "PublicDescription": "BL Egress Occupancy",
         "UMask": "0x2",
         "Unit": "HA"
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
         "PerPkg": "1",
@@ -1875,7 +1708,6 @@
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
         "PerPkg": "1",
@@ -1885,7 +1717,6 @@
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
         "PerPkg": "1",
@@ -1895,7 +1726,6 @@
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
         "PerPkg": "1",
@@ -1905,7 +1735,6 @@
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
         "PerPkg": "1",
@@ -1915,7 +1744,6 @@
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
         "PerPkg": "1",
@@ -1925,7 +1753,6 @@
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
         "PerPkg": "1",
@@ -1935,7 +1762,6 @@
     },
     {
         "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
         "PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json
index 750870fd1cb1f..1c2cf94889a1a 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Number of qfclks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_Q_CLOCKTICKS",
         "PerPkg": "1",
@@ -10,17 +9,14 @@
     },
     {
         "BriefDescription": "Count of CTO Events",
-        "Counter": "0,1,2,3",
         "EventCode": "0x38",
         "EventName": "UNC_Q_CTO_COUNT",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots.  If both slots trigger in a given cycle, the event will increment by 2.  You can use edge detect to count the number of cases when both events triggered.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS",
         "PerPkg": "1",
@@ -30,7 +26,6 @@
     },
     {
         "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT",
         "PerPkg": "1",
@@ -40,7 +35,6 @@
     },
     {
         "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Not Set",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT",
         "PerPkg": "1",
@@ -50,7 +44,6 @@
     },
     {
         "BriefDescription": "Direct 2 Core Spawning; Spawn Success",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_Q_DIRECT2CORE.SUCCESS",
         "PerPkg": "1",
@@ -60,7 +53,6 @@
     },
     {
         "BriefDescription": "Cycles in L1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_Q_L1_POWER_CYCLES",
         "PerPkg": "1",
@@ -69,7 +61,6 @@
     },
     {
         "BriefDescription": "Cycles in L0p",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_Q_RxL0P_POWER_CYCLES",
         "PerPkg": "1",
@@ -78,7 +69,6 @@
     },
     {
         "BriefDescription": "Cycles in L0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xf",
         "EventName": "UNC_Q_RxL0_POWER_CYCLES",
         "PerPkg": "1",
@@ -87,7 +77,6 @@
     },
     {
         "BriefDescription": "Rx Flit Buffer Bypassed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_Q_RxL_BYPASSED",
         "PerPkg": "1",
@@ -96,7 +85,6 @@
     },
     {
         "BriefDescription": "CRC Errors Detected; LinkInit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT",
         "PerPkg": "1",
@@ -106,7 +94,6 @@
     },
     {
         "BriefDescription": "CRC Errors Detected; Normal Operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
         "PerPkg": "1",
@@ -116,10 +103,8 @@
     },
     {
         "BriefDescription": "VN0 Credit Consumed; DRS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1e",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
         "UMask": "0x1",
@@ -127,10 +112,8 @@
     },
     {
         "BriefDescription": "VN0 Credit Consumed; HOM",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1e",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
         "UMask": "0x8",
@@ -138,10 +121,8 @@
     },
     {
         "BriefDescription": "VN0 Credit Consumed; NCB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1e",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
         "UMask": "0x2",
@@ -149,10 +130,8 @@
     },
     {
         "BriefDescription": "VN0 Credit Consumed; NCS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1e",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
         "UMask": "0x4",
@@ -160,10 +139,8 @@
     },
     {
         "BriefDescription": "VN0 Credit Consumed; NDR",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1e",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
         "UMask": "0x20",
@@ -171,10 +148,8 @@
     },
     {
         "BriefDescription": "VN0 Credit Consumed; SNP",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1e",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
         "UMask": "0x10",
@@ -182,17 +157,14 @@
     },
     {
         "BriefDescription": "VNA Credit Consumed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1d",
         "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Cycles Not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0xa",
         "EventName": "UNC_Q_RxL_CYCLES_NE",
         "PerPkg": "1",
@@ -201,7 +173,6 @@
     },
     {
         "BriefDescription": "Flits Received - Group 0; Data Tx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_Q_RxL_FLITS_G0.DATA",
         "PerPkg": "1",
@@ -211,7 +182,6 @@
     },
     {
         "BriefDescription": "Flits Received - Group 0; Idle and Null Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_Q_RxL_FLITS_G0.IDLE",
         "PerPkg": "1",
@@ -221,7 +191,6 @@
     },
     {
         "BriefDescription": "Flits Received - Group 0; Non-Data protocol Tx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_Q_RxL_FLITS_G0.NON_DATA",
         "PerPkg": "1",
@@ -231,10 +200,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_Q_RxL_FLITS_G1.DRS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x18",
@@ -242,10 +209,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 1; DRS Data Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x8",
@@ -253,10 +218,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 1; DRS Header Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x10",
@@ -264,10 +227,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 1; HOM Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_Q_RxL_FLITS_G1.HOM",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x6",
@@ -275,10 +236,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x4",
@@ -286,10 +245,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 1; HOM Request Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x2",
@@ -297,10 +254,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 1; SNP Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_Q_RxL_FLITS_G1.SNP",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x1",
@@ -308,10 +263,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_Q_RxL_FLITS_G2.NCB",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0xc",
@@ -319,10 +272,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 2; Non-Coherent data Rx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x4",
@@ -330,10 +281,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 2; Non-Coherent non-data Rx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x8",
@@ -341,10 +290,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_Q_RxL_FLITS_G2.NCS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x10",
@@ -352,10 +299,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x1",
@@ -363,10 +308,8 @@
     },
     {
         "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits received from the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x2",
@@ -374,7 +317,6 @@
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_Q_RxL_INSERTS",
         "PerPkg": "1",
@@ -383,67 +325,54 @@
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - DRS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_Q_RxL_INSERTS_DRS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only DRS flits.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - HOM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc",
         "EventName": "UNC_Q_RxL_INSERTS_HOM",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only HOM flits.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - NCB",
-        "Counter": "0,1,2,3",
         "EventCode": "0xa",
         "EventName": "UNC_Q_RxL_INSERTS_NCB",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCB flits.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - NCS",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb",
         "EventName": "UNC_Q_RxL_INSERTS_NCS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NCS flits.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - NDR",
-        "Counter": "0,1,2,3",
         "EventCode": "0xe",
         "EventName": "UNC_Q_RxL_INSERTS_NDR",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only NDR flits.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Rx Flit Buffer Allocations - SNP",
-        "Counter": "0,1,2,3",
         "EventCode": "0xd",
         "EventName": "UNC_Q_RxL_INSERTS_SNP",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.  This monitors only SNP flits.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - All Packets",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb",
         "EventName": "UNC_Q_RxL_OCCUPANCY",
         "PerPkg": "1",
@@ -452,67 +381,54 @@
     },
     {
         "BriefDescription": "RxQ Occupancy - DRS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x15",
         "EventName": "UNC_Q_RxL_OCCUPANCY_DRS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors DRS flits only.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - HOM",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_Q_RxL_OCCUPANCY_HOM",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors HOM flits only.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - NCB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x16",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NCB",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCB flits only.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - NCS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x17",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NCS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NCS flits only.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - NDR",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1a",
         "EventName": "UNC_Q_RxL_OCCUPANCY_NDR",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors NDR flits only.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "RxQ Occupancy - SNP",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_Q_RxL_OCCUPANCY_SNP",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle.  Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.  This monitors SNP flits only.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - HOM",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_Q_RxL_STALLS.BGF_DRS",
         "PerPkg": "1",
@@ -522,7 +438,6 @@
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - DRS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_Q_RxL_STALLS.BGF_HOM",
         "PerPkg": "1",
@@ -532,7 +447,6 @@
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - SNP",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_Q_RxL_STALLS.BGF_NCB",
         "PerPkg": "1",
@@ -542,7 +456,6 @@
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - NDR",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_Q_RxL_STALLS.BGF_NCS",
         "PerPkg": "1",
@@ -552,7 +465,6 @@
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - NCS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_Q_RxL_STALLS.BGF_NDR",
         "PerPkg": "1",
@@ -562,7 +474,6 @@
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - NCB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_Q_RxL_STALLS.BGF_SNP",
         "PerPkg": "1",
@@ -572,7 +483,6 @@
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI; Egress Credits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_Q_RxL_STALLS.EGRESS_CREDITS",
         "PerPkg": "1",
@@ -582,7 +492,6 @@
     },
     {
         "BriefDescription": "Stalls Sending to R3QPI; GV",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_Q_RxL_STALLS.GV",
         "PerPkg": "1",
@@ -592,7 +501,6 @@
     },
     {
         "BriefDescription": "Cycles in L0p",
-        "Counter": "0,1,2,3",
         "EventCode": "0xd",
         "EventName": "UNC_Q_TxL0P_POWER_CYCLES",
         "PerPkg": "1",
@@ -601,7 +509,6 @@
     },
     {
         "BriefDescription": "Cycles in L0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc",
         "EventName": "UNC_Q_TxL0_POWER_CYCLES",
         "PerPkg": "1",
@@ -610,7 +517,6 @@
     },
     {
         "BriefDescription": "Tx Flit Buffer Bypassed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_Q_TxL_BYPASSED",
         "PerPkg": "1",
@@ -619,7 +525,6 @@
     },
     {
         "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL",
         "PerPkg": "1",
@@ -629,7 +534,6 @@
     },
     {
         "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL",
         "PerPkg": "1",
@@ -639,7 +543,6 @@
     },
     {
         "BriefDescription": "Tx Flit Buffer Cycles not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_Q_TxL_CYCLES_NE",
         "PerPkg": "1",
@@ -648,7 +551,6 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G0.DATA",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.",
@@ -657,7 +559,6 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 0; Idle and Null Flits",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G0.IDLE",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.",
@@ -666,7 +567,6 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits transmitted across the QPI Link.  It includes filters for Idle, protocol, and Data Flits.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.",
@@ -675,9 +575,7 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G1.DRS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x18",
@@ -685,9 +583,7 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x8",
@@ -695,9 +591,7 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x10",
@@ -705,9 +599,7 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 1; HOM Flits",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G1.HOM",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x6",
@@ -715,9 +607,7 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x4",
@@ -725,9 +615,7 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x2",
@@ -735,9 +623,7 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 1; SNP Flits",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_Q_TxL_FLITS_G1.SNP",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for SNP, HOM, and DRS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x1",
@@ -745,10 +631,8 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_Q_TxL_FLITS_G2.NCB",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0xc",
@@ -756,10 +640,8 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 2; Non-Coherent data Tx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x4",
@@ -767,10 +649,8 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 2; Non-Coherent non-data Tx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x8",
@@ -778,10 +658,8 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_Q_TxL_FLITS_G2.NCS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x10",
@@ -789,10 +667,8 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x1",
@@ -800,10 +676,8 @@
     },
     {
         "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of flits trasmitted across the QPI Link.  This is one of three 'groups' that allow us to track flits.  It includes filters for NDR, NCB, and NCS message classes.  Each 'flit' is made up of 80 bits of information (in addition to some ECC data).  In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data).   In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit.  When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'.  Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed.  One can calculate the bandwidth of the link by taking: flits*80b/time.  Note that this is not the same as 'data' bandwidth.  For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information.  To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.",
         "UMask": "0x2",
@@ -811,7 +685,6 @@
     },
     {
         "BriefDescription": "Tx Flit Buffer Allocations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_Q_TxL_INSERTS",
         "PerPkg": "1",
@@ -820,7 +693,6 @@
     },
     {
         "BriefDescription": "Tx Flit Buffer Occupancy",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_Q_TxL_OCCUPANCY",
         "PerPkg": "1",
@@ -829,20 +701,16 @@
     },
     {
         "BriefDescription": "VNA Credits Returned",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1c",
         "EventName": "UNC_Q_VNA_CREDIT_RETURNS",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of VNA credits returned.",
         "Unit": "QPI LL"
     },
     {
         "BriefDescription": "VNA Credits Pending Return - Occupancy",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1b",
         "EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.",
         "Unit": "QPI LL"
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json
index a165a77947a07..2faf0dc6675d5 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "DRAM Activate Count",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_M_ACT_COUNT",
         "PerPkg": "1",
@@ -10,77 +9,62 @@
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.ALL",
         "PerPkg": "1",
-        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
         "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.RD",
         "PerPkg": "1",
-        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
         "UMask": "0x3",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.RD_REG",
         "PerPkg": "1",
-        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
         "PerPkg": "1",
-        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
         "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.WR",
         "PerPkg": "1",
-        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
         "UMask": "0xc",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.WR_RMM",
         "PerPkg": "1",
-        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
         "UMask": "0x8",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.WR_WMM",
         "PerPkg": "1",
-        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
         "UMask": "0x4",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "uclks",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_M_CLOCKTICKS",
         "PerPkg": "1",
         "PublicDescription": "Uncore Fixed Counter - uclks",
@@ -88,7 +72,6 @@
     },
     {
         "BriefDescription": "DRAM Precharge All Commands",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_M_DRAM_PRE_ALL",
         "PerPkg": "1",
@@ -97,7 +80,6 @@
     },
     {
         "BriefDescription": "Number of DRAM Refreshes Issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_M_DRAM_REFRESH.HIGH",
         "PerPkg": "1",
@@ -107,7 +89,6 @@
     },
     {
         "BriefDescription": "Number of DRAM Refreshes Issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_M_DRAM_REFRESH.PANIC",
         "PerPkg": "1",
@@ -117,7 +98,6 @@
     },
     {
         "BriefDescription": "ECC Correctable Errors",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
         "PerPkg": "1",
@@ -126,7 +106,6 @@
     },
     {
         "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_M_MAJOR_MODES.ISOCH",
         "PerPkg": "1",
@@ -136,7 +115,6 @@
     },
     {
         "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
         "PerPkg": "1",
@@ -146,7 +124,6 @@
     },
     {
         "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_M_MAJOR_MODES.READ",
         "PerPkg": "1",
@@ -156,7 +133,6 @@
     },
     {
         "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_M_MAJOR_MODES.WRITE",
         "PerPkg": "1",
@@ -166,7 +142,6 @@
     },
     {
         "BriefDescription": "Channel DLLOFF Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x84",
         "EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
         "PerPkg": "1",
@@ -175,7 +150,6 @@
     },
     {
         "BriefDescription": "Channel PPD Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "UNC_M_POWER_CHANNEL_PPD",
         "PerPkg": "1",
@@ -184,7 +158,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
         "PerPkg": "1",
@@ -194,7 +167,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
         "PerPkg": "1",
@@ -204,7 +176,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
         "PerPkg": "1",
@@ -214,7 +185,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
         "PerPkg": "1",
@@ -224,7 +194,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
         "PerPkg": "1",
@@ -234,7 +203,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
         "PerPkg": "1",
@@ -244,7 +212,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
         "PerPkg": "1",
@@ -254,7 +221,6 @@
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
         "PerPkg": "1",
@@ -264,7 +230,6 @@
     },
     {
         "BriefDescription": "Critical Throttle Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x86",
         "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
         "PerPkg": "1",
@@ -273,7 +238,6 @@
     },
     {
         "BriefDescription": "Clock-Enabled Self-Refresh",
-        "Counter": "0,1,2,3",
         "EventCode": "0x43",
         "EventName": "UNC_M_POWER_SELF_REFRESH",
         "PerPkg": "1",
@@ -282,7 +246,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
         "PerPkg": "1",
@@ -292,7 +255,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
         "PerPkg": "1",
@@ -302,7 +264,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
         "PerPkg": "1",
@@ -312,7 +273,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
         "PerPkg": "1",
@@ -322,7 +282,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
         "PerPkg": "1",
@@ -332,7 +291,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
         "PerPkg": "1",
@@ -342,7 +300,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
         "PerPkg": "1",
@@ -352,7 +309,6 @@
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
         "PerPkg": "1",
@@ -362,7 +318,6 @@
     },
     {
         "BriefDescription": "Read Preemption Count; Read over Read Preemption",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
         "PerPkg": "1",
@@ -372,7 +327,6 @@
     },
     {
         "BriefDescription": "Read Preemption Count; Read over Write Preemption",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
         "PerPkg": "1",
@@ -382,7 +336,6 @@
     },
     {
         "BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
         "PerPkg": "1",
@@ -392,7 +345,6 @@
     },
     {
         "BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
         "PerPkg": "1",
@@ -402,7 +354,6 @@
     },
     {
         "BriefDescription": "Read Pending Queue Full Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_M_RPQ_CYCLES_FULL",
         "PerPkg": "1",
@@ -411,7 +362,6 @@
     },
     {
         "BriefDescription": "Read Pending Queue Not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0x11",
         "EventName": "UNC_M_RPQ_CYCLES_NE",
         "PerPkg": "1",
@@ -420,7 +370,6 @@
     },
     {
         "BriefDescription": "Read Pending Queue Allocations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_M_RPQ_INSERTS",
         "PerPkg": "1",
@@ -429,7 +378,6 @@
     },
     {
         "BriefDescription": "Read Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_M_RPQ_OCCUPANCY",
         "PerPkg": "1",
@@ -438,7 +386,6 @@
     },
     {
         "BriefDescription": "Write Pending Queue Full Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_M_WPQ_CYCLES_FULL",
         "PerPkg": "1",
@@ -447,7 +394,6 @@
     },
     {
         "BriefDescription": "Write Pending Queue Not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_M_WPQ_CYCLES_NE",
         "PerPkg": "1",
@@ -456,7 +402,6 @@
     },
     {
         "BriefDescription": "Write Pending Queue Allocations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "UNC_M_WPQ_INSERTS",
         "PerPkg": "1",
@@ -465,7 +410,6 @@
     },
     {
         "BriefDescription": "Write Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
         "EventCode": "0x81",
         "EventName": "UNC_M_WPQ_OCCUPANCY",
         "PerPkg": "1",
@@ -474,7 +418,6 @@
     },
     {
         "BriefDescription": "Write Pending Queue CAM Match",
-        "Counter": "0,1,2,3",
         "EventCode": "0x23",
         "EventName": "UNC_M_WPQ_READ_HIT",
         "PerPkg": "1",
@@ -483,7 +426,6 @@
     },
     {
         "BriefDescription": "Write Pending Queue CAM Match",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_M_WPQ_WRITE_HIT",
         "PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-other.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-other.json
index 588549a668bdf..51a9a4e810462 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-other.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Address Match (Conflict) Count; Conflict Merges",
-        "Counter": "0,1",
         "EventCode": "0x17",
         "EventName": "UNC_I_ADDRESS_MATCH.MERGE_COUNT",
         "PerPkg": "1",
@@ -11,7 +10,6 @@
     },
     {
         "BriefDescription": "Address Match (Conflict) Count; Conflict Stalls",
-        "Counter": "0,1",
         "EventCode": "0x17",
         "EventName": "UNC_I_ADDRESS_MATCH.STALL_COUNT",
         "PerPkg": "1",
@@ -21,7 +19,6 @@
     },
     {
         "BriefDescription": "Write Ack Pending Occupancy; Any Source",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.ANY",
         "PerPkg": "1",
@@ -31,7 +28,6 @@
     },
     {
         "BriefDescription": "Write Ack Pending Occupancy; Select Source",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.SOURCE",
         "PerPkg": "1",
@@ -41,7 +37,6 @@
     },
     {
         "BriefDescription": "Outstanding Write Ownership Occupancy; Any Source",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.ANY",
         "PerPkg": "1",
@@ -51,7 +46,6 @@
     },
     {
         "BriefDescription": "Outstanding Write Ownership Occupancy; Select Source",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.SOURCE",
         "PerPkg": "1",
@@ -61,7 +55,6 @@
     },
     {
         "BriefDescription": "Outstanding Read Occupancy; Any Source",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_I_CACHE_READ_OCCUPANCY.ANY",
         "PerPkg": "1",
@@ -71,7 +64,6 @@
     },
     {
         "BriefDescription": "Outstanding Read Occupancy; Select Source",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_I_CACHE_READ_OCCUPANCY.SOURCE",
         "PerPkg": "1",
@@ -81,7 +73,6 @@
     },
     {
         "BriefDescription": "Total Write Cache Occupancy; Any Source",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
         "PerPkg": "1",
@@ -91,7 +82,6 @@
     },
     {
         "BriefDescription": "Total Write Cache Occupancy; Select Source",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
         "PerPkg": "1",
@@ -101,7 +91,6 @@
     },
     {
         "BriefDescription": "Outstanding Write Occupancy; Any Source",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.ANY",
         "PerPkg": "1",
@@ -111,7 +100,6 @@
     },
     {
         "BriefDescription": "Outstanding Write Occupancy; Select Source",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.SOURCE",
         "PerPkg": "1",
@@ -121,14 +109,12 @@
     },
     {
         "BriefDescription": "Clocks in the IRP",
-        "Counter": "0,1",
         "EventName": "UNC_I_CLOCKTICKS",
         "PerPkg": "1",
         "PublicDescription": "Number of clocks in the IRP.",
         "Unit": "IRP"
     },
     {
-        "Counter": "0,1",
         "EventCode": "0xB",
         "EventName": "UNC_I_RxR_AK_CYCLES_FULL",
         "PerPkg": "1",
@@ -137,7 +123,6 @@
     },
     {
         "BriefDescription": "AK Ingress Occupancy",
-        "Counter": "0,1",
         "EventCode": "0xA",
         "EventName": "UNC_I_RxR_AK_INSERTS",
         "PerPkg": "1",
@@ -145,7 +130,6 @@
         "Unit": "IRP"
     },
     {
-        "Counter": "0,1",
         "EventCode": "0xC",
         "EventName": "UNC_I_RxR_AK_OCCUPANCY",
         "PerPkg": "1",
@@ -153,7 +137,6 @@
         "Unit": "IRP"
     },
     {
-        "Counter": "0,1",
         "EventCode": "0x4",
         "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
         "PerPkg": "1",
@@ -162,7 +145,6 @@
     },
     {
         "BriefDescription": "BL Ingress Occupancy - DRS",
-        "Counter": "0,1",
         "EventCode": "0x1",
         "EventName": "UNC_I_RxR_BL_DRS_INSERTS",
         "PerPkg": "1",
@@ -170,7 +152,6 @@
         "Unit": "IRP"
     },
     {
-        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY",
         "PerPkg": "1",
@@ -178,7 +159,6 @@
         "Unit": "IRP"
     },
     {
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
         "PerPkg": "1",
@@ -187,7 +167,6 @@
     },
     {
         "BriefDescription": "BL Ingress Occupancy - NCB",
-        "Counter": "0,1",
         "EventCode": "0x2",
         "EventName": "UNC_I_RxR_BL_NCB_INSERTS",
         "PerPkg": "1",
@@ -195,7 +174,6 @@
         "Unit": "IRP"
     },
     {
-        "Counter": "0,1",
         "EventCode": "0x8",
         "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY",
         "PerPkg": "1",
@@ -203,7 +181,6 @@
         "Unit": "IRP"
     },
     {
-        "Counter": "0,1",
         "EventCode": "0x6",
         "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
         "PerPkg": "1",
@@ -212,7 +189,6 @@
     },
     {
         "BriefDescription": "BL Ingress Occupancy - NCS",
-        "Counter": "0,1",
         "EventCode": "0x3",
         "EventName": "UNC_I_RxR_BL_NCS_INSERTS",
         "PerPkg": "1",
@@ -220,7 +196,6 @@
         "Unit": "IRP"
     },
     {
-        "Counter": "0,1",
         "EventCode": "0x9",
         "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY",
         "PerPkg": "1",
@@ -229,7 +204,6 @@
     },
     {
         "BriefDescription": "Tickle Count; Ownership Lost",
-        "Counter": "0,1",
         "EventCode": "0x16",
         "EventName": "UNC_I_TICKLES.LOST_OWNERSHIP",
         "PerPkg": "1",
@@ -239,7 +213,6 @@
     },
     {
         "BriefDescription": "Tickle Count; Data Returned",
-        "Counter": "0,1",
         "EventCode": "0x16",
         "EventName": "UNC_I_TICKLES.TOP_OF_QUEUE",
         "PerPkg": "1",
@@ -249,7 +222,6 @@
     },
     {
         "BriefDescription": "Inbound Transaction Count; Read Prefetches",
-        "Counter": "0,1",
         "EventCode": "0x15",
         "EventName": "UNC_I_TRANSACTIONS.PD_PREFETCHES",
         "PerPkg": "1",
@@ -259,7 +231,6 @@
     },
     {
         "BriefDescription": "Inbound Transaction Count; Reads",
-        "Counter": "0,1",
         "EventCode": "0x15",
         "EventName": "UNC_I_TRANSACTIONS.READS",
         "PerPkg": "1",
@@ -269,7 +240,6 @@
     },
     {
         "BriefDescription": "Inbound Transaction Count; Writes",
-        "Counter": "0,1",
         "EventCode": "0x15",
         "EventName": "UNC_I_TRANSACTIONS.WRITES",
         "PerPkg": "1",
@@ -279,7 +249,6 @@
     },
     {
         "BriefDescription": "No AD Egress Credit Stalls",
-        "Counter": "0,1",
         "EventCode": "0x18",
         "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
         "PerPkg": "1",
@@ -288,7 +257,6 @@
     },
     {
         "BriefDescription": "No BL Egress Credit Stalls",
-        "Counter": "0,1",
         "EventCode": "0x19",
         "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
         "PerPkg": "1",
@@ -297,7 +265,6 @@
     },
     {
         "BriefDescription": "Outbound Read Requests",
-        "Counter": "0,1",
         "EventCode": "0xE",
         "EventName": "UNC_I_TxR_DATA_INSERTS_NCB",
         "PerPkg": "1",
@@ -306,7 +273,6 @@
     },
     {
         "BriefDescription": "Outbound Read Requests",
-        "Counter": "0,1",
         "EventCode": "0xF",
         "EventName": "UNC_I_TxR_DATA_INSERTS_NCS",
         "PerPkg": "1",
@@ -315,7 +281,6 @@
     },
     {
         "BriefDescription": "Outbound Request Queue Occupancy",
-        "Counter": "0,1",
         "EventCode": "0xD",
         "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY",
         "PerPkg": "1",
@@ -324,7 +289,6 @@
     },
     {
         "BriefDescription": "Write Ordering Stalls",
-        "Counter": "0,1",
         "EventCode": "0x1A",
         "EventName": "UNC_I_WRITE_ORDERING_STALL_CYCLES",
         "PerPkg": "1",
@@ -333,7 +297,6 @@
     },
     {
         "BriefDescription": "Number of uclks in domain",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_R2_CLOCKTICKS",
         "PerPkg": "1",
@@ -342,7 +305,6 @@
     },
     {
         "BriefDescription": "R2PCIe IIO Credit Acquired; DRS",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
         "PerPkg": "1",
@@ -352,7 +314,6 @@
     },
     {
         "BriefDescription": "R2PCIe IIO Credit Acquired; NCB",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
         "PerPkg": "1",
@@ -362,7 +323,6 @@
     },
     {
         "BriefDescription": "R2PCIe IIO Credit Acquired; NCS",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
         "PerPkg": "1",
@@ -372,7 +332,6 @@
     },
     {
         "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; DRS",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_R2_IIO_CREDITS_REJECT.DRS",
         "PerPkg": "1",
@@ -382,7 +341,6 @@
     },
     {
         "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; NCB",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_R2_IIO_CREDITS_REJECT.NCB",
         "PerPkg": "1",
@@ -392,7 +350,6 @@
     },
     {
         "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; NCS",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_R2_IIO_CREDITS_REJECT.NCS",
         "PerPkg": "1",
@@ -402,7 +359,6 @@
     },
     {
         "BriefDescription": "R2PCIe IIO Credits in Use; DRS",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_R2_IIO_CREDITS_USED.DRS",
         "PerPkg": "1",
@@ -412,7 +368,6 @@
     },
     {
         "BriefDescription": "R2PCIe IIO Credits in Use; NCB",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_R2_IIO_CREDITS_USED.NCB",
         "PerPkg": "1",
@@ -422,7 +377,6 @@
     },
     {
         "BriefDescription": "R2PCIe IIO Credits in Use; NCS",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_R2_IIO_CREDITS_USED.NCS",
         "PerPkg": "1",
@@ -432,7 +386,6 @@
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CCW_EVEN",
         "PerPkg": "1",
@@ -442,7 +395,6 @@
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CCW_ODD",
         "PerPkg": "1",
@@ -452,7 +404,6 @@
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CW_EVEN",
         "PerPkg": "1",
@@ -462,7 +413,6 @@
     },
     {
         "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_R2_RING_AD_USED.CW_ODD",
         "PerPkg": "1",
@@ -472,7 +422,6 @@
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CCW_EVEN",
         "PerPkg": "1",
@@ -482,7 +431,6 @@
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CCW_ODD",
         "PerPkg": "1",
@@ -492,7 +440,6 @@
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CW_EVEN",
         "PerPkg": "1",
@@ -502,7 +449,6 @@
     },
     {
         "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_R2_RING_AK_USED.CW_ODD",
         "PerPkg": "1",
@@ -512,7 +458,6 @@
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CCW_EVEN",
         "PerPkg": "1",
@@ -522,7 +467,6 @@
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CCW_ODD",
         "PerPkg": "1",
@@ -532,7 +476,6 @@
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CW_EVEN",
         "PerPkg": "1",
@@ -542,7 +485,6 @@
     },
     {
         "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_R2_RING_BL_USED.CW_ODD",
         "PerPkg": "1",
@@ -552,7 +494,6 @@
     },
     {
         "BriefDescription": "R2 IV Ring in Use; Any",
-        "Counter": "0,1,2,3",
         "EventCode": "0xa",
         "EventName": "UNC_R2_RING_IV_USED.ANY",
         "PerPkg": "1",
@@ -570,7 +511,6 @@
     },
     {
         "BriefDescription": "Ingress Cycles Not Empty; DRS",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R2_RxR_CYCLES_NE.DRS",
         "PerPkg": "1",
@@ -580,7 +520,6 @@
     },
     {
         "BriefDescription": "Ingress Cycles Not Empty; NCB",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R2_RxR_CYCLES_NE.NCB",
         "PerPkg": "1",
@@ -590,7 +529,6 @@
     },
     {
         "BriefDescription": "Ingress Cycles Not Empty; NCS",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R2_RxR_CYCLES_NE.NCS",
         "PerPkg": "1",
@@ -654,7 +592,6 @@
     },
     {
         "BriefDescription": "Egress NACK; AD",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R2_TxR_NACKS.AD",
         "PerPkg": "1",
@@ -664,7 +601,6 @@
     },
     {
         "BriefDescription": "Egress NACK; AK",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R2_TxR_NACKS.AK",
         "PerPkg": "1",
@@ -674,7 +610,6 @@
     },
     {
         "BriefDescription": "Egress NACK; BL",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "UNC_R2_TxR_NACKS.BL",
         "PerPkg": "1",
@@ -684,7 +619,6 @@
     },
     {
         "BriefDescription": "Number of uclks in domain",
-        "Counter": "0,1,2",
         "EventCode": "0x1",
         "EventName": "UNC_R3_CLOCKTICKS",
         "PerPkg": "1",
@@ -693,7 +627,6 @@
     },
     {
         "BriefDescription": "to IIO BL Credit Acquired",
-        "Counter": "0,1",
         "EventCode": "0x20",
         "EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.DRS",
         "PerPkg": "1",
@@ -703,7 +636,6 @@
     },
     {
         "BriefDescription": "to IIO BL Credit Acquired",
-        "Counter": "0,1",
         "EventCode": "0x20",
         "EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.NCB",
         "PerPkg": "1",
@@ -713,7 +645,6 @@
     },
     {
         "BriefDescription": "to IIO BL Credit Acquired",
-        "Counter": "0,1",
         "EventCode": "0x20",
         "EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.NCS",
         "PerPkg": "1",
@@ -723,7 +654,6 @@
     },
     {
         "BriefDescription": "to IIO BL Credit Rejected",
-        "Counter": "0,1",
         "EventCode": "0x21",
         "EventName": "UNC_R3_IIO_CREDITS_REJECT.DRS",
         "PerPkg": "1",
@@ -733,7 +663,6 @@
     },
     {
         "BriefDescription": "to IIO BL Credit Rejected",
-        "Counter": "0,1",
         "EventCode": "0x21",
         "EventName": "UNC_R3_IIO_CREDITS_REJECT.NCB",
         "PerPkg": "1",
@@ -743,7 +672,6 @@
     },
     {
         "BriefDescription": "to IIO BL Credit Rejected",
-        "Counter": "0,1",
         "EventCode": "0x21",
         "EventName": "UNC_R3_IIO_CREDITS_REJECT.NCS",
         "PerPkg": "1",
@@ -753,7 +681,6 @@
     },
     {
         "BriefDescription": "to IIO BL Credit In Use",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_R3_IIO_CREDITS_USED.DRS",
         "PerPkg": "1",
@@ -763,7 +690,6 @@
     },
     {
         "BriefDescription": "to IIO BL Credit In Use",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_R3_IIO_CREDITS_USED.NCB",
         "PerPkg": "1",
@@ -773,7 +699,6 @@
     },
     {
         "BriefDescription": "to IIO BL Credit In Use",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_R3_IIO_CREDITS_USED.NCS",
         "PerPkg": "1",
@@ -783,7 +708,6 @@
     },
     {
         "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2",
         "EventCode": "0x7",
         "EventName": "UNC_R3_RING_AD_USED.CCW_EVEN",
         "PerPkg": "1",
@@ -793,7 +717,6 @@
     },
     {
         "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2",
         "EventCode": "0x7",
         "EventName": "UNC_R3_RING_AD_USED.CCW_ODD",
         "PerPkg": "1",
@@ -803,7 +726,6 @@
     },
     {
         "BriefDescription": "R3 AD Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2",
         "EventCode": "0x7",
         "EventName": "UNC_R3_RING_AD_USED.CW_EVEN",
         "PerPkg": "1",
@@ -813,7 +735,6 @@
     },
     {
         "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2",
         "EventCode": "0x7",
         "EventName": "UNC_R3_RING_AD_USED.CW_ODD",
         "PerPkg": "1",
@@ -823,7 +744,6 @@
     },
     {
         "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2",
         "EventCode": "0x8",
         "EventName": "UNC_R3_RING_AK_USED.CCW_EVEN",
         "PerPkg": "1",
@@ -833,7 +753,6 @@
     },
     {
         "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2",
         "EventCode": "0x8",
         "EventName": "UNC_R3_RING_AK_USED.CCW_ODD",
         "PerPkg": "1",
@@ -843,7 +762,6 @@
     },
     {
         "BriefDescription": "R3 AK Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2",
         "EventCode": "0x8",
         "EventName": "UNC_R3_RING_AK_USED.CW_EVEN",
         "PerPkg": "1",
@@ -853,7 +771,6 @@
     },
     {
         "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2",
         "EventCode": "0x8",
         "EventName": "UNC_R3_RING_AK_USED.CW_ODD",
         "PerPkg": "1",
@@ -863,7 +780,6 @@
     },
     {
         "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even",
-        "Counter": "0,1,2",
         "EventCode": "0x9",
         "EventName": "UNC_R3_RING_BL_USED.CCW_EVEN",
         "PerPkg": "1",
@@ -873,7 +789,6 @@
     },
     {
         "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd",
-        "Counter": "0,1,2",
         "EventCode": "0x9",
         "EventName": "UNC_R3_RING_BL_USED.CCW_ODD",
         "PerPkg": "1",
@@ -883,7 +798,6 @@
     },
     {
         "BriefDescription": "R3 BL Ring in Use; Clockwise and Even",
-        "Counter": "0,1,2",
         "EventCode": "0x9",
         "EventName": "UNC_R3_RING_BL_USED.CW_EVEN",
         "PerPkg": "1",
@@ -893,7 +807,6 @@
     },
     {
         "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd",
-        "Counter": "0,1,2",
         "EventCode": "0x9",
         "EventName": "UNC_R3_RING_BL_USED.CW_ODD",
         "PerPkg": "1",
@@ -903,7 +816,6 @@
     },
     {
         "BriefDescription": "R3 IV Ring in Use; Any",
-        "Counter": "0,1,2",
         "EventCode": "0xa",
         "EventName": "UNC_R3_RING_IV_USED.ANY",
         "PerPkg": "1",
@@ -913,7 +825,6 @@
     },
     {
         "BriefDescription": "Ingress Bypassed",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "UNC_R3_RxR_BYPASSED.AD",
         "PerPkg": "1",
@@ -923,7 +834,6 @@
     },
     {
         "BriefDescription": "Ingress Cycles Not Empty; DRS",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R3_RxR_CYCLES_NE.DRS",
         "PerPkg": "1",
@@ -933,7 +843,6 @@
     },
     {
         "BriefDescription": "Ingress Cycles Not Empty; HOM",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R3_RxR_CYCLES_NE.HOM",
         "PerPkg": "1",
@@ -943,7 +852,6 @@
     },
     {
         "BriefDescription": "Ingress Cycles Not Empty; NCB",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R3_RxR_CYCLES_NE.NCB",
         "PerPkg": "1",
@@ -953,7 +861,6 @@
     },
     {
         "BriefDescription": "Ingress Cycles Not Empty; NCS",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R3_RxR_CYCLES_NE.NCS",
         "PerPkg": "1",
@@ -963,7 +870,6 @@
     },
     {
         "BriefDescription": "Ingress Cycles Not Empty; NDR",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R3_RxR_CYCLES_NE.NDR",
         "PerPkg": "1",
@@ -973,7 +879,6 @@
     },
     {
         "BriefDescription": "Ingress Cycles Not Empty; SNP",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "UNC_R3_RxR_CYCLES_NE.SNP",
         "PerPkg": "1",
@@ -983,7 +888,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; DRS",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R3_RxR_INSERTS.DRS",
         "PerPkg": "1",
@@ -993,7 +897,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; HOM",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R3_RxR_INSERTS.HOM",
         "PerPkg": "1",
@@ -1003,7 +906,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; NCB",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R3_RxR_INSERTS.NCB",
         "PerPkg": "1",
@@ -1013,7 +915,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; NCS",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R3_RxR_INSERTS.NCS",
         "PerPkg": "1",
@@ -1023,7 +924,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; NDR",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R3_RxR_INSERTS.NDR",
         "PerPkg": "1",
@@ -1033,7 +933,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations; SNP",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "UNC_R3_RxR_INSERTS.SNP",
         "PerPkg": "1",
@@ -1097,7 +996,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS",
         "PerPkg": "1",
@@ -1107,7 +1005,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM",
         "PerPkg": "1",
@@ -1117,7 +1014,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Message Class",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB",
         "PerPkg": "1",
@@ -1127,7 +1023,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS",
         "PerPkg": "1",
@@ -1137,7 +1032,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR",
         "PerPkg": "1",
@@ -1147,7 +1041,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class",
-        "Counter": "0,1",
         "EventCode": "0x37",
         "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP",
         "PerPkg": "1",
@@ -1157,7 +1050,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Used; DRS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x36",
         "EventName": "UNC_R3_VN0_CREDITS_USED.DRS",
         "PerPkg": "1",
@@ -1167,7 +1059,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Used; HOM Message Class",
-        "Counter": "0,1",
         "EventCode": "0x36",
         "EventName": "UNC_R3_VN0_CREDITS_USED.HOM",
         "PerPkg": "1",
@@ -1177,7 +1068,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Used; NCB Message Class",
-        "Counter": "0,1",
         "EventCode": "0x36",
         "EventName": "UNC_R3_VN0_CREDITS_USED.NCB",
         "PerPkg": "1",
@@ -1187,7 +1077,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Used; NCS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x36",
         "EventName": "UNC_R3_VN0_CREDITS_USED.NCS",
         "PerPkg": "1",
@@ -1197,7 +1086,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Used; NDR Message Class",
-        "Counter": "0,1",
         "EventCode": "0x36",
         "EventName": "UNC_R3_VN0_CREDITS_USED.NDR",
         "PerPkg": "1",
@@ -1207,7 +1095,6 @@
     },
     {
         "BriefDescription": "VN0 Credit Used; SNP Message Class",
-        "Counter": "0,1",
         "EventCode": "0x36",
         "EventName": "UNC_R3_VN0_CREDITS_USED.SNP",
         "PerPkg": "1",
@@ -1217,7 +1104,6 @@
     },
     {
         "BriefDescription": "VNA credit Acquisitions",
-        "Counter": "0,1",
         "EventCode": "0x33",
         "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED",
         "PerPkg": "1",
@@ -1226,7 +1112,6 @@
     },
     {
         "BriefDescription": "VNA Credit Reject; DRS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS",
         "PerPkg": "1",
@@ -1236,7 +1121,6 @@
     },
     {
         "BriefDescription": "VNA Credit Reject; HOM Message Class",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM",
         "PerPkg": "1",
@@ -1246,7 +1130,6 @@
     },
     {
         "BriefDescription": "VNA Credit Reject; NCB Message Class",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB",
         "PerPkg": "1",
@@ -1256,7 +1139,6 @@
     },
     {
         "BriefDescription": "VNA Credit Reject; NCS Message Class",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS",
         "PerPkg": "1",
@@ -1266,7 +1148,6 @@
     },
     {
         "BriefDescription": "VNA Credit Reject; NDR Message Class",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR",
         "PerPkg": "1",
@@ -1276,7 +1157,6 @@
     },
     {
         "BriefDescription": "VNA Credit Reject; SNP Message Class",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP",
         "PerPkg": "1",
@@ -1286,7 +1166,6 @@
     },
     {
         "BriefDescription": "Cycles with no VNA credits available",
-        "Counter": "0,1",
         "EventCode": "0x31",
         "EventName": "UNC_R3_VNA_CREDIT_CYCLES_OUT",
         "PerPkg": "1",
@@ -1295,16 +1174,19 @@
     },
     {
         "BriefDescription": "Cycles with 1 or more VNA credits in use",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "UNC_R3_VNA_CREDIT_CYCLES_USED",
         "PerPkg": "1",
         "PublicDescription": "Number of QPI uclk cycles with one or more VNA credits in use.  This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average number of used VNA credits.",
         "Unit": "R3QPI"
     },
+    {
+        "EventName": "UNC_U_CLOCKTICKS",
+        "PerPkg": "1",
+        "Unit": "UBOX"
+    },
     {
         "BriefDescription": "VLW Received",
-        "Counter": "0,1",
         "EventCode": "0x42",
         "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
         "PerPkg": "1",
@@ -1314,7 +1196,6 @@
     },
     {
         "BriefDescription": "VLW Received",
-        "Counter": "0,1",
         "EventCode": "0x42",
         "EventName": "UNC_U_EVENT_MSG.INT_PRIO",
         "PerPkg": "1",
@@ -1324,7 +1205,6 @@
     },
     {
         "BriefDescription": "VLW Received",
-        "Counter": "0,1",
         "EventCode": "0x42",
         "EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
         "PerPkg": "1",
@@ -1334,7 +1214,6 @@
     },
     {
         "BriefDescription": "VLW Received",
-        "Counter": "0,1",
         "EventCode": "0x42",
         "EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
         "PerPkg": "1",
@@ -1344,7 +1223,6 @@
     },
     {
         "BriefDescription": "VLW Received",
-        "Counter": "0,1",
         "EventCode": "0x42",
         "EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
         "PerPkg": "1",
@@ -1354,7 +1232,6 @@
     },
     {
         "BriefDescription": "Filter Match",
-        "Counter": "0,1",
         "EventCode": "0x41",
         "EventName": "UNC_U_FILTER_MATCH.DISABLE",
         "PerPkg": "1",
@@ -1364,7 +1241,6 @@
     },
     {
         "BriefDescription": "Filter Match",
-        "Counter": "0,1",
         "EventCode": "0x41",
         "EventName": "UNC_U_FILTER_MATCH.ENABLE",
         "PerPkg": "1",
@@ -1374,7 +1250,6 @@
     },
     {
         "BriefDescription": "Filter Match",
-        "Counter": "0,1",
         "EventCode": "0x41",
         "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
         "PerPkg": "1",
@@ -1384,7 +1259,6 @@
     },
     {
         "BriefDescription": "Filter Match",
-        "Counter": "0,1",
         "EventCode": "0x41",
         "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE",
         "PerPkg": "1",
@@ -1394,7 +1268,6 @@
     },
     {
         "BriefDescription": "IDI Lock/SplitLock Cycles",
-        "Counter": "0,1",
         "EventCode": "0x44",
         "EventName": "UNC_U_LOCK_CYCLES",
         "PerPkg": "1",
@@ -1403,10 +1276,8 @@
     },
     {
         "BriefDescription": "MsgCh Requests by Size; 4B Requests",
-        "Counter": "0,1",
         "EventCode": "0x47",
         "EventName": "UNC_U_MSG_CHNL_SIZE_COUNT.4B",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of transactions on the message channel filtered by request size.  This includes both reads and writes.",
         "UMask": "0x1",
@@ -1414,10 +1285,8 @@
     },
     {
         "BriefDescription": "MsgCh Requests by Size; 8B Requests",
-        "Counter": "0,1",
         "EventCode": "0x47",
         "EventName": "UNC_U_MSG_CHNL_SIZE_COUNT.8B",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of transactions on the message channel filtered by request size.  This includes both reads and writes.",
         "UMask": "0x2",
@@ -1425,10 +1294,8 @@
     },
     {
         "BriefDescription": "Cycles PHOLD Assert to Ack; ACK to Deassert",
-        "Counter": "0,1",
         "EventCode": "0x45",
         "EventName": "UNC_U_PHOLD_CYCLES.ACK_TO_DEASSERT",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "PHOLD cycles.  Filter from source CoreID.",
         "UMask": "0x2",
@@ -1436,10 +1303,8 @@
     },
     {
         "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
-        "Counter": "0,1",
         "EventCode": "0x45",
         "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "PHOLD cycles.  Filter from source CoreID.",
         "UMask": "0x1",
@@ -1447,17 +1312,14 @@
     },
     {
         "BriefDescription": "RACU Request",
-        "Counter": "0,1",
         "EventCode": "0x46",
         "EventName": "UNC_U_RACU_REQUESTS.COUNT",
-        "ExtSel": "1",
         "PerPkg": "1",
         "UMask": "0x1",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.CMC",
         "PerPkg": "1",
@@ -1467,7 +1329,6 @@
     },
     {
         "BriefDescription": "Monitor Sent to T0; Livelock",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.LIVELOCK",
         "PerPkg": "1",
@@ -1477,7 +1338,6 @@
     },
     {
         "BriefDescription": "Monitor Sent to T0; LTError",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.LTERROR",
         "PerPkg": "1",
@@ -1487,7 +1347,6 @@
     },
     {
         "BriefDescription": "Monitor Sent to T0; Monitor T0",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
         "PerPkg": "1",
@@ -1497,7 +1356,6 @@
     },
     {
         "BriefDescription": "Monitor Sent to T0; Monitor T1",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
         "PerPkg": "1",
@@ -1507,7 +1365,6 @@
     },
     {
         "BriefDescription": "Monitor Sent to T0; Other",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.OTHER",
         "PerPkg": "1",
@@ -1517,7 +1374,6 @@
     },
     {
         "BriefDescription": "Monitor Sent to T0; Trap",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.TRAP",
         "PerPkg": "1",
@@ -1527,7 +1383,6 @@
     },
     {
         "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "UNC_U_U2C_EVENTS.UMC",
         "PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json
index 817ea6d7f7851..638aa8a35cdb8 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "pclk Cycles",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_P_CLOCKTICKS",
         "PerPkg": "1",
         "PublicDescription": "The PCU runs off a fixed 800 MHz clock.  This event counts the number of pclk cycles measured while the counter was enabled.  The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
@@ -9,87 +8,70 @@
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_P_CORE0_TRANSITION_CYCLES",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_P_CORE1_TRANSITION_CYCLES",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_P_CORE2_TRANSITION_CYCLES",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_P_CORE3_TRANSITION_CYCLES",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_P_CORE4_TRANSITION_CYCLES",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_P_CORE5_TRANSITION_CYCLES",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_P_CORE6_TRANSITION_CYCLES",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xa",
         "EventName": "UNC_P_CORE7_TRANSITION_CYCLES",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of cycles spent performing core C state transitions.  There is one event per core.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1e",
         "EventName": "UNC_P_DEMOTIONS_CORE0",
         "PerPkg": "1",
@@ -98,7 +80,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1f",
         "EventName": "UNC_P_DEMOTIONS_CORE1",
         "PerPkg": "1",
@@ -107,7 +88,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "UNC_P_DEMOTIONS_CORE2",
         "PerPkg": "1",
@@ -116,7 +96,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_P_DEMOTIONS_CORE3",
         "PerPkg": "1",
@@ -125,7 +104,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_P_DEMOTIONS_CORE4",
         "PerPkg": "1",
@@ -134,7 +112,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x23",
         "EventName": "UNC_P_DEMOTIONS_CORE5",
         "PerPkg": "1",
@@ -143,7 +120,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_P_DEMOTIONS_CORE6",
         "PerPkg": "1",
@@ -152,7 +128,6 @@
     },
     {
         "BriefDescription": "Core C State Demotions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x25",
         "EventName": "UNC_P_DEMOTIONS_CORE7",
         "PerPkg": "1",
@@ -161,7 +136,6 @@
     },
     {
         "BriefDescription": "Frequency Residency",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb",
         "EventName": "UNC_P_FREQ_BAND0_CYCLES",
         "PerPkg": "1",
@@ -170,7 +144,6 @@
     },
     {
         "BriefDescription": "Frequency Residency",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc",
         "EventName": "UNC_P_FREQ_BAND1_CYCLES",
         "PerPkg": "1",
@@ -179,7 +152,6 @@
     },
     {
         "BriefDescription": "Frequency Residency",
-        "Counter": "0,1,2,3",
         "EventCode": "0xd",
         "EventName": "UNC_P_FREQ_BAND2_CYCLES",
         "PerPkg": "1",
@@ -188,7 +160,6 @@
     },
     {
         "BriefDescription": "Frequency Residency",
-        "Counter": "0,1,2,3",
         "EventCode": "0xe",
         "EventName": "UNC_P_FREQ_BAND3_CYCLES",
         "PerPkg": "1",
@@ -197,7 +168,6 @@
     },
     {
         "BriefDescription": "Current Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_P_FREQ_MAX_CURRENT_CYCLES",
         "PerPkg": "1",
@@ -206,7 +176,6 @@
     },
     {
         "BriefDescription": "Thermal Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
         "PerPkg": "1",
@@ -215,7 +184,6 @@
     },
     {
         "BriefDescription": "OS Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_P_FREQ_MAX_OS_CYCLES",
         "PerPkg": "1",
@@ -224,7 +192,6 @@
     },
     {
         "BriefDescription": "Power Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
         "PerPkg": "1",
@@ -233,36 +200,29 @@
     },
     {
         "BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower.  This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW.  This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Perf P Limit Strongest Lower Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_P_FREQ_MIN_PERF_P_CYCLES",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles when Perf P Limit is preventing us from dropping the frequency lower.  Perf P Limit is an algorithm that takes input from remote sockets when determining if a socket should drop it's frequency down.  This is largely to minimize increases in snoop and remote read latencies.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Cycles spent changing Frequency",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_P_FREQ_TRANS_CYCLES",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Counts the number of cycles when the system is changing frequency.  This can not be filtered by thread ID.  One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Memory Phase Shedding Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2f",
         "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
         "PerPkg": "1",
@@ -271,7 +231,6 @@
     },
     {
         "BriefDescription": "Number of cores in C0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
         "PerPkg": "1",
@@ -280,7 +239,6 @@
     },
     {
         "BriefDescription": "Number of cores in C0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
         "PerPkg": "1",
@@ -289,7 +247,6 @@
     },
     {
         "BriefDescription": "Number of cores in C0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
         "PerPkg": "1",
@@ -298,7 +255,6 @@
     },
     {
         "BriefDescription": "External Prochot",
-        "Counter": "0,1,2,3",
         "EventCode": "0xa",
         "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
         "PerPkg": "1",
@@ -307,7 +263,6 @@
     },
     {
         "BriefDescription": "Internal Prochot",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
         "PerPkg": "1",
@@ -316,17 +271,14 @@
     },
     {
         "BriefDescription": "Total Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb",
         "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
-        "ExtSel": "1",
         "PerPkg": "1",
         "PublicDescription": "Number of cycles spent performing core C state transitions across all cores.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Cycles Changing Voltage",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "UNC_P_VOLT_TRANS_CYCLES_CHANGE",
         "PerPkg": "1",
@@ -335,7 +287,6 @@
     },
     {
         "BriefDescription": "Cycles Decreasing Voltage",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_P_VOLT_TRANS_CYCLES_DECREASE",
         "PerPkg": "1",
@@ -344,7 +295,6 @@
     },
     {
         "BriefDescription": "Cycles Increasing Voltage",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1",
         "EventName": "UNC_P_VOLT_TRANS_CYCLES_INCREASE",
         "PerPkg": "1",
@@ -353,7 +303,6 @@
     },
     {
         "BriefDescription": "VR Hot",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "UNC_P_VR_HOT_CYCLES",
         "PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json b/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json
index 98362abba1a7d..fa08d355b97e6 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Load misses in all DTLB levels that cause page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
         "SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
     },
     {
         "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
         "PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.",
@@ -20,8 +16,6 @@
     },
     {
         "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "100003",
@@ -29,8 +23,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
         "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
@@ -39,8 +31,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
         "SampleAfterValue": "100003",
@@ -48,8 +38,6 @@
     },
     {
         "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT",
         "SampleAfterValue": "100003",
@@ -57,8 +45,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "100003",
@@ -66,8 +52,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_DURATION",
         "SampleAfterValue": "2000003",
@@ -75,8 +59,6 @@
     },
     {
         "BriefDescription": "Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4F",
         "EventName": "EPT.WALK_CYCLES",
         "SampleAfterValue": "2000003",
@@ -84,8 +66,6 @@
     },
     {
         "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAE",
         "EventName": "ITLB.ITLB_FLUSH",
         "SampleAfterValue": "100007",
@@ -93,8 +73,6 @@
     },
     {
         "BriefDescription": "Misses at all ITLB levels that cause page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
         "SampleAfterValue": "100003",
@@ -102,8 +80,6 @@
     },
     {
         "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT",
         "SampleAfterValue": "100003",
@@ -111,8 +87,6 @@
     },
     {
         "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "100003",
@@ -120,8 +94,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_DURATION",
         "PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
@@ -130,8 +102,6 @@
     },
     {
         "BriefDescription": "DTLB flush attempts of the thread-specific entries.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.DTLB_THREAD",
         "SampleAfterValue": "100007",
@@ -139,8 +109,6 @@
     },
     {
         "BriefDescription": "STLB flush attempts.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.STLB_ANY",
         "SampleAfterValue": "100007",
-- 
GitLab


From 2c3fd22bb3ff166a072c083e6b7468259c37e46a Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:54:57 -0800
Subject: [PATCH 581/875] perf vendor events intel: Refresh knightslanding
 events

Update the knightslanding events using the new tooling from:

  https://github.com/intel/perfmon

The events are unchanged but unused json values are removed. This
increases consistency across the json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-11-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../arch/x86/knightslanding/cache.json        |  411 -------
 .../x86/knightslanding/floating-point.json    |    3 -
 .../arch/x86/knightslanding/frontend.json     |    7 -
 .../arch/x86/knightslanding/memory.json       |  201 ----
 .../arch/x86/knightslanding/pipeline.json     |   44 -
 .../arch/x86/knightslanding/uncore-other.json | 1016 +++++------------
 .../x86/knightslanding/virtual-memory.json    |    7 -
 7 files changed, 287 insertions(+), 1402 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/cache.json b/tools/perf/pmu-events/arch/x86/knightslanding/cache.json
index 5e10eabda300e..01aea3d2832e5 100644
--- a/tools/perf/pmu-events/arch/x86/knightslanding/cache.json
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/cache.json
@@ -1,14 +1,12 @@
 [
     {
         "BriefDescription": "Counts the number of MEC requests that were not accepted into the L2Q because of any L2  queue reject condition. There is no concept of at-ret here. It might include requests due to instructions in the speculative path.",
-        "Counter": "0,1",
         "EventCode": "0x31",
         "EventName": "CORE_REJECT_L2Q.ALL",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Counts the number of core cycles the fetch stalls because of an icache miss. This is a cummulative count of core cycles the fetch stalled for all icache misses.",
-        "Counter": "0,1",
         "EventCode": "0x86",
         "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES",
         "PublicDescription": "This event counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses.",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "Counts the number of L2 cache misses",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_REQUESTS.MISS",
         "SampleAfterValue": "200003",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "Counts the total number of L2 cache references.",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_REQUESTS.REFERENCE",
         "SampleAfterValue": "200003",
@@ -33,14 +29,12 @@
     },
     {
         "BriefDescription": "Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) exlcuding SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REQUESTS_REJECT.ALL",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Counts all the load micro-ops retired",
-        "Counter": "0,1",
         "EventCode": "0x04",
         "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
         "PublicDescription": "This event counts the number of load micro-ops retired.",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "Counts all the store micro-ops retired",
-        "Counter": "0,1",
         "EventCode": "0x04",
         "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
         "PublicDescription": "This event counts the number of store micro-ops retired.",
@@ -58,7 +51,6 @@
     },
     {
         "BriefDescription": "Counts the loads retired that get the data from the other core in the same tile in M state",
-        "Counter": "0,1",
         "Data_LA": "1",
         "EventCode": "0x04",
         "EventName": "MEM_UOPS_RETIRED.HITM",
@@ -68,7 +60,6 @@
     },
     {
         "BriefDescription": "Counts the number of load micro-ops retired that miss in L1 D cache",
-        "Counter": "0,1",
         "EventCode": "0x04",
         "EventName": "MEM_UOPS_RETIRED.L1_MISS_LOADS",
         "PublicDescription": "This event counts the number of load micro-ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted.",
@@ -77,7 +68,6 @@
     },
     {
         "BriefDescription": "Counts the number of load micro-ops retired that hit in the L2",
-        "Counter": "0,1",
         "Data_LA": "1",
         "EventCode": "0x04",
         "EventName": "MEM_UOPS_RETIRED.L2_HIT_LOADS",
@@ -87,7 +77,6 @@
     },
     {
         "BriefDescription": "Counts the number of load micro-ops retired that miss in the L2",
-        "Counter": "0,1",
         "Data_LA": "1",
         "EventCode": "0x04",
         "EventName": "MEM_UOPS_RETIRED.L2_MISS_LOADS",
@@ -97,7 +86,6 @@
     },
     {
         "BriefDescription": "Counts the number of load micro-ops retired that caused micro TLB miss",
-        "Counter": "0,1",
         "EventCode": "0x04",
         "EventName": "MEM_UOPS_RETIRED.UTLB_MISS_LOADS",
         "SampleAfterValue": "200003",
@@ -105,7 +93,6 @@
     },
     {
         "BriefDescription": "Counts the matrix events specified by MSR_OFFCORE_RESPx",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE",
         "SampleAfterValue": "100007",
@@ -113,2190 +100,1792 @@
     },
     {
         "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for any response",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010044",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800400044",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800400044",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000400044",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800180044",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800080044",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080044",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for responses which hit its own tile's L2 with data in E state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_E",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0004000044",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for responses which hit its own tile's L2 with data in F state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0010000044",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for responses which hit its own tile's L2 with data in M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0002000044",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for responses which hit its own tile's L2 with data in S state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_S",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0008000044",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand code reads and prefetch code read requests  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000044",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for any response",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000013091",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800403091",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800403091",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000403091",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800183091",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800083091",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000083091",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses which hit its own tile's L2 with data in E state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_E",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0004003091",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses which hit its own tile's L2 with data in F state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0010003091",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses which hit its own tile's L2 with data in M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0002003091",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses which hit its own tile's L2 with data in S state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_S",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0008003091",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000003091",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Prefetch requests that accounts for any response",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010070",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800400070",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800400070",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000400070",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800180070",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800080070",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080070",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in E state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_E",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0004000070",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in F state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0010000070",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0002000070",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000070",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Read request  that accounts for any response",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00000132f7",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Read request  that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x18004032f7",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Read request  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x08004032f7",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Read request  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10004032f7",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Read request  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x18001832f7",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Read request  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x08000832f7",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Read request  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10000832f7",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Read request  that accounts for responses which hit its own tile's L2 with data in E state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_E",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00040032f7",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Read request  that accounts for responses which hit its own tile's L2 with data in F state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00100032f7",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Read request  that accounts for responses which hit its own tile's L2 with data in M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00020032f7",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Read request  that accounts for responses which hit its own tile's L2 with data in S state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_S",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00080032f7",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Read request  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x40000032f7",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any request that accounts for any response",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000018000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any request that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800408000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800408000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000408000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any request that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800188000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800088000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000088000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in E state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_E",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0004008000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in F state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0010008000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0002008000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in S state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_S",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0008008000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000008000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data write requests  that accounts for any response",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010022",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data write requests  that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800400022",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data write requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800400022",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data write requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000400022",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data write requests  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800180022",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data write requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800080022",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data write requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080022",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data write requests  that accounts for responses which hit its own tile's L2 with data in E state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_E",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0004000022",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data write requests  that accounts for responses which hit its own tile's L2 with data in F state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0010000022",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data write requests  that accounts for responses which hit its own tile's L2 with data in M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0002000022",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data write requests  that accounts for responses which hit its own tile's L2 with data in S state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_S",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0008000022",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data write requests  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000022",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Bus locks and split lock requests that accounts for any response",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010400",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800400400",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800400400",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000400400",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800180400",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800080400",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080400",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in E state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_E",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0004000400",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in F state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0010000400",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0002000400",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in S state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_S",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0008000400",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000400",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for any response",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010004",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800400004",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800400004",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000400004",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800180004",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800080004",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080004",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in E state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_E",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0004000004",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in F state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0010000004",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0002000004",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in S state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_S",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0008000004",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000004",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for any response",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010001",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_FAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800400001",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_FAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000400001",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_NEAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800080001",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_NEAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080001",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in E state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_E",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0004000001",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in F state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0010000001",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0002000001",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in S state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_S",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0008000001",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000001",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data writes that accounts for any response",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010002",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800400002",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800400002",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000400002",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800180002",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800080002",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080002",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in E state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_E",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0004000002",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in F state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0010000002",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0002000002",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in S state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_S",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0008000002",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000002",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Full streaming stores (WC and should be programmed on PMC1) that accounts for any response",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010800",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for any response",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010080",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800400080",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800400080",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000400080",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800180080",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800080080",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080080",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses which hit its own tile's L2 with data in E state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_E",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0004000080",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses which hit its own tile's L2 with data in F state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0010000080",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses which hit its own tile's L2 with data in M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0002000080",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses which hit its own tile's L2 with data in S state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_S",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0008000080",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000080",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial streaming stores (WC and should be programmed on PMC1) that accounts for any response",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.ANY_RESPONSE",
         "MSRIndex": "0x1a7",
         "MSRValue": "0x0000014000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for any response",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.ANY_RESPONSE",
         "MSRIndex": "0x1a7",
         "MSRValue": "0x0000010100",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE",
         "MSRIndex": "0x1a7",
         "MSRValue": "0x1800400100",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE_E_F",
         "MSRIndex": "0x1a7",
         "MSRValue": "0x0800400100",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE_M",
         "MSRIndex": "0x1a7",
         "MSRValue": "0x1000400100",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE",
         "MSRIndex": "0x1a7",
         "MSRValue": "0x1800180100",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE_E_F",
         "MSRIndex": "0x1a7",
         "MSRValue": "0x0800080100",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE_M",
         "MSRIndex": "0x1a7",
         "MSRValue": "0x1000080100",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in E state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_E",
         "MSRIndex": "0x1a7",
         "MSRValue": "0x0004000100",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in F state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_F",
         "MSRIndex": "0x1a7",
         "MSRValue": "0x0010000100",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_M",
         "MSRIndex": "0x1a7",
         "MSRValue": "0x0002000100",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in S state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_S",
         "MSRIndex": "0x1a7",
         "MSRValue": "0x0008000100",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data HW prefetches that accounts for any response",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000012000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800402000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800402000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000402000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800182000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800082000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000082000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in E state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_E",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0004002000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in F state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0010002000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0002002000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in S state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_S",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0008002000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000002000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 code HW prefetches that accounts for any response",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010040",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800400040",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800400040",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000400040",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800180040",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800080040",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080040",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in E state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_THIS_TILE_E",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0004000040",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in F state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_THIS_TILE_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0010000040",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000040",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for any response",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010020",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_FAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800400020",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_FAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000400020",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800180020",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800080020",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080020",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in E state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_E",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0004000020",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in F state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0010000020",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0002000020",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in S state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_S",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0008000020",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that provides no supplier details",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000020020",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Software Prefetches that accounts for any response",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000011000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800401000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800401000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000401000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800181000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800081000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000081000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in E state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_E",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0004001000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in F state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0010001000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0002001000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in S state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_S",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0008001000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000001000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all streaming stores (WC and should be programmed on PMC1) that accounts for any response",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
         "MSRIndex": "0x1a7",
         "MSRValue": "0x0000014800",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for any response",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010200",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_FAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800400200",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_FAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000400200",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1800180200",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE_E_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0800080200",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080200",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for responses which hit its own tile's L2 with data in E state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_E",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0004000200",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for responses which hit its own tile's L2 with data in F state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_F",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0010000200",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for responses which hit its own tile's L2 with data in M state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0002000200",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for responses which hit its own tile's L2 with data in S state",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_S",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0008000200",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000200",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     }
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json b/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json
index ff5db600e420b..ecc96f32f167b 100644
--- a/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Counts the number of floating operations retired that required microcode assists",
-        "Counter": "0,1",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.FP_ASSIST",
         "PublicDescription": "This event counts the number of times that the pipeline stalled due to FP operations needing assists.",
@@ -10,7 +9,6 @@
     },
     {
         "BriefDescription": "Counts the number of vector SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.",
-        "Counter": "0,1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.PACKED_SIMD",
         "PublicDescription": "This event counts the number of packed vector SSE, AVX, AVX2, and AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.",
@@ -19,7 +17,6 @@
     },
     {
         "BriefDescription": "Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt.",
-        "Counter": "0,1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.SCALAR_SIMD",
         "PublicDescription": "This event counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro ops), division, sqrt.",
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json b/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json
index 63343a0d1e860..9001f5019848f 100644
--- a/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end.",
-        "Counter": "0,1",
         "EventCode": "0xE6",
         "EventName": "BACLEARS.ALL",
         "SampleAfterValue": "200003",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end.",
-        "Counter": "0,1",
         "EventCode": "0xE6",
         "EventName": "BACLEARS.COND",
         "SampleAfterValue": "200003",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end.",
-        "Counter": "0,1",
         "EventCode": "0xE6",
         "EventName": "BACLEARS.RETURN",
         "SampleAfterValue": "200003",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "Counts all instruction fetches, including uncacheable fetches.",
-        "Counter": "0,1",
         "EventCode": "0x80",
         "EventName": "ICACHE.ACCESSES",
         "SampleAfterValue": "200003",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "Counts all instruction fetches that hit the instruction cache.",
-        "Counter": "0,1",
         "EventCode": "0x80",
         "EventName": "ICACHE.HIT",
         "SampleAfterValue": "200003",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.",
-        "Counter": "0,1",
         "EventCode": "0x80",
         "EventName": "ICACHE.MISSES",
         "SampleAfterValue": "200003",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "Counts the number of times the MSROM starts a flow of uops.",
-        "Counter": "0,1",
         "EventCode": "0xE7",
         "EventName": "MS_DECODED.MS_ENTRY",
         "SampleAfterValue": "200003",
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/memory.json b/tools/perf/pmu-events/arch/x86/knightslanding/memory.json
index 2611defaeaa21..b0361f6f0dd9e 100644
--- a/tools/perf/pmu-events/arch/x86/knightslanding/memory.json
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/memory.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Counts the number of times the machine clears due to memory ordering hazards",
-        "Counter": "0,1",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
         "SampleAfterValue": "200003",
@@ -9,1101 +8,901 @@
     },
     {
         "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for responses from DDR (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0181800044",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for data responses from DRAM Far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0101000044",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for data responses from DRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080800044",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for responses from MCDRAM (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0180600044",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100400044",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for data responses from MCDRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080200044",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from DDR (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0181803091",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from DRAM Far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0101003091",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from DRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080803091",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from MCDRAM (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0180603091",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100403091",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from MCDRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080203091",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0101000070",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080800070",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Prefetch requests that accounts for responses from MCDRAM (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0180600070",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100400070",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080200070",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Read request  that accounts for responses from DDR (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x01818032f7",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Read request  that accounts for data responses from DRAM Far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x01010032f7",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Read request  that accounts for data responses from DRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00808032f7",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Read request  that accounts for responses from MCDRAM (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x01806032f7",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Read request  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x01004032f7",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any Read request  that accounts for data responses from MCDRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00802032f7",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any request that accounts for responses from DDR (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0181808000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any request that accounts for data responses from DRAM Far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0101008000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any request that accounts for data responses from DRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080808000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any request that accounts for responses from MCDRAM (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0180608000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100408000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any request that accounts for data responses from MCDRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080208000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data write requests  that accounts for responses from DDR (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0181800022",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data write requests  that accounts for data responses from DRAM Far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0101000022",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data write requests  that accounts for data responses from DRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080800022",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data write requests  that accounts for responses from MCDRAM (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0180600022",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data write requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100400022",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data write requests  that accounts for data responses from MCDRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080200022",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from DDR (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0181800400",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0101000400",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080800400",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from MCDRAM (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0180600400",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100400400",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080200400",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from DDR (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0181800004",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0101000004",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080800004",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from MCDRAM (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0180600004",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100400004",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080200004",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from DDR (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0181800001",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0101000001",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080800001",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from MCDRAM (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0180600001",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100400001",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080200001",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from DDR (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0181800002",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0101000002",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080800002",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from MCDRAM (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0180600002",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100400002",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080200002",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from DDR (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0181800080",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from DRAM Far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0101000080",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from DRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080800080",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from MCDRAM (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0180600080",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100400080",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from MCDRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080200080",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from any NON_DRAM system address. This includes MMIO transactions",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000020080",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_FAR",
         "MSRIndex": "0x1a7",
         "MSRValue": "0x0101000100",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_NEAR",
         "MSRIndex": "0x1a7",
         "MSRValue": "0x0080800100",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from MCDRAM (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM",
         "MSRIndex": "0x1a7",
         "MSRValue": "0x0180600100",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_FAR",
         "MSRIndex": "0x1a7",
         "MSRValue": "0x0100400100",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_NEAR",
         "MSRIndex": "0x1a7",
         "MSRValue": "0x0080200100",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from DDR (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0181802000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0101002000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080802000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100402000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080202000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from DDR (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0181800040",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0101000040",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080800040",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100400040",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080200040",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from DDR (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0181800020",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0101000020",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080800020",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from MCDRAM (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0180600020",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100400020",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080200020",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from any NON_DRAM system address. This includes MMIO transactions",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000020020",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Software Prefetches that accounts for responses from DDR (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0181801000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0101001000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080801000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Software Prefetches that accounts for responses from MCDRAM (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0180601000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100401000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080201000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from DDR (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0181800200",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from DRAM Far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0101000200",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from DRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080800200",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from MCDRAM (local and far)",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0180600200",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_FAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0100400200",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from MCDRAM Local.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_NEAR",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080200200",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     }
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json b/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json
index 1f13bc2686cb3..1b803fa386415 100644
--- a/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Counts the number of branch instructions retired",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Counts the number of near CALL branch instructions retired.",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.CALL",
         "PEBS": "1",
@@ -18,7 +16,6 @@
     },
     {
         "BriefDescription": "Counts the number of far branch instructions retired.",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.FAR_BRANCH",
         "PEBS": "1",
@@ -27,7 +24,6 @@
     },
     {
         "BriefDescription": "Counts the number of near indirect CALL branch instructions retired.",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.IND_CALL",
         "PEBS": "1",
@@ -36,7 +32,6 @@
     },
     {
         "BriefDescription": "Counts the number of branch instructions retired that were conditional jumps.",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.JCC",
         "PEBS": "1",
@@ -45,7 +40,6 @@
     },
     {
         "BriefDescription": "Counts the number of branch instructions retired that were near indirect CALL or near indirect JMP.",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NON_RETURN_IND",
         "PEBS": "1",
@@ -54,7 +48,6 @@
     },
     {
         "BriefDescription": "Counts the number of near relative CALL branch instructions retired.",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.REL_CALL",
         "PEBS": "1",
@@ -63,7 +56,6 @@
     },
     {
         "BriefDescription": "Counts the number of near RET branch instructions retired.",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.RETURN",
         "PEBS": "1",
@@ -72,7 +64,6 @@
     },
     {
         "BriefDescription": "Counts the number of branch instructions retired that were conditional jumps and predicted taken.",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.TAKEN_JCC",
         "PEBS": "1",
@@ -81,7 +72,6 @@
     },
     {
         "BriefDescription": "Counts the number of mispredicted branch instructions retired",
-        "Counter": "0,1",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
@@ -89,7 +79,6 @@
     },
     {
         "BriefDescription": "Counts the number of mispredicted near CALL branch instructions retired.",
-        "Counter": "0,1",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.CALL",
         "PEBS": "1",
@@ -98,7 +87,6 @@
     },
     {
         "BriefDescription": "Counts the number of mispredicted far branch instructions retired.",
-        "Counter": "0,1",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.FAR_BRANCH",
         "PEBS": "1",
@@ -107,7 +95,6 @@
     },
     {
         "BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.",
-        "Counter": "0,1",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.IND_CALL",
         "PEBS": "1",
@@ -116,7 +103,6 @@
     },
     {
         "BriefDescription": "Counts the number of mispredicted branch instructions retired that were conditional jumps.",
-        "Counter": "0,1",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.JCC",
         "PEBS": "1",
@@ -125,7 +111,6 @@
     },
     {
         "BriefDescription": "Counts the number of mispredicted branch instructions retired that were near indirect CALL or near indirect JMP.",
-        "Counter": "0,1",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
         "PEBS": "1",
@@ -134,7 +119,6 @@
     },
     {
         "BriefDescription": "Counts the number of mispredicted near relative CALL branch instructions retired.",
-        "Counter": "0,1",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.REL_CALL",
         "PEBS": "1",
@@ -143,7 +127,6 @@
     },
     {
         "BriefDescription": "Counts the number of mispredicted near RET branch instructions retired.",
-        "Counter": "0,1",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.RETURN",
         "PEBS": "1",
@@ -152,7 +135,6 @@
     },
     {
         "BriefDescription": "Counts the number of mispredicted branch instructions retired that were conditional jumps and predicted taken.",
-        "Counter": "0,1",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.TAKEN_JCC",
         "PEBS": "1",
@@ -161,7 +143,6 @@
     },
     {
         "BriefDescription": "Counts the number of unhalted reference clock cycles",
-        "Counter": "0,1",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF",
         "SampleAfterValue": "2000003",
@@ -169,14 +150,12 @@
     },
     {
         "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
-        "Counter": "Fixed counter 3",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
         "SampleAfterValue": "2000003",
         "UMask": "0x3"
     },
     {
         "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
-        "Counter": "Fixed counter 2",
         "EventName": "CPU_CLK_UNHALTED.THREAD",
         "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter",
         "SampleAfterValue": "2000003",
@@ -184,14 +163,12 @@
     },
     {
         "BriefDescription": "Counts the number of unhalted core clock cycles",
-        "Counter": "0,1",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Cycles the number of core cycles when divider is busy.  Does not imply a stall waiting for the divider.",
-        "Counter": "0,1",
         "EventCode": "0xCD",
         "EventName": "CYCLES_DIV_BUSY.ALL",
         "PublicDescription": "This event counts cycles when the divider is busy. More specifically cycles when the divide unit is unable to accept a new divide uop because it is busy processing a previously dispatched uop. The cycles will be counted irrespective of whether or not another divide uop is waiting to enter the divide unit (from the RS). This event counts integer divides, x87 divides, divss, divsd, sqrtss, sqrtsd event and does not count vector divides.",
@@ -200,7 +177,6 @@
     },
     {
         "BriefDescription": "Fixed Counter: Counts the number of instructions retired",
-        "Counter": "Fixed counter 1",
         "EventName": "INST_RETIRED.ANY",
         "PublicDescription": "This event counts the number of instructions that retire.  For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires.  The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps.",
         "SampleAfterValue": "2000003",
@@ -208,14 +184,12 @@
     },
     {
         "BriefDescription": "Counts the total number of instructions retired",
-        "Counter": "0,1",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.ANY_P",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Counts all nukes",
-        "Counter": "0,1",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.ALL",
         "SampleAfterValue": "200003",
@@ -223,7 +197,6 @@
     },
     {
         "BriefDescription": "Counts the number of times that the machine clears due to program modifying data within 1K of a recently fetched code page",
-        "Counter": "0,1",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.SMC",
         "SampleAfterValue": "200003",
@@ -231,7 +204,6 @@
     },
     {
         "BriefDescription": "Counts the total number of core cycles when no micro-ops are allocated for any reason.",
-        "Counter": "0,1",
         "EventCode": "0xCA",
         "EventName": "NO_ALLOC_CYCLES.ALL",
         "SampleAfterValue": "200003",
@@ -239,7 +211,6 @@
     },
     {
         "BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire.",
-        "Counter": "0,1",
         "EventCode": "0xCA",
         "EventName": "NO_ALLOC_CYCLES.MISPREDICTS",
         "PublicDescription": "This event counts the number of core cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire.",
@@ -248,7 +219,6 @@
     },
     {
         "BriefDescription": "Counts the number of core cycles when no micro-ops are allocated, the IQ is empty, and no other condition is blocking allocation.",
-        "Counter": "0,1",
         "EventCode": "0xCA",
         "EventName": "NO_ALLOC_CYCLES.NOT_DELIVERED",
         "PublicDescription": "This event counts the number of core cycles when no uops are allocated, the instruction queue is empty and the alloc pipe is stalled waiting for instructions to be fetched.",
@@ -257,7 +227,6 @@
     },
     {
         "BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and a RATstall (caused by reservation station full) is asserted.",
-        "Counter": "0,1",
         "EventCode": "0xCA",
         "EventName": "NO_ALLOC_CYCLES.RAT_STALL",
         "SampleAfterValue": "200003",
@@ -265,7 +234,6 @@
     },
     {
         "BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and the ROB is full",
-        "Counter": "0,1",
         "EventCode": "0xCA",
         "EventName": "NO_ALLOC_CYCLES.ROB_FULL",
         "SampleAfterValue": "200003",
@@ -273,7 +241,6 @@
     },
     {
         "BriefDescription": "Counts any retired load that was pushed into the recycle queue for any reason.",
-        "Counter": "0,1",
         "EventCode": "0x03",
         "EventName": "RECYCLEQ.ANY_LD",
         "SampleAfterValue": "200003",
@@ -281,7 +248,6 @@
     },
     {
         "BriefDescription": "Counts any retired store that was pushed into the recycle queue for any reason.",
-        "Counter": "0,1",
         "EventCode": "0x03",
         "EventName": "RECYCLEQ.ANY_ST",
         "SampleAfterValue": "200003",
@@ -289,7 +255,6 @@
     },
     {
         "BriefDescription": "Counts the number of occurences a retired load gets blocked because its address overlaps with a store whose data is not ready",
-        "Counter": "0,1",
         "EventCode": "0x03",
         "EventName": "RECYCLEQ.LD_BLOCK_STD_NOTREADY",
         "SampleAfterValue": "200003",
@@ -297,7 +262,6 @@
     },
     {
         "BriefDescription": "Counts the number of occurences a retired load gets blocked because its address partially overlaps with a store",
-        "Counter": "0,1",
         "Data_LA": "1",
         "EventCode": "0x03",
         "EventName": "RECYCLEQ.LD_BLOCK_ST_FORWARD",
@@ -307,7 +271,6 @@
     },
     {
         "BriefDescription": "Counts the number of occurences a retired load that is a cache line split. Each split should be counted only once.",
-        "Counter": "0,1",
         "Data_LA": "1",
         "EventCode": "0x03",
         "EventName": "RECYCLEQ.LD_SPLITS",
@@ -317,7 +280,6 @@
     },
     {
         "BriefDescription": "Counts all the retired locked loads. It does not include stores because we would double count if we count stores",
-        "Counter": "0,1",
         "EventCode": "0x03",
         "EventName": "RECYCLEQ.LOCK",
         "SampleAfterValue": "200003",
@@ -325,7 +287,6 @@
     },
     {
         "BriefDescription": "Counts the store micro-ops retired that were pushed in the rehad queue because the store address buffer is full",
-        "Counter": "0,1",
         "EventCode": "0x03",
         "EventName": "RECYCLEQ.STA_FULL",
         "SampleAfterValue": "200003",
@@ -333,7 +294,6 @@
     },
     {
         "BriefDescription": "Counts the number of occurences a retired store that is a cache line split. Each split should be counted only once.",
-        "Counter": "0,1",
         "EventCode": "0x03",
         "EventName": "RECYCLEQ.ST_SPLITS",
         "PublicDescription": "This event counts the number of retired store that experienced a cache line boundary split(Precise Event). Note that each spilt should be counted only once.",
@@ -342,7 +302,6 @@
     },
     {
         "BriefDescription": "Counts the total number of core cycles the Alloc pipeline is stalled when any one of the reservation stations is full.",
-        "Counter": "0,1",
         "EventCode": "0xCB",
         "EventName": "RS_FULL_STALL.ALL",
         "SampleAfterValue": "200003",
@@ -350,7 +309,6 @@
     },
     {
         "BriefDescription": "Counts the number of core cycles when allocation pipeline is stalled and is waiting for a free MEC reservation station entry.",
-        "Counter": "0,1",
         "EventCode": "0xCB",
         "EventName": "RS_FULL_STALL.MEC",
         "SampleAfterValue": "200003",
@@ -358,7 +316,6 @@
     },
     {
         "BriefDescription": "Counts the number of micro-ops retired",
-        "Counter": "0,1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ALL",
         "PublicDescription": "This event counts the number of micro-ops (uops) retired. The processor decodes complex macro instructions into a sequence of simpler uops. Most instructions are composed of one or two uops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists.",
@@ -367,7 +324,6 @@
     },
     {
         "BriefDescription": "Counts the number of micro-ops retired that are from the complex flows issued by the micro-sequencer (MS).",
-        "Counter": "0,1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.MS",
         "PublicDescription": "This event counts the number of micro-ops retired that were supplied from MSROM.",
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json
index a5e1a9a47e730..3abd9c3fdc481 100644
--- a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -IPQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.IPQ_HIT",
         "PerPkg": "1",
@@ -10,7 +9,6 @@
     },
     {
         "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -IPQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.IPQ_MISS",
         "PerPkg": "1",
@@ -19,7 +17,6 @@
     },
     {
         "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -IRQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.IRQ_HIT",
         "PerPkg": "1",
@@ -27,8 +24,7 @@
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -IRQ ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -IRQ",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.IRQ_MISS",
         "PerPkg": "1",
@@ -37,7 +33,6 @@
     },
     {
         "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -IRQ or PRQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.LOC_ALL",
         "PerPkg": "1",
@@ -46,7 +41,6 @@
     },
     {
         "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -PRQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.PRQ_HIT",
         "PerPkg": "1",
@@ -55,7 +49,6 @@
     },
     {
         "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -PRQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_C_TOR_INSERTS.PRQ_MISS",
         "PerPkg": "1",
@@ -64,43 +57,38 @@
     },
     {
         "BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x02",
         "EventName": "UNC_E_EDC_ACCESS.HIT_CLEAN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "EDC_UCLK"
     },
     {
-        "BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode.",
         "EventCode": "0x02",
         "EventName": "UNC_E_EDC_ACCESS.HIT_DIRTY",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "EDC_UCLK"
     },
     {
         "BriefDescription": "Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x02",
         "EventName": "UNC_E_EDC_ACCESS.MISS_CLEAN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "EDC_UCLK"
     },
     {
         "BriefDescription": "Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x02",
         "EventName": "UNC_E_EDC_ACCESS.MISS_DIRTY",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "EDC_UCLK"
     },
     {
         "BriefDescription": "Number of EDC Hits or Misses. Miss I",
-        "Counter": "0,1,2,3",
         "EventCode": "0x02",
         "EventName": "UNC_E_EDC_ACCESS.MISS_INVALID",
         "PerPkg": "1",
@@ -109,75 +97,66 @@
     },
     {
         "BriefDescription": "ECLK count",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_E_E_CLOCKTICKS",
         "PerPkg": "1",
         "Unit": "EDC_ECLK"
     },
     {
-        "BriefDescription": "Counts the number of read requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all read requests as well as streaming stores that hit or miss in the MCDRAM cache. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Counts the number of read requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all read requests as well as streaming stores that hit or miss in the MCDRAM cache.",
         "EventCode": "0x01",
         "EventName": "UNC_E_RPQ_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "EDC_ECLK"
     },
     {
         "BriefDescription": "UCLK count",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_E_U_CLOCKTICKS",
         "PerPkg": "1",
         "Unit": "EDC_UCLK"
     },
     {
         "BriefDescription": "Counts the number of write requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all streaming stores, writebacks and, read requests that miss in MCDRAM cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x02",
         "EventName": "UNC_E_WPQ_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "EDC_ECLK"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
@@ -186,7 +165,6 @@
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
@@ -195,7 +173,6 @@
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR6",
         "PerPkg": "1",
@@ -204,7 +181,6 @@
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR7",
         "PerPkg": "1",
@@ -213,61 +189,54 @@
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 0-7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x81",
         "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0x81",
         "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED_EXT.TGR8",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x82",
         "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x82",
         "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x82",
         "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x82",
         "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0x82",
         "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
@@ -276,7 +245,6 @@
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0x82",
         "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
@@ -285,7 +253,6 @@
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0x82",
         "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR6",
         "PerPkg": "1",
@@ -294,7 +261,6 @@
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x82",
         "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR7",
         "PerPkg": "1",
@@ -303,61 +269,54 @@
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 0-7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY_EXT.TGR8",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
@@ -366,7 +325,6 @@
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
@@ -375,7 +333,6 @@
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR6",
         "PerPkg": "1",
@@ -384,7 +341,6 @@
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR7",
         "PerPkg": "1",
@@ -393,61 +349,54 @@
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 0-7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED_EXT.TGR8",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8A",
         "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8A",
         "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8A",
         "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8A",
         "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8A",
         "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
@@ -456,7 +405,6 @@
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8A",
         "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
@@ -465,7 +413,6 @@
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8A",
         "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR6",
         "PerPkg": "1",
@@ -474,7 +421,6 @@
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8A",
         "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR7",
         "PerPkg": "1",
@@ -483,61 +429,54 @@
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 0-7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8B",
         "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8B",
         "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY_EXT.TGR8",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR4",
         "PerPkg": "1",
@@ -546,7 +485,6 @@
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR5",
         "PerPkg": "1",
@@ -555,7 +493,6 @@
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR6",
         "PerPkg": "1",
@@ -564,7 +501,6 @@
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR7",
         "PerPkg": "1",
@@ -573,61 +509,54 @@
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0-7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.ANY_OF_TGR0_THRU_TGR7",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.TGR8",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD4",
         "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD4",
         "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD4",
         "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD4",
         "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD4",
         "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR4",
         "PerPkg": "1",
@@ -636,7 +565,6 @@
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD4",
         "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR5",
         "PerPkg": "1",
@@ -645,7 +573,6 @@
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD4",
         "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR6",
         "PerPkg": "1",
@@ -654,7 +581,6 @@
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD4",
         "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR7",
         "PerPkg": "1",
@@ -663,61 +589,54 @@
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0-7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD5",
         "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.ANY_OF_TGR0_THRU_TGR7",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD5",
         "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.TGR8",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x84",
         "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x84",
         "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x84",
         "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x84",
         "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0x84",
         "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
@@ -726,7 +645,6 @@
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0x84",
         "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
@@ -735,7 +653,6 @@
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0x84",
         "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR6",
         "PerPkg": "1",
@@ -744,7 +661,6 @@
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x84",
         "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR7",
         "PerPkg": "1",
@@ -753,61 +669,54 @@
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 0-7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED_EXT.TGR8",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x86",
         "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x86",
         "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x86",
         "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x86",
         "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0x86",
         "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
@@ -816,7 +725,6 @@
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0x86",
         "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
@@ -825,7 +733,6 @@
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0x86",
         "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR6",
         "PerPkg": "1",
@@ -834,7 +741,6 @@
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x86",
         "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR7",
         "PerPkg": "1",
@@ -843,61 +749,54 @@
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 0-7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY_EXT.TGR8",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8C",
         "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8C",
         "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8C",
         "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8C",
         "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8C",
         "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
@@ -906,7 +805,6 @@
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8C",
         "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
@@ -915,7 +813,6 @@
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8C",
         "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR6",
         "PerPkg": "1",
@@ -924,7 +821,6 @@
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8C",
         "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR7",
         "PerPkg": "1",
@@ -933,61 +829,54 @@
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 0-7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8D",
         "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8D",
         "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED_EXT.TGR8",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8E",
         "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8E",
         "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8E",
         "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8E",
         "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8E",
         "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
@@ -996,7 +885,6 @@
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8E",
         "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
@@ -1005,7 +893,6 @@
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8E",
         "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR6",
         "PerPkg": "1",
@@ -1014,7 +901,6 @@
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8E",
         "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR7",
         "PerPkg": "1",
@@ -1023,61 +909,54 @@
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 0-7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8F",
         "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8F",
         "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY_EXT.TGR8",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR4",
         "PerPkg": "1",
@@ -1086,7 +965,6 @@
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR5",
         "PerPkg": "1",
@@ -1095,7 +973,6 @@
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR6",
         "PerPkg": "1",
@@ -1104,7 +981,6 @@
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR7",
         "PerPkg": "1",
@@ -1113,61 +989,54 @@
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0-7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD3",
         "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.ANY_OF_TGR0_THRU_TGR7",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD3",
         "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.TGR8",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD6",
         "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD6",
         "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD6",
         "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD6",
         "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD6",
         "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR4",
         "PerPkg": "1",
@@ -1176,7 +1045,6 @@
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD6",
         "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR5",
         "PerPkg": "1",
@@ -1185,7 +1053,6 @@
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD6",
         "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR6",
         "PerPkg": "1",
@@ -1194,7 +1061,6 @@
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD6",
         "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR7",
         "PerPkg": "1",
@@ -1203,43 +1069,38 @@
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0-7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD7",
         "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.ANY_OF_TGR0_THRU_TGR7",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Stall on No AD Transgress Credits For Transgress 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD7",
         "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.TGR8",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Writeback transactions from L2 to the LLC  This includes all write transactions -- both Cachable and UC.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x37",
         "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.E_STATE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Filters for any transaction originating from the IPQ or IRQ.  This does not include lookups originating from the ISMQ.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x37",
         "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.F_STATE",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Lines Victimized that Match NID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x37",
         "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.LOCAL",
         "PerPkg": "1",
@@ -1248,16 +1109,14 @@
     },
     {
         "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Read transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x37",
         "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.M_STATE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Lines Victimized that Does Not Match NID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x37",
         "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.REMOTE",
         "PerPkg": "1",
@@ -1266,16 +1125,14 @@
     },
     {
         "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Filters for only snoop requests coming from the remote socket(s) through the IPQ.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x37",
         "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.S_STATE",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Uncore Clocks",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "UNC_H_CLOCK",
         "PerPkg": "1",
@@ -1283,313 +1140,278 @@
     },
     {
         "BriefDescription": "CMS Horizontal ADS Used",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9D",
         "EventName": "UNC_H_EGRESS_HORZ_ADS_USED.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal ADS Used",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9D",
         "EventName": "UNC_H_EGRESS_HORZ_ADS_USED.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal ADS Used",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9D",
         "EventName": "UNC_H_EGRESS_HORZ_ADS_USED.BL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Bypass. AD ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9F",
         "EventName": "UNC_H_EGRESS_HORZ_BYPASS.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Bypass. AK ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9F",
         "EventName": "UNC_H_EGRESS_HORZ_BYPASS.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Bypass. BL ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9F",
         "EventName": "UNC_H_EGRESS_HORZ_BYPASS.BL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Bypass. IV ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9F",
         "EventName": "UNC_H_EGRESS_HORZ_BYPASS.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full AD",
-        "Counter": "0,1,2,3",
         "EventCode": "0x96",
         "EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full AK",
-        "Counter": "0,1,2,3",
         "EventCode": "0x96",
         "EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full BL",
-        "Counter": "0,1,2,3",
         "EventCode": "0x96",
         "EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.BL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full IV",
-        "Counter": "0,1,2,3",
         "EventCode": "0x96",
         "EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty AD",
-        "Counter": "0,1,2,3",
         "EventCode": "0x97",
         "EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty AK",
-        "Counter": "0,1,2,3",
         "EventCode": "0x97",
         "EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty BL",
-        "Counter": "0,1,2,3",
         "EventCode": "0x97",
         "EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.BL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty IV",
-        "Counter": "0,1,2,3",
         "EventCode": "0x97",
         "EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Inserts AD",
-        "Counter": "0,1,2,3",
         "EventCode": "0x95",
         "EventName": "UNC_H_EGRESS_HORZ_INSERTS.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Inserts AK",
-        "Counter": "0,1,2,3",
         "EventCode": "0x95",
         "EventName": "UNC_H_EGRESS_HORZ_INSERTS.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Inserts BL",
-        "Counter": "0,1,2,3",
         "EventCode": "0x95",
         "EventName": "UNC_H_EGRESS_HORZ_INSERTS.BL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Inserts IV",
-        "Counter": "0,1,2,3",
         "EventCode": "0x95",
         "EventName": "UNC_H_EGRESS_HORZ_INSERTS.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress NACKs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x99",
         "EventName": "UNC_H_EGRESS_HORZ_NACK.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress NACKs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x99",
         "EventName": "UNC_H_EGRESS_HORZ_NACK.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress NACKs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x99",
         "EventName": "UNC_H_EGRESS_HORZ_NACK.BL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress NACKs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x99",
         "EventName": "UNC_H_EGRESS_HORZ_NACK.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Occupancy AD",
-        "Counter": "0,1,2,3",
         "EventCode": "0x94",
         "EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Occupancy AK",
-        "Counter": "0,1,2,3",
         "EventCode": "0x94",
         "EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Occupancy BL",
-        "Counter": "0,1,2,3",
         "EventCode": "0x94",
         "EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.BL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Occupancy IV",
-        "Counter": "0,1,2,3",
         "EventCode": "0x94",
         "EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Injection Starvation",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9B",
         "EventName": "UNC_H_EGRESS_HORZ_STARVED.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Injection Starvation",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9B",
         "EventName": "UNC_H_EGRESS_HORZ_STARVED.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Injection Starvation",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9B",
         "EventName": "UNC_H_EGRESS_HORZ_STARVED.BL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Injection Starvation",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9B",
         "EventName": "UNC_H_EGRESS_HORZ_STARVED.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAE",
         "EventName": "UNC_H_EGRESS_ORDERING.IV_SNP_GO_DN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAE",
         "EventName": "UNC_H_EGRESS_ORDERING.IV_SNP_GO_UP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9C",
         "EventName": "UNC_H_EGRESS_VERT_ADS_USED.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9C",
         "EventName": "UNC_H_EGRESS_VERT_ADS_USED.AD_AG1",
         "PerPkg": "1",
@@ -1598,16 +1420,14 @@
     },
     {
         "BriefDescription": "CMS Vertical ADS Used",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9C",
         "EventName": "UNC_H_EGRESS_VERT_ADS_USED.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9C",
         "EventName": "UNC_H_EGRESS_VERT_ADS_USED.AK_AG1",
         "PerPkg": "1",
@@ -1616,16 +1436,14 @@
     },
     {
         "BriefDescription": "CMS Vertical ADS Used",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9C",
         "EventName": "UNC_H_EGRESS_VERT_ADS_USED.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9C",
         "EventName": "UNC_H_EGRESS_VERT_ADS_USED.BL_AG1",
         "PerPkg": "1",
@@ -1634,16 +1452,14 @@
     },
     {
         "BriefDescription": "CMS Vertical Egress Bypass. AD ring agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9E",
         "EventName": "UNC_H_EGRESS_VERT_BYPASS.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress Bypass. AD ring agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9E",
         "EventName": "UNC_H_EGRESS_VERT_BYPASS.AD_AG1",
         "PerPkg": "1",
@@ -1652,16 +1468,14 @@
     },
     {
         "BriefDescription": "CMS Vertical Egress Bypass. AK ring agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9E",
         "EventName": "UNC_H_EGRESS_VERT_BYPASS.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress Bypass. AK ring agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9E",
         "EventName": "UNC_H_EGRESS_VERT_BYPASS.AK_AG1",
         "PerPkg": "1",
@@ -1670,16 +1484,14 @@
     },
     {
         "BriefDescription": "CMS Vertical Egress Bypass. BL ring agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9E",
         "EventName": "UNC_H_EGRESS_VERT_BYPASS.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress Bypass. BL ring agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9E",
         "EventName": "UNC_H_EGRESS_VERT_BYPASS.BL_AG1",
         "PerPkg": "1",
@@ -1688,25 +1500,22 @@
     },
     {
         "BriefDescription": "CMS Vertical Egress Bypass. IV ring agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9E",
         "EventName": "UNC_H_EGRESS_VERT_BYPASS.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AD - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x92",
         "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AD - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x92",
         "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AD_AG1",
         "PerPkg": "1",
@@ -1715,16 +1524,14 @@
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AK - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x92",
         "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AK - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x92",
         "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AK_AG1",
         "PerPkg": "1",
@@ -1733,16 +1540,14 @@
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full BL - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x92",
         "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full BL - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x92",
         "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.BL_AG1",
         "PerPkg": "1",
@@ -1751,25 +1556,22 @@
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full IV - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x92",
         "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty AD - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x93",
         "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty AD - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x93",
         "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AD_AG1",
         "PerPkg": "1",
@@ -1778,16 +1580,14 @@
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty AK - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x93",
         "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty AK - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x93",
         "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AK_AG1",
         "PerPkg": "1",
@@ -1796,16 +1596,14 @@
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty BL - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x93",
         "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty BL - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x93",
         "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.BL_AG1",
         "PerPkg": "1",
@@ -1814,25 +1612,22 @@
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty IV - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x93",
         "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Allocations AD - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x91",
         "EventName": "UNC_H_EGRESS_VERT_INSERTS.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Allocations AD - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x91",
         "EventName": "UNC_H_EGRESS_VERT_INSERTS.AD_AG1",
         "PerPkg": "1",
@@ -1841,16 +1636,14 @@
     },
     {
         "BriefDescription": "CMS Vert Egress Allocations AK - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x91",
         "EventName": "UNC_H_EGRESS_VERT_INSERTS.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Allocations AK - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x91",
         "EventName": "UNC_H_EGRESS_VERT_INSERTS.AK_AG1",
         "PerPkg": "1",
@@ -1859,16 +1652,14 @@
     },
     {
         "BriefDescription": "CMS Vert Egress Allocations BL - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x91",
         "EventName": "UNC_H_EGRESS_VERT_INSERTS.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Allocations BL - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x91",
         "EventName": "UNC_H_EGRESS_VERT_INSERTS.BL_AG1",
         "PerPkg": "1",
@@ -1877,25 +1668,22 @@
     },
     {
         "BriefDescription": "CMS Vert Egress Allocations IV - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x91",
         "EventName": "UNC_H_EGRESS_VERT_INSERTS.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress NACKs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x98",
         "EventName": "UNC_H_EGRESS_VERT_NACK.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress NACKs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x98",
         "EventName": "UNC_H_EGRESS_VERT_NACK.AD_AG1",
         "PerPkg": "1",
@@ -1904,16 +1692,14 @@
     },
     {
         "BriefDescription": "CMS Vertical Egress NACKs Onto AK Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x98",
         "EventName": "UNC_H_EGRESS_VERT_NACK.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress NACKs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x98",
         "EventName": "UNC_H_EGRESS_VERT_NACK.AK_AG1",
         "PerPkg": "1",
@@ -1922,16 +1708,14 @@
     },
     {
         "BriefDescription": "CMS Vertical Egress NACKs Onto BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x98",
         "EventName": "UNC_H_EGRESS_VERT_NACK.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress NACKs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x98",
         "EventName": "UNC_H_EGRESS_VERT_NACK.BL_AG1",
         "PerPkg": "1",
@@ -1940,25 +1724,22 @@
     },
     {
         "BriefDescription": "CMS Vertical Egress NACKs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x98",
         "EventName": "UNC_H_EGRESS_VERT_NACK.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Occupancy AD - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x90",
         "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Occupancy AD - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x90",
         "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AD_AG1",
         "PerPkg": "1",
@@ -1967,16 +1748,14 @@
     },
     {
         "BriefDescription": "CMS Vert Egress Occupancy AK - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x90",
         "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Occupancy AK - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x90",
         "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AK_AG1",
         "PerPkg": "1",
@@ -1985,16 +1764,14 @@
     },
     {
         "BriefDescription": "CMS Vert Egress Occupancy BL - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x90",
         "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Occupancy BL - Agent 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x90",
         "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.BL_AG1",
         "PerPkg": "1",
@@ -2003,25 +1780,22 @@
     },
     {
         "BriefDescription": "CMS Vert Egress Occupancy IV - Agent 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x90",
         "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9A",
         "EventName": "UNC_H_EGRESS_VERT_STARVED.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9A",
         "EventName": "UNC_H_EGRESS_VERT_STARVED.AD_AG1",
         "PerPkg": "1",
@@ -2030,16 +1804,14 @@
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation Onto AK Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9A",
         "EventName": "UNC_H_EGRESS_VERT_STARVED.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9A",
         "EventName": "UNC_H_EGRESS_VERT_STARVED.AK_AG1",
         "PerPkg": "1",
@@ -2048,16 +1820,14 @@
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation Onto BL Ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9A",
         "EventName": "UNC_H_EGRESS_VERT_STARVED.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9A",
         "EventName": "UNC_H_EGRESS_VERT_STARVED.BL_AG1",
         "PerPkg": "1",
@@ -2066,25 +1836,22 @@
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9A",
         "EventName": "UNC_H_EGRESS_VERT_STARVED.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts cycles source throttling is adderted - horizontal",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA5",
         "EventName": "UNC_H_FAST_ASSERTED.HORZ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts cycles source throttling is adderted - vertical",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA5",
         "EventName": "UNC_H_FAST_ASSERTED.VERT",
         "PerPkg": "1",
@@ -2092,160 +1859,142 @@
     },
     {
         "BriefDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Left and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA7",
         "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Left and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA7",
         "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Right and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA7",
         "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Right and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA7",
         "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Left and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA9",
         "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Left and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA9",
         "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Right and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA9",
         "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Right and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA9",
         "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Left and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAB",
         "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Left and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAB",
         "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Right and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAB",
         "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Right and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAB",
         "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop - Left",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAD",
         "EventName": "UNC_H_HORZ_RING_IV_IN_USE.LEFT",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop - Right",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAD",
         "EventName": "UNC_H_HORZ_RING_IV_IN_USE.RIGHT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IPQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_H_INGRESS_INSERTS.IPQ",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IRQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_H_INGRESS_INSERTS.IRQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IRQ Rejected",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_H_INGRESS_INSERTS.IRQ_REJ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - PRQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_H_INGRESS_INSERTS.PRQ",
         "PerPkg": "1",
@@ -2254,7 +2003,6 @@
     },
     {
         "BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - PRQ Rejected",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "UNC_H_INGRESS_INSERTS.PRQ_REJ",
         "PerPkg": "1",
@@ -2263,34 +2011,30 @@
     },
     {
         "BriefDescription": "Cycles with the IPQ in Internal Starvation.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_H_INGRESS_INT_STARVED.IPQ",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles with the IRQ in Internal Starvation.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_H_INGRESS_INT_STARVED.IRQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles with the ISMQ in Internal Starvation.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_H_INGRESS_INT_STARVED.ISMQ",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Ingress internal starvation cycles. Counts cycles in internal starvation. This occurs when one or more of the entries in the ingress queue are being starved out by other entries in the queue.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "UNC_H_INGRESS_INT_STARVED.PRQ",
         "PerPkg": "1",
@@ -2302,7 +2046,7 @@
         "EventCode": "0x11",
         "EventName": "UNC_H_INGRESS_OCCUPANCY.IPQ",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
@@ -2310,7 +2054,7 @@
         "EventCode": "0x11",
         "EventName": "UNC_H_INGRESS_OCCUPANCY.IRQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
@@ -2318,7 +2062,7 @@
         "EventCode": "0x11",
         "EventName": "UNC_H_INGRESS_OCCUPANCY.IRQ_REJ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
@@ -2339,25 +2083,22 @@
     },
     {
         "BriefDescription": "Ingress Probe Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Ingress Probe Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Ingress Probe Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
@@ -2366,7 +2107,6 @@
     },
     {
         "BriefDescription": "Ingress Probe Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
@@ -2375,7 +2115,6 @@
     },
     {
         "BriefDescription": "Ingress Probe Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
@@ -2384,25 +2123,22 @@
     },
     {
         "BriefDescription": "Ingress Probe Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Ingress Probe Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Ingress Probe Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
@@ -2411,7 +2147,6 @@
     },
     {
         "BriefDescription": "Ingress Probe Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x23",
         "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
@@ -2420,16 +2155,14 @@
     },
     {
         "BriefDescription": "Ingress Probe Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x23",
         "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.ANY_REJECT_IPQ0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Ingress Probe Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x23",
         "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
@@ -2438,16 +2171,14 @@
     },
     {
         "BriefDescription": "Ingress Probe Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x23",
         "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Ingress Probe Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x23",
         "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.SF_WAY",
         "PerPkg": "1",
@@ -2456,25 +2187,22 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
@@ -2483,7 +2211,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
@@ -2492,7 +2219,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
@@ -2501,25 +2227,22 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
@@ -2528,7 +2251,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
@@ -2537,16 +2259,14 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.ANY_REJECT_IRQ0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
@@ -2555,16 +2275,14 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.SF_WAY",
         "PerPkg": "1",
@@ -2573,25 +2291,22 @@
     },
     {
         "BriefDescription": "ISMQ Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "ISMQ Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "ISMQ Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
@@ -2600,7 +2315,6 @@
     },
     {
         "BriefDescription": "ISMQ Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
@@ -2609,7 +2323,6 @@
     },
     {
         "BriefDescription": "ISMQ Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
@@ -2618,25 +2331,22 @@
     },
     {
         "BriefDescription": "ISMQ Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "ISMQ Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "ISMQ Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
@@ -2645,25 +2355,22 @@
     },
     {
         "BriefDescription": "ISMQ Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2C",
         "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "ISMQ Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2C",
         "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "ISMQ Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2C",
         "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AK_NON_UPI",
         "PerPkg": "1",
@@ -2672,7 +2379,6 @@
     },
     {
         "BriefDescription": "ISMQ Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2C",
         "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_NCB_VN0",
         "PerPkg": "1",
@@ -2681,7 +2387,6 @@
     },
     {
         "BriefDescription": "ISMQ Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2C",
         "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_NCS_VN0",
         "PerPkg": "1",
@@ -2690,25 +2395,22 @@
     },
     {
         "BriefDescription": "ISMQ Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2C",
         "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "ISMQ Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2C",
         "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "ISMQ Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2C",
         "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.IV_NON_UPI",
         "PerPkg": "1",
@@ -2717,25 +2419,22 @@
     },
     {
         "BriefDescription": "Other Queue Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Other Queue Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Other Queue Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.AK_NON_UPI",
         "PerPkg": "1",
@@ -2744,7 +2443,6 @@
     },
     {
         "BriefDescription": "Other Queue Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_NCB_VN0",
         "PerPkg": "1",
@@ -2753,7 +2451,6 @@
     },
     {
         "BriefDescription": "Other Queue Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_NCS_VN0",
         "PerPkg": "1",
@@ -2762,25 +2459,22 @@
     },
     {
         "BriefDescription": "Other Queue Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Other Queue Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Other Queue Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.IV_NON_UPI",
         "PerPkg": "1",
@@ -2789,7 +2483,6 @@
     },
     {
         "BriefDescription": "Other Queue Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2F",
         "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.ALLOW_SNP",
         "PerPkg": "1",
@@ -2798,16 +2491,14 @@
     },
     {
         "BriefDescription": "Other Queue Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2F",
         "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.ANY_REJECT_IRQ0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Other Queue Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2F",
         "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.PA_MATCH",
         "PerPkg": "1",
@@ -2816,16 +2507,14 @@
     },
     {
         "BriefDescription": "Other Queue Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2F",
         "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Other Queue Retries",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2F",
         "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.SF_WAY",
         "PerPkg": "1",
@@ -2834,25 +2523,22 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
@@ -2861,7 +2547,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
@@ -2870,7 +2555,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
@@ -2879,25 +2563,22 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
@@ -2906,7 +2587,6 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
@@ -2915,16 +2595,14 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.ANY_REJECT_IRQ0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
@@ -2933,16 +2611,14 @@
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Ingress Request Queue Rejects",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.SF_WAY",
         "PerPkg": "1",
@@ -2951,25 +2627,22 @@
     },
     {
         "BriefDescription": "REQUESTQ'' includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "REQUESTQ'' includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "REQUESTQ'' includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AK_NON_UPI",
         "PerPkg": "1",
@@ -2978,7 +2651,6 @@
     },
     {
         "BriefDescription": "REQUESTQ'' includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_NCB_VN0",
         "PerPkg": "1",
@@ -2987,7 +2659,6 @@
     },
     {
         "BriefDescription": "REQUESTQ'' includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_NCS_VN0",
         "PerPkg": "1",
@@ -2996,25 +2667,22 @@
     },
     {
         "BriefDescription": "REQUESTQ'' includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "REQUESTQ'' includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "REQUESTQ'' includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.IV_NON_UPI",
         "PerPkg": "1",
@@ -3023,7 +2691,6 @@
     },
     {
         "BriefDescription": "REQUESTQ'' includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2B",
         "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.ALLOW_SNP",
         "PerPkg": "1",
@@ -3032,16 +2699,14 @@
     },
     {
         "BriefDescription": "REQUESTQ'' includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2B",
         "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.ANY_REJECT_IRQ0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "REQUESTQ'' includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2B",
         "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.PA_MATCH",
         "PerPkg": "1",
@@ -3050,16 +2715,14 @@
     },
     {
         "BriefDescription": "REQUESTQ'' includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2B",
         "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "REQUESTQ'' includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2B",
         "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.SF_WAY",
         "PerPkg": "1",
@@ -3068,7 +2731,6 @@
     },
     {
         "BriefDescription": "Miscellaneous events in the Cbo. CV0 Prefetch Miss",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_H_MISC.CV0_PREF_MISS",
         "PerPkg": "1",
@@ -3077,7 +2739,6 @@
     },
     {
         "BriefDescription": "Miscellaneous events in the Cbo. CV0 Prefetch Victim",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_H_MISC.CV0_PREF_VIC",
         "PerPkg": "1",
@@ -3086,178 +2747,158 @@
     },
     {
         "BriefDescription": "Miscellaneous events in the Cbo. RFO HitS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_H_MISC.RFO_HIT_S",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Miscellaneous events in the Cbo. Silent Snoop Eviction",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_H_MISC.RSPI_WAS_FSE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Miscellaneous events in the Cbo. Write Combining Aliasing",
-        "Counter": "0,1,2,3",
         "EventCode": "0x39",
         "EventName": "UNC_H_MISC.WC_ALIASING",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Number of incoming messages from the Horizontal ring that were bounced, by ring type.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA1",
         "EventName": "UNC_H_RING_BOUNCES_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Number of incoming messages from the Horizontal ring that were bounced, by ring type - Acknowledgements to core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA1",
         "EventName": "UNC_H_RING_BOUNCES_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Number of incoming messages from the Horizontal ring that were bounced, by ring type - Data Responses to core.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA1",
         "EventName": "UNC_H_RING_BOUNCES_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Number of incoming messages from the Horizontal ring that were bounced, by ring type - Snoops of processor's cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA1",
         "EventName": "UNC_H_RING_BOUNCES_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Number of incoming messages from the Vertical ring that were bounced, by ring type.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA0",
         "EventName": "UNC_H_RING_BOUNCES_VERT.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Number of incoming messages from the Vertical ring that were bounced, by ring type - Acknowledgements to core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA0",
         "EventName": "UNC_H_RING_BOUNCES_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Number of incoming messages from the Vertical ring that were bounced, by ring type - Data Responses to core.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA0",
         "EventName": "UNC_H_RING_BOUNCES_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Number of incoming messages from the Vertical ring that were bounced, by ring type - Snoops of processor's cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA0",
         "EventName": "UNC_H_RING_BOUNCES_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Horizontal ring sink starvation count - AD ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA3",
         "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Horizontal ring sink starvation count - AK ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA3",
         "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Horizontal ring sink starvation count - BL ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA3",
         "EventName": "UNC_H_RING_SINK_STARVED_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Horizontal ring sink starvation count - IV ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA3",
         "EventName": "UNC_H_RING_SINK_STARVED_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical ring sink starvation count - AD ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "UNC_H_RING_SINK_STARVED_VERT.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical ring sink starvation count - AK ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "UNC_H_RING_SINK_STARVED_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical ring sink starvation count - BL ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "UNC_H_RING_SINK_STARVED_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical ring sink starvation count - IV ring",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "UNC_H_RING_SINK_STARVED_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts cycles in throttle mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA4",
         "EventName": "UNC_H_RING_SRC_THRTL",
         "PerPkg": "1",
@@ -3265,7 +2906,6 @@
     },
     {
         "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Filters for any transaction originating from the IPQ or IRQ.  This does not include lookups originating from the ISMQ.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "UNC_H_SF_LOOKUP.ANY",
         "PerPkg": "1",
@@ -3274,43 +2914,38 @@
     },
     {
         "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Read transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "UNC_H_SF_LOOKUP.DATA_READ",
         "PerPkg": "1",
-        "UMask": "0x03",
+        "UMask": "0x3",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Filters for only snoop requests coming from the remote socket(s) through the IPQ.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "UNC_H_SF_LOOKUP.REMOTE_SNOOP",
         "PerPkg": "1",
-        "UMask": "0x09",
+        "UMask": "0x9",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Writeback transactions from L2 to the LLC  This includes all write transactions -- both Cachable and UC.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "UNC_H_SF_LOOKUP.WRITE",
         "PerPkg": "1",
-        "UMask": "0x05",
+        "UMask": "0x5",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.AD_CRD",
         "PerPkg": "1",
@@ -3319,16 +2954,14 @@
     },
     {
         "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.BL_CRD",
         "PerPkg": "1",
@@ -3337,16 +2970,14 @@
     },
     {
         "BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_H_TG_INGRESS_BYPASS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_H_TG_INGRESS_BYPASS.AD_CRD",
         "PerPkg": "1",
@@ -3355,25 +2986,22 @@
     },
     {
         "BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_H_TG_INGRESS_BYPASS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_H_TG_INGRESS_BYPASS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_H_TG_INGRESS_BYPASS.BL_CRD",
         "PerPkg": "1",
@@ -3382,25 +3010,22 @@
     },
     {
         "BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_H_TG_INGRESS_BYPASS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.AD_CRD",
         "PerPkg": "1",
@@ -3409,25 +3034,22 @@
     },
     {
         "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.BL_CRD",
         "PerPkg": "1",
@@ -3436,7 +3058,6 @@
     },
     {
         "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.IFV",
         "PerPkg": "1",
@@ -3445,25 +3066,22 @@
     },
     {
         "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_H_TG_INGRESS_INSERTS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_H_TG_INGRESS_INSERTS.AD_CRD",
         "PerPkg": "1",
@@ -3472,25 +3090,22 @@
     },
     {
         "BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_H_TG_INGRESS_INSERTS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_H_TG_INGRESS_INSERTS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_H_TG_INGRESS_INSERTS.BL_CRD",
         "PerPkg": "1",
@@ -3499,25 +3114,22 @@
     },
     {
         "BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_H_TG_INGRESS_INSERTS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
@@ -3526,25 +3138,22 @@
     },
     {
         "BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
@@ -3553,16 +3162,14 @@
     },
     {
         "BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -SF/LLC Evictions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_H_TOR_INSERTS.EVICT",
         "PerPkg": "1",
@@ -3571,16 +3178,14 @@
     },
     {
         "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -Hit (Not a Miss)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_H_TOR_INSERTS.HIT",
         "PerPkg": "1",
-        "UMask": "0x1F",
+        "UMask": "0x1f",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -IPQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_H_TOR_INSERTS.IPQ",
         "PerPkg": "1",
@@ -3589,7 +3194,6 @@
     },
     {
         "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -IRQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_H_TOR_INSERTS.IRQ",
         "PerPkg": "1",
@@ -3598,16 +3202,14 @@
     },
     {
         "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -Miss",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_H_TOR_INSERTS.MISS",
         "PerPkg": "1",
-        "UMask": "0x2F",
+        "UMask": "0x2f",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match  qualifications specified by the subevent -PRQ",
-        "Counter": "0,1,2,3",
         "EventCode": "0x35",
         "EventName": "UNC_H_TOR_INSERTS.PRQ",
         "PerPkg": "1",
@@ -3627,7 +3229,7 @@
         "EventCode": "0x36",
         "EventName": "UNC_H_TOR_OCCUPANCY.HIT",
         "PerPkg": "1",
-        "UMask": "0x1F",
+        "UMask": "0x1f",
         "Unit": "CHA"
     },
     {
@@ -3683,7 +3285,7 @@
         "EventCode": "0x36",
         "EventName": "UNC_H_TOR_OCCUPANCY.MISS",
         "PerPkg": "1",
-        "UMask": "0x2F",
+        "UMask": "0x2f",
         "Unit": "CHA"
     },
     {
@@ -3712,167 +3314,148 @@
     },
     {
         "BriefDescription": "Uncore Clocks",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_H_U_CLOCKTICKS",
         "PerPkg": "1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Down and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA6",
         "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Down and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA6",
         "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Up and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA6",
         "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Up and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA6",
         "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Down and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA8",
         "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Down and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA8",
         "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Up and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA8",
         "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Up and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA8",
         "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Down and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAA",
         "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Down and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAA",
         "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Up and Even",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAA",
         "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Up and Odd",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAA",
         "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop - Down",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAC",
         "EventName": "UNC_H_VERT_RING_IV_IN_USE.DN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop - Up",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAC",
         "EventName": "UNC_H_VERT_RING_IV_IN_USE.UP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full.  AD_0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x25",
         "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AD_0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full.  AD_1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x25",
         "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AD_1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full.  AK_0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x25",
         "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AK_0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full.  AK_1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x25",
         "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AK_1",
         "PerPkg": "1",
@@ -3881,16 +3464,14 @@
     },
     {
         "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full.  BL_0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x25",
         "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.BL_0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full.  BL_1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x25",
         "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.BL_1",
         "PerPkg": "1",
@@ -3899,34 +3480,30 @@
     },
     {
         "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty.  AD_0",
-        "Counter": "0,1",
         "EventCode": "0x23",
         "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AD_0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty.  AD_1",
-        "Counter": "0,1",
         "EventCode": "0x23",
         "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AD_1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty.  AK_0",
-        "Counter": "0,1",
         "EventCode": "0x23",
         "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AK_0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty.  AK_1",
-        "Counter": "0,1",
         "EventCode": "0x23",
         "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AK_1",
         "PerPkg": "1",
@@ -3935,16 +3512,14 @@
     },
     {
         "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty.  BL_0",
-        "Counter": "0,1",
         "EventCode": "0x23",
         "EventName": "UNC_M2P_EGRESS_CYCLES_NE.BL_0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty.  BL_1",
-        "Counter": "0,1",
         "EventCode": "0x23",
         "EventName": "UNC_M2P_EGRESS_CYCLES_NE.BL_1",
         "PerPkg": "1",
@@ -3953,16 +3528,14 @@
     },
     {
         "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the  the M2PCIe Egress queue. AD_0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_M2P_EGRESS_INSERTS.AD_0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the  the M2PCIe Egress queue. AD_1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_M2P_EGRESS_INSERTS.AD_1",
         "PerPkg": "1",
@@ -3971,16 +3544,14 @@
     },
     {
         "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the  the M2PCIe Egress queue. AK_0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_M2P_EGRESS_INSERTS.AK_0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the  the M2PCIe Egress queue. AK_1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_M2P_EGRESS_INSERTS.AK_1",
         "PerPkg": "1",
@@ -3989,16 +3560,14 @@
     },
     {
         "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the  the M2PCIe Egress queue. AK_CRD_0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_M2P_EGRESS_INSERTS.AK_CRD_0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the  the M2PCIe Egress queue. AK_CRD_1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_M2P_EGRESS_INSERTS.AK_CRD_1",
         "PerPkg": "1",
@@ -4007,16 +3576,14 @@
     },
     {
         "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the  the M2PCIe Egress queue. BL_0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_M2P_EGRESS_INSERTS.BL_0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the  the M2PCIe Egress queue. BL_1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_M2P_EGRESS_INSERTS.BL_1",
         "PerPkg": "1",
@@ -4025,7 +3592,6 @@
     },
     {
         "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.ALL",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_M2P_INGRESS_CYCLES_NE.ALL",
         "PerPkg": "1",
@@ -4034,68 +3600,60 @@
     },
     {
         "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_IDI",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_IDI",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CAS All",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "UNC_M_CAS_COUNT.ALL",
         "PerPkg": "1",
-        "UMask": "0x03",
+        "UMask": "0x3",
         "Unit": "iMC_DCLK"
     },
     {
         "BriefDescription": "CAS Reads",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "UNC_M_CAS_COUNT.RD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "iMC_DCLK"
     },
     {
         "BriefDescription": "CAS Writes",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "UNC_M_CAS_COUNT.WR",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "iMC_DCLK"
     },
     {
         "BriefDescription": "DCLK count",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_M_D_CLOCKTICKS",
         "PerPkg": "1",
         "Unit": "iMC_DCLK"
     },
     {
         "BriefDescription": "UCLK count",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_M_U_CLOCKTICKS",
         "PerPkg": "1",
         "Unit": "iMC_UCLK"
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json b/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json
index 821cdd44a12fd..99a8fa8f19cc4 100644
--- a/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Counts the number of load micro-ops retired that cause a DTLB miss",
-        "Counter": "0,1",
         "Data_LA": "1",
         "EventCode": "0x04",
         "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
@@ -11,7 +10,6 @@
     },
     {
         "BriefDescription": "Counts the total number of core cycles for all the page walks. The cycles for page walks started in speculative path will also be included.",
-        "Counter": "0,1",
         "EventCode": "0x05",
         "EventName": "PAGE_WALKS.CYCLES",
         "PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress.",
@@ -20,7 +18,6 @@
     },
     {
         "BriefDescription": "Counts the total number of core cycles for all the D-side page walks. The cycles for page walks started in speculative path will also be included.",
-        "Counter": "0,1",
         "EventCode": "0x05",
         "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
         "SampleAfterValue": "200003",
@@ -28,7 +25,6 @@
     },
     {
         "BriefDescription": "Counts the total D-side page walks that are completed or started. The page walks started in the speculative path will also be counted",
-        "Counter": "0,1",
         "EdgeDetect": "1",
         "EventCode": "0x05",
         "EventName": "PAGE_WALKS.D_SIDE_WALKS",
@@ -37,7 +33,6 @@
     },
     {
         "BriefDescription": "Counts the total number of core cycles for all the I-side page walks. The cycles for page walks started in speculative path will also be included.",
-        "Counter": "0,1",
         "EventCode": "0x05",
         "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
         "PublicDescription": "This event counts every cycle when an I-side (walks due to an instruction fetch) page walk is in progress.",
@@ -46,7 +41,6 @@
     },
     {
         "BriefDescription": "Counts the total I-side page walks that are completed.",
-        "Counter": "0,1",
         "EdgeDetect": "1",
         "EventCode": "0x05",
         "EventName": "PAGE_WALKS.I_SIDE_WALKS",
@@ -55,7 +49,6 @@
     },
     {
         "BriefDescription": "Counts the total page walks that are completed (I-side and D-side)",
-        "Counter": "0,1",
         "EdgeDetect": "1",
         "EventCode": "0x05",
         "EventName": "PAGE_WALKS.WALKS",
-- 
GitLab


From 5362e4d1f24ed4d4edd9dc1cbf846218c88eabc3 Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:54:58 -0800
Subject: [PATCH 582/875] perf vendor events intel: Refresh meteorlake events

Update the meteorlake events using the new tooling from:

  https://github.com/intel/perfmon

The events are unchanged but they are sorted and unused json values
are removed. This increases consistency across the json files. The
CPUID matching regular expression is updated to match the perfmon one.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-12-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/pmu-events/arch/x86/mapfile.csv    |   2 +-
 .../pmu-events/arch/x86/meteorlake/cache.json | 170 ++++----------
 .../arch/x86/meteorlake/frontend.json         |   6 -
 .../arch/x86/meteorlake/memory.json           |  77 ++----
 .../pmu-events/arch/x86/meteorlake/other.json |  24 +-
 .../arch/x86/meteorlake/pipeline.json         | 222 ++++++------------
 .../arch/x86/meteorlake/virtual-memory.json   |  28 +--
 7 files changed, 166 insertions(+), 363 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index de3f9dd4e6f73..84f74acf91d9f 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -17,7 +17,7 @@ GenuineIntel-6-3A,v23,ivybridge,core
 GenuineIntel-6-3E,v22,ivytown,core
 GenuineIntel-6-2D,v21,jaketown,core
 GenuineIntel-6-(57|85),v9,knightslanding,core
-GenuineIntel-6-AA,v1.00,meteorlake,core
+GenuineIntel-6-A[AC],v1.00,meteorlake,core
 GenuineIntel-6-1[AEF],v3,nehalemep,core
 GenuineIntel-6-2E,v3,nehalemex,core
 GenuineIntel-6-2A,v17,sandybridge,core
diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/cache.json b/tools/perf/pmu-events/arch/x86/meteorlake/cache.json
index 32b2aa9b14750..0970724a29849 100644
--- a/tools/perf/pmu-events/arch/x86/meteorlake/cache.json
+++ b/tools/perf/pmu-events/arch/x86/meteorlake/cache.json
@@ -1,262 +1,196 @@
 [
+    {
+        "BriefDescription": "L2 code requests",
+        "EventCode": "0x24",
+        "EventName": "L2_RQSTS.ALL_CODE_RD",
+        "SampleAfterValue": "200003",
+        "UMask": "0xe4",
+        "Unit": "cpu_core"
+    },
+    {
+        "BriefDescription": "Demand Data Read access L2 cache",
+        "EventCode": "0x24",
+        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
+        "SampleAfterValue": "200003",
+        "UMask": "0xe1",
+        "Unit": "cpu_core"
+    },
     {
         "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2e",
         "EventName": "LONGEST_LAT_CACHE.MISS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "200003",
         "UMask": "0x41",
         "Unit": "cpu_atom"
     },
+    {
+        "BriefDescription": "Core-originated cacheable requests that missed L3  (Except hardware prefetches to the L3)",
+        "EventCode": "0x2e",
+        "EventName": "LONGEST_LAT_CACHE.MISS",
+        "SampleAfterValue": "100003",
+        "UMask": "0x41",
+        "Unit": "cpu_core"
+    },
     {
         "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2e",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "200003",
         "UMask": "0x4f",
         "Unit": "cpu_atom"
     },
+    {
+        "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
+        "EventCode": "0x2e",
+        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
+        "SampleAfterValue": "100003",
+        "UMask": "0x4f",
+        "Unit": "cpu_core"
+    },
+    {
+        "BriefDescription": "Retired load instructions.",
+        "Data_LA": "1",
+        "EventCode": "0xd0",
+        "EventName": "MEM_INST_RETIRED.ALL_LOADS",
+        "PEBS": "1",
+        "SampleAfterValue": "1000003",
+        "UMask": "0x81",
+        "Unit": "cpu_core"
+    },
+    {
+        "BriefDescription": "Retired store instructions.",
+        "Data_LA": "1",
+        "EventCode": "0xd0",
+        "EventName": "MEM_INST_RETIRED.ALL_STORES",
+        "PEBS": "1",
+        "SampleAfterValue": "1000003",
+        "UMask": "0x82",
+        "Unit": "cpu_core"
+    },
     {
         "BriefDescription": "Counts the number of load ops retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "200003",
         "UMask": "0x81",
         "Unit": "cpu_atom"
     },
     {
         "BriefDescription": "Counts the number of store ops retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "200003",
         "UMask": "0x82",
         "Unit": "cpu_atom"
     },
     {
         "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
-        "CollectPEBSRecord": "3",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x80",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "TakenAlone": "1",
         "UMask": "0x5",
         "Unit": "cpu_atom"
     },
     {
         "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
-        "CollectPEBSRecord": "3",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x10",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "TakenAlone": "1",
         "UMask": "0x5",
         "Unit": "cpu_atom"
     },
     {
         "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
-        "CollectPEBSRecord": "3",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x100",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "TakenAlone": "1",
         "UMask": "0x5",
         "Unit": "cpu_atom"
     },
     {
         "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
-        "CollectPEBSRecord": "3",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x20",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "TakenAlone": "1",
         "UMask": "0x5",
         "Unit": "cpu_atom"
     },
     {
         "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
-        "CollectPEBSRecord": "3",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x4",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "TakenAlone": "1",
         "UMask": "0x5",
         "Unit": "cpu_atom"
     },
     {
         "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
-        "CollectPEBSRecord": "3",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x200",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "TakenAlone": "1",
         "UMask": "0x5",
         "Unit": "cpu_atom"
     },
     {
         "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
-        "CollectPEBSRecord": "3",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x40",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "TakenAlone": "1",
         "UMask": "0x5",
         "Unit": "cpu_atom"
     },
     {
         "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
-        "CollectPEBSRecord": "3",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x8",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "TakenAlone": "1",
         "UMask": "0x5",
         "Unit": "cpu_atom"
     },
     {
         "BriefDescription": "Counts the number of  stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
-        "CollectPEBSRecord": "3",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
         "UMask": "0x6",
         "Unit": "cpu_atom"
-    },
-    {
-        "BriefDescription": "L2 code requests",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x24",
-        "EventName": "L2_RQSTS.ALL_CODE_RD",
-        "PEBScounters": "0,1,2,3",
-        "SampleAfterValue": "200003",
-        "UMask": "0xe4",
-        "Unit": "cpu_core"
-    },
-    {
-        "BriefDescription": "Demand Data Read access L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x24",
-        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
-        "PEBScounters": "0,1,2,3",
-        "SampleAfterValue": "200003",
-        "UMask": "0xe1",
-        "Unit": "cpu_core"
-    },
-    {
-        "BriefDescription": "Core-originated cacheable requests that missed L3  (Except hardware prefetches to the L3)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
-        "EventCode": "0x2e",
-        "EventName": "LONGEST_LAT_CACHE.MISS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
-        "SampleAfterValue": "100003",
-        "UMask": "0x41",
-        "Unit": "cpu_core"
-    },
-    {
-        "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
-        "EventCode": "0x2e",
-        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
-        "SampleAfterValue": "100003",
-        "UMask": "0x4f",
-        "Unit": "cpu_core"
-    },
-    {
-        "BriefDescription": "Retired load instructions.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
-        "Data_LA": "1",
-        "EventCode": "0xd0",
-        "EventName": "MEM_INST_RETIRED.ALL_LOADS",
-        "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
-        "SampleAfterValue": "1000003",
-        "UMask": "0x81",
-        "Unit": "cpu_core"
-    },
-    {
-        "BriefDescription": "Retired store instructions.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
-        "Data_LA": "1",
-        "EventCode": "0xd0",
-        "EventName": "MEM_INST_RETIRED.ALL_STORES",
-        "L1_Hit_Indication": "1",
-        "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
-        "SampleAfterValue": "1000003",
-        "UMask": "0x82",
-        "Unit": "cpu_core"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json b/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json
index 9657768fc95a9..7de11819dd0d6 100644
--- a/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json
@@ -1,22 +1,16 @@
 [
     {
         "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.ACCESSES",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "200003",
         "UMask": "0x3",
         "Unit": "cpu_atom"
     },
     {
         "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.MISSES",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "200003",
         "UMask": "0x2",
         "Unit": "cpu_atom"
diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/memory.json b/tools/perf/pmu-events/arch/x86/meteorlake/memory.json
index 15b2294a8ae78..b7715cec1dbc6 100644
--- a/tools/perf/pmu-events/arch/x86/meteorlake/memory.json
+++ b/tools/perf/pmu-events/arch/x86/meteorlake/memory.json
@@ -1,157 +1,102 @@
 [
-    {
-        "BriefDescription": "Counts cacheable demand data reads were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3,4,5,6,7",
-        "EventCode": "0xB7",
-        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
-        "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3FBFC00001",
-        "SampleAfterValue": "100003",
-        "UMask": "0x1",
-        "Unit": "cpu_atom"
-    },
-    {
-        "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3,4,5,6,7",
-        "EventCode": "0xB7",
-        "EventName": "OCR.DEMAND_RFO.L3_MISS",
-        "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3FBFC00002",
-        "SampleAfterValue": "100003",
-        "UMask": "0x1",
-        "Unit": "cpu_atom"
-    },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x80",
         "PEBS": "2",
-        "PEBScounters": "1,2,3,4,5,6,7",
         "SampleAfterValue": "1009",
-        "TakenAlone": "1",
         "UMask": "0x1",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x10",
         "PEBS": "2",
-        "PEBScounters": "1,2,3,4,5,6,7",
         "SampleAfterValue": "20011",
-        "TakenAlone": "1",
         "UMask": "0x1",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x100",
         "PEBS": "2",
-        "PEBScounters": "1,2,3,4,5,6,7",
         "SampleAfterValue": "503",
-        "TakenAlone": "1",
         "UMask": "0x1",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x20",
         "PEBS": "2",
-        "PEBScounters": "1,2,3,4,5,6,7",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x4",
         "PEBS": "2",
-        "PEBScounters": "1,2,3,4,5,6,7",
         "SampleAfterValue": "100003",
-        "TakenAlone": "1",
         "UMask": "0x1",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x200",
         "PEBS": "2",
-        "PEBScounters": "1,2,3,4,5,6,7",
         "SampleAfterValue": "101",
-        "TakenAlone": "1",
         "UMask": "0x1",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x40",
         "PEBS": "2",
-        "PEBScounters": "1,2,3,4,5,6,7",
         "SampleAfterValue": "2003",
-        "TakenAlone": "1",
         "UMask": "0x1",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x8",
         "PEBS": "2",
-        "PEBScounters": "1,2,3,4,5,6,7",
         "SampleAfterValue": "50021",
-        "TakenAlone": "1",
         "UMask": "0x1",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.",
-        "CollectPEBSRecord": "2",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE",
@@ -160,9 +105,18 @@
         "UMask": "0x2",
         "Unit": "cpu_core"
     },
+    {
+        "BriefDescription": "Counts cacheable demand data reads were not supplied by the L3 cache.",
+        "EventCode": "0xB7",
+        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
+        "MSRIndex": "0x1a6,0x1a7",
+        "MSRValue": "0x3FBFC00001",
+        "SampleAfterValue": "100003",
+        "UMask": "0x1",
+        "Unit": "cpu_atom"
+    },
     {
         "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
@@ -171,9 +125,18 @@
         "UMask": "0x1",
         "Unit": "cpu_core"
     },
+    {
+        "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO were not supplied by the L3 cache.",
+        "EventCode": "0xB7",
+        "EventName": "OCR.DEMAND_RFO.L3_MISS",
+        "MSRIndex": "0x1a6,0x1a7",
+        "MSRValue": "0x3FBFC00002",
+        "SampleAfterValue": "100003",
+        "UMask": "0x1",
+        "Unit": "cpu_atom"
+    },
     {
         "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_RFO.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/other.json b/tools/perf/pmu-events/arch/x86/meteorlake/other.json
index 14273ac54d2ca..ae98e3d0e1491 100644
--- a/tools/perf/pmu-events/arch/x86/meteorlake/other.json
+++ b/tools/perf/pmu-events/arch/x86/meteorlake/other.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Counts cacheable demand data reads Catch all value for any response types - this includes response types not define in the OCR.  If this is set all other response types will be ignored",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB7",
         "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
@@ -10,20 +9,8 @@
         "UMask": "0x1",
         "Unit": "cpu_atom"
     },
-    {
-        "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO Catch all value for any response types - this includes response types not define in the OCR.  If this is set all other response types will be ignored",
-        "Counter": "0,1,2,3,4,5,6,7",
-        "EventCode": "0xB7",
-        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
-        "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x10002",
-        "SampleAfterValue": "100003",
-        "UMask": "0x1",
-        "Unit": "cpu_atom"
-    },
     {
         "BriefDescription": "Counts demand data reads that have any type of response.",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
@@ -32,9 +19,18 @@
         "UMask": "0x1",
         "Unit": "cpu_core"
     },
+    {
+        "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO Catch all value for any response types - this includes response types not define in the OCR.  If this is set all other response types will be ignored",
+        "EventCode": "0xB7",
+        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
+        "MSRIndex": "0x1a6,0x1a7",
+        "MSRValue": "0x10002",
+        "SampleAfterValue": "100003",
+        "UMask": "0x1",
+        "Unit": "cpu_atom"
+    },
     {
         "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json b/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json
index 0a7981675b6c6..7be7e40c03ac5 100644
--- a/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json
@@ -1,254 +1,182 @@
 [
     {
         "BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "200003",
         "Unit": "cpu_atom"
     },
+    {
+        "BriefDescription": "All branch instructions retired.",
+        "EventCode": "0xc4",
+        "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
+        "PEBS": "1",
+        "SampleAfterValue": "400009",
+        "Unit": "cpu_core"
+    },
     {
         "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "200003",
         "Unit": "cpu_atom"
     },
+    {
+        "BriefDescription": "All mispredicted branch instructions retired.",
+        "EventCode": "0xc5",
+        "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
+        "PEBS": "1",
+        "SampleAfterValue": "400009",
+        "Unit": "cpu_core"
+    },
     {
         "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
-        "CollectPEBSRecord": "2",
-        "Counter": "33",
         "EventName": "CPU_CLK_UNHALTED.CORE",
-        "PEBScounters": "33",
         "SampleAfterValue": "2000003",
         "UMask": "0x2",
         "Unit": "cpu_atom"
     },
     {
         "BriefDescription": "Counts the number of unhalted core clock cycles[This event is alias to CPU_CLK_UNHALTED.THREAD_P]",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_UNHALTED.CORE_P",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "2000003",
         "Unit": "cpu_atom"
     },
     {
         "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
-        "CollectPEBSRecord": "2",
-        "Counter": "34",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
-        "PEBScounters": "34",
         "SampleAfterValue": "2000003",
         "UMask": "0x3",
         "Unit": "cpu_atom"
     },
-    {
-        "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
-        "CollectPEBSRecord": "2",
-        "Counter": "33",
-        "EventName": "CPU_CLK_UNHALTED.THREAD",
-        "PEBScounters": "33",
-        "SampleAfterValue": "2000003",
-        "UMask": "0x2",
-        "Unit": "cpu_atom"
-    },
-    {
-        "BriefDescription": "Counts the number of unhalted core clock cycles[This event is alias to CPU_CLK_UNHALTED.CORE_P]",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
-        "EventCode": "0x3c",
-        "EventName": "CPU_CLK_UNHALTED.THREAD_P",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
-        "SampleAfterValue": "2000003",
-        "Unit": "cpu_atom"
-    },
-    {
-        "BriefDescription": "Fixed Counter: Counts the number of instructions retired",
-        "CollectPEBSRecord": "2",
-        "Counter": "32",
-        "EventName": "INST_RETIRED.ANY",
-        "PEBS": "1",
-        "PEBScounters": "32",
-        "SampleAfterValue": "2000003",
-        "UMask": "0x1",
-        "Unit": "cpu_atom"
-    },
-    {
-        "BriefDescription": "Counts the number of instructions retired",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
-        "EventCode": "0xc0",
-        "EventName": "INST_RETIRED.ANY_P",
-        "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
-        "SampleAfterValue": "2000003",
-        "Unit": "cpu_atom"
-    },
-    {
-        "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
-        "EventCode": "0x73",
-        "EventName": "TOPDOWN_BAD_SPECULATION.ALL",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
-        "SampleAfterValue": "1000003",
-        "Unit": "cpu_atom"
-    },
-    {
-        "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
-        "EventCode": "0x74",
-        "EventName": "TOPDOWN_BE_BOUND.ALL",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
-        "SampleAfterValue": "1000003",
-        "Unit": "cpu_atom"
-    },
-    {
-        "BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
-        "EventCode": "0x71",
-        "EventName": "TOPDOWN_FE_BOUND.ALL",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
-        "SampleAfterValue": "1000003",
-        "Unit": "cpu_atom"
-    },
-    {
-        "BriefDescription": "Counts the number of consumed retirement slots.  Similar to UOPS_RETIRED.ALL",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
-        "EventCode": "0x72",
-        "EventName": "TOPDOWN_RETIRING.ALL",
-        "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
-        "SampleAfterValue": "1000003",
-        "Unit": "cpu_atom"
-    },
-    {
-        "BriefDescription": "All branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
-        "EventCode": "0xc4",
-        "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
-        "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
-        "SampleAfterValue": "400009",
-        "Unit": "cpu_core"
-    },
-    {
-        "BriefDescription": "All mispredicted branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
-        "EventCode": "0xc5",
-        "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
-        "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
-        "SampleAfterValue": "400009",
-        "Unit": "cpu_core"
-    },
     {
         "BriefDescription": "Reference cycles when the core is not in halt state.",
-        "CollectPEBSRecord": "2",
-        "Counter": "34",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
-        "PEBScounters": "34",
         "SampleAfterValue": "2000003",
         "UMask": "0x3",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Reference cycles when the core is not in halt state.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "2000003",
         "UMask": "0x1",
         "Unit": "cpu_core"
     },
+    {
+        "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
+        "EventName": "CPU_CLK_UNHALTED.THREAD",
+        "SampleAfterValue": "2000003",
+        "UMask": "0x2",
+        "Unit": "cpu_atom"
+    },
     {
         "BriefDescription": "Core cycles when the thread is not in halt state",
-        "CollectPEBSRecord": "2",
-        "Counter": "33",
         "EventName": "CPU_CLK_UNHALTED.THREAD",
-        "PEBScounters": "33",
         "SampleAfterValue": "2000003",
         "UMask": "0x2",
         "Unit": "cpu_core"
     },
+    {
+        "BriefDescription": "Counts the number of unhalted core clock cycles[This event is alias to CPU_CLK_UNHALTED.CORE_P]",
+        "EventCode": "0x3c",
+        "EventName": "CPU_CLK_UNHALTED.THREAD_P",
+        "SampleAfterValue": "2000003",
+        "Unit": "cpu_atom"
+    },
     {
         "BriefDescription": "Thread cycles when thread is not in halt state",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "2000003",
         "Unit": "cpu_core"
     },
+    {
+        "BriefDescription": "Fixed Counter: Counts the number of instructions retired",
+        "EventName": "INST_RETIRED.ANY",
+        "PEBS": "1",
+        "SampleAfterValue": "2000003",
+        "UMask": "0x1",
+        "Unit": "cpu_atom"
+    },
     {
         "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
-        "CollectPEBSRecord": "2",
-        "Counter": "32",
         "EventName": "INST_RETIRED.ANY",
         "PEBS": "1",
-        "PEBScounters": "32",
         "SampleAfterValue": "2000003",
         "UMask": "0x1",
         "Unit": "cpu_core"
     },
+    {
+        "BriefDescription": "Counts the number of instructions retired",
+        "EventCode": "0xc0",
+        "EventName": "INST_RETIRED.ANY_P",
+        "PEBS": "1",
+        "SampleAfterValue": "2000003",
+        "Unit": "cpu_atom"
+    },
     {
         "BriefDescription": "Number of instructions retired. General Counter - architectural event",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc0",
         "EventName": "INST_RETIRED.ANY_P",
         "PEBS": "1",
-        "PEBScounters": "1,2,3,4,5,6,7",
         "SampleAfterValue": "2000003",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.STORE_FORWARD",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
         "UMask": "0x82",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
-        "CollectPEBSRecord": "2",
-        "Counter": "35",
         "EventName": "TOPDOWN.SLOTS",
-        "PEBScounters": "35",
         "SampleAfterValue": "10000003",
         "UMask": "0x4",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa4",
         "EventName": "TOPDOWN.SLOTS_P",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "10000003",
         "UMask": "0x1",
         "Unit": "cpu_core"
+    },
+    {
+        "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
+        "EventCode": "0x73",
+        "EventName": "TOPDOWN_BAD_SPECULATION.ALL",
+        "SampleAfterValue": "1000003",
+        "Unit": "cpu_atom"
+    },
+    {
+        "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls",
+        "EventCode": "0x74",
+        "EventName": "TOPDOWN_BE_BOUND.ALL",
+        "SampleAfterValue": "1000003",
+        "Unit": "cpu_atom"
+    },
+    {
+        "BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls",
+        "EventCode": "0x71",
+        "EventName": "TOPDOWN_FE_BOUND.ALL",
+        "SampleAfterValue": "1000003",
+        "Unit": "cpu_atom"
+    },
+    {
+        "BriefDescription": "Counts the number of consumed retirement slots.  Similar to UOPS_RETIRED.ALL",
+        "EventCode": "0x72",
+        "EventName": "TOPDOWN_RETIRING.ALL",
+        "PEBS": "1",
+        "SampleAfterValue": "1000003",
+        "Unit": "cpu_atom"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/virtual-memory.json b/tools/perf/pmu-events/arch/x86/meteorlake/virtual-memory.json
index 3087730cca7bb..0ee62378bf22b 100644
--- a/tools/perf/pmu-events/arch/x86/meteorlake/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/meteorlake/virtual-memory.json
@@ -1,44 +1,32 @@
 [
-    {
-        "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
-        "EventCode": "0x85",
-        "EventName": "ITLB_MISSES.WALK_COMPLETED",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
-        "SampleAfterValue": "200003",
-        "UMask": "0xe",
-        "Unit": "cpu_atom"
-    },
     {
         "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
         "UMask": "0xe",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
         "UMask": "0xe",
         "Unit": "cpu_core"
     },
+    {
+        "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
+        "EventCode": "0x85",
+        "EventName": "ITLB_MISSES.WALK_COMPLETED",
+        "SampleAfterValue": "200003",
+        "UMask": "0xe",
+        "Unit": "cpu_atom"
+    },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x11",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
         "UMask": "0xe",
         "Unit": "cpu_core"
-- 
GitLab


From 7e353370cd17547620a7757fb1a6c146f3287ea3 Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:54:59 -0800
Subject: [PATCH 583/875] perf vendor events intel: Refresh nehalemep events

Update the nehalemep events using the new tooling from:

  https://github.com/intel/perfmon

The events are unchanged but unused json values are removed. This
increases consistency across the json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-13-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../pmu-events/arch/x86/nehalemep/cache.json  | 524 ------------------
 .../arch/x86/nehalemep/floating-point.json    |  28 -
 .../arch/x86/nehalemep/frontend.json          |   3 -
 .../pmu-events/arch/x86/nehalemep/memory.json | 134 -----
 .../pmu-events/arch/x86/nehalemep/other.json  |  18 -
 .../arch/x86/nehalemep/pipeline.json          | 127 +----
 .../arch/x86/nehalemep/virtual-memory.json    |  13 -
 7 files changed, 5 insertions(+), 842 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/cache.json b/tools/perf/pmu-events/arch/x86/nehalemep/cache.json
index 1ee91300baf93..1a132fcda9640 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemep/cache.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemep/cache.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Cycles L1D locked",
-        "Counter": "0,1",
         "EventCode": "0x63",
         "EventName": "CACHE_LOCK_CYCLES.L1D",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Cycles L1D and L2 locked",
-        "Counter": "0,1",
         "EventCode": "0x63",
         "EventName": "CACHE_LOCK_CYCLES.L1D_L2",
         "SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "L1D cache lines replaced in M state",
-        "Counter": "0,1",
         "EventCode": "0x51",
         "EventName": "L1D.M_EVICT",
         "SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "L1D cache lines allocated in the M state",
-        "Counter": "0,1",
         "EventCode": "0x51",
         "EventName": "L1D.M_REPL",
         "SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "L1D snoop eviction of cache lines in M state",
-        "Counter": "0,1",
         "EventCode": "0x51",
         "EventName": "L1D.M_SNOOP_EVICT",
         "SampleAfterValue": "2000000",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "L1 data cache lines allocated",
-        "Counter": "0,1",
         "EventCode": "0x51",
         "EventName": "L1D.REPL",
         "SampleAfterValue": "2000000",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "All references to the L1 data cache",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "L1D_ALL_REF.ANY",
         "SampleAfterValue": "2000000",
@@ -57,7 +50,6 @@
     },
     {
         "BriefDescription": "L1 data cacheable reads and writes",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "L1D_ALL_REF.CACHEABLE",
         "SampleAfterValue": "2000000",
@@ -65,7 +57,6 @@
     },
     {
         "BriefDescription": "L1 data cache read in E state",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE_LD.E_STATE",
         "SampleAfterValue": "2000000",
@@ -73,7 +64,6 @@
     },
     {
         "BriefDescription": "L1 data cache read in I state (misses)",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE_LD.I_STATE",
         "SampleAfterValue": "2000000",
@@ -81,7 +71,6 @@
     },
     {
         "BriefDescription": "L1 data cache reads",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE_LD.MESI",
         "SampleAfterValue": "2000000",
@@ -89,7 +78,6 @@
     },
     {
         "BriefDescription": "L1 data cache read in M state",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE_LD.M_STATE",
         "SampleAfterValue": "2000000",
@@ -97,7 +85,6 @@
     },
     {
         "BriefDescription": "L1 data cache read in S state",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE_LD.S_STATE",
         "SampleAfterValue": "2000000",
@@ -105,7 +92,6 @@
     },
     {
         "BriefDescription": "L1 data cache load locks in E state",
-        "Counter": "0,1",
         "EventCode": "0x42",
         "EventName": "L1D_CACHE_LOCK.E_STATE",
         "SampleAfterValue": "2000000",
@@ -113,7 +99,6 @@
     },
     {
         "BriefDescription": "L1 data cache load lock hits",
-        "Counter": "0,1",
         "EventCode": "0x42",
         "EventName": "L1D_CACHE_LOCK.HIT",
         "SampleAfterValue": "2000000",
@@ -121,7 +106,6 @@
     },
     {
         "BriefDescription": "L1 data cache load locks in M state",
-        "Counter": "0,1",
         "EventCode": "0x42",
         "EventName": "L1D_CACHE_LOCK.M_STATE",
         "SampleAfterValue": "2000000",
@@ -129,7 +113,6 @@
     },
     {
         "BriefDescription": "L1 data cache load locks in S state",
-        "Counter": "0,1",
         "EventCode": "0x42",
         "EventName": "L1D_CACHE_LOCK.S_STATE",
         "SampleAfterValue": "2000000",
@@ -137,7 +120,6 @@
     },
     {
         "BriefDescription": "L1D load lock accepted in fill buffer",
-        "Counter": "0,1",
         "EventCode": "0x53",
         "EventName": "L1D_CACHE_LOCK_FB_HIT",
         "SampleAfterValue": "2000000",
@@ -145,7 +127,6 @@
     },
     {
         "BriefDescription": "L1D prefetch load lock accepted in fill buffer",
-        "Counter": "0,1",
         "EventCode": "0x52",
         "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
         "SampleAfterValue": "2000000",
@@ -153,7 +134,6 @@
     },
     {
         "BriefDescription": "L1 data cache stores in E state",
-        "Counter": "0,1",
         "EventCode": "0x41",
         "EventName": "L1D_CACHE_ST.E_STATE",
         "SampleAfterValue": "2000000",
@@ -161,7 +141,6 @@
     },
     {
         "BriefDescription": "L1 data cache stores in M state",
-        "Counter": "0,1",
         "EventCode": "0x41",
         "EventName": "L1D_CACHE_ST.M_STATE",
         "SampleAfterValue": "2000000",
@@ -169,7 +148,6 @@
     },
     {
         "BriefDescription": "L1 data cache stores in S state",
-        "Counter": "0,1",
         "EventCode": "0x41",
         "EventName": "L1D_CACHE_ST.S_STATE",
         "SampleAfterValue": "2000000",
@@ -177,7 +155,6 @@
     },
     {
         "BriefDescription": "L1D hardware prefetch misses",
-        "Counter": "0,1",
         "EventCode": "0x4E",
         "EventName": "L1D_PREFETCH.MISS",
         "SampleAfterValue": "200000",
@@ -185,7 +162,6 @@
     },
     {
         "BriefDescription": "L1D hardware prefetch requests",
-        "Counter": "0,1",
         "EventCode": "0x4E",
         "EventName": "L1D_PREFETCH.REQUESTS",
         "SampleAfterValue": "200000",
@@ -193,7 +169,6 @@
     },
     {
         "BriefDescription": "L1D hardware prefetch requests triggered",
-        "Counter": "0,1",
         "EventCode": "0x4E",
         "EventName": "L1D_PREFETCH.TRIGGERS",
         "SampleAfterValue": "200000",
@@ -201,7 +176,6 @@
     },
     {
         "BriefDescription": "L1 writebacks to L2 in E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.E_STATE",
         "SampleAfterValue": "100000",
@@ -209,7 +183,6 @@
     },
     {
         "BriefDescription": "L1 writebacks to L2 in I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.I_STATE",
         "SampleAfterValue": "100000",
@@ -217,7 +190,6 @@
     },
     {
         "BriefDescription": "All L1 writebacks to L2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.MESI",
         "SampleAfterValue": "100000",
@@ -225,7 +197,6 @@
     },
     {
         "BriefDescription": "L1 writebacks to L2 in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.M_STATE",
         "SampleAfterValue": "100000",
@@ -233,7 +204,6 @@
     },
     {
         "BriefDescription": "L1 writebacks to L2 in S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.S_STATE",
         "SampleAfterValue": "100000",
@@ -241,7 +211,6 @@
     },
     {
         "BriefDescription": "All L2 data requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.ANY",
         "SampleAfterValue": "200000",
@@ -249,7 +218,6 @@
     },
     {
         "BriefDescription": "L2 data demand loads in E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
         "SampleAfterValue": "200000",
@@ -257,7 +225,6 @@
     },
     {
         "BriefDescription": "L2 data demand loads in I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
         "SampleAfterValue": "200000",
@@ -265,7 +232,6 @@
     },
     {
         "BriefDescription": "L2 data demand requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.MESI",
         "SampleAfterValue": "200000",
@@ -273,7 +239,6 @@
     },
     {
         "BriefDescription": "L2 data demand loads in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
         "SampleAfterValue": "200000",
@@ -281,7 +246,6 @@
     },
     {
         "BriefDescription": "L2 data demand loads in S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
         "SampleAfterValue": "200000",
@@ -289,7 +253,6 @@
     },
     {
         "BriefDescription": "L2 data prefetches in E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
         "SampleAfterValue": "200000",
@@ -297,7 +260,6 @@
     },
     {
         "BriefDescription": "L2 data prefetches in the I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
         "SampleAfterValue": "200000",
@@ -305,7 +267,6 @@
     },
     {
         "BriefDescription": "All L2 data prefetches",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
         "SampleAfterValue": "200000",
@@ -313,7 +274,6 @@
     },
     {
         "BriefDescription": "L2 data prefetches in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
         "SampleAfterValue": "200000",
@@ -321,7 +281,6 @@
     },
     {
         "BriefDescription": "L2 data prefetches in the S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
         "SampleAfterValue": "200000",
@@ -329,7 +288,6 @@
     },
     {
         "BriefDescription": "L2 lines alloacated",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.ANY",
         "SampleAfterValue": "100000",
@@ -337,7 +295,6 @@
     },
     {
         "BriefDescription": "L2 lines allocated in the E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.E_STATE",
         "SampleAfterValue": "100000",
@@ -345,7 +302,6 @@
     },
     {
         "BriefDescription": "L2 lines allocated in the S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.S_STATE",
         "SampleAfterValue": "100000",
@@ -353,7 +309,6 @@
     },
     {
         "BriefDescription": "L2 lines evicted",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.ANY",
         "SampleAfterValue": "100000",
@@ -361,7 +316,6 @@
     },
     {
         "BriefDescription": "L2 lines evicted by a demand request",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
         "SampleAfterValue": "100000",
@@ -369,7 +323,6 @@
     },
     {
         "BriefDescription": "L2 modified lines evicted by a demand request",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
         "SampleAfterValue": "100000",
@@ -377,7 +330,6 @@
     },
     {
         "BriefDescription": "L2 lines evicted by a prefetch request",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
         "SampleAfterValue": "100000",
@@ -385,7 +337,6 @@
     },
     {
         "BriefDescription": "L2 modified lines evicted by a prefetch request",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
         "SampleAfterValue": "100000",
@@ -393,7 +344,6 @@
     },
     {
         "BriefDescription": "L2 instruction fetches",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.IFETCHES",
         "SampleAfterValue": "200000",
@@ -401,7 +351,6 @@
     },
     {
         "BriefDescription": "L2 instruction fetch hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.IFETCH_HIT",
         "SampleAfterValue": "200000",
@@ -409,7 +358,6 @@
     },
     {
         "BriefDescription": "L2 instruction fetch misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.IFETCH_MISS",
         "SampleAfterValue": "200000",
@@ -417,7 +365,6 @@
     },
     {
         "BriefDescription": "L2 load hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.LD_HIT",
         "SampleAfterValue": "200000",
@@ -425,7 +372,6 @@
     },
     {
         "BriefDescription": "L2 load misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.LD_MISS",
         "SampleAfterValue": "200000",
@@ -433,7 +379,6 @@
     },
     {
         "BriefDescription": "L2 requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.LOADS",
         "SampleAfterValue": "200000",
@@ -441,7 +386,6 @@
     },
     {
         "BriefDescription": "All L2 misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.MISS",
         "SampleAfterValue": "200000",
@@ -449,7 +393,6 @@
     },
     {
         "BriefDescription": "All L2 prefetches",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PREFETCHES",
         "SampleAfterValue": "200000",
@@ -457,7 +400,6 @@
     },
     {
         "BriefDescription": "L2 prefetch hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PREFETCH_HIT",
         "SampleAfterValue": "200000",
@@ -465,7 +407,6 @@
     },
     {
         "BriefDescription": "L2 prefetch misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PREFETCH_MISS",
         "SampleAfterValue": "200000",
@@ -473,7 +414,6 @@
     },
     {
         "BriefDescription": "All L2 requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.REFERENCES",
         "SampleAfterValue": "200000",
@@ -481,7 +421,6 @@
     },
     {
         "BriefDescription": "L2 RFO requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFOS",
         "SampleAfterValue": "200000",
@@ -489,7 +428,6 @@
     },
     {
         "BriefDescription": "L2 RFO hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_HIT",
         "SampleAfterValue": "200000",
@@ -497,7 +435,6 @@
     },
     {
         "BriefDescription": "L2 RFO misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_MISS",
         "SampleAfterValue": "200000",
@@ -505,7 +442,6 @@
     },
     {
         "BriefDescription": "All L2 transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.ANY",
         "SampleAfterValue": "200000",
@@ -513,7 +449,6 @@
     },
     {
         "BriefDescription": "L2 fill transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.FILL",
         "SampleAfterValue": "200000",
@@ -521,7 +456,6 @@
     },
     {
         "BriefDescription": "L2 instruction fetch transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.IFETCH",
         "SampleAfterValue": "200000",
@@ -529,7 +463,6 @@
     },
     {
         "BriefDescription": "L1D writeback to L2 transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.L1D_WB",
         "SampleAfterValue": "200000",
@@ -537,7 +470,6 @@
     },
     {
         "BriefDescription": "L2 Load transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.LOAD",
         "SampleAfterValue": "200000",
@@ -545,7 +477,6 @@
     },
     {
         "BriefDescription": "L2 prefetch transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.PREFETCH",
         "SampleAfterValue": "200000",
@@ -553,7 +484,6 @@
     },
     {
         "BriefDescription": "L2 RFO transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.RFO",
         "SampleAfterValue": "200000",
@@ -561,7 +491,6 @@
     },
     {
         "BriefDescription": "L2 writeback to LLC transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.WB",
         "SampleAfterValue": "200000",
@@ -569,7 +498,6 @@
     },
     {
         "BriefDescription": "L2 demand lock RFOs in E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.E_STATE",
         "SampleAfterValue": "100000",
@@ -577,7 +505,6 @@
     },
     {
         "BriefDescription": "All demand L2 lock RFOs that hit the cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.HIT",
         "SampleAfterValue": "100000",
@@ -585,7 +512,6 @@
     },
     {
         "BriefDescription": "L2 demand lock RFOs in I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.I_STATE",
         "SampleAfterValue": "100000",
@@ -593,7 +519,6 @@
     },
     {
         "BriefDescription": "All demand L2 lock RFOs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.MESI",
         "SampleAfterValue": "100000",
@@ -601,7 +526,6 @@
     },
     {
         "BriefDescription": "L2 demand lock RFOs in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.M_STATE",
         "SampleAfterValue": "100000",
@@ -609,7 +533,6 @@
     },
     {
         "BriefDescription": "L2 demand lock RFOs in S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.S_STATE",
         "SampleAfterValue": "100000",
@@ -617,7 +540,6 @@
     },
     {
         "BriefDescription": "All L2 demand store RFOs that hit the cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.HIT",
         "SampleAfterValue": "100000",
@@ -625,7 +547,6 @@
     },
     {
         "BriefDescription": "L2 demand store RFOs in I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.I_STATE",
         "SampleAfterValue": "100000",
@@ -633,7 +554,6 @@
     },
     {
         "BriefDescription": "All L2 demand store RFOs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.MESI",
         "SampleAfterValue": "100000",
@@ -641,7 +561,6 @@
     },
     {
         "BriefDescription": "L2 demand store RFOs in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.M_STATE",
         "SampleAfterValue": "100000",
@@ -649,7 +568,6 @@
     },
     {
         "BriefDescription": "L2 demand store RFOs in S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.S_STATE",
         "SampleAfterValue": "100000",
@@ -657,7 +575,6 @@
     },
     {
         "BriefDescription": "Longest latency cache miss",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.MISS",
         "SampleAfterValue": "100000",
@@ -665,7 +582,6 @@
     },
     {
         "BriefDescription": "Longest latency cache reference",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
         "SampleAfterValue": "200000",
@@ -673,18 +589,15 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
         "MSRIndex": "0x3F6",
-        "MSRValue": "0x0",
         "PEBS": "2",
         "SampleAfterValue": "2000000",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
         "MSRIndex": "0x3F6",
@@ -695,7 +608,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
         "MSRIndex": "0x3F6",
@@ -706,7 +618,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
         "MSRIndex": "0x3F6",
@@ -717,7 +628,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
         "MSRIndex": "0x3F6",
@@ -728,7 +638,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
         "MSRIndex": "0x3F6",
@@ -739,7 +648,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
         "MSRIndex": "0x3F6",
@@ -750,7 +658,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
         "MSRIndex": "0x3F6",
@@ -761,7 +668,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
         "MSRIndex": "0x3F6",
@@ -772,7 +678,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
         "MSRIndex": "0x3F6",
@@ -783,7 +688,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
         "MSRIndex": "0x3F6",
@@ -794,7 +698,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
         "MSRIndex": "0x3F6",
@@ -805,7 +708,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
         "MSRIndex": "0x3F6",
@@ -816,7 +718,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
         "MSRIndex": "0x3F6",
@@ -827,7 +728,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
         "MSRIndex": "0x3F6",
@@ -838,7 +738,6 @@
     },
     {
         "BriefDescription": "Instructions retired which contains a load (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LOADS",
         "PEBS": "1",
@@ -847,7 +746,6 @@
     },
     {
         "BriefDescription": "Instructions retired which contains a store (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.STORES",
         "PEBS": "1",
@@ -856,7 +754,6 @@
     },
     {
         "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.HIT_LFB",
         "PEBS": "1",
@@ -865,7 +762,6 @@
     },
     {
         "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.L1D_HIT",
         "PEBS": "1",
@@ -874,7 +770,6 @@
     },
     {
         "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.L2_HIT",
         "PEBS": "1",
@@ -883,7 +778,6 @@
     },
     {
         "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.LLC_MISS",
         "PEBS": "1",
@@ -892,7 +786,6 @@
     },
     {
         "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
         "PEBS": "1",
@@ -901,7 +794,6 @@
     },
     {
         "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
         "PEBS": "1",
@@ -910,7 +802,6 @@
     },
     {
         "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM",
         "PEBS": "1",
@@ -919,7 +810,6 @@
     },
     {
         "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM",
         "PEBS": "1",
@@ -928,7 +818,6 @@
     },
     {
         "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT",
         "PEBS": "1",
@@ -937,7 +826,6 @@
     },
     {
         "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM",
         "PEBS": "1",
@@ -946,7 +834,6 @@
     },
     {
         "BriefDescription": "Load instructions retired IO (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE",
         "PEBS": "1",
@@ -955,7 +842,6 @@
     },
     {
         "BriefDescription": "Offcore L1 data cache writebacks",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
         "SampleAfterValue": "100000",
@@ -963,7 +849,6 @@
     },
     {
         "BriefDescription": "Offcore requests blocked due to Super Queue full",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "OFFCORE_REQUESTS_SQ_FULL",
         "SampleAfterValue": "100000",
@@ -971,2240 +856,1833 @@
     },
     {
         "BriefDescription": "Offcore data reads satisfied by any cache or DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F11",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore data reads",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF11",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x111",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x211",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x411",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x711",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4711",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1811",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3811",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x811",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by any cache or DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F44",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore code reads",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF44",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x144",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x244",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x444",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x744",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4744",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1844",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3844",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x844",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by any cache or DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7FFF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFFFF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x80FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x47FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x18FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x38FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x10FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F22",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore RFO requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF22",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x122",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x222",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x422",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x722",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4722",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1822",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3822",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x822",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F08",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore writebacks",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF08",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x108",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x408",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x708",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4708",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1808",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3808",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x808",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F77",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore code or data read requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF77",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x177",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x277",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x477",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x777",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4777",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1877",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3877",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x877",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = any cache_dram",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F33",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = any location",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF33",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x133",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x233",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x433",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = local cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x733",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = local cache or dram",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4733",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1833",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = remote cache or dram",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3833",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x833",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F03",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore demand data requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF03",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x103",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x203",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x403",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x703",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4703",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1803",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3803",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x803",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F01",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore demand data reads",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF01",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x101",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x201",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x401",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x701",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4701",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1801",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3801",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x801",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F04",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore demand code reads",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF04",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x104",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x204",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x404",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x704",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4704",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1804",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3804",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x804",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F02",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore demand RFO requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF02",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x102",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x202",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x402",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x702",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4702",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1802",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3802",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x802",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F80",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore other requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF80",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8080",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x180",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x280",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x480",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x780",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4780",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1880",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3880",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1080",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x880",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F30",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore prefetch data requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF30",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8030",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x130",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x230",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x430",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x730",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4730",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1830",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3830",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1030",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x830",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F10",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore prefetch data reads",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF10",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x110",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x210",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x410",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x710",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4710",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1810",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3810",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x810",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F40",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore prefetch code reads",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF40",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x140",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x240",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x440",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x740",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4740",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1840",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3840",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x840",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F20",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore prefetch RFO requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF20",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x120",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x220",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x420",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x720",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4720",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1820",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3820",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x820",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F70",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore prefetch requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF70",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x170",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x270",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x470",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x770",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4770",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1870",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3870",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x870",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Super Queue lock splits across a cache line",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF4",
         "EventName": "SQ_MISC.SPLIT_LOCK",
         "SampleAfterValue": "2000000",
@@ -3212,7 +2690,6 @@
     },
     {
         "BriefDescription": "Loads delayed with at-Retirement block code",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "STORE_BLOCKS.AT_RET",
         "SampleAfterValue": "200000",
@@ -3220,7 +2697,6 @@
     },
     {
         "BriefDescription": "Cacheable loads delayed with L1D block code",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "STORE_BLOCKS.L1D_BLOCK",
         "SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json b/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json
index 666e466d351c4..c03f8990fa82a 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "X87 Floating point assists (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF7",
         "EventName": "FP_ASSIST.ALL",
         "PEBS": "1",
@@ -10,7 +9,6 @@
     },
     {
         "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF7",
         "EventName": "FP_ASSIST.INPUT",
         "PEBS": "1",
@@ -19,7 +17,6 @@
     },
     {
         "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF7",
         "EventName": "FP_ASSIST.OUTPUT",
         "PEBS": "1",
@@ -28,7 +25,6 @@
     },
     {
         "BriefDescription": "MMX Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.MMX",
         "SampleAfterValue": "2000000",
@@ -36,7 +32,6 @@
     },
     {
         "BriefDescription": "SSE2 integer Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
         "SampleAfterValue": "2000000",
@@ -44,7 +39,6 @@
     },
     {
         "BriefDescription": "SSE* FP double precision Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
         "SampleAfterValue": "2000000",
@@ -52,7 +46,6 @@
     },
     {
         "BriefDescription": "SSE and SSE2 FP Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_FP",
         "SampleAfterValue": "2000000",
@@ -60,7 +53,6 @@
     },
     {
         "BriefDescription": "SSE FP packed Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
         "SampleAfterValue": "2000000",
@@ -68,7 +60,6 @@
     },
     {
         "BriefDescription": "SSE FP scalar Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
         "SampleAfterValue": "2000000",
@@ -76,7 +67,6 @@
     },
     {
         "BriefDescription": "SSE* FP single precision Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
         "SampleAfterValue": "2000000",
@@ -84,7 +74,6 @@
     },
     {
         "BriefDescription": "Computational floating-point operations executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.X87",
         "SampleAfterValue": "2000000",
@@ -92,7 +81,6 @@
     },
     {
         "BriefDescription": "All Floating Point to and from MMX transitions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCC",
         "EventName": "FP_MMX_TRANS.ANY",
         "SampleAfterValue": "2000000",
@@ -100,7 +88,6 @@
     },
     {
         "BriefDescription": "Transitions from MMX to Floating Point instructions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCC",
         "EventName": "FP_MMX_TRANS.TO_FP",
         "SampleAfterValue": "2000000",
@@ -108,7 +95,6 @@
     },
     {
         "BriefDescription": "Transitions from Floating Point to MMX instructions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCC",
         "EventName": "FP_MMX_TRANS.TO_MMX",
         "SampleAfterValue": "2000000",
@@ -116,7 +102,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer pack operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACK",
         "SampleAfterValue": "200000",
@@ -124,7 +109,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer arithmetic operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_ARITH",
         "SampleAfterValue": "200000",
@@ -132,7 +116,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer logical operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_LOGICAL",
         "SampleAfterValue": "200000",
@@ -140,7 +123,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer multiply operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_MPY",
         "SampleAfterValue": "200000",
@@ -148,7 +130,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer shift operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_SHIFT",
         "SampleAfterValue": "200000",
@@ -156,7 +137,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer shuffle/move operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.SHUFFLE_MOVE",
         "SampleAfterValue": "200000",
@@ -164,7 +144,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer unpack operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.UNPACK",
         "SampleAfterValue": "200000",
@@ -172,7 +151,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit pack operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACK",
         "SampleAfterValue": "200000",
@@ -180,7 +158,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit arithmetic operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_ARITH",
         "SampleAfterValue": "200000",
@@ -188,7 +165,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit logical operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_LOGICAL",
         "SampleAfterValue": "200000",
@@ -196,7 +172,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit packed multiply operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_MPY",
         "SampleAfterValue": "200000",
@@ -204,7 +179,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit shift operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_SHIFT",
         "SampleAfterValue": "200000",
@@ -212,7 +186,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit shuffle/move operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.SHUFFLE_MOVE",
         "SampleAfterValue": "200000",
@@ -220,7 +193,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit unpack operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.UNPACK",
         "SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json b/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json
index c561ac24d91d1..f7f28510e3ae9 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MACRO_INSTS.DECODED",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Macro-fused instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA6",
         "EventName": "MACRO_INSTS.FUSIONS_DECODED",
         "SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "Two Uop instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "TWO_UOP_INSTS_DECODED",
         "SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/memory.json b/tools/perf/pmu-events/arch/x86/nehalemep/memory.json
index 6e95de3f34093..f810880a295e9 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemep/memory.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemep/memory.json
@@ -1,738 +1,604 @@
 [
     {
         "BriefDescription": "Offcore data reads satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF811",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF844",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x60FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF8FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x40FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x20FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF822",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF808",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF877",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = any LLC miss",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF833",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the local DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF803",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF801",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF804",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF802",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6080",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF880",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2080",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6030",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF830",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4030",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2030",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF810",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF840",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF820",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF870",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     }
diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/other.json b/tools/perf/pmu-events/arch/x86/nehalemep/other.json
index f6887b234b0e5..fb706cb518322 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemep/other.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemep/other.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "ES segment renames",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD5",
         "EventName": "ES_REG_RENAMES",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "I/O transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6C",
         "EventName": "IO_TRANSACTIONS",
         "SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "L1I instruction fetch stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.CYCLES_STALLED",
         "SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "L1I instruction fetch hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.HITS",
         "SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "L1I instruction fetch misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.MISSES",
         "SampleAfterValue": "2000000",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "L1I Instruction fetches",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.READS",
         "SampleAfterValue": "2000000",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "Large ITLB hit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x82",
         "EventName": "LARGE_ITLB.HIT",
         "SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
     },
     {
         "BriefDescription": "All loads dispatched",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.ANY",
         "SampleAfterValue": "2000000",
@@ -65,7 +57,6 @@
     },
     {
         "BriefDescription": "Loads dispatched from the MOB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.MOB",
         "SampleAfterValue": "2000000",
@@ -73,7 +64,6 @@
     },
     {
         "BriefDescription": "Loads dispatched that bypass the MOB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.RS",
         "SampleAfterValue": "2000000",
@@ -81,7 +71,6 @@
     },
     {
         "BriefDescription": "Loads dispatched from stage 305",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.RS_DELAYED",
         "SampleAfterValue": "2000000",
@@ -89,7 +78,6 @@
     },
     {
         "BriefDescription": "False dependencies due to partial address aliasing",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "PARTIAL_ADDRESS_ALIAS",
         "SampleAfterValue": "200000",
@@ -97,7 +85,6 @@
     },
     {
         "BriefDescription": "All Store buffer stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "SB_DRAIN.ANY",
         "SampleAfterValue": "200000",
@@ -105,7 +92,6 @@
     },
     {
         "BriefDescription": "Segment rename stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD4",
         "EventName": "SEG_RENAME_STALLS",
         "SampleAfterValue": "2000000",
@@ -113,7 +99,6 @@
     },
     {
         "BriefDescription": "Thread responded HIT to snoop",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "SNOOP_RESPONSE.HIT",
         "SampleAfterValue": "100000",
@@ -121,7 +106,6 @@
     },
     {
         "BriefDescription": "Thread responded HITE to snoop",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "SNOOP_RESPONSE.HITE",
         "SampleAfterValue": "100000",
@@ -129,7 +113,6 @@
     },
     {
         "BriefDescription": "Thread responded HITM to snoop",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "SNOOP_RESPONSE.HITM",
         "SampleAfterValue": "100000",
@@ -137,7 +120,6 @@
     },
     {
         "BriefDescription": "Super Queue full stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF6",
         "EventName": "SQ_FULL_STALL_CYCLES",
         "SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json b/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json
index 6fc1a6efd8e89..c45f2ffa861e4 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Cycles the divider is busy",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "ARITH.CYCLES_DIV_BUSY",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Divide Operations executed",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x14",
@@ -20,7 +18,6 @@
     },
     {
         "BriefDescription": "Multiply operations executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "ARITH.MUL",
         "SampleAfterValue": "2000000",
@@ -28,7 +25,6 @@
     },
     {
         "BriefDescription": "BACLEAR asserted with bad target address",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE6",
         "EventName": "BACLEAR.BAD_TARGET",
         "SampleAfterValue": "2000000",
@@ -36,7 +32,6 @@
     },
     {
         "BriefDescription": "BACLEAR asserted, regardless of cause",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE6",
         "EventName": "BACLEAR.CLEAR",
         "SampleAfterValue": "2000000",
@@ -44,7 +39,6 @@
     },
     {
         "BriefDescription": "Instruction queue forced BACLEAR",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA7",
         "EventName": "BACLEAR_FORCE_IQ",
         "SampleAfterValue": "2000000",
@@ -52,7 +46,6 @@
     },
     {
         "BriefDescription": "Early Branch Prediciton Unit clears",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE8",
         "EventName": "BPU_CLEARS.EARLY",
         "SampleAfterValue": "2000000",
@@ -60,7 +53,6 @@
     },
     {
         "BriefDescription": "Late Branch Prediction Unit clears",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE8",
         "EventName": "BPU_CLEARS.LATE",
         "SampleAfterValue": "2000000",
@@ -68,7 +60,6 @@
     },
     {
         "BriefDescription": "Branch prediction unit missed call or return",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE5",
         "EventName": "BPU_MISSED_CALL_RET",
         "SampleAfterValue": "2000000",
@@ -76,7 +67,6 @@
     },
     {
         "BriefDescription": "Branch instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE0",
         "EventName": "BR_INST_DECODED",
         "SampleAfterValue": "2000000",
@@ -84,7 +74,6 @@
     },
     {
         "BriefDescription": "Branch instructions executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ANY",
         "SampleAfterValue": "200000",
@@ -92,7 +81,6 @@
     },
     {
         "BriefDescription": "Conditional branch instructions executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.COND",
         "SampleAfterValue": "200000",
@@ -100,7 +88,6 @@
     },
     {
         "BriefDescription": "Unconditional branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.DIRECT",
         "SampleAfterValue": "200000",
@@ -108,7 +95,6 @@
     },
     {
         "BriefDescription": "Unconditional call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
         "SampleAfterValue": "20000",
@@ -116,7 +102,6 @@
     },
     {
         "BriefDescription": "Indirect call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
         "SampleAfterValue": "20000",
@@ -124,7 +109,6 @@
     },
     {
         "BriefDescription": "Indirect non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
         "SampleAfterValue": "20000",
@@ -132,7 +116,6 @@
     },
     {
         "BriefDescription": "Call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.NEAR_CALLS",
         "SampleAfterValue": "20000",
@@ -140,7 +123,6 @@
     },
     {
         "BriefDescription": "All non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.NON_CALLS",
         "SampleAfterValue": "200000",
@@ -148,7 +130,6 @@
     },
     {
         "BriefDescription": "Indirect return branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.RETURN_NEAR",
         "SampleAfterValue": "20000",
@@ -156,7 +137,6 @@
     },
     {
         "BriefDescription": "Taken branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN",
         "SampleAfterValue": "200000",
@@ -164,7 +144,6 @@
     },
     {
         "BriefDescription": "Retired branch instructions (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
@@ -173,7 +152,6 @@
     },
     {
         "BriefDescription": "Retired conditional branch instructions (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -182,7 +160,6 @@
     },
     {
         "BriefDescription": "Retired near call instructions (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -191,7 +168,6 @@
     },
     {
         "BriefDescription": "Mispredicted branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ANY",
         "SampleAfterValue": "20000",
@@ -199,7 +175,6 @@
     },
     {
         "BriefDescription": "Mispredicted conditional branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.COND",
         "SampleAfterValue": "20000",
@@ -207,7 +182,6 @@
     },
     {
         "BriefDescription": "Mispredicted unconditional branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.DIRECT",
         "SampleAfterValue": "20000",
@@ -215,7 +189,6 @@
     },
     {
         "BriefDescription": "Mispredicted non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
         "SampleAfterValue": "2000",
@@ -223,7 +196,6 @@
     },
     {
         "BriefDescription": "Mispredicted indirect call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
         "SampleAfterValue": "2000",
@@ -231,7 +203,6 @@
     },
     {
         "BriefDescription": "Mispredicted indirect non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
         "SampleAfterValue": "2000",
@@ -239,7 +210,6 @@
     },
     {
         "BriefDescription": "Mispredicted call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.NEAR_CALLS",
         "SampleAfterValue": "2000",
@@ -247,7 +217,6 @@
     },
     {
         "BriefDescription": "Mispredicted non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.NON_CALLS",
         "SampleAfterValue": "20000",
@@ -255,7 +224,6 @@
     },
     {
         "BriefDescription": "Mispredicted return branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.RETURN_NEAR",
         "SampleAfterValue": "2000",
@@ -263,7 +231,6 @@
     },
     {
         "BriefDescription": "Mispredicted taken branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN",
         "SampleAfterValue": "20000",
@@ -271,7 +238,6 @@
     },
     {
         "BriefDescription": "Mispredicted near retired calls (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -280,15 +246,11 @@
     },
     {
         "BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
-        "Counter": "Fixed counter 3",
-        "EventCode": "0x0",
         "EventName": "CPU_CLK_UNHALTED.REF",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_P",
         "SampleAfterValue": "100000",
@@ -296,33 +258,25 @@
     },
     {
         "BriefDescription": "Cycles when thread is not halted (fixed counter)",
-        "Counter": "Fixed counter 2",
-        "EventCode": "0x0",
         "EventName": "CPU_CLK_UNHALTED.THREAD",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Cycles when thread is not halted (programmable counter)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Total CPU cycles",
-        "Counter": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
         "Invert": "1",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Any Instruction Length Decoder stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.ANY",
         "SampleAfterValue": "2000000",
@@ -330,7 +284,6 @@
     },
     {
         "BriefDescription": "Instruction Queue full stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.IQ_FULL",
         "SampleAfterValue": "2000000",
@@ -338,7 +291,6 @@
     },
     {
         "BriefDescription": "Length Change Prefix stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.LCP",
         "SampleAfterValue": "2000000",
@@ -346,7 +298,6 @@
     },
     {
         "BriefDescription": "Stall cycles due to BPU MRU bypass",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.MRU",
         "SampleAfterValue": "2000000",
@@ -354,7 +305,6 @@
     },
     {
         "BriefDescription": "Regen stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.REGEN",
         "SampleAfterValue": "2000000",
@@ -362,7 +312,6 @@
     },
     {
         "BriefDescription": "Instructions that must be decoded by decoder 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "INST_DECODED.DEC0",
         "SampleAfterValue": "2000000",
@@ -370,7 +319,6 @@
     },
     {
         "BriefDescription": "Instructions written to instruction queue.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x17",
         "EventName": "INST_QUEUE_WRITES",
         "SampleAfterValue": "2000000",
@@ -378,7 +326,6 @@
     },
     {
         "BriefDescription": "Cycles instructions are written to the instruction queue",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
         "EventName": "INST_QUEUE_WRITE_CYCLES",
         "SampleAfterValue": "2000000",
@@ -386,15 +333,11 @@
     },
     {
         "BriefDescription": "Instructions retired (fixed counter)",
-        "Counter": "Fixed counter 1",
-        "EventCode": "0x0",
         "EventName": "INST_RETIRED.ANY",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.ANY_P",
         "PEBS": "1",
@@ -403,7 +346,6 @@
     },
     {
         "BriefDescription": "Retired MMX instructions (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.MMX",
         "PEBS": "1",
@@ -412,7 +354,6 @@
     },
     {
         "BriefDescription": "Total cycles (Precise Event)",
-        "Counter": "0,1,2,3",
         "CounterMask": "16",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.TOTAL_CYCLES",
@@ -423,7 +364,6 @@
     },
     {
         "BriefDescription": "Total cycles (Precise Event)",
-        "Counter": "0,1,2,3",
         "CounterMask": "16",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
@@ -434,7 +374,6 @@
     },
     {
         "BriefDescription": "Retired floating-point operations (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.X87",
         "PEBS": "1",
@@ -443,7 +382,6 @@
     },
     {
         "BriefDescription": "Load operations conflicting with software prefetches",
-        "Counter": "0,1",
         "EventCode": "0x4C",
         "EventName": "LOAD_HIT_PRE",
         "SampleAfterValue": "200000",
@@ -451,7 +389,6 @@
     },
     {
         "BriefDescription": "Cycles when uops were delivered by the LSD",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.ACTIVE",
@@ -460,7 +397,6 @@
     },
     {
         "BriefDescription": "Cycles no uops were delivered by the LSD",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.INACTIVE",
@@ -470,7 +406,6 @@
     },
     {
         "BriefDescription": "Loops that can't stream from the instruction queue",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "LSD_OVERFLOW",
         "SampleAfterValue": "2000000",
@@ -478,7 +413,6 @@
     },
     {
         "BriefDescription": "Cycles machine clear asserted",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.CYCLES",
         "SampleAfterValue": "20000",
@@ -486,7 +420,6 @@
     },
     {
         "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MEM_ORDER",
         "SampleAfterValue": "20000",
@@ -494,7 +427,6 @@
     },
     {
         "BriefDescription": "Self-Modifying Code detected",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.SMC",
         "SampleAfterValue": "20000",
@@ -502,7 +434,6 @@
     },
     {
         "BriefDescription": "All RAT stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.ANY",
         "SampleAfterValue": "2000000",
@@ -510,7 +441,6 @@
     },
     {
         "BriefDescription": "Flag stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.FLAGS",
         "SampleAfterValue": "2000000",
@@ -518,7 +448,6 @@
     },
     {
         "BriefDescription": "Partial register stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.REGISTERS",
         "SampleAfterValue": "2000000",
@@ -526,7 +455,6 @@
     },
     {
         "BriefDescription": "ROB read port stalls cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.ROB_READ_PORT",
         "SampleAfterValue": "2000000",
@@ -534,7 +462,6 @@
     },
     {
         "BriefDescription": "Scoreboard stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.SCOREBOARD",
         "SampleAfterValue": "2000000",
@@ -542,7 +469,6 @@
     },
     {
         "BriefDescription": "Resource related stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ANY",
         "SampleAfterValue": "2000000",
@@ -550,7 +476,6 @@
     },
     {
         "BriefDescription": "FPU control word write stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.FPCW",
         "SampleAfterValue": "2000000",
@@ -558,7 +483,6 @@
     },
     {
         "BriefDescription": "Load buffer stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.LOAD",
         "SampleAfterValue": "2000000",
@@ -566,7 +490,6 @@
     },
     {
         "BriefDescription": "MXCSR rename stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.MXCSR",
         "SampleAfterValue": "2000000",
@@ -574,7 +497,6 @@
     },
     {
         "BriefDescription": "Other Resource related stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.OTHER",
         "SampleAfterValue": "2000000",
@@ -582,7 +504,6 @@
     },
     {
         "BriefDescription": "ROB full stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ROB_FULL",
         "SampleAfterValue": "2000000",
@@ -590,7 +511,6 @@
     },
     {
         "BriefDescription": "Reservation Station full stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.RS_FULL",
         "SampleAfterValue": "2000000",
@@ -598,7 +518,6 @@
     },
     {
         "BriefDescription": "Store buffer stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.STORE",
         "SampleAfterValue": "2000000",
@@ -606,7 +525,6 @@
     },
     {
         "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
         "PEBS": "1",
@@ -615,7 +533,6 @@
     },
     {
         "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
         "PEBS": "1",
@@ -624,7 +541,6 @@
     },
     {
         "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
         "PEBS": "1",
@@ -633,7 +549,6 @@
     },
     {
         "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
         "PEBS": "1",
@@ -642,7 +557,6 @@
     },
     {
         "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
         "PEBS": "1",
@@ -651,7 +565,6 @@
     },
     {
         "BriefDescription": "Stack pointer instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "UOPS_DECODED.ESP_FOLDING",
         "SampleAfterValue": "2000000",
@@ -659,7 +572,6 @@
     },
     {
         "BriefDescription": "Stack pointer sync operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "UOPS_DECODED.ESP_SYNC",
         "SampleAfterValue": "2000000",
@@ -667,7 +579,6 @@
     },
     {
         "BriefDescription": "Uops decoded by Microcode Sequencer",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xD1",
         "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
@@ -676,7 +587,6 @@
     },
     {
         "BriefDescription": "Cycles no Uops are decoded",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xD1",
         "EventName": "UOPS_DECODED.STALL_CYCLES",
@@ -687,7 +597,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles Uops executed on any port (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
@@ -697,7 +606,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
@@ -707,7 +615,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops executed on any port (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xB1",
@@ -719,7 +626,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops executed on ports 0-4 (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xB1",
@@ -731,7 +637,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles no Uops issued on any port (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
@@ -742,7 +647,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
@@ -752,7 +656,6 @@
     },
     {
         "BriefDescription": "Uops executed on port 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT0",
         "SampleAfterValue": "2000000",
@@ -760,7 +663,6 @@
     },
     {
         "BriefDescription": "Uops issued on ports 0, 1 or 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT015",
         "SampleAfterValue": "2000000",
@@ -768,7 +670,6 @@
     },
     {
         "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
@@ -778,7 +679,6 @@
     },
     {
         "BriefDescription": "Uops executed on port 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT1",
         "SampleAfterValue": "2000000",
@@ -787,7 +687,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops issued on ports 2, 3 or 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT234_CORE",
         "SampleAfterValue": "2000000",
@@ -796,7 +695,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops executed on port 2 (core count)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT2_CORE",
         "SampleAfterValue": "2000000",
@@ -805,7 +703,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops executed on port 3 (core count)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT3_CORE",
         "SampleAfterValue": "2000000",
@@ -814,7 +711,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops executed on port 4 (core count)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT4_CORE",
         "SampleAfterValue": "2000000",
@@ -822,7 +718,6 @@
     },
     {
         "BriefDescription": "Uops executed on port 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT5",
         "SampleAfterValue": "2000000",
@@ -830,7 +725,6 @@
     },
     {
         "BriefDescription": "Uops issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.ANY",
         "SampleAfterValue": "2000000",
@@ -839,7 +733,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles no Uops were issued on any thread",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -850,7 +743,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles Uops were issued on either thread",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
@@ -859,7 +751,6 @@
     },
     {
         "BriefDescription": "Fused Uops issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.FUSED",
         "SampleAfterValue": "2000000",
@@ -867,7 +758,6 @@
     },
     {
         "BriefDescription": "Cycles no Uops were issued",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -877,7 +767,6 @@
     },
     {
         "BriefDescription": "Cycles Uops are being retired",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
@@ -887,7 +776,6 @@
     },
     {
         "BriefDescription": "Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ANY",
         "PEBS": "1",
@@ -896,7 +784,6 @@
     },
     {
         "BriefDescription": "Macro-fused Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.MACRO_FUSED",
         "PEBS": "1",
@@ -905,7 +792,6 @@
     },
     {
         "BriefDescription": "Retirement slots used (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
         "PEBS": "1",
@@ -914,7 +800,6 @@
     },
     {
         "BriefDescription": "Cycles Uops are not retiring (Precise Event)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -925,7 +810,6 @@
     },
     {
         "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
-        "Counter": "0,1,2,3",
         "CounterMask": "16",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
@@ -936,7 +820,6 @@
     },
     {
         "BriefDescription": "Uop unfusions due to FP exceptions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xDB",
         "EventName": "UOP_UNFUSION",
         "SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json b/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json
index e88c0802e6790..c434cd4ef4f1f 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "DTLB load misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.ANY",
         "SampleAfterValue": "200000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "DTLB load miss caused by low part of address",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.PDE_MISS",
         "SampleAfterValue": "200000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "DTLB second level hit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
         "SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "DTLB load miss page walks complete",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "DTLB misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.ANY",
         "SampleAfterValue": "200000",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "DTLB first level misses but second level hit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.STLB_HIT",
         "SampleAfterValue": "200000",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "DTLB miss page walks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
     },
     {
         "BriefDescription": "ITLB flushes",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAE",
         "EventName": "ITLB_FLUSH",
         "SampleAfterValue": "2000000",
@@ -65,7 +57,6 @@
     },
     {
         "BriefDescription": "ITLB miss",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.ANY",
         "SampleAfterValue": "200000",
@@ -73,7 +64,6 @@
     },
     {
         "BriefDescription": "ITLB miss page walks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -81,7 +71,6 @@
     },
     {
         "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC8",
         "EventName": "ITLB_MISS_RETIRED",
         "PEBS": "1",
@@ -90,7 +79,6 @@
     },
     {
         "BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
         "PEBS": "1",
@@ -99,7 +87,6 @@
     },
     {
         "BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC",
         "EventName": "MEM_STORE_RETIRED.DTLB_MISS",
         "PEBS": "1",
-- 
GitLab


From d4e50e519ba0af3ab961de74bd88366ea11f3e62 Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:55:00 -0800
Subject: [PATCH 584/875] perf vendor events intel: Refresh nehalemex events

Update the nehalemex events using the new tooling from:

  https://github.com/intel/perfmon

The events are unchanged but unused json values are removed. This
increases consistency across the json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-14-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../pmu-events/arch/x86/nehalemex/cache.json  | 519 ------------------
 .../arch/x86/nehalemex/floating-point.json    |  28 -
 .../arch/x86/nehalemex/frontend.json          |   3 -
 .../pmu-events/arch/x86/nehalemex/memory.json | 134 -----
 .../pmu-events/arch/x86/nehalemex/other.json  |  18 -
 .../arch/x86/nehalemex/pipeline.json          | 127 +----
 .../arch/x86/nehalemex/virtual-memory.json    |  13 -
 7 files changed, 5 insertions(+), 837 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/cache.json b/tools/perf/pmu-events/arch/x86/nehalemex/cache.json
index 01542c4ea6784..a4142cd2ca86e 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemex/cache.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemex/cache.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Cycles L1D locked",
-        "Counter": "0,1",
         "EventCode": "0x63",
         "EventName": "CACHE_LOCK_CYCLES.L1D",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Cycles L1D and L2 locked",
-        "Counter": "0,1",
         "EventCode": "0x63",
         "EventName": "CACHE_LOCK_CYCLES.L1D_L2",
         "SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "L1D cache lines replaced in M state",
-        "Counter": "0,1",
         "EventCode": "0x51",
         "EventName": "L1D.M_EVICT",
         "SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "L1D cache lines allocated in the M state",
-        "Counter": "0,1",
         "EventCode": "0x51",
         "EventName": "L1D.M_REPL",
         "SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "L1D snoop eviction of cache lines in M state",
-        "Counter": "0,1",
         "EventCode": "0x51",
         "EventName": "L1D.M_SNOOP_EVICT",
         "SampleAfterValue": "2000000",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "L1 data cache lines allocated",
-        "Counter": "0,1",
         "EventCode": "0x51",
         "EventName": "L1D.REPL",
         "SampleAfterValue": "2000000",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "All references to the L1 data cache",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "L1D_ALL_REF.ANY",
         "SampleAfterValue": "2000000",
@@ -57,7 +50,6 @@
     },
     {
         "BriefDescription": "L1 data cacheable reads and writes",
-        "Counter": "0,1",
         "EventCode": "0x43",
         "EventName": "L1D_ALL_REF.CACHEABLE",
         "SampleAfterValue": "2000000",
@@ -65,7 +57,6 @@
     },
     {
         "BriefDescription": "L1 data cache read in E state",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE_LD.E_STATE",
         "SampleAfterValue": "2000000",
@@ -73,7 +64,6 @@
     },
     {
         "BriefDescription": "L1 data cache read in I state (misses)",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE_LD.I_STATE",
         "SampleAfterValue": "2000000",
@@ -81,7 +71,6 @@
     },
     {
         "BriefDescription": "L1 data cache reads",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE_LD.MESI",
         "SampleAfterValue": "2000000",
@@ -89,7 +78,6 @@
     },
     {
         "BriefDescription": "L1 data cache read in M state",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE_LD.M_STATE",
         "SampleAfterValue": "2000000",
@@ -97,7 +85,6 @@
     },
     {
         "BriefDescription": "L1 data cache read in S state",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE_LD.S_STATE",
         "SampleAfterValue": "2000000",
@@ -105,7 +92,6 @@
     },
     {
         "BriefDescription": "L1 data cache load locks in E state",
-        "Counter": "0,1",
         "EventCode": "0x42",
         "EventName": "L1D_CACHE_LOCK.E_STATE",
         "SampleAfterValue": "2000000",
@@ -113,7 +99,6 @@
     },
     {
         "BriefDescription": "L1 data cache load lock hits",
-        "Counter": "0,1",
         "EventCode": "0x42",
         "EventName": "L1D_CACHE_LOCK.HIT",
         "SampleAfterValue": "2000000",
@@ -121,7 +106,6 @@
     },
     {
         "BriefDescription": "L1 data cache load locks in M state",
-        "Counter": "0,1",
         "EventCode": "0x42",
         "EventName": "L1D_CACHE_LOCK.M_STATE",
         "SampleAfterValue": "2000000",
@@ -129,7 +113,6 @@
     },
     {
         "BriefDescription": "L1 data cache load locks in S state",
-        "Counter": "0,1",
         "EventCode": "0x42",
         "EventName": "L1D_CACHE_LOCK.S_STATE",
         "SampleAfterValue": "2000000",
@@ -137,7 +120,6 @@
     },
     {
         "BriefDescription": "L1D load lock accepted in fill buffer",
-        "Counter": "0,1",
         "EventCode": "0x53",
         "EventName": "L1D_CACHE_LOCK_FB_HIT",
         "SampleAfterValue": "2000000",
@@ -145,7 +127,6 @@
     },
     {
         "BriefDescription": "L1D prefetch load lock accepted in fill buffer",
-        "Counter": "0,1",
         "EventCode": "0x52",
         "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
         "SampleAfterValue": "2000000",
@@ -153,7 +134,6 @@
     },
     {
         "BriefDescription": "L1 data cache stores in E state",
-        "Counter": "0,1",
         "EventCode": "0x41",
         "EventName": "L1D_CACHE_ST.E_STATE",
         "SampleAfterValue": "2000000",
@@ -161,7 +141,6 @@
     },
     {
         "BriefDescription": "L1 data cache stores in M state",
-        "Counter": "0,1",
         "EventCode": "0x41",
         "EventName": "L1D_CACHE_ST.M_STATE",
         "SampleAfterValue": "2000000",
@@ -169,7 +148,6 @@
     },
     {
         "BriefDescription": "L1 data cache stores in S state",
-        "Counter": "0,1",
         "EventCode": "0x41",
         "EventName": "L1D_CACHE_ST.S_STATE",
         "SampleAfterValue": "2000000",
@@ -177,7 +155,6 @@
     },
     {
         "BriefDescription": "L1D hardware prefetch misses",
-        "Counter": "0,1",
         "EventCode": "0x4E",
         "EventName": "L1D_PREFETCH.MISS",
         "SampleAfterValue": "200000",
@@ -185,7 +162,6 @@
     },
     {
         "BriefDescription": "L1D hardware prefetch requests",
-        "Counter": "0,1",
         "EventCode": "0x4E",
         "EventName": "L1D_PREFETCH.REQUESTS",
         "SampleAfterValue": "200000",
@@ -193,7 +169,6 @@
     },
     {
         "BriefDescription": "L1D hardware prefetch requests triggered",
-        "Counter": "0,1",
         "EventCode": "0x4E",
         "EventName": "L1D_PREFETCH.TRIGGERS",
         "SampleAfterValue": "200000",
@@ -201,7 +176,6 @@
     },
     {
         "BriefDescription": "L1 writebacks to L2 in E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.E_STATE",
         "SampleAfterValue": "100000",
@@ -209,7 +183,6 @@
     },
     {
         "BriefDescription": "L1 writebacks to L2 in I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.I_STATE",
         "SampleAfterValue": "100000",
@@ -217,7 +190,6 @@
     },
     {
         "BriefDescription": "All L1 writebacks to L2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.MESI",
         "SampleAfterValue": "100000",
@@ -225,7 +197,6 @@
     },
     {
         "BriefDescription": "L1 writebacks to L2 in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.M_STATE",
         "SampleAfterValue": "100000",
@@ -233,7 +204,6 @@
     },
     {
         "BriefDescription": "L1 writebacks to L2 in S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.S_STATE",
         "SampleAfterValue": "100000",
@@ -241,7 +211,6 @@
     },
     {
         "BriefDescription": "All L2 data requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.ANY",
         "SampleAfterValue": "200000",
@@ -249,7 +218,6 @@
     },
     {
         "BriefDescription": "L2 data demand loads in E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
         "SampleAfterValue": "200000",
@@ -257,7 +225,6 @@
     },
     {
         "BriefDescription": "L2 data demand loads in I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
         "SampleAfterValue": "200000",
@@ -265,7 +232,6 @@
     },
     {
         "BriefDescription": "L2 data demand requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.MESI",
         "SampleAfterValue": "200000",
@@ -273,7 +239,6 @@
     },
     {
         "BriefDescription": "L2 data demand loads in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
         "SampleAfterValue": "200000",
@@ -281,7 +246,6 @@
     },
     {
         "BriefDescription": "L2 data demand loads in S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
         "SampleAfterValue": "200000",
@@ -289,7 +253,6 @@
     },
     {
         "BriefDescription": "L2 data prefetches in E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
         "SampleAfterValue": "200000",
@@ -297,7 +260,6 @@
     },
     {
         "BriefDescription": "L2 data prefetches in the I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
         "SampleAfterValue": "200000",
@@ -305,7 +267,6 @@
     },
     {
         "BriefDescription": "All L2 data prefetches",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
         "SampleAfterValue": "200000",
@@ -313,7 +274,6 @@
     },
     {
         "BriefDescription": "L2 data prefetches in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
         "SampleAfterValue": "200000",
@@ -321,7 +281,6 @@
     },
     {
         "BriefDescription": "L2 data prefetches in the S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
         "SampleAfterValue": "200000",
@@ -329,7 +288,6 @@
     },
     {
         "BriefDescription": "L2 lines alloacated",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.ANY",
         "SampleAfterValue": "100000",
@@ -337,7 +295,6 @@
     },
     {
         "BriefDescription": "L2 lines allocated in the E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.E_STATE",
         "SampleAfterValue": "100000",
@@ -345,7 +302,6 @@
     },
     {
         "BriefDescription": "L2 lines allocated in the S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.S_STATE",
         "SampleAfterValue": "100000",
@@ -353,7 +309,6 @@
     },
     {
         "BriefDescription": "L2 lines evicted",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.ANY",
         "SampleAfterValue": "100000",
@@ -361,7 +316,6 @@
     },
     {
         "BriefDescription": "L2 lines evicted by a demand request",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
         "SampleAfterValue": "100000",
@@ -369,7 +323,6 @@
     },
     {
         "BriefDescription": "L2 modified lines evicted by a demand request",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
         "SampleAfterValue": "100000",
@@ -377,7 +330,6 @@
     },
     {
         "BriefDescription": "L2 lines evicted by a prefetch request",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
         "SampleAfterValue": "100000",
@@ -385,7 +337,6 @@
     },
     {
         "BriefDescription": "L2 modified lines evicted by a prefetch request",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
         "SampleAfterValue": "100000",
@@ -393,7 +344,6 @@
     },
     {
         "BriefDescription": "L2 instruction fetches",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.IFETCHES",
         "SampleAfterValue": "200000",
@@ -401,7 +351,6 @@
     },
     {
         "BriefDescription": "L2 instruction fetch hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.IFETCH_HIT",
         "SampleAfterValue": "200000",
@@ -409,7 +358,6 @@
     },
     {
         "BriefDescription": "L2 instruction fetch misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.IFETCH_MISS",
         "SampleAfterValue": "200000",
@@ -417,7 +365,6 @@
     },
     {
         "BriefDescription": "L2 load hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.LD_HIT",
         "SampleAfterValue": "200000",
@@ -425,7 +372,6 @@
     },
     {
         "BriefDescription": "L2 load misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.LD_MISS",
         "SampleAfterValue": "200000",
@@ -433,7 +379,6 @@
     },
     {
         "BriefDescription": "L2 requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.LOADS",
         "SampleAfterValue": "200000",
@@ -441,7 +386,6 @@
     },
     {
         "BriefDescription": "All L2 misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.MISS",
         "SampleAfterValue": "200000",
@@ -449,7 +393,6 @@
     },
     {
         "BriefDescription": "All L2 prefetches",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PREFETCHES",
         "SampleAfterValue": "200000",
@@ -457,7 +400,6 @@
     },
     {
         "BriefDescription": "L2 prefetch hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PREFETCH_HIT",
         "SampleAfterValue": "200000",
@@ -465,7 +407,6 @@
     },
     {
         "BriefDescription": "L2 prefetch misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PREFETCH_MISS",
         "SampleAfterValue": "200000",
@@ -473,7 +414,6 @@
     },
     {
         "BriefDescription": "All L2 requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.REFERENCES",
         "SampleAfterValue": "200000",
@@ -481,7 +421,6 @@
     },
     {
         "BriefDescription": "L2 RFO requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFOS",
         "SampleAfterValue": "200000",
@@ -489,7 +428,6 @@
     },
     {
         "BriefDescription": "L2 RFO hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_HIT",
         "SampleAfterValue": "200000",
@@ -497,7 +435,6 @@
     },
     {
         "BriefDescription": "L2 RFO misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_MISS",
         "SampleAfterValue": "200000",
@@ -505,7 +442,6 @@
     },
     {
         "BriefDescription": "All L2 transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.ANY",
         "SampleAfterValue": "200000",
@@ -513,7 +449,6 @@
     },
     {
         "BriefDescription": "L2 fill transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.FILL",
         "SampleAfterValue": "200000",
@@ -521,7 +456,6 @@
     },
     {
         "BriefDescription": "L2 instruction fetch transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.IFETCH",
         "SampleAfterValue": "200000",
@@ -529,7 +463,6 @@
     },
     {
         "BriefDescription": "L1D writeback to L2 transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.L1D_WB",
         "SampleAfterValue": "200000",
@@ -537,7 +470,6 @@
     },
     {
         "BriefDescription": "L2 Load transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.LOAD",
         "SampleAfterValue": "200000",
@@ -545,7 +477,6 @@
     },
     {
         "BriefDescription": "L2 prefetch transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.PREFETCH",
         "SampleAfterValue": "200000",
@@ -553,7 +484,6 @@
     },
     {
         "BriefDescription": "L2 RFO transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.RFO",
         "SampleAfterValue": "200000",
@@ -561,7 +491,6 @@
     },
     {
         "BriefDescription": "L2 writeback to LLC transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.WB",
         "SampleAfterValue": "200000",
@@ -569,7 +498,6 @@
     },
     {
         "BriefDescription": "L2 demand lock RFOs in E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.E_STATE",
         "SampleAfterValue": "100000",
@@ -577,7 +505,6 @@
     },
     {
         "BriefDescription": "All demand L2 lock RFOs that hit the cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.HIT",
         "SampleAfterValue": "100000",
@@ -585,7 +512,6 @@
     },
     {
         "BriefDescription": "L2 demand lock RFOs in I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.I_STATE",
         "SampleAfterValue": "100000",
@@ -593,7 +519,6 @@
     },
     {
         "BriefDescription": "All demand L2 lock RFOs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.MESI",
         "SampleAfterValue": "100000",
@@ -601,7 +526,6 @@
     },
     {
         "BriefDescription": "L2 demand lock RFOs in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.M_STATE",
         "SampleAfterValue": "100000",
@@ -609,7 +533,6 @@
     },
     {
         "BriefDescription": "L2 demand lock RFOs in S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.S_STATE",
         "SampleAfterValue": "100000",
@@ -617,7 +540,6 @@
     },
     {
         "BriefDescription": "All L2 demand store RFOs that hit the cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.HIT",
         "SampleAfterValue": "100000",
@@ -625,7 +547,6 @@
     },
     {
         "BriefDescription": "L2 demand store RFOs in I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.I_STATE",
         "SampleAfterValue": "100000",
@@ -633,7 +554,6 @@
     },
     {
         "BriefDescription": "All L2 demand store RFOs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.MESI",
         "SampleAfterValue": "100000",
@@ -641,7 +561,6 @@
     },
     {
         "BriefDescription": "L2 demand store RFOs in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.M_STATE",
         "SampleAfterValue": "100000",
@@ -649,7 +568,6 @@
     },
     {
         "BriefDescription": "L2 demand store RFOs in S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.S_STATE",
         "SampleAfterValue": "100000",
@@ -657,7 +575,6 @@
     },
     {
         "BriefDescription": "Longest latency cache miss",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.MISS",
         "SampleAfterValue": "100000",
@@ -665,7 +582,6 @@
     },
     {
         "BriefDescription": "Longest latency cache reference",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
         "SampleAfterValue": "200000",
@@ -673,18 +589,15 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
         "MSRIndex": "0x3F6",
-        "MSRValue": "0x0",
         "PEBS": "2",
         "SampleAfterValue": "2000000",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
         "MSRIndex": "0x3F6",
@@ -695,7 +608,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
         "MSRIndex": "0x3F6",
@@ -706,7 +618,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
         "MSRIndex": "0x3F6",
@@ -717,7 +628,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
         "MSRIndex": "0x3F6",
@@ -728,7 +638,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
         "MSRIndex": "0x3F6",
@@ -739,7 +648,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
         "MSRIndex": "0x3F6",
@@ -750,7 +658,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
         "MSRIndex": "0x3F6",
@@ -761,7 +668,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
         "MSRIndex": "0x3F6",
@@ -772,7 +678,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
         "MSRIndex": "0x3F6",
@@ -783,7 +688,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
         "MSRIndex": "0x3F6",
@@ -794,7 +698,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
         "MSRIndex": "0x3F6",
@@ -805,7 +708,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
         "MSRIndex": "0x3F6",
@@ -816,7 +718,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
         "MSRIndex": "0x3F6",
@@ -827,7 +728,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
         "MSRIndex": "0x3F6",
@@ -838,7 +738,6 @@
     },
     {
         "BriefDescription": "Instructions retired which contains a load (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LOADS",
         "PEBS": "1",
@@ -847,7 +746,6 @@
     },
     {
         "BriefDescription": "Instructions retired which contains a store (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.STORES",
         "PEBS": "1",
@@ -856,7 +754,6 @@
     },
     {
         "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.HIT_LFB",
         "PEBS": "1",
@@ -865,7 +762,6 @@
     },
     {
         "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.L1D_HIT",
         "PEBS": "1",
@@ -874,7 +770,6 @@
     },
     {
         "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.L2_HIT",
         "PEBS": "1",
@@ -883,7 +778,6 @@
     },
     {
         "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.LLC_MISS",
         "PEBS": "1",
@@ -892,7 +786,6 @@
     },
     {
         "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
         "PEBS": "1",
@@ -901,7 +794,6 @@
     },
     {
         "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
         "PEBS": "1",
@@ -910,7 +802,6 @@
     },
     {
         "BriefDescription": "Offcore L1 data cache writebacks",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
         "SampleAfterValue": "100000",
@@ -918,7 +809,6 @@
     },
     {
         "BriefDescription": "Offcore requests blocked due to Super Queue full",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "OFFCORE_REQUESTS_SQ_FULL",
         "SampleAfterValue": "100000",
@@ -926,2240 +816,1833 @@
     },
     {
         "BriefDescription": "Offcore data reads satisfied by any cache or DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F11",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore data reads",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF11",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x111",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x211",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x411",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x711",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4711",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1811",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3811",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x811",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by any cache or DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F44",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore code reads",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF44",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x144",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x244",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x444",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x744",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4744",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1844",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3844",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x844",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by any cache or DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7FFF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFFFF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x80FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x47FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x18FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x38FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x10FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F22",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore RFO requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF22",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x122",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x222",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x422",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x722",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4722",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1822",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3822",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x822",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F08",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore writebacks",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF08",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x108",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x408",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x708",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4708",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1808",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3808",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x808",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F77",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore code or data read requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF77",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x177",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x277",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x477",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x777",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4777",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1877",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3877",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x877",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = any cache_dram",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F33",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = any location",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF33",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x133",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x233",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x433",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = local cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x733",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = local cache or dram",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4733",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1833",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = remote cache or dram",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3833",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x833",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F03",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore demand data requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF03",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x103",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x203",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x403",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x703",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4703",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1803",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3803",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x803",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F01",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore demand data reads",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF01",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x101",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x201",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x401",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x701",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4701",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1801",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3801",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x801",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F04",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore demand code reads",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF04",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x104",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x204",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x404",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x704",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4704",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1804",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3804",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x804",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F02",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore demand RFO requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF02",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x102",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x202",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x402",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x702",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4702",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1802",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3802",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x802",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F80",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore other requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF80",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8080",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x180",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x280",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x480",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x780",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4780",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1880",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3880",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1080",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x880",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F30",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore prefetch data requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF30",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8030",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x130",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x230",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x430",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x730",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4730",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1830",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3830",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1030",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x830",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F10",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore prefetch data reads",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF10",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x110",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x210",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x410",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x710",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4710",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1810",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3810",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x810",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F40",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore prefetch code reads",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF40",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x140",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x240",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x440",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x740",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4740",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1840",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3840",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x840",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F20",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore prefetch RFO requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF20",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x120",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x220",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x420",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x720",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4720",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1820",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3820",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x820",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F70",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore prefetch requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF70",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x170",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x270",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x470",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x770",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4770",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1870",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3870",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x870",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Super Queue lock splits across a cache line",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF4",
         "EventName": "SQ_MISC.SPLIT_LOCK",
         "SampleAfterValue": "2000000",
@@ -3167,7 +2650,6 @@
     },
     {
         "BriefDescription": "Loads delayed with at-Retirement block code",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "STORE_BLOCKS.AT_RET",
         "SampleAfterValue": "200000",
@@ -3175,7 +2657,6 @@
     },
     {
         "BriefDescription": "Cacheable loads delayed with L1D block code",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "STORE_BLOCKS.L1D_BLOCK",
         "SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json b/tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json
index 666e466d351c4..c03f8990fa82a 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "X87 Floating point assists (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF7",
         "EventName": "FP_ASSIST.ALL",
         "PEBS": "1",
@@ -10,7 +9,6 @@
     },
     {
         "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF7",
         "EventName": "FP_ASSIST.INPUT",
         "PEBS": "1",
@@ -19,7 +17,6 @@
     },
     {
         "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF7",
         "EventName": "FP_ASSIST.OUTPUT",
         "PEBS": "1",
@@ -28,7 +25,6 @@
     },
     {
         "BriefDescription": "MMX Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.MMX",
         "SampleAfterValue": "2000000",
@@ -36,7 +32,6 @@
     },
     {
         "BriefDescription": "SSE2 integer Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
         "SampleAfterValue": "2000000",
@@ -44,7 +39,6 @@
     },
     {
         "BriefDescription": "SSE* FP double precision Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
         "SampleAfterValue": "2000000",
@@ -52,7 +46,6 @@
     },
     {
         "BriefDescription": "SSE and SSE2 FP Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_FP",
         "SampleAfterValue": "2000000",
@@ -60,7 +53,6 @@
     },
     {
         "BriefDescription": "SSE FP packed Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
         "SampleAfterValue": "2000000",
@@ -68,7 +60,6 @@
     },
     {
         "BriefDescription": "SSE FP scalar Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
         "SampleAfterValue": "2000000",
@@ -76,7 +67,6 @@
     },
     {
         "BriefDescription": "SSE* FP single precision Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
         "SampleAfterValue": "2000000",
@@ -84,7 +74,6 @@
     },
     {
         "BriefDescription": "Computational floating-point operations executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.X87",
         "SampleAfterValue": "2000000",
@@ -92,7 +81,6 @@
     },
     {
         "BriefDescription": "All Floating Point to and from MMX transitions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCC",
         "EventName": "FP_MMX_TRANS.ANY",
         "SampleAfterValue": "2000000",
@@ -100,7 +88,6 @@
     },
     {
         "BriefDescription": "Transitions from MMX to Floating Point instructions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCC",
         "EventName": "FP_MMX_TRANS.TO_FP",
         "SampleAfterValue": "2000000",
@@ -108,7 +95,6 @@
     },
     {
         "BriefDescription": "Transitions from Floating Point to MMX instructions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCC",
         "EventName": "FP_MMX_TRANS.TO_MMX",
         "SampleAfterValue": "2000000",
@@ -116,7 +102,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer pack operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACK",
         "SampleAfterValue": "200000",
@@ -124,7 +109,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer arithmetic operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_ARITH",
         "SampleAfterValue": "200000",
@@ -132,7 +116,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer logical operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_LOGICAL",
         "SampleAfterValue": "200000",
@@ -140,7 +123,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer multiply operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_MPY",
         "SampleAfterValue": "200000",
@@ -148,7 +130,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer shift operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_SHIFT",
         "SampleAfterValue": "200000",
@@ -156,7 +137,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer shuffle/move operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.SHUFFLE_MOVE",
         "SampleAfterValue": "200000",
@@ -164,7 +144,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer unpack operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.UNPACK",
         "SampleAfterValue": "200000",
@@ -172,7 +151,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit pack operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACK",
         "SampleAfterValue": "200000",
@@ -180,7 +158,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit arithmetic operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_ARITH",
         "SampleAfterValue": "200000",
@@ -188,7 +165,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit logical operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_LOGICAL",
         "SampleAfterValue": "200000",
@@ -196,7 +172,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit packed multiply operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_MPY",
         "SampleAfterValue": "200000",
@@ -204,7 +179,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit shift operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_SHIFT",
         "SampleAfterValue": "200000",
@@ -212,7 +186,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit shuffle/move operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.SHUFFLE_MOVE",
         "SampleAfterValue": "200000",
@@ -220,7 +193,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit unpack operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.UNPACK",
         "SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/frontend.json b/tools/perf/pmu-events/arch/x86/nehalemex/frontend.json
index c561ac24d91d1..f7f28510e3ae9 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemex/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemex/frontend.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MACRO_INSTS.DECODED",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Macro-fused instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA6",
         "EventName": "MACRO_INSTS.FUSIONS_DECODED",
         "SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "Two Uop instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "TWO_UOP_INSTS_DECODED",
         "SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/memory.json b/tools/perf/pmu-events/arch/x86/nehalemex/memory.json
index 6e95de3f34093..f810880a295e9 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemex/memory.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemex/memory.json
@@ -1,738 +1,604 @@
 [
     {
         "BriefDescription": "Offcore data reads satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF811",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF844",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x60FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF8FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x40FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x20FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF822",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF808",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF877",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = any LLC miss",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF833",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the local DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF803",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF801",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF804",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF802",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6080",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF880",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2080",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6030",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF830",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4030",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2030",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF810",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF840",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF820",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF870",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     }
diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/other.json b/tools/perf/pmu-events/arch/x86/nehalemex/other.json
index f6887b234b0e5..fb706cb518322 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemex/other.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemex/other.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "ES segment renames",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD5",
         "EventName": "ES_REG_RENAMES",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "I/O transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6C",
         "EventName": "IO_TRANSACTIONS",
         "SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "L1I instruction fetch stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.CYCLES_STALLED",
         "SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "L1I instruction fetch hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.HITS",
         "SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "L1I instruction fetch misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.MISSES",
         "SampleAfterValue": "2000000",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "L1I Instruction fetches",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.READS",
         "SampleAfterValue": "2000000",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "Large ITLB hit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x82",
         "EventName": "LARGE_ITLB.HIT",
         "SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
     },
     {
         "BriefDescription": "All loads dispatched",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.ANY",
         "SampleAfterValue": "2000000",
@@ -65,7 +57,6 @@
     },
     {
         "BriefDescription": "Loads dispatched from the MOB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.MOB",
         "SampleAfterValue": "2000000",
@@ -73,7 +64,6 @@
     },
     {
         "BriefDescription": "Loads dispatched that bypass the MOB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.RS",
         "SampleAfterValue": "2000000",
@@ -81,7 +71,6 @@
     },
     {
         "BriefDescription": "Loads dispatched from stage 305",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.RS_DELAYED",
         "SampleAfterValue": "2000000",
@@ -89,7 +78,6 @@
     },
     {
         "BriefDescription": "False dependencies due to partial address aliasing",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "PARTIAL_ADDRESS_ALIAS",
         "SampleAfterValue": "200000",
@@ -97,7 +85,6 @@
     },
     {
         "BriefDescription": "All Store buffer stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "SB_DRAIN.ANY",
         "SampleAfterValue": "200000",
@@ -105,7 +92,6 @@
     },
     {
         "BriefDescription": "Segment rename stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD4",
         "EventName": "SEG_RENAME_STALLS",
         "SampleAfterValue": "2000000",
@@ -113,7 +99,6 @@
     },
     {
         "BriefDescription": "Thread responded HIT to snoop",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "SNOOP_RESPONSE.HIT",
         "SampleAfterValue": "100000",
@@ -121,7 +106,6 @@
     },
     {
         "BriefDescription": "Thread responded HITE to snoop",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "SNOOP_RESPONSE.HITE",
         "SampleAfterValue": "100000",
@@ -129,7 +113,6 @@
     },
     {
         "BriefDescription": "Thread responded HITM to snoop",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "SNOOP_RESPONSE.HITM",
         "SampleAfterValue": "100000",
@@ -137,7 +120,6 @@
     },
     {
         "BriefDescription": "Super Queue full stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF6",
         "EventName": "SQ_FULL_STALL_CYCLES",
         "SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json b/tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json
index 6fc1a6efd8e89..c45f2ffa861e4 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Cycles the divider is busy",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "ARITH.CYCLES_DIV_BUSY",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Divide Operations executed",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x14",
@@ -20,7 +18,6 @@
     },
     {
         "BriefDescription": "Multiply operations executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "ARITH.MUL",
         "SampleAfterValue": "2000000",
@@ -28,7 +25,6 @@
     },
     {
         "BriefDescription": "BACLEAR asserted with bad target address",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE6",
         "EventName": "BACLEAR.BAD_TARGET",
         "SampleAfterValue": "2000000",
@@ -36,7 +32,6 @@
     },
     {
         "BriefDescription": "BACLEAR asserted, regardless of cause",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE6",
         "EventName": "BACLEAR.CLEAR",
         "SampleAfterValue": "2000000",
@@ -44,7 +39,6 @@
     },
     {
         "BriefDescription": "Instruction queue forced BACLEAR",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA7",
         "EventName": "BACLEAR_FORCE_IQ",
         "SampleAfterValue": "2000000",
@@ -52,7 +46,6 @@
     },
     {
         "BriefDescription": "Early Branch Prediciton Unit clears",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE8",
         "EventName": "BPU_CLEARS.EARLY",
         "SampleAfterValue": "2000000",
@@ -60,7 +53,6 @@
     },
     {
         "BriefDescription": "Late Branch Prediction Unit clears",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE8",
         "EventName": "BPU_CLEARS.LATE",
         "SampleAfterValue": "2000000",
@@ -68,7 +60,6 @@
     },
     {
         "BriefDescription": "Branch prediction unit missed call or return",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE5",
         "EventName": "BPU_MISSED_CALL_RET",
         "SampleAfterValue": "2000000",
@@ -76,7 +67,6 @@
     },
     {
         "BriefDescription": "Branch instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE0",
         "EventName": "BR_INST_DECODED",
         "SampleAfterValue": "2000000",
@@ -84,7 +74,6 @@
     },
     {
         "BriefDescription": "Branch instructions executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ANY",
         "SampleAfterValue": "200000",
@@ -92,7 +81,6 @@
     },
     {
         "BriefDescription": "Conditional branch instructions executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.COND",
         "SampleAfterValue": "200000",
@@ -100,7 +88,6 @@
     },
     {
         "BriefDescription": "Unconditional branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.DIRECT",
         "SampleAfterValue": "200000",
@@ -108,7 +95,6 @@
     },
     {
         "BriefDescription": "Unconditional call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
         "SampleAfterValue": "20000",
@@ -116,7 +102,6 @@
     },
     {
         "BriefDescription": "Indirect call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
         "SampleAfterValue": "20000",
@@ -124,7 +109,6 @@
     },
     {
         "BriefDescription": "Indirect non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
         "SampleAfterValue": "20000",
@@ -132,7 +116,6 @@
     },
     {
         "BriefDescription": "Call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.NEAR_CALLS",
         "SampleAfterValue": "20000",
@@ -140,7 +123,6 @@
     },
     {
         "BriefDescription": "All non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.NON_CALLS",
         "SampleAfterValue": "200000",
@@ -148,7 +130,6 @@
     },
     {
         "BriefDescription": "Indirect return branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.RETURN_NEAR",
         "SampleAfterValue": "20000",
@@ -156,7 +137,6 @@
     },
     {
         "BriefDescription": "Taken branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN",
         "SampleAfterValue": "200000",
@@ -164,7 +144,6 @@
     },
     {
         "BriefDescription": "Retired branch instructions (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
@@ -173,7 +152,6 @@
     },
     {
         "BriefDescription": "Retired conditional branch instructions (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -182,7 +160,6 @@
     },
     {
         "BriefDescription": "Retired near call instructions (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -191,7 +168,6 @@
     },
     {
         "BriefDescription": "Mispredicted branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ANY",
         "SampleAfterValue": "20000",
@@ -199,7 +175,6 @@
     },
     {
         "BriefDescription": "Mispredicted conditional branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.COND",
         "SampleAfterValue": "20000",
@@ -207,7 +182,6 @@
     },
     {
         "BriefDescription": "Mispredicted unconditional branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.DIRECT",
         "SampleAfterValue": "20000",
@@ -215,7 +189,6 @@
     },
     {
         "BriefDescription": "Mispredicted non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
         "SampleAfterValue": "2000",
@@ -223,7 +196,6 @@
     },
     {
         "BriefDescription": "Mispredicted indirect call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
         "SampleAfterValue": "2000",
@@ -231,7 +203,6 @@
     },
     {
         "BriefDescription": "Mispredicted indirect non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
         "SampleAfterValue": "2000",
@@ -239,7 +210,6 @@
     },
     {
         "BriefDescription": "Mispredicted call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.NEAR_CALLS",
         "SampleAfterValue": "2000",
@@ -247,7 +217,6 @@
     },
     {
         "BriefDescription": "Mispredicted non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.NON_CALLS",
         "SampleAfterValue": "20000",
@@ -255,7 +224,6 @@
     },
     {
         "BriefDescription": "Mispredicted return branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.RETURN_NEAR",
         "SampleAfterValue": "2000",
@@ -263,7 +231,6 @@
     },
     {
         "BriefDescription": "Mispredicted taken branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN",
         "SampleAfterValue": "20000",
@@ -271,7 +238,6 @@
     },
     {
         "BriefDescription": "Mispredicted near retired calls (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -280,15 +246,11 @@
     },
     {
         "BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
-        "Counter": "Fixed counter 3",
-        "EventCode": "0x0",
         "EventName": "CPU_CLK_UNHALTED.REF",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_P",
         "SampleAfterValue": "100000",
@@ -296,33 +258,25 @@
     },
     {
         "BriefDescription": "Cycles when thread is not halted (fixed counter)",
-        "Counter": "Fixed counter 2",
-        "EventCode": "0x0",
         "EventName": "CPU_CLK_UNHALTED.THREAD",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Cycles when thread is not halted (programmable counter)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Total CPU cycles",
-        "Counter": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
         "Invert": "1",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Any Instruction Length Decoder stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.ANY",
         "SampleAfterValue": "2000000",
@@ -330,7 +284,6 @@
     },
     {
         "BriefDescription": "Instruction Queue full stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.IQ_FULL",
         "SampleAfterValue": "2000000",
@@ -338,7 +291,6 @@
     },
     {
         "BriefDescription": "Length Change Prefix stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.LCP",
         "SampleAfterValue": "2000000",
@@ -346,7 +298,6 @@
     },
     {
         "BriefDescription": "Stall cycles due to BPU MRU bypass",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.MRU",
         "SampleAfterValue": "2000000",
@@ -354,7 +305,6 @@
     },
     {
         "BriefDescription": "Regen stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.REGEN",
         "SampleAfterValue": "2000000",
@@ -362,7 +312,6 @@
     },
     {
         "BriefDescription": "Instructions that must be decoded by decoder 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "INST_DECODED.DEC0",
         "SampleAfterValue": "2000000",
@@ -370,7 +319,6 @@
     },
     {
         "BriefDescription": "Instructions written to instruction queue.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x17",
         "EventName": "INST_QUEUE_WRITES",
         "SampleAfterValue": "2000000",
@@ -378,7 +326,6 @@
     },
     {
         "BriefDescription": "Cycles instructions are written to the instruction queue",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
         "EventName": "INST_QUEUE_WRITE_CYCLES",
         "SampleAfterValue": "2000000",
@@ -386,15 +333,11 @@
     },
     {
         "BriefDescription": "Instructions retired (fixed counter)",
-        "Counter": "Fixed counter 1",
-        "EventCode": "0x0",
         "EventName": "INST_RETIRED.ANY",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.ANY_P",
         "PEBS": "1",
@@ -403,7 +346,6 @@
     },
     {
         "BriefDescription": "Retired MMX instructions (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.MMX",
         "PEBS": "1",
@@ -412,7 +354,6 @@
     },
     {
         "BriefDescription": "Total cycles (Precise Event)",
-        "Counter": "0,1,2,3",
         "CounterMask": "16",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.TOTAL_CYCLES",
@@ -423,7 +364,6 @@
     },
     {
         "BriefDescription": "Total cycles (Precise Event)",
-        "Counter": "0,1,2,3",
         "CounterMask": "16",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
@@ -434,7 +374,6 @@
     },
     {
         "BriefDescription": "Retired floating-point operations (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.X87",
         "PEBS": "1",
@@ -443,7 +382,6 @@
     },
     {
         "BriefDescription": "Load operations conflicting with software prefetches",
-        "Counter": "0,1",
         "EventCode": "0x4C",
         "EventName": "LOAD_HIT_PRE",
         "SampleAfterValue": "200000",
@@ -451,7 +389,6 @@
     },
     {
         "BriefDescription": "Cycles when uops were delivered by the LSD",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.ACTIVE",
@@ -460,7 +397,6 @@
     },
     {
         "BriefDescription": "Cycles no uops were delivered by the LSD",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.INACTIVE",
@@ -470,7 +406,6 @@
     },
     {
         "BriefDescription": "Loops that can't stream from the instruction queue",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "LSD_OVERFLOW",
         "SampleAfterValue": "2000000",
@@ -478,7 +413,6 @@
     },
     {
         "BriefDescription": "Cycles machine clear asserted",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.CYCLES",
         "SampleAfterValue": "20000",
@@ -486,7 +420,6 @@
     },
     {
         "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MEM_ORDER",
         "SampleAfterValue": "20000",
@@ -494,7 +427,6 @@
     },
     {
         "BriefDescription": "Self-Modifying Code detected",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.SMC",
         "SampleAfterValue": "20000",
@@ -502,7 +434,6 @@
     },
     {
         "BriefDescription": "All RAT stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.ANY",
         "SampleAfterValue": "2000000",
@@ -510,7 +441,6 @@
     },
     {
         "BriefDescription": "Flag stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.FLAGS",
         "SampleAfterValue": "2000000",
@@ -518,7 +448,6 @@
     },
     {
         "BriefDescription": "Partial register stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.REGISTERS",
         "SampleAfterValue": "2000000",
@@ -526,7 +455,6 @@
     },
     {
         "BriefDescription": "ROB read port stalls cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.ROB_READ_PORT",
         "SampleAfterValue": "2000000",
@@ -534,7 +462,6 @@
     },
     {
         "BriefDescription": "Scoreboard stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.SCOREBOARD",
         "SampleAfterValue": "2000000",
@@ -542,7 +469,6 @@
     },
     {
         "BriefDescription": "Resource related stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ANY",
         "SampleAfterValue": "2000000",
@@ -550,7 +476,6 @@
     },
     {
         "BriefDescription": "FPU control word write stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.FPCW",
         "SampleAfterValue": "2000000",
@@ -558,7 +483,6 @@
     },
     {
         "BriefDescription": "Load buffer stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.LOAD",
         "SampleAfterValue": "2000000",
@@ -566,7 +490,6 @@
     },
     {
         "BriefDescription": "MXCSR rename stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.MXCSR",
         "SampleAfterValue": "2000000",
@@ -574,7 +497,6 @@
     },
     {
         "BriefDescription": "Other Resource related stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.OTHER",
         "SampleAfterValue": "2000000",
@@ -582,7 +504,6 @@
     },
     {
         "BriefDescription": "ROB full stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ROB_FULL",
         "SampleAfterValue": "2000000",
@@ -590,7 +511,6 @@
     },
     {
         "BriefDescription": "Reservation Station full stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.RS_FULL",
         "SampleAfterValue": "2000000",
@@ -598,7 +518,6 @@
     },
     {
         "BriefDescription": "Store buffer stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.STORE",
         "SampleAfterValue": "2000000",
@@ -606,7 +525,6 @@
     },
     {
         "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
         "PEBS": "1",
@@ -615,7 +533,6 @@
     },
     {
         "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
         "PEBS": "1",
@@ -624,7 +541,6 @@
     },
     {
         "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
         "PEBS": "1",
@@ -633,7 +549,6 @@
     },
     {
         "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
         "PEBS": "1",
@@ -642,7 +557,6 @@
     },
     {
         "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
         "PEBS": "1",
@@ -651,7 +565,6 @@
     },
     {
         "BriefDescription": "Stack pointer instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "UOPS_DECODED.ESP_FOLDING",
         "SampleAfterValue": "2000000",
@@ -659,7 +572,6 @@
     },
     {
         "BriefDescription": "Stack pointer sync operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "UOPS_DECODED.ESP_SYNC",
         "SampleAfterValue": "2000000",
@@ -667,7 +579,6 @@
     },
     {
         "BriefDescription": "Uops decoded by Microcode Sequencer",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xD1",
         "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
@@ -676,7 +587,6 @@
     },
     {
         "BriefDescription": "Cycles no Uops are decoded",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xD1",
         "EventName": "UOPS_DECODED.STALL_CYCLES",
@@ -687,7 +597,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles Uops executed on any port (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
@@ -697,7 +606,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
@@ -707,7 +615,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops executed on any port (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xB1",
@@ -719,7 +626,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops executed on ports 0-4 (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xB1",
@@ -731,7 +637,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles no Uops issued on any port (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
@@ -742,7 +647,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
@@ -752,7 +656,6 @@
     },
     {
         "BriefDescription": "Uops executed on port 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT0",
         "SampleAfterValue": "2000000",
@@ -760,7 +663,6 @@
     },
     {
         "BriefDescription": "Uops issued on ports 0, 1 or 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT015",
         "SampleAfterValue": "2000000",
@@ -768,7 +670,6 @@
     },
     {
         "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
@@ -778,7 +679,6 @@
     },
     {
         "BriefDescription": "Uops executed on port 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT1",
         "SampleAfterValue": "2000000",
@@ -787,7 +687,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops issued on ports 2, 3 or 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT234_CORE",
         "SampleAfterValue": "2000000",
@@ -796,7 +695,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops executed on port 2 (core count)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT2_CORE",
         "SampleAfterValue": "2000000",
@@ -805,7 +703,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops executed on port 3 (core count)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT3_CORE",
         "SampleAfterValue": "2000000",
@@ -814,7 +711,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops executed on port 4 (core count)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT4_CORE",
         "SampleAfterValue": "2000000",
@@ -822,7 +718,6 @@
     },
     {
         "BriefDescription": "Uops executed on port 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT5",
         "SampleAfterValue": "2000000",
@@ -830,7 +725,6 @@
     },
     {
         "BriefDescription": "Uops issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.ANY",
         "SampleAfterValue": "2000000",
@@ -839,7 +733,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles no Uops were issued on any thread",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -850,7 +743,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles Uops were issued on either thread",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
@@ -859,7 +751,6 @@
     },
     {
         "BriefDescription": "Fused Uops issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.FUSED",
         "SampleAfterValue": "2000000",
@@ -867,7 +758,6 @@
     },
     {
         "BriefDescription": "Cycles no Uops were issued",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -877,7 +767,6 @@
     },
     {
         "BriefDescription": "Cycles Uops are being retired",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
@@ -887,7 +776,6 @@
     },
     {
         "BriefDescription": "Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ANY",
         "PEBS": "1",
@@ -896,7 +784,6 @@
     },
     {
         "BriefDescription": "Macro-fused Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.MACRO_FUSED",
         "PEBS": "1",
@@ -905,7 +792,6 @@
     },
     {
         "BriefDescription": "Retirement slots used (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
         "PEBS": "1",
@@ -914,7 +800,6 @@
     },
     {
         "BriefDescription": "Cycles Uops are not retiring (Precise Event)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -925,7 +810,6 @@
     },
     {
         "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
-        "Counter": "0,1,2,3",
         "CounterMask": "16",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
@@ -936,7 +820,6 @@
     },
     {
         "BriefDescription": "Uop unfusions due to FP exceptions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xDB",
         "EventName": "UOP_UNFUSION",
         "SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json b/tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json
index e88c0802e6790..c434cd4ef4f1f 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "DTLB load misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.ANY",
         "SampleAfterValue": "200000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "DTLB load miss caused by low part of address",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.PDE_MISS",
         "SampleAfterValue": "200000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "DTLB second level hit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
         "SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "DTLB load miss page walks complete",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "DTLB misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.ANY",
         "SampleAfterValue": "200000",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "DTLB first level misses but second level hit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.STLB_HIT",
         "SampleAfterValue": "200000",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "DTLB miss page walks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
     },
     {
         "BriefDescription": "ITLB flushes",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAE",
         "EventName": "ITLB_FLUSH",
         "SampleAfterValue": "2000000",
@@ -65,7 +57,6 @@
     },
     {
         "BriefDescription": "ITLB miss",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.ANY",
         "SampleAfterValue": "200000",
@@ -73,7 +64,6 @@
     },
     {
         "BriefDescription": "ITLB miss page walks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -81,7 +71,6 @@
     },
     {
         "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC8",
         "EventName": "ITLB_MISS_RETIRED",
         "PEBS": "1",
@@ -90,7 +79,6 @@
     },
     {
         "BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
         "PEBS": "1",
@@ -99,7 +87,6 @@
     },
     {
         "BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC",
         "EventName": "MEM_STORE_RETIRED.DTLB_MISS",
         "PEBS": "1",
-- 
GitLab


From 28641ef5f387f2c8f57a7273d1ce35d168f14f86 Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:55:01 -0800
Subject: [PATCH 585/875] perf vendor events intel: Refresh sandybridge metrics
 and events

Update the sandybridge metrics and events using the new tooling from:

  https://github.com/intel/perfmon

The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1".  The
events are unchanged but unused json values are removed. The
formatting changes increase consistency across the json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-15-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../arch/x86/sandybridge/cache.json           | 441 ------------------
 .../arch/x86/sandybridge/floating-point.json  |  30 --
 .../arch/x86/sandybridge/frontend.json        |  64 ---
 .../arch/x86/sandybridge/memory.json          | 108 -----
 .../arch/x86/sandybridge/other.json           |  12 -
 .../arch/x86/sandybridge/pipeline.json        | 257 ----------
 .../arch/x86/sandybridge/snb-metrics.json     |  83 ++--
 .../arch/x86/sandybridge/uncore-cache.json    |  50 --
 .../arch/x86/sandybridge/uncore-other.json    |  28 +-
 .../arch/x86/sandybridge/virtual-memory.json  |  32 --
 10 files changed, 57 insertions(+), 1048 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/cache.json b/tools/perf/pmu-events/arch/x86/sandybridge/cache.json
index a1d6223521311..65696ea2a5811 100644
--- a/tools/perf/pmu-events/arch/x86/sandybridge/cache.json
+++ b/tools/perf/pmu-events/arch/x86/sandybridge/cache.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Allocated L1D data cache lines in M state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x51",
         "EventName": "L1D.ALLOCATED_IN_M",
         "SampleAfterValue": "2000003",
@@ -10,8 +8,6 @@
     },
     {
         "BriefDescription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x51",
         "EventName": "L1D.ALL_M_REPLACEMENT",
         "SampleAfterValue": "2000003",
@@ -19,8 +15,6 @@
     },
     {
         "BriefDescription": "L1D data cache lines in M state evicted due to replacement.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x51",
         "EventName": "L1D.EVICTION",
         "SampleAfterValue": "2000003",
@@ -28,8 +22,6 @@
     },
     {
         "BriefDescription": "L1D data line replacements.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x51",
         "EventName": "L1D.REPLACEMENT",
         "PublicDescription": "This event counts L1D data line replacements.  Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier.",
@@ -38,8 +30,6 @@
     },
     {
         "BriefDescription": "Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xBF",
         "EventName": "L1D_BLOCKS.BANK_CONFLICT_CYCLES",
@@ -48,8 +38,6 @@
     },
     {
         "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.FB_FULL",
@@ -58,8 +46,6 @@
     },
     {
         "BriefDescription": "L1D miss oustandings duration in cycles.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING",
         "SampleAfterValue": "2000003",
@@ -67,8 +53,6 @@
     },
     {
         "BriefDescription": "Cycles with L1D load Misses outstanding.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -78,8 +62,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -88,8 +70,6 @@
     },
     {
         "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "L2_L1D_WB_RQSTS.ALL",
         "SampleAfterValue": "200003",
@@ -97,8 +77,6 @@
     },
     {
         "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "L2_L1D_WB_RQSTS.HIT_E",
         "SampleAfterValue": "200003",
@@ -106,8 +84,6 @@
     },
     {
         "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "L2_L1D_WB_RQSTS.HIT_M",
         "SampleAfterValue": "200003",
@@ -115,8 +91,6 @@
     },
     {
         "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in S state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "L2_L1D_WB_RQSTS.HIT_S",
         "SampleAfterValue": "200003",
@@ -124,8 +98,6 @@
     },
     {
         "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "L2_L1D_WB_RQSTS.MISS",
         "SampleAfterValue": "200003",
@@ -133,8 +105,6 @@
     },
     {
         "BriefDescription": "L2 cache lines filling L2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.ALL",
         "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache.  Lines are filled into the L2 cache when there was an L2 miss.",
@@ -143,8 +113,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in E state filling L2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.E",
         "SampleAfterValue": "100003",
@@ -152,8 +120,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in I state filling L2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.I",
         "SampleAfterValue": "100003",
@@ -161,8 +127,6 @@
     },
     {
         "BriefDescription": "L2 cache lines in S state filling L2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.S",
         "SampleAfterValue": "100003",
@@ -170,8 +134,6 @@
     },
     {
         "BriefDescription": "Clean L2 cache lines evicted by demand.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
         "SampleAfterValue": "100003",
@@ -179,8 +141,6 @@
     },
     {
         "BriefDescription": "Dirty L2 cache lines evicted by demand.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
         "SampleAfterValue": "100003",
@@ -188,8 +148,6 @@
     },
     {
         "BriefDescription": "Dirty L2 cache lines filling the L2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DIRTY_ALL",
         "SampleAfterValue": "100003",
@@ -197,8 +155,6 @@
     },
     {
         "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.PF_CLEAN",
         "SampleAfterValue": "100003",
@@ -206,8 +162,6 @@
     },
     {
         "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.PF_DIRTY",
         "SampleAfterValue": "100003",
@@ -215,8 +169,6 @@
     },
     {
         "BriefDescription": "L2 code requests.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_CODE_RD",
         "SampleAfterValue": "200003",
@@ -224,8 +176,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
         "SampleAfterValue": "200003",
@@ -233,8 +183,6 @@
     },
     {
         "BriefDescription": "Requests from L2 hardware prefetchers.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_PF",
         "SampleAfterValue": "200003",
@@ -242,8 +190,6 @@
     },
     {
         "BriefDescription": "RFO requests to L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_RFO",
         "SampleAfterValue": "200003",
@@ -251,8 +197,6 @@
     },
     {
         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_HIT",
         "SampleAfterValue": "200003",
@@ -260,8 +204,6 @@
     },
     {
         "BriefDescription": "L2 cache misses when fetching instructions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_MISS",
         "SampleAfterValue": "200003",
@@ -269,8 +211,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests that hit L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
         "SampleAfterValue": "200003",
@@ -278,8 +218,6 @@
     },
     {
         "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PF_HIT",
         "SampleAfterValue": "200003",
@@ -287,8 +225,6 @@
     },
     {
         "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PF_MISS",
         "SampleAfterValue": "200003",
@@ -296,8 +232,6 @@
     },
     {
         "BriefDescription": "RFO requests that hit L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_HIT",
         "SampleAfterValue": "200003",
@@ -305,8 +239,6 @@
     },
     {
         "BriefDescription": "RFO requests that miss L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_MISS",
         "SampleAfterValue": "200003",
@@ -314,8 +246,6 @@
     },
     {
         "BriefDescription": "RFOs that access cache lines in any state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x27",
         "EventName": "L2_STORE_LOCK_RQSTS.ALL",
         "SampleAfterValue": "200003",
@@ -323,8 +253,6 @@
     },
     {
         "BriefDescription": "RFOs that hit cache lines in E state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x27",
         "EventName": "L2_STORE_LOCK_RQSTS.HIT_E",
         "SampleAfterValue": "200003",
@@ -332,8 +260,6 @@
     },
     {
         "BriefDescription": "RFOs that hit cache lines in M state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x27",
         "EventName": "L2_STORE_LOCK_RQSTS.HIT_M",
         "SampleAfterValue": "200003",
@@ -341,8 +267,6 @@
     },
     {
         "BriefDescription": "RFOs that miss cache lines.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x27",
         "EventName": "L2_STORE_LOCK_RQSTS.MISS",
         "SampleAfterValue": "200003",
@@ -350,8 +274,6 @@
     },
     {
         "BriefDescription": "L2 or LLC HW prefetches that access L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.ALL_PF",
         "SampleAfterValue": "200003",
@@ -359,8 +281,6 @@
     },
     {
         "BriefDescription": "Transactions accessing L2 pipe.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.ALL_REQUESTS",
         "SampleAfterValue": "200003",
@@ -368,8 +288,6 @@
     },
     {
         "BriefDescription": "L2 cache accesses when fetching instructions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.CODE_RD",
         "SampleAfterValue": "200003",
@@ -377,8 +295,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests that access L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.DEMAND_DATA_RD",
         "SampleAfterValue": "200003",
@@ -386,8 +302,6 @@
     },
     {
         "BriefDescription": "L1D writebacks that access L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L1D_WB",
         "SampleAfterValue": "200003",
@@ -395,8 +309,6 @@
     },
     {
         "BriefDescription": "L2 fill requests that access L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L2_FILL",
         "SampleAfterValue": "200003",
@@ -404,8 +316,6 @@
     },
     {
         "BriefDescription": "L2 writebacks that access L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L2_WB",
         "SampleAfterValue": "200003",
@@ -413,8 +323,6 @@
     },
     {
         "BriefDescription": "RFO requests that access L2 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.RFO",
         "SampleAfterValue": "200003",
@@ -422,8 +330,6 @@
     },
     {
         "BriefDescription": "Cycles when L1D is locked.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x63",
         "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
         "SampleAfterValue": "2000003",
@@ -431,8 +337,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests missed LLC.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.MISS",
         "SampleAfterValue": "100003",
@@ -440,8 +344,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests that refer to LLC.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
         "SampleAfterValue": "100003",
@@ -449,8 +351,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",
         "PEBS": "1",
@@ -460,8 +360,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",
         "PEBS": "1",
@@ -471,8 +369,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",
         "PEBS": "1",
@@ -481,8 +377,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",
         "PEBS": "1",
@@ -491,8 +385,6 @@
     },
     {
         "BriefDescription": "Retired load uops with unknown information as data source in cache serviced the load. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD4",
         "EventName": "MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS",
         "PEBS": "1",
@@ -502,8 +394,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
         "PEBS": "1",
@@ -512,8 +402,6 @@
     },
     {
         "BriefDescription": "Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
         "PEBS": "1",
@@ -522,8 +410,6 @@
     },
     {
         "BriefDescription": "Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
         "PEBS": "1",
@@ -532,8 +418,6 @@
     },
     {
         "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",
         "PEBS": "1",
@@ -543,8 +427,6 @@
     },
     {
         "BriefDescription": "All retired load uops. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
         "PEBS": "1",
@@ -554,8 +436,6 @@
     },
     {
         "BriefDescription": "All retired store uops. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
         "PEBS": "1",
@@ -565,8 +445,6 @@
     },
     {
         "BriefDescription": "Retired load uops with locked access. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
         "PEBS": "1",
@@ -575,8 +453,6 @@
     },
     {
         "BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
         "PEBS": "1",
@@ -586,8 +462,6 @@
     },
     {
         "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
         "PEBS": "1",
@@ -597,8 +471,6 @@
     },
     {
         "BriefDescription": "Retired load uops that miss the STLB. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
         "PEBS": "1",
@@ -607,8 +479,6 @@
     },
     {
         "BriefDescription": "Retired store uops that miss the STLB. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
         "PEBS": "1",
@@ -617,8 +487,6 @@
     },
     {
         "BriefDescription": "Demand and prefetch data reads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
         "SampleAfterValue": "100003",
@@ -626,8 +494,6 @@
     },
     {
         "BriefDescription": "Cacheable and noncachaeble code read requests.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
         "SampleAfterValue": "100003",
@@ -635,8 +501,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests sent to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
         "SampleAfterValue": "100003",
@@ -644,8 +508,6 @@
     },
     {
         "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
         "SampleAfterValue": "100003",
@@ -653,8 +515,6 @@
     },
     {
         "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB2",
         "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
         "SampleAfterValue": "2000003",
@@ -662,8 +522,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
         "SampleAfterValue": "2000003",
@@ -671,8 +529,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
@@ -681,8 +537,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
@@ -691,8 +545,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
@@ -701,8 +553,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
         "SampleAfterValue": "2000003",
@@ -710,8 +560,6 @@
     },
     {
         "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "6",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6",
@@ -720,8 +568,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
         "SampleAfterValue": "2000003",
@@ -729,1148 +575,861 @@
     },
     {
         "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0244",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0244",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0244",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x000105B3",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads that hit in the LLC.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0240",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0240",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0240",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0240",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0240",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads that hit in the LLC.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0090",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0090",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0090",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0090",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0090",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch RFOs that hit in the LLC.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo references (demand & prefetch) .",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x000107F7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c03f7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c03f7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c03f7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c03f7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean response.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c03f7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch prefetch RFOs .",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00010122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "COREWB & ANY_RESPONSE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10008",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_INTO_CORE and RESPONSE = ANY_RESPONSE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10433",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00010004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that hit in the LLC.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data reads .",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00010001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data reads that hit in the LLC.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand rfo's .",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x00010002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoops sent to sibling cores return clean response.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_M and SNOOP = HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_M.HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x18000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803c8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2380408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_RESPONSE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) data reads that hit in the LLC.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the LLC.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0200",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0200",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0200",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0200",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0200",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3f803c0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003c0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003c0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003c0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003c0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_LLC_DATA_RD and RESPONSE = ANY_RESPONSE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_LLC_IFETCH and RESPONSE = ANY_RESPONSE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10200",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts non-temporal stores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10800",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Split locks in SQ.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF4",
         "EventName": "SQ_MISC.SPLIT_LOCK",
         "SampleAfterValue": "100003",
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json b/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json
index eb2ff2cfdf6b0..8c2a246adef97 100644
--- a/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Cycles with any input/output SSE or FP assist.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.ANY",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Number of SIMD FP assists due to input values.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.SIMD_INPUT",
         "SampleAfterValue": "100003",
@@ -20,8 +16,6 @@
     },
     {
         "BriefDescription": "Number of SIMD FP assists due to Output values.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.SIMD_OUTPUT",
         "SampleAfterValue": "100003",
@@ -29,8 +23,6 @@
     },
     {
         "BriefDescription": "Number of X87 assists due to input value.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.X87_INPUT",
         "SampleAfterValue": "100003",
@@ -38,8 +30,6 @@
     },
     {
         "BriefDescription": "Number of X87 assists due to output value.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.X87_OUTPUT",
         "SampleAfterValue": "100003",
@@ -47,8 +37,6 @@
     },
     {
         "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",
         "SampleAfterValue": "2000003",
@@ -56,8 +44,6 @@
     },
     {
         "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",
         "SampleAfterValue": "2000003",
@@ -65,8 +51,6 @@
     },
     {
         "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",
         "SampleAfterValue": "2000003",
@@ -74,8 +58,6 @@
     },
     {
         "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",
         "SampleAfterValue": "2000003",
@@ -83,8 +65,6 @@
     },
     {
         "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.X87",
         "SampleAfterValue": "2000003",
@@ -92,8 +72,6 @@
     },
     {
         "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.AVX_STORE",
         "SampleAfterValue": "100003",
@@ -101,8 +79,6 @@
     },
     {
         "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.AVX_TO_SSE",
         "SampleAfterValue": "100003",
@@ -110,8 +86,6 @@
     },
     {
         "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.SSE_TO_AVX",
         "SampleAfterValue": "100003",
@@ -119,8 +93,6 @@
     },
     {
         "BriefDescription": "Number of AVX-256 Computational FP double precision uops issued this cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x11",
         "EventName": "SIMD_FP_256.PACKED_DOUBLE",
         "SampleAfterValue": "2000003",
@@ -128,8 +100,6 @@
     },
     {
         "BriefDescription": "Number of GSSE-256 Computational FP single precision uops issued this cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x11",
         "EventName": "SIMD_FP_256.PACKED_SINGLE",
         "SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json b/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json
index e2c82e43a2deb..69ab8d215f843 100644
--- a/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xE6",
         "EventName": "BACLEARS.ANY",
         "SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
     },
     {
         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAB",
         "EventName": "DSB2MITE_SWITCHES.COUNT",
         "SampleAfterValue": "2000003",
@@ -19,8 +15,6 @@
     },
     {
         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAB",
         "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
         "PublicDescription": "This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline.  It excludes cycles when the back-end cannot  accept new micro-ops.  The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.",
@@ -29,8 +23,6 @@
     },
     {
         "BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAC",
         "EventName": "DSB_FILL.ALL_CANCEL",
         "SampleAfterValue": "2000003",
@@ -38,8 +30,6 @@
     },
     {
         "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAC",
         "EventName": "DSB_FILL.EXCEED_DSB_LINES",
         "SampleAfterValue": "2000003",
@@ -47,8 +37,6 @@
     },
     {
         "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAC",
         "EventName": "DSB_FILL.OTHER_CANCEL",
         "SampleAfterValue": "2000003",
@@ -56,8 +44,6 @@
     },
     {
         "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.HIT",
         "SampleAfterValue": "2000003",
@@ -65,8 +51,6 @@
     },
     {
         "BriefDescription": "Instruction cache, streaming buffer and victim cache misses.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE.MISSES",
         "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.",
@@ -75,8 +59,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -85,8 +67,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -95,8 +75,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering 4 Uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -105,8 +83,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering any Uop.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -115,8 +91,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_CYCLES",
@@ -125,8 +99,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_UOPS",
         "SampleAfterValue": "2000003",
@@ -134,8 +106,6 @@
     },
     {
         "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0x79",
         "EventName": "IDQ.EMPTY",
         "SampleAfterValue": "2000003",
@@ -143,8 +113,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_ALL_UOPS",
         "SampleAfterValue": "2000003",
@@ -152,8 +120,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_CYCLES",
@@ -162,8 +128,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_UOPS",
         "SampleAfterValue": "2000003",
@@ -171,8 +135,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_CYCLES",
@@ -182,8 +144,6 @@
     },
     {
         "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_DSB_CYCLES",
@@ -192,8 +152,6 @@
     },
     {
         "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
@@ -203,8 +161,6 @@
     },
     {
         "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_DSB_UOPS",
         "SampleAfterValue": "2000003",
@@ -212,8 +168,6 @@
     },
     {
         "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_MITE_UOPS",
         "SampleAfterValue": "2000003",
@@ -221,8 +175,6 @@
     },
     {
         "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
@@ -232,8 +184,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_UOPS",
         "SampleAfterValue": "2000003",
@@ -241,8 +191,6 @@
     },
     {
         "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled .",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
         "PublicDescription": "This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled.  In the ideal case 4 uops can be delivered each cycle.  The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them.  This event is used in determining the front-end bound category of the top-down pipeline slots characterization.",
@@ -251,8 +199,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -261,8 +207,6 @@
     },
     {
         "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@@ -272,8 +216,6 @@
     },
     {
         "BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE",
@@ -283,8 +225,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "3",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@@ -293,8 +233,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@@ -303,8 +241,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/memory.json b/tools/perf/pmu-events/arch/x86/sandybridge/memory.json
index 3c283ca309f35..0a6fc0136f4a9 100644
--- a/tools/perf/pmu-events/arch/x86/sandybridge/memory.json
+++ b/tools/perf/pmu-events/arch/x86/sandybridge/memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
         "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers.  Machine clears can have a significant performance impact if they are happening frequently.",
@@ -11,124 +9,94 @@
     },
     {
         "BriefDescription": "Loads with latency value being above 128.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x80",
         "PEBS": "2",
         "SampleAfterValue": "1009",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 16.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x10",
         "PEBS": "2",
         "SampleAfterValue": "20011",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 256.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x100",
         "PEBS": "2",
         "SampleAfterValue": "503",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 32.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x20",
         "PEBS": "2",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 4 .",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x4",
         "PEBS": "2",
         "SampleAfterValue": "100003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 512.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x200",
         "PEBS": "2",
         "SampleAfterValue": "101",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 64.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x40",
         "PEBS": "2",
         "SampleAfterValue": "2003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Loads with latency value being above 8.",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x8",
         "PEBS": "2",
         "SampleAfterValue": "50021",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).",
-        "Counter": "3",
-        "CounterHTOff": "3",
         "EventCode": "0xCD",
         "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
         "PEBS": "2",
-        "PRECISE_STORE": "1",
         "SampleAfterValue": "2000003",
-        "TakenAlone": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x05",
         "EventName": "MISALIGN_MEM_REF.LOADS",
         "SampleAfterValue": "2000003",
@@ -136,8 +104,6 @@
     },
     {
         "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x05",
         "EventName": "MISALIGN_MEM_REF.STORES",
         "SampleAfterValue": "2000003",
@@ -145,298 +111,224 @@
     },
     {
         "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC  and the data returned from dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x300400244",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC  and the data returned from dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x300400091",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch code reads that miss the LLC  and the data returned from dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_MISS.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x300400240",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads that miss the LLC  and the data returned from dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_MISS.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x300400090",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch RFOs that miss the LLC  and the data returned from dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_MISS.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x300400120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3004003f7",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs that miss the LLC  and the data returned from dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x300400122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_MISS_LOCAL.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1f80408fff",
-        "Offcore": "1",
         "PublicDescription": "This event counts any requests that miss the LLC where the data was returned from local DRAM",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts LLC replacements.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x6004001b3",
-        "Offcore": "1",
         "PublicDescription": "This event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC  where the data is returned from local DRAM",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS_LOCAL.ANY_LLC_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x17004001b3",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x300400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x300400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_MISS_LOCAL.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1f80400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data writes (RFOs) that miss the LLC and the data returned from dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x300400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_MISS_LOCAL.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1f80400010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_MISS_LOCAL.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1f80400040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x300400040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x300400010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the LLC  and the data returned from dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x300400020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the LLC  and the data returned from dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x300400200",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the LLC  and the data returned from dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x300400080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC  and the data returned from dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x300400100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.LLC_MISS_LOCAL.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1f80400080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.LLC_MISS_LOCAL.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1f80400200",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBE",
         "EventName": "PAGE_WALKS.LLC_MISS",
         "SampleAfterValue": "100003",
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/other.json b/tools/perf/pmu-events/arch/x86/sandybridge/other.json
index 2f873ab14156b..9f96121baef8e 100644
--- a/tools/perf/pmu-events/arch/x86/sandybridge/other.json
+++ b/tools/perf/pmu-events/arch/x86/sandybridge/other.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Unhalted core cycles when the thread is in ring 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5C",
         "EventName": "CPL_CYCLES.RING0",
         "SampleAfterValue": "2000003",
@@ -10,8 +8,6 @@
     },
     {
         "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5C",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5C",
         "EventName": "CPL_CYCLES.RING123",
         "SampleAfterValue": "2000003",
@@ -30,8 +24,6 @@
     },
     {
         "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4E",
         "EventName": "HW_PRE_REQ.DL1_MISS",
         "SampleAfterValue": "2000003",
@@ -39,8 +31,6 @@
     },
     {
         "BriefDescription": "Valid instructions written to IQ per cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x17",
         "EventName": "INSTS_WRITTEN_TO_IQ.INSTS",
         "SampleAfterValue": "2000003",
@@ -48,8 +38,6 @@
     },
     {
         "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x63",
         "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
         "SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json b/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json
index 2c3b6c92aa6b7..53ab5993e8b04 100644
--- a/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB6",
         "EventName": "AGU_BYPASS_CANCEL.COUNT",
         "SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
     },
     {
         "BriefDescription": "Divide operations executed.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x14",
@@ -22,8 +18,6 @@
     },
     {
         "BriefDescription": "Cycles when divider is busy executing divide operations.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x14",
         "EventName": "ARITH.FPU_DIV_ACTIVE",
         "SampleAfterValue": "2000003",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Speculative and retired  branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_BRANCHES",
         "SampleAfterValue": "200003",
@@ -40,8 +32,6 @@
     },
     {
         "BriefDescription": "Speculative and retired macro-conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -49,8 +39,6 @@
     },
     {
         "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
         "SampleAfterValue": "200003",
@@ -58,8 +46,6 @@
     },
     {
         "BriefDescription": "Speculative and retired direct near calls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
         "SampleAfterValue": "200003",
@@ -67,8 +53,6 @@
     },
     {
         "BriefDescription": "Speculative and retired indirect branches excluding calls and returns.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
         "SampleAfterValue": "200003",
@@ -76,8 +60,6 @@
     },
     {
         "BriefDescription": "Speculative and retired indirect return branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
         "SampleAfterValue": "200003",
@@ -85,8 +67,6 @@
     },
     {
         "BriefDescription": "Not taken macro-conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -94,8 +74,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired macro-conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -103,8 +81,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
         "SampleAfterValue": "200003",
@@ -112,8 +88,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired direct near calls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
         "SampleAfterValue": "200003",
@@ -121,8 +95,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
         "SampleAfterValue": "200003",
@@ -130,8 +102,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect calls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
         "SampleAfterValue": "200003",
@@ -139,8 +109,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
         "SampleAfterValue": "200003",
@@ -148,16 +116,12 @@
     },
     {
         "BriefDescription": "All (macro) branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "SampleAfterValue": "400009"
     },
     {
         "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
         "PEBS": "2",
@@ -166,8 +130,6 @@
     },
     {
         "BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -176,8 +138,6 @@
     },
     {
         "BriefDescription": "Far branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.FAR_BRANCH",
         "SampleAfterValue": "100007",
@@ -185,8 +145,6 @@
     },
     {
         "BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -195,8 +153,6 @@
     },
     {
         "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
         "PEBS": "1",
@@ -205,8 +161,6 @@
     },
     {
         "BriefDescription": "Return instructions retired. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_RETURN",
         "PEBS": "1",
@@ -215,8 +169,6 @@
     },
     {
         "BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
@@ -225,8 +177,6 @@
     },
     {
         "BriefDescription": "Not taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NOT_TAKEN",
         "SampleAfterValue": "400009",
@@ -234,8 +184,6 @@
     },
     {
         "BriefDescription": "Speculative and retired mispredicted macro conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_BRANCHES",
         "SampleAfterValue": "200003",
@@ -243,8 +191,6 @@
     },
     {
         "BriefDescription": "Speculative and retired mispredicted macro conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -252,8 +198,6 @@
     },
     {
         "BriefDescription": "Speculative and retired mispredicted direct near calls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL",
         "SampleAfterValue": "200003",
@@ -261,8 +205,6 @@
     },
     {
         "BriefDescription": "Mispredicted indirect branches excluding calls and returns.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
         "SampleAfterValue": "200003",
@@ -270,8 +212,6 @@
     },
     {
         "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -279,8 +219,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
         "SampleAfterValue": "200003",
@@ -288,8 +226,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted direct near calls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL",
         "SampleAfterValue": "200003",
@@ -297,8 +233,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
         "SampleAfterValue": "200003",
@@ -306,8 +240,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect calls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
         "SampleAfterValue": "200003",
@@ -315,8 +247,6 @@
     },
     {
         "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
         "SampleAfterValue": "200003",
@@ -324,27 +254,20 @@
     },
     {
         "BriefDescription": "All mispredicted macro branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "SampleAfterValue": "400009"
     },
     {
         "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
         "PEBS": "2",
-        "PublicDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
         "SampleAfterValue": "400009",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -353,8 +276,6 @@
     },
     {
         "BriefDescription": "Direct and indirect mispredicted near call instructions retired. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -363,8 +284,6 @@
     },
     {
         "BriefDescription": "Mispredicted not taken branch instructions retired.(Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NOT_TAKEN",
         "PEBS": "1",
@@ -373,8 +292,6 @@
     },
     {
         "BriefDescription": "Mispredicted taken branch instructions retired. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.TAKEN",
         "PEBS": "1",
@@ -383,8 +300,6 @@
     },
     {
         "BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "2000003",
@@ -392,8 +307,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
         "SampleAfterValue": "2000003",
@@ -402,8 +315,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
         "SampleAfterValue": "2000003",
@@ -411,8 +322,6 @@
     },
     {
         "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "2000003",
@@ -420,8 +329,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the core is not in halt state.",
-        "Counter": "Fixed counter 2",
-        "CounterHTOff": "Fixed counter 2",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
         "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
         "SampleAfterValue": "2000003",
@@ -429,19 +336,14 @@
     },
     {
         "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
-        "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "AnyThread": "1",
         "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
         "SampleAfterValue": "2000003",
@@ -449,8 +351,6 @@
     },
     {
         "BriefDescription": "Core cycles when the thread is not in halt state.",
-        "Counter": "Fixed counter 1",
-        "CounterHTOff": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD",
         "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
         "SampleAfterValue": "2000003",
@@ -459,16 +359,12 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
-        "Counter": "Fixed counter 1",
-        "CounterHTOff": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Thread cycles when thread is not in halt state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
         "SampleAfterValue": "2000003"
@@ -476,16 +372,12 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "2",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
@@ -494,8 +386,6 @@
     },
     {
         "BriefDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
@@ -504,8 +394,6 @@
     },
     {
         "BriefDescription": "Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "4",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_NO_DISPATCH",
@@ -514,8 +402,6 @@
     },
     {
         "BriefDescription": "Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",
-        "Counter": "2",
-        "CounterHTOff": "2",
         "CounterMask": "6",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
@@ -524,8 +410,6 @@
     },
     {
         "BriefDescription": "Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "5",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
@@ -534,8 +418,6 @@
     },
     {
         "BriefDescription": "Stall cycles because IQ is full.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.IQ_FULL",
         "SampleAfterValue": "2000003",
@@ -543,8 +425,6 @@
     },
     {
         "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.LCP",
         "SampleAfterValue": "2000003",
@@ -552,8 +432,6 @@
     },
     {
         "BriefDescription": "Instructions retired from execution.",
-        "Counter": "Fixed counter 0",
-        "CounterHTOff": "Fixed counter 0",
         "EventName": "INST_RETIRED.ANY",
         "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers.",
         "SampleAfterValue": "2000003",
@@ -561,27 +439,20 @@
     },
     {
         "BriefDescription": "Number of instructions retired. General Counter   - architectural event.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.ANY_P",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Instructions retired. (Precise Event - PEBS).",
-        "Counter": "1",
-        "CounterHTOff": "1",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.PREC_DIST",
         "PEBS": "2",
         "SampleAfterValue": "2000003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RAT_STALL_CYCLES",
         "SampleAfterValue": "2000003",
@@ -589,8 +460,6 @@
     },
     {
         "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES",
@@ -600,8 +469,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
@@ -610,8 +477,6 @@
     },
     {
         "BriefDescription": "Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x0D",
@@ -621,8 +486,6 @@
     },
     {
         "BriefDescription": "Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.ALL_BLOCK",
         "SampleAfterValue": "100003",
@@ -630,8 +493,6 @@
     },
     {
         "BriefDescription": "Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.DATA_UNKNOWN",
         "SampleAfterValue": "100003",
@@ -639,8 +500,6 @@
     },
     {
         "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.NO_SR",
         "SampleAfterValue": "100003",
@@ -648,8 +507,6 @@
     },
     {
         "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.STORE_FORWARD",
         "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load.  The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store.  See the table of not supported store forwards in the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual.  The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.",
@@ -658,8 +515,6 @@
     },
     {
         "BriefDescription": "False dependencies in MOB due to partial compare.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x07",
         "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
         "PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K.  This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline.  The enhanced address check typically has a performance penalty of 5 cycles.",
@@ -668,8 +523,6 @@
     },
     {
         "BriefDescription": "This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x07",
         "EventName": "LD_BLOCKS_PARTIAL.ALL_STA_BLOCK",
         "SampleAfterValue": "100003",
@@ -677,8 +530,6 @@
     },
     {
         "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4C",
         "EventName": "LOAD_HIT_PRE.HW_PF",
         "SampleAfterValue": "100003",
@@ -686,8 +537,6 @@
     },
     {
         "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4C",
         "EventName": "LOAD_HIT_PRE.SW_PF",
         "SampleAfterValue": "100003",
@@ -695,8 +544,6 @@
     },
     {
         "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_4_UOPS",
@@ -705,8 +552,6 @@
     },
     {
         "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_ACTIVE",
@@ -715,8 +560,6 @@
     },
     {
         "BriefDescription": "Number of Uops delivered by the LSD.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA8",
         "EventName": "LSD.UOPS",
         "SampleAfterValue": "2000003",
@@ -724,8 +567,6 @@
     },
     {
         "BriefDescription": "Number of machine clears (nukes) of any type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xc3",
@@ -735,8 +576,6 @@
     },
     {
         "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MASKMOV",
         "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",
@@ -745,8 +584,6 @@
     },
     {
         "BriefDescription": "Self-modifying code (SMC) detected.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.SMC",
         "PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear.  Machine clears can have a significant performance impact if they are happening frequently.",
@@ -755,8 +592,6 @@
     },
     {
         "BriefDescription": "Retired instructions experiencing ITLB misses.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.ITLB_MISS_RETIRED",
         "SampleAfterValue": "100003",
@@ -764,8 +599,6 @@
     },
     {
         "BriefDescription": "Increments the number of flags-merge uops in flight each cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x59",
         "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP",
         "SampleAfterValue": "2000003",
@@ -773,8 +606,6 @@
     },
     {
         "BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x59",
         "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES",
@@ -784,8 +615,6 @@
     },
     {
         "BriefDescription": "Multiply packed/scalar single precision uops allocated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x59",
         "EventName": "PARTIAL_RAT_STALLS.MUL_SINGLE_UOP",
         "SampleAfterValue": "2000003",
@@ -793,8 +622,6 @@
     },
     {
         "BriefDescription": "Cycles with at least one slow LEA uop being allocated.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x59",
         "EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW",
         "PublicDescription": "This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.",
@@ -803,8 +630,6 @@
     },
     {
         "BriefDescription": "Resource-related stall cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ANY",
         "SampleAfterValue": "2000003",
@@ -812,8 +637,6 @@
     },
     {
         "BriefDescription": "Counts the cycles of stall due to lack of load buffers.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.LB",
         "SampleAfterValue": "2000003",
@@ -821,8 +644,6 @@
     },
     {
         "BriefDescription": "Resource stalls due to load or store buffers all being in use.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.LB_SB",
         "SampleAfterValue": "2000003",
@@ -830,8 +651,6 @@
     },
     {
         "BriefDescription": "Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.MEM_RS",
         "SampleAfterValue": "2000003",
@@ -839,8 +658,6 @@
     },
     {
         "BriefDescription": "Resource stalls due to Rob being full, FCSW, MXCSR and OTHER.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.OOO_RSRC",
         "SampleAfterValue": "2000003",
@@ -848,8 +665,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to re-order buffer full.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ROB",
         "SampleAfterValue": "2000003",
@@ -857,8 +672,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no eligible RS entry available.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.RS",
         "SampleAfterValue": "2000003",
@@ -866,8 +679,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.SB",
         "SampleAfterValue": "2000003",
@@ -875,8 +686,6 @@
     },
     {
         "BriefDescription": "Cycles with either free list is empty.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5B",
         "EventName": "RESOURCE_STALLS2.ALL_FL_EMPTY",
         "SampleAfterValue": "2000003",
@@ -884,8 +693,6 @@
     },
     {
         "BriefDescription": "Resource stalls2 control structures full for physical registers.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5B",
         "EventName": "RESOURCE_STALLS2.ALL_PRF_CONTROL",
         "SampleAfterValue": "2000003",
@@ -893,8 +700,6 @@
     },
     {
         "BriefDescription": "Cycles when Allocator is stalled if BOB is full and new branch needs it.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5B",
         "EventName": "RESOURCE_STALLS2.BOB_FULL",
         "SampleAfterValue": "2000003",
@@ -902,8 +707,6 @@
     },
     {
         "BriefDescription": "Resource stalls out of order resources full.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5B",
         "EventName": "RESOURCE_STALLS2.OOO_RSRC",
         "SampleAfterValue": "2000003",
@@ -911,8 +714,6 @@
     },
     {
         "BriefDescription": "Count cases of saving new LBR.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCC",
         "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
         "SampleAfterValue": "2000003",
@@ -920,8 +721,6 @@
     },
     {
         "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5E",
         "EventName": "RS_EVENTS.EMPTY_CYCLES",
         "SampleAfterValue": "2000003",
@@ -929,8 +728,6 @@
     },
     {
         "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5E",
@@ -941,8 +738,6 @@
     },
     {
         "BriefDescription": "Uops dispatched from any thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_DISPATCHED.CORE",
         "SampleAfterValue": "2000003",
@@ -950,8 +745,6 @@
     },
     {
         "BriefDescription": "Uops dispatched per thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_DISPATCHED.THREAD",
         "SampleAfterValue": "2000003",
@@ -959,8 +752,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are dispatched to port 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_0",
         "SampleAfterValue": "2000003",
@@ -969,8 +760,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE",
         "SampleAfterValue": "2000003",
@@ -978,8 +767,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are dispatched to port 1.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_1",
         "SampleAfterValue": "2000003",
@@ -988,8 +775,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 1.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE",
         "SampleAfterValue": "2000003",
@@ -997,8 +782,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_2",
         "SampleAfterValue": "2000003",
@@ -1007,8 +790,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 2.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE",
         "SampleAfterValue": "2000003",
@@ -1016,8 +797,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_3",
         "SampleAfterValue": "2000003",
@@ -1026,8 +805,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE",
         "SampleAfterValue": "2000003",
@@ -1035,8 +812,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are dispatched to port 4.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_4",
         "SampleAfterValue": "2000003",
@@ -1045,8 +820,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 4.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE",
         "SampleAfterValue": "2000003",
@@ -1054,8 +827,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are dispatched to port 5.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_5",
         "SampleAfterValue": "2000003",
@@ -1064,8 +835,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles per core when uops are dispatched to port 5.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE",
         "SampleAfterValue": "2000003",
@@ -1073,8 +842,6 @@
     },
     {
         "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@@ -1083,8 +850,6 @@
     },
     {
         "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@@ -1093,8 +858,6 @@
     },
     {
         "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@@ -1103,8 +866,6 @@
     },
     {
         "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@@ -1113,8 +874,6 @@
     },
     {
         "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
         "Invert": "1",
@@ -1123,8 +882,6 @@
     },
     {
         "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.ANY",
         "PublicDescription": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.",
@@ -1134,8 +891,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -1145,8 +900,6 @@
     },
     {
         "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -1156,8 +909,6 @@
     },
     {
         "BriefDescription": "Actually retired uops. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ALL",
         "PEBS": "1",
@@ -1167,8 +918,6 @@
     },
     {
         "BriefDescription": "Cycles without actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",
@@ -1178,8 +927,6 @@
     },
     {
         "BriefDescription": "Retirement slots used. (Precise Event - PEBS).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
         "PEBS": "1",
@@ -1189,8 +936,6 @@
     },
     {
         "BriefDescription": "Cycles without actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -1200,8 +945,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 10 actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "10",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json b/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json
index 5d5a6d6f3bdab..a7b3c835b03d7 100644
--- a/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json
@@ -65,7 +65,7 @@
     },
     {
         "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
-        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
         "MetricGroup": "TopdownL1;tma_L1_group",
         "MetricName": "tma_bad_speculation",
         "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
@@ -73,7 +73,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
-        "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
+        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
         "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
         "MetricName": "tma_branch_mispredicts",
         "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
@@ -97,7 +97,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
-        "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB)) * tma_backend_bound",
+        "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if IPC > 1.8 else (cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) * tma_backend_bound",
         "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
         "MetricName": "tma_memory_bound",
         "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@@ -113,7 +113,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
-        "MetricExpr": "(MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
+        "MetricExpr": "MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
         "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_l3_bound",
         "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
@@ -121,7 +121,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
-        "MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS))) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
+        "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
         "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_dram_bound",
         "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS",
@@ -169,7 +169,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
-        "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING)) / CLKS",
+        "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if IPC > 1.8 else (cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING)) / CLKS",
         "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
         "MetricName": "tma_ports_utilization",
         "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@@ -233,7 +233,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
-        "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
         "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
         "MetricName": "tma_microcode_sequencer",
         "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
@@ -284,19 +284,19 @@
     },
     {
         "BriefDescription": "Floating Point Operations Per Cycle",
-        "MetricExpr": "(1 * (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / CORE_CLKS",
+        "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / CORE_CLKS",
         "MetricGroup": "Flops;Ret",
         "MetricName": "FLOPc"
     },
     {
         "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
-        "MetricExpr": "UOPS_DISPATCHED.THREAD / ((cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@ / 2) if #SMT_on else cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@)",
+        "MetricExpr": "UOPS_DISPATCHED.THREAD / (cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@)",
         "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
         "MetricName": "ILP"
     },
     {
         "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
-        "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
+        "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
         "MetricGroup": "SMT",
         "MetricName": "CORE_CLKS"
     },
@@ -314,25 +314,25 @@
     },
     {
         "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
-        "MetricExpr": "IDQ.DSB_UOPS / ((IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS))",
+        "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
         "MetricGroup": "DSB;Fed;FetchBW",
         "MetricName": "DSB_Coverage"
     },
     {
         "BriefDescription": "Average CPU Utilization",
-        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
+        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
         "MetricGroup": "HPC;Summary",
         "MetricName": "CPU_Utilization"
     },
     {
         "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
-        "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
+        "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
         "MetricGroup": "Power;Summary",
         "MetricName": "Average_Frequency"
     },
     {
         "BriefDescription": "Giga Floating Point Operations Per Second",
-        "MetricExpr": "((1 * (FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1000000000) / duration_time",
+        "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1e9 / duration_time",
         "MetricGroup": "Cor;Flops;HPC",
         "MetricName": "GFLOPs",
         "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
@@ -345,7 +345,7 @@
     },
     {
         "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
-        "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
+        "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
         "MetricGroup": "SMT",
         "MetricName": "SMT_2T_Utilization"
     },
@@ -363,68 +363,87 @@
     },
     {
         "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
-        "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1000000 / duration_time / 1000",
+        "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3",
         "MetricGroup": "HPC;Mem;MemoryBW;SoC",
         "MetricName": "DRAM_BW_Use"
     },
     {
         "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)",
-        "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
+        "MetricExpr": "MEM_Parallel_Requests",
         "MetricGroup": "Mem;SoC",
         "MetricName": "MEM_Request_Latency"
     },
     {
         "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests",
-        "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
+        "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL",
         "MetricGroup": "Mem;SoC",
         "MetricName": "MEM_Parallel_Requests"
     },
+    {
+        "BriefDescription": "Socket actual clocks when any core is active on that socket",
+        "MetricExpr": "UNC_CLOCK.SOCKET",
+        "MetricGroup": "SoC",
+        "MetricName": "Socket_CLKS"
+    },
     {
         "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
         "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
         "MetricGroup": "Branches;OS",
         "MetricName": "IpFarBranch"
     },
+    {
+        "BriefDescription": "Uncore frequency per die [GHZ]",
+        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+        "MetricGroup": "SoC",
+        "MetricName": "UNCORE_FREQ"
+    },
     {
         "BriefDescription": "C3 residency percent per core",
-        "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C3_Core_Residency"
+        "MetricName": "C3_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C6 residency percent per core",
-        "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C6_Core_Residency"
+        "MetricName": "C6_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C7 residency percent per core",
-        "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C7_Core_Residency"
+        "MetricName": "C7_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C2 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C2_Pkg_Residency"
+        "MetricName": "C2_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C3 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C3_Pkg_Residency"
+        "MetricName": "C3_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C6 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C6_Pkg_Residency"
+        "MetricName": "C6_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C7 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C7_Pkg_Residency"
+        "MetricName": "C7_Pkg_Residency",
+        "ScaleUnit": "100%"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json
index 6b0639944d78f..c538557ba4c09 100644
--- a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json
@@ -1,251 +1,201 @@
 [
     {
         "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
         "UMask": "0x86",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
         "UMask": "0x88",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
         "UMask": "0x81",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
         "UMask": "0x8f",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
         "UMask": "0x46",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
         "UMask": "0x48",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
         "UMask": "0x41",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
         "UMask": "0x4f",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
         "UMask": "0x16",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup read request that access cache and found line in I-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",
         "UMask": "0x18",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup read request that access cache and found line in M-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup read request that access cache and found line in M-state.",
         "UMask": "0x11",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
         "UMask": "0x1f",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
         "UMask": "0x26",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup write request that access cache and found line in I-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup write request that access cache and found line in I-state.",
         "UMask": "0x28",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup write request that access cache and found line in M-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",
         "UMask": "0x21",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
         "PerPkg": "1",
-        "PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
         "UMask": "0x2f",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
         "UMask": "0x88",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "An external snoop hits a modified line in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL",
         "PerPkg": "1",
-        "PublicDescription": "An external snoop hits a modified line in some processor core.",
         "UMask": "0x28",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
         "UMask": "0x48",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
         "UMask": "0x84",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "An external snoop hits a non-modified line in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL",
         "PerPkg": "1",
-        "PublicDescription": "An external snoop hits a non-modified line in some processor core.",
         "UMask": "0x24",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
         "UMask": "0x44",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
         "UMask": "0x81",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "An external snoop misses in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL",
         "PerPkg": "1",
-        "PublicDescription": "An external snoop misses in some processor core.",
         "UMask": "0x21",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
         "UMask": "0x41",
         "Unit": "CBO"
     }
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json
index 88f1e326205fa..c3252c094a9cc 100644
--- a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json
@@ -4,18 +4,15 @@
         "EventCode": "0x83",
         "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "PublicDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Number of requests allocated in Coherency Tracker.",
-        "Counter": "0,1",
         "EventCode": "0x84",
         "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
         "PerPkg": "1",
-        "PublicDescription": "Number of requests allocated in Coherency Tracker.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
@@ -23,69 +20,56 @@
         "EventCode": "0x80",
         "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "PublicDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
-        "Counter": "0,1",
         "CounterMask": "10",
         "EventCode": "0x80",
         "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL",
         "PerPkg": "1",
-        "PublicDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
-        "Counter": "0,1",
         "CounterMask": "1",
         "EventCode": "0x80",
         "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
         "PerPkg": "1",
-        "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
-        "Counter": "0,1",
         "EventCode": "0x81",
         "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
         "PerPkg": "1",
-        "PublicDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Counts the number of LLC evictions allocated.",
-        "Counter": "0,1",
         "EventCode": "0x81",
         "EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS",
         "PerPkg": "1",
-        "PublicDescription": "Counts the number of LLC evictions allocated.",
         "UMask": "0x80",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
-        "Counter": "0,1",
         "EventCode": "0x81",
         "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
         "PerPkg": "1",
-        "PublicDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.",
         "UMask": "0x20",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
-        "Counter": "Fixed",
         "EventCode": "0xff",
         "EventName": "UNC_CLOCK.SOCKET",
         "PerPkg": "1",
-        "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
         "Unit": "ARB"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json b/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json
index 98362abba1a7d..fa08d355b97e6 100644
--- a/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Load misses in all DTLB levels that cause page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
         "SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
     },
     {
         "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
         "PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.",
@@ -20,8 +16,6 @@
     },
     {
         "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "100003",
@@ -29,8 +23,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
         "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
@@ -39,8 +31,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
         "SampleAfterValue": "100003",
@@ -48,8 +38,6 @@
     },
     {
         "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT",
         "SampleAfterValue": "100003",
@@ -57,8 +45,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "100003",
@@ -66,8 +52,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_DURATION",
         "SampleAfterValue": "2000003",
@@ -75,8 +59,6 @@
     },
     {
         "BriefDescription": "Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4F",
         "EventName": "EPT.WALK_CYCLES",
         "SampleAfterValue": "2000003",
@@ -84,8 +66,6 @@
     },
     {
         "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAE",
         "EventName": "ITLB.ITLB_FLUSH",
         "SampleAfterValue": "100007",
@@ -93,8 +73,6 @@
     },
     {
         "BriefDescription": "Misses at all ITLB levels that cause page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
         "SampleAfterValue": "100003",
@@ -102,8 +80,6 @@
     },
     {
         "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT",
         "SampleAfterValue": "100003",
@@ -111,8 +87,6 @@
     },
     {
         "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "100003",
@@ -120,8 +94,6 @@
     },
     {
         "BriefDescription": "Cycles when PMH is busy with page walks.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_DURATION",
         "PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
@@ -130,8 +102,6 @@
     },
     {
         "BriefDescription": "DTLB flush attempts of the thread-specific entries.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.DTLB_THREAD",
         "SampleAfterValue": "100007",
@@ -139,8 +109,6 @@
     },
     {
         "BriefDescription": "STLB flush attempts.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.STLB_ANY",
         "SampleAfterValue": "100007",
-- 
GitLab


From 400dd489d42faef3647d990dd67f553371ec204b Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:55:02 -0800
Subject: [PATCH 586/875] perf vendor events intel: Refresh sapphirerapids
 metrics and events

Update the sapphirerapids metrics and events using the new tooling from:

  https://github.com/intel/perfmon

The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
order of metrics varies as TMA metrics are first converted and then
removed if perfmon versions are found. The events are updated to 1.09,
in particular uncore, with fixes to uncore events and improved
descriptions. The formatting changes increase consistency across the
json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-16-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/pmu-events/arch/x86/mapfile.csv    |    2 +-
 .../arch/x86/sapphirerapids/cache.json        |  350 +-
 .../x86/sapphirerapids/floating-point.json    |   63 -
 .../arch/x86/sapphirerapids/frontend.json     |  144 -
 .../arch/x86/sapphirerapids/memory.json       |  125 +-
 .../arch/x86/sapphirerapids/other.json        |   91 +-
 .../arch/x86/sapphirerapids/pipeline.json     |  424 +-
 .../arch/x86/sapphirerapids/spr-metrics.json  | 2309 +++---
 .../x86/sapphirerapids/uncore-memory.json     |  526 +-
 .../arch/x86/sapphirerapids/uncore-other.json | 6606 ++++++++---------
 .../arch/x86/sapphirerapids/uncore-power.json |   84 +-
 .../x86/sapphirerapids/virtual-memory.json    |   80 -
 12 files changed, 4483 insertions(+), 6321 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 84f74acf91d9f..a5de68bcebcd0 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -21,7 +21,7 @@ GenuineIntel-6-A[AC],v1.00,meteorlake,core
 GenuineIntel-6-1[AEF],v3,nehalemep,core
 GenuineIntel-6-2E,v3,nehalemex,core
 GenuineIntel-6-2A,v17,sandybridge,core
-GenuineIntel-6-8F,v1.06,sapphirerapids,core
+GenuineIntel-6-8F,v1.09,sapphirerapids,core
 GenuineIntel-6-(37|4A|4C|4D|5A),v14,silvermont,core
 GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v53,skylake,core
 GenuineIntel-6-55-[01234],v1.28,skylakex,core
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json
index c05c741e22db1..92a605ecac6e9 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json
@@ -1,1192 +1,898 @@
 [
     {
         "BriefDescription": "L1D.HWPF_MISS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x51",
         "EventName": "L1D.HWPF_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x51",
         "EventName": "L1D.REPLACEMENT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.FB_FULL",
-        "PEBScounters": "0,1,2,3",
-        "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
+        "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
+        "Deprecated": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.L2_STALL",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.L2_STALLS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of L1D misses that are outstanding",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles with L1D load Misses outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "L2 cache lines filling L2",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x25",
         "EventName": "L2_LINES_IN.ALL",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1f"
     },
     {
         "BriefDescription": "L2_LINES_OUT.NON_SILENT",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_LINES_OUT.NON_SILENT",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_LINES_OUT.SILENT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_LINES_OUT.USELESS_HWPF",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "All accesses to L2 cache[This event is alias to L2_RQSTS.REFERENCES]",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_REQUEST.ALL",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses.[This event is alias to L2_RQSTS.REFERENCES]",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xff"
     },
     {
         "BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_RQSTS.MISS]",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_REQUEST.MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses.[This event is alias to L2_RQSTS.MISS]",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x3f"
     },
     {
         "BriefDescription": "L2 code requests",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_CODE_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of L2 code requests.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xe4"
     },
     {
         "BriefDescription": "Demand Data Read access L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xe1"
     },
     {
         "BriefDescription": "Demand requests that miss L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts demand requests that miss L2 cache.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x27"
     },
     {
         "BriefDescription": "Demand requests to L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts demand requests to L2 cache.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xe7"
     },
     {
         "BriefDescription": "L2_RQSTS.ALL_HWPF",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_HWPF",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xf0"
     },
     {
         "BriefDescription": "RFO requests to L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_RFO",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xe2"
     },
     {
         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xc4"
     },
     {
         "BriefDescription": "L2 cache misses when fetching instructions",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts L2 cache misses when fetching instructions.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x24"
     },
     {
         "BriefDescription": "Demand Data Read requests that hit L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xc1"
     },
     {
         "BriefDescription": "Demand Data Read miss L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x21"
     },
     {
         "BriefDescription": "L2_RQSTS.HWPF_MISS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.HWPF_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x30"
     },
     {
         "BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_REQUEST.MISS]",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses.[This event is alias to L2_REQUEST.MISS]",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x3f"
     },
     {
         "BriefDescription": "All accesses to L2 cache[This event is alias to L2_REQUEST.ALL]",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.REFERENCES",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses.[This event is alias to L2_REQUEST.ALL]",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xff"
     },
     {
         "BriefDescription": "RFO requests that hit L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xc2"
     },
     {
         "BriefDescription": "RFO requests that miss L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x22"
     },
     {
         "BriefDescription": "SW prefetch requests that hit L2 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.SWPF_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0xc8"
     },
     {
         "BriefDescription": "SW prefetch requests that miss L2 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.SWPF_MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x28"
     },
     {
         "BriefDescription": "Core-originated cacheable requests that missed L3  (Except hardware prefetches to the L3)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2e",
         "EventName": "LONGEST_LAT_CACHE.MISS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2.  It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x41"
     },
     {
         "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2e",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2.  It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4f"
     },
     {
         "BriefDescription": "Retired load instructions.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.ALL_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",
         "SampleAfterValue": "1000003",
         "UMask": "0x81"
     },
     {
         "BriefDescription": "Retired store instructions.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.ALL_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts all retired store instructions.",
         "SampleAfterValue": "1000003",
         "UMask": "0x82"
     },
     {
         "BriefDescription": "All retired memory instructions.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.ANY",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts all retired memory instructions - loads and stores.",
         "SampleAfterValue": "1000003",
         "UMask": "0x83"
     },
     {
         "BriefDescription": "Retired load instructions with locked access.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.LOCK_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with locked access.",
         "SampleAfterValue": "100007",
         "UMask": "0x21"
     },
     {
         "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",
         "SampleAfterValue": "100003",
         "UMask": "0x41"
     },
     {
         "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.SPLIT_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
         "SampleAfterValue": "100003",
         "UMask": "0x42"
     },
     {
         "BriefDescription": "Retired load instructions that miss the STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).",
         "SampleAfterValue": "100003",
         "UMask": "0x11"
     },
     {
         "BriefDescription": "Retired store instructions that miss the STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).",
         "SampleAfterValue": "100003",
         "UMask": "0x12"
     },
     {
         "BriefDescription": "Completed demand load uops that miss the L1 d-cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x43",
         "EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Number of completed demand load requests that missed the L1 data cache including shadow misses (FB hits, merge to an ongoing L1D miss)",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0xfd"
     },
     {
         "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.",
         "SampleAfterValue": "20011",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
         "SampleAfterValue": "20011",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.",
         "SampleAfterValue": "100003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.",
         "SampleAfterValue": "20011",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd3",
         "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
-        "PEBScounters": "0,1,2,3",
+        "PEBS": "1",
         "PublicDescription": "Retired load instructions which data sources missed L3 but serviced from local DRAM.",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd3",
         "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM",
-        "PEBScounters": "0,1,2,3",
+        "PEBS": "1",
         "SampleAfterValue": "1000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd3",
         "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD",
-        "PEBScounters": "0,1,2,3",
+        "PEBS": "1",
         "PublicDescription": "Retired load instructions whose data sources was forwarded from a remote cache.",
         "SampleAfterValue": "100007",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd3",
         "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM",
-        "PEBScounters": "0,1,2,3",
+        "PEBS": "1",
         "SampleAfterValue": "1000003",
         "UMask": "0x4"
     },
     {
-        "BriefDescription": "Retired load instructions with remote Intel Optane DC persistent memory as the data source where the data request missed all caches.",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.",
         "EventCode": "0xd3",
         "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM",
-        "PEBScounters": "0,1,2,3",
-        "PublicDescription": "Counts retired load instructions with remote Intel Optane DC persistent memory as the data source and the data request missed L3.",
+        "PublicDescription": "Counts retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3.",
         "SampleAfterValue": "100007",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd4",
         "EventName": "MEM_LOAD_MISC_RETIRED.UC",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock).",
         "SampleAfterValue": "100007",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.FB_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.",
         "SampleAfterValue": "100007",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L1_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.",
         "SampleAfterValue": "1000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired load instructions missed L1 cache as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L1_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
         "SampleAfterValue": "200003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L2_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Retired load instructions missed L2 cache as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L2_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
         "SampleAfterValue": "100021",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L3_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.",
         "SampleAfterValue": "100021",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Retired load instructions missed L3 cache as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L3_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.",
         "SampleAfterValue": "50021",
         "UMask": "0x20"
     },
     {
-        "BriefDescription": "Retired load instructions with local Intel Optane DC persistent memory as the data source where the data request missed all caches.",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.LOCAL_PMM",
-        "PEBScounters": "0,1,2,3",
-        "PublicDescription": "Counts retired load instructions with local Intel Optane DC persistent memory as the data source and the data request missed L3.",
+        "PEBS": "1",
+        "PublicDescription": "Counts retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3.",
         "SampleAfterValue": "1000003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "MEM_STORE_RETIRED.L2_HIT",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x44",
         "EventName": "MEM_STORE_RETIRED.L2_HIT",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired memory uops for any access",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xe5",
         "EventName": "MEM_UOP_RETIRED.ANY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of retired micro-operations (uops) for load or store memory accesses",
         "SampleAfterValue": "1000003",
         "UMask": "0x3"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1008000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x808000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1030000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x830000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1008000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x808000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_RFO.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1008000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x808000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.HWPF_L3.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80082380",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.READS_TO_CORE.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F003C4477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C4477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C4477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C4477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1830004477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1030004477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x830004477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1008004477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x808004477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO), hardware prefetch RFOs (which bring data to L2), and software prefetches for exclusive ownership (PREFETCHW) that hit to a (M)odified cacheline in the L3 or snoop filter.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.RFO_TO_CORE.L3_HIT_M",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1F80040022",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.STREAMING_WR.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080800",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OFFCORE_REQUESTS.ALL_REQUESTS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Demand and prefetch data reads",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "OFFCORE_REQUESTS.DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Demand Data Read requests sent to uncore",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
+        "Deprecated": "1",
         "EventCode": "0x20",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x20",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
+    {
+        "BriefDescription": "Cycles where at least 1 outstanding demand data read request is pending.",
+        "CounterMask": "1",
+        "EventCode": "0x20",
+        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
+        "SampleAfterValue": "2000003",
+        "UMask": "0x1"
+    },
     {
         "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x20",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
+    {
+        "BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.",
+        "EventCode": "0x20",
+        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
+        "PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.   Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
+        "SampleAfterValue": "1000003",
+        "UMask": "0x1"
+    },
     {
         "BriefDescription": "Number of PREFETCHNTA instructions executed.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "SW_PREFETCH_ACCESS.NTA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of PREFETCHW instructions executed.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Number of PREFETCHT0 instructions executed.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "SW_PREFETCH_ACCESS.T0",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x40",
         "EventName": "SW_PREFETCH_ACCESS.T1_T2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/floating-point.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/floating-point.json
index 32074d4556911..01baea3df5629 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/floating-point.json
@@ -1,222 +1,159 @@
 [
     {
         "BriefDescription": "ARITH.FPDIV_ACTIVE",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xb0",
         "EventName": "ARITH.FPDIV_ACTIVE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all microcode FP assists.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc1",
         "EventName": "ASSISTS.FP",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts all microcode Floating Point assists.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "ASSISTS.SSE_AVX_MIX",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc1",
         "EventName": "ASSISTS.SSE_AVX_MIX",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb3",
         "EventName": "FP_ARITH_DISPATCHED.PORT_0",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb3",
         "EventName": "FP_ARITH_DISPATCHED.PORT_1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb3",
         "EventName": "FP_ARITH_DISPATCHED.PORT_5",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xcf",
         "EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "100003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xcf",
         "EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "100003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xcf",
         "EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "100003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xcf",
         "EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "100003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex.",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xcf",
         "EventName": "FP_ARITH_INST_RETIRED2.SCALAR",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR",
         "SampleAfterValue": "100003",
         "UMask": "0x3"
     },
     {
         "BriefDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xcf",
         "EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired.",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xcf",
         "EventName": "FP_ARITH_INST_RETIRED2.VECTOR",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR",
         "SampleAfterValue": "100003",
         "UMask": "0x1c"
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/frontend.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/frontend.json
index ff0d47ce8e9a1..2c7c617f27ed8 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/frontend.json
@@ -1,498 +1,354 @@
 [
     {
         "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "DECODE.LCP",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
         "SampleAfterValue": "500009",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles the Microcode Sequencer is busy.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "DECODE.MS_BUSY",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "500009",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x61",
         "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Retired Instructions who experienced DSB miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x1",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.DSB_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x11",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.ITLB_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x14",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.L1I_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x12",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.L2_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x13",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x600106",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x608006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x601006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x600206",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x610006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x100206",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x602006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x600406",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x620006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x604006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x600806",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "FRONTEND_RETIRED.MS_FLOWS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.MS_FLOWS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x8",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.STLB_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x15",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x17",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "ICACHE_DATA.STALLS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at a 32 Byte granularity.",
         "SampleAfterValue": "500009",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "ICACHE_TAG.STALLS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
         "SampleAfterValue": "200003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_CYCLES_ANY",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Cycles DSB is delivering optimal number of Uops",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "6",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_CYCLES_OK",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_UOPS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Cycles MITE is delivering any Uop",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_CYCLES_ANY",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Cycles MITE is delivering optimal number of Uops",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "6",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_CYCLES_OK",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_UOPS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_CYCLES_ANY",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Number of switches from DSB or MITE to the MS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_SWITCHES",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Uops delivered to IDQ while MS is busy",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_UOPS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS).",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x9c",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "6",
         "EventCode": "0x9c",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x9c",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/memory.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/memory.json
index 6e761b628ca45..b72a36999930e 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/memory.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/memory.json
@@ -1,207 +1,150 @@
 [
     {
         "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "6",
         "EventCode": "0xa3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x6"
     },
     {
         "BriefDescription": "Number of machine clears due to memory ordering conflicts.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0x47",
         "EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "3",
         "EventCode": "0x47",
         "EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x3"
     },
     {
         "BriefDescription": "MEMORY_ACTIVITY.STALLS_L2_MISS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "5",
         "EventCode": "0x47",
         "EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x5"
     },
     {
         "BriefDescription": "MEMORY_ACTIVITY.STALLS_L3_MISS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "9",
         "EventCode": "0x47",
         "EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x9"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x80",
         "PEBS": "2",
-        "PEBScounters": "1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "1009",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x10",
         "PEBS": "2",
-        "PEBScounters": "1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "20011",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x100",
         "PEBS": "2",
-        "PEBScounters": "1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "503",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x20",
         "PEBS": "2",
-        "PEBScounters": "1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x4",
         "PEBS": "2",
-        "PEBScounters": "1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "100003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x200",
         "PEBS": "2",
-        "PEBScounters": "1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "101",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x40",
         "PEBS": "2",
-        "PEBScounters": "1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "2003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x8",
         "PEBS": "2",
-        "PEBScounters": "1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "50021",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.",
-        "CollectPEBSRecord": "2",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE",
@@ -212,225 +155,187 @@
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC00004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBFC00001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_RFO.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F3FC00002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.HWPF_L3.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x94002380",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.HWPF_L3.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84002380",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.READS_TO_CORE.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F3FC04477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F04C04477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.  It does not count misses to the L3 which go to Local CXL Type 2 Memory or Local Non DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x70CC04477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores that missed the local socket's L1, L2, and L3 caches.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.STREAMING_WR.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x94000800",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000800",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
+    {
+        "BriefDescription": "Counts demand data read requests that miss the L3 cache.",
+        "EventCode": "0x21",
+        "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
+        "SampleAfterValue": "100003",
+        "UMask": "0x10"
+    },
+    {
+        "BriefDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.",
+        "EventCode": "0x20",
+        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
+        "PublicDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.  Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known by the requesting core to have missed the L3 cache.",
+        "SampleAfterValue": "2000003",
+        "UMask": "0x10"
+    },
     {
         "BriefDescription": "Number of times an RTM execution aborted.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times RTM abort was triggered.",
         "SampleAfterValue": "100003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_EVENTS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
         "SampleAfterValue": "100003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MEM",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
         "SampleAfterValue": "100003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
         "SampleAfterValue": "100003",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
         "SampleAfterValue": "100003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Number of times an RTM execution successfully committed",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.COMMIT",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times RTM commit succeeded.",
         "SampleAfterValue": "100003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of times an RTM execution started.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.START",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CAPACITY_READ",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CONFLICT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/other.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/other.json
index 95dbef8ae80af..5d4c15dbf4d39 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/other.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/other.json
@@ -1,428 +1,341 @@
 [
     {
         "BriefDescription": "ASSISTS.PAGE_FAULT",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc1",
         "EventName": "ASSISTS.PAGE_FAULT",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts the cycles where the AMX (Advance Matrix Extension) unit is busy performing an operation.",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb7",
         "EventName": "EXE.AMX_BUSY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_CODE_RD.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x73C000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_CODE_RD.SNC_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x708000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_DATA_RD.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x73C000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_DATA_RD.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x730000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that were supplied by PMM attached to another socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_DATA_RD.REMOTE_PMM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x703000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_DATA_RD.SNC_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x708000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F3FFC0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_RFO.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x73C000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.DEMAND_RFO.SNC_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x708000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data load hardware prefetch requests to the L1 data cache that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.HWPF_L1D.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetches (which bring data to L2) that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.HWPF_L2.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10070",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetches to the L3 only that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.HWPF_L3.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x12380",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.HWPF_L3.REMOTE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x90002380",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writebacks of modified cachelines and streaming stores that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.MODIFIED_WRITE.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10808",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F3FFC4477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.READS_TO_CORE.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x73C004477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104004477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x70C004477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_PMM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x700C04477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.READS_TO_CORE.REMOTE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F33004477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.READS_TO_CORE.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x730004477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.READS_TO_CORE.REMOTE_MEMORY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x733004477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socket.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.READS_TO_CORE.REMOTE_PMM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x703004477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.READS_TO_CORE.SNC_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x708004477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10800",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A,0x2B",
         "EventName": "OCR.WRITE_ESTIMATE.MEMORY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xFBFF80822",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa5",
         "EventName": "RS.EMPTY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x7"
     },
     {
         "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xa5",
         "EventName": "RS.EMPTY_COUNT",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x7"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY_COUNT",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
+        "Deprecated": "1",
         "EdgeDetect": "1",
         "EventCode": "0xa5",
         "EventName": "RS_EMPTY.COUNT",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x7"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
+        "Deprecated": "1",
         "EventCode": "0xa5",
         "EventName": "RS_EMPTY.CYCLES",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x7"
     },
     {
         "BriefDescription": "XQ.FULL_CYCLES",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x2d",
         "EventName": "XQ.FULL_CYCLES",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json
index b2f0d9393d3ca..ceb14181ebc8d 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json
@@ -15,1357 +15,945 @@
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event ARITH.DIV_ACTIVE",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
+        "Deprecated": "1",
         "EventCode": "0xb0",
         "EventName": "ARITH.DIVIDER_ACTIVE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x9"
     },
     {
         "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xb0",
         "EventName": "ARITH.DIV_ACTIVE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x9"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event ARITH.FPDIV_ACTIVE",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
+        "Deprecated": "1",
         "EventCode": "0xb0",
         "EventName": "ARITH.FP_DIVIDER_ACTIVE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event counts the cycles the integer divider is busy.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb0",
         "EventName": "ARITH.IDIV_ACTIVE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event ARITH.IDIV_ACTIVE",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
+        "Deprecated": "1",
         "EventCode": "0xb0",
         "EventName": "ARITH.INT_DIVIDER_ACTIVE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc1",
         "EventName": "ASSISTS.ANY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware. Examples include AD (page Access Dirty), FP and AVX related assists.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1b"
     },
     {
         "BriefDescription": "All branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts all branch instructions retired.",
         "SampleAfterValue": "400009"
     },
     {
         "BriefDescription": "Conditional branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.COND",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts conditional branch instructions retired.",
         "SampleAfterValue": "400009",
         "UMask": "0x11"
     },
     {
         "BriefDescription": "Not taken branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.COND_NTAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts not taken branch instructions retired.",
         "SampleAfterValue": "400009",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Taken conditional branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.COND_TAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts taken conditional branch instructions retired.",
         "SampleAfterValue": "400009",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Far branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.FAR_BRANCH",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts far branch instructions retired.",
         "SampleAfterValue": "100007",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Indirect near branch instructions retired (excluding returns)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.INDIRECT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.",
         "SampleAfterValue": "100003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Direct and indirect near call instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts both direct and indirect near call instructions retired.",
         "SampleAfterValue": "100007",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Return instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.NEAR_RETURN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts return instructions retired.",
         "SampleAfterValue": "100007",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Taken branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts taken branch instructions retired.",
         "SampleAfterValue": "400009",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "All mispredicted branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch.  When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
         "SampleAfterValue": "400009"
     },
     {
         "BriefDescription": "Mispredicted conditional branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.COND",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts mispredicted conditional branch instructions retired.",
         "SampleAfterValue": "400009",
         "UMask": "0x11"
     },
     {
         "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.COND_NTAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.",
         "SampleAfterValue": "400009",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "number of branch instructions retired that were mispredicted and taken.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.COND_TAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts taken conditional mispredicted branch instructions retired.",
         "SampleAfterValue": "400009",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.INDIRECT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.",
         "SampleAfterValue": "100003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Mispredicted indirect CALL retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.INDIRECT_CALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.",
         "SampleAfterValue": "400009",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.",
         "SampleAfterValue": "400009",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.RET",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.",
         "SampleAfterValue": "100007",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xec",
         "EventName": "CPU_CLK_UNHALTED.C01",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state.  This state can be entered via the TPAUSE or UMWAIT instructions.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xec",
         "EventName": "CPU_CLK_UNHALTED.C02",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state.  This state can be entered via the TPAUSE or UMWAIT instructions.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI state.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xec",
         "EventName": "CPU_CLK_UNHALTED.C0_WAIT",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts core clocks when the thread is in the C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions) or running the PAUSE instruction.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x70"
     },
     {
         "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xec",
         "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0.  A hyperthread becomes inactive when it executes the HLT or MWAIT instructions.  If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.",
         "SampleAfterValue": "25003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "CPU_CLK_UNHALTED.PAUSE",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xec",
         "EventName": "CPU_CLK_UNHALTED.PAUSE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "CPU_CLK_UNHALTED.PAUSE_INST",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xec",
         "EventName": "CPU_CLK_UNHALTED.PAUSE_INST",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Reference cycles when the core is not in halt state.",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 2",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
-        "PEBScounters": "34",
         "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x3"
     },
     {
         "BriefDescription": "Reference cycles when the core is not in halt state.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Core cycles when the thread is not in halt state",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD",
-        "PEBScounters": "33",
         "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Thread cycles when thread is not in halt state",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
-        "SampleAfterValue": "2000003",
-        "Speculative": "1"
+        "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "8",
         "EventCode": "0xa3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xa3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "16",
         "EventCode": "0xa3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "12",
         "EventCode": "0xa3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0xc"
     },
     {
         "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "5",
         "EventCode": "0xa3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x5"
     },
     {
         "BriefDescription": "Total execution stalls.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xa3",
         "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa6",
         "EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa6",
         "EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa6",
         "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa6",
         "EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "5",
         "EventCode": "0xa6",
         "EventName": "EXE_ACTIVITY.BOUND_ON_LOADS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x21"
     },
     {
         "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xa6",
         "EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Cycles no uop executed while RS was not empty, the SB was not full and there was no outstanding load.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa6",
         "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of cycles total of 0 uops executed on all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) was not full and there was no outstanding load.",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Instruction decoders utilized in a cycle",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x75",
         "EventName": "INST_DECODED.DECODERS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 0",
         "EventName": "INST_RETIRED.ANY",
         "PEBS": "1",
-        "PEBScounters": "32",
         "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of instructions retired. General Counter - architectural event",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc0",
         "EventName": "INST_RETIRED.ANY_P",
         "PEBS": "1",
-        "PEBScounters": "1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "INST_RETIRED.MACRO_FUSED",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc0",
         "EventName": "INST_RETIRED.MACRO_FUSED",
-        "PEBScounters": "1,2,3,4,5,6,7",
         "SampleAfterValue": "2000003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Retired NOP instructions.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc0",
         "EventName": "INST_RETIRED.NOP",
-        "PEBScounters": "1,2,3,4,5,6,7",
         "PublicDescription": "Counts all retired NOP or ENDBR32/64 instructions",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Precise instruction retired with PEBS precise-distribution",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 0",
         "EventName": "INST_RETIRED.PREC_DIST",
         "PEBS": "1",
-        "PEBScounters": "32",
         "PublicDescription": "A version of INST_RETIRED that allows for a precise distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Counter 0.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "INST_RETIRED.REP_ITERATION",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc0",
         "EventName": "INST_RETIRED.REP_ITERATION",
-        "PEBScounters": "1,2,3,4,5,6,7",
         "SampleAfterValue": "2000003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xad",
         "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
         "SampleAfterValue": "500009",
-        "Speculative": "1",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "INT_MISC.MBA_STALLS",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xad",
         "EventName": "INT_MISC.MBA_STALLS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xad",
         "EventName": "INT_MISC.RECOVERY_CYCLES",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
         "SampleAfterValue": "500009",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "INT_MISC.UNKNOWN_BRANCH_CYCLES",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xad",
         "EventName": "INT_MISC.UNKNOWN_BRANCH_CYCLES",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x7",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
-        "TakenAlone": "1",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "TMA slots where uops got dropped",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xad",
         "EventName": "INT_MISC.UOP_DROPPING",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "INT_VEC_RETIRED.128BIT",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xe7",
         "EventName": "INT_VEC_RETIRED.128BIT",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
         "UMask": "0x13"
     },
     {
         "BriefDescription": "INT_VEC_RETIRED.256BIT",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xe7",
         "EventName": "INT_VEC_RETIRED.256BIT",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
         "UMask": "0xac"
     },
     {
         "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xe7",
         "EventName": "INT_VEC_RETIRED.ADD_128",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vector instructions.",
         "SampleAfterValue": "1000003",
         "UMask": "0x3"
     },
     {
         "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xe7",
         "EventName": "INT_VEC_RETIRED.ADD_256",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vector instructions.",
         "SampleAfterValue": "1000003",
         "UMask": "0xc"
     },
     {
         "BriefDescription": "INT_VEC_RETIRED.MUL_256",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xe7",
         "EventName": "INT_VEC_RETIRED.MUL_256",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "INT_VEC_RETIRED.SHUFFLES",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xe7",
         "EventName": "INT_VEC_RETIRED.SHUFFLES",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "INT_VEC_RETIRED.VNNI_128",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xe7",
         "EventName": "INT_VEC_RETIRED.VNNI_128",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "INT_VEC_RETIRED.VNNI_256",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xe7",
         "EventName": "INT_VEC_RETIRED.VNNI_256",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "False dependencies in MOB due to partial compare on address.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.ADDRESS_ALIAS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.NO_SR",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x88"
     },
     {
         "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.STORE_FORWARD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x82"
     },
     {
         "BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4c",
         "EventName": "LOAD_HIT_PREFETCH.SWPF",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xa8",
         "EventName": "LSD.CYCLES_ACTIVE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "6",
         "EventCode": "0xa8",
         "EventName": "LSD.CYCLES_OK",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of Uops delivered by the LSD.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa8",
         "EventName": "LSD.UOPS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of machine clears (nukes) of any type.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.COUNT",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of machine clears (nukes) of any type.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Self-modifying code (SMC) detected.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.SMC",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "MISC2_RETIRED.LFENCE",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xe0",
         "EventName": "MISC2_RETIRED.LFENCE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "400009",
-        "Speculative": "1",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Increments whenever there is an update to the LBR array.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xcc",
         "EventName": "MISC_RETIRED.LBR_INSERTS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.",
         "SampleAfterValue": "100003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa2",
         "EventName": "RESOURCE_STALLS.SB",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa2",
         "EventName": "RESOURCE_STALLS.SCOREBOARD",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa4",
         "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of slots in TMA method where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
         "SampleAfterValue": "10000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "TMA slots wasted due to incorrect speculations.",
-        "CollectPEBSRecord": "2",
         "EventCode": "0xa4",
         "EventName": "TOPDOWN.BAD_SPEC_SLOTS",
         "PublicDescription": "Number of slots of TMA method that were wasted due to incorrect speculation. It covers all types of control-flow or data-related mis-speculations.",
         "SampleAfterValue": "10000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions",
-        "CollectPEBSRecord": "2",
         "EventCode": "0xa4",
         "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS",
         "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of specualtive operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction.",
         "SampleAfterValue": "10000003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "TOPDOWN.MEMORY_BOUND_SLOTS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa4",
         "EventName": "TOPDOWN.MEMORY_BOUND_SLOTS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "10000003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 3",
         "EventName": "TOPDOWN.SLOTS",
-        "PEBScounters": "35",
         "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
         "SampleAfterValue": "10000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa4",
         "EventName": "TOPDOWN.SLOTS_P",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
         "SampleAfterValue": "10000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "UOPS_DECODED.DEC0_UOPS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x76",
         "EventName": "UOPS_DECODED.DEC0_UOPS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Uops executed on port 0",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb2",
         "EventName": "UOPS_DISPATCHED.PORT_0",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of uops dispatch to execution  port 0.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Uops executed on port 1",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb2",
         "EventName": "UOPS_DISPATCHED.PORT_1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of uops dispatch to execution  port 1.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Uops executed on ports 2, 3 and 10",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb2",
         "EventName": "UOPS_DISPATCHED.PORT_2_3_10",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of uops dispatch to execution ports 2, 3 and 10",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Uops executed on ports 4 and 9",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb2",
         "EventName": "UOPS_DISPATCHED.PORT_4_9",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of uops dispatch to execution ports 4 and 9",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Uops executed on ports 5 and 11",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb2",
         "EventName": "UOPS_DISPATCHED.PORT_5_11",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of uops dispatch to execution ports 5 and 11",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Uops executed on port 6",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb2",
         "EventName": "UOPS_DISPATCHED.PORT_6",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of uops dispatch to execution  port 6.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Uops executed on ports 7 and 8",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb2",
         "EventName": "UOPS_DISPATCHED.PORT_7_8",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of uops dispatch to execution  ports 7 and 8.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Number of uops executed on the core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of uops executed from any thread.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_3",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_4",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.STALLS",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UOPS_EXECUTED.STALLS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
+        "Deprecated": "1",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.STALL_CYCLES",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.THREAD",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of x87 uops dispatched.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.X87",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of x87 uops executed.",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Uops that RAT issues to RS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xae",
         "EventName": "UOPS_ISSUED.ANY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
         "SampleAfterValue": "2000003",
-        "Speculative": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles with retired uop(s).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.CYCLES",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles where at least one uop has retired.",
         "SampleAfterValue": "1000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Retired uops except the last uop of each instruction.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.HEAVY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of each instruction. An instruction that is decoded into less than two uops does not contribute to the count.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "UOPS_RETIRED.MS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.MS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x8",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "2000003",
-        "TakenAlone": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Retirement slots used.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.SLOTS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the retirement slots used each cycle.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles without actually retired uops.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.STALLS",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "This event counts cycles without actually retired uops.",
         "SampleAfterValue": "1000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UOPS_RETIRED.STALLS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
+        "Deprecated": "1",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.STALL_CYCLES",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
         "UMask": "0x2"
     }
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json
index 9ec42a68c160a..ce18fc458e371 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json
@@ -1,1643 +1,1616 @@
 [
     {
-        "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
-        "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / SLOTS",
-        "MetricGroup": "PGO;TopdownL1;tma_L1_group",
-        "MetricName": "tma_frontend_bound",
-        "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
+        "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
+        "MetricGroup": "Bad;BadSpec;BrMispredicts",
+        "MetricName": "Mispredictions"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
-        "MetricExpr": "(topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / SLOTS)",
-        "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
-        "MetricName": "tma_fetch_latency",
-        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
+        "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))",
+        "MetricGroup": "Mem;MemoryBW;Offcore",
+        "MetricName": "Memory_Bandwidth"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses",
-        "MetricExpr": "ICACHE_DATA.STALLS / CLKS",
-        "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_icache_misses",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
+        "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound))",
+        "MetricGroup": "Mem;MemoryLat;Offcore",
+        "MetricName": "Memory_Latency"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses",
-        "MetricExpr": "ICACHE_TAG.STALLS / CLKS",
-        "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_itlb_misses",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
+        "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))",
+        "MetricGroup": "Mem;MemoryTLB;Offcore",
+        "MetricName": "Memory_Data_TLBs"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
-        "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CLKS + tma_unknown_branches",
-        "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_branch_resteers",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)",
+        "MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)",
+        "MetricGroup": "Ret",
+        "MetricName": "Branching_Overhead"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage",
-        "MetricExpr": "(tma_branch_mispredicts / tma_bad_speculation) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
-        "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group",
-        "MetricName": "tma_mispredicts_resteers",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage.  Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)",
+        "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)",
+        "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB",
+        "MetricName": "Big_Code"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears",
-        "MetricExpr": "(1 - (tma_branch_mispredicts / tma_bad_speculation)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
-        "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group",
-        "MetricName": "tma_clears_resteers",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears.  Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks",
+        "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code",
+        "MetricGroup": "Fed;FetchBW;Frontend",
+        "MetricName": "Instruction_Fetch_BW"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
-        "MetricExpr": "INT_MISC.UNKNOWN_BRANCH_CYCLES / CLKS",
-        "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_branch_resteers_group",
-        "MetricName": "tma_unknown_branches",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: FRONTEND_RETIRED.UNKNOWN_BRANCH",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
+        "MetricExpr": "INST_RETIRED.ANY / CLKS",
+        "MetricGroup": "Ret;Summary",
+        "MetricName": "IPC"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
-        "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS",
-        "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_dsb_switches",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Uops Per Instruction",
+        "MetricExpr": "tma_retiring * SLOTS / INST_RETIRED.ANY",
+        "MetricGroup": "Pipeline;Ret;Retire",
+        "MetricName": "UPI"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
-        "MetricExpr": "DECODE.LCP / CLKS",
-        "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_lcp",
-        "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instruction per taken branch",
+        "MetricExpr": "tma_retiring * SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
+        "MetricGroup": "Branches;Fed;FetchBW",
+        "MetricName": "UpTB"
     },
     {
-        "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
-        "MetricExpr": "3 * IDQ.MS_SWITCHES / CLKS",
-        "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_ms_switches",
-        "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: FRONTEND_RETIRED.MS_FLOWS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
+        "MetricExpr": "1 / IPC",
+        "MetricGroup": "Mem;Pipeline",
+        "MetricName": "CPI"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
-        "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
-        "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
-        "MetricName": "tma_fetch_bandwidth",
-        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues.  For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "Pipeline",
+        "MetricName": "CLKS"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
-        "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / CORE_CLKS / 2",
-        "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
-        "MetricName": "tma_mite",
-        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
+        "MetricExpr": "TOPDOWN.SLOTS",
+        "MetricGroup": "tma_L1_group",
+        "MetricName": "SLOTS"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder",
-        "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) / CORE_CLKS",
-        "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_mite_group",
-        "MetricName": "tma_decoder0_alone",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
+        "MetricExpr": "(SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)",
+        "MetricGroup": "SMT;tma_L1_group",
+        "MetricName": "Slots_Utilization"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
-        "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / CORE_CLKS / 2",
-        "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
-        "MetricName": "tma_dsb",
-        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline.  For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "The ratio of Executed- by Issued-Uops",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
+        "MetricGroup": "Cor;Pipeline",
+        "MetricName": "Execute_per_Issue",
+        "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
     },
     {
-        "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
-        "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)",
-        "MetricGroup": "TopdownL1;tma_L1_group",
-        "MetricName": "tma_bad_speculation",
-        "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
+        "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
+        "MetricGroup": "Ret;SMT;tma_L1_group",
+        "MetricName": "CoreIPC"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
-        "MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
-        "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
-        "MetricName": "tma_branch_mispredicts",
-        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Floating Point Operations Per Cycle",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF + 4 * AMX_OPS_RETIRED.BF16) / CORE_CLKS",
+        "MetricGroup": "Flops;Ret",
+        "MetricName": "FLOPc"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
-        "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)",
-        "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group",
-        "MetricName": "tma_machine_clears",
-        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears.  These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
+        "MetricExpr": "(FP_ARITH_DISPATCHED.PORT_0 + FP_ARITH_DISPATCHED.PORT_1 + FP_ARITH_DISPATCHED.PORT_5) / (2 * CORE_CLKS)",
+        "MetricGroup": "Cor;Flops;HPC",
+        "MetricName": "FP_Arith_Utilization",
+        "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
     },
     {
-        "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
-        "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
-        "MetricGroup": "TopdownL1;tma_L1_group",
-        "MetricName": "tma_backend_bound",
-        "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
+        "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
+        "MetricName": "ILP"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
-        "MetricExpr": "topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
-        "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
-        "MetricName": "tma_memory_bound",
-        "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
+        "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)",
+        "MetricGroup": "Cor;SMT",
+        "MetricName": "Core_Bound_Likely"
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
-        "MetricExpr": "max((EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS) / CLKS, 0)",
-        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_l1_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache.  The L1 data cache typically has the shortest latency.  However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
+        "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED",
+        "MetricGroup": "SMT",
+        "MetricName": "CORE_CLKS"
     },
     {
-        "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
-        "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS, 0)) / CLKS",
-        "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_dtlb_load",
-        "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS",
+        "MetricGroup": "InsType",
+        "MetricName": "IpLoad"
     },
     {
-        "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
-        "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
-        "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group",
-        "MetricName": "tma_load_stlb_hit",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES",
+        "MetricGroup": "InsType",
+        "MetricName": "IpStore"
     },
     {
-        "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk",
-        "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CLKS",
-        "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group",
-        "MetricName": "tma_load_stlb_miss",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Branches;Fed;InsType",
+        "MetricName": "IpBranch"
     },
     {
-        "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
-        "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS",
-        "MetricGroup": "TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_store_fwd_blk",
-        "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
+        "MetricGroup": "Branches;Fed;PGO",
+        "MetricName": "IpCall"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
-        "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
-        "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_lock_latency",
-        "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instruction per taken branch",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
+        "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
+        "MetricName": "IpTB"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary",
-        "MetricExpr": "Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS",
-        "MetricGroup": "TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_split_loads",
-        "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary.  Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Branch instructions per taken branch. ",
+        "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
+        "MetricGroup": "Branches;Fed;PGO",
+        "MetricName": "BpTkBranch"
     },
     {
-        "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
-        "MetricExpr": "L1D_PEND_MISS.FB_FULL / CLKS",
-        "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_fb_full",
-        "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF + 4 * AMX_OPS_RETIRED.BF16)",
+        "MetricGroup": "Flops;InsType",
+        "MetricName": "IpFLOP"
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
-        "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS) / CLKS",
-        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_l2_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.VECTOR))",
+        "MetricGroup": "Flops;InsType",
+        "MetricName": "IpArith",
+        "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
-        "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS) / CLKS",
-        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_l3_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
+        "MetricGroup": "Flops;FpScalar;InsType",
+        "MetricName": "IpArith_Scalar_SP",
+        "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
-        "MetricExpr": "((25 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + (24 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_contested_accesses",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
+        "MetricGroup": "Flops;FpScalar;InsType",
+        "MetricName": "IpArith_Scalar_DP",
+        "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
-        "MetricExpr": "(24 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD)))) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_data_sharing",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF)",
+        "MetricGroup": "Flops;FpVector;InsType",
+        "MetricName": "IpArith_AVX128",
+        "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
-        "MetricExpr": "(9 * Average_Frequency) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_l3_hit_latency",
-        "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF)",
+        "MetricGroup": "Flops;FpVector;InsType",
+        "MetricName": "IpArith_AVX256",
+        "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
-        "MetricExpr": "(XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS) / CLKS",
-        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_sq_full",
-        "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF)",
+        "MetricGroup": "Flops;FpVector;InsType",
+        "MetricName": "IpArith_AVX512",
+        "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
-        "MetricExpr": "((MEMORY_ACTIVITY.STALLS_L3_MISS / CLKS) - tma_pmm_bound)",
-        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_dram_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic AMX operation (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / AMX_OPS_RETIRED.BF16",
+        "MetricGroup": "Flops;FpVector;InsType;Server",
+        "MetricName": "IpArith_AMX_F16",
+        "PublicDescription": "Instructions per FP Arithmetic AMX operation (lower number means higher occurrence rate). Operations factored per matrices' sizes of the AMX instructions."
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
-        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / CLKS",
-        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group",
-        "MetricName": "tma_mem_bandwidth",
-        "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM).  The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Integer Arithmetic AMX operation (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / AMX_OPS_RETIRED.INT8",
+        "MetricGroup": "InsType;IntVector;Server",
+        "MetricName": "IpArith_AMX_Int8",
+        "PublicDescription": "Instructions per Integer Arithmetic AMX operation (lower number means higher occurrence rate). Operations factored per matrices' sizes of the AMX instructions."
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to memory bandwidth Allocation feature (RDT's memory bandwidth throttling).",
-        "MetricExpr": "INT_MISC.MBA_STALLS / CLKS",
-        "MetricGroup": "MemoryBW;Offcore;Server;TopdownL5;tma_mem_bandwidth_group",
-        "MetricName": "tma_mba_stalls",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@",
+        "MetricGroup": "Prefetches",
+        "MetricName": "IpSWPF"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
-        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth",
-        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group",
-        "MetricName": "tma_mem_latency",
-        "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM).  This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
+        "MetricExpr": "INST_RETIRED.ANY",
+        "MetricGroup": "Summary;tma_L1_group",
+        "MetricName": "Instructions"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
-        "MetricExpr": "(54.5 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "Server;TopdownL5;tma_mem_latency_group",
-        "MetricName": "tma_local_dram",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
+        "MetricExpr": "tma_retiring * SLOTS / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
+        "MetricGroup": "Pipeline;Ret",
+        "MetricName": "Retire"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
-        "MetricExpr": "(119 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "Server;Snoop;TopdownL5;tma_mem_latency_group",
-        "MetricName": "tma_remote_dram",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions",
+        "MetricExpr": "INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
+        "MetricGroup": "Pipeline;Ret",
+        "MetricName": "Strings_Cycles"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
-        "MetricExpr": "((108 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + (108 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_mem_latency_group",
-        "MetricName": "tma_remote_cache",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / cpu@ASSISTS.ANY\\,umask\\=0x1B@",
+        "MetricGroup": "Pipeline;Ret;Retire",
+        "MetricName": "IpAssist"
     },
     {
-        "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a",
-        "MetricExpr": "(((1 - ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + 10 * ((MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) / ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + 10 * ((MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))))) * (MEMORY_ACTIVITY.STALLS_L3_MISS / CLKS)) if (1000000 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS) else 0)",
-        "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_pmm_bound",
-        "PublicDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ",
-        "ScaleUnit": "100%"
+        "BriefDescription": "",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
+        "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
+        "MetricName": "Execute"
     },
     {
-        "BriefDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
-        "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CLKS",
-        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_store_bound",
-        "PublicDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average number of Uops issued by front-end when it issued something",
+        "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@",
+        "MetricGroup": "Fed;FetchBW",
+        "MetricName": "Fetch_UpC"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
-        "MetricExpr": "((MEM_STORE_RETIRED.L2_HIT * 10 * (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES))) + (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
-        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_store_latency",
-        "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
+        "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
+        "MetricGroup": "DSB;Fed;FetchBW",
+        "MetricName": "DSB_Coverage"
     },
     {
-        "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
-        "MetricExpr": "(28 * Average_Frequency) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
-        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_false_sharing",
-        "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line.  Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
+        "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@",
+        "MetricGroup": "DSBmiss",
+        "MetricName": "DSB_Switch_Cost"
+    },
+    {
+        "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
+        "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))",
+        "MetricGroup": "DSBmiss;Fed",
+        "MetricName": "DSB_Misses"
     },
     {
-        "BriefDescription": "This metric represents rate of split store accesses",
-        "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CORE_CLKS",
-        "MetricGroup": "TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_split_stores",
-        "PublicDescription": "This metric represents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS",
+        "MetricGroup": "DSBmiss;Fed",
+        "MetricName": "IpDSB_Miss_Ret"
     },
     {
-        "BriefDescription": "This metric estimates how often CPU was stalled  due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores",
-        "MetricExpr": "9 * OCR.STREAMING_WR.ANY_RESPONSE / CLKS",
-        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_streaming_stores",
-        "PublicDescription": "This metric estimates how often CPU was stalled  due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck. Sample with: OCR.STREAMING_WR.ANY_RESPONSE",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;BadSpec;BrMispredicts",
+        "MetricName": "IpMispredict"
     },
     {
-        "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
-        "MetricExpr": "(7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CORE_CLKS",
-        "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_dtlb_store",
-        "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead.  Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page.  Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
+        "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;BrMispredicts",
+        "MetricName": "Branch_Misprediction_Cost"
     },
     {
-        "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
-        "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
-        "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group",
-        "MetricName": "tma_store_stlb_hit",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of branches that are non-taken conditionals",
+        "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;Branches;CodeGen;PGO",
+        "MetricName": "Cond_NT"
     },
     {
-        "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk",
-        "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS",
-        "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group",
-        "MetricName": "tma_store_stlb_miss",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of branches that are taken conditionals",
+        "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;Branches;CodeGen;PGO",
+        "MetricName": "Cond_TK"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
-        "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)",
-        "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group",
-        "MetricName": "tma_core_bound",
-        "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of branches that are CALL or RET",
+        "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;Branches",
+        "MetricName": "CallRet"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
-        "MetricExpr": "ARITH.DIVIDER_ACTIVE / CLKS",
-        "MetricGroup": "TopdownL3;tma_core_bound_group",
-        "MetricName": "tma_divider",
-        "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps",
+        "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;Branches",
+        "MetricName": "Jump"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
-        "MetricExpr": "(cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@)) / CLKS if (ARITH.DIVIDER_ACTIVE < (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS)) else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@) / CLKS",
-        "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
-        "MetricName": "tma_ports_utilization",
-        "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)",
+        "MetricExpr": "1 - (Cond_NT + Cond_TK + CallRet + Jump)",
+        "MetricGroup": "Bad;Branches",
+        "MetricName": "Other_Branches"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / CLKS + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS) / CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_0",
-        "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
+        "MetricExpr": "L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY",
+        "MetricGroup": "Mem;MemoryBound;MemoryLat",
+        "MetricName": "Load_Miss_Real_Latency"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations",
-        "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / CLKS",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_0_group",
-        "MetricName": "tma_serializing_operation",
-        "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
+        "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
+        "MetricGroup": "Mem;MemoryBW;MemoryBound",
+        "MetricName": "MLP"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions",
-        "MetricExpr": "CPU_CLK_UNHALTED.PAUSE / CLKS",
-        "MetricGroup": "TopdownL6;tma_serializing_operation_group",
-        "MetricName": "tma_slow_pause",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: CPU_CLK_UNHALTED.PAUSE_INST",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L1MPKI"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions.",
-        "MetricExpr": "13 * MISC2_RETIRED.LFENCE / CLKS",
-        "MetricGroup": "TopdownL6;tma_serializing_operation_group",
-        "MetricName": "tma_memory_fence",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
+        "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L1MPKI_Load"
     },
     {
-        "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued",
-        "MetricExpr": "160 * ASSISTS.SSE_AVX_MIX / CLKS",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_0_group",
-        "MetricName": "tma_mixing_vectors",
-        "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+        "MetricGroup": "Backend;CacheMisses;Mem",
+        "MetricName": "L2MPKI"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles where the Advanced Matrix Extensions (AMX) execution engine was busy with tile (arithmetic) operations",
-        "MetricExpr": "EXE.AMX_BUSY / CORE_CLKS",
-        "MetricGroup": "Compute;HPC;Server;TopdownL5;tma_ports_utilized_0_group",
-        "MetricName": "tma_amx_busy",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
+        "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem;Offcore",
+        "MetricName": "L2MPKI_All"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "EXE_ACTIVITY.1_PORTS_UTIL / CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_1",
-        "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (including speculative)",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L2MPKI_Load"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "EXE_ACTIVITY.2_PORTS_UTIL / CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_2",
-        "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
+        "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L2HPKI_All"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_3m",
-        "PublicDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache hits per kilo instruction for all demand loads  (including speculative)",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L2HPKI_Load"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
-        "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5_11 + UOPS_DISPATCHED.PORT_6) / (5 * CORE_CLKS)",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
-        "MetricName": "tma_alu_op_utilization",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L3MPKI"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED.PORT_0",
-        "MetricExpr": "UOPS_DISPATCHED.PORT_0 / CORE_CLKS",
-        "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group",
-        "MetricName": "tma_port_0",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "FB_HPKI"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED.PORT_1",
-        "MetricExpr": "UOPS_DISPATCHED.PORT_1 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
-        "MetricName": "tma_port_1",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
+        "MetricConstraint": "NO_NMI_WATCHDOG",
+        "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (4 * CORE_CLKS)",
+        "MetricGroup": "Mem;MemoryTLB",
+        "MetricName": "Page_Walks_Utilization"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) Sample with: UOPS_DISPATCHED.PORT_6",
-        "MetricExpr": "UOPS_DISPATCHED.PORT_6 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
-        "MetricName": "tma_port_6",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
+        "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L1D_Cache_Fill_BW"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3_10",
-        "MetricExpr": "UOPS_DISPATCHED.PORT_2_3_10 / (3 * CORE_CLKS)",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
-        "MetricName": "tma_load_op_utilization",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
+        "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L2_Cache_Fill_BW"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations Sample with: UOPS_DISPATCHED.PORT_7_8",
-        "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * CORE_CLKS)",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
-        "MetricName": "tma_store_op_utilization",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
+        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L3_Cache_Fill_BW"
     },
     {
-        "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
-        "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
-        "MetricGroup": "TopdownL1;tma_L1_group",
-        "MetricName": "tma_retiring",
-        "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided.  Sample with: UOPS_RETIRED.SLOTS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
+        "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW;Offcore",
+        "MetricName": "L3_Cache_Access_BW"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
-        "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)",
-        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
-        "MetricName": "tma_light_operations",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
+        "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / Instructions",
+        "MetricGroup": "L2Evicts;Mem;Server",
+        "MetricName": "L2_Evictions_Silent_PKI"
     },
     {
-        "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
-        "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector + tma_fp_amx",
-        "MetricGroup": "HPC;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_fp_arith",
-        "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
+        "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / Instructions",
+        "MetricGroup": "L2Evicts;Mem;Server",
+        "MetricName": "L2_Evictions_NonSilent_PKI"
     },
     {
-        "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
-        "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD",
-        "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group",
-        "MetricName": "tma_x87_use",
-        "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
+        "MetricExpr": "L1D_Cache_Fill_BW",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L1D_Cache_Fill_BW_1T"
     },
     {
-        "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR) / (tma_retiring * SLOTS)",
-        "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group",
-        "MetricName": "tma_fp_scalar",
-        "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
+        "MetricExpr": "L2_Cache_Fill_BW",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L2_Cache_Fill_BW_1T"
     },
     {
-        "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.VECTOR) / (tma_retiring * SLOTS)",
-        "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group",
-        "MetricName": "tma_fp_vector",
-        "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
+        "MetricExpr": "L3_Cache_Fill_BW",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L3_Cache_Fill_BW_1T"
     },
     {
-        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF) / (tma_retiring * SLOTS)",
-        "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
-        "MetricName": "tma_fp_vector_128b",
-        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
+        "MetricExpr": "L3_Cache_Access_BW",
+        "MetricGroup": "Mem;MemoryBW;Offcore",
+        "MetricName": "L3_Cache_Access_BW_1T"
     },
     {
-        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF) / (tma_retiring * SLOTS)",
-        "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
-        "MetricName": "tma_fp_vector_256b",
-        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average CPU Utilization",
+        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+        "MetricGroup": "HPC;Summary",
+        "MetricName": "CPU_Utilization"
     },
     {
-        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) / (tma_retiring * SLOTS)",
-        "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
-        "MetricName": "tma_fp_vector_512b",
-        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
+        "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
+        "MetricGroup": "Power;Summary",
+        "MetricName": "Average_Frequency"
     },
     {
-        "BriefDescription": "This metric approximates arithmetic floating-point (FP) matrix uops fraction the CPU has retired (aggregated across all supported FP datatypes in AMX engine)",
-        "MetricExpr": "cpu@AMX_OPS_RETIRED.BF16\\,cmask\\=1@ / (tma_retiring * SLOTS)",
-        "MetricGroup": "Compute;Flops;HPC;Pipeline;Server;TopdownL4;tma_fp_arith_group",
-        "MetricName": "tma_fp_amx",
-        "PublicDescription": "This metric approximates arithmetic floating-point (FP) matrix uops fraction the CPU has retired (aggregated across all supported FP datatypes in AMX engine). Refer to AMX_Busy and GFLOPs metrics for actual AMX utilization and FP performance, resp.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Giga Floating Point Operations Per Second",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF + 4 * AMX_OPS_RETIRED.BF16) / 1e9 / duration_time",
+        "MetricGroup": "Cor;Flops;HPC",
+        "MetricName": "GFLOPs",
+        "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
     },
     {
-        "BriefDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired)",
-        "MetricExpr": "tma_int_vector_128b + tma_int_vector_256b + tma_shuffles",
-        "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_int_operations",
-        "PublicDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired). Vector/Matrix Int operations and shuffles are counted. Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Tera Integer (matrix) Operations Per Second",
+        "MetricExpr": "8 * AMX_OPS_RETIRED.INT8 / 1e12 / duration_time",
+        "MetricGroup": "Cor;HPC;IntVector;Server",
+        "MetricName": "TIOPS"
     },
     {
-        "BriefDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.",
-        "MetricExpr": "(INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128) / (tma_retiring * SLOTS)",
-        "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_int_operations_group",
-        "MetricName": "tma_int_vector_128b",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average Frequency Utilization relative nominal frequency",
+        "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
+        "MetricGroup": "Power",
+        "MetricName": "Turbo_Utilization"
     },
     {
-        "BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.",
-        "MetricExpr": "(INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256) / (tma_retiring * SLOTS)",
-        "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_int_operations_group",
-        "MetricName": "tma_int_vector_256b",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
+        "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)",
+        "MetricGroup": "SMT",
+        "MetricName": "SMT_2T_Utilization"
     },
     {
-        "BriefDescription": "This metric approximates arithmetic Integer (Int) matrix uops fraction the CPU has retired (aggregated across all supported Int datatypes in AMX engine)",
-        "MetricExpr": "cpu@AMX_OPS_RETIRED.INT8\\,cmask\\=1@ / (tma_retiring * SLOTS)",
-        "MetricGroup": "Compute;HPC;IntVector;Pipeline;Server;TopdownL4;tma_int_operations_group",
-        "MetricName": "tma_int_amx",
-        "PublicDescription": "This metric approximates arithmetic Integer (Int) matrix uops fraction the CPU has retired (aggregated across all supported Int datatypes in AMX engine). Refer to AMX_Busy and TIOPs metrics for actual AMX utilization and Int performance, resp.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "OS",
+        "MetricName": "Kernel_Utilization"
     },
     {
-        "BriefDescription": "This metric represents Shuffle (cross \"vector lane\" data transfers) uops fraction the CPU has retired.",
-        "MetricExpr": "INT_VEC_RETIRED.SHUFFLES / (tma_retiring * SLOTS)",
-        "MetricGroup": "HPC;Pipeline;TopdownL4;tma_int_operations_group",
-        "MetricName": "tma_shuffles",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
+        "MetricGroup": "OS",
+        "MetricName": "Kernel_CPI"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.",
-        "MetricExpr": "tma_light_operations * MEM_UOP_RETIRED.ANY / (tma_retiring * SLOTS)",
-        "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_memory_operations",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
+        "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time",
+        "MetricGroup": "HPC;Mem;MemoryBW;SoC",
+        "MetricName": "DRAM_BW_Use"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions",
-        "MetricExpr": "tma_light_operations * INST_RETIRED.MACRO_FUSED / (tma_retiring * SLOTS)",
-        "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_fused_instructions",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
+        "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (Socket_CLKS / duration_time)",
+        "MetricGroup": "Mem;MemoryLat;SoC",
+        "MetricName": "MEM_Read_Latency"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused",
-        "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED) / (tma_retiring * SLOTS)",
-        "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_non_fused_branches",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
+        "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@thresh\\=1@",
+        "MetricGroup": "Mem;MemoryBW;SoC",
+        "MetricName": "MEM_Parallel_Reads"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions",
-        "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_retiring * SLOTS)",
-        "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_nop_instructions",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
+        "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / uncore_cha_0@event\\=0x1@",
+        "MetricGroup": "Mem;MemoryLat;Server;SoC",
+        "MetricName": "MEM_PMM_Read_Latency"
     },
     {
-        "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting",
-        "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_int_operations + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions))",
-        "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_other_light_ops",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
+        "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / uncore_cha_0@event\\=0x1@",
+        "MetricGroup": "Mem;MemoryLat;Server;SoC",
+        "MetricName": "MEM_DRAM_Read_Latency"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
-        "MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
-        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
-        "MetricName": "tma_heavy_operations",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences. Sample with: UOPS_RETIRED.HEAVY",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]",
+        "MetricExpr": "64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW;Server;SoC",
+        "MetricName": "PMM_Read_BW"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops",
-        "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer",
-        "MetricGroup": "TopdownL3;tma_heavy_operations_group",
-        "MetricName": "tma_few_uops_instructions",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]",
+        "MetricExpr": "64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW;Server;SoC",
+        "MetricName": "PMM_Write_BW"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
-        "MetricExpr": "UOPS_RETIRED.MS / SLOTS",
-        "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
-        "MetricName": "tma_microcode_sequencer",
-        "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]",
+        "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e9 / duration_time",
+        "MetricGroup": "IoBW;Mem;Server;SoC",
+        "MetricName": "IO_Write_BW"
     },
     {
-        "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
-        "MetricExpr": "100 * cpu@ASSISTS.ANY\\,umask\\=0x1B@ / SLOTS",
-        "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
-        "MetricName": "tma_assists",
-        "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Socket actual clocks when any core is active on that socket",
+        "MetricExpr": "uncore_cha_0@event\\=0x1@",
+        "MetricGroup": "SoC",
+        "MetricName": "Socket_CLKS"
     },
     {
-        "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults",
-        "MetricExpr": "99 * ASSISTS.PAGE_FAULT / SLOTS",
-        "MetricGroup": "TopdownL5;tma_assists_group",
-        "MetricName": "tma_page_faults",
-        "PublicDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
+        "MetricGroup": "Branches;OS",
+        "MetricName": "IpFarBranch"
     },
     {
-        "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists",
-        "MetricExpr": "30 * ASSISTS.FP / SLOTS",
-        "MetricGroup": "HPC;TopdownL5;tma_assists_group",
-        "MetricName": "tma_fp_assists",
-        "PublicDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called denormals).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Uncore frequency per die [GHZ]",
+        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+        "MetricGroup": "SoC",
+        "MetricName": "UNCORE_FREQ"
     },
     {
-        "BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists. ",
-        "MetricExpr": "63 * ASSISTS.SSE_AVX_MIX / SLOTS",
-        "MetricGroup": "HPC;TopdownL5;tma_assists_group",
-        "MetricName": "tma_avx_assists",
+        "BriefDescription": "Percentage of time spent in the active CPU power state C0",
+        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+        "MetricName": "cpu_utilization",
         "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
-        "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
-        "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
-        "MetricName": "tma_cisc",
-        "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources. Sample with: FRONTEND_RETIRED.MS_FLOWS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "CPU operating frequency (in GHz)",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / duration_time",
+        "MetricName": "cpu_operating_frequency",
+        "ScaleUnit": "1GHz"
     },
     {
-        "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
-        "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
-        "MetricGroup": "Bad;BadSpec;BrMispredicts",
-        "MetricName": "Mispredictions"
+        "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY",
+        "MetricName": "cpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) ",
-        "MetricGroup": "Mem;MemoryBW;Offcore",
-        "MetricName": "Memory_Bandwidth"
+        "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
+        "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
+        "MetricName": "loads_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + (tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)))",
-        "MetricGroup": "Mem;MemoryLat;Offcore",
-        "MetricName": "Memory_Latency"
+        "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
+        "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY",
+        "MetricName": "stores_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) ",
-        "MetricGroup": "Mem;MemoryTLB;Offcore",
-        "MetricName": "Memory_Data_TLBs"
+        "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
+        "MetricName": "l1d_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)",
-        "MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)",
-        "MetricGroup": "Ret",
-        "MetricName": "Branching_Overhead"
+        "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ",
+        "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY",
+        "MetricName": "l1d_demand_data_read_hits_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)",
-        "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)",
-        "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB",
-        "MetricName": "Big_Code"
+        "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
+        "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
+        "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks",
-        "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code",
-        "MetricGroup": "Fed;FetchBW;Frontend",
-        "MetricName": "Instruction_Fetch_BW"
+        "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ",
+        "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY",
+        "MetricName": "l2_demand_data_read_hits_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
-        "MetricExpr": "INST_RETIRED.ANY / CLKS",
-        "MetricGroup": "Ret;Summary",
-        "MetricName": "IPC"
+        "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
+        "MetricName": "l2_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Uops Per Instruction",
-        "MetricExpr": "(tma_retiring * SLOTS) / INST_RETIRED.ANY",
-        "MetricGroup": "Pipeline;Ret;Retire",
-        "MetricName": "UPI"
+        "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
+        "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+        "MetricName": "l2_demand_data_read_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instruction per taken branch",
-        "MetricExpr": "(tma_retiring * SLOTS) / BR_INST_RETIRED.NEAR_TAKEN",
-        "MetricGroup": "Branches;Fed;FetchBW",
-        "MetricName": "UpTB"
+        "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
+        "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
+        "MetricName": "l2_demand_code_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
-        "MetricExpr": "1 / IPC",
-        "MetricGroup": "Mem;Pipeline",
-        "MetricName": "CPI"
+        "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA + UNC_CHA_TOR_INSERTS.IA_MISS_DRD + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF) / INST_RETIRED.ANY",
+        "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
-        "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
-        "MetricGroup": "Pipeline",
-        "MetricName": "CLKS"
+        "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD / INST_RETIRED.ANY",
+        "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
-        "MetricExpr": "TOPDOWN.SLOTS",
-        "MetricGroup": "tma_L1_group",
-        "MetricName": "SLOTS"
+        "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds",
+        "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD) * #num_packages)) * duration_time",
+        "MetricName": "llc_demand_data_read_miss_latency",
+        "ScaleUnit": "1ns"
     },
     {
-        "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
-        "MetricExpr": "SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1",
-        "MetricGroup": "SMT;tma_L1_group",
-        "MetricName": "Slots_Utilization"
+        "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds",
+        "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL) * #num_packages)) * duration_time",
+        "MetricName": "llc_demand_data_read_miss_latency_for_local_requests",
+        "ScaleUnit": "1ns"
     },
     {
-        "BriefDescription": "The ratio of Executed- by Issued-Uops",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
-        "MetricGroup": "Cor;Pipeline",
-        "MetricName": "Execute_per_Issue",
-        "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
+        "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds",
+        "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE) * #num_packages)) * duration_time",
+        "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests",
+        "ScaleUnit": "1ns"
     },
     {
-        "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
-        "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
-        "MetricGroup": "Ret;SMT;tma_L1_group",
-        "MetricName": "CoreIPC"
+        "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to Intel(R) Optane(TM) Persistent Memory(PMEM) in nano seconds",
+        "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM) * #num_packages)) * duration_time",
+        "MetricName": "llc_demand_data_read_miss_to_pmem_latency",
+        "ScaleUnit": "1ns"
     },
     {
-        "BriefDescription": "Floating Point Operations Per Cycle",
-        "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR_HALF) + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF + 4 * AMX_OPS_RETIRED.BF16) / CORE_CLKS",
-        "MetricGroup": "Flops;Ret",
-        "MetricName": "FLOPc"
+        "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds",
+        "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR) * #num_packages)) * duration_time",
+        "MetricName": "llc_demand_data_read_miss_to_dram_latency",
+        "ScaleUnit": "1ns"
     },
     {
-        "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
-        "MetricExpr": "(FP_ARITH_DISPATCHED.PORT_0 + FP_ARITH_DISPATCHED.PORT_1 + FP_ARITH_DISPATCHED.PORT_5) / (2 * CORE_CLKS)",
-        "MetricGroup": "Cor;Flops;HPC",
-        "MetricName": "FP_Arith_Utilization",
-        "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
+        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions",
+        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+        "MetricName": "itlb_2nd_level_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / ((UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
-        "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
-        "MetricName": "ILP"
+        "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions",
+        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+        "MetricName": "itlb_2nd_level_large_page_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
-        "MetricExpr": "(1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0",
-        "MetricGroup": "Cor;SMT",
-        "MetricName": "Core_Bound_Likely"
+        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions",
+        "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+        "MetricName": "dtlb_2nd_level_load_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
-        "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED",
-        "MetricGroup": "SMT",
-        "MetricName": "CORE_CLKS"
+        "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions",
+        "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+        "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS",
-        "MetricGroup": "InsType",
-        "MetricName": "IpLoad"
+        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions",
+        "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+        "MetricName": "dtlb_2nd_level_store_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES",
-        "MetricGroup": "InsType",
-        "MetricName": "IpStore"
+        "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+        "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE)",
+        "MetricName": "numa_reads_addressed_to_local_dram",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Branches;Fed;InsType",
-        "MetricName": "IpBranch"
+        "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+        "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE)",
+        "MetricName": "numa_reads_addressed_to_remote_dram",
+        "ScaleUnit": "100%"
+    },
+    {
+        "BriefDescription": "Uncore operating frequency in GHz",
+        "MetricExpr": "UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages) / 1e9 / duration_time",
+        "MetricName": "uncore_frequency",
+        "ScaleUnit": "1GHz"
     },
     {
-        "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
-        "MetricGroup": "Branches;Fed;PGO",
-        "MetricName": "IpCall"
+        "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)",
+        "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 7.111111111111111 / 1e6 / duration_time",
+        "MetricName": "upi_data_transmit_bw",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instruction per taken branch",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
-        "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
-        "MetricName": "IpTB"
+        "BriefDescription": "DDR memory read bandwidth (MB/sec)",
+        "MetricExpr": "UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time",
+        "MetricName": "memory_bandwidth_read",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Branch instructions per taken branch. ",
-        "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
-        "MetricGroup": "Branches;Fed;PGO",
-        "MetricName": "BpTkBranch"
+        "BriefDescription": "DDR memory write bandwidth (MB/sec)",
+        "MetricExpr": "UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time",
+        "MetricName": "memory_bandwidth_write",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR_HALF) + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF + 4 * AMX_OPS_RETIRED.BF16)",
-        "MetricGroup": "Flops;InsType",
-        "MetricName": "IpFLOP"
+        "BriefDescription": "DDR memory bandwidth (MB/sec)",
+        "MetricExpr": "(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time",
+        "MetricName": "memory_bandwidth_total",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.VECTOR))",
-        "MetricGroup": "Flops;InsType",
-        "MetricName": "IpArith",
-        "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
+        "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)",
+        "MetricExpr": "UNC_M_PMM_RPQ_INSERTS * 64 / 1e6 / duration_time",
+        "MetricName": "pmem_memory_bandwidth_read",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
-        "MetricGroup": "Flops;FpScalar;InsType",
-        "MetricName": "IpArith_Scalar_SP",
-        "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)",
+        "MetricExpr": "UNC_M_PMM_WPQ_INSERTS * 64 / 1e6 / duration_time",
+        "MetricName": "pmem_memory_bandwidth_write",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
-        "MetricGroup": "Flops;FpScalar;InsType",
-        "MetricName": "IpArith_Scalar_DP",
-        "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)",
+        "MetricExpr": "(UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS) * 64 / 1e6 / duration_time",
+        "MetricName": "pmem_memory_bandwidth_total",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF)",
-        "MetricGroup": "Flops;FpVector;InsType",
-        "MetricName": "IpArith_AVX128",
-        "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
+        "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e6 / duration_time",
+        "MetricName": "io_bandwidth_disk_or_network_writes",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF)",
-        "MetricGroup": "Flops;FpVector;InsType",
-        "MetricName": "IpArith_AVX256",
-        "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
+        "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR) * 64 / 1e6 / duration_time",
+        "MetricName": "io_bandwidth_disk_or_network_reads",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF)",
-        "MetricGroup": "Flops;FpVector;InsType",
-        "MetricName": "IpArith_AVX512",
-        "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
+        "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+        "MetricName": "percent_uops_delivered_from_decoded_icache",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic AMX operation (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / AMX_OPS_RETIRED.BF16",
-        "MetricGroup": "Flops;FpVector;InsType;Server",
-        "MetricName": "IpArith_AMX_F16",
-        "PublicDescription": "Instructions per FP Arithmetic AMX operation (lower number means higher occurrence rate). Operations factored per matrices' sizes of the AMX instructions."
+        "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
+        "MetricExpr": "IDQ.MITE_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+        "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions per Integer Arithmetic AMX operation (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / AMX_OPS_RETIRED.INT8",
-        "MetricGroup": "InsType;IntVector;Server",
-        "MetricName": "IpArith_AMX_Int8",
-        "PublicDescription": "Instructions per Integer Arithmetic AMX operation (lower number means higher occurrence rate). Operations factored per matrices' sizes of the AMX instructions."
+        "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
+        "MetricExpr": "IDQ.MS_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+        "MetricName": "percent_uops_delivered_from_microcode_sequencer",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@",
-        "MetricGroup": "Prefetches",
-        "MetricName": "IpSWPF"
+        "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.",
+        "MetricExpr": "UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1e6 / duration_time",
+        "MetricName": "llc_miss_local_memory_bandwidth_read",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
-        "MetricExpr": "INST_RETIRED.ANY",
-        "MetricGroup": "Summary;tma_L1_group",
-        "MetricName": "Instructions"
+        "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.",
+        "MetricExpr": "UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1e6 / duration_time",
+        "MetricName": "llc_miss_local_memory_bandwidth_write",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
-        "MetricExpr": "(tma_retiring * SLOTS) / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
-        "MetricGroup": "Pipeline;Ret",
-        "MetricName": "Retire"
+        "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.",
+        "MetricExpr": "UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1e6 / duration_time",
+        "MetricName": "llc_miss_remote_memory_bandwidth_read",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions",
-        "MetricExpr": "INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
-        "MetricGroup": "Pipeline;Ret",
-        "MetricName": "Strings_Cycles"
+        "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.",
+        "MetricExpr": "UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1e6 / duration_time",
+        "MetricName": "llc_miss_remote_memory_bandwidth_write",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / cpu@ASSISTS.ANY\\,umask\\=0x1B@",
-        "MetricGroup": "Pipeline;Ret;Retire",
-        "MetricName": "IpAssist"
+        "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
+        "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / slots",
+        "MetricGroup": "PGO;TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_frontend_bound",
+        "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
-        "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
-        "MetricName": "Execute"
+        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
+        "MetricExpr": "topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / slots",
+        "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+        "MetricName": "tma_fetch_latency",
+        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average number of Uops issued by front-end when it issued something",
-        "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@",
-        "MetricGroup": "Fed;FetchBW",
-        "MetricName": "Fetch_UpC"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.",
+        "MetricExpr": "ICACHE_DATA.STALLS / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_icache_misses",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
-        "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
-        "MetricGroup": "DSB;Fed;FetchBW",
-        "MetricName": "DSB_Coverage"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.",
+        "MetricExpr": "ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_itlb_misses",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
-        "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@",
-        "MetricGroup": "DSBmiss",
-        "MetricName": "DSB_Switch_Cost"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
+        "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + tma_unknown_branches",
+        "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_branch_resteers",
+        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
-        "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))",
-        "MetricGroup": "DSBmiss;Fed",
-        "MetricName": "DSB_Misses"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ",
+        "MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) / max(1 - (tma_frontend_bound + topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)), 0) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+        "MetricName": "tma_mispredicts_resteers",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS",
-        "MetricGroup": "DSBmiss;Fed",
-        "MetricName": "IpDSB_Miss_Ret"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ",
+        "MetricExpr": "(1 - topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) / max(1 - (tma_frontend_bound + topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)), 0)) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+        "MetricName": "tma_clears_resteers",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;BadSpec;BrMispredicts",
-        "MetricName": "IpMispredict"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
+        "MetricExpr": "INT_MISC.UNKNOWN_BRANCH_CYCLES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+        "MetricName": "tma_unknown_branches",
+        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
-        "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;BrMispredicts",
-        "MetricName": "Branch_Misprediction_Cost"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
+        "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_dsb_switches",
+        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of branches that are non-taken conditionals",
-        "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;Branches;CodeGen;PGO",
-        "MetricName": "Cond_NT"
+        "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
+        "MetricExpr": "DECODE.LCP / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_lcp",
+        "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of branches that are taken conditionals",
-        "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;Branches;CodeGen;PGO",
-        "MetricName": "Cond_TK"
+        "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
+        "MetricExpr": "3 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_ms_switches",
+        "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of branches that are CALL or RET",
-        "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;Branches",
-        "MetricName": "CallRet"
+        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
+        "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
+        "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+        "MetricName": "tma_fetch_bandwidth",
+        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues.  For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps",
-        "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;Branches",
-        "MetricName": "Jump"
+        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
+        "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / CPU_CLK_UNHALTED.DISTRIBUTED / 2",
+        "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+        "MetricName": "tma_mite",
+        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)",
-        "MetricExpr": "1 - (Cond_NT + Cond_TK + CallRet + Jump)",
-        "MetricGroup": "Bad;Branches",
-        "MetricName": "Other_Branches"
+        "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder",
+        "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=0x1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=0x2@) / CPU_CLK_UNHALTED.DISTRIBUTED",
+        "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group",
+        "MetricName": "tma_decoder0_alone",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
-        "MetricExpr": "L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY",
-        "MetricGroup": "Mem;MemoryBound;MemoryLat",
-        "MetricName": "Load_Miss_Real_Latency"
+        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
+        "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / CPU_CLK_UNHALTED.DISTRIBUTED / 2",
+        "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+        "MetricName": "tma_dsb",
+        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline.  For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
-        "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
-        "MetricGroup": "Mem;MemoryBW;MemoryBound",
-        "MetricName": "MLP"
+        "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
+        "MetricExpr": "max(1 - (tma_frontend_bound + topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)), 0)",
+        "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_bad_speculation",
+        "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L1MPKI"
+        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
+        "MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * slots",
+        "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+        "MetricName": "tma_branch_mispredicts",
+        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L1MPKI_Load"
+        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
+        "MetricExpr": "max(0, tma_bad_speculation - topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound))",
+        "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+        "MetricName": "tma_machine_clears",
+        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears.  These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "Backend;CacheMisses;Mem",
-        "MetricName": "L2MPKI"
+        "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
+        "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * slots",
+        "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_backend_bound",
+        "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem;Offcore",
-        "MetricName": "L2MPKI_All"
+        "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
+        "MetricExpr": "topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * slots",
+        "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+        "MetricName": "tma_memory_bound",
+        "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L2MPKI_Load"
+        "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
+        "MetricExpr": "max((EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS) / CPU_CLK_UNHALTED.THREAD, 0)",
+        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_l1_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache.  The L1 data cache typically has the shortest latency.  However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
-        "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L2HPKI_All"
+        "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
+        "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS, 0)) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_dtlb_load",
+        "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache hits per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L2HPKI_Load"
+        "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
+        "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
+        "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group",
+        "MetricName": "tma_load_stlb_hit",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L3MPKI"
+        "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk",
+        "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group",
+        "MetricName": "tma_load_stlb_miss",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "FB_HPKI"
+        "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
+        "MetricExpr": "min(13 * LD_BLOCKS.STORE_FORWARD / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_store_fwd_blk",
+        "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
-        "MetricConstraint": "NO_NMI_WATCHDOG",
-        "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (4 * CORE_CLKS)",
-        "MetricGroup": "Mem;MemoryTLB",
-        "MetricName": "Page_Walks_Utilization"
+        "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
+        "MetricExpr": "min((16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_lock_latency",
+        "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
-        "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L1D_Cache_Fill_BW"
+        "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ",
+        "MetricExpr": "min(Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_split_loads",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
-        "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L2_Cache_Fill_BW"
+        "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
+        "MetricExpr": "L1D_PEND_MISS.FB_FULL / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_fb_full",
+        "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L3_Cache_Fill_BW"
+        "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
+        "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_l2_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time",
-        "MetricGroup": "Mem;MemoryBW;Offcore",
-        "MetricName": "L3_Cache_Access_BW"
+        "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
+        "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_l3_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
-        "MetricExpr": "1000 * L2_LINES_OUT.SILENT / Instructions",
-        "MetricGroup": "L2Evicts;Mem;Server",
-        "MetricName": "L2_Evictions_Silent_PKI"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
+        "MetricExpr": "min(((28 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + (27 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_contested_accesses",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
-        "MetricExpr": "1000 * L2_LINES_OUT.NON_SILENT / Instructions",
-        "MetricGroup": "L2Evicts;Mem;Server",
-        "MetricName": "L2_Evictions_NonSilent_PKI"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
+        "MetricExpr": "min((27 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_data_sharing",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
-        "MetricExpr": "L1D_Cache_Fill_BW",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L1D_Cache_Fill_BW_1T"
+        "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
+        "MetricExpr": "min((12 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_l3_hit_latency",
+        "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
-        "MetricExpr": "L2_Cache_Fill_BW",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L2_Cache_Fill_BW_1T"
+        "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
+        "MetricExpr": "(XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_sq_full",
+        "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "L3_Cache_Fill_BW",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L3_Cache_Fill_BW_1T"
+        "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
+        "MetricExpr": "min(MEMORY_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD - tma_pmm_bound, 1)",
+        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_dram_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "L3_Cache_Access_BW",
-        "MetricGroup": "Mem;MemoryBW;Offcore",
-        "MetricName": "L3_Cache_Access_BW_1T"
+        "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
+        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+        "MetricName": "tma_mem_bandwidth",
+        "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM).  The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average CPU Utilization",
-        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
-        "MetricGroup": "HPC;Summary",
-        "MetricName": "CPU_Utilization"
+        "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to memory bandwidth Allocation feature (RDT's memory bandwidth throttling).",
+        "MetricExpr": "INT_MISC.MBA_STALLS / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryBW;Offcore;Server;TopdownL5;tma_L5_group;tma_mem_bandwidth_group",
+        "MetricName": "tma_mba_stalls",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
-        "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
-        "MetricGroup": "Power;Summary",
-        "MetricName": "Average_Frequency"
+        "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
+        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CPU_CLK_UNHALTED.THREAD - tma_mem_bandwidth",
+        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+        "MetricName": "tma_mem_latency",
+        "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM).  This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Giga Floating Point Operations Per Second",
-        "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR_HALF) + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF + 4 * AMX_OPS_RETIRED.BF16) / 1000000000) / duration_time",
-        "MetricGroup": "Cor;Flops;HPC",
-        "MetricName": "GFLOPs",
-        "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
+        "MetricExpr": "min((66.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 12 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group",
+        "MetricName": "tma_local_dram",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Tera Integer (matrix) Operations Per Second",
-        "MetricExpr": "(8 * AMX_OPS_RETIRED.INT8 / 1e12) / duration_time",
-        "MetricGroup": "Cor;HPC;IntVector;Server",
-        "MetricName": "TIOPS"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
+        "MetricExpr": "min((131 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 12 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+        "MetricName": "tma_remote_dram",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average Frequency Utilization relative nominal frequency",
-        "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
-        "MetricGroup": "Power",
-        "MetricName": "Turbo_Utilization"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
+        "MetricExpr": "min(((120 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 12 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + (120 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 12 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+        "MetricName": "tma_remote_cache",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
-        "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0",
-        "MetricGroup": "SMT",
-        "MetricName": "SMT_2T_Utilization"
+        "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a",
+        "MetricExpr": "min(((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (MEMORY_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0), 1)",
+        "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_pmm_bound",
+        "PublicDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
-        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
-        "MetricGroup": "OS",
-        "MetricName": "Kernel_Utilization"
+        "BriefDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
+        "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_store_bound",
+        "PublicDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
-        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
-        "MetricGroup": "OS",
-        "MetricName": "Kernel_CPI"
+        "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
+        "MetricExpr": "(MEM_STORE_RETIRED.L2_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_store_latency",
+        "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
-        "MetricExpr": "(64 * (uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@) / 1000000000) / duration_time",
-        "MetricGroup": "HPC;Mem;MemoryBW;SoC",
-        "MetricName": "DRAM_BW_Use"
+        "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
+        "MetricExpr": "min(28 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_false_sharing",
+        "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
-        "MetricExpr": "1000000000 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (Socket_CLKS / duration_time)",
-        "MetricGroup": "Mem;MemoryLat;SoC",
-        "MetricName": "MEM_Read_Latency"
+        "BriefDescription": "This metric represents rate of split store accesses",
+        "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CPU_CLK_UNHALTED.DISTRIBUTED",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_split_stores",
+        "PublicDescription": "This metric represents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granularity.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
-        "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / cha@UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD\\,thresh\\=1@",
-        "MetricGroup": "Mem;MemoryBW;SoC",
-        "MetricName": "MEM_Parallel_Reads"
+        "BriefDescription": "This metric estimates how often CPU was stalled  due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores",
+        "MetricExpr": "min(9 * OCR.STREAMING_WR.ANY_RESPONSE / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_streaming_stores",
+        "PublicDescription": "This metric estimates how often CPU was stalled  due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
-        "MetricExpr": "(1000000000 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / uncore_cha_0@event\\=0x1@)",
-        "MetricGroup": "Mem;MemoryLat;Server;SoC",
-        "MetricName": "MEM_PMM_Read_Latency"
+        "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
+        "MetricExpr": "min((7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CPU_CLK_UNHALTED.DISTRIBUTED, 1)",
+        "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_dtlb_store",
+        "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead.  Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page.  Try using larger page sizes for large amounts of frequently-used data.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
-        "MetricExpr": " 1000000000 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / uncore_cha_0@event\\=0x1@",
-        "MetricGroup": "Mem;MemoryLat;Server;SoC",
-        "MetricName": "MEM_DRAM_Read_Latency"
+        "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
+        "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
+        "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group",
+        "MetricName": "tma_store_stlb_hit",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]",
-        "MetricExpr": "((64 * UNC_M_PMM_RPQ_INSERTS / 1000000000) / duration_time)",
-        "MetricGroup": "Mem;MemoryBW;Server;SoC",
-        "MetricName": "PMM_Read_BW"
+        "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk",
+        "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CPU_CLK_UNHALTED.DISTRIBUTED",
+        "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group",
+        "MetricName": "tma_store_stlb_miss",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]",
-        "MetricExpr": "((64 * UNC_M_PMM_WPQ_INSERTS / 1000000000) / duration_time)",
-        "MetricGroup": "Mem;MemoryBW;Server;SoC",
-        "MetricName": "PMM_Write_BW"
+        "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
+        "MetricExpr": "max(0, topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) + 0 * slots",
+        "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+        "MetricName": "tma_core_bound",
+        "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]",
-        "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1000000000 / duration_time",
-        "MetricGroup": "IoBW;Mem;Server;SoC",
-        "MetricName": "IO_Write_BW"
+        "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
+        "MetricExpr": "ARITH.DIVIDER_ACTIVE / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group",
+        "MetricName": "tma_divider",
+        "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Socket actual clocks when any core is active on that socket",
-        "MetricExpr": "uncore_cha_0@event\\=0x1@",
-        "MetricGroup": "SoC",
-        "MetricName": "Socket_CLKS"
+        "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
+        "MetricExpr": "((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS else (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@) / CPU_CLK_UNHALTED.THREAD) + 0 * slots",
+        "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group",
+        "MetricName": "tma_ports_utilization",
+        "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
-        "MetricGroup": "Branches;OS",
-        "MetricName": "IpFarBranch"
+        "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+        "MetricExpr": "cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / CPU_CLK_UNHALTED.THREAD + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_0",
+        "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C1 residency percent per core",
-        "MetricExpr": "(cstate_core@c1\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C1_Core_Residency"
+        "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations",
+        "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group",
+        "MetricName": "tma_serializing_operation",
+        "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C6 residency percent per core",
-        "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C6_Core_Residency"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.",
+        "MetricExpr": "CPU_CLK_UNHALTED.PAUSE / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group",
+        "MetricName": "tma_slow_pause",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C2 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C2_Pkg_Residency"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions.",
+        "MetricExpr": "min(13 * MISC2_RETIRED.LFENCE / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group",
+        "MetricName": "tma_memory_fence",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C6 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C6_Pkg_Residency"
+        "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued",
+        "MetricExpr": "min(160 * ASSISTS.SSE_AVX_MIX / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group",
+        "MetricName": "tma_mixing_vectors",
+        "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uncore frequency per die [GHZ]",
-        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000",
-        "MetricGroup": "SoC",
-        "MetricName": "UNCORE_FREQ"
+        "BriefDescription": "This metric estimates fraction of cycles where the Advanced Matrix Extensions (AMX) execution engine was busy with tile (arithmetic) operations",
+        "MetricExpr": "EXE.AMX_BUSY / CPU_CLK_UNHALTED.DISTRIBUTED",
+        "MetricGroup": "Compute;HPC;Server;TopdownL5;tma_L5_group;tma_ports_utilized_0_group",
+        "MetricName": "tma_amx_busy",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "CPU operating frequency (in GHz)",
-        "MetricExpr": "(( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ ) / 1000000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "cpu_operating_frequency",
-        "ScaleUnit": "1GHz"
+        "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+        "MetricExpr": "EXE_ACTIVITY.1_PORTS_UTIL / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_1",
+        "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
-        "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "loads_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+        "MetricExpr": "EXE_ACTIVITY.2_PORTS_UTIL / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_2",
+        "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
-        "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "stores_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
+        "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_3m",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l1d_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
+        "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5_11 + UOPS_DISPATCHED.PORT_6) / (5 * CPU_CLK_UNHALTED.DISTRIBUTED)",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+        "MetricName": "tma_alu_op_utilization",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ",
-        "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l1d_demand_data_read_hits_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)",
+        "MetricExpr": "UOPS_DISPATCHED.PORT_0 / CPU_CLK_UNHALTED.DISTRIBUTED",
+        "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+        "MetricName": "tma_port_0",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
-        "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)",
+        "MetricExpr": "UOPS_DISPATCHED.PORT_1 / CPU_CLK_UNHALTED.DISTRIBUTED",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+        "MetricName": "tma_port_1",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ",
-        "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_demand_data_read_hits_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)",
+        "MetricExpr": "UOPS_DISPATCHED.PORT_6 / CPU_CLK_UNHALTED.DISTRIBUTED",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+        "MetricName": "tma_port_6",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations",
+        "MetricExpr": "UOPS_DISPATCHED.PORT_2_3_10 / (3 * CPU_CLK_UNHALTED.DISTRIBUTED)",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+        "MetricName": "tma_load_op_utilization",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
-        "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_demand_data_read_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
+        "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * CPU_CLK_UNHALTED.DISTRIBUTED)",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+        "MetricName": "tma_store_op_utilization",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
-        "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_demand_code_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
+        "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * slots",
+        "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_retiring",
+        "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "( UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA + UNC_CHA_TOR_INSERTS.IA_MISS_DRD + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF ) / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
+        "MetricExpr": "max(0, topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) + 0 * slots",
+        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+        "MetricName": "tma_light_operations",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
+        "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD + tma_fp_scalar + tma_fp_vector + tma_fp_amx",
+        "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_fp_arith",
+        "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds",
-        "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD) * #num_packages ) ) ) * duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_demand_data_read_miss_latency",
-        "ScaleUnit": "1ns"
+        "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
+        "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD + 0 * slots",
+        "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group",
+        "MetricName": "tma_x87_use",
+        "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds",
-        "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL) * #num_packages ) ) ) * duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_demand_data_read_miss_latency_for_local_requests",
-        "ScaleUnit": "1ns"
+        "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+        "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group",
+        "MetricName": "tma_fp_scalar",
+        "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds",
-        "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE) * #num_packages ) ) ) * duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests",
-        "ScaleUnit": "1ns"
+        "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
+        "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.VECTOR) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)",
+        "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group",
+        "MetricName": "tma_fp_vector",
+        "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to Intel(R) Optane(TM) Persistent Memory(PMEM) in nano seconds",
-        "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM) * #num_packages ) ) ) * duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_demand_data_read_miss_to_pmem_latency",
-        "ScaleUnit": "1ns"
+        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
+        "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)",
+        "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+        "MetricName": "tma_fp_vector_128b",
+        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds",
-        "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR) * #num_packages ) ) ) * duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_demand_data_read_miss_to_dram_latency",
-        "ScaleUnit": "1ns"
+        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
+        "MetricExpr": "min((FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)",
+        "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+        "MetricName": "tma_fp_vector_256b",
+        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
-        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "itlb_2nd_level_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
+        "MetricExpr": "min((FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)",
+        "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+        "MetricName": "tma_fp_vector_512b",
+        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
-        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "itlb_2nd_level_large_page_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric approximates arithmetic floating-point (FP) matrix uops fraction the CPU has retired (aggregated across all supported FP datatypes in AMX engine)",
+        "MetricExpr": "cpu@AMX_OPS_RETIRED.BF16\\,cmask\\=0x1@ / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+        "MetricGroup": "Compute;Flops;HPC;Pipeline;Server;TopdownL4;tma_L4_group;tma_fp_arith_group",
+        "MetricName": "tma_fp_amx",
+        "PublicDescription": "This metric approximates arithmetic floating-point (FP) matrix uops fraction the CPU has retired (aggregated across all supported FP datatypes in AMX engine). Refer to AMX_Busy and GFLOPs metrics for actual AMX utilization and FP performance, resp.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
-        "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "dtlb_2nd_level_load_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired)",
+        "MetricExpr": "tma_int_vector_128b + tma_int_vector_256b + tma_shuffles",
+        "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_int_operations",
+        "PublicDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired). Vector/Matrix Int operations and shuffles are counted. Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.",
-        "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.",
+        "MetricExpr": "(INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+        "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group",
+        "MetricName": "tma_int_vector_128b",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
-        "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "dtlb_2nd_level_store_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.",
+        "MetricExpr": "(INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+        "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group",
+        "MetricName": "tma_int_vector_256b",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
-        "MetricExpr": "100 * ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL ) / ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE )",
-        "MetricGroup": "",
-        "MetricName": "numa_reads_addressed_to_local_dram",
-        "ScaleUnit": "1%"
+        "BriefDescription": "This metric approximates arithmetic Integer (Int) matrix uops fraction the CPU has retired (aggregated across all supported Int datatypes in AMX engine)",
+        "MetricExpr": "cpu@AMX_OPS_RETIRED.INT8\\,cmask\\=0x1@ / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+        "MetricGroup": "Compute;HPC;IntVector;Pipeline;Server;TopdownL4;tma_L4_group;tma_int_operations_group",
+        "MetricName": "tma_int_amx",
+        "PublicDescription": "This metric approximates arithmetic Integer (Int) matrix uops fraction the CPU has retired (aggregated across all supported Int datatypes in AMX engine). Refer to AMX_Busy and TIOPs metrics for actual AMX utilization and Int performance, resp.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
-        "MetricExpr": "100 * ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE ) / ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE )",
-        "MetricGroup": "",
-        "MetricName": "numa_reads_addressed_to_remote_dram",
-        "ScaleUnit": "1%"
+        "BriefDescription": "This metric represents Shuffle (cross \"vector lane\" data transfers) uops fraction the CPU has retired.",
+        "MetricExpr": "INT_VEC_RETIRED.SHUFFLES / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+        "MetricGroup": "HPC;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group",
+        "MetricName": "tma_shuffles",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uncore operating frequency in GHz",
-        "MetricExpr": "( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_CLOCKTICKS) * #num_packages ) / 1000000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "uncore_frequency",
-        "ScaleUnit": "1GHz"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.",
+        "MetricExpr": "max(0, topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) * MEM_UOP_RETIRED.ANY / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+        "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_memory_operations",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_UPI_TxL_FLITS.ALL_DATA * (64 / 9.0) / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "upi_data_transmit_bw",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions",
+        "MetricExpr": "max(0, topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) * INST_RETIRED.MACRO_FUSED / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+        "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_fused_instructions",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "DDR memory read bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "memory_bandwidth_read",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused",
+        "MetricExpr": "max(0, topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) * (BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+        "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_non_fused_branches",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "DDR memory write bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "memory_bandwidth_write",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions",
+        "MetricExpr": "max(0, topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) * INST_RETIRED.NOP / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+        "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_nop_instructions",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "DDR memory bandwidth (MB/sec)",
-        "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "memory_bandwidth_total",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting",
+        "MetricExpr": "max(0, max(0, topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) - (tma_fp_arith + tma_int_operations + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions))",
+        "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_other_light_ops",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_M_PMM_RPQ_INSERTS * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "pmem_memory_bandwidth_read",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
+        "MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * slots",
+        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+        "MetricName": "tma_heavy_operations",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_M_PMM_WPQ_INSERTS * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "pmem_memory_bandwidth_write",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops",
+        "MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - tma_microcode_sequencer",
+        "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group",
+        "MetricName": "tma_few_uops_instructions",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)",
-        "MetricExpr": "(( UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS ) * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "pmem_memory_bandwidth_total",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
+        "MetricExpr": "UOPS_RETIRED.MS / slots",
+        "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group",
+        "MetricName": "tma_microcode_sequencer",
+        "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
-        "MetricExpr": "( UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "io_bandwidth_disk_or_network_writes",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
+        "MetricExpr": "min(100 * cpu@ASSISTS.ANY\\,umask\\=0x1B@ / slots, 1)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+        "MetricName": "tma_assists",
+        "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
-        "MetricExpr": "(( UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR ) * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "io_bandwidth_disk_or_network_reads",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults",
+        "MetricExpr": "99 * ASSISTS.PAGE_FAULT / slots",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_assists_group",
+        "MetricName": "tma_page_faults",
+        "PublicDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
-        "MetricExpr": "100 * ( IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )",
-        "MetricGroup": "",
-        "MetricName": "percent_uops_delivered_from_decoded_icache",
-        "ScaleUnit": "1%"
+        "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists",
+        "MetricExpr": "30 * ASSISTS.FP / slots",
+        "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group",
+        "MetricName": "tma_fp_assists",
+        "PublicDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called denormals).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
-        "MetricExpr": "100 * ( IDQ.MITE_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )",
-        "MetricGroup": "",
-        "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
-        "ScaleUnit": "1%"
+        "BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists. ",
+        "MetricExpr": "63 * ASSISTS.SSE_AVX_MIX / slots",
+        "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group",
+        "MetricName": "tma_avx_assists",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
-        "MetricExpr": "100 * ( IDQ.MS_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )",
-        "MetricGroup": "",
-        "MetricName": "percent_uops_delivered_from_microcode_sequencer",
-        "ScaleUnit": "1%"
+        "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
+        "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+        "MetricName": "tma_cisc",
+        "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.",
-        "MetricExpr": "( UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_miss_local_memory_bandwidth_read",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "C1 residency percent per core",
+        "MetricExpr": "cstate_core@c1\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C1_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.",
-        "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_miss_local_memory_bandwidth_write",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "C6 residency percent per core",
+        "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C6_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.",
-        "MetricExpr": "( UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_miss_remote_memory_bandwidth_read",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "C2 residency percent per package",
+        "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C2_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.",
-        "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_miss_remote_memory_bandwidth_write",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "C6 residency percent per package",
+        "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C6_Pkg_Residency",
+        "ScaleUnit": "100%"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-memory.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-memory.json
index 41d7cd4958a1b..b77fd0f7ab506 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-memory.json
@@ -1,499 +1,461 @@
 [
     {
-        "BriefDescription": "IMC Clockticks at DCLK frequency",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x01",
-        "EventName": "UNC_M_CLOCKTICKS",
+        "BriefDescription": "Activate due to read, write, underfill, or bypass",
+        "EventCode": "0x02",
+        "EventName": "UNC_M_ACT_COUNT.ALL",
         "PerPkg": "1",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM Activate Count : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+        "UMask": "0xff",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "IMC Clockticks at HCLK frequency",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x01",
-        "EventName": "UNC_M_HCLOCKTICKS",
+        "BriefDescription": "All DRAM CAS commands issued",
+        "EventCode": "0x05",
+        "EventName": "UNC_M_CAS_COUNT.ALL",
         "PerPkg": "1",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : All DRAM Read and Write actions : DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM CAS commands issued on this channel.",
+        "UMask": "0xff",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 0",
         "EventCode": "0x05",
-        "EventName": "UNC_M_CAS_COUNT.RD_REG",
+        "EventName": "UNC_M_CAS_COUNT.PCH0",
         "PerPkg": "1",
-        "UMask": "0x00000000c1",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 0 : DRAM RD_CAS and WR_CAS Commands",
+        "UMask": "0x40",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM underfill read CAS commands issued",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 1",
         "EventCode": "0x05",
-        "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
+        "EventName": "UNC_M_CAS_COUNT.PCH1",
         "PerPkg": "1",
-        "UMask": "0x00000000c4",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 1 : DRAM RD_CAS and WR_CAS Commands",
+        "UMask": "0x80",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "All DRAM read CAS commands issued (including underfills)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x05",
         "EventName": "UNC_M_CAS_COUNT.RD",
         "PerPkg": "1",
-        "UMask": "0x00000000cf",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM Read CAS commands issued on this channel.  This includes underfills.",
+        "UMask": "0xcf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "All DRAM write CAS commands issued",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.",
         "EventCode": "0x05",
-        "EventName": "UNC_M_CAS_COUNT.WR",
+        "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG",
         "PerPkg": "1",
-        "UMask": "0x00000000f0",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands",
+        "UMask": "0xc2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Pending Queue Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_M_RPQ_INSERTS.PCH0",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.",
+        "EventCode": "0x05",
+        "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL",
         "PerPkg": "1",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands",
+        "UMask": "0xc8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Pending Queue Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_M_RPQ_INSERTS.PCH1",
+        "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)",
+        "EventCode": "0x05",
+        "EventName": "UNC_M_CAS_COUNT.RD_REG",
         "PerPkg": "1",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/out auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the total number or DRAM Read CAS commands issued on this channel.  This includes both regular RD CAS commands as well as those with implicit Precharge.   We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
+        "UMask": "0xc1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_M_WPQ_INSERTS.PCH0",
+        "BriefDescription": "DRAM underfill read CAS commands issued",
+        "EventCode": "0x05",
+        "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
         "PerPkg": "1",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : Underfill Read Issued : DRAM RD_CAS and WR_CAS Commands",
+        "UMask": "0xc4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_M_WPQ_INSERTS.PCH1",
+        "BriefDescription": "All DRAM write CAS commands issued",
+        "EventCode": "0x05",
+        "EventName": "UNC_M_CAS_COUNT.WR",
         "PerPkg": "1",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM Write CAS commands issued on this channel.",
+        "UMask": "0xf0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre",
+        "EventCode": "0x05",
+        "EventName": "UNC_M_CAS_COUNT.WR_NONPRE",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands",
+        "UMask": "0xd0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x81",
-        "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.",
+        "EventCode": "0x05",
+        "EventName": "UNC_M_CAS_COUNT.WR_PRE",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands",
+        "UMask": "0xe0",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0",
+        "BriefDescription": "IMC Clockticks at DCLK frequency",
+        "EventCode": "0x01",
+        "EventName": "UNC_M_CLOCKTICKS",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "Number of DRAM DCLK clock cycles while the event is enabled",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1",
+        "BriefDescription": "IMC Clockticks at HCLK frequency",
+        "EventCode": "0x01",
+        "EventName": "UNC_M_HCLOCKTICKS",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "Number of DRAM HCLK clock cycles while the event is enabled",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "PMM Read Pending Queue inserts",
+        "EventCode": "0xe3",
+        "EventName": "UNC_M_PMM_RPQ_INSERTS",
+        "PerPkg": "1",
+        "PublicDescription": "Counts number of read requests allocated in the PMM Read Pending Queue.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "PMM Read Pending Queue occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xe0",
         "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH0",
         "PerPkg": "1",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "PMM Read Pending Queue occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xe0",
         "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH1",
         "PerPkg": "1",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Read Pending Queue inserts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe3",
-        "EventName": "UNC_M_PMM_RPQ_INSERTS",
+        "BriefDescription": "PMM Read Pending Queue Occupancy",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT_SCH0",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Write Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe4",
-        "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL",
+        "BriefDescription": "PMM Read Pending Queue Occupancy",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT_SCH1",
+        "PerPkg": "1",
+        "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
+        "UMask": "0x20",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "PMM Read Pending Queue Occupancy",
+        "EventCode": "0xe0",
+        "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH0",
         "PerPkg": "1",
-        "UMask": "0x03",
+        "PublicDescription": "Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
+        "UMask": "0x4",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "PMM Read Pending Queue Occupancy",
+        "EventCode": "0xe0",
+        "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH1",
+        "PerPkg": "1",
+        "PublicDescription": "Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "PMM Write Pending Queue inserts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xe7",
         "EventName": "UNC_M_PMM_WPQ_INSERTS",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "Counts number of  write requests allocated in the PMM Write Pending Queue.",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "PMM Write Pending Queue Occupancy",
+        "EventCode": "0xe4",
+        "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL",
+        "PerPkg": "1",
+        "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the Write Pending Queue to the PMM DIMM.",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "PMM Write Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xE4",
         "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH0",
         "PerPkg": "1",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "PMM Write Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xE4",
         "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH1",
         "PerPkg": "1",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Activate due to read, write, underfill, or bypass",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_M_ACT_COUNT.ALL",
+        "BriefDescription": "Channel PPD Cycles",
+        "EventCode": "0x85",
+        "EventName": "UNC_M_POWER_CHANNEL_PPD",
         "PerPkg": "1",
-        "UMask": "0x00000000ff",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "Channel PPD Cycles : Number of cycles when all the ranks in the channel are in PPD mode.  If IBT=off is enabled, then this can be used to count those cycles.  If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Precharge due to read on page miss",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_M_PRE_COUNT.RD",
+        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+        "EventCode": "0x47",
+        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0",
         "PerPkg": "1",
-        "UMask": "0x0000000011",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Precharge due to write on page miss",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_M_PRE_COUNT.WR",
+        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+        "EventCode": "0x47",
+        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1",
         "PerPkg": "1",
-        "UMask": "0x0000000022",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge commands. : Precharge due to (?)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_M_PRE_COUNT.PGT",
+        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+        "EventCode": "0x47",
+        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2",
         "PerPkg": "1",
-        "UMask": "0x0000000088",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Precharge due to read, write, underfill, or PGT",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_M_PRE_COUNT.ALL",
+        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+        "EventCode": "0x47",
+        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3",
         "PerPkg": "1",
-        "UMask": "0x00000000ff",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "All DRAM CAS commands issued",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_M_CAS_COUNT.ALL",
+        "BriefDescription": "Clock-Enabled Self-Refresh",
+        "EventCode": "0x43",
+        "EventName": "UNC_M_POWER_SELF_REFRESH",
         "PerPkg": "1",
-        "UMask": "0x00000000ff",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "Clock-Enabled Self-Refresh : Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock.  This happens in some package C-states.  For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing.  One use of this is for Monroe technology.  Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG",
+        "BriefDescription": "Precharge due to read, write, underfill, or PGT.",
+        "EventCode": "0x03",
+        "EventName": "UNC_M_PRE_COUNT.ALL",
         "PerPkg": "1",
-        "UMask": "0x00000000c2",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
+        "UMask": "0xff",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL",
+        "BriefDescription": "DRAM Precharge commands. : Precharge due to (?)",
+        "EventCode": "0x03",
+        "EventName": "UNC_M_PRE_COUNT.PGT",
         "PerPkg": "1",
-        "UMask": "0x00000000c8",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM Precharge commands. : Precharge due to (?) : Counts the number of DRAM Precharge commands sent on this channel.",
+        "UMask": "0x88",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_M_CAS_COUNT.WR_PRE",
+        "BriefDescription": "DRAM Precharge commands. : Prechages from Page Table",
+        "EventCode": "0x03",
+        "EventName": "UNC_M_PRE_COUNT.PGT_PCH0",
         "PerPkg": "1",
-        "UMask": "0x00000000e0",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM Precharge commands. : Prechages from Page Table : Counts the number of DRAM Precharge commands sent on this channel. : Equivalent to PAGE_EMPTY",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Read Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe0",
-        "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH0",
+        "BriefDescription": "DRAM Precharge commands.",
+        "EventCode": "0x03",
+        "EventName": "UNC_M_PRE_COUNT.PGT_PCH1",
         "PerPkg": "1",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
+        "UMask": "0x80",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Read Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe0",
-        "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH1",
+        "BriefDescription": "Precharge due to read on page miss",
+        "EventCode": "0x03",
+        "EventName": "UNC_M_PRE_COUNT.RD",
         "PerPkg": "1",
-        "UMask": "0x0000000008",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
+        "UMask": "0x11",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM Precharge commands. : Precharge due to read",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x03",
         "EventName": "UNC_M_PRE_COUNT.RD_PCH0",
         "PerPkg": "1",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge commands. : Precharge due to write",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "DRAM Precharge commands.",
         "EventCode": "0x03",
-        "EventName": "UNC_M_PRE_COUNT.WR_PCH0",
+        "EventName": "UNC_M_PRE_COUNT.RD_PCH1",
         "PerPkg": "1",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge commands",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "DRAM Precharge commands.",
         "EventCode": "0x03",
-        "EventName": "UNC_M_PRE_COUNT.UFILL_PCH0",
+        "EventName": "UNC_M_PRE_COUNT.UFILL",
         "PerPkg": "1",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
+        "UMask": "0x44",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge commands. : Prechages from Page Table",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "DRAM Precharge commands.",
         "EventCode": "0x03",
-        "EventName": "UNC_M_PRE_COUNT.PGT_PCH0",
+        "EventName": "UNC_M_PRE_COUNT.UFILL_PCH0",
         "PerPkg": "1",
-        "UMask": "0x0000000008",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge commands",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "DRAM Precharge commands.",
         "EventCode": "0x03",
-        "EventName": "UNC_M_PRE_COUNT.RD_PCH1",
+        "EventName": "UNC_M_PRE_COUNT.UFILL_PCH1",
         "PerPkg": "1",
-        "UMask": "0x0000000010",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
+        "UMask": "0x40",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge commands",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Precharge due to write on page miss",
         "EventCode": "0x03",
-        "EventName": "UNC_M_PRE_COUNT.WR_PCH1",
+        "EventName": "UNC_M_PRE_COUNT.WR",
         "PerPkg": "1",
-        "UMask": "0x0000000020",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
+        "UMask": "0x22",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge commands",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "DRAM Precharge commands. : Precharge due to write",
         "EventCode": "0x03",
-        "EventName": "UNC_M_PRE_COUNT.UFILL_PCH1",
+        "EventName": "UNC_M_PRE_COUNT.WR_PCH0",
         "PerPkg": "1",
-        "UMask": "0x0000000040",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge commands",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "DRAM Precharge commands.",
         "EventCode": "0x03",
-        "EventName": "UNC_M_PRE_COUNT.PGT_PCH1",
+        "EventName": "UNC_M_PRE_COUNT.WR_PCH1",
         "PerPkg": "1",
-        "UMask": "0x0000000080",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
+        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge commands",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_M_PRE_COUNT.UFILL",
+        "BriefDescription": "Read Pending Queue Allocations",
+        "EventCode": "0x10",
+        "EventName": "UNC_M_RPQ_INSERTS.PCH0",
         "PerPkg": "1",
-        "UMask": "0x0000000044",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_M_CAS_COUNT.WR_NONPRE",
+        "BriefDescription": "Read Pending Queue Allocations",
+        "EventCode": "0x10",
+        "EventName": "UNC_M_RPQ_INSERTS.PCH1",
         "PerPkg": "1",
-        "UMask": "0x00000000D0",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_M_CAS_COUNT.PCH0",
+        "BriefDescription": "Read Pending Queue Occupancy",
+        "EventCode": "0x80",
+        "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0",
         "PerPkg": "1",
-        "UMask": "0x0000000040",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle.  This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_M_CAS_COUNT.PCH1",
+        "BriefDescription": "Read Pending Queue Occupancy",
+        "EventCode": "0x81",
+        "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1",
         "PerPkg": "1",
-        "UMask": "0x0000000080",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle.  This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Read Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT_SCH0",
+        "BriefDescription": "Write Pending Queue Allocations",
+        "EventCode": "0x20",
+        "EventName": "UNC_M_WPQ_INSERTS.PCH0",
         "PerPkg": "1",
-        "UMask": "0x0000000010",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue.  This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PMM Read Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT_SCH1",
+        "BriefDescription": "Write Pending Queue Allocations",
+        "EventCode": "0x20",
+        "EventName": "UNC_M_WPQ_INSERTS.PCH1",
+        "PerPkg": "1",
+        "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue.  This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.",
+        "UMask": "0x2",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Write Pending Queue Occupancy",
+        "EventCode": "0x82",
+        "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0",
+        "PerPkg": "1",
+        "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle.  This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.  So, we provide filtering based on if the request has posted or not.  By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA.  The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory.  High average occupancies will generally coincide with high write major mode counts.",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Write Pending Queue Occupancy",
+        "EventCode": "0x83",
+        "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1",
         "PerPkg": "1",
-        "UMask": "0x0000000020",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle.  This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.  So, we provide filtering based on if the request has posted or not.  By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA.  The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory.  High average occupancies will generally coincide with high write major mode counts.",
         "Unit": "iMC"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-other.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-other.json
index 495ceee21071d..fd253e3276df1 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-other.json
@@ -1,5141 +1,4465 @@
 [
     {
-        "BriefDescription": "UPI Clockticks",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CHA Clockticks",
         "EventCode": "0x01",
-        "EventName": "UNC_UPI_CLOCKTICKS",
+        "EventName": "UNC_CHA_CLOCKTICKS",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CHA clock cycles while the event is enabled",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Sent : All Data",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
+        "BriefDescription": "CMS Clockticks",
+        "EventCode": "0xc0",
+        "EventName": "UNC_CHA_CMS_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x000000000f",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRP Clockticks",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x01",
-        "EventName": "UNC_I_CLOCKTICKS",
+        "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed",
+        "EventCode": "0x53",
+        "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
-        "Unit": "IRP"
+        "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2P Clockticks",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x01",
-        "EventName": "UNC_M2P_CLOCKTICKS",
+        "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed",
+        "EventCode": "0x53",
+        "EventName": "UNC_CHA_DIR_LOOKUP.SNP",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
-        "Unit": "M2PCIe"
+        "PublicDescription": "Counts  transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "IIO Clockticks",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x01",
-        "EventName": "UNC_IIO_CLOCKTICKS",
+        "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe",
+        "EventCode": "0x54",
+        "EventName": "UNC_CHA_DIR_UPDATE.HA",
         "PerPkg": "1",
-        "PortMask": "0x0000",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of 4 bytes made by IIO Part0 to Memory",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe",
+        "EventCode": "0x54",
+        "EventName": "UNC_CHA_DIR_UPDATE.TOR",
         "PerPkg": "1",
-        "PortMask": "0x0001",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of 4 bytes made by IIO Part1 to Memory",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD",
         "PerPkg": "1",
-        "PortMask": "0x0002",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
+        "UMask": "0x1bc1ff",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of 4 bytes made by IIO Part2 to Memory",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Cache and Snoop Filter Lookups; Snoop Requests from a Remote Socket",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP",
         "PerPkg": "1",
-        "PortMask": "0x0004",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ.  This does not include lookups originating from the ISMQ.",
+        "UMask": "0x1c19ff",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of 4 bytes made by IIO Part3 to Memory",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "All LLC lines in E state that are victimized on a fill",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E",
         "PerPkg": "1",
-        "PortMask": "0x0008",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "All LLC lines in M state that are victimized on a fill",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M",
         "PerPkg": "1",
-        "PortMask": "0x0001",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "All LLC lines in S state that are victimized on a fill",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S",
         "PerPkg": "1",
-        "PortMask": "0x0002",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "OSB Snoop Broadcast : Local InvItoE",
+        "EventCode": "0x55",
+        "EventName": "UNC_CHA_OSB.LOCAL_INVITOE",
         "PerPkg": "1",
-        "PortMask": "0x0004",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "OSB Snoop Broadcast : Local InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "OSB Snoop Broadcast : Local Rd",
+        "EventCode": "0x55",
+        "EventName": "UNC_CHA_OSB.LOCAL_READ",
         "PerPkg": "1",
-        "PortMask": "0x0008",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "OSB Snoop Broadcast : Local Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "Requests for exclusive ownership of a cache line without receiving data",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.INVITOE",
         "PerPkg": "1",
-        "PortMask": "0x0010",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
+        "UMask": "0x30",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "Local requests for exclusive ownership of a cache line  without receiving data",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL",
         "PerPkg": "1",
-        "PortMask": "0x0020",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "Read requests made into the CHA",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.READS",
         "PerPkg": "1",
-        "PortMask": "0x0040",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a  write) .",
+        "UMask": "0x3",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "Read requests from a unit on this socket",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.READS_LOCAL",
         "PerPkg": "1",
-        "PortMask": "0x0080",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a  write).",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "Read requests from a remote socket",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.READS_REMOTE",
         "PerPkg": "1",
-        "PortMask": "0x0010",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a  write).",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "Write requests made into the CHA",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.WRITES",
         "PerPkg": "1",
-        "PortMask": "0x0020",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
+        "UMask": "0xc",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "Write Requests from a unit on this socket",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL",
         "PerPkg": "1",
-        "PortMask": "0x0040",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts  write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "Read and Write Requests; Writes Remote",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE",
         "PerPkg": "1",
-        "PortMask": "0x0080",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : All",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.ALL",
         "PerPkg": "1",
-        "PortMask": "0x0001",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : All : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0xc001ffff",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : DDR Access",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.DDR",
         "PerPkg": "1",
-        "PortMask": "0x0002",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : DDR Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : SF/LLC Evictions",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.EVICT",
         "PerPkg": "1",
-        "PortMask": "0x0004",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : SF/LLC Evictions : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : Just Hits",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.HIT",
         "PerPkg": "1",
-        "PortMask": "0x0008",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : Just Hits : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; All from Local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA",
         "PerPkg": "1",
-        "PortMask": "0x0010",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests from IA Cores",
+        "UMask": "0xc001ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts;CLFlush from Local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH",
         "PerPkg": "1",
-        "PortMask": "0x0020",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; CLFlush events that are initiated from the Core",
+        "UMask": "0xc8c7ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts;CLFlushOpt from Local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT",
         "PerPkg": "1",
-        "PortMask": "0x0040",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; CLFlushOpt events that are initiated from the Core",
+        "UMask": "0xc8d7ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; CRd from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD",
         "PerPkg": "1",
-        "PortMask": "0x0080",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts; Code read from local IA that misses in the snoop filter",
+        "UMask": "0xc80fff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Clockticks",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x01",
-        "EventName": "UNC_M2M_CLOCKTICKS",
+        "BriefDescription": "TOR Inserts; CRd Pref from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc88fff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M3UPI Clockticks",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x01",
-        "EventName": "UNC_M3UPI_CLOCKTICKS",
+        "BriefDescription": "TOR Inserts; DRd from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
-        "Unit": "M3UPI"
+        "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc817ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read requests from a unit on this socket",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.READS_LOCAL",
+        "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE",
         "PerPkg": "1",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc837ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read requests from a remote socket",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.READS_REMOTE",
+        "BriefDescription": "TOR Inserts; DRd Opt from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT",
         "PerPkg": "1",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "TOR Inserts; Data read opt from local IA that misses in the snoop filter",
+        "UMask": "0xc827ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write Requests from a unit on this socket",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL",
+        "BriefDescription": "TOR Inserts; DRd Opt Pref from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF",
         "PerPkg": "1",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc8a7ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read and Write Requests; Writes Remote",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE",
+        "BriefDescription": "TOR Inserts; DRd Pref from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF",
         "PerPkg": "1",
-        "UMask": "0x0000000008",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "TOR Inserts; Data read prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc897ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Requests for exclusive ownership of a cache line without receiving data",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.INVITOE",
+        "BriefDescription": "TOR Inserts; Hits from Local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
         "PerPkg": "1",
-        "UMask": "0x0000000030",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0xc001fd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA Clockticks",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x01",
-        "EventName": "UNC_CHA_CLOCKTICKS",
+        "BriefDescription": "TOR Inserts; CRd hits from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "TOR Inserts; Code read from local IA that hits in the snoop filter",
+        "UMask": "0xc80ffd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts for CRd misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "TOR Inserts; CRd Pref hits from local IA",
         "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF",
         "PerPkg": "1",
-        "UMask": "0x00c80ffe01",
-        "UMaskExt": "0x00c80ffe",
+        "PublicDescription": "TOR Inserts; Code read prefetch from local IA that hits in the snoop filter",
+        "UMask": "0xc88ffd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts for DRd misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "TOR Inserts; DRd hits from local IA",
         "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD",
         "PerPkg": "1",
-        "UMask": "0x00c817fe01",
-        "UMaskExt": "0x00c817fe",
+        "PublicDescription": "TOR Inserts; Data read from local IA that hits in the snoop filter",
+        "UMask": "0xc817fd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts for DRd Pref misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC",
         "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE",
         "PerPkg": "1",
-        "UMask": "0x00c897fe01",
-        "UMaskExt": "0x00c897fe",
+        "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to page walks that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc837fd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts for ItoM from local IO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "TOR Inserts; DRd Opt hits from local IA",
         "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT",
         "PerPkg": "1",
-        "UMask": "0x00cc43ff04",
-        "UMaskExt": "0x00cc43ff",
+        "PublicDescription": "TOR Inserts; Data read opt from local IA that hits in the snoop filter",
+        "UMask": "0xc827fd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts for DRd misses from local IA targeting local memory",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "TOR Inserts; DRd Opt Pref hits from local IA",
         "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF",
         "PerPkg": "1",
-        "UMask": "0x00c816fe01",
-        "UMaskExt": "0x00c816fe",
+        "PublicDescription": "TOR Inserts; Data read opt prefetch from local IA that hits in the snoop filter",
+        "UMask": "0xc8a7fd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts for DRd misses from local IA targeting remote memory",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "TOR Inserts; DRd Pref hits from local IA",
         "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF",
         "PerPkg": "1",
-        "UMask": "0x00c8177e01",
-        "UMaskExt": "0x00c8177e",
+        "PublicDescription": "TOR Inserts; Data read prefetch from local IA that hits in the snoop filter",
+        "UMask": "0xc897fd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts for DRd Pref misses from local IA targeting local memory",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC",
         "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM",
         "PerPkg": "1",
-        "UMask": "0x00C896FE01",
-        "UMaskExt": "0x00C896FE",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc47fd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts for DRd Pref misses from local IA targeting remote memory",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "TOR Inserts; LLCPrefCode hits from local IA",
         "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE",
         "PerPkg": "1",
-        "UMask": "0x00C8977E01",
-        "UMaskExt": "0x00C8977E",
+        "PublicDescription": "TOR Inserts; Last level cache prefetch code read from local IA that hits in the snoop filter",
+        "UMask": "0xcccffd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy for DRd misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
+        "BriefDescription": "TOR Inserts; LLCPrefData hits from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA",
         "PerPkg": "1",
-        "UMask": "0x00c817fe01",
-        "UMaskExt": "0x00c817fe",
+        "PublicDescription": "TOR Inserts; Last level cache prefetch data read from local IA that hits in the snoop filter",
+        "UMask": "0xccd7fd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy for DRd misses from local IA targeting local memory",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL",
+        "BriefDescription": "TOR Inserts; LLCPrefRFO hits from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO",
         "PerPkg": "1",
-        "UMask": "0x00c816fe01",
-        "UMaskExt": "0x00c816fe",
+        "PublicDescription": "TOR Inserts; Last level cache prefetch read for ownership from local IA that hits in the snoop filter",
+        "UMask": "0xccc7fd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy for DRd misses from local IA targeting remote memory",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE",
+        "BriefDescription": "TOR Inserts; RFO hits from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
         "PerPkg": "1",
-        "UMask": "0x00c8177e01",
-        "UMaskExt": "0x00c8177e",
+        "PublicDescription": "TOR Inserts; Read for ownership from local IA that hits in the snoop filter",
+        "UMask": "0xc807fd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts for DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "TOR Inserts; RFO Pref hits from local IA",
         "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF",
         "PerPkg": "1",
-        "UMask": "0x00c8178a01",
-        "UMaskExt": "0x00c8178a",
+        "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that hits in the snoop filter",
+        "UMask": "0xc887fd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts for DRds issued by IA Cores targeting DDR Mem that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "TOR Inserts;ItoM from Local IA",
         "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM",
         "PerPkg": "1",
-        "UMask": "0x00c8178601",
-        "UMaskExt": "0x00c81786",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; ItoM events that are initiated from the Core",
+        "UMask": "0xcc47ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy for DRds issued by iA Cores targeting DDR Mem that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR",
+        "BriefDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR",
         "PerPkg": "1",
-        "UMask": "0x00c8178601",
-        "UMaskExt": "0x00c81786",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcd47ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy for DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM",
+        "BriefDescription": "TOR Inserts; LLCPrefCode from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE",
         "PerPkg": "1",
-        "UMask": "0x00c8178a01",
-        "UMaskExt": "0x00c8178a",
+        "PublicDescription": "TOR Inserts; Last level cache prefetch code read from local IA.",
+        "UMask": "0xcccfff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts for RdCur from local IO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "TOR Inserts; LLCPrefData from local IA",
         "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA",
         "PerPkg": "1",
-        "UMask": "0x00c8f3ff04",
-        "UMaskExt": "0x00c8f3ff",
+        "PublicDescription": "TOR Inserts; Last level cache prefetch data read from local IA.",
+        "UMask": "0xccd7ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts for ItoMCacheNears from IO devices",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "TOR Inserts; LLCPrefRFO from local IA",
         "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO",
         "PerPkg": "1",
-        "UMask": "0x00cd43ff04",
-        "UMaskExt": "0x00cd43ff",
+        "PublicDescription": "TOR Inserts; Last level cache prefetch read for ownership from local IA that misses in the snoop filter",
+        "UMask": "0xccc7ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Sent : Slot 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.SLOT0",
+        "BriefDescription": "TOR Inserts; misses from Local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
         "PerPkg": "1",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Sent : Slot 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.SLOT1",
+        "BriefDescription": "TOR Inserts for CRd misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
         "PerPkg": "1",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode CRd",
+        "UMask": "0xc80ffe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Sent : Slot 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.SLOT2",
+        "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc80efe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Sent : Data",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.DATA",
+        "BriefDescription": "TOR Inserts; CRd Pref misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF",
         "PerPkg": "1",
-        "UMask": "0x0000000008",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc88ffe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Sent : LLCRD Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.LLCRD",
+        "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x0000000010",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc88efe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.NULL",
+        "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x0000000020",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc88f7e01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Sent : LLCTRL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.LLCTRL",
+        "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x0000000040",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc80f7e01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Sent : Protocol Header",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.PROTHDR",
+        "BriefDescription": "TOR Inserts for DRd misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD",
         "PerPkg": "1",
-        "UMask": "0x0000000080",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd",
+        "UMask": "0xc817fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Sent : All Non Data",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
+        "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE",
         "PerPkg": "1",
-        "UMask": "0x0000000097",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc837fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Sent : Idle",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.IDLE",
+        "BriefDescription": "TOR Inserts for DRds issued by IA Cores targeting DDR Mem that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR",
         "PerPkg": "1",
-        "UMask": "0x0000000047",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target DDR memory",
+        "UMask": "0xc8178601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "All Null Flits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
+        "BriefDescription": "TOR Inserts for DRd misses from local IA targeting local memory",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x0000000027",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target local memory",
+        "UMask": "0xc816fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Received : Slot 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.SLOT0",
+        "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR",
         "PerPkg": "1",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8168601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Received : Slot 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.SLOT1",
+        "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM",
         "PerPkg": "1",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8168a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Received : Slot 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.SLOT2",
+        "BriefDescription": "TOR Inserts; DRd Opt misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT",
         "PerPkg": "1",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "TOR Inserts; Data read opt from local IA that misses in the snoop filter",
+        "UMask": "0xc827fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Received : Data",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.DATA",
+        "BriefDescription": "TOR Inserts; DRd Opt Pref misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF",
         "PerPkg": "1",
-        "UMask": "0x0000000008",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc8a7fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Received : LLCRD Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.LLCRD",
+        "BriefDescription": "TOR Inserts for DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM",
         "PerPkg": "1",
-        "UMask": "0x0000000010",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target PMM memory",
+        "UMask": "0xc8178a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.NULL",
+        "BriefDescription": "TOR Inserts for DRd Pref misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF",
         "PerPkg": "1",
-        "UMask": "0x0000000020",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF",
+        "UMask": "0xc897fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Received : LLCTRL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.LLCTRL",
+        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_DDR",
         "PerPkg": "1",
-        "UMask": "0x0000000040",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8978601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Received : Protocol Header",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.PROTHDR",
+        "BriefDescription": "TOR Inserts for DRd Pref misses from local IA targeting local memory",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x0000000080",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target local memory",
+        "UMask": "0xc896fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Received : All Data",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
+        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_DDR",
         "PerPkg": "1",
-        "UMask": "0x000000000f",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8968601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Received : All Non Data",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
+        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_PMM",
         "PerPkg": "1",
-        "UMask": "0x0000000097",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8968a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Received : Idle",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.IDLE",
+        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_PMM",
         "PerPkg": "1",
-        "UMask": "0x0000000047",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8978a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Null FLITs received from any slot",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
+        "BriefDescription": "TOR Inserts for DRd Pref misses from local IA targeting remote memory",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x0000000027",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target remote memory",
+        "UMask": "0xc8977e01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
+        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_DDR",
         "PerPkg": "1",
-        "UMask": "0x000000000e",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8970601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
+        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_PMM",
         "PerPkg": "1",
-        "UMask": "0x000000010e",
-        "UMaskExt": "0x00000001",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8970a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
+        "BriefDescription": "TOR Inserts for DRd misses from local IA targeting remote memory",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x000000000f",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and target remote memory",
+        "UMask": "0xc8177e01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
+        "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR",
         "PerPkg": "1",
-        "UMask": "0x000000010f",
-        "UMaskExt": "0x00000001",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8170601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
+        "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM",
         "PerPkg": "1",
-        "UMask": "0x000000000e",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8170a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
+        "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM",
         "PerPkg": "1",
-        "UMask": "0x000000010e",
-        "UMaskExt": "0x00000001",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc47fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
+        "BriefDescription": "TOR Inserts; LLCPrefCode misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE",
         "PerPkg": "1",
-        "UMask": "0x000000000f",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "TOR Inserts; Last level cache prefetch code read from local IA that misses in the snoop filter",
+        "UMask": "0xcccffe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
+        "BriefDescription": "TOR Inserts; LLCPrefData misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA",
         "PerPkg": "1",
-        "UMask": "0x000000010f",
-        "UMaskExt": "0x00000001",
-        "Unit": "UPI LL"
+        "PublicDescription": "TOR Inserts; Last level cache prefetch data read from local IA that misses in the snoop filter",
+        "UMask": "0xccd7fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Direct packet attempts : D2C",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C",
+        "BriefDescription": "TOR Inserts; LLCPrefRFO misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO",
         "PerPkg": "1",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "TOR Inserts; Last level cache prefetch read for ownership from local IA that misses in the snoop filter",
+        "UMask": "0xccc7fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles in L1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_UPI_L1_POWER_CYCLES",
+        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8668601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "RxQ Flit Buffer Allocations : Slot 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x30",
-        "EventName": "UNC_UPI_RxL_INSERTS.SLOT0",
+        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM",
         "PerPkg": "1",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8668a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "RxQ Flit Buffer Allocations : Slot 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x30",
-        "EventName": "UNC_UPI_RxL_INSERTS.SLOT1",
+        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR",
         "PerPkg": "1",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86e8601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "RxQ Flit Buffer Allocations : Slot 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x30",
-        "EventName": "UNC_UPI_RxL_INSERTS.SLOT2",
+        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM",
         "PerPkg": "1",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86e8a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x31",
-        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0",
+        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR",
         "PerPkg": "1",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8670601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x31",
-        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1",
+        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM",
         "PerPkg": "1",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8670a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x31",
-        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2",
+        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR",
         "PerPkg": "1",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86f0601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "RxQ Occupancy - All Packets : Slot 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x32",
-        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0",
+        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM",
         "PerPkg": "1",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86f0a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "RxQ Occupancy - All Packets : Slot 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x32",
-        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1",
+        "BriefDescription": "TOR Inserts; RFO misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
         "PerPkg": "1",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "TOR Inserts; Read for ownership from local IA that misses in the snoop filter",
+        "UMask": "0xc807fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "RxQ Occupancy - All Packets : Slot 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x32",
-        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2",
+        "BriefDescription": "TOR Inserts RFO misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "TOR Inserts; Read for ownership from local IA that misses in the snoop filter",
+        "UMask": "0xc806fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tx Flit Buffer Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_UPI_TxL_INSERTS",
+        "BriefDescription": "TOR Inserts; RFO pref misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc887fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tx Flit Buffer Bypassed",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_UPI_TxL_BYPASSED",
+        "BriefDescription": "TOR Inserts; RFO prefetch misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc886fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tx Flit Buffer Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_UPI_TxL_OCCUPANCY",
+        "BriefDescription": "TOR Inserts; RFO prefetch misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
-        "Unit": "UPI LL"
+        "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc8877e01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "FAF allocation -- sent to ADQ",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x16",
-        "EventName": "UNC_I_FAF_TRANSACTIONS",
+        "BriefDescription": "TOR Inserts; RFO misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
-        "Unit": "IRP"
+        "PublicDescription": "TOR Inserts Read for ownership from local IA that misses in the snoop filter",
+        "UMask": "0xc8077e01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "FAF - request insert from TC",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_I_FAF_INSERTS",
+        "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
-        "Unit": "IRP"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc877de01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "FAF occupancy",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_I_FAF_OCCUPANCY",
+        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
-        "Unit": "IRP"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86ffe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
+        "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF",
         "PerPkg": "1",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IRP"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc867fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Inbound write (fast path) requests received by the IRP",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
+        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR",
         "PerPkg": "1",
-        "UMask": "0x0000000008",
-        "UMaskExt": "0x00000000",
-        "Unit": "IRP"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8678601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Clockticks",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_M2P_CMS_CLOCKTICKS",
+        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM",
         "PerPkg": "1",
-        "Unit": "M2PCIe"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8678a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for 4 bytes made by IIO Part0 to Memory",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR",
         "PerPkg": "1",
-        "PortMask": "0x0001",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86f8601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for 4 bytes made by IIO Part1 to Memory",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM",
         "PerPkg": "1",
-        "PortMask": "0x0002",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86f8a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for 4 bytes made by IIO Part2 to Memory",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL",
         "PerPkg": "1",
-        "PortMask": "0x0004",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc87fde01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for 4 bytes made by IIO Part3 to Memory",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; RFO from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO",
         "PerPkg": "1",
-        "PortMask": "0x0008",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts; Read for ownership from local IA that misses in the snoop filter",
+        "UMask": "0xc807ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; RFO pref from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF",
         "PerPkg": "1",
-        "PortMask": "0x0010",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc887ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts;SpecItoM from Local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM",
         "PerPkg": "1",
-        "PortMask": "0x0020",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; SpecItoM events that are initiated from the Core",
+        "UMask": "0xcc57ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core.  Non Modified Write Backs",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE",
         "PerPkg": "1",
-        "PortMask": "0x0040",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "WbEFtoEs issued by iA Cores .  (Non Modified Write Backs)  :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.  Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc3fff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI",
         "PerPkg": "1",
-        "PortMask": "0x0080",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "WbMtoIs issued by iA Cores .  (Modified Write Backs)  :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.  Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc27ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL",
         "PerPkg": "1",
-        "PortMask": "0x0001",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86fff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF",
         "PerPkg": "1",
-        "PortMask": "0x0002",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc867ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; All from local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO",
         "PerPkg": "1",
-        "PortMask": "0x0004",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH",
         "PerPkg": "1",
-        "PortMask": "0x0008",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8c3ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; Hits from local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
         "PerPkg": "1",
-        "PortMask": "0x0001",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fd04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is  made by IIO Part1 to Memory",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; ItoM hits from local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM",
         "PerPkg": "1",
-        "PortMask": "0x0002",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc43fd04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR",
         "PerPkg": "1",
-        "PortMask": "0x0004",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcd43fd04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; RdCur and FsRdCur hits from local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR",
         "PerPkg": "1",
-        "PortMask": "0x0008",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8f3fd04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; RFO hits from local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO",
         "PerPkg": "1",
-        "PortMask": "0x0010",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc803fd04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts for ItoM from local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM",
         "PerPkg": "1",
-        "PortMask": "0x0020",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Inserts into the TOR from local IO with the opcode ItoM",
+        "UMask": "0xcc43ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts for ItoMCacheNears from IO devices.",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR",
         "PerPkg": "1",
-        "PortMask": "0x0040",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Inserts into the TOR from local IO devices with the opcode ItoMCacheNears.  This event indicates a partial write request.",
+        "UMask": "0xcd43ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; Misses from local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
         "PerPkg": "1",
-        "PortMask": "0x0080",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fe04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; ItoM misses from local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
         "PerPkg": "1",
-        "PortMask": "0x0010",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc43fe04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR",
         "PerPkg": "1",
-        "PortMask": "0x0020",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcd43fe04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; RdCur and FsRdCur misses from local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR",
         "PerPkg": "1",
-        "PortMask": "0x0040",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8f3fe04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; RFO misses from local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
         "PerPkg": "1",
-        "PortMask": "0x0080",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc803fe04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts for RdCur from local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR",
         "PerPkg": "1",
-        "PortMask": "0x0001",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Inserts into the TOR from local IO with the opcode RdCur",
+        "UMask": "0xc8f3ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; RFO from local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO",
         "PerPkg": "1",
-        "PortMask": "0x0002",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc803ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI",
         "PerPkg": "1",
-        "PortMask": "0x0004",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc23ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : IPQ",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IPQ",
         "PerPkg": "1",
-        "PortMask": "0x0008",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : IPQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : IRQ - iA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA",
         "PerPkg": "1",
-        "PortMask": "0x0010",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : IRQ - iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : From an iA Core",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : IRQ - Non iA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA",
         "PerPkg": "1",
-        "PortMask": "0x0020",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : IRQ - Non iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : Just ISOC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.ISOC",
         "PerPkg": "1",
-        "PortMask": "0x0040",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : Just ISOC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : Just Local Targets",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT",
         "PerPkg": "1",
-        "PortMask": "0x0080",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : Just Local Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : All from Local iA and IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
         "PerPkg": "1",
-        "PortMask": "0x0001",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : All from Local iA and IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally initiated requests",
+        "UMask": "0xc000ff05",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : All from Local iA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA",
         "PerPkg": "1",
-        "PortMask": "0x0002",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : All from Local iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally initiated requests from iA Cores",
+        "UMask": "0xc000ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : All from Local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO",
         "PerPkg": "1",
-        "PortMask": "0x0004",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : All from Local IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally generated IO traffic",
+        "UMask": "0xc000ff04",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC",
         "PerPkg": "1",
-        "PortMask": "0x0008",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : Just Misses",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.MISS",
         "PerPkg": "1",
-        "PortMask": "0x0001",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : Just Misses : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : MMCFG Access",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.MMCFG",
         "PerPkg": "1",
-        "PortMask": "0x0002",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : MMCFG Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : MMIO Access",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.MMIO",
         "PerPkg": "1",
-        "PortMask": "0x0004",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : MMIO Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : Just NonCoherent",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.NONCOH",
         "PerPkg": "1",
-        "PortMask": "0x0008",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : Just NonCoherent : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : PMM Access",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.PMM",
         "PerPkg": "1",
-        "PortMask": "0x0010",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : PM Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC",
         "PerPkg": "1",
-        "PortMask": "0x0020",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : PRQ - IOSF",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF",
         "PerPkg": "1",
-        "PortMask": "0x0040",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : PRQ - IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : From a PCIe Device",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : PRQ - Non IOSF",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF",
         "PerPkg": "1",
-        "PortMask": "0x0080",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : PRQ - Non IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : Just Remote Targets",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.REMOTE_TGT",
         "PerPkg": "1",
-        "PortMask": "0x0010",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : Just Remote Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : All from Remote",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL",
         "PerPkg": "1",
-        "PortMask": "0x0020",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : All from Remote : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All remote requests (e.g. snoops, writebacks) that came from remote sockets",
+        "UMask": "0xc001ffc8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : All Snoops from Remote",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.REM_SNPS",
         "PerPkg": "1",
-        "PortMask": "0x0040",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : All Snoops from Remote : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All snoops to this LLC that came from remote sockets",
+        "UMask": "0xc001ff08",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : RRQ",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.RRQ",
         "PerPkg": "1",
-        "PortMask": "0x0080",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : RRQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts; All Snoops from Remote",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.SNPS_FROM_REM",
         "PerPkg": "1",
-        "PortMask": "0x0001",
-        "UMask": "0x0000000080",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. All snoops to this LLC that came from remote sockets.",
+        "UMask": "0xc001ff08",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Inserts : WBQ",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.WBQ",
         "PerPkg": "1",
-        "PortMask": "0x0002",
-        "UMask": "0x0000000080",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Inserts : WBQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Occupancy : All",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL",
+        "PerPkg": "1",
+        "PublicDescription": "TOR Occupancy : All : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0xc001ffff",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "TOR Occupancy : DDR Access",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR",
+        "PerPkg": "1",
+        "PublicDescription": "TOR Occupancy : DDR Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "TOR Occupancy : SF/LLC Evictions",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
+        "PerPkg": "1",
+        "PublicDescription": "TOR Occupancy : SF/LLC Evictions : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "TOR Occupancy : Just Hits",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
+        "PerPkg": "1",
+        "PublicDescription": "TOR Occupancy : Just Hits : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "TOR Occupancy; All from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
+        "PerPkg": "1",
+        "PublicDescription": "TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001ff01",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH",
+        "PerPkg": "1",
+        "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8c7ff01",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT",
+        "PerPkg": "1",
+        "PublicDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8d7ff01",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "TOR Occupancy; CRd from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD",
+        "PerPkg": "1",
+        "PublicDescription": "TOR Occupancy; Code read from local IA that misses in the snoop filter",
+        "UMask": "0xc80fff01",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "TOR Occupancy; CRd Pref from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF",
+        "PerPkg": "1",
+        "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc88fff01",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "TOR Occupancy; DRd from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD",
+        "PerPkg": "1",
+        "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc817ff01",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "TOR Occupancy; DRd Opt from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT",
+        "PerPkg": "1",
+        "PublicDescription": "TOR Occupancy; Data read opt from local IA that misses in the snoop filter",
+        "UMask": "0xc827ff01",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "TOR Occupancy; DRd Opt Pref from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF",
+        "PerPkg": "1",
+        "PublicDescription": "TOR Occupancy; Data read opt prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc8a7ff01",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "TOR Occupancy; DRd Pref from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF",
+        "PerPkg": "1",
+        "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc897ff01",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "TOR Occupancy; Hits from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
+        "PerPkg": "1",
+        "PublicDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fd01",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "TOR Occupancy; CRd hits from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
+        "PerPkg": "1",
+        "PublicDescription": "TOR Occupancy; Code read from local IA that hits in the snoop filter",
+        "UMask": "0xc80ffd01",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "TOR Occupancy; CRd Pref hits from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF",
+        "PerPkg": "1",
+        "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that hits in the snoop filter",
+        "UMask": "0xc88ffd01",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "TOR Occupancy; DRd hits from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
+        "PerPkg": "1",
+        "PublicDescription": "TOR Occupancy; Data read from local IA that hits in the snoop filter",
+        "UMask": "0xc817fd01",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "TOR Occupancy; DRd Opt hits from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT",
         "PerPkg": "1",
-        "PortMask": "0x0004",
-        "UMask": "0x0000000080",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Occupancy; Data read opt from local IA that hits in the snoop filter",
+        "UMask": "0xc827fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Occupancy; DRd Opt Pref hits from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF",
         "PerPkg": "1",
-        "PortMask": "0x0008",
-        "UMask": "0x0000000080",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Occupancy; Data read opt prefetch from local IA that hits in the snoop filter",
+        "UMask": "0xc8a7fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Occupancy; DRd Pref hits from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF",
         "PerPkg": "1",
-        "PortMask": "0x0010",
-        "UMask": "0x0000000080",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that hits in the snoop filter",
+        "UMask": "0xc897fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM",
         "PerPkg": "1",
-        "PortMask": "0x0020",
-        "UMask": "0x0000000080",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc47fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Occupancy; LLCPrefCode hits from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE",
         "PerPkg": "1",
-        "PortMask": "0x0040",
-        "UMask": "0x0000000080",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Occupancy; Last level cache prefetch code read from local IA that hits in the snoop filter",
+        "UMask": "0xcccffd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Occupancy; LLCPrefData hits from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA",
         "PerPkg": "1",
-        "PortMask": "0x0080",
-        "UMask": "0x0000000080",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Occupancy; Last level cache prefetch data read from local IA that hits in the snoop filter",
+        "UMask": "0xccd7fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Occupancy; LLCPrefRFO hits from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Occupancy; Last level cache prefetch read for ownership from local IA that hits in the snoop filter",
+        "UMask": "0xccc7fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Occupancy; RFO hits from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Occupancy; Read for ownership from local IA that hits in the snoop filter",
+        "UMask": "0xc807fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Occupancy; RFO Pref hits from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that hits in the snoop filter",
+        "UMask": "0xc887fd01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc47ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcd47ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Occupancy; LLCPrefCode from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Occupancy; Last level cache prefetch data read from local IA.",
+        "UMask": "0xcccfff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Occupancy; LLCPrefData from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Occupancy; Last level cache prefetch data read from local IA that misses in the snoop filter",
+        "UMask": "0xccd7ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "TOR Occupancy; LLCPrefRFO from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Occupancy; Last level cache prefetch read for ownership from local IA that misses in the snoop filter",
+        "UMask": "0xccc7ff01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
-        "FCMask": "0x04",
+        "BriefDescription": "TOR Occupancy; Misses from Local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
         "PerPkg": "1",
-        "UMask": "0x00000000ff",
-        "UMaskExt": "0x00000000",
-        "Unit": "IIO"
+        "PublicDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AD Ingress (from CMS) : AD Ingress (from CMS) Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_M2M_RxC_AD_INSERTS",
+        "BriefDescription": "TOR Occupancy; CRd misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
         "PerPkg": "1",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Code read from local IA that misses in the snoop filter",
+        "UMask": "0xc80ffe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AD Ingress (from CMS) Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
+        "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc80efe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages sent direct to core (bypassing the CHA)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x16",
-        "EventName": "UNC_M2M_DIRECT2CORE_TAKEN",
+        "BriefDescription": "TOR Occupancy; CRd Pref misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF",
         "PerPkg": "1",
-        "UMask": "0x07",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc88ffe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x17",
-        "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
+        "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x07",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc88efe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number of reads in which direct to core transaction were overridden",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
+        "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc88f7e01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages sent direct to the Intel UPI",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2M_DIRECT2UPI_TAKEN",
+        "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x07",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc80f7e01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles when direct to Intel UPI was disabled",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1a",
-        "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
+        "BriefDescription": "TOR Occupancy for DRd misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
         "PerPkg": "1",
-        "UMask": "0x07",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd",
+        "UMask": "0xc817fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1b",
-        "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS",
+        "BriefDescription": "TOR Occupancy for DRds issued by iA Cores targeting DDR Mem that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR",
         "PerPkg": "1",
-        "UMask": "0x07",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target DDR memory",
+        "UMask": "0xc8178601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1c",
-        "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE",
+        "BriefDescription": "TOR Occupancy for DRd misses from local IA targeting local memory",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target local memory",
+        "UMask": "0xc816fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY",
+        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8168601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A",
+        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8168a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I",
+        "BriefDescription": "TOR Occupancy; DRd Opt misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Data read opt from local IA that misses in the snoop filter",
+        "UMask": "0xc827fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S",
+        "BriefDescription": "TOR Occupancy; DRd Opt Pref misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Data read opt prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc8a7fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory update from A to I",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I",
+        "BriefDescription": "TOR Occupancy for DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM",
         "PerPkg": "1",
-        "UMask": "0x0320",
-        "UMaskExt": "0x03",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target PMM memory",
+        "UMask": "0xc8178a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory update from A to S",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S",
+        "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF",
         "PerPkg": "1",
-        "UMask": "0x0340",
-        "UMaskExt": "0x03",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc897fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory update from/to Any state",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY",
+        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_DDR",
         "PerPkg": "1",
-        "UMask": "0x0301",
-        "UMaskExt": "0x03",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8978601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory update from I to A",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A",
+        "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x0304",
-        "UMaskExt": "0x03",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc896fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory update from I to S",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S",
+        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_DDR",
         "PerPkg": "1",
-        "UMask": "0x0302",
-        "UMaskExt": "0x03",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8968601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory update from S to A",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A",
+        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_PMM",
         "PerPkg": "1",
-        "UMask": "0x0310",
-        "UMaskExt": "0x03",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8968a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory update from S to I",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I",
+        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_PMM",
         "PerPkg": "1",
-        "UMask": "0x0308",
-        "UMaskExt": "0x03",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8978a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Inserts : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x32",
-        "EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
+        "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x0000000104",
-        "UMaskExt": "0x00000001",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc8977e01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Inserts : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x32",
-        "EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
+        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_DDR",
         "PerPkg": "1",
-        "UMask": "0x0000000204",
-        "UMaskExt": "0x00000002",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8970601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Occupancy : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
+        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_PMM",
         "PerPkg": "1",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8970a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Tracker Occupancy : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
+        "BriefDescription": "TOR Occupancy for DRd misses from local IA targeting remote memory",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target remote memory",
+        "UMask": "0xc8177e01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT",
+        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR",
         "PerPkg": "1",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8170601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_UPI",
+        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM",
         "PerPkg": "1",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8170a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT",
+        "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM",
         "PerPkg": "1",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc47fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_UPI",
+        "BriefDescription": "TOR Occupancy; LLCPrefCode misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE",
         "PerPkg": "1",
-        "UMask": "0x0000000008",
-        "UMaskExt": "0x00000000",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Last level cache prefetch code read from local IA that misses in the snoop filter",
+        "UMask": "0xcccffe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x56",
-        "EventName": "UNC_M2M_PREFCAM_INSERTS.UPI_ALLCH",
+        "BriefDescription": "TOR Occupancy; LLCPrefData misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA",
         "PerPkg": "1",
-        "UMask": "0x000000000a",
-        "UMaskExt": "0x00000000",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Last level cache prefetch data read from local IA that misses in the snoop filter",
+        "UMask": "0xccd7fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x56",
-        "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH",
+        "BriefDescription": "TOR Occupancy; LLCPrefRFO misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO",
         "PerPkg": "1",
-        "UMask": "0x0000000005",
-        "UMaskExt": "0x00000000",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy; Last level cache prefetch read for ownership from local IA that misses in the snoop filter",
+        "UMask": "0xccc7fe01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH",
+        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR",
         "PerPkg": "1",
-        "UMask": "0x0000000005",
-        "UMaskExt": "0x00000000",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8668601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": ": UPI - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5d",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.UPI_ALLCH",
+        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM",
         "PerPkg": "1",
-        "UMask": "0x000000000a",
-        "UMaskExt": "0x00000000",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8668a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": ": XPT - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5d",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPT_ALLCH",
+        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR",
         "PerPkg": "1",
-        "UMask": "0x0000000005",
-        "UMaskExt": "0x00000000",
-        "Unit": "M2M"
+        "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86e8601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "FlowQ Generated Prefetch",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x29",
-        "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN",
+        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
-        "Unit": "M3UPI"
+        "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86e8a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "D2U Sent",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2a",
-        "EventName": "UNC_M3UPI_D2U_SENT",
+        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
-        "Unit": "M3UPI"
+        "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8670601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "D2C Sent",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2b",
-        "EventName": "UNC_M3UPI_D2C_SENT",
+        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
-        "Unit": "M3UPI"
+        "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8670a01",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M3UPI CMS Clockticks",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_M3UPI_CMS_CLOCKTICKS",
+        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR",
         "PerPkg": "1",
-        "Unit": "M3UPI"
+        "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86f0601",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Local requests for exclusive ownership of a cache line  without receiving data",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL",
+        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM",
         "PerPkg": "1",
-        "UMask": "0x0000000010",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86f0a01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read requests made into the CHA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.READS",
+        "BriefDescription": "TOR Occupancy; RFO misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
         "PerPkg": "1",
-        "UMask": "0x0000000003",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter",
+        "UMask": "0xc807fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write requests made into the CHA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.WRITES",
+        "BriefDescription": "TOR Occupancy; RFO misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x000000000c",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter",
+        "UMask": "0xc806fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x53",
-        "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP",
+        "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF",
         "PerPkg": "1",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc887fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x53",
-        "EventName": "UNC_CHA_DIR_LOOKUP.SNP",
+        "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc886fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x54",
-        "EventName": "UNC_CHA_DIR_UPDATE.HA",
+        "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc8877e01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x54",
-        "EventName": "UNC_CHA_DIR_UPDATE.TOR",
+        "BriefDescription": "TOR Occupancy; RFO misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter",
+        "UMask": "0xc8077e01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "OSB Snoop Broadcast : Local InvItoE",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_CHA_OSB.LOCAL_INVITOE",
+        "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF",
         "PerPkg": "1",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc877de01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "OSB Snoop Broadcast : Local Rd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_CHA_OSB.LOCAL_READ",
+        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL",
         "PerPkg": "1",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86ffe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Clockticks",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_CHA_CMS_CLOCKTICKS",
+        "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc867fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD",
+        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR",
         "PerPkg": "1",
-        "UMask": "0x00001bc1ff",
-        "UMaskExt": "0x00001bc1",
+        "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8678601",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cache and Snoop Filter Lookups; Snoop Requests from a Remote Socket",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP",
+        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM",
         "PerPkg": "1",
-        "UMask": "0x00001c19ff",
-        "UMaskExt": "0x00001c19",
+        "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8678a01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; All Snoops from Remote",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.SNPS_FROM_REM",
+        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR",
         "PerPkg": "1",
-        "UMask": "0x00c001ff08",
-        "UMaskExt": "0x00c001ff",
+        "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86f8601",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.ALL",
+        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM",
         "PerPkg": "1",
-        "UMask": "0x00C001FFff",
-        "UMaskExt": "0x00C001FF",
+        "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86f8a01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; All from Local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA",
+        "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL",
         "PerPkg": "1",
-        "UMask": "0x00c001ff01",
-        "UMaskExt": "0x00c001ff",
+        "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc87fde01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; Hits from Local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
+        "BriefDescription": "TOR Occupancy; RFO from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO",
         "PerPkg": "1",
-        "UMask": "0x00c001fd01",
-        "UMaskExt": "0x00c001fd",
+        "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter",
+        "UMask": "0xc807ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; CRd hits from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
+        "BriefDescription": "TOR Occupancy; RFO prefetch from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF",
         "PerPkg": "1",
-        "UMask": "0x00c80ffd01",
-        "UMaskExt": "0x00c80ffd",
+        "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc887ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; DRd hits from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD",
+        "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM",
         "PerPkg": "1",
-        "UMask": "0x00c817fd01",
-        "UMaskExt": "0x00c817fd",
+        "PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc57ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; LLCPrefRFO hits from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO",
+        "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI",
         "PerPkg": "1",
-        "UMask": "0x00ccc7fd01",
-        "UMaskExt": "0x00ccc7fd",
+        "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc27ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; RFO hits from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
+        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL",
         "PerPkg": "1",
-        "UMask": "0x00c807fd01",
-        "UMaskExt": "0x00c807fd",
+        "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86fff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; misses from Local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+        "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF",
         "PerPkg": "1",
-        "UMask": "0x00c001fe01",
-        "UMaskExt": "0x00c001fe",
+        "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc867ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; LLCPrefRFO misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO",
+        "BriefDescription": "TOR Occupancy; All from local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
         "PerPkg": "1",
-        "UMask": "0x00ccc7fe01",
-        "UMaskExt": "0x00ccc7fe",
+        "PublicDescription": "TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001ff04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; RFO misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
+        "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Devices",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH",
         "PerPkg": "1",
-        "UMask": "0x00c807fe01",
-        "UMaskExt": "0x00c807fe",
+        "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8c3ff04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; All from local IO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO",
+        "BriefDescription": "TOR Occupancy; Hits from local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
         "PerPkg": "1",
-        "UMask": "0x00c001ff04",
-        "UMaskExt": "0x00c001ff",
+        "PublicDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fd04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; Hits from local IO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
+        "BriefDescription": "TOR Occupancy; ITOM hits from local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM",
         "PerPkg": "1",
-        "UMask": "0x00c001fd04",
-        "UMaskExt": "0x00c001fd",
+        "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc43fd04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; Misses from local IO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
+        "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR",
         "PerPkg": "1",
-        "UMask": "0x00c001fe04",
-        "UMaskExt": "0x00c001fe",
+        "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcd43fd04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; ItoM misses from local IO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
+        "BriefDescription": "TOR Occupancy; RdCur and FsRdCur hits from local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR",
         "PerPkg": "1",
-        "UMask": "0x00cc43fe04",
-        "UMaskExt": "0x00cc43fe",
+        "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8f3fd04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; RFO misses from local IO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
+        "BriefDescription": "TOR Occupancy; RFO hits from local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO",
         "PerPkg": "1",
-        "UMask": "0x00c803fe04",
-        "UMaskExt": "0x00c803fe",
+        "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc803fd04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : IRQ - iA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA",
+        "BriefDescription": "TOR Occupancy; ITOM from local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM",
         "PerPkg": "1",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc43ff04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : SF/LLC Evictions",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.EVICT",
+        "BriefDescription": "TOR Occupancy; Misses from local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
         "PerPkg": "1",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fe04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : PRQ - IOSF",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF",
+        "BriefDescription": "TOR Occupancy; ITOM misses from local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
         "PerPkg": "1",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc43fe04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : IPQ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IPQ",
+        "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR",
         "PerPkg": "1",
-        "UMask": "0x0000000008",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcd43fe04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : IRQ - Non iA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA",
+        "BriefDescription": "TOR Occupancy; RdCur and FsRdCur misses from local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR",
         "PerPkg": "1",
-        "UMask": "0x0000000010",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8f3fe04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : PRQ - Non IOSF",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF",
+        "BriefDescription": "TOR Occupancy; RFO misses from local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
         "PerPkg": "1",
-        "UMask": "0x0000000020",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc803fe04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RRQ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.RRQ",
+        "BriefDescription": "TOR Occupancy; RdCur and FsRdCur from local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR",
         "PerPkg": "1",
-        "UMask": "0x0000000040",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8f3ff04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : WBQ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.WBQ",
+        "BriefDescription": "TOR Occupancy; ItoM from local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO",
         "PerPkg": "1",
-        "UMask": "0x0000000080",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc803ff04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All from Local IO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO",
+        "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI",
         "PerPkg": "1",
-        "UMask": "0x00C000FF04",
-        "UMaskExt": "0x00C000FF",
+        "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc23ff04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All from Local iA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA",
+        "BriefDescription": "TOR Occupancy : IPQ",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ",
         "PerPkg": "1",
-        "UMask": "0x00c000ff01",
-        "UMaskExt": "0x00c000ff",
+        "PublicDescription": "TOR Occupancy : IPQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All from Local iA and IO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
+        "BriefDescription": "TOR Occupancy : IRQ - iA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA",
         "PerPkg": "1",
-        "UMask": "0x00C000FF05",
-        "UMaskExt": "0x00C000FF",
+        "PublicDescription": "TOR Occupancy : IRQ - iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T : From an iA Core",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All Snoops from Remote",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.REM_SNPS",
+        "BriefDescription": "TOR Occupancy : IRQ - Non iA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA",
         "PerPkg": "1",
-        "UMask": "0x00C001FF08",
-        "UMaskExt": "0x00C001FF",
+        "PublicDescription": "TOR Occupancy : IRQ - Non iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All from Remote",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL",
+        "BriefDescription": "TOR Occupancy : Just ISOC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC",
         "PerPkg": "1",
-        "UMask": "0x00C001FFC8",
-        "UMaskExt": "0x00C001FF",
+        "PublicDescription": "TOR Occupancy : Just ISOC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : Just Hits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.HIT",
+        "BriefDescription": "TOR Occupancy : Just Local Targets",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT",
         "PerPkg": "1",
-        "UMaskExt": "0x00000001",
+        "PublicDescription": "TOR Occupancy : Just Local Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : Just Misses",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.MISS",
+        "BriefDescription": "TOR Occupancy : All from Local iA and IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
         "PerPkg": "1",
-        "UMaskExt": "0x00000002",
+        "PublicDescription": "TOR Occupancy : All from Local iA and IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T : All locally initiated requests",
+        "UMask": "0xc000ff05",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : MMCFG Access",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.MMCFG",
+        "BriefDescription": "TOR Occupancy : All from Local iA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA",
         "PerPkg": "1",
-        "UMaskExt": "0x00000020",
+        "PublicDescription": "TOR Occupancy : All from Local iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T : All locally initiated requests from iA Cores",
+        "UMask": "0xc000ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : MMIO Access",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.MMIO",
+        "BriefDescription": "TOR Occupancy : All from Local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO",
         "PerPkg": "1",
-        "UMaskExt": "0x00000040",
+        "PublicDescription": "TOR Occupancy : All from Local IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T : All locally generated IO traffic",
+        "UMask": "0xc000ff04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : Just Local Targets",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT",
+        "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC",
         "PerPkg": "1",
-        "UMaskExt": "0x00000080",
+        "PublicDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : Just Remote Targets",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.REMOTE_TGT",
+        "BriefDescription": "TOR Occupancy : Just Misses",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
         "PerPkg": "1",
-        "UMaskExt": "0x00000100",
+        "PublicDescription": "TOR Occupancy : Just Misses : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC",
+        "BriefDescription": "TOR Occupancy : MMCFG Access",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG",
         "PerPkg": "1",
-        "UMaskExt": "0x00000200",
+        "PublicDescription": "TOR Occupancy : MMCFG Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC",
+        "BriefDescription": "TOR Occupancy : MMIO Access",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.MMIO",
         "PerPkg": "1",
-        "UMaskExt": "0x00000400",
+        "PublicDescription": "TOR Occupancy : MMIO Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : Just NonCoherent",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.NONCOH",
+        "BriefDescription": "TOR Occupancy : Just NonCoherent",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH",
         "PerPkg": "1",
-        "UMaskExt": "0x01000000",
+        "PublicDescription": "TOR Occupancy : Just NonCoherent : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : Just ISOC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.ISOC",
+        "BriefDescription": "TOR Occupancy : PMM Access",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.PMM",
         "PerPkg": "1",
-        "UMaskExt": "0x02000000",
+        "PublicDescription": "TOR Occupancy : PMM Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; CRd Pref hits from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF",
+        "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC",
         "PerPkg": "1",
-        "UMask": "0x00c88ffd01",
-        "UMaskExt": "0x00c88ffd",
+        "PublicDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; DRd Pref hits from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF",
+        "BriefDescription": "TOR Occupancy : PRQ - IOSF",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
         "PerPkg": "1",
-        "UMask": "0x00c897fd01",
-        "UMaskExt": "0x00c897fd",
+        "PublicDescription": "TOR Occupancy : PRQ - IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T : From a PCIe Device",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; DRd Opt hits from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT",
+        "BriefDescription": "TOR Occupancy : PRQ - Non IOSF",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF",
         "PerPkg": "1",
-        "UMask": "0x00c827fd01",
-        "UMaskExt": "0x00c827fd",
+        "PublicDescription": "TOR Occupancy : PRQ - Non IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
-    {
-        "BriefDescription": "TOR Inserts; DRd Opt Pref hits from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF",
+    {
+        "BriefDescription": "TOR Occupancy : Just Remote Targets",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.REMOTE_TGT",
         "PerPkg": "1",
-        "UMask": "0x00c8a7fd01",
-        "UMaskExt": "0x00c8a7fd",
+        "PublicDescription": "TOR Occupancy : Just Remote Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; RFO Pref hits from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF",
+        "BriefDescription": "TOR Occupancy : All from Remote",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.REM_ALL",
         "PerPkg": "1",
-        "UMask": "0x00c887fd01",
-        "UMaskExt": "0x00c887fd",
+        "PublicDescription": "TOR Occupancy : All from Remote : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T : All remote requests (e.g. snoops, writebacks) that came from remote sockets",
+        "UMask": "0xc001ffc8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; CRd Pref misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF",
+        "BriefDescription": "TOR Occupancy : All Snoops from Remote",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.REM_SNPS",
         "PerPkg": "1",
-        "UMask": "0x00c88ffe01",
-        "UMaskExt": "0x00c88ffe",
+        "PublicDescription": "TOR Occupancy : All Snoops from Remote : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T : All snoops to this LLC that came from remote sockets",
+        "UMask": "0xc001ff08",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; DRd Opt misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT",
+        "BriefDescription": "TOR Occupancy : RRQ",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.RRQ",
         "PerPkg": "1",
-        "UMask": "0x00c827fe01",
-        "UMaskExt": "0x00c827fe",
+        "PublicDescription": "TOR Occupancy : RRQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; DRd Opt Pref misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF",
+        "BriefDescription": "TOR Occupancy; All Snoops from Remote",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.SNPS_FROM_REM",
         "PerPkg": "1",
-        "UMask": "0x00c8a7fe01",
-        "UMaskExt": "0x00c8a7fe",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   All snoops to this LLC that came from remote sockets.",
+        "UMask": "0xc001ff08",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; RFO pref misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF",
+        "BriefDescription": "TOR Occupancy : WBQ",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.WBQ",
         "PerPkg": "1",
-        "UMask": "0x00c887fe01",
-        "UMaskExt": "0x00c887fe",
+        "PublicDescription": "TOR Occupancy : WBQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; ItoM hits from local IO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM",
+        "BriefDescription": "IIO Clockticks",
+        "EventCode": "0x01",
+        "EventName": "UNC_IIO_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x00cc43fd04",
-        "UMaskExt": "0x00cc43fd",
-        "Unit": "CHA"
+        "PortMask": "0x0000",
+        "PublicDescription": "Number of IIO clock cycles while the event is enabled",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; RFO hits from local IO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c803fd04",
-        "UMaskExt": "0x00c803fd",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; RFO from local IO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c803ff04",
-        "UMaskExt": "0x00c803ff",
-        "Unit": "CHA"
+        "PortMask": "0x02",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; RFO pref from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c887ff01",
-        "UMaskExt": "0x00c887ff",
-        "Unit": "CHA"
+        "PortMask": "0x04",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; RFO from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c807ff01",
-        "UMaskExt": "0x00c807ff",
-        "Unit": "CHA"
+        "PortMask": "0x08",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; LLCPrefRFO from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00ccc7ff01",
-        "UMaskExt": "0x00ccc7ff",
-        "Unit": "CHA"
+        "PortMask": "0x10",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; DRd from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c817ff01",
-        "UMaskExt": "0x00c817ff",
-        "Unit": "CHA"
+        "PortMask": "0x20",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; DRd Pref from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c897ff01",
-        "UMaskExt": "0x00c897ff",
-        "Unit": "CHA"
+        "PortMask": "0x40",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; DRd Opt from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c827ff01",
-        "UMaskExt": "0x00c827ff",
-        "Unit": "CHA"
+        "PortMask": "0x80",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; DRd Opt Pref from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF",
+        "BriefDescription": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
+        "EventCode": "0xd5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0x00c8a7ff01",
-        "UMaskExt": "0x00c8a7ff",
-        "Unit": "CHA"
+        "UMask": "0xff",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; CRd Pref from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF",
+        "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00C88FFF01",
-        "UMaskExt": "0x00C88FFF",
-        "Unit": "CHA"
+        "PortMask": "0x0100",
+        "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; CRd from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD",
+        "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c80fff01",
-        "UMaskExt": "0x00c80fff",
-        "Unit": "CHA"
+        "PortMask": "0x0200",
+        "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts RFO misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL",
+        "BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c806fe01",
-        "UMaskExt": "0x00c806fe",
-        "Unit": "CHA"
+        "PortMask": "0x0001",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; RFO misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE",
+        "BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c8077e01",
-        "UMaskExt": "0x00c8077e",
-        "Unit": "CHA"
+        "PortMask": "0x0002",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; RFO prefetch misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL",
+        "BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c886fe01",
-        "UMaskExt": "0x00c886fe",
-        "Unit": "CHA"
+        "PortMask": "0x0004",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; RFO prefetch misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE",
+        "BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c8877e01",
-        "UMaskExt": "0x00c8877e",
-        "Unit": "CHA"
+        "PortMask": "0x0008",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts;CLFlush from Local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH",
+        "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c8c7ff01",
-        "UMaskExt": "0x00c8c7ff",
-        "Unit": "CHA"
+        "PortMask": "0x0010",
+        "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts;CLFlushOpt from Local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT",
+        "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c8d7ff01",
-        "UMaskExt": "0x00c8d7ff",
-        "Unit": "CHA"
+        "PortMask": "0x0020",
+        "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts;ItoM from Local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM",
+        "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00cc47ff01",
-        "UMaskExt": "0x00cc47ff",
-        "Unit": "CHA"
+        "PortMask": "0x0040",
+        "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts;SpecItoM from Local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM",
+        "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00cc57ff01",
-        "UMaskExt": "0x00cc57ff",
-        "Unit": "CHA"
+        "PortMask": "0x0080",
+        "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; All Snoops from Remote",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.SNPS_FROM_REM",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c001ff08",
-        "UMaskExt": "0x00c001ff",
-        "Unit": "CHA"
+        "PortMask": "0x0001",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : All",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00C001FFff",
-        "UMaskExt": "0x00C001FF",
-        "Unit": "CHA"
+        "PortMask": "0x0002",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; All from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c001ff01",
-        "UMaskExt": "0x00c001ff",
-        "Unit": "CHA"
+        "PortMask": "0x0004",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; Hits from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c001fd01",
-        "UMaskExt": "0x00c001fd",
-        "Unit": "CHA"
+        "PortMask": "0x0008",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; CRd hits from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c80ffd01",
-        "UMaskExt": "0x00c80ffd",
-        "Unit": "CHA"
+        "PortMask": "0x0010",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; DRd hits from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c817fd01",
-        "UMaskExt": "0x00c817fd",
-        "Unit": "CHA"
+        "PortMask": "0x0020",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; LLCPrefRFO hits from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00ccc7fd01",
-        "UMaskExt": "0x00ccc7fd",
-        "Unit": "CHA"
+        "PortMask": "0x0040",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; RFO hits from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c807fd01",
-        "UMaskExt": "0x00c807fd",
-        "Unit": "CHA"
+        "PortMask": "0x0080",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; Misses from Local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
+        "BriefDescription": "Read request for 4 bytes made by IIO Part0 to Memory",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c001fe01",
-        "UMaskExt": "0x00c001fe",
-        "Unit": "CHA"
+        "PortMask": "0x0001",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; CRd misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
+        "BriefDescription": "Read request for 4 bytes made by IIO Part1 to Memory",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c80ffe01",
-        "UMaskExt": "0x00c80ffe",
-        "Unit": "CHA"
+        "PortMask": "0x0002",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; LLCPrefRFO misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO",
+        "BriefDescription": "Read request for 4 bytes made by IIO Part2 to Memory",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00ccc7fe01",
-        "UMaskExt": "0x00ccc7fe",
-        "Unit": "CHA"
+        "PortMask": "0x0004",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; RFO misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
+        "BriefDescription": "Read request for 4 bytes made by IIO Part3 to Memory",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c807fe01",
-        "UMaskExt": "0x00c807fe",
-        "Unit": "CHA"
+        "PortMask": "0x0008",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; All from local IO",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
+        "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c001ff04",
-        "UMaskExt": "0x00c001ff",
-        "Unit": "CHA"
+        "PortMask": "0x0010",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; Hits from local IO",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
+        "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c001fd04",
-        "UMaskExt": "0x00c001fd",
-        "Unit": "CHA"
+        "PortMask": "0x0020",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; Misses from local IO",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
+        "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c001fe04",
-        "UMaskExt": "0x00c001fe",
-        "Unit": "CHA"
+        "PortMask": "0x0040",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; RFO misses from local IO",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
+        "BriefDescription": "Data requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c803fe04",
-        "UMaskExt": "0x00c803fe",
-        "Unit": "CHA"
+        "PortMask": "0x0080",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; ITOM misses from local IO",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
+        "BriefDescription": "Write request of 4 bytes made by IIO Part0 to Memory",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00cc43fe04",
-        "UMaskExt": "0x00cc43fe",
-        "Unit": "CHA"
+        "PortMask": "0x0001",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : IRQ - iA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA",
+        "BriefDescription": "Write request of 4 bytes made by IIO Part1 to Memory",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "CHA"
+        "PortMask": "0x0002",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : SF/LLC Evictions",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
+        "BriefDescription": "Write request of 4 bytes made by IIO Part2 to Memory",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "CHA"
+        "PortMask": "0x0004",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : PRQ - IOSF",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
+        "BriefDescription": "Write request of 4 bytes made by IIO Part3 to Memory",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "CHA"
+        "PortMask": "0x0008",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : IPQ",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ",
+        "BriefDescription": "Data requested of the CPU : Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x0000000008",
-        "UMaskExt": "0x00000000",
-        "Unit": "CHA"
+        "PortMask": "0x0010",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : IRQ - Non iA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA",
+        "BriefDescription": "Data requested of the CPU : Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x0000000010",
-        "UMaskExt": "0x00000000",
-        "Unit": "CHA"
+        "PortMask": "0x0020",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : PRQ - Non IOSF",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF",
+        "BriefDescription": "Data requested of the CPU : Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x0000000020",
-        "UMaskExt": "0x00000000",
-        "Unit": "CHA"
+        "PortMask": "0x0040",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : RRQ",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.RRQ",
+        "BriefDescription": "Data requested of the CPU : Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x0000000040",
-        "UMaskExt": "0x00000000",
-        "Unit": "CHA"
+        "PortMask": "0x0080",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : WBQ",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.WBQ",
+        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x0000000080",
-        "UMaskExt": "0x00000000",
-        "Unit": "CHA"
+        "PortMask": "0x0001",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : All from Local IO",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO",
+        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00C000FF04",
-        "UMaskExt": "0x00C000FF",
-        "Unit": "CHA"
+        "PortMask": "0x0002",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : All from Local iA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA",
+        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00C000FF01",
-        "UMaskExt": "0x00C000FF",
-        "Unit": "CHA"
+        "PortMask": "0x0004",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : All from Local iA and IO",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
+        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00C000FF05",
-        "UMaskExt": "0x00C000FF",
-        "Unit": "CHA"
+        "PortMask": "0x0008",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : All Snoops from Remote",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.REM_SNPS",
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00C001FF08",
-        "UMaskExt": "0x00C001FF",
-        "Unit": "CHA"
+        "PortMask": "0x0010",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : All from Remote",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.REM_ALL",
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00C001FFC8",
-        "UMaskExt": "0x00C001FF",
-        "Unit": "CHA"
+        "PortMask": "0x0020",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : Just Hits",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x00000001",
-        "Unit": "CHA"
+        "PortMask": "0x0040",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : Just Misses",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMaskExt": "0x00000002",
-        "Unit": "CHA"
+        "PortMask": "0x0080",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : MMCFG Access",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG",
+        "BriefDescription": ": Context cache hits",
+        "EventCode": "0x40",
+        "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS",
         "PerPkg": "1",
-        "UMaskExt": "0x00000020",
-        "Unit": "CHA"
+        "PortMask": "0x0000",
+        "PublicDescription": ": Context cache hits : Counts each time a first look up of the transaction hits the RCC.",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : MMIO Access",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.MMIO",
+        "BriefDescription": ": Context cache lookups",
+        "EventCode": "0x40",
+        "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS",
         "PerPkg": "1",
-        "UMaskExt": "0x00000040",
-        "Unit": "CHA"
+        "PortMask": "0x0000",
+        "PublicDescription": ": Context cache lookups : Counts each time a transaction looks up root context cache.",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : Just Local Targets",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT",
+        "BriefDescription": ": IOTLB lookups first",
+        "EventCode": "0x40",
+        "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS",
         "PerPkg": "1",
-        "UMaskExt": "0x00000080",
-        "Unit": "CHA"
+        "PortMask": "0x0000",
+        "PublicDescription": ": IOTLB lookups first : Some transactions have to look up IOTLB multiple times.  Counts the first time a request looks up IOTLB.",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : Just Remote Targets",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.REMOTE_TGT",
+        "BriefDescription": "IOTLB Fills (same as IOTLB miss)",
+        "EventCode": "0x40",
+        "EventName": "UNC_IIO_IOMMU0.MISSES",
         "PerPkg": "1",
-        "UMaskExt": "0x00000100",
-        "Unit": "CHA"
+        "PortMask": "0x0000",
+        "PublicDescription": "IOTLB Fills (same as IOTLB miss) : When a transaction misses IOTLB, it does a page walk to look up memory and bring in the relevant page translation. Counts when this page translation is written to IOTLB.",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC",
+        "BriefDescription": ": IOMMU memory access",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES",
         "PerPkg": "1",
-        "UMaskExt": "0x00000200",
-        "Unit": "CHA"
+        "PublicDescription": ": IOMMU memory access : IOMMU sends out memory fetches when it misses the cache look up which is indicated by this signal.  M2IOSF only uses low priority channel",
+        "UMask": "0xc0",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC",
+        "BriefDescription": ": PWC Hit to a 2M page",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS",
         "PerPkg": "1",
-        "UMaskExt": "0x00000400",
-        "Unit": "CHA"
+        "PublicDescription": ": PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : Just NonCoherent",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH",
+        "BriefDescription": ": PWT Hit to a 256T page",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_IOMMU1.PWC_256T_HITS",
         "PerPkg": "1",
-        "UMaskExt": "0x01000000",
-        "Unit": "CHA"
+        "PublicDescription": ": PWT Hit to a 256T page : Counts each time a transaction's first look up hits the SLPWC at the 512G level",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : Just ISOC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC",
+        "BriefDescription": ": PWC Hit to a 4K page",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS",
         "PerPkg": "1",
-        "UMaskExt": "0x02000000",
-        "Unit": "CHA"
+        "PublicDescription": ": PWC Hit to a 4K page : Counts each time a transaction's first look up hits the SLPWC at the 4K level",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; CRd Pref hits from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF",
+        "BriefDescription": ": PWC Hit to a 1G page",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS",
         "PerPkg": "1",
-        "UMask": "0x00c88ffd01",
-        "UMaskExt": "0x00c88ffd",
-        "Unit": "CHA"
+        "PublicDescription": ": PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; DRd Pref hits from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF",
+        "BriefDescription": ": Global IOTLB invalidation cycles",
+        "EventCode": "0x43",
+        "EventName": "UNC_IIO_IOMMU3.PWT_OCCUPANCY_MSB",
         "PerPkg": "1",
-        "UMask": "0x00c897fd01",
-        "UMaskExt": "0x00c897fd",
-        "Unit": "CHA"
+        "PortMask": "0x0000",
+        "PublicDescription": ": Global IOTLB invalidation cycles : Indicates that IOMMU is doing global invalidation.",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; DRd Opt hits from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT",
+        "BriefDescription": "PWT occupancy.  Does not include 9th bit of occupancy (will undercount if PWT is greater than 255 per cycle).",
+        "EventCode": "0x42",
+        "EventName": "UNC_IIO_PWT_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x00c827fd01",
-        "UMaskExt": "0x00c827fd",
-        "Unit": "CHA"
+        "PortMask": "0x0000",
+        "PublicDescription": "PWT occupancy : Indicates how many page walks are outstanding at any point in time.",
+        "UMask": "0xff",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; DRd Opt Pref hits from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF",
+        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c8a7fd01",
-        "UMaskExt": "0x00c8a7fd",
-        "Unit": "CHA"
+        "PortMask": "0x0001",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; RFO Pref hits from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF",
+        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c887fd01",
-        "UMaskExt": "0x00c887fd",
-        "Unit": "CHA"
+        "PortMask": "0x0002",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; CRd Pref misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF",
+        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c88ffe01",
-        "UMaskExt": "0x00c88ffe",
-        "Unit": "CHA"
+        "PortMask": "0x0004",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF",
+        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c897fe01",
-        "UMaskExt": "0x00c897fe",
-        "Unit": "CHA"
+        "PortMask": "0x0008",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; DRd Opt misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c827fe01",
-        "UMaskExt": "0x00c827fe",
-        "Unit": "CHA"
+        "PortMask": "0x0010",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; DRd Opt Pref misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c8a7fe01",
-        "UMaskExt": "0x00c8a7fe",
-        "Unit": "CHA"
+        "PortMask": "0x0020",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c887fe01",
-        "UMaskExt": "0x00c887fe",
-        "Unit": "CHA"
+        "PortMask": "0x0040",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; ITOM hits from local IO",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00cc43fd04",
-        "UMaskExt": "0x00cc43fd",
-        "Unit": "CHA"
+        "PortMask": "0x0080",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; RFO hits from local IO",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO",
+        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c803fd04",
-        "UMaskExt": "0x00c803fd",
-        "Unit": "CHA"
+        "PortMask": "0x0001",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; ItoM from local IO",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO",
+        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c803ff04",
-        "UMaskExt": "0x00c803ff",
-        "Unit": "CHA"
+        "PortMask": "0x0002",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; ITOM from local IO",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM",
+        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00cc43ff04",
-        "UMaskExt": "0x00cc43ff",
-        "Unit": "CHA"
+        "PortMask": "0x0004",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; RFO from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO",
+        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c807ff01",
-        "UMaskExt": "0x00c807ff",
-        "Unit": "CHA"
+        "PortMask": "0x0008",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; RFO prefetch from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c887ff01",
-        "UMaskExt": "0x00c887ff",
-        "Unit": "CHA"
+        "PortMask": "0x0010",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; LLCPrefRFO from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00ccc7ff01",
-        "UMaskExt": "0x00ccc7ff",
-        "Unit": "CHA"
+        "PortMask": "0x0020",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; DRd from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c817ff01",
-        "UMaskExt": "0x00c817ff",
-        "Unit": "CHA"
+        "PortMask": "0x0040",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; DRd Opt from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c827ff01",
-        "UMaskExt": "0x00c827ff",
-        "Unit": "CHA"
+        "PortMask": "0x0080",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; DRd Opt Pref from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF",
+        "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c8a7ff01",
-        "UMaskExt": "0x00c8a7ff",
-        "Unit": "CHA"
+        "PortMask": "0x0001",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; CRd from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD",
+        "BriefDescription": "Read request for up to a 64 byte transaction is  made by IIO Part1 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c80fff01",
-        "UMaskExt": "0x00c80fff",
-        "Unit": "CHA"
+        "PortMask": "0x0002",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; CRd Pref from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF",
+        "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c88fff01",
-        "UMaskExt": "0x00c88fff",
-        "Unit": "CHA"
+        "PortMask": "0x0004",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; DRd Pref from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF",
+        "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c897ff01",
-        "UMaskExt": "0x00c897ff",
-        "Unit": "CHA"
+        "PortMask": "0x0008",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00C896FE01",
-        "UMaskExt": "0x00C896FE",
-        "Unit": "CHA"
+        "PortMask": "0x0010",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00C8977E01",
-        "UMaskExt": "0x00C8977E",
-        "Unit": "CHA"
+        "PortMask": "0x0020",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; RFO misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c806fe01",
-        "UMaskExt": "0x00c806fe",
-        "Unit": "CHA"
+        "PortMask": "0x0040",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; RFO misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c8077e01",
-        "UMaskExt": "0x00c8077e",
-        "Unit": "CHA"
+        "PortMask": "0x0080",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL",
+        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c886fe01",
-        "UMaskExt": "0x00c886fe",
-        "Unit": "CHA"
+        "PortMask": "0x0001",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE",
+        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c8877e01",
-        "UMaskExt": "0x00c8877e",
-        "Unit": "CHA"
+        "PortMask": "0x0002",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "All LLC lines in E state that are victimized on a fill",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E",
+        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x0000000002",
-        "UMaskExt": "0x00000000",
-        "Unit": "CHA"
+        "PortMask": "0x0004",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "All LLC lines in M state that are victimized on a fill",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M",
+        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x0000000001",
-        "UMaskExt": "0x00000000",
-        "Unit": "CHA"
+        "PortMask": "0x0008",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "All LLC lines in S state that are victimized on a fill",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x0000000004",
-        "UMaskExt": "0x00000000",
-        "Unit": "CHA"
+        "PortMask": "0x0010",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00cd43fd04",
-        "UMaskExt": "0x00cd43fd",
-        "Unit": "CHA"
+        "PortMask": "0x0020",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00cd43fe04",
-        "UMaskExt": "0x00cd43fe",
-        "Unit": "CHA"
+        "PortMask": "0x0040",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c837fe01",
-        "UMaskExt": "0x00c837fe",
-        "Unit": "CHA"
+        "PortMask": "0x0080",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c837fd01",
-        "UMaskExt": "0x00c837fd",
-        "Unit": "CHA"
+        "PortMask": "0x0001",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c837ff01",
-        "UMaskExt": "0x00c837ff",
-        "Unit": "CHA"
+        "PortMask": "0x0002",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core.  Non Modified Write Backs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0xcc3fff01",
-        "UMaskExt": "0xcc3fff",
-        "Unit": "CHA"
+        "PortMask": "0x0004",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; RdCur and FsRdCur hits from local IO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c8f3fd04",
-        "UMaskExt": "0x00c8f3fd",
-        "Unit": "CHA"
+        "PortMask": "0x0008",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; RdCur and FsRdCur misses from local IO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c8f3fe04",
-        "UMaskExt": "0x00c8f3fe",
-        "Unit": "CHA"
+        "PortMask": "0x0010",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; RdCur and FsRdCur hits from local IO",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c8f3fd04",
-        "UMaskExt": "0x00c8f3fd",
-        "Unit": "CHA"
+        "PortMask": "0x0020",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; RdCur and FsRdCur misses from local IO",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c8f3fe04",
-        "UMaskExt": "0x00c8f3fe",
-        "Unit": "CHA"
+        "PortMask": "0x0040",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; RdCur and FsRdCur from local IO",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x00c8f3ff04",
-        "UMaskExt": "0x00c8f3ff",
-        "Unit": "CHA"
+        "PortMask": "0x0080",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
-    {
-        "BriefDescription": "TOR Inserts; LLCPrefCode hits from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE",
+    {
+        "BriefDescription": "IRP Clockticks",
+        "EventCode": "0x01",
+        "EventName": "UNC_I_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x00cccffd01",
-        "UMaskExt": "0x00cccffd",
-        "Unit": "CHA"
+        "PublicDescription": "Number of IRP clock cycles while the event is enabled",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "TOR Inserts; LLCPrefData hits from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA",
+        "BriefDescription": "FAF - request insert from TC.",
+        "EventCode": "0x18",
+        "EventName": "UNC_I_FAF_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x00ccd7fd01",
-        "UMaskExt": "0x00ccd7fd",
-        "Unit": "CHA"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "TOR Inserts; LLCPrefData from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA",
+        "BriefDescription": "FAF occupancy",
+        "EventCode": "0x19",
+        "EventName": "UNC_I_FAF_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x00ccd7ff01",
-        "UMaskExt": "0x00ccd7ff",
-        "Unit": "CHA"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "TOR Inserts; LLCPrefCode misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE",
+        "BriefDescription": "FAF allocation -- sent to ADQ",
+        "EventCode": "0x16",
+        "EventName": "UNC_I_FAF_TRANSACTIONS",
         "PerPkg": "1",
-        "UMask": "0x00cccffe01",
-        "UMaskExt": "0x00cccffe",
-        "Unit": "CHA"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "TOR Inserts; LLCPrefData misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA",
+        "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)",
+        "EventCode": "0x20",
+        "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x00ccd7fe01",
-        "UMaskExt": "0x00ccd7fe",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "TOR Occupancy; LLCPrefCode hits from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE",
+        "BriefDescription": "Misc Events - Set 1 : Lost Forward",
+        "EventCode": "0x1f",
+        "EventName": "UNC_I_MISC1.LOST_FWD",
         "PerPkg": "1",
-        "UMask": "0x00cccffd01",
-        "UMaskExt": "0x00cccffd",
-        "Unit": "CHA"
+        "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed",
+        "UMask": "0x10",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "TOR Occupancy; LLCPrefData hits from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA",
+        "BriefDescription": "Inbound write (fast path) requests received by the IRP.",
+        "EventCode": "0x11",
+        "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
         "PerPkg": "1",
-        "UMask": "0x00ccd7fd01",
-        "UMaskExt": "0x00ccd7fd",
-        "Unit": "CHA"
+        "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.",
+        "UMask": "0x8",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "TOR Occupancy; LLCPrefData from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA",
+        "BriefDescription": "M2M Clockticks",
+        "EventCode": "0x01",
+        "EventName": "UNC_M2M_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x00ccd7ff01",
-        "UMaskExt": "0x00ccd7ff",
-        "Unit": "CHA"
+        "PublicDescription": "Clockticks of the mesh to memory (M2M)",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Occupancy; LLCPrefCode misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE",
+        "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled",
+        "EventCode": "0x17",
+        "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
         "PerPkg": "1",
-        "UMask": "0x00cccffe01",
-        "UMaskExt": "0x00cccffe",
-        "Unit": "CHA"
+        "UMask": "0x7",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Occupancy; LLCPrefData misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA",
+        "BriefDescription": "Messages sent direct to core (bypassing the CHA)",
+        "EventCode": "0x16",
+        "EventName": "UNC_M2M_DIRECT2CORE_TAKEN",
         "PerPkg": "1",
-        "UMask": "0x00ccd7fe01",
-        "UMaskExt": "0x00ccd7fe",
-        "Unit": "CHA"
+        "UMask": "0x7",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts; LLCPrefCode from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE",
+        "BriefDescription": "Number of reads in which direct to core transaction were overridden",
+        "EventCode": "0x18",
+        "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
         "PerPkg": "1",
-        "UMask": "0x00cccfff01",
-        "UMaskExt": "0x00cccfff",
-        "Unit": "CHA"
+        "UMask": "0x3",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Occupancy; LLCPrefCode from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE",
+        "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden",
+        "EventCode": "0x1b",
+        "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS",
         "PerPkg": "1",
-        "UMask": "0x00cccfff01",
-        "UMaskExt": "0x00cccfff",
-        "Unit": "CHA"
+        "UMask": "0x7",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM",
+        "BriefDescription": "Cycles when direct to Intel UPI was disabled",
+        "EventCode": "0x1a",
+        "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
         "PerPkg": "1",
-        "UMask": "0x00c8168a01",
-        "UMaskExt": "0x00c8168a",
-        "Unit": "CHA"
+        "UMask": "0x7",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM",
+        "BriefDescription": "Messages sent direct to the Intel UPI",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2M_DIRECT2UPI_TAKEN",
         "PerPkg": "1",
-        "UMask": "0x00c8170a01",
-        "UMaskExt": "0x00c8170a",
-        "Unit": "CHA"
+        "UMask": "0x7",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR",
+        "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden",
+        "EventCode": "0x1c",
+        "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE",
         "PerPkg": "1",
-        "UMask": "0x00c8168601",
-        "UMaskExt": "0x00c81686",
-        "Unit": "CHA"
+        "UMask": "0x3",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR",
+        "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)",
+        "EventCode": "0x20",
+        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY",
         "PerPkg": "1",
-        "UMask": "0x00c8170601",
-        "UMaskExt": "0x00c81706",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_PMM",
+        "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)",
+        "EventCode": "0x20",
+        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A",
         "PerPkg": "1",
-        "UMask": "0x00C8978A01",
-        "UMaskExt": "0x00C8978A",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_PMM",
+        "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)",
+        "EventCode": "0x20",
+        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I",
         "PerPkg": "1",
-        "UMask": "0x00C8968A01",
-        "UMaskExt": "0x00C8968A",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_PMM",
+        "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)",
+        "EventCode": "0x20",
+        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S",
         "PerPkg": "1",
-        "UMask": "0x00C8970A01",
-        "UMaskExt": "0x00C8970A",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_DDR",
+        "BriefDescription": "Multi-socket cacheline Directory update from A to I",
+        "EventCode": "0x21",
+        "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I",
         "PerPkg": "1",
-        "UMask": "0x00C8978601",
-        "UMaskExt": "0x00C89786",
-        "Unit": "CHA"
+        "UMask": "0x320",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_DDR",
+        "BriefDescription": "Multi-socket cacheline Directory update from A to S",
+        "EventCode": "0x21",
+        "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S",
         "PerPkg": "1",
-        "UMask": "0x00C8968601",
-        "UMaskExt": "0x00C89686",
-        "Unit": "CHA"
+        "UMask": "0x340",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_DDR",
+        "BriefDescription": "Multi-socket cacheline Directory update from/to Any state",
+        "EventCode": "0x21",
+        "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY",
         "PerPkg": "1",
-        "UMask": "0x00C8970601",
-        "UMaskExt": "0x00C89706",
-        "Unit": "CHA"
+        "UMask": "0x301",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL",
+        "BriefDescription": "Multi-socket cacheline Directory update from I to A",
+        "EventCode": "0x21",
+        "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A",
         "PerPkg": "1",
-        "UMask": "0x00C80EFE01",
-        "UMaskExt": "0x00C80EFE",
-        "Unit": "CHA"
+        "UMask": "0x304",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE",
+        "BriefDescription": "Multi-socket cacheline Directory update from I to S",
+        "EventCode": "0x21",
+        "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S",
         "PerPkg": "1",
-        "UMask": "0x00C80F7E01",
-        "UMaskExt": "0x00C80F7E",
-        "Unit": "CHA"
+        "UMask": "0x302",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL",
+        "BriefDescription": "Multi-socket cacheline Directory update from S to A",
+        "EventCode": "0x21",
+        "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A",
         "PerPkg": "1",
-        "UMask": "0x00C88EFE01",
-        "UMaskExt": "0x00C88EFE",
-        "Unit": "CHA"
+        "UMask": "0x310",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE",
+        "BriefDescription": "Multi-socket cacheline Directory update from S to I",
+        "EventCode": "0x21",
+        "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I",
         "PerPkg": "1",
-        "UMask": "0x00C88F7E01",
-        "UMaskExt": "0x00C88F7E",
-        "Unit": "CHA"
+        "UMask": "0x308",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR",
+        "BriefDescription": "UNC_M2M_IMC_READS.TO_PMM",
+        "EventCode": "0x24",
+        "EventName": "UNC_M2M_IMC_READS.TO_PMM",
         "PerPkg": "1",
-        "UMask": "0x00CD47FF01",
-        "UMaskExt": "0x00CD47FF",
-        "Unit": "CHA"
+        "UMask": "0x320",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI",
+        "BriefDescription": "PMM - All Channels",
+        "EventCode": "0x25",
+        "EventName": "UNC_M2M_IMC_WRITES.TO_PMM",
         "PerPkg": "1",
-        "UMask": "0x00cc27ff01",
-        "UMaskExt": "0x00cc27ff",
-        "Unit": "CHA"
+        "UMask": "0x1880",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM",
+        "BriefDescription": "Data Prefetches Dropped",
+        "EventCode": "0x58",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_UPI",
         "PerPkg": "1",
-        "UMask": "0x00CC47FD01",
-        "UMaskExt": "0x00CC47FD",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM",
+        "BriefDescription": "Data Prefetches Dropped",
+        "EventCode": "0x58",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT",
         "PerPkg": "1",
-        "UMask": "0x00CC47FE01",
-        "UMaskExt": "0x00CC47FE",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF",
+        "BriefDescription": "Data Prefetches Dropped",
+        "EventCode": "0x58",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_UPI",
         "PerPkg": "1",
-        "UMask": "0x00C877DE01",
-        "UMaskExt": "0x00C877DE",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL",
+        "BriefDescription": "Data Prefetches Dropped",
+        "EventCode": "0x58",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT",
         "PerPkg": "1",
-        "UMask": "0x00C87FDE01",
-        "UMaskExt": "0x00C87FDE",
-        "Unit": "CHA"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF",
+        "BriefDescription": "Data Prefetches Dropped",
+        "EventCode": "0x58",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH",
         "PerPkg": "1",
-        "UMask": "0x00C867FF01",
-        "UMaskExt": "0x00C867FF",
-        "Unit": "CHA"
+        "UMask": "0x5",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF",
+        "BriefDescription": ": UPI - All Channels",
+        "EventCode": "0x5d",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.UPI_ALLCH",
         "PerPkg": "1",
-        "UMask": "0x00C867FE01",
-        "UMaskExt": "0x00C867FE",
-        "Unit": "CHA"
+        "UMask": "0xa",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM",
+        "BriefDescription": ": XPT - All Channels",
+        "EventCode": "0x5d",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPT_ALLCH",
         "PerPkg": "1",
-        "UMask": "0x00C8678A01",
-        "UMaskExt": "0x00C8678A",
-        "Unit": "CHA"
+        "UMask": "0x5",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM",
+        "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels",
+        "EventCode": "0x56",
+        "EventName": "UNC_M2M_PREFCAM_INSERTS.UPI_ALLCH",
         "PerPkg": "1",
-        "UMask": "0x00C8668A01",
-        "UMaskExt": "0x00C8668A",
-        "Unit": "CHA"
+        "UMask": "0xa",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM",
+        "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels",
+        "EventCode": "0x56",
+        "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH",
         "PerPkg": "1",
-        "UMask": "0x00C8670A01",
-        "UMaskExt": "0x00C8670A",
-        "Unit": "CHA"
+        "PublicDescription": "Prefetch CAM Inserts : XPT -All Channels",
+        "UMask": "0x5",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR",
+        "BriefDescription": "AD Ingress (from CMS) : AD Ingress (from CMS) Allocations",
+        "EventCode": "0x02",
+        "EventName": "UNC_M2M_RxC_AD_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x00C8678601",
-        "UMaskExt": "0x00C86786",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR",
+        "BriefDescription": "AD Ingress (from CMS) Occupancy",
+        "EventCode": "0x03",
+        "EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x00C8668601",
-        "UMaskExt": "0x00C86686",
-        "Unit": "CHA"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR",
+        "BriefDescription": "Tracker Inserts : Channel 0",
+        "EventCode": "0x32",
+        "EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
         "PerPkg": "1",
-        "UMask": "0x00C8670601",
-        "UMaskExt": "0x00C86706",
-        "Unit": "CHA"
+        "UMask": "0x104",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL",
+        "BriefDescription": "Tracker Inserts : Channel 1",
+        "EventCode": "0x32",
+        "EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
         "PerPkg": "1",
-        "UMask": "0x00C86FFF01",
-        "UMaskExt": "0x00C86FFF",
-        "Unit": "CHA"
+        "UMask": "0x204",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL",
+        "BriefDescription": "Tracker Occupancy : Channel 0",
+        "EventCode": "0x33",
+        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
         "PerPkg": "1",
-        "UMask": "0x00C86FFE01",
-        "UMaskExt": "0x00C86FFE",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM",
+        "BriefDescription": "Tracker Occupancy : Channel 1",
+        "EventCode": "0x33",
+        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
         "PerPkg": "1",
-        "UMask": "0x00C86F8A01",
-        "UMaskExt": "0x00C86F8A",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM",
+        "BriefDescription": "M2P Clockticks",
+        "EventCode": "0x01",
+        "EventName": "UNC_M2P_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x00C86E8A01",
-        "UMaskExt": "0x00C86E8A",
-        "Unit": "CHA"
+        "PublicDescription": "Number of M2P clock cycles while the event is enabled",
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM",
+        "BriefDescription": "CMS Clockticks",
+        "EventCode": "0xc0",
+        "EventName": "UNC_M2P_CMS_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x00C86F0A01",
-        "UMaskExt": "0x00C86F0A",
-        "Unit": "CHA"
+        "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR",
+        "BriefDescription": "M3UPI Clockticks",
+        "EventCode": "0x01",
+        "EventName": "UNC_M3UPI_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x00C86F8601",
-        "UMaskExt": "0x00C86F86",
-        "Unit": "CHA"
+        "PublicDescription": "Number of M2UPI clock cycles while the event is enabled",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR",
+        "BriefDescription": "M3UPI CMS Clockticks",
+        "EventCode": "0xc0",
+        "EventName": "UNC_M3UPI_CMS_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x00C86E8601",
-        "UMaskExt": "0x00C86E86",
-        "Unit": "CHA"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR",
+        "BriefDescription": "D2C Sent",
+        "EventCode": "0x2b",
+        "EventName": "UNC_M3UPI_D2C_SENT",
         "PerPkg": "1",
-        "UMask": "0x00C86F0601",
-        "UMaskExt": "0x00C86F06",
-        "Unit": "CHA"
+        "PublicDescription": "D2C Sent : Count cases BL sends direct to core",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI",
+        "BriefDescription": "D2U Sent",
+        "EventCode": "0x2a",
+        "EventName": "UNC_M3UPI_D2U_SENT",
         "PerPkg": "1",
-        "UMask": "0x00CC23FF04",
-        "UMaskExt": "0x00CC23FF",
-        "Unit": "CHA"
+        "PublicDescription": "D2U Sent : Cases where SMI3 sends D2U command",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH",
+        "BriefDescription": "FlowQ Generated Prefetch",
+        "EventCode": "0x29",
+        "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN",
         "PerPkg": "1",
-        "UMask": "0x00C8C3FF04",
-        "UMaskExt": "0x00C8C3FF",
-        "Unit": "CHA"
+        "PublicDescription": "FlowQ Generated Prefetch : Count cases where FlowQ causes spawn of Prefetch to iMC/SMI3 target",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM",
+        "BriefDescription": "UPI Clockticks",
+        "EventCode": "0x01",
+        "EventName": "UNC_UPI_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x00c8168a01",
-        "UMaskExt": "0x00c8168a",
-        "Unit": "CHA"
+        "PublicDescription": "Number of UPI LL clock cycles while the event is enabled",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM",
+        "BriefDescription": "Direct packet attempts : D2C",
+        "EventCode": "0x12",
+        "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C",
         "PerPkg": "1",
-        "UMask": "0x00c8170a01",
-        "UMaskExt": "0x00c8170a",
-        "Unit": "CHA"
+        "PublicDescription": "Direct packet attempts : D2C : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on.  There are 4 mutually exclusive filters.  Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases.  Note that this does not count packets that are not candidates for Direct2Core.  The only candidates for Direct2Core are DRS packets destined for Cbos.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR",
+        "BriefDescription": "Cycles in L1",
+        "EventCode": "0x21",
+        "EventName": "UNC_UPI_L1_POWER_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x00c8168601",
-        "UMaskExt": "0x00c81686",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode.  L1 is a mode that totally shuts down a UPI link.  Use edge detect to count the number of instances when the UPI link entered L1.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR",
+        "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass",
+        "EventCode": "0x05",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
         "PerPkg": "1",
-        "UMask": "0x00c8170601",
-        "UMaskExt": "0x00c81706",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0xe",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_PMM",
+        "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode",
+        "EventCode": "0x05",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
         "PerPkg": "1",
-        "UMask": "0x00c8978a01",
-        "UMaskExt": "0x00c8978a",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x10e",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_PMM",
+        "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard",
+        "EventCode": "0x05",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
         "PerPkg": "1",
-        "UMask": "0x00c8968a01",
-        "UMaskExt": "0x00c8968a",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0xf",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_PMM",
+        "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode",
+        "EventCode": "0x05",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
         "PerPkg": "1",
-        "UMask": "0x00c8970a01",
-        "UMaskExt": "0x00c8970a",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x10f",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_DDR",
+        "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 0",
+        "EventCode": "0x31",
+        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0",
         "PerPkg": "1",
-        "UMask": "0x00c8978601",
-        "UMaskExt": "0x00c89786",
-        "Unit": "CHA"
+        "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 0 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_DDR",
+        "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 1",
+        "EventCode": "0x31",
+        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1",
         "PerPkg": "1",
-        "UMask": "0x00c8968601",
-        "UMaskExt": "0x00c89686",
-        "Unit": "CHA"
+        "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 1 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_DDR",
+        "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 2",
+        "EventCode": "0x31",
+        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2",
         "PerPkg": "1",
-        "UMask": "0x00c8970601",
-        "UMaskExt": "0x00c89706",
-        "Unit": "CHA"
+        "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 2 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL",
+        "BriefDescription": "Valid Flits Received : All Data",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
         "PerPkg": "1",
-        "UMask": "0x00c80efe01",
-        "UMaskExt": "0x00c80efe",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c).",
+        "UMask": "0xf",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE",
+        "BriefDescription": "Null FLITs received from any slot",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
         "PerPkg": "1",
-        "UMask": "0x00c80f7e01",
-        "UMaskExt": "0x00c80f7e",
-        "Unit": "CHA"
+        "UMask": "0x27",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL",
+        "BriefDescription": "Valid Flits Received : Data",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.DATA",
         "PerPkg": "1",
-        "UMask": "0x00c88efe01",
-        "UMaskExt": "0x00c88efe",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Received : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE",
+        "BriefDescription": "Valid Flits Received : Idle",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.IDLE",
         "PerPkg": "1",
-        "UMask": "0x00c88f7e01",
-        "UMaskExt": "0x00c88f7e",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Received : Idle : Shows legal flit time (hides impact of L0p and L0c).",
+        "UMask": "0x47",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH",
+        "BriefDescription": "Valid Flits Received : LLCRD Not Empty",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.LLCRD",
         "PerPkg": "1",
-        "UMask": "0x00c8c7ff01",
-        "UMaskExt": "0x00c8c7ff",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Received : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
+        "UMask": "0x10",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT",
+        "BriefDescription": "Valid Flits Received : LLCTRL",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.LLCTRL",
         "PerPkg": "1",
-        "UMask": "0x00c8d7ff01",
-        "UMaskExt": "0x00c8d7ff",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Received : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet.  Enables counting of slot 0 LLCTRL messages.",
+        "UMask": "0x40",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR",
+        "BriefDescription": "Valid Flits Received : All Non Data",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
         "PerPkg": "1",
-        "UMask": "0x00cd47ff01",
-        "UMaskExt": "0x00cd47ff",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c).",
+        "UMask": "0x97",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM",
+        "BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Empty",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.NULL",
         "PerPkg": "1",
-        "UMask": "0x00cc57ff01",
-        "UMaskExt": "0x00cc57ff",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Received : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.",
+        "UMask": "0x20",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI",
+        "BriefDescription": "Valid Flits Received : Protocol Header",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.PROTHDR",
         "PerPkg": "1",
-        "UMask": "0x00cc27ff01",
-        "UMaskExt": "0x00cc27ff",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Received : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
+        "UMask": "0x80",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM",
+        "BriefDescription": "Valid Flits Received : Slot 0",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.SLOT0",
         "PerPkg": "1",
-        "UMask": "0x00cc47ff01",
-        "UMaskExt": "0x00cc47ff",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Received : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM",
+        "BriefDescription": "Valid Flits Received : Slot 1",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.SLOT1",
         "PerPkg": "1",
-        "UMask": "0x00cc47fd01",
-        "UMaskExt": "0x00cc47fd",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Received : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM",
+        "BriefDescription": "Valid Flits Received : Slot 2",
+        "EventCode": "0x03",
+        "EventName": "UNC_UPI_RxL_FLITS.SLOT2",
         "PerPkg": "1",
-        "UMask": "0x00cc47fe01",
-        "UMaskExt": "0x00cc47fe",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Received : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.",
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF",
+        "BriefDescription": "RxQ Flit Buffer Allocations : Slot 0",
+        "EventCode": "0x30",
+        "EventName": "UNC_UPI_RxL_INSERTS.SLOT0",
         "PerPkg": "1",
-        "UMask": "0x00c877de01",
-        "UMaskExt": "0x00c877de",
-        "Unit": "CHA"
+        "PublicDescription": "RxQ Flit Buffer Allocations : Slot 0 : Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL",
+        "BriefDescription": "RxQ Flit Buffer Allocations : Slot 1",
+        "EventCode": "0x30",
+        "EventName": "UNC_UPI_RxL_INSERTS.SLOT1",
         "PerPkg": "1",
-        "UMask": "0x00c87fde01",
-        "UMaskExt": "0x00c87fde",
-        "Unit": "CHA"
+        "PublicDescription": "RxQ Flit Buffer Allocations : Slot 1 : Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF",
+        "BriefDescription": "RxQ Flit Buffer Allocations : Slot 2",
+        "EventCode": "0x30",
+        "EventName": "UNC_UPI_RxL_INSERTS.SLOT2",
         "PerPkg": "1",
-        "UMask": "0x00c867ff01",
-        "UMaskExt": "0x00c867ff",
-        "Unit": "CHA"
+        "PublicDescription": "RxQ Flit Buffer Allocations : Slot 2 : Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF",
+        "BriefDescription": "RxQ Occupancy - All Packets : Slot 0",
+        "EventCode": "0x32",
+        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0",
         "PerPkg": "1",
-        "UMask": "0x00c867fe01",
-        "UMaskExt": "0x00c867fe",
-        "Unit": "CHA"
+        "PublicDescription": "RxQ Occupancy - All Packets : Slot 0 : Accumulates the number of elements in the UPI RxQ in each cycle.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM",
+        "BriefDescription": "RxQ Occupancy - All Packets : Slot 1",
+        "EventCode": "0x32",
+        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1",
         "PerPkg": "1",
-        "UMask": "0x00c8678a01",
-        "UMaskExt": "0x00c8678a",
-        "Unit": "CHA"
+        "PublicDescription": "RxQ Occupancy - All Packets : Slot 1 : Accumulates the number of elements in the UPI RxQ in each cycle.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM",
+        "BriefDescription": "RxQ Occupancy - All Packets : Slot 2",
+        "EventCode": "0x32",
+        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2",
         "PerPkg": "1",
-        "UMask": "0x00c8668a01",
-        "UMaskExt": "0x00c8668a",
-        "Unit": "CHA"
+        "PublicDescription": "RxQ Occupancy - All Packets : Slot 2 : Accumulates the number of elements in the UPI RxQ in each cycle.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM",
+        "BriefDescription": "Cycles in L0p",
+        "EventCode": "0x27",
+        "EventName": "UNC_UPI_TxL0P_POWER_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x00c8670a01",
-        "UMaskExt": "0x00c8670a",
-        "Unit": "CHA"
+        "PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses.  Use edge detect to count the number of instances when the UPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR",
+        "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass",
+        "EventCode": "0x04",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
         "PerPkg": "1",
-        "UMask": "0x00c8678601",
-        "UMaskExt": "0x00c86786",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0xe",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR",
+        "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode",
+        "EventCode": "0x04",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
         "PerPkg": "1",
-        "UMask": "0x00c8668601",
-        "UMaskExt": "0x00c86686",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x10e",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR",
+        "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard",
+        "EventCode": "0x04",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
         "PerPkg": "1",
-        "UMask": "0x00c8670601",
-        "UMaskExt": "0x00c86706",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0xf",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL",
+        "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode",
+        "EventCode": "0x04",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
         "PerPkg": "1",
-        "UMask": "0x00c86fff01",
-        "UMaskExt": "0x00c86fff",
-        "Unit": "CHA"
+        "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+        "UMask": "0x10f",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL",
+        "BriefDescription": "Tx Flit Buffer Bypassed",
+        "EventCode": "0x41",
+        "EventName": "UNC_UPI_TxL_BYPASSED",
         "PerPkg": "1",
-        "UMask": "0x00c86ffe01",
-        "UMaskExt": "0x00c86ffe",
-        "Unit": "CHA"
+        "PublicDescription": "Tx Flit Buffer Bypassed : Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the UPI Link. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM",
+        "BriefDescription": "Valid Flits Sent : All Data",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
         "PerPkg": "1",
-        "UMask": "0x00c86f8a01",
-        "UMaskExt": "0x00c86f8a",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Sent : All Data : Counts number of data flits across this UPI link.",
+        "UMask": "0xf",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM",
+        "BriefDescription": "All Null Flits",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
         "PerPkg": "1",
-        "UMask": "0x00c86e8a01",
-        "UMaskExt": "0x00c86e8a",
-        "Unit": "CHA"
+        "UMask": "0x27",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM",
+        "BriefDescription": "Valid Flits Sent : Data",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.DATA",
         "PerPkg": "1",
-        "UMask": "0x00c86f0a01",
-        "UMaskExt": "0x00c86f0a",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Sent : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR",
+        "BriefDescription": "Valid Flits Sent : Idle",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.IDLE",
         "PerPkg": "1",
-        "UMask": "0x00c86f8601",
-        "UMaskExt": "0x00c86f86",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Sent : Idle : Shows legal flit time (hides impact of L0p and L0c).",
+        "UMask": "0x47",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR",
+        "BriefDescription": "Valid Flits Sent : LLCRD Not Empty",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.LLCRD",
         "PerPkg": "1",
-        "UMask": "0x00c86e8601",
-        "UMaskExt": "0x00c86e86",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Sent : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
+        "UMask": "0x10",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR",
+        "BriefDescription": "Valid Flits Sent : LLCTRL",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.LLCTRL",
         "PerPkg": "1",
-        "UMask": "0x00c86f0601",
-        "UMaskExt": "0x00c86f06",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Sent : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet.  Enables counting of slot 0 LLCTRL messages.",
+        "UMask": "0x40",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI",
+        "BriefDescription": "Valid Flits Sent : All Non Data",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
         "PerPkg": "1",
-        "UMask": "0x00cc23ff04",
-        "UMaskExt": "0x00cc23ff",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c).",
+        "UMask": "0x97",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Devices",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH",
+        "BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.NULL",
         "PerPkg": "1",
-        "UMask": "0x00c8c3ff04",
-        "UMaskExt": "0x00c8c3ff",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.",
+        "UMask": "0x20",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR",
+        "BriefDescription": "Valid Flits Sent : Protocol Header",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.PROTHDR",
         "PerPkg": "1",
-        "UMask": "0x00cd43fd04",
-        "UMaskExt": "0x00cd43fd",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Sent : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
+        "UMask": "0x80",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR",
+        "BriefDescription": "Valid Flits Sent : Slot 0",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.SLOT0",
         "PerPkg": "1",
-        "UMask": "0x00cd43fe04",
-        "UMaskExt": "0x00cd43fe",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Sent : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : PMM Access",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.PMM",
+        "BriefDescription": "Valid Flits Sent : Slot 1",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.SLOT1",
         "PerPkg": "1",
-        "UMaskExt": "0x00000008",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Sent : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : PMM Access",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.PMM",
+        "BriefDescription": "Valid Flits Sent : Slot 2",
+        "EventCode": "0x02",
+        "EventName": "UNC_UPI_TxL_FLITS.SLOT2",
         "PerPkg": "1",
-        "UMaskExt": "0x00000008",
-        "Unit": "CHA"
+        "PublicDescription": "Valid Flits Sent : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.",
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Occupancy : DDR Access",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR",
+        "BriefDescription": "Tx Flit Buffer Allocations",
+        "EventCode": "0x40",
+        "EventName": "UNC_UPI_TxL_INSERTS",
         "PerPkg": "1",
-        "UMaskExt": "0x00000004",
-        "Unit": "CHA"
+        "PublicDescription": "Tx Flit Buffer Allocations : Number of allocations into the UPI Tx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "TOR Inserts : DDR Access",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.DDR",
+        "BriefDescription": "Tx Flit Buffer Occupancy",
+        "EventCode": "0x42",
+        "EventName": "UNC_UPI_TxL_OCCUPANCY",
         "PerPkg": "1",
-        "UMaskExt": "0x00000004",
-        "Unit": "CHA"
+        "PublicDescription": "Tx Flit Buffer Occupancy : Accumulates the number of flits in the TxQ.  Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.",
+        "Unit": "UPI LL"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-power.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-power.json
index 6299afe544cbe..b1d5a605e0a75 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-power.json
@@ -1,12 +1,90 @@
 [
     {
         "BriefDescription": "PCU PCLK Clockticks",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x01",
         "EventName": "UNC_P_CLOCKTICKS",
         "PerPkg": "1",
-        "UMaskExt": "0x00000000",
+        "PublicDescription": "Number of PCU PCLK Clock cycles while the event is enabled",
+        "Unit": "PCU"
+    },
+    {
+        "BriefDescription": "Thermal Strongest Upper Limit Cycles",
+        "EventCode": "0x04",
+        "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
+        "PerPkg": "1",
+        "PublicDescription": "Thermal Strongest Upper Limit Cycles : Number of cycles any frequency is reduced due to a thermal limit.  Count only if throttling is occurring.",
+        "Unit": "PCU"
+    },
+    {
+        "BriefDescription": "Power Strongest Upper Limit Cycles",
+        "EventCode": "0x05",
+        "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
+        "PerPkg": "1",
+        "PublicDescription": "Power Strongest Upper Limit Cycles : Counts the number of cycles when power is the upper limit on frequency.",
+        "Unit": "PCU"
+    },
+    {
+        "BriefDescription": "Cycles spent changing Frequency",
+        "EventCode": "0x74",
+        "EventName": "UNC_P_FREQ_TRANS_CYCLES",
+        "PerPkg": "1",
+        "PublicDescription": "Cycles spent changing Frequency : Counts the number of cycles when the system is changing frequency.  This can not be filtered by thread ID.  One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
+        "Unit": "PCU"
+    },
+    {
+        "BriefDescription": "Package C State Residency - C2E",
+        "EventCode": "0x2b",
+        "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
+        "PerPkg": "1",
+        "PublicDescription": "Package C State Residency - C2E : Counts the number of cycles when the package was in C2E.  This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert).  Residency events do not include transition times.",
+        "Unit": "PCU"
+    },
+    {
+        "BriefDescription": "Package C State Residency - C6",
+        "EventCode": "0x2d",
+        "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
+        "PerPkg": "1",
+        "PublicDescription": "Package C State Residency - C6 : Counts the number of cycles when the package was in C6.  This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert).  Residency events do not include transition times.",
+        "Unit": "PCU"
+    },
+    {
+        "BriefDescription": "Number of cores in C0",
+        "EventCode": "0x35",
+        "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C0",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cores in C0 : This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
+        "Unit": "PCU"
+    },
+    {
+        "BriefDescription": "Number of cores in C3",
+        "EventCode": "0x36",
+        "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C3",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cores in C3 : This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
+        "Unit": "PCU"
+    },
+    {
+        "BriefDescription": "Number of cores in C6",
+        "EventCode": "0x37",
+        "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C6",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cores in C6 : This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
+        "Unit": "PCU"
+    },
+    {
+        "BriefDescription": "External Prochot",
+        "EventCode": "0x0a",
+        "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
+        "PerPkg": "1",
+        "PublicDescription": "External Prochot : Counts the number of cycles that we are in external PROCHOT mode.  This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
+        "Unit": "PCU"
+    },
+    {
+        "BriefDescription": "Internal Prochot",
+        "EventCode": "0x09",
+        "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
+        "PerPkg": "1",
+        "PublicDescription": "Internal Prochot : Counts the number of cycles that we are in Internal PROCHOT mode.  This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
         "Unit": "PCU"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/virtual-memory.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/virtual-memory.json
index f591f4fedc0b8..a1e3b8d2ebe79 100644
--- a/tools/perf/pmu-events/arch/x86/sapphirerapids/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/virtual-memory.json
@@ -1,245 +1,165 @@
 [
     {
         "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x12",
         "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0xe"
     },
     {
         "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x13",
         "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0xe"
     },
     {
         "BriefDescription": "Page walks completed due to a demand data store to a 1G page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x11",
         "EventName": "ITLB_MISSES.STLB_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x11",
         "EventName": "ITLB_MISSES.WALK_ACTIVE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x11",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0xe"
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x11",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x11",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x11",
         "EventName": "ITLB_MISSES.WALK_PENDING",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.",
         "SampleAfterValue": "100003",
-        "Speculative": "1",
         "UMask": "0x10"
     }
 ]
-- 
GitLab


From 1b91a994a2ac3cb374249b09bb818375267aea97 Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:55:03 -0800
Subject: [PATCH 587/875] perf vendor events intel: Refresh silvermont events

Update the silvermont events using the new tooling from:

  https://github.com/intel/perfmon

The events are unchanged but unused json values are removed. This
increases consistency across the json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-17-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../pmu-events/arch/x86/silvermont/cache.json | 133 ------------------
 .../arch/x86/silvermont/floating-point.json   |   1 -
 .../arch/x86/silvermont/frontend.json         |   8 --
 .../arch/x86/silvermont/memory.json           |   1 -
 .../pmu-events/arch/x86/silvermont/other.json |   2 -
 .../arch/x86/silvermont/pipeline.json         |  35 -----
 .../arch/x86/silvermont/virtual-memory.json   |   7 -
 7 files changed, 187 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/silvermont/cache.json b/tools/perf/pmu-events/arch/x86/silvermont/cache.json
index 7959504dff293..818e0664a3a62 100644
--- a/tools/perf/pmu-events/arch/x86/silvermont/cache.json
+++ b/tools/perf/pmu-events/arch/x86/silvermont/cache.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Counts the number of request that were not accepted into the L2Q because the L2Q is FULL.",
-        "Counter": "0,1",
         "EventCode": "0x31",
         "EventName": "CORE_REJECT_L2Q.ALL",
         "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q.  It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link.  The L2Q may also reject transactions  from a core to insure fairness between cores, or to delay a core?s dirty eviction when the address conflicts incoming external snoops.  (Note that L2 prefetcher requests that are dropped are not counted by this event.)",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
-        "Counter": "0,1",
         "EventCode": "0x86",
         "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES",
         "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss.  Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.\r\nCounts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes.  This will include cycles due to an ITLB miss, ICache miss and other events.",
@@ -18,7 +16,6 @@
     },
     {
         "BriefDescription": "Counts the number of request from the L2 that were not accepted into the XQ",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_XQ.ALL",
         "PublicDescription": "This event counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims).",
@@ -26,7 +23,6 @@
     },
     {
         "BriefDescription": "L2 cache request misses",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.MISS",
         "PublicDescription": "This event counts the total number of L2 cache references and the number of L2 cache misses respectively.",
@@ -35,7 +31,6 @@
     },
     {
         "BriefDescription": "L2 cache requests from this core",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
         "PublicDescription": "This event counts requests originating from the core that references a cache line in the L2 cache.",
@@ -44,7 +39,6 @@
     },
     {
         "BriefDescription": "All Loads",
-        "Counter": "0,1",
         "EventCode": "0x04",
         "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
         "PublicDescription": "This event counts the number of load ops retired.",
@@ -53,7 +47,6 @@
     },
     {
         "BriefDescription": "All Stores",
-        "Counter": "0,1",
         "EventCode": "0x04",
         "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
         "PublicDescription": "This event counts the number of store ops retired.",
@@ -62,7 +55,6 @@
     },
     {
         "BriefDescription": "Cross core or cross module hitm",
-        "Counter": "0,1",
         "EventCode": "0x04",
         "EventName": "MEM_UOPS_RETIRED.HITM",
         "PEBS": "1",
@@ -72,7 +64,6 @@
     },
     {
         "BriefDescription": "Loads missed L1",
-        "Counter": "0,1",
         "EventCode": "0x04",
         "EventName": "MEM_UOPS_RETIRED.L1_MISS_LOADS",
         "PublicDescription": "This event counts the number of load ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted.",
@@ -81,7 +72,6 @@
     },
     {
         "BriefDescription": "Loads hit L2",
-        "Counter": "0,1",
         "EventCode": "0x04",
         "EventName": "MEM_UOPS_RETIRED.L2_HIT_LOADS",
         "PEBS": "1",
@@ -91,7 +81,6 @@
     },
     {
         "BriefDescription": "Loads missed L2",
-        "Counter": "0,1",
         "EventCode": "0x04",
         "EventName": "MEM_UOPS_RETIRED.L2_MISS_LOADS",
         "PEBS": "1",
@@ -101,7 +90,6 @@
     },
     {
         "BriefDescription": "Loads missed UTLB",
-        "Counter": "0,1",
         "EventCode": "0x04",
         "EventName": "MEM_UOPS_RETIRED.UTLB_MISS",
         "PublicDescription": "This event counts the number of load ops retired that had UTLB miss.",
@@ -110,7 +98,6 @@
     },
     {
         "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
@@ -119,623 +106,510 @@
     },
     {
         "BriefDescription": "Counts any code reads (demand & prefetch) that have any response type.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010044",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any code reads (demand & prefetch) that miss L2.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1680000044",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any code reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000000044",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any code reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400000044",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any code reads (demand & prefetch) that miss L2 with a snoop miss response.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200000044",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any data read (demand & prefetch) that have any response type.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000013091",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any data read (demand & prefetch) that miss L2.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1680003091",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any data read (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000003091",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any data read (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400003091",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any data read (demand & prefetch) that miss L2 with a snoop miss response.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200003091",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any request that have any response type.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000018008",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any request that hit in the other module where modified copies were found in other core's L1 cache.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000008008",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400008008",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any request that miss L2 with a snoop miss response.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200008008",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any rfo reads (demand & prefetch) that have any response type.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010022",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1680000022",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any rfo reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000000022",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400000022",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2 with a snoop miss response.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200000022",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writeback (modified to exclusive) that miss L2.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1680000008",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts writeback (modified to exclusive) that miss L2 with no details on snoop-related information.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0080000008",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that have any response type.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010004",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1680000004",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400000004",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2 with a snoop miss response.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200000004",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000004",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand and DCU prefetch data read that have any response type.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000010001",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand and DCU prefetch data read that miss L2.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1680000001",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand and DCU prefetch data read that hit in the other module where modified copies were found in other core's L1 cache.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000000001",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand and DCU prefetch data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400000001",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand and DCU prefetch data read that miss L2 with a snoop miss response.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200000001",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand and DCU prefetch data read that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000001",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1680000002",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand and DCU prefetch RFOs that hit in the other module where modified copies were found in other core's L1 cache.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000000002",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400000002",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2 with a snoop miss response.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200000002",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand and DCU prefetch RFOs that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x4000000002",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads of partial cache lines (including UC and WC) that miss L2.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1680000080",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Countsof demand RFO requests to write to partial cache lines that miss L2.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1680000100",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts DCU hardware prefetcher data read that have any response type.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0000012000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts DCU hardware prefetcher data read that miss L2.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1680002000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts DCU hardware prefetcher data read that hit in the other module where modified copies were found in other core's L1 cache.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000002000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts DCU hardware prefetcher data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400002000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts DCU hardware prefetcher data read that miss L2 with a snoop miss response.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200002000",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1680000040",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400000040",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2 with a snoop miss response.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200000040",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1680000010",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000000010",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400000010",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2 with a snoop miss response.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200000010",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1680000020",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts RFO requests generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000000020",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0400000020",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2 with a snoop miss response.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x0200000020",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming store that miss L2.",
-        "Counter": "0,1",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1680004800",
-        "Offcore": "1",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Any reissued load uops",
-        "Counter": "0,1",
         "EventCode": "0x03",
         "EventName": "REHABQ.ANY_LD",
         "PublicDescription": "This event counts the number of load uops reissued from Rehabq.",
@@ -744,7 +618,6 @@
     },
     {
         "BriefDescription": "Any reissued store uops",
-        "Counter": "0,1",
         "EventCode": "0x03",
         "EventName": "REHABQ.ANY_ST",
         "PublicDescription": "This event counts the number of store uops reissued from Rehabq.",
@@ -753,7 +626,6 @@
     },
     {
         "BriefDescription": "Loads blocked due to store data not ready",
-        "Counter": "0,1",
         "EventCode": "0x03",
         "EventName": "REHABQ.LD_BLOCK_STD_NOTREADY",
         "PublicDescription": "This event counts the cases where a forward was technically possible, but did not occur because the store data was not available at the right time.",
@@ -762,7 +634,6 @@
     },
     {
         "BriefDescription": "Loads blocked due to store forward restriction",
-        "Counter": "0,1",
         "EventCode": "0x03",
         "EventName": "REHABQ.LD_BLOCK_ST_FORWARD",
         "PEBS": "1",
@@ -772,7 +643,6 @@
     },
     {
         "BriefDescription": "Load uops that split cache line boundary",
-        "Counter": "0,1",
         "EventCode": "0x03",
         "EventName": "REHABQ.LD_SPLITS",
         "PEBS": "1",
@@ -782,7 +652,6 @@
     },
     {
         "BriefDescription": "Uops with lock semantics",
-        "Counter": "0,1",
         "EventCode": "0x03",
         "EventName": "REHABQ.LOCK",
         "PublicDescription": "This event counts the number of retired memory operations with lock semantics. These are either implicit locked instructions such as the XCHG instruction or instructions with an explicit LOCK prefix (0xF0).",
@@ -791,7 +660,6 @@
     },
     {
         "BriefDescription": "Store address buffer full",
-        "Counter": "0,1",
         "EventCode": "0x03",
         "EventName": "REHABQ.STA_FULL",
         "PublicDescription": "This event counts the number of retired stores that are delayed because there is not a store address buffer available.",
@@ -800,7 +668,6 @@
     },
     {
         "BriefDescription": "Store uops that split cache line boundary",
-        "Counter": "0,1",
         "EventCode": "0x03",
         "EventName": "REHABQ.ST_SPLITS",
         "PublicDescription": "This event counts the number of retire stores that experienced cache line boundary splits.",
diff --git a/tools/perf/pmu-events/arch/x86/silvermont/floating-point.json b/tools/perf/pmu-events/arch/x86/silvermont/floating-point.json
index aa4faf1105129..f2b1e8f08d685 100644
--- a/tools/perf/pmu-events/arch/x86/silvermont/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/silvermont/floating-point.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Stalls due to FP assists",
-        "Counter": "0,1",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.FP_ASSIST",
         "PublicDescription": "This event counts the number of times that pipeline stalled due to FP operations needing assists.",
diff --git a/tools/perf/pmu-events/arch/x86/silvermont/frontend.json b/tools/perf/pmu-events/arch/x86/silvermont/frontend.json
index 43e5e48f7212f..c35da10f7133a 100644
--- a/tools/perf/pmu-events/arch/x86/silvermont/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/silvermont/frontend.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Counts the number of baclears",
-        "Counter": "0,1",
         "EventCode": "0xE6",
         "EventName": "BACLEARS.ALL",
         "PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end.  The BACLEARS.ANY event counts the number of baclears for any type of branch.",
@@ -10,7 +9,6 @@
     },
     {
         "BriefDescription": "Counts the number of JCC baclears",
-        "Counter": "0,1",
         "EventCode": "0xE6",
         "EventName": "BACLEARS.COND",
         "PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end.  The BACLEARS.COND event counts the number of JCC (Jump on Condtional Code) baclears.",
@@ -19,7 +17,6 @@
     },
     {
         "BriefDescription": "Counts the number of RETURN baclears",
-        "Counter": "0,1",
         "EventCode": "0xE6",
         "EventName": "BACLEARS.RETURN",
         "PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end.  The BACLEARS.RETURN event counts the number of RETURN baclears.",
@@ -28,7 +25,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction",
-        "Counter": "0,1",
         "EventCode": "0xE9",
         "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",
         "PublicDescription": "Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction.",
@@ -37,7 +33,6 @@
     },
     {
         "BriefDescription": "Instruction fetches",
-        "Counter": "0,1",
         "EventCode": "0x80",
         "EventName": "ICACHE.ACCESSES",
         "PublicDescription": "This event counts all instruction fetches, not including most uncacheable\r\nfetches.",
@@ -46,7 +41,6 @@
     },
     {
         "BriefDescription": "Instruction fetches from Icache",
-        "Counter": "0,1",
         "EventCode": "0x80",
         "EventName": "ICACHE.HIT",
         "PublicDescription": "This event counts all instruction fetches from the instruction cache.",
@@ -55,7 +49,6 @@
     },
     {
         "BriefDescription": "Icache miss",
-        "Counter": "0,1",
         "EventCode": "0x80",
         "EventName": "ICACHE.MISSES",
         "PublicDescription": "This event counts all instruction fetches that miss the Instruction cache or produce memory requests. This includes uncacheable fetches. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.",
@@ -64,7 +57,6 @@
     },
     {
         "BriefDescription": "Counts the number of times entered into a ucode flow in the FEC.  Includes inserted flows due to front-end detected faults or assists.  Speculative count.",
-        "Counter": "0,1",
         "EventCode": "0xE7",
         "EventName": "MS_DECODED.MS_ENTRY",
         "PublicDescription": "Counts the number of times the MSROM starts a flow of UOPS. It does not count every time a UOP is read from the microcode ROM.  The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine.  Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort.  The event will count MSROM startups for UOPS that are speculative, and subsequently cleared by branch mispredict or machine clear.  Background: UOPS are produced by two mechanisms.  Either they are generated by hardware that decodes instructions into UOPS, or they are delivered by a ROM (called the MSROM) that holds UOPS associated with a specific instruction.  MSROM UOPS might also be delivered in response to some condition such as a fault or other exceptional condition.  This event is an excellent mechanism for detecting instructions that require the use of MSROM instructions.",
diff --git a/tools/perf/pmu-events/arch/x86/silvermont/memory.json b/tools/perf/pmu-events/arch/x86/silvermont/memory.json
index 0f5fba43da4c1..15ea451872108 100644
--- a/tools/perf/pmu-events/arch/x86/silvermont/memory.json
+++ b/tools/perf/pmu-events/arch/x86/silvermont/memory.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Stalls due to Memory ordering",
-        "Counter": "0,1",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
         "PublicDescription": "This event counts the number of times that pipeline was cleared due to memory ordering issues.",
diff --git a/tools/perf/pmu-events/arch/x86/silvermont/other.json b/tools/perf/pmu-events/arch/x86/silvermont/other.json
index 4db59d84c144d..cff113adb8234 100644
--- a/tools/perf/pmu-events/arch/x86/silvermont/other.json
+++ b/tools/perf/pmu-events/arch/x86/silvermont/other.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Cycles code-fetch stalled due to any reason.",
-        "Counter": "0,1",
         "EventCode": "0x86",
         "EventName": "FETCH_STALL.ALL",
         "PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes.  This will include cycles due to an ITLB miss, ICache miss and other events.",
@@ -10,7 +9,6 @@
     },
     {
         "BriefDescription": "Cycles code-fetch stalled due to an outstanding ITLB miss.",
-        "Counter": "0,1",
         "EventCode": "0x86",
         "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES",
         "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss.  Note: this event is not the same as page walk cycles to retrieve an instruction translation.",
diff --git a/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json b/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json
index e42a37eabc174..59f6116a7eae4 100644
--- a/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Counts the number of branch instructions retired...",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
@@ -10,18 +9,15 @@
     },
     {
         "BriefDescription": "Counts the number of taken branch instructions retired",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES",
         "PEBS": "2",
-        "PEBScounters": "0,1",
         "PublicDescription": "ALL_TAKEN_BRANCHES counts the number of all taken branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.",
         "SampleAfterValue": "200003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Counts the number of near CALL branch instructions retired",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.CALL",
         "PEBS": "1",
@@ -31,7 +27,6 @@
     },
     {
         "BriefDescription": "Counts the number of far branch instructions retired",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.FAR_BRANCH",
         "PEBS": "1",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "Counts the number of near indirect CALL branch instructions retired",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.IND_CALL",
         "PEBS": "1",
@@ -51,7 +45,6 @@
     },
     {
         "BriefDescription": "Counts the number of JCC branch instructions retired",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.JCC",
         "PEBS": "1",
@@ -61,7 +54,6 @@
     },
     {
         "BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NON_RETURN_IND",
         "PEBS": "1",
@@ -71,7 +63,6 @@
     },
     {
         "BriefDescription": "Counts the number of near relative CALL branch instructions retired",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.REL_CALL",
         "PEBS": "1",
@@ -81,7 +72,6 @@
     },
     {
         "BriefDescription": "Counts the number of near RET branch instructions retired",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.RETURN",
         "PEBS": "1",
@@ -91,7 +81,6 @@
     },
     {
         "BriefDescription": "Counts the number of taken JCC branch instructions retired",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.TAKEN_JCC",
         "PEBS": "1",
@@ -101,7 +90,6 @@
     },
     {
         "BriefDescription": "Counts the number of mispredicted branch instructions retired",
-        "Counter": "0,1",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
@@ -110,7 +98,6 @@
     },
     {
         "BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired",
-        "Counter": "0,1",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.IND_CALL",
         "PEBS": "1",
@@ -120,7 +107,6 @@
     },
     {
         "BriefDescription": "Counts the number of mispredicted JCC branch instructions retired",
-        "Counter": "0,1",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.JCC",
         "PEBS": "1",
@@ -130,7 +116,6 @@
     },
     {
         "BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired",
-        "Counter": "0,1",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
         "PEBS": "1",
@@ -140,7 +125,6 @@
     },
     {
         "BriefDescription": "Counts the number of mispredicted near RET branch instructions retired",
-        "Counter": "0,1",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.RETURN",
         "PEBS": "1",
@@ -150,7 +134,6 @@
     },
     {
         "BriefDescription": "Counts the number of mispredicted taken JCC branch instructions retired",
-        "Counter": "0,1",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.TAKEN_JCC",
         "PEBS": "1",
@@ -160,7 +143,6 @@
     },
     {
         "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
-        "Counter": "Fixed counter 2",
         "EventName": "CPU_CLK_UNHALTED.CORE",
         "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios.  The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. In systems with a constant core frequency, this event can give you a measurement of the elapsed time while the core was not in halt state by dividing the event count by the core frequency. This event is architecturally defined and is a designated fixed counter.  CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time.  CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF.",
         "SampleAfterValue": "2000003",
@@ -168,7 +150,6 @@
     },
     {
         "BriefDescription": "Core cycles when core is not halted",
-        "Counter": "0,1",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.CORE_P",
         "PublicDescription": "This event counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time.",
@@ -176,7 +157,6 @@
     },
     {
         "BriefDescription": "Reference cycles when core is not halted",
-        "Counter": "0,1",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF",
         "PublicDescription": "This event counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.",
@@ -185,7 +165,6 @@
     },
     {
         "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
-        "Counter": "Fixed counter 3",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
         "PublicDescription": "Counts the number of reference cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios.  The core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  Divide this event count by core frequency to determine the elapsed time while the core was not in halt state.  Divide this event count by core frequency to determine the elapsed time while the core was not in halt state.  This event is architecturally defined and is a designated fixed counter.  CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time.  CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF.",
         "SampleAfterValue": "2000003",
@@ -193,7 +172,6 @@
     },
     {
         "BriefDescription": "Cycles the divider is busy.  Does not imply a stall waiting for the divider.",
-        "Counter": "0,1",
         "EventCode": "0xCD",
         "EventName": "CYCLES_DIV_BUSY.ALL",
         "PublicDescription": "Cycles the divider is busy.This event counts the cycles when the divide unit is unable to accept a new divide UOP because it is busy processing a previously dispatched UOP. The cycles will be counted irrespective of whether or not another divide UOP is waiting to enter the divide unit (from the RS). This event might count cycles while a divide is in progress even if the RS is empty.  The divide instruction is one of the longest latency instructions in the machine.  Hence, it has a special event associated with it to help determine if divides are delaying the retirement of instructions.",
@@ -202,7 +180,6 @@
     },
     {
         "BriefDescription": "Fixed Counter: Counts the number of instructions retired",
-        "Counter": "Fixed counter 1",
         "EventName": "INST_RETIRED.ANY",
         "PublicDescription": "This event counts the number of instructions that retire.  For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires.  The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps.  Background: Modern microprocessors employ extensive pipelining and speculative techniques.  Since sometimes an instruction is started but never completed, the notion of \"retirement\" is introduced.  A retired instruction is one that commits its states. Or stated differently, an instruction might be abandoned at some point. No instruction is truly finished until it retires.  This counter measures the number of completed instructions.  The fixed event is INST_RETIRED.ANY and the programmable event is INST_RETIRED.ANY_P.",
         "SampleAfterValue": "2000003",
@@ -210,7 +187,6 @@
     },
     {
         "BriefDescription": "Instructions retired",
-        "Counter": "0,1",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.ANY_P",
         "PublicDescription": "This event counts the number of instructions that retire execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers.",
@@ -218,7 +194,6 @@
     },
     {
         "BriefDescription": "Counts all machine clears",
-        "Counter": "0,1",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.ALL",
         "PublicDescription": "Machine clears happen when something happens in the machine that causes the hardware to need to take special care to get the right answer. When such a condition is signaled on an instruction, the front end of the machine is notified that it must restart, so no more instructions will be decoded from the current path.  All instructions \"older\" than this one will be allowed to finish.  This instruction and all \"younger\" instructions must be cleared, since they must not be allowed to complete.  Essentially, the hardware waits until the problematic instruction is the oldest instruction in the machine.  This means all older instructions are retired, and all pending stores (from older instructions) are completed.  Then the new path of instructions from the front end are allowed to start into the machine.  There are many conditions that might cause a machine clear (including the receipt of an interrupt, or a trap or a fault).  All those conditions (including but not limited to MACHINE_CLEARS.MEMORY_ORDERING, MACHINE_CLEARS.SMC, and MACHINE_CLEARS.FP_ASSIST) are captured in the ANY event. In addition, some conditions can be specifically counted (i.e. SMC, MEMORY_ORDERING, FP_ASSIST).  However, the sum of SMC, MEMORY_ORDERING, and FP_ASSIST machine clears will not necessarily equal the number of ANY.",
@@ -227,7 +202,6 @@
     },
     {
         "BriefDescription": "Self-Modifying Code detected",
-        "Counter": "0,1",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.SMC",
         "PublicDescription": "This event counts the number of times that a program writes to a code section. Self-modifying code causes a severe penalty in all Intel? architecture processors.",
@@ -236,7 +210,6 @@
     },
     {
         "BriefDescription": "Counts the number of cycles when no uops are allocated for any reason.",
-        "Counter": "0,1",
         "EventCode": "0xCA",
         "EventName": "NO_ALLOC_CYCLES.ALL",
         "PublicDescription": "The NO_ALLOC_CYCLES.ALL event counts the number of cycles when the front-end does not provide any instructions to be allocated for any reason. This event indicates the cycles where an allocation stalls occurs, and no UOPS are allocated in that cycle.",
@@ -245,7 +218,6 @@
     },
     {
         "BriefDescription": "Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire.  After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted",
-        "Counter": "0,1",
         "EventCode": "0xCA",
         "EventName": "NO_ALLOC_CYCLES.MISPREDICTS",
         "PublicDescription": "Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire.  After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted.",
@@ -254,7 +226,6 @@
     },
     {
         "BriefDescription": "Counts the number of cycles when no uops are allocated, the IQ is empty, and no other condition is blocking allocation.",
-        "Counter": "0,1",
         "EventCode": "0xCA",
         "EventName": "NO_ALLOC_CYCLES.NOT_DELIVERED",
         "PublicDescription": "The NO_ALLOC_CYCLES.NOT_DELIVERED event is used to measure front-end inefficiencies, i.e. when front-end of the machine is not delivering micro-ops to the back-end and the back-end is not stalled. This event can be used to identify if the machine is truly front-end bound.  When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance.  Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into micro-ops (uops) in machine understandable format and putting them into a micro-op queue to be consumed by back end. The back-end then takes these micro-ops, allocates the required resources.  When all resources are ready, micro-ops are executed. If the back-end is not ready to accept micro-ops from the front-end, then we do not want to count these as front-end bottlenecks.  However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more UOPS. This event counts the cycles only when back-end is requesting more uops and front-end is not able to provide them. Some examples of conditions that cause front-end efficiencies are: Icache misses, ITLB misses, and decoder restrictions that limit the the front-end bandwidth.",
@@ -263,7 +234,6 @@
     },
     {
         "BriefDescription": "Counts the number of cycles when no uops are allocated and a RATstall is asserted.",
-        "Counter": "0,1",
         "EventCode": "0xCA",
         "EventName": "NO_ALLOC_CYCLES.RAT_STALL",
         "SampleAfterValue": "200003",
@@ -271,7 +241,6 @@
     },
     {
         "BriefDescription": "Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available)",
-        "Counter": "0,1",
         "EventCode": "0xCA",
         "EventName": "NO_ALLOC_CYCLES.ROB_FULL",
         "PublicDescription": "Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available).",
@@ -280,7 +249,6 @@
     },
     {
         "BriefDescription": "Counts the number of cycles the Alloc pipeline is stalled when any one of the RSs (IEC, FPC and MEC) is full. This event is a superset of all the individual RS stall event counts.",
-        "Counter": "0,1",
         "EventCode": "0xCB",
         "EventName": "RS_FULL_STALL.ALL",
         "SampleAfterValue": "200003",
@@ -288,7 +256,6 @@
     },
     {
         "BriefDescription": "Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry.  The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M",
-        "Counter": "0,1",
         "EventCode": "0xCB",
         "EventName": "RS_FULL_STALL.MEC",
         "PublicDescription": "Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry.  The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M.",
@@ -297,7 +264,6 @@
     },
     {
         "BriefDescription": "Micro-ops retired",
-        "Counter": "0,1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ALL",
         "PublicDescription": "This event counts the number of micro-ops retired. The processor decodes complex macro instructions into a sequence of simpler micro-ops. Most instructions are composed of one or two micro-ops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists. In some cases micro-op sequences are fused or whole instructions are fused into one micro-op. See other UOPS_RETIRED events for differentiating retired fused and non-fused micro-ops.",
@@ -306,7 +272,6 @@
     },
     {
         "BriefDescription": "MSROM micro-ops retired",
-        "Counter": "0,1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.MS",
         "PublicDescription": "This event counts the number of micro-ops retired that were supplied from MSROM.",
diff --git a/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json b/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json
index b50cee3a5e4c7..1be3fa5c4ad35 100644
--- a/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Loads missed DTLB",
-        "Counter": "0,1",
         "EventCode": "0x04",
         "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
         "PEBS": "1",
@@ -11,7 +10,6 @@
     },
     {
         "BriefDescription": "Total cycles for all the page walks. (I-side and D-side)",
-        "Counter": "0,1",
         "EventCode": "0x05",
         "EventName": "PAGE_WALKS.CYCLES",
         "PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress.  Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event.",
@@ -20,7 +18,6 @@
     },
     {
         "BriefDescription": "Duration of D-side page-walks in core cycles",
-        "Counter": "0,1",
         "EventCode": "0x05",
         "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
         "PublicDescription": "This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.",
@@ -29,7 +26,6 @@
     },
     {
         "BriefDescription": "D-side page-walks",
-        "Counter": "0,1",
         "EdgeDetect": "1",
         "EventCode": "0x05",
         "EventName": "PAGE_WALKS.D_SIDE_WALKS",
@@ -39,7 +35,6 @@
     },
     {
         "BriefDescription": "Duration of I-side page-walks in core cycles",
-        "Counter": "0,1",
         "EventCode": "0x05",
         "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
         "PublicDescription": "This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.",
@@ -48,7 +43,6 @@
     },
     {
         "BriefDescription": "I-side page-walks",
-        "Counter": "0,1",
         "EdgeDetect": "1",
         "EventCode": "0x05",
         "EventName": "PAGE_WALKS.I_SIDE_WALKS",
@@ -58,7 +52,6 @@
     },
     {
         "BriefDescription": "Total page walks that are completed (I-side and D-side)",
-        "Counter": "0,1",
         "EdgeDetect": "1",
         "EventCode": "0x05",
         "EventName": "PAGE_WALKS.WALKS",
-- 
GitLab


From 00ca782ec9f8d32ac65142f96a7423af78356818 Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:55:04 -0800
Subject: [PATCH 588/875] perf vendor events intel: Refresh skylake metrics and
 events

Update the skylake metrics and events using the new tooling from:

  https://github.com/intel/perfmon

The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1".  The
events are unchanged but unused json values are removed. The
formatting changes increase consistency across the json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-18-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../pmu-events/arch/x86/skylake/cache.json    | 660 ------------------
 .../arch/x86/skylake/floating-point.json      |  14 -
 .../pmu-events/arch/x86/skylake/frontend.json | 109 ---
 .../pmu-events/arch/x86/skylake/memory.json   | 358 ----------
 .../pmu-events/arch/x86/skylake/other.json    |   4 -
 .../pmu-events/arch/x86/skylake/pipeline.json | 192 -----
 .../arch/x86/skylake/skl-metrics.json         | 155 ++--
 .../arch/x86/skylake/uncore-cache.json        |  18 -
 .../arch/x86/skylake/uncore-other.json        |  31 +-
 .../arch/x86/skylake/virtual-memory.json      |  56 --
 10 files changed, 103 insertions(+), 1494 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/skylake/cache.json b/tools/perf/pmu-events/arch/x86/skylake/cache.json
index c3183819bf525..1538ddb5752fe 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/cache.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/cache.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "L1D data line replacements",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x51",
         "EventName": "L1D.REPLACEMENT",
         "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.FB_FULL",
         "PublicDescription": "Number of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructions.",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "L1D miss outstandings duration in cycles",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING",
         "PublicDescription": "Counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch.Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Cycles with L1D load Misses outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -43,8 +35,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -53,8 +43,6 @@
     },
     {
         "BriefDescription": "L2 cache lines filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.ALL",
         "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
@@ -63,8 +51,6 @@
     },
     {
         "BriefDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.NON_SILENT",
         "SampleAfterValue": "200003",
@@ -72,8 +58,6 @@
     },
     {
         "BriefDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.SILENT",
         "SampleAfterValue": "200003",
@@ -81,8 +65,6 @@
     },
     {
         "BriefDescription": "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.USELESS_HWPF",
         "SampleAfterValue": "200003",
@@ -90,8 +72,6 @@
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.USELESS_PREF",
         "SampleAfterValue": "200003",
@@ -99,8 +79,6 @@
     },
     {
         "BriefDescription": "L2 code requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_CODE_RD",
         "PublicDescription": "Counts the total number of L2 code requests.",
@@ -109,8 +87,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
         "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
@@ -119,8 +95,6 @@
     },
     {
         "BriefDescription": "Demand requests that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
         "PublicDescription": "Demand requests that miss L2 cache.",
@@ -129,8 +103,6 @@
     },
     {
         "BriefDescription": "Demand requests to L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
         "PublicDescription": "Demand requests to L2 cache.",
@@ -139,8 +111,6 @@
     },
     {
         "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_PF",
         "PublicDescription": "Counts the total number of requests from the L2 hardware prefetchers.",
@@ -149,8 +119,6 @@
     },
     {
         "BriefDescription": "RFO requests to L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_RFO",
         "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
@@ -159,8 +127,6 @@
     },
     {
         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_HIT",
         "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
@@ -169,8 +135,6 @@
     },
     {
         "BriefDescription": "L2 cache misses when fetching instructions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_MISS",
         "PublicDescription": "Counts L2 cache misses when fetching instructions.",
@@ -179,8 +143,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
         "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",
@@ -189,8 +151,6 @@
     },
     {
         "BriefDescription": "Demand Data Read miss L2, no rejects",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
         "PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
@@ -199,8 +159,6 @@
     },
     {
         "BriefDescription": "All requests that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.MISS",
         "PublicDescription": "All requests that miss L2 cache.",
@@ -209,8 +167,6 @@
     },
     {
         "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PF_HIT",
         "PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache.",
@@ -219,8 +175,6 @@
     },
     {
         "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PF_MISS",
         "PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache.",
@@ -229,8 +183,6 @@
     },
     {
         "BriefDescription": "All L2 requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.REFERENCES",
         "PublicDescription": "All L2 requests.",
@@ -239,8 +191,6 @@
     },
     {
         "BriefDescription": "RFO requests that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_HIT",
         "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
@@ -249,8 +199,6 @@
     },
     {
         "BriefDescription": "RFO requests that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_MISS",
         "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
@@ -259,8 +207,6 @@
     },
     {
         "BriefDescription": "L2 writebacks that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L2_WB",
         "PublicDescription": "Counts L2 writebacks that access L2 cache.",
@@ -269,8 +215,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests missed L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL057",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.MISS",
@@ -280,8 +224,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL057",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
@@ -291,8 +233,6 @@
     },
     {
         "BriefDescription": "All retired load instructions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.ALL_LOADS",
@@ -302,24 +242,18 @@
     },
     {
         "BriefDescription": "All retired store instructions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.ALL_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "SampleAfterValue": "2000003",
         "UMask": "0x82"
     },
     {
         "BriefDescription": "All retired memory instructions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.ANY",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "PublicDescription": "Counts all retired memory instructions - loads and stores.",
         "SampleAfterValue": "2000003",
@@ -327,8 +261,6 @@
     },
     {
         "BriefDescription": "Retired load instructions with locked access.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.LOCK_LOADS",
@@ -338,8 +270,6 @@
     },
     {
         "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
@@ -350,12 +280,9 @@
     },
     {
         "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.SPLIT_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
         "SampleAfterValue": "100003",
@@ -363,8 +290,6 @@
     },
     {
         "BriefDescription": "Retired load instructions that miss the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
@@ -375,12 +300,9 @@
     },
     {
         "BriefDescription": "Retired store instructions that miss the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).",
         "SampleAfterValue": "100003",
@@ -388,8 +310,6 @@
     },
     {
         "BriefDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
@@ -400,8 +320,6 @@
     },
     {
         "BriefDescription": "Retired load instructions which data sources were HitM responses from shared L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
@@ -412,8 +330,6 @@
     },
     {
         "BriefDescription": "Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
@@ -423,8 +339,6 @@
     },
     {
         "BriefDescription": "Retired load instructions which data sources were hits in L3 without snoops required",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
@@ -435,8 +349,6 @@
     },
     {
         "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD4",
         "EventName": "MEM_LOAD_MISC_RETIRED.UC",
@@ -446,8 +358,6 @@
     },
     {
         "BriefDescription": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_RETIRED.FB_HIT",
@@ -458,8 +368,6 @@
     },
     {
         "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_RETIRED.L1_HIT",
@@ -470,8 +378,6 @@
     },
     {
         "BriefDescription": "Retired load instructions missed L1 cache as data sources",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_RETIRED.L1_MISS",
@@ -482,8 +388,6 @@
     },
     {
         "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_RETIRED.L2_HIT",
@@ -494,8 +398,6 @@
     },
     {
         "BriefDescription": "Retired load instructions missed L2 cache as data sources",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_RETIRED.L2_MISS",
@@ -506,8 +408,6 @@
     },
     {
         "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_RETIRED.L3_HIT",
@@ -518,8 +418,6 @@
     },
     {
         "BriefDescription": "Retired load instructions missed L3 cache as data sources",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_RETIRED.L3_MISS",
@@ -530,8 +428,6 @@
     },
     {
         "BriefDescription": "Demand and prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
         "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
@@ -540,8 +436,6 @@
     },
     {
         "BriefDescription": "Any memory transaction that reached the SQ.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
         "PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..",
@@ -550,8 +444,6 @@
     },
     {
         "BriefDescription": "Cacheable and noncachaeble code read requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
         "PublicDescription": "Counts both cacheable and non-cacheable code read requests.",
@@ -560,8 +452,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests sent to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
         "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
@@ -570,8 +460,6 @@
     },
     {
         "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
         "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
@@ -580,8 +468,6 @@
     },
     {
         "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB2",
         "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
         "PublicDescription": "Counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entries.",
@@ -590,8 +476,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
         "PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
@@ -600,8 +484,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
@@ -611,8 +493,6 @@
     },
     {
         "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
@@ -622,8 +502,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
@@ -633,8 +511,6 @@
     },
     {
         "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
@@ -644,8 +520,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
         "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
@@ -654,8 +528,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
         "PublicDescription": "Counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the promotion point.",
@@ -664,8 +536,6 @@
     },
     {
         "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "6",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
@@ -674,8 +544,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
         "PublicDescription": "Counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
@@ -684,8 +552,6 @@
     },
     {
         "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
@@ -694,2072 +560,1554 @@
     },
     {
         "BriefDescription": "Counts all demand code readshave any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC01C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10001C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4001C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2001C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x801C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1001C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x401C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC0080004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x40080004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC0040004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x40040004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC0100004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x40100004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC0400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x40400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC0020004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x40020004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data readshave any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC01C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10001C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4001C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2001C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x801C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1001C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x401C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC0080001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x40080001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC0040001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x40040001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC0100001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x40100001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC0400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x40400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC0020001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x40020001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC01C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10001C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4001C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2001C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x801C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1001C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x401C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC0080002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000080002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400080002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200080002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80080002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100080002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x40080002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC0040002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000040002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400040002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200040002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80040002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100040002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x40040002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC0100002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000100002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400100002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200100002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80100002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100100002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x40100002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC0400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x40400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC0020002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000020002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400020002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200020002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80020002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100020002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x40020002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requestshave any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x18000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC01C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10001C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4001C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2001C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x801C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1001C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x401C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC0088000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000088000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400088000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200088000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80088000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100088000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x40088000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC0048000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000048000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400048000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200048000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80048000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100048000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x40048000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC0108000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000108000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400108000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200108000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80108000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100108000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x40108000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC0408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x40408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC0028000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000028000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400028000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200028000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80028000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100028000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x40028000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of cache line split locks sent to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF4",
         "EventName": "SQ_MISC.SPLIT_LOCK",
         "PublicDescription": "Counts the number of cache line split locks sent to the uncore.",
@@ -2768,8 +2116,6 @@
     },
     {
         "BriefDescription": "Number of PREFETCHNTA instructions executed.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.NTA",
         "SampleAfterValue": "2000003",
@@ -2777,8 +2123,6 @@
     },
     {
         "BriefDescription": "Number of PREFETCHW instructions executed.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
         "SampleAfterValue": "2000003",
@@ -2786,8 +2130,6 @@
     },
     {
         "BriefDescription": "Number of PREFETCHT0 instructions executed.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.T0",
         "SampleAfterValue": "2000003",
@@ -2795,8 +2137,6 @@
     },
     {
         "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.T1_T2",
         "SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/skylake/floating-point.json b/tools/perf/pmu-events/arch/x86/skylake/floating-point.json
index d6cee5ae44027..eb83fa537e7de 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/floating-point.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
         "PublicDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
         "PublicDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
         "PublicDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
         "PublicDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -41,8 +33,6 @@
     },
     {
         "BriefDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
         "PublicDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -51,8 +41,6 @@
     },
     {
         "BriefDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
         "PublicDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -61,8 +49,6 @@
     },
     {
         "BriefDescription": "Cycles with any input/output SSE or FP assist",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.ANY",
diff --git a/tools/perf/pmu-events/arch/x86/skylake/frontend.json b/tools/perf/pmu-events/arch/x86/skylake/frontend.json
index 8633ee406813a..13ccf50db43df 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/frontend.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xE6",
         "EventName": "BACLEARS.ANY",
         "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAB",
         "EventName": "DSB2MITE_SWITCHES.COUNT",
         "PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAB",
         "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
         "PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Retired Instructions who experienced DSB miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
         "MSRIndex": "0x3F7",
@@ -40,13 +32,10 @@
         "PEBS": "1",
         "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.DSB_MISS",
         "MSRIndex": "0x3F7",
@@ -54,13 +43,10 @@
         "PEBS": "1",
         "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.ITLB_MISS",
         "MSRIndex": "0x3F7",
@@ -68,39 +54,30 @@
         "PEBS": "1",
         "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.L1I_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x12",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.L2_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x13",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
         "MSRIndex": "0x3F7",
@@ -108,26 +85,20 @@
         "PEBS": "2",
         "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x408006",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
         "MSRIndex": "0x3F7",
@@ -135,39 +106,30 @@
         "PEBS": "1",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x400206",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x410006",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
         "MSRIndex": "0x3F7",
@@ -175,39 +137,30 @@
         "PEBS": "1",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x200206",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x300206",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
         "MSRIndex": "0x3F7",
@@ -215,52 +168,40 @@
         "PEBS": "1",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x400406",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x420006",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x404006",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
         "MSRIndex": "0x3F7",
@@ -268,13 +209,10 @@
         "PEBS": "1",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.STLB_MISS",
         "MSRIndex": "0x3F7",
@@ -282,13 +220,10 @@
         "PEBS": "1",
         "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE_16B.IFDATA_STALL",
         "PublicDescription": "Cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.",
@@ -297,8 +232,6 @@
     },
     {
         "BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x83",
         "EventName": "ICACHE_64B.IFTAG_HIT",
         "SampleAfterValue": "200003",
@@ -306,8 +239,6 @@
     },
     {
         "BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x83",
         "EventName": "ICACHE_64B.IFTAG_MISS",
         "SampleAfterValue": "200003",
@@ -315,8 +246,6 @@
     },
     {
         "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x83",
         "EventName": "ICACHE_64B.IFTAG_STALL",
         "SampleAfterValue": "200003",
@@ -324,8 +253,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -335,8 +262,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -346,8 +271,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering 4 Uops",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -357,8 +280,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering any Uop",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -368,8 +289,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_CYCLES",
@@ -379,8 +298,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_UOPS",
         "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.",
@@ -389,8 +306,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_CYCLES",
@@ -400,8 +315,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_UOPS",
         "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@@ -410,8 +323,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_CYCLES",
@@ -421,8 +332,6 @@
     },
     {
         "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_DSB_CYCLES",
@@ -432,8 +341,6 @@
     },
     {
         "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_MITE_UOPS",
         "PublicDescription": "Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.",
@@ -442,8 +349,6 @@
     },
     {
         "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
@@ -454,8 +359,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_UOPS",
         "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
@@ -464,8 +367,6 @@
     },
     {
         "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
         "PublicDescription": "Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4  x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions).  c. Instruction Decode Queue (IDQ) delivers four uops.",
@@ -474,8 +375,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -485,8 +384,6 @@
     },
     {
         "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@@ -496,8 +393,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@@ -507,8 +402,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@@ -518,8 +411,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
diff --git a/tools/perf/pmu-events/arch/x86/skylake/memory.json b/tools/perf/pmu-events/arch/x86/skylake/memory.json
index 74ea4ccb4c9a3..588ad6059a136 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/memory.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "6",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.ABORTED",
         "PEBS": "1",
@@ -32,8 +26,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.ABORTED_EVENTS",
         "SampleAfterValue": "2000003",
@@ -41,8 +33,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.ABORTED_MEM",
         "SampleAfterValue": "2000003",
@@ -50,8 +40,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.ABORTED_MEMTYPE",
         "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.",
@@ -60,8 +48,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.ABORTED_TIMER",
         "SampleAfterValue": "2000003",
@@ -69,8 +55,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
         "SampleAfterValue": "2000003",
@@ -78,8 +62,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution successfully committed",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.COMMIT",
         "PublicDescription": "Number of times HLE commit succeeded.",
@@ -88,8 +70,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution started.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.START",
         "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.",
@@ -98,8 +78,6 @@
     },
     {
         "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL089",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
@@ -109,8 +87,6 @@
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
@@ -119,13 +95,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "1009",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
@@ -134,13 +107,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "20011",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
@@ -149,13 +119,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "503",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
@@ -164,13 +131,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
@@ -179,13 +143,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "100003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
@@ -194,13 +155,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "101",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
@@ -209,13 +167,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "2003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
@@ -224,13 +179,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "50021",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Demand Data Read requests who miss L3 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
         "PublicDescription": "Demand Data Read requests who miss L3 cache.",
@@ -239,8 +191,6 @@
     },
     {
         "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
@@ -249,8 +199,6 @@
     },
     {
         "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
         "SampleAfterValue": "2000003",
@@ -258,8 +206,6 @@
     },
     {
         "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "6",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
@@ -268,1064 +214,798 @@
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x20001C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000080004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000040004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000100004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFC400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x203C400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7C400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC4000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2004000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x44000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000400004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000020004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x20001C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000080001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000040001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000100001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFC400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x203C400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7C400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC4000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2004000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x44000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000400001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000020001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x20001C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000080002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000040002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000100002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFC400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x203C400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7C400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC4000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2004000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x44000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000400002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000020002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x20001C8000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000088000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000048000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000108000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FFC408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103C408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x43C408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x23C408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xBC408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x203C408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x13C408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7C408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FC4008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x84008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2004008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SPL_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x44008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000408000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts any other requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000028000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.ABORTED",
         "PEBS": "1",
@@ -1335,8 +1015,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.ABORTED_EVENTS",
         "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
@@ -1345,8 +1023,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.ABORTED_MEM",
         "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
@@ -1355,8 +1031,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
         "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.",
@@ -1365,8 +1039,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.ABORTED_TIMER",
         "SampleAfterValue": "2000003",
@@ -1374,8 +1046,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
         "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.",
@@ -1384,8 +1054,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution successfully committed",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.COMMIT",
         "PublicDescription": "Number of times RTM commit succeeded.",
@@ -1394,8 +1062,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution started.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.START",
         "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.",
@@ -1404,8 +1070,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC1",
         "SampleAfterValue": "2000003",
@@ -1413,8 +1077,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC2",
         "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
@@ -1423,8 +1085,6 @@
     },
     {
         "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC3",
         "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
@@ -1433,8 +1093,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC4",
         "PublicDescription": "RTM region detected inside HLE.",
@@ -1443,8 +1101,6 @@
     },
     {
         "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC5",
         "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
@@ -1453,8 +1109,6 @@
     },
     {
         "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CAPACITY",
         "SampleAfterValue": "2000003",
@@ -1462,8 +1116,6 @@
     },
     {
         "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CONFLICT",
         "PublicDescription": "Number of times a TSX line had a cache conflict.",
@@ -1472,8 +1124,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
         "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
@@ -1482,8 +1132,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
         "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
@@ -1492,8 +1140,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
         "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
@@ -1502,8 +1148,6 @@
     },
     {
         "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
         "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
@@ -1512,8 +1156,6 @@
     },
     {
         "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
         "PublicDescription": "Number of times we could not allocate Lock Buffer.",
diff --git a/tools/perf/pmu-events/arch/x86/skylake/other.json b/tools/perf/pmu-events/arch/x86/skylake/other.json
index 8f4bc8892c476..9f3a9dffb8070 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/other.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/other.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Number of hardware interrupts received by the processor.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCB",
         "EventName": "HW_INTERRUPTS.RECEIVED",
         "PublicDescription": "Counts the number of hardware interruptions received by the processor.",
@@ -10,8 +8,6 @@
         "UMask": "0x1"
     },
     {
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x09",
         "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
         "SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/skylake/pipeline.json b/tools/perf/pmu-events/arch/x86/skylake/pipeline.json
index 79fda10ec4bbd..cf35a535c2f6d 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/pipeline.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x14",
         "EventName": "ARITH.DIVIDER_ACTIVE",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "All (macro) branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "All (macro) branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
@@ -33,8 +27,6 @@
     },
     {
         "BriefDescription": "Conditional branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.CONDITIONAL",
@@ -45,8 +37,6 @@
     },
     {
         "BriefDescription": "Not taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.COND_NTAKEN",
@@ -56,8 +46,6 @@
     },
     {
         "BriefDescription": "Far branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.FAR_BRANCH",
@@ -68,8 +56,6 @@
     },
     {
         "BriefDescription": "Direct and indirect near call instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL",
@@ -80,8 +66,6 @@
     },
     {
         "BriefDescription": "Return instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_RETURN",
@@ -92,8 +76,6 @@
     },
     {
         "BriefDescription": "Taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
@@ -104,8 +86,6 @@
     },
     {
         "BriefDescription": "Not taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NOT_TAKEN",
@@ -115,8 +95,6 @@
     },
     {
         "BriefDescription": "All mispredicted macro branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch.  When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
@@ -124,8 +102,6 @@
     },
     {
         "BriefDescription": "Mispredicted macro branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
         "PEBS": "2",
@@ -135,8 +111,6 @@
     },
     {
         "BriefDescription": "Mispredicted conditional branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -146,8 +120,6 @@
     },
     {
         "BriefDescription": "Mispredicted direct and indirect near call instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -157,8 +129,6 @@
     },
     {
         "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
@@ -167,8 +137,6 @@
     },
     {
         "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "25003",
@@ -176,8 +144,6 @@
     },
     {
         "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
         "SampleAfterValue": "25003",
@@ -186,8 +152,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
         "SampleAfterValue": "25003",
@@ -195,8 +159,6 @@
     },
     {
         "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "25003",
@@ -204,8 +166,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the core is not in halt state.",
-        "Counter": "Fixed counter 2",
-        "CounterHTOff": "Fixed counter 2",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
         "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
         "SampleAfterValue": "2000003",
@@ -213,8 +173,6 @@
     },
     {
         "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
         "SampleAfterValue": "25003",
@@ -223,8 +181,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
         "SampleAfterValue": "25003",
@@ -232,8 +188,6 @@
     },
     {
         "BriefDescription": "Counts when there is a transition from ring 1, 2 or 3 to ring 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x3C",
@@ -243,8 +197,6 @@
     },
     {
         "BriefDescription": "Core cycles when the thread is not in halt state",
-        "Counter": "Fixed counter 1",
-        "CounterHTOff": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD",
         "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
         "SampleAfterValue": "2000003",
@@ -253,16 +205,12 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
-        "Counter": "Fixed counter 1",
-        "CounterHTOff": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Thread cycles when thread is not in halt state",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
         "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
@@ -271,16 +219,12 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "8",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
@@ -289,8 +233,6 @@
     },
     {
         "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
@@ -299,8 +241,6 @@
     },
     {
         "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "16",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
@@ -309,8 +249,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "12",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
@@ -319,8 +257,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "5",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
@@ -329,8 +265,6 @@
     },
     {
         "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "20",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
@@ -339,8 +273,6 @@
     },
     {
         "BriefDescription": "Total execution stalls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
@@ -349,8 +281,6 @@
     },
     {
         "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA6",
         "EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
         "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
@@ -359,8 +289,6 @@
     },
     {
         "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA6",
         "EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
         "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
@@ -369,8 +297,6 @@
     },
     {
         "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA6",
         "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
         "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
@@ -379,8 +305,6 @@
     },
     {
         "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA6",
         "EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
         "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
@@ -389,8 +313,6 @@
     },
     {
         "BriefDescription": "Cycles where the Store Buffer was full and no outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA6",
         "EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
         "SampleAfterValue": "2000003",
@@ -398,8 +320,6 @@
     },
     {
         "BriefDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA6",
         "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS",
         "PublicDescription": "Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty.",
@@ -408,8 +328,6 @@
     },
     {
         "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.LCP",
         "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
@@ -418,8 +336,6 @@
     },
     {
         "BriefDescription": "Instruction decoders utilized in a cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x55",
         "EventName": "INST_DECODED.DECODERS",
         "PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
@@ -428,8 +344,6 @@
     },
     {
         "BriefDescription": "Instructions retired from execution.",
-        "Counter": "Fixed counter 0",
-        "CounterHTOff": "Fixed counter 0",
         "EventName": "INST_RETIRED.ANY",
         "PublicDescription": "Counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
         "SampleAfterValue": "2000003",
@@ -437,8 +351,6 @@
     },
     {
         "BriefDescription": "Number of instructions retired. General Counter - architectural event",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091, SKL044",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.ANY_P",
@@ -447,8 +359,6 @@
     },
     {
         "BriefDescription": "Number of all retired NOP instructions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091, SKL044",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.NOP",
@@ -458,8 +368,6 @@
     },
     {
         "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
-        "Counter": "1",
-        "CounterHTOff": "1",
         "Errata": "SKL091, SKL044",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.PREC_DIST",
@@ -470,8 +378,6 @@
     },
     {
         "BriefDescription": "Number of cycles using always true condition applied to  PEBS instructions retired event.",
-        "Counter": "0,2,3",
-        "CounterHTOff": "0,2,3",
         "CounterMask": "10",
         "Errata": "SKL091, SKL044",
         "EventCode": "0xC0",
@@ -484,8 +390,6 @@
     },
     {
         "BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
         "SampleAfterValue": "2000003",
@@ -493,8 +397,6 @@
     },
     {
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES",
         "PublicDescription": "Core cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
@@ -504,8 +406,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
         "SampleAfterValue": "2000003",
@@ -513,8 +413,6 @@
     },
     {
         "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.NO_SR",
         "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
@@ -523,8 +421,6 @@
     },
     {
         "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.STORE_FORWARD",
         "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
@@ -533,8 +429,6 @@
     },
     {
         "BriefDescription": "False dependencies in MOB due to partial compare on address.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x07",
         "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
         "PublicDescription": "Counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",
@@ -543,8 +437,6 @@
     },
     {
         "BriefDescription": "Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4C",
         "EventName": "LOAD_HIT_PRE.SW_PF",
         "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
@@ -553,8 +445,6 @@
     },
     {
         "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_4_UOPS",
@@ -564,8 +454,6 @@
     },
     {
         "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_ACTIVE",
@@ -575,8 +463,6 @@
     },
     {
         "BriefDescription": "Number of Uops delivered by the LSD.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA8",
         "EventName": "LSD.UOPS",
         "PublicDescription": "Number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
@@ -585,8 +471,6 @@
     },
     {
         "BriefDescription": "Number of machine clears (nukes) of any type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xC3",
@@ -596,8 +480,6 @@
     },
     {
         "BriefDescription": "Self-modifying code (SMC) detected.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.SMC",
         "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
@@ -606,8 +488,6 @@
     },
     {
         "BriefDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.ANY",
         "SampleAfterValue": "100003",
@@ -615,8 +495,6 @@
     },
     {
         "BriefDescription": "Cycles where the pipeline is stalled due to serializing operations.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x59",
         "EventName": "PARTIAL_RAT_STALLS.SCOREBOARD",
         "PublicDescription": "This event counts cycles during which the microcode scoreboard stalls happen.",
@@ -625,8 +503,6 @@
     },
     {
         "BriefDescription": "Resource-related stall cycles",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa2",
         "EventName": "RESOURCE_STALLS.ANY",
         "PublicDescription": "Counts resource-related stall cycles.",
@@ -635,8 +511,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.SB",
         "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
@@ -645,8 +519,6 @@
     },
     {
         "BriefDescription": "Increments whenever there is an update to the LBR array.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCC",
         "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
         "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.",
@@ -655,8 +527,6 @@
     },
     {
         "BriefDescription": "Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL products.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCC",
         "EventName": "ROB_MISC_EVENTS.PAUSE_INST",
         "SampleAfterValue": "2000003",
@@ -664,8 +534,6 @@
     },
     {
         "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5E",
         "EventName": "RS_EVENTS.EMPTY_CYCLES",
         "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
@@ -674,8 +542,6 @@
     },
     {
         "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5E",
@@ -687,8 +553,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_0",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.",
@@ -697,8 +561,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 1",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_1",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.",
@@ -707,8 +569,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_2",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 2.",
@@ -717,8 +577,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_3",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 3.",
@@ -727,8 +585,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 4",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_4",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 4.",
@@ -737,8 +593,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 5",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_5",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.",
@@ -747,8 +601,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 6",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_6",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
@@ -757,8 +609,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 7",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 7.",
@@ -767,8 +617,6 @@
     },
     {
         "BriefDescription": "Number of uops executed on the core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE",
         "PublicDescription": "Number of uops executed from any thread.",
@@ -777,8 +625,6 @@
     },
     {
         "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@@ -787,8 +633,6 @@
     },
     {
         "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@@ -797,8 +641,6 @@
     },
     {
         "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@@ -807,8 +649,6 @@
     },
     {
         "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@@ -817,8 +657,6 @@
     },
     {
         "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
@@ -828,8 +666,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
@@ -839,8 +675,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
@@ -850,8 +684,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
@@ -861,8 +693,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
@@ -872,8 +702,6 @@
     },
     {
         "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.STALL_CYCLES",
@@ -884,8 +712,6 @@
     },
     {
         "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.THREAD",
         "PublicDescription": "Number of uops to be executed per-thread each cycle.",
@@ -894,8 +720,6 @@
     },
     {
         "BriefDescription": "Counts the number of x87 uops dispatched.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.X87",
         "PublicDescription": "Counts the number of x87 uops executed.",
@@ -904,8 +728,6 @@
     },
     {
         "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.ANY",
         "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
@@ -914,8 +736,6 @@
     },
     {
         "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.SLOW_LEA",
         "SampleAfterValue": "2000003",
@@ -923,8 +743,6 @@
     },
     {
         "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -935,8 +753,6 @@
     },
     {
         "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
         "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.",
@@ -945,8 +761,6 @@
     },
     {
         "BriefDescription": "Number of macro-fused uops retired. (non precise)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.MACRO_FUSED",
         "PublicDescription": "Counts the number of macro-fused uops retired. (non precise)",
@@ -955,8 +769,6 @@
     },
     {
         "BriefDescription": "Retirement slots used.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
         "PublicDescription": "Counts the retirement slots used.",
@@ -965,8 +777,6 @@
     },
     {
         "BriefDescription": "Cycles without actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -977,8 +787,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 10 actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "16",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json b/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json
index f138b9836b514..972d3744c2c85 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json
@@ -41,7 +41,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage",
-        "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
+        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
         "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group",
         "MetricName": "tma_mispredicts_resteers",
         "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage.  Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
@@ -49,7 +49,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears",
-        "MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT))) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
+        "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
         "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group",
         "MetricName": "tma_clears_resteers",
         "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears.  Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
@@ -120,7 +120,7 @@
     },
     {
         "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
-        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
         "MetricGroup": "TopdownL1;tma_L1_group",
         "MetricName": "tma_bad_speculation",
         "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
@@ -128,7 +128,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
-        "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
+        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
         "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
         "MetricName": "tma_branch_mispredicts",
         "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
@@ -144,7 +144,7 @@
     },
     {
         "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
-        "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+        "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
         "MetricGroup": "TopdownL1;tma_L1_group",
         "MetricName": "tma_backend_bound",
         "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
@@ -152,7 +152,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
-        "MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * tma_backend_bound",
+        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound",
         "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
         "MetricName": "tma_memory_bound",
         "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@@ -198,7 +198,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
-        "MetricExpr": "(12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * (9 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
+        "MetricExpr": "(12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (9 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
         "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
         "MetricName": "tma_lock_latency",
         "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS",
@@ -230,7 +230,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
-        "MetricExpr": "((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / ((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@)) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS)",
+        "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS)",
         "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_l2_bound",
         "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS",
@@ -246,7 +246,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
-        "MetricExpr": "((18.5 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM + (16.5 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+        "MetricExpr": "(18.5 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM + 16.5 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
         "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_contested_accesses",
         "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
@@ -254,7 +254,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
-        "MetricExpr": "(16.5 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+        "MetricExpr": "16.5 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
         "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_data_sharing",
         "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
@@ -262,7 +262,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
-        "MetricExpr": "(6.5 * Average_Frequency) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+        "MetricExpr": "6.5 * Average_Frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
         "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_l3_hit_latency",
         "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
@@ -270,7 +270,7 @@
     },
     {
         "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
-        "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
+        "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
         "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_sq_full",
         "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
@@ -278,7 +278,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
-        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS) - tma_l2_bound)",
+        "MetricExpr": "CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS - tma_l2_bound",
         "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_dram_bound",
         "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS",
@@ -310,7 +310,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
-        "MetricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES))) + (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
+        "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
         "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
         "MetricName": "tma_store_latency",
         "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
@@ -318,7 +318,7 @@
     },
     {
         "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
-        "MetricExpr": "(22 * Average_Frequency) * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
+        "MetricExpr": "22 * Average_Frequency * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
         "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
         "MetricName": "tma_false_sharing",
         "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line.  Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM",
@@ -372,7 +372,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
-        "MetricExpr": "(EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if (ARITH.DIVIDER_ACTIVE < (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY)) else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CLKS",
+        "MetricExpr": "((EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CLKS)",
         "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
         "MetricName": "tma_ports_utilization",
         "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@@ -427,7 +427,7 @@
     },
     {
         "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
-        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / (4 * CORE_CLKS)",
+        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS",
         "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
         "MetricName": "tma_alu_op_utilization",
         "ScaleUnit": "100%"
@@ -483,7 +483,7 @@
     },
     {
         "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
+        "MetricExpr": "tma_port_4",
         "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
         "MetricName": "tma_store_op_utilization",
         "ScaleUnit": "100%"
@@ -622,7 +622,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
-        "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
         "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
         "MetricName": "tma_microcode_sequencer",
         "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
@@ -652,19 +652,19 @@
     },
     {
         "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) ",
+        "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))",
         "MetricGroup": "Mem;MemoryBW;Offcore",
         "MetricName": "Memory_Bandwidth"
     },
     {
         "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + (tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)))",
+        "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound))",
         "MetricGroup": "Mem;MemoryLat;Offcore",
         "MetricName": "Memory_Latency"
     },
     {
         "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency))) ",
+        "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)))",
         "MetricGroup": "Mem;MemoryTLB;Offcore",
         "MetricName": "Memory_Data_TLBs"
     },
@@ -737,32 +737,32 @@
     },
     {
         "BriefDescription": "Floating Point Operations Per Cycle",
-        "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
         "MetricGroup": "Flops;Ret",
         "MetricName": "FLOPc"
     },
     {
         "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
-        "MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
         "MetricGroup": "Cor;Flops;HPC",
         "MetricName": "FP_Arith_Utilization",
         "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
     },
     {
         "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / ((UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
         "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
         "MetricName": "ILP"
     },
     {
         "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
-        "MetricExpr": "(1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0",
+        "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)",
         "MetricGroup": "Cor;SMT",
         "MetricName": "Core_Bound_Likely"
     },
     {
         "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
-        "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
+        "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
         "MetricGroup": "SMT",
         "MetricName": "CORE_CLKS"
     },
@@ -804,13 +804,13 @@
     },
     {
         "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
         "MetricGroup": "Flops;InsType",
         "MetricName": "IpFLOP"
     },
     {
         "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
         "MetricGroup": "Flops;InsType",
         "MetricName": "IpArith",
         "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
@@ -905,7 +905,7 @@
     },
     {
         "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
-        "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
+        "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
         "MetricGroup": "Bad;BrMispredicts",
         "MetricName": "Branch_Misprediction_Cost"
     },
@@ -947,55 +947,55 @@
     },
     {
         "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L1MPKI"
     },
     {
         "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L1MPKI_Load"
     },
     {
         "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
         "MetricGroup": "Backend;CacheMisses;Mem",
         "MetricName": "L2MPKI"
     },
     {
         "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem;Offcore",
         "MetricName": "L2MPKI_All"
     },
     {
         "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L2MPKI_Load"
     },
     {
         "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
-        "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L2HPKI_All"
     },
     {
         "BriefDescription": "L2 cache hits per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L2HPKI_Load"
     },
     {
         "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L3MPKI"
     },
     {
         "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "FB_HPKI"
     },
@@ -1008,25 +1008,25 @@
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
-        "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
+        "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L1D_Cache_Fill_BW"
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
-        "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
+        "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L2_Cache_Fill_BW"
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
+        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L3_Cache_Fill_BW"
     },
     {
         "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time",
+        "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW;Offcore",
         "MetricName": "L3_Cache_Access_BW"
     },
@@ -1056,19 +1056,19 @@
     },
     {
         "BriefDescription": "Average CPU Utilization",
-        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
+        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
         "MetricGroup": "HPC;Summary",
         "MetricName": "CPU_Utilization"
     },
     {
         "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
-        "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
+        "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
         "MetricGroup": "Power;Summary",
         "MetricName": "Average_Frequency"
     },
     {
         "BriefDescription": "Giga Floating Point Operations Per Second",
-        "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1000000000) / duration_time",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time",
         "MetricGroup": "Cor;Flops;HPC",
         "MetricName": "GFLOPs",
         "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
@@ -1081,7 +1081,7 @@
     },
     {
         "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
-        "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
+        "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
         "MetricGroup": "SMT",
         "MetricName": "SMT_2T_Utilization"
     },
@@ -1099,74 +1099,99 @@
     },
     {
         "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
-        "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1000000 / duration_time / 1000",
+        "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3",
         "MetricGroup": "HPC;Mem;MemoryBW;SoC",
         "MetricName": "DRAM_BW_Use"
     },
     {
         "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)",
-        "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
+        "MetricExpr": "MEM_Parallel_Requests",
         "MetricGroup": "Mem;SoC",
         "MetricName": "MEM_Request_Latency"
     },
     {
         "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests",
-        "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
+        "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL",
         "MetricGroup": "Mem;SoC",
         "MetricName": "MEM_Parallel_Requests"
     },
+    {
+        "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
+        "MetricExpr": "1e9 * (UNC_ARB_TRK_OCCUPANCY.DATA_READ / UNC_ARB_TRK_REQUESTS.DATA_READ) / (Socket_CLKS / duration_time)",
+        "MetricGroup": "Mem;MemoryLat;SoC",
+        "MetricName": "MEM_Read_Latency"
+    },
     {
         "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
-        "MetricExpr": "arb@event\\=0x80\\,umask\\=0x2@ / arb@event\\=0x80\\,umask\\=0x2\\,cmask\\=1@",
+        "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.DATA_READ / UNC_ARB_TRK_OCCUPANCY.DATA_READ@thresh\\=1@",
         "MetricGroup": "Mem;MemoryBW;SoC",
         "MetricName": "MEM_Parallel_Reads"
     },
+    {
+        "BriefDescription": "Socket actual clocks when any core is active on that socket",
+        "MetricExpr": "UNC_CLOCK.SOCKET",
+        "MetricGroup": "SoC",
+        "MetricName": "Socket_CLKS"
+    },
     {
         "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
         "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
         "MetricGroup": "Branches;OS",
         "MetricName": "IpFarBranch"
     },
+    {
+        "BriefDescription": "Uncore frequency per die [GHZ]",
+        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+        "MetricGroup": "SoC",
+        "MetricName": "UNCORE_FREQ"
+    },
     {
         "BriefDescription": "C3 residency percent per core",
-        "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C3_Core_Residency"
+        "MetricName": "C3_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C6 residency percent per core",
-        "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C6_Core_Residency"
+        "MetricName": "C6_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C7 residency percent per core",
-        "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C7_Core_Residency"
+        "MetricName": "C7_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C2 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C2_Pkg_Residency"
+        "MetricName": "C2_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C3 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C3_Pkg_Residency"
+        "MetricName": "C3_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C6 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C6_Pkg_Residency"
+        "MetricName": "C6_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C7 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C7_Pkg_Residency"
+        "MetricName": "C7_Pkg_Residency",
+        "ScaleUnit": "100%"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json b/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json
index edb1014bee0f7..ec9463c94ffe5 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
         "PerPkg": "1",
@@ -11,7 +10,6 @@
     },
     {
         "BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
         "PerPkg": "1",
@@ -21,7 +19,6 @@
     },
     {
         "BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
         "PerPkg": "1",
@@ -31,7 +28,6 @@
     },
     {
         "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
         "PerPkg": "1",
@@ -41,7 +37,6 @@
     },
     {
         "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
         "PerPkg": "1",
@@ -51,7 +46,6 @@
     },
     {
         "BriefDescription": "L3 Lookup read request that access cache and found line in I-state",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
         "PerPkg": "1",
@@ -61,7 +55,6 @@
     },
     {
         "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
         "PerPkg": "1",
@@ -71,7 +64,6 @@
     },
     {
         "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
         "PerPkg": "1",
@@ -81,7 +73,6 @@
     },
     {
         "BriefDescription": "L3 Lookup write request that access cache and found line in M-state",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
         "PerPkg": "1",
@@ -91,7 +82,6 @@
     },
     {
         "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state",
-        "Counter": "0,1",
         "EventCode": "0x34",
         "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
         "PerPkg": "1",
@@ -101,41 +91,33 @@
     },
     {
         "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
         "UMask": "0x48",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
         "UMask": "0x44",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
         "UMask": "0x81",
         "Unit": "CBO"
     },
     {
         "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
         "PerPkg": "1",
-        "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
         "UMask": "0x41",
         "Unit": "CBO"
     }
diff --git a/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json b/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json
index bf5d4acdd6b88..e6d4cd625597d 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json
@@ -1,12 +1,10 @@
 [
     {
         "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
-        "Counter": "0,1",
         "EventCode": "0x84",
         "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
         "PerPkg": "1",
-        "PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
@@ -14,8 +12,7 @@
         "EventCode": "0x80",
         "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "PublicDescription": "Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
@@ -24,8 +21,7 @@
         "EventCode": "0x80",
         "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
         "PerPkg": "1",
-        "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
@@ -33,43 +29,42 @@
         "EventCode": "0x80",
         "EventName": "UNC_ARB_TRK_OCCUPANCY.DATA_READ",
         "PerPkg": "1",
-        "PublicDescription": "Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk.",
-        "UMask": "0x02",
+        "UMask": "0x2",
+        "Unit": "ARB"
+    },
+    {
+        "EventCode": "0x81",
+        "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
+        "PerPkg": "1",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
-        "Counter": "0,1",
         "EventCode": "0x81",
         "EventName": "UNC_ARB_TRK_REQUESTS.DATA_READ",
         "PerPkg": "1",
-        "PublicDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
-        "Counter": "0,1",
         "EventCode": "0x81",
         "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
         "PerPkg": "1",
-        "PublicDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
-        "Counter": "0,1",
         "EventCode": "0x81",
         "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
         "PerPkg": "1",
-        "PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
         "UMask": "0x20",
         "Unit": "ARB"
     },
     {
         "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
-        "Counter": "FIXED",
         "EventCode": "0xff",
         "EventName": "UNC_CLOCK.SOCKET",
         "PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json b/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json
index dd334b416c57d..f59405877ae8b 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Load misses in all DTLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
         "PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
         "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
@@ -32,8 +26,6 @@
     },
     {
         "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
         "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -42,8 +34,6 @@
     },
     {
         "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
         "PublicDescription": "Counts completed page walks  (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -52,8 +42,6 @@
     },
     {
         "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
         "PublicDescription": "Counts completed page walks  (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -62,8 +50,6 @@
     },
     {
         "BriefDescription": "Page walk completed due to a demand data load to a 4K page",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
         "PublicDescription": "Counts completed page walks  (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -72,8 +58,6 @@
     },
     {
         "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
         "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture.",
@@ -82,8 +66,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
         "PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
@@ -92,8 +74,6 @@
     },
     {
         "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT",
         "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
@@ -102,8 +82,6 @@
     },
     {
         "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
@@ -113,8 +91,6 @@
     },
     {
         "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
         "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -123,8 +99,6 @@
     },
     {
         "BriefDescription": "Page walk completed due to a demand data store to a 1G page",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
         "PublicDescription": "Counts completed page walks  (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -133,8 +107,6 @@
     },
     {
         "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
         "PublicDescription": "Counts completed page walks  (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -143,8 +115,6 @@
     },
     {
         "BriefDescription": "Page walk completed due to a demand data store to a 4K page",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
         "PublicDescription": "Counts completed page walks  (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -153,8 +123,6 @@
     },
     {
         "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
         "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture.",
@@ -163,8 +131,6 @@
     },
     {
         "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4f",
         "EventName": "EPT.WALK_PENDING",
         "PublicDescription": "Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type.",
@@ -173,8 +139,6 @@
     },
     {
         "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAE",
         "EventName": "ITLB.ITLB_FLUSH",
         "PublicDescription": "Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
@@ -183,8 +147,6 @@
     },
     {
         "BriefDescription": "Misses at all ITLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
         "PublicDescription": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed.",
@@ -193,8 +155,6 @@
     },
     {
         "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT",
         "SampleAfterValue": "100003",
@@ -202,8 +162,6 @@
     },
     {
         "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_ACTIVE",
@@ -213,8 +171,6 @@
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
         "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -223,8 +179,6 @@
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
         "PublicDescription": "Counts completed page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -233,8 +187,6 @@
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
         "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -243,8 +195,6 @@
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
         "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -253,8 +203,6 @@
     },
     {
         "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_PENDING",
         "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.",
@@ -263,8 +211,6 @@
     },
     {
         "BriefDescription": "DTLB flush attempts of the thread-specific entries",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.DTLB_THREAD",
         "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
@@ -273,8 +219,6 @@
     },
     {
         "BriefDescription": "STLB flush attempts",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.STLB_ANY",
         "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
-- 
GitLab


From ecabdc6a7280f5714fcd978504af72de68e0f327 Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:55:05 -0800
Subject: [PATCH 589/875] perf vendor events intel: Refresh skylakex metrics
 and events

Update the skylakex metrics and events using the new tooling from:

  https://github.com/intel/perfmon

The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
order of metrics varies as TMA metrics are first converted and then
removed if perfmon versions are found. The events are updated with
fixes to uncore events and improved descriptions. uncore-other.json
changes due to events now being sorted. The formatting changes
increase consistency across the json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-19-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../pmu-events/arch/x86/skylakex/cache.json   |   368 -
 .../arch/x86/skylakex/floating-point.json     |    18 -
 .../arch/x86/skylakex/frontend.json           |   109 -
 .../pmu-events/arch/x86/skylakex/memory.json  |   310 -
 .../pmu-events/arch/x86/skylakex/other.json   |    30 -
 .../arch/x86/skylakex/pipeline.json           |   194 -
 .../arch/x86/skylakex/skx-metrics.json        |  2134 +-
 .../arch/x86/skylakex/uncore-memory.json      |  2303 +-
 .../arch/x86/skylakex/uncore-other.json       | 29356 +++++++++-------
 .../arch/x86/skylakex/uncore-power.json       |    45 +-
 .../arch/x86/skylakex/virtual-memory.json     |    56 -
 11 files changed, 18426 insertions(+), 16497 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/skylakex/cache.json b/tools/perf/pmu-events/arch/x86/skylakex/cache.json
index e21010c0df416..92da692795e72 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/cache.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/cache.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "L1D data line replacements",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x51",
         "EventName": "L1D.REPLACEMENT",
         "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.FB_FULL",
         "PublicDescription": "Number of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructions.",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "L1D miss outstandings duration in cycles",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING",
         "PublicDescription": "Counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch.Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Cycles with L1D load Misses outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -43,8 +35,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -53,8 +43,6 @@
     },
     {
         "BriefDescription": "L2 cache lines filling L2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.ALL",
         "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
@@ -63,8 +51,6 @@
     },
     {
         "BriefDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3.  Clean lines may either be allocated in L3 or dropped",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.NON_SILENT",
         "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3.  Clean lines may either be allocated in L3 or dropped.",
@@ -73,8 +59,6 @@
     },
     {
         "BriefDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded event.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.SILENT",
         "SampleAfterValue": "200003",
@@ -82,8 +66,6 @@
     },
     {
         "BriefDescription": "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.USELESS_HWPF",
         "SampleAfterValue": "200003",
@@ -91,8 +73,6 @@
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Deprecated": "1",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.USELESS_PREF",
@@ -101,8 +81,6 @@
     },
     {
         "BriefDescription": "L2 code requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_CODE_RD",
         "PublicDescription": "Counts the total number of L2 code requests.",
@@ -111,8 +89,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
         "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
@@ -121,8 +97,6 @@
     },
     {
         "BriefDescription": "Demand requests that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
         "PublicDescription": "Demand requests that miss L2 cache.",
@@ -131,8 +105,6 @@
     },
     {
         "BriefDescription": "Demand requests to L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
         "PublicDescription": "Demand requests to L2 cache.",
@@ -141,8 +113,6 @@
     },
     {
         "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_PF",
         "PublicDescription": "Counts the total number of requests from the L2 hardware prefetchers.",
@@ -151,8 +121,6 @@
     },
     {
         "BriefDescription": "RFO requests to L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_RFO",
         "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
@@ -161,8 +129,6 @@
     },
     {
         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_HIT",
         "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
@@ -171,8 +137,6 @@
     },
     {
         "BriefDescription": "L2 cache misses when fetching instructions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_MISS",
         "PublicDescription": "Counts L2 cache misses when fetching instructions.",
@@ -181,8 +145,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
         "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",
@@ -191,8 +153,6 @@
     },
     {
         "BriefDescription": "Demand Data Read miss L2, no rejects",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
         "PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
@@ -201,8 +161,6 @@
     },
     {
         "BriefDescription": "All requests that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.MISS",
         "PublicDescription": "All requests that miss L2 cache.",
@@ -211,8 +169,6 @@
     },
     {
         "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PF_HIT",
         "PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache.",
@@ -221,8 +177,6 @@
     },
     {
         "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PF_MISS",
         "PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache.",
@@ -231,8 +185,6 @@
     },
     {
         "BriefDescription": "All L2 requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.REFERENCES",
         "PublicDescription": "All L2 requests.",
@@ -241,8 +193,6 @@
     },
     {
         "BriefDescription": "RFO requests that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_HIT",
         "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
@@ -251,8 +201,6 @@
     },
     {
         "BriefDescription": "RFO requests that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_MISS",
         "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
@@ -261,8 +209,6 @@
     },
     {
         "BriefDescription": "L2 writebacks that access L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF0",
         "EventName": "L2_TRANS.L2_WB",
         "PublicDescription": "Counts L2 writebacks that access L2 cache.",
@@ -271,8 +217,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests missed L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL057",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.MISS",
@@ -282,8 +226,6 @@
     },
     {
         "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL057",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
@@ -293,8 +235,6 @@
     },
     {
         "BriefDescription": "All retired load instructions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.ALL_LOADS",
@@ -304,24 +244,18 @@
     },
     {
         "BriefDescription": "All retired store instructions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.ALL_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "SampleAfterValue": "2000003",
         "UMask": "0x82"
     },
     {
         "BriefDescription": "All retired memory instructions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.ANY",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "PublicDescription": "Counts all retired memory instructions - loads and stores.",
         "SampleAfterValue": "2000003",
@@ -329,8 +263,6 @@
     },
     {
         "BriefDescription": "Retired load instructions with locked access.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.LOCK_LOADS",
@@ -340,8 +272,6 @@
     },
     {
         "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
@@ -352,12 +282,9 @@
     },
     {
         "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.SPLIT_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
         "SampleAfterValue": "100003",
@@ -365,8 +292,6 @@
     },
     {
         "BriefDescription": "Retired load instructions that miss the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
@@ -377,12 +302,9 @@
     },
     {
         "BriefDescription": "Retired store instructions that miss the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD0",
         "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
         "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).",
         "SampleAfterValue": "100003",
@@ -390,8 +312,6 @@
     },
     {
         "BriefDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
@@ -402,8 +322,6 @@
     },
     {
         "BriefDescription": "Retired load instructions which data sources were HitM responses from shared L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
@@ -414,8 +332,6 @@
     },
     {
         "BriefDescription": "Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
@@ -425,8 +341,6 @@
     },
     {
         "BriefDescription": "Retired load instructions which data sources were hits in L3 without snoops required",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
@@ -437,8 +351,6 @@
     },
     {
         "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD3",
         "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
@@ -449,8 +361,6 @@
     },
     {
         "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from remote dram",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD3",
         "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM",
@@ -460,8 +370,6 @@
     },
     {
         "BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD3",
         "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD",
@@ -472,8 +380,6 @@
     },
     {
         "BriefDescription": "Retired load instructions whose data sources was remote HITM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD3",
         "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM",
@@ -484,8 +390,6 @@
     },
     {
         "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD4",
         "EventName": "MEM_LOAD_MISC_RETIRED.UC",
@@ -495,8 +399,6 @@
     },
     {
         "BriefDescription": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_RETIRED.FB_HIT",
@@ -507,8 +409,6 @@
     },
     {
         "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_RETIRED.L1_HIT",
@@ -519,8 +419,6 @@
     },
     {
         "BriefDescription": "Retired load instructions missed L1 cache as data sources",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_RETIRED.L1_MISS",
@@ -531,8 +429,6 @@
     },
     {
         "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_RETIRED.L2_HIT",
@@ -543,8 +439,6 @@
     },
     {
         "BriefDescription": "Retired load instructions missed L2 cache as data sources",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_RETIRED.L2_MISS",
@@ -555,8 +449,6 @@
     },
     {
         "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_RETIRED.L3_HIT",
@@ -567,8 +459,6 @@
     },
     {
         "BriefDescription": "Retired load instructions missed L3 cache as data sources",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xD1",
         "EventName": "MEM_LOAD_RETIRED.L3_MISS",
@@ -579,8 +469,6 @@
     },
     {
         "BriefDescription": "Demand and prefetch data reads",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
         "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
@@ -589,8 +477,6 @@
     },
     {
         "BriefDescription": "Any memory transaction that reached the SQ.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
         "PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..",
@@ -599,8 +485,6 @@
     },
     {
         "BriefDescription": "Cacheable and noncachaeble code read requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
         "PublicDescription": "Counts both cacheable and non-cacheable code read requests.",
@@ -609,8 +493,6 @@
     },
     {
         "BriefDescription": "Demand Data Read requests sent to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
         "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
@@ -619,8 +501,6 @@
     },
     {
         "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
         "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
@@ -629,8 +509,6 @@
     },
     {
         "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB2",
         "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
         "PublicDescription": "Counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entries.",
@@ -639,8 +517,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
         "PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
@@ -649,8 +525,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
@@ -660,8 +534,6 @@
     },
     {
         "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
@@ -671,8 +543,6 @@
     },
     {
         "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
@@ -682,8 +552,6 @@
     },
     {
         "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
@@ -693,8 +561,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
         "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
@@ -703,8 +569,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
         "PublicDescription": "Counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the promotion point.",
@@ -713,8 +577,6 @@
     },
     {
         "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "6",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
@@ -723,8 +585,6 @@
     },
     {
         "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
         "PublicDescription": "Counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
@@ -733,8 +593,6 @@
     },
     {
         "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
@@ -743,872 +601,654 @@
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads that have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads that have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads that hit in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs that have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs that hit in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs that have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that hit in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) that have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that have any response type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3F803C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of cache line split locks sent to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xF4",
         "EventName": "SQ_MISC.SPLIT_LOCK",
         "PublicDescription": "Counts the number of cache line split locks sent to the uncore.",
@@ -1617,8 +1257,6 @@
     },
     {
         "BriefDescription": "Number of PREFETCHNTA instructions executed.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.NTA",
         "SampleAfterValue": "2000003",
@@ -1626,8 +1264,6 @@
     },
     {
         "BriefDescription": "Number of PREFETCHW instructions executed.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
         "SampleAfterValue": "2000003",
@@ -1635,8 +1271,6 @@
     },
     {
         "BriefDescription": "Number of PREFETCHT0 instructions executed.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.T0",
         "SampleAfterValue": "2000003",
@@ -1644,8 +1278,6 @@
     },
     {
         "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.T1_T2",
         "SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json b/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json
index 09810e3d688cf..64dd36387209e 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
         "PublicDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
         "PublicDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
         "PublicDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
         "PublicDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -41,8 +33,6 @@
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
         "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -51,8 +41,6 @@
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
         "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -61,8 +49,6 @@
     },
     {
         "BriefDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
         "PublicDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -71,8 +57,6 @@
     },
     {
         "BriefDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC7",
         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
         "PublicDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -81,8 +65,6 @@
     },
     {
         "BriefDescription": "Cycles with any input/output SSE or FP assist",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xCA",
         "EventName": "FP_ASSIST.ANY",
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/frontend.json b/tools/perf/pmu-events/arch/x86/skylakex/frontend.json
index 8633ee406813a..13ccf50db43df 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/frontend.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xE6",
         "EventName": "BACLEARS.ANY",
         "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAB",
         "EventName": "DSB2MITE_SWITCHES.COUNT",
         "PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAB",
         "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
         "PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Retired Instructions who experienced DSB miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
         "MSRIndex": "0x3F7",
@@ -40,13 +32,10 @@
         "PEBS": "1",
         "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.DSB_MISS",
         "MSRIndex": "0x3F7",
@@ -54,13 +43,10 @@
         "PEBS": "1",
         "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.ITLB_MISS",
         "MSRIndex": "0x3F7",
@@ -68,39 +54,30 @@
         "PEBS": "1",
         "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.L1I_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x12",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.L2_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x13",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
         "MSRIndex": "0x3F7",
@@ -108,26 +85,20 @@
         "PEBS": "2",
         "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x408006",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
         "MSRIndex": "0x3F7",
@@ -135,39 +106,30 @@
         "PEBS": "1",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x400206",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x410006",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
         "MSRIndex": "0x3F7",
@@ -175,39 +137,30 @@
         "PEBS": "1",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x200206",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x300206",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
         "MSRIndex": "0x3F7",
@@ -215,52 +168,40 @@
         "PEBS": "1",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x400406",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x420006",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x404006",
         "PEBS": "1",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
         "MSRIndex": "0x3F7",
@@ -268,13 +209,10 @@
         "PEBS": "1",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC6",
         "EventName": "FRONTEND_RETIRED.STLB_MISS",
         "MSRIndex": "0x3F7",
@@ -282,13 +220,10 @@
         "PEBS": "1",
         "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x80",
         "EventName": "ICACHE_16B.IFDATA_STALL",
         "PublicDescription": "Cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.",
@@ -297,8 +232,6 @@
     },
     {
         "BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x83",
         "EventName": "ICACHE_64B.IFTAG_HIT",
         "SampleAfterValue": "200003",
@@ -306,8 +239,6 @@
     },
     {
         "BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x83",
         "EventName": "ICACHE_64B.IFTAG_MISS",
         "SampleAfterValue": "200003",
@@ -315,8 +246,6 @@
     },
     {
         "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x83",
         "EventName": "ICACHE_64B.IFTAG_STALL",
         "SampleAfterValue": "200003",
@@ -324,8 +253,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -335,8 +262,6 @@
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -346,8 +271,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering 4 Uops",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -357,8 +280,6 @@
     },
     {
         "BriefDescription": "Cycles MITE is delivering any Uop",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -368,8 +289,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_CYCLES",
@@ -379,8 +298,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_UOPS",
         "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.",
@@ -389,8 +306,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_CYCLES",
@@ -400,8 +315,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_UOPS",
         "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@@ -410,8 +323,6 @@
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_CYCLES",
@@ -421,8 +332,6 @@
     },
     {
         "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_DSB_CYCLES",
@@ -432,8 +341,6 @@
     },
     {
         "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_MITE_UOPS",
         "PublicDescription": "Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.",
@@ -442,8 +349,6 @@
     },
     {
         "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
@@ -454,8 +359,6 @@
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_UOPS",
         "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
@@ -464,8 +367,6 @@
     },
     {
         "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
         "PublicDescription": "Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4  x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions).  c. Instruction Decode Queue (IDQ) delivers four uops.",
@@ -474,8 +375,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -485,8 +384,6 @@
     },
     {
         "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@@ -496,8 +393,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@@ -507,8 +402,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@@ -518,8 +411,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x9C",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/memory.json b/tools/perf/pmu-events/arch/x86/skylakex/memory.json
index a570fe3e7a2d3..2b797dbc75fe0 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/memory.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "6",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.ABORTED",
         "PEBS": "1",
@@ -32,8 +26,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.ABORTED_EVENTS",
         "SampleAfterValue": "2000003",
@@ -41,8 +33,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.ABORTED_MEM",
         "SampleAfterValue": "2000003",
@@ -50,8 +40,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.ABORTED_MEMTYPE",
         "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.",
@@ -60,8 +48,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.ABORTED_TIMER",
         "SampleAfterValue": "2000003",
@@ -69,8 +55,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
         "SampleAfterValue": "2000003",
@@ -78,8 +62,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution successfully committed",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.COMMIT",
         "PublicDescription": "Number of times HLE commit succeeded.",
@@ -88,8 +70,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE execution started.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC8",
         "EventName": "HLE_RETIRED.START",
         "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.",
@@ -98,8 +78,6 @@
     },
     {
         "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL089",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
@@ -109,8 +87,6 @@
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
@@ -119,13 +95,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "1009",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
@@ -134,13 +107,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "20011",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
@@ -149,13 +119,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "503",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
@@ -164,13 +131,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
@@ -179,13 +143,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "100003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
@@ -194,13 +155,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "101",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
@@ -209,13 +167,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "2003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
@@ -224,13 +179,10 @@
         "PEBS": "2",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "50021",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Demand Data Read requests who miss L3 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
         "PublicDescription": "Demand Data Read requests who miss L3 cache.",
@@ -239,8 +191,6 @@
     },
     {
         "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
@@ -249,8 +199,6 @@
     },
     {
         "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
         "SampleAfterValue": "2000003",
@@ -258,8 +206,6 @@
     },
     {
         "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "6",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
@@ -268,872 +214,654 @@
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63FC00491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800491",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads that miss in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63FC00490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800490",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs that miss in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63FC00120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800120",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63FC00122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800122",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that miss in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local or remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63FC00004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that miss in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that miss the L3 and the modified data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local or remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63FC00001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63FC00002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63FC00400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63FC00010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63FC00020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63FC00080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800080",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3FBC000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103FC00100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x83FC00100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63FC00100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x604000100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x63B800100",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.ABORTED",
         "PEBS": "1",
@@ -1143,8 +871,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.ABORTED_EVENTS",
         "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
@@ -1153,8 +879,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.ABORTED_MEM",
         "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
@@ -1163,8 +887,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
         "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.",
@@ -1173,8 +895,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.ABORTED_TIMER",
         "SampleAfterValue": "2000003",
@@ -1182,8 +902,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
         "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.",
@@ -1192,8 +910,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution successfully committed",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.COMMIT",
         "PublicDescription": "Number of times RTM commit succeeded.",
@@ -1202,8 +918,6 @@
     },
     {
         "BriefDescription": "Number of times an RTM execution started.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC9",
         "EventName": "RTM_RETIRED.START",
         "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.",
@@ -1212,8 +926,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC1",
         "SampleAfterValue": "2000003",
@@ -1221,8 +933,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC2",
         "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
@@ -1231,8 +941,6 @@
     },
     {
         "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC3",
         "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
@@ -1241,8 +949,6 @@
     },
     {
         "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC4",
         "PublicDescription": "RTM region detected inside HLE.",
@@ -1251,8 +957,6 @@
     },
     {
         "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC5",
         "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
@@ -1261,8 +965,6 @@
     },
     {
         "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CAPACITY",
         "SampleAfterValue": "2000003",
@@ -1270,8 +972,6 @@
     },
     {
         "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CONFLICT",
         "PublicDescription": "Number of times a TSX line had a cache conflict.",
@@ -1280,8 +980,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
         "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
@@ -1290,8 +988,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
         "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
@@ -1300,8 +996,6 @@
     },
     {
         "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
         "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
@@ -1310,8 +1004,6 @@
     },
     {
         "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
         "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
@@ -1320,8 +1012,6 @@
     },
     {
         "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x54",
         "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
         "PublicDescription": "Number of times we could not allocate Lock Buffer.",
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/other.json b/tools/perf/pmu-events/arch/x86/skylakex/other.json
index 403805e7e5813..cda8a7a45f0c0 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/other.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/other.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
         "PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
         "PublicDescription": "Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
         "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture).  This includes high current AVX 512-bit instructions.",
@@ -31,8 +25,6 @@
     },
     {
         "BriefDescription": "Core cycles the core was throttled due to a pending power level request.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x28",
         "EventName": "CORE_POWER.THROTTLE",
         "PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.",
@@ -41,8 +33,6 @@
     },
     {
         "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDFE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xEF",
         "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE",
         "SampleAfterValue": "2000003",
@@ -50,8 +40,6 @@
     },
     {
         "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xEF",
         "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM",
         "SampleAfterValue": "2000003",
@@ -59,8 +47,6 @@
     },
     {
         "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITFSE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xEF",
         "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE",
         "SampleAfterValue": "2000003",
@@ -68,8 +54,6 @@
     },
     {
         "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITI",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xEF",
         "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI",
         "SampleAfterValue": "2000003",
@@ -77,8 +61,6 @@
     },
     {
         "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDFE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xEF",
         "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE",
         "SampleAfterValue": "2000003",
@@ -86,8 +68,6 @@
     },
     {
         "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDM",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xEF",
         "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM",
         "SampleAfterValue": "2000003",
@@ -95,8 +75,6 @@
     },
     {
         "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SHITFSE",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xEF",
         "EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE",
         "SampleAfterValue": "2000003",
@@ -104,8 +82,6 @@
     },
     {
         "BriefDescription": "Number of hardware interrupts received by the processor.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCB",
         "EventName": "HW_INTERRUPTS.RECEIVED",
         "PublicDescription": "Counts the number of hardware interruptions received by the processor.",
@@ -114,8 +90,6 @@
     },
     {
         "BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xFE",
         "EventName": "IDI_MISC.WB_DOWNGRADE",
         "PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.",
@@ -124,8 +98,6 @@
     },
     {
         "BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xFE",
         "EventName": "IDI_MISC.WB_UPGRADE",
         "PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.",
@@ -134,8 +106,6 @@
     },
     {
         "BriefDescription": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x09",
         "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
         "SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json b/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json
index f085b9145952c..64e1fe3513331 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x14",
         "EventName": "ARITH.DIVIDER_ACTIVE",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "All (macro) branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "All (macro) branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
@@ -33,8 +27,6 @@
     },
     {
         "BriefDescription": "Conditional branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.CONDITIONAL",
@@ -45,8 +37,6 @@
     },
     {
         "BriefDescription": "Not taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.COND_NTAKEN",
@@ -56,8 +46,6 @@
     },
     {
         "BriefDescription": "Far branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.FAR_BRANCH",
@@ -68,8 +56,6 @@
     },
     {
         "BriefDescription": "Direct and indirect near call instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL",
@@ -80,8 +66,6 @@
     },
     {
         "BriefDescription": "Return instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_RETURN",
@@ -92,8 +76,6 @@
     },
     {
         "BriefDescription": "Taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
@@ -104,8 +86,6 @@
     },
     {
         "BriefDescription": "Not taken branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NOT_TAKEN",
@@ -115,8 +95,6 @@
     },
     {
         "BriefDescription": "All mispredicted macro branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch.  When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
@@ -124,8 +102,6 @@
     },
     {
         "BriefDescription": "Mispredicted macro branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
         "PEBS": "2",
@@ -135,8 +111,6 @@
     },
     {
         "BriefDescription": "Mispredicted conditional branch instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -146,8 +120,6 @@
     },
     {
         "BriefDescription": "Mispredicted direct and indirect near call instructions retired.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -157,8 +129,6 @@
     },
     {
         "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
@@ -167,8 +137,6 @@
     },
     {
         "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.RET",
         "PEBS": "1",
@@ -178,8 +146,6 @@
     },
     {
         "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "25003",
@@ -187,8 +153,6 @@
     },
     {
         "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
         "SampleAfterValue": "25003",
@@ -197,8 +161,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
         "SampleAfterValue": "25003",
@@ -206,8 +168,6 @@
     },
     {
         "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
         "SampleAfterValue": "25003",
@@ -215,8 +175,6 @@
     },
     {
         "BriefDescription": "Reference cycles when the core is not in halt state.",
-        "Counter": "Fixed counter 2",
-        "CounterHTOff": "Fixed counter 2",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
         "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
         "SampleAfterValue": "2000003",
@@ -224,8 +182,6 @@
     },
     {
         "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
         "SampleAfterValue": "25003",
@@ -234,8 +190,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
         "SampleAfterValue": "25003",
@@ -243,8 +197,6 @@
     },
     {
         "BriefDescription": "Counts when there is a transition from ring 1, 2 or 3 to ring 0.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x3C",
@@ -254,8 +206,6 @@
     },
     {
         "BriefDescription": "Core cycles when the thread is not in halt state",
-        "Counter": "Fixed counter 1",
-        "CounterHTOff": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD",
         "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
         "SampleAfterValue": "2000003",
@@ -264,16 +214,12 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
-        "Counter": "Fixed counter 1",
-        "CounterHTOff": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Thread cycles when thread is not in halt state",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
         "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
@@ -282,16 +228,12 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "8",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
@@ -300,8 +242,6 @@
     },
     {
         "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
@@ -310,8 +250,6 @@
     },
     {
         "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "16",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
@@ -320,8 +258,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "12",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
@@ -330,8 +266,6 @@
     },
     {
         "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "5",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
@@ -340,8 +274,6 @@
     },
     {
         "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
         "CounterMask": "20",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
@@ -350,8 +282,6 @@
     },
     {
         "BriefDescription": "Total execution stalls.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xA3",
         "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
@@ -360,8 +290,6 @@
     },
     {
         "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA6",
         "EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
         "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
@@ -370,8 +298,6 @@
     },
     {
         "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA6",
         "EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
         "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
@@ -380,8 +306,6 @@
     },
     {
         "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA6",
         "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
         "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
@@ -390,8 +314,6 @@
     },
     {
         "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA6",
         "EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
         "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
@@ -400,8 +322,6 @@
     },
     {
         "BriefDescription": "Cycles where the Store Buffer was full and no outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA6",
         "EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
         "SampleAfterValue": "2000003",
@@ -409,8 +329,6 @@
     },
     {
         "BriefDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA6",
         "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS",
         "PublicDescription": "Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty.",
@@ -419,8 +337,6 @@
     },
     {
         "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.LCP",
         "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
@@ -429,8 +345,6 @@
     },
     {
         "BriefDescription": "Instruction decoders utilized in a cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x55",
         "EventName": "INST_DECODED.DECODERS",
         "PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
@@ -439,8 +353,6 @@
     },
     {
         "BriefDescription": "Instructions retired from execution.",
-        "Counter": "Fixed counter 0",
-        "CounterHTOff": "Fixed counter 0",
         "EventName": "INST_RETIRED.ANY",
         "PublicDescription": "Counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
         "SampleAfterValue": "2000003",
@@ -448,8 +360,6 @@
     },
     {
         "BriefDescription": "Number of instructions retired. General Counter - architectural event",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091, SKL044",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.ANY_P",
@@ -458,8 +368,6 @@
     },
     {
         "BriefDescription": "Number of all retired NOP instructions.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "Errata": "SKL091, SKL044",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.NOP",
@@ -469,8 +377,6 @@
     },
     {
         "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
-        "Counter": "1",
-        "CounterHTOff": "1",
         "Errata": "SKL091, SKL044",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.PREC_DIST",
@@ -481,8 +387,6 @@
     },
     {
         "BriefDescription": "Number of cycles using always true condition applied to  PEBS instructions retired event.",
-        "Counter": "0,2,3",
-        "CounterHTOff": "0,2,3",
         "CounterMask": "10",
         "Errata": "SKL091, SKL044",
         "EventCode": "0xC0",
@@ -495,8 +399,6 @@
     },
     {
         "BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
         "SampleAfterValue": "2000003",
@@ -504,8 +406,6 @@
     },
     {
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES",
         "PublicDescription": "Core cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
@@ -515,8 +415,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0D",
         "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
         "SampleAfterValue": "2000003",
@@ -524,8 +422,6 @@
     },
     {
         "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.NO_SR",
         "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
@@ -534,8 +430,6 @@
     },
     {
         "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.STORE_FORWARD",
         "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
@@ -544,8 +438,6 @@
     },
     {
         "BriefDescription": "False dependencies in MOB due to partial compare on address.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x07",
         "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
         "PublicDescription": "Counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",
@@ -554,8 +446,6 @@
     },
     {
         "BriefDescription": "Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4C",
         "EventName": "LOAD_HIT_PRE.SW_PF",
         "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
@@ -564,8 +454,6 @@
     },
     {
         "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_4_UOPS",
@@ -575,8 +463,6 @@
     },
     {
         "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.CYCLES_ACTIVE",
@@ -586,8 +472,6 @@
     },
     {
         "BriefDescription": "Number of Uops delivered by the LSD.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA8",
         "EventName": "LSD.UOPS",
         "PublicDescription": "Number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
@@ -596,8 +480,6 @@
     },
     {
         "BriefDescription": "Number of machine clears (nukes) of any type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xC3",
@@ -607,8 +489,6 @@
     },
     {
         "BriefDescription": "Self-modifying code (SMC) detected.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.SMC",
         "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
@@ -617,8 +497,6 @@
     },
     {
         "BriefDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC1",
         "EventName": "OTHER_ASSISTS.ANY",
         "SampleAfterValue": "100003",
@@ -626,8 +504,6 @@
     },
     {
         "BriefDescription": "Cycles where the pipeline is stalled due to serializing operations.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x59",
         "EventName": "PARTIAL_RAT_STALLS.SCOREBOARD",
         "PublicDescription": "This event counts cycles during which the microcode scoreboard stalls happen.",
@@ -636,8 +512,6 @@
     },
     {
         "BriefDescription": "Resource-related stall cycles",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa2",
         "EventName": "RESOURCE_STALLS.ANY",
         "PublicDescription": "Counts resource-related stall cycles.",
@@ -646,8 +520,6 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.SB",
         "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
@@ -656,8 +528,6 @@
     },
     {
         "BriefDescription": "Increments whenever there is an update to the LBR array.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCC",
         "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
         "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.",
@@ -666,8 +536,6 @@
     },
     {
         "BriefDescription": "Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL products.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xCC",
         "EventName": "ROB_MISC_EVENTS.PAUSE_INST",
         "SampleAfterValue": "2000003",
@@ -675,8 +543,6 @@
     },
     {
         "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5E",
         "EventName": "RS_EVENTS.EMPTY_CYCLES",
         "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
@@ -685,8 +551,6 @@
     },
     {
         "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5E",
@@ -698,8 +562,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 0",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_0",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.",
@@ -708,8 +570,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 1",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_1",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.",
@@ -718,8 +578,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 2",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_2",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 2.",
@@ -728,8 +586,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_3",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 3.",
@@ -738,8 +594,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 4",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_4",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 4.",
@@ -748,8 +602,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 5",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_5",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.",
@@ -758,8 +610,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 6",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_6",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
@@ -768,8 +618,6 @@
     },
     {
         "BriefDescription": "Cycles per thread when uops are executed in port 7",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xA1",
         "EventName": "UOPS_DISPATCHED_PORT.PORT_7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 7.",
@@ -778,8 +626,6 @@
     },
     {
         "BriefDescription": "Number of uops executed on the core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE",
         "PublicDescription": "Number of uops executed from any thread.",
@@ -788,8 +634,6 @@
     },
     {
         "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@@ -798,8 +642,6 @@
     },
     {
         "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@@ -808,8 +650,6 @@
     },
     {
         "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@@ -818,8 +658,6 @@
     },
     {
         "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@@ -828,8 +666,6 @@
     },
     {
         "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
@@ -839,8 +675,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
@@ -850,8 +684,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
@@ -861,8 +693,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
@@ -872,8 +702,6 @@
     },
     {
         "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
@@ -883,8 +711,6 @@
     },
     {
         "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.STALL_CYCLES",
@@ -895,8 +721,6 @@
     },
     {
         "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.THREAD",
         "PublicDescription": "Number of uops to be executed per-thread each cycle.",
@@ -905,8 +729,6 @@
     },
     {
         "BriefDescription": "Counts the number of x87 uops dispatched.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.X87",
         "PublicDescription": "Counts the number of x87 uops executed.",
@@ -915,8 +737,6 @@
     },
     {
         "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.ANY",
         "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
@@ -925,8 +745,6 @@
     },
     {
         "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.SLOW_LEA",
         "SampleAfterValue": "2000003",
@@ -934,8 +752,6 @@
     },
     {
         "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -946,8 +762,6 @@
     },
     {
         "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0E",
         "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
         "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.",
@@ -956,8 +770,6 @@
     },
     {
         "BriefDescription": "Number of macro-fused uops retired. (non precise)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.MACRO_FUSED",
         "PublicDescription": "Counts the number of macro-fused uops retired. (non precise)",
@@ -966,8 +778,6 @@
     },
     {
         "BriefDescription": "Retirement slots used.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
         "PublicDescription": "Counts the retirement slots used.",
@@ -976,8 +786,6 @@
     },
     {
         "BriefDescription": "Cycles without actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -988,8 +796,6 @@
     },
     {
         "BriefDescription": "Cycles with less than 10 actually retired uops.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "16",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json b/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json
index bc8e42554096c..1f8d60cce3cee 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json
@@ -1,1513 +1,1497 @@
 [
     {
-        "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
-        "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS",
-        "MetricGroup": "PGO;TopdownL1;tma_L1_group",
-        "MetricName": "tma_frontend_bound",
-        "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
+        "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
+        "MetricGroup": "Bad;BadSpec;BrMispredicts",
+        "MetricName": "Mispredictions"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
-        "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS",
-        "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
-        "MetricName": "tma_fetch_latency",
-        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
+        "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))",
+        "MetricGroup": "Mem;MemoryBW;Offcore",
+        "MetricName": "Memory_Bandwidth"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses",
-        "MetricExpr": "(ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@) / CLKS",
-        "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_icache_misses",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
+        "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound))",
+        "MetricGroup": "Mem;MemoryLat;Offcore",
+        "MetricName": "Memory_Latency"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses",
-        "MetricExpr": "ICACHE_64B.IFTAG_STALL / CLKS",
-        "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_itlb_misses",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
+        "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)))",
+        "MetricGroup": "Mem;MemoryTLB;Offcore",
+        "MetricName": "Memory_Data_TLBs"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
-        "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CLKS + tma_unknown_branches",
-        "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_branch_resteers",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)",
+        "MetricExpr": "100 * ((BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)",
+        "MetricGroup": "Ret",
+        "MetricName": "Branching_Overhead"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage",
-        "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
-        "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group",
-        "MetricName": "tma_mispredicts_resteers",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage.  Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)",
+        "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)",
+        "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB",
+        "MetricName": "Big_Code"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears",
-        "MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT))) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
-        "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group",
-        "MetricName": "tma_clears_resteers",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears.  Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks",
+        "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code",
+        "MetricGroup": "Fed;FetchBW;Frontend",
+        "MetricName": "Instruction_Fetch_BW"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
-        "MetricExpr": "9 * BACLEARS.ANY / CLKS",
-        "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_branch_resteers_group",
-        "MetricName": "tma_unknown_branches",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: BACLEARS.ANY",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
+        "MetricExpr": "INST_RETIRED.ANY / CLKS",
+        "MetricGroup": "Ret;Summary",
+        "MetricName": "IPC"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
-        "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS",
-        "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_dsb_switches",
-        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Uops Per Instruction",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
+        "MetricGroup": "Pipeline;Ret;Retire",
+        "MetricName": "UPI"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
-        "MetricExpr": "ILD_STALL.LCP / CLKS",
-        "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_lcp",
-        "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instruction per taken branch",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
+        "MetricGroup": "Branches;Fed;FetchBW",
+        "MetricName": "UpTB"
     },
     {
-        "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
-        "MetricExpr": "2 * IDQ.MS_SWITCHES / CLKS",
-        "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group",
-        "MetricName": "tma_ms_switches",
-        "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
+        "MetricExpr": "1 / IPC",
+        "MetricGroup": "Mem;Pipeline",
+        "MetricName": "CPI"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
-        "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
-        "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
-        "MetricName": "tma_fetch_bandwidth",
-        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues.  For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "Pipeline",
+        "MetricName": "CLKS"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
-        "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
-        "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
-        "MetricName": "tma_mite",
-        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
+        "MetricExpr": "4 * CORE_CLKS",
+        "MetricGroup": "tma_L1_group",
+        "MetricName": "SLOTS"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder",
-        "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) / CORE_CLKS",
-        "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_mite_group",
-        "MetricName": "tma_decoder0_alone",
-        "ScaleUnit": "100%"
+        "BriefDescription": "The ratio of Executed- by Issued-Uops",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
+        "MetricGroup": "Cor;Pipeline",
+        "MetricName": "Execute_per_Issue",
+        "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
-        "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2",
-        "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
-        "MetricName": "tma_dsb",
-        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline.  For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
+        "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
+        "MetricGroup": "Ret;SMT;tma_L1_group",
+        "MetricName": "CoreIPC"
     },
     {
-        "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
-        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
-        "MetricGroup": "TopdownL1;tma_L1_group",
-        "MetricName": "tma_bad_speculation",
-        "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Floating Point Operations Per Cycle",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS",
+        "MetricGroup": "Flops;Ret",
+        "MetricName": "FLOPc"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
-        "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
-        "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
-        "MetricName": "tma_branch_mispredicts",
-        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
+        "MetricGroup": "Cor;Flops;HPC",
+        "MetricName": "FP_Arith_Utilization",
+        "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
-        "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
-        "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group",
-        "MetricName": "tma_machine_clears",
-        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears.  These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
+        "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
+        "MetricName": "ILP"
     },
     {
-        "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
-        "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
-        "MetricGroup": "TopdownL1;tma_L1_group",
-        "MetricName": "tma_backend_bound",
-        "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
+        "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)",
+        "MetricGroup": "Cor;SMT",
+        "MetricName": "Core_Bound_Likely"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
-        "MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * tma_backend_bound",
-        "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
-        "MetricName": "tma_memory_bound",
-        "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
+        "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
+        "MetricGroup": "SMT",
+        "MetricName": "CORE_CLKS"
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
-        "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CLKS, 0)",
-        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_l1_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache.  The L1 data cache typically has the shortest latency.  However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS",
+        "MetricGroup": "InsType",
+        "MetricName": "IpLoad"
     },
     {
-        "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
-        "MetricExpr": "min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / CLKS",
-        "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_dtlb_load",
-        "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES",
+        "MetricGroup": "InsType",
+        "MetricName": "IpStore"
     },
     {
-        "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
-        "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
-        "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group",
-        "MetricName": "tma_load_stlb_hit",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Branches;Fed;InsType",
+        "MetricName": "IpBranch"
     },
     {
-        "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk",
-        "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CLKS",
-        "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group",
-        "MetricName": "tma_load_stlb_miss",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
+        "MetricGroup": "Branches;Fed;PGO",
+        "MetricName": "IpCall"
     },
     {
-        "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
-        "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS",
-        "MetricGroup": "TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_store_fwd_blk",
-        "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instruction per taken branch",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
+        "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
+        "MetricName": "IpTB"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
-        "MetricExpr": "(12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * (11 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
-        "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_lock_latency",
-        "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Branch instructions per taken branch. ",
+        "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
+        "MetricGroup": "Branches;Fed;PGO",
+        "MetricName": "BpTkBranch"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary",
-        "MetricExpr": "Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS",
-        "MetricGroup": "TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_split_loads",
-        "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary.  Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
+        "MetricGroup": "Flops;InsType",
+        "MetricName": "IpFLOP"
     },
     {
-        "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
-        "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CLKS",
-        "MetricGroup": "TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_4k_aliasing",
-        "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))",
+        "MetricGroup": "Flops;InsType",
+        "MetricName": "IpArith",
+        "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
     },
     {
-        "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
-        "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / CLKS",
-        "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group",
-        "MetricName": "tma_fb_full",
-        "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
+        "MetricGroup": "Flops;FpScalar;InsType",
+        "MetricName": "IpArith_Scalar_SP",
+        "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
-        "MetricExpr": "((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / ((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@)) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS)",
-        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_l2_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
+        "MetricGroup": "Flops;FpScalar;InsType",
+        "MetricName": "IpArith_Scalar_DP",
+        "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
-        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / CLKS",
-        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_l3_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)",
+        "MetricGroup": "Flops;FpVector;InsType",
+        "MetricName": "IpArith_AVX128",
+        "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
-        "MetricExpr": "((44 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + (44 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_contested_accesses",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
+        "MetricGroup": "Flops;FpVector;InsType",
+        "MetricName": "IpArith_AVX256",
+        "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
-        "MetricExpr": "(44 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD)))) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_data_sharing",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
+        "MetricGroup": "Flops;FpVector;InsType",
+        "MetricName": "IpArith_AVX512",
+        "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
-        "MetricExpr": "(17 * Average_Frequency) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_l3_hit_latency",
-        "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@",
+        "MetricGroup": "Prefetches",
+        "MetricName": "IpSWPF"
     },
     {
-        "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
-        "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
-        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
-        "MetricName": "tma_sq_full",
-        "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
+        "MetricExpr": "INST_RETIRED.ANY",
+        "MetricGroup": "Summary;tma_L1_group",
+        "MetricName": "Instructions"
     },
     {
-        "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
-        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS) - tma_l2_bound)",
-        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_dram_bound",
-        "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
+        "MetricGroup": "Pipeline;Ret",
+        "MetricName": "Retire"
+    },
+    {
+        "BriefDescription": "",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
+        "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
+        "MetricName": "Execute"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
-        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / CLKS",
-        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group",
-        "MetricName": "tma_mem_bandwidth",
-        "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM).  The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average number of Uops issued by front-end when it issued something",
+        "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@",
+        "MetricGroup": "Fed;FetchBW",
+        "MetricName": "Fetch_UpC"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
-        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth",
-        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group",
-        "MetricName": "tma_mem_latency",
-        "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM).  This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
+        "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
+        "MetricGroup": "DSB;Fed;FetchBW",
+        "MetricName": "DSB_Coverage"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
-        "MetricExpr": "(59.5 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "Server;TopdownL5;tma_mem_latency_group",
-        "MetricName": "tma_local_dram",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
+        "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHES.COUNT",
+        "MetricGroup": "DSBmiss",
+        "MetricName": "DSB_Switch_Cost"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
-        "MetricExpr": "(127 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "Server;Snoop;TopdownL5;tma_mem_latency_group",
-        "MetricName": "tma_remote_dram",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
+        "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))",
+        "MetricGroup": "DSBmiss;Fed",
+        "MetricName": "DSB_Misses"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
-        "MetricExpr": "((89.5 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + (89.5 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
-        "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_mem_latency_group",
-        "MetricName": "tma_remote_cache",
-        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS",
+        "MetricGroup": "DSBmiss;Fed",
+        "MetricName": "IpDSB_Miss_Ret"
     },
     {
-        "BriefDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
-        "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CLKS",
-        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
-        "MetricName": "tma_store_bound",
-        "PublicDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
+        "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;BadSpec;BrMispredicts",
+        "MetricName": "IpMispredict"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
-        "MetricExpr": "((L2_RQSTS.RFO_HIT * 11 * (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES))) + (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
-        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_store_latency",
-        "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
+        "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;BrMispredicts",
+        "MetricName": "Branch_Misprediction_Cost"
     },
     {
-        "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
-        "MetricExpr": "((110 * Average_Frequency) * (OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM) + (47.5 * Average_Frequency) * (OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE)) / CLKS",
-        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_false_sharing",
-        "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line.  Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of branches that are non-taken conditionals",
+        "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;Branches;CodeGen;PGO",
+        "MetricName": "Cond_NT"
     },
     {
-        "BriefDescription": "This metric represents rate of split store accesses",
-        "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CORE_CLKS",
-        "MetricGroup": "TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_split_stores",
-        "PublicDescription": "This metric represents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of branches that are taken conditionals",
+        "MetricExpr": "(BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) / BR_INST_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;Branches;CodeGen;PGO",
+        "MetricName": "Cond_TK"
     },
     {
-        "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
-        "MetricExpr": "(9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CORE_CLKS",
-        "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group",
-        "MetricName": "tma_dtlb_store",
-        "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead.  Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page.  Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of branches that are CALL or RET",
+        "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;Branches",
+        "MetricName": "CallRet"
     },
     {
-        "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
-        "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
-        "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group",
-        "MetricName": "tma_store_stlb_hit",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps",
+        "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES",
+        "MetricGroup": "Bad;Branches",
+        "MetricName": "Jump"
     },
     {
-        "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk",
-        "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS",
-        "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group",
-        "MetricName": "tma_store_stlb_miss",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
+        "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)",
+        "MetricGroup": "Mem;MemoryBound;MemoryLat",
+        "MetricName": "Load_Miss_Real_Latency"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
-        "MetricExpr": "tma_backend_bound - tma_memory_bound",
-        "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group",
-        "MetricName": "tma_core_bound",
-        "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
+        "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
+        "MetricGroup": "Mem;MemoryBW;MemoryBound",
+        "MetricName": "MLP"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
-        "MetricExpr": "ARITH.DIVIDER_ACTIVE / CLKS",
-        "MetricGroup": "TopdownL3;tma_core_bound_group",
-        "MetricName": "tma_divider",
-        "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L1MPKI"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
-        "MetricExpr": "(EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if (ARITH.DIVIDER_ACTIVE < (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY)) else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CLKS",
-        "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
-        "MetricName": "tma_ports_utilization",
-        "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
+        "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L1MPKI_Load"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_NONE / 2 if #SMT_on else CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CORE_CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_0",
-        "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+        "MetricGroup": "Backend;CacheMisses;Mem",
+        "MetricName": "L2MPKI"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations",
-        "MetricExpr": "PARTIAL_RAT_STALLS.SCOREBOARD / CLKS",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_0_group",
-        "MetricName": "tma_serializing_operation",
-        "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: PARTIAL_RAT_STALLS.SCOREBOARD",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
+        "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem;Offcore",
+        "MetricName": "L2MPKI_All"
     },
     {
-        "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued",
-        "MetricExpr": "CLKS * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_0_group",
-        "MetricName": "tma_mixing_vectors",
-        "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (including speculative)",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L2MPKI_Load"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2) / 2 if #SMT_on else EXE_ACTIVITY.1_PORTS_UTIL) / CORE_CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_1",
-        "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
+        "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L2HPKI_All"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
-        "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3) / 2 if #SMT_on else EXE_ACTIVITY.2_PORTS_UTIL) / CORE_CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_2",
-        "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L2 cache hits per kilo instruction for all demand loads  (including speculative)",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L2HPKI_Load"
     },
     {
-        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
-        "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_3) / CORE_CLKS",
-        "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
-        "MetricName": "tma_ports_utilized_3m",
-        "ScaleUnit": "100%"
+        "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "L3MPKI"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
-        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / (4 * CORE_CLKS)",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
-        "MetricName": "tma_alu_op_utilization",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
+        "MetricGroup": "CacheMisses;Mem",
+        "MetricName": "FB_HPKI"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED_PORT.PORT_0",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS",
-        "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group",
-        "MetricName": "tma_port_0",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
+        "MetricConstraint": "NO_NMI_WATCHDOG",
+        "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING) / (2 * CORE_CLKS)",
+        "MetricGroup": "Mem;MemoryTLB",
+        "MetricName": "Page_Walks_Utilization"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_1",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
-        "MetricName": "tma_port_1",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
+        "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L1D_Cache_Fill_BW"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) Sample with: UOPS_DISPATCHED.PORT_5",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
-        "MetricName": "tma_port_5",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
+        "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L2_Cache_Fill_BW"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_6",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
-        "MetricName": "tma_port_6",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
+        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L3_Cache_Fill_BW"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3",
-        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
-        "MetricName": "tma_load_op_utilization",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
+        "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time",
+        "MetricGroup": "Mem;MemoryBW;Offcore",
+        "MetricName": "L3_Cache_Access_BW"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_2",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_load_op_utilization_group",
-        "MetricName": "tma_port_2",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
+        "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / Instructions",
+        "MetricGroup": "L2Evicts;Mem;Server",
+        "MetricName": "L2_Evictions_Silent_PKI"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_3",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_load_op_utilization_group",
-        "MetricName": "tma_port_3",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
+        "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / Instructions",
+        "MetricGroup": "L2Evicts;Mem;Server",
+        "MetricName": "L2_Evictions_NonSilent_PKI"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
-        "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
-        "MetricName": "tma_store_op_utilization",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
+        "MetricExpr": "L1D_Cache_Fill_BW",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L1D_Cache_Fill_BW_1T"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data) Sample with: UOPS_DISPATCHED_PORT.PORT_4",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_store_op_utilization_group",
-        "MetricName": "tma_port_4",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
+        "MetricExpr": "L2_Cache_Fill_BW",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L2_Cache_Fill_BW_1T"
     },
     {
-        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address) Sample with: UOPS_DISPATCHED_PORT.PORT_7",
-        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS",
-        "MetricGroup": "TopdownL6;tma_store_op_utilization_group",
-        "MetricName": "tma_port_7",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
+        "MetricExpr": "L3_Cache_Fill_BW",
+        "MetricGroup": "Mem;MemoryBW",
+        "MetricName": "L3_Cache_Fill_BW_1T"
     },
     {
-        "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
-        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS",
-        "MetricGroup": "TopdownL1;tma_L1_group",
-        "MetricName": "tma_retiring",
-        "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided.  Sample with: UOPS_RETIRED.RETIRE_SLOTS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
+        "MetricExpr": "L3_Cache_Access_BW",
+        "MetricGroup": "Mem;MemoryBW;Offcore",
+        "MetricName": "L3_Cache_Access_BW_1T"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
-        "MetricExpr": "tma_retiring - tma_heavy_operations",
-        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
-        "MetricName": "tma_light_operations",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average CPU Utilization",
+        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+        "MetricGroup": "HPC;Summary",
+        "MetricName": "CPU_Utilization"
     },
     {
-        "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
-        "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector",
-        "MetricGroup": "HPC;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_fp_arith",
-        "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
+        "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
+        "MetricGroup": "Power;Summary",
+        "MetricName": "Average_Frequency"
     },
     {
-        "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
-        "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD",
-        "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group",
-        "MetricName": "tma_x87_use",
-        "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Giga Floating Point Operations Per Second",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time",
+        "MetricGroup": "Cor;Flops;HPC",
+        "MetricName": "GFLOPs",
+        "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
     },
     {
-        "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / UOPS_RETIRED.RETIRE_SLOTS",
-        "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group",
-        "MetricName": "tma_fp_scalar",
-        "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average Frequency Utilization relative nominal frequency",
+        "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
+        "MetricGroup": "Power",
+        "MetricName": "Turbo_Utilization"
     },
     {
-        "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS",
-        "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group",
-        "MetricName": "tma_fp_vector",
-        "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0",
+        "MetricExpr": "(CORE_POWER.LVL0_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL0_TURBO_LICENSE / CORE_CLKS)",
+        "MetricGroup": "Power",
+        "MetricName": "Power_License0_Utilization",
+        "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes."
     },
     {
-        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS",
-        "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
-        "MetricName": "tma_fp_vector_128b",
-        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1",
+        "MetricExpr": "(CORE_POWER.LVL1_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL1_TURBO_LICENSE / CORE_CLKS)",
+        "MetricGroup": "Power",
+        "MetricName": "Power_License1_Utilization",
+        "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions."
     },
     {
-        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS",
-        "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
-        "MetricName": "tma_fp_vector_256b",
-        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)",
+        "MetricExpr": "(CORE_POWER.LVL2_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL2_TURBO_LICENSE / CORE_CLKS)",
+        "MetricGroup": "Power",
+        "MetricName": "Power_License2_Utilization",
+        "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX).  This includes high current AVX 512-bit instructions."
     },
     {
-        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
-        "MetricExpr": "(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS",
-        "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
-        "MetricName": "tma_fp_vector_512b",
-        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
+        "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
+        "MetricGroup": "SMT",
+        "MetricName": "SMT_2T_Utilization"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.",
-        "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY",
-        "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_memory_operations",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "OS",
+        "MetricName": "Kernel_Utilization"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions",
-        "MetricExpr": "tma_light_operations * UOPS_RETIRED.MACRO_FUSED / UOPS_RETIRED.RETIRE_SLOTS",
-        "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_fused_instructions",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
+        "MetricGroup": "OS",
+        "MetricName": "Kernel_CPI"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused",
-        "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS",
-        "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_non_fused_branches",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
+        "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time",
+        "MetricGroup": "HPC;Mem;MemoryBW;SoC",
+        "MetricName": "DRAM_BW_Use"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions",
-        "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / UOPS_RETIRED.RETIRE_SLOTS",
-        "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_nop_instructions",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
+        "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (Socket_CLKS / duration_time)",
+        "MetricGroup": "Mem;MemoryLat;SoC",
+        "MetricName": "MEM_Read_Latency"
     },
     {
-        "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting",
-        "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions))",
-        "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
-        "MetricName": "tma_other_light_ops",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
+        "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@thresh\\=1@",
+        "MetricGroup": "Mem;MemoryBW;SoC",
+        "MetricName": "MEM_Parallel_Reads"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
-        "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / SLOTS",
-        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
-        "MetricName": "tma_heavy_operations",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
+        "MetricExpr": "1e9 * (UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSERTS) / imc_0@event\\=0x0@",
+        "MetricGroup": "Mem;MemoryLat;Server;SoC",
+        "MetricName": "MEM_DRAM_Read_Latency"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops",
-        "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer",
-        "MetricGroup": "TopdownL3;tma_heavy_operations_group",
-        "MetricName": "tma_few_uops_instructions",
-        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]",
+        "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1e9 / duration_time",
+        "MetricGroup": "IoBW;Mem;Server;SoC",
+        "MetricName": "IO_Write_BW"
     },
     {
-        "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
-        "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
-        "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
-        "MetricName": "tma_microcode_sequencer",
-        "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]",
+        "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3) * 4 / 1e9 / duration_time",
+        "MetricGroup": "IoBW;Mem;Server;SoC",
+        "MetricName": "IO_Read_BW"
     },
     {
-        "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
-        "MetricExpr": "100 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / SLOTS",
-        "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
-        "MetricName": "tma_assists",
-        "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Socket actual clocks when any core is active on that socket",
+        "MetricExpr": "cha_0@event\\=0x0@",
+        "MetricGroup": "SoC",
+        "MetricName": "Socket_CLKS"
     },
     {
-        "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
-        "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
-        "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
-        "MetricName": "tma_cisc",
-        "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
-        "ScaleUnit": "100%"
+        "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
+        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
+        "MetricGroup": "Branches;OS",
+        "MetricName": "IpFarBranch"
     },
     {
-        "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
-        "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
-        "MetricGroup": "Bad;BadSpec;BrMispredicts",
-        "MetricName": "Mispredictions"
+        "BriefDescription": "Uncore frequency per die [GHZ]",
+        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+        "MetricGroup": "SoC",
+        "MetricName": "UNCORE_FREQ"
     },
     {
-        "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) ",
-        "MetricGroup": "Mem;MemoryBW;Offcore",
-        "MetricName": "Memory_Bandwidth"
+        "BriefDescription": "Percentage of time spent in the active CPU power state C0",
+        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+        "MetricName": "cpu_utilization",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + (tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)))",
-        "MetricGroup": "Mem;MemoryLat;Offcore",
-        "MetricName": "Memory_Latency"
+        "BriefDescription": "CPU operating frequency (in GHz)",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / duration_time",
+        "MetricName": "cpu_operating_frequency",
+        "ScaleUnit": "1GHz"
     },
     {
-        "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency))) ",
-        "MetricGroup": "Mem;MemoryTLB;Offcore",
-        "MetricName": "Memory_Data_TLBs"
+        "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY",
+        "MetricName": "cpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)",
-        "MetricExpr": "100 * ((BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)",
-        "MetricGroup": "Ret",
-        "MetricName": "Branching_Overhead"
+        "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
+        "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
+        "MetricName": "loads_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)",
-        "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)",
-        "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB",
-        "MetricName": "Big_Code"
+        "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
+        "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY",
+        "MetricName": "stores_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks",
-        "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code",
-        "MetricGroup": "Fed;FetchBW;Frontend",
-        "MetricName": "Instruction_Fetch_BW"
+        "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
+        "MetricName": "l1d_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
-        "MetricExpr": "INST_RETIRED.ANY / CLKS",
-        "MetricGroup": "Ret;Summary",
-        "MetricName": "IPC"
+        "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ",
+        "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY",
+        "MetricName": "l1d_demand_data_read_hits_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Uops Per Instruction",
-        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
-        "MetricGroup": "Pipeline;Ret;Retire",
-        "MetricName": "UPI"
+        "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
+        "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
+        "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instruction per taken branch",
-        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
-        "MetricGroup": "Branches;Fed;FetchBW",
-        "MetricName": "UpTB"
+        "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ",
+        "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY",
+        "MetricName": "l2_demand_data_read_hits_per_instr",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
-        "MetricExpr": "1 / IPC",
-        "MetricGroup": "Mem;Pipeline",
-        "MetricName": "CPI"
+        "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
+        "MetricName": "l2_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
-        "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
-        "MetricGroup": "Pipeline",
-        "MetricName": "CLKS"
+        "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
+        "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+        "MetricName": "l2_demand_data_read_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
-        "MetricExpr": "4 * CORE_CLKS",
-        "MetricGroup": "tma_L1_group",
-        "MetricName": "SLOTS"
+        "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
+        "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
+        "MetricName": "l2_demand_code_mpi",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "The ratio of Executed- by Issued-Uops",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
-        "MetricGroup": "Cor;Pipeline",
-        "MetricName": "Execute_per_Issue",
-        "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
+        "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x12D4043300000000@ / INST_RETIRED.ANY",
+        "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
-        "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
-        "MetricGroup": "Ret;SMT;tma_L1_group",
-        "MetricName": "CoreIPC"
+        "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+        "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x12CC023300000000@ / INST_RETIRED.ANY",
+        "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Floating Point Operations Per Cycle",
-        "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS",
-        "MetricGroup": "Flops;Ret",
-        "MetricName": "FLOPc"
+        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds",
+        "MetricExpr": "1e9 * (cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043300000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043300000000@) / (UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time",
+        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency",
+        "ScaleUnit": "1ns"
     },
     {
-        "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
-        "MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
-        "MetricGroup": "Cor;Flops;HPC",
-        "MetricName": "FP_Arith_Utilization",
-        "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
+        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds",
+        "MetricExpr": "1e9 * (cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043200000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@) / (UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time",
+        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests",
+        "ScaleUnit": "1ns"
     },
     {
-        "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / ((UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
-        "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
-        "MetricName": "ILP"
+        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds",
+        "MetricExpr": "1e9 * (cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043100000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@) / (UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time",
+        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests",
+        "ScaleUnit": "1ns"
     },
     {
-        "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
-        "MetricExpr": "(1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0",
-        "MetricGroup": "Cor;SMT",
-        "MetricName": "Core_Bound_Likely"
+        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions",
+        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+        "MetricName": "itlb_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
-        "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
-        "MetricGroup": "SMT",
-        "MetricName": "CORE_CLKS"
+        "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions",
+        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+        "MetricName": "itlb_large_page_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS",
-        "MetricGroup": "InsType",
-        "MetricName": "IpLoad"
+        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions",
+        "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+        "MetricName": "dtlb_load_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES",
-        "MetricGroup": "InsType",
-        "MetricName": "IpStore"
+        "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions",
+        "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+        "MetricName": "dtlb_2mb_large_page_load_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Branches;Fed;InsType",
-        "MetricName": "IpBranch"
+        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions",
+        "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+        "MetricName": "dtlb_store_mpi",
+        "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+        "ScaleUnit": "1per_instr"
     },
     {
-        "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
-        "MetricGroup": "Branches;Fed;PGO",
-        "MetricName": "IpCall"
+        "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+        "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ / (cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@)",
+        "MetricName": "numa_reads_addressed_to_local_dram",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instruction per taken branch",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
-        "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
-        "MetricName": "IpTB"
+        "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+        "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@ / (cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@)",
+        "MetricName": "numa_reads_addressed_to_remote_dram",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Branch instructions per taken branch. ",
-        "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
-        "MetricGroup": "Branches;Fed;PGO",
-        "MetricName": "BpTkBranch"
+        "BriefDescription": "Uncore operating frequency in GHz",
+        "MetricExpr": "UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages) / 1e9 / duration_time",
+        "MetricName": "uncore_frequency",
+        "ScaleUnit": "1GHz"
     },
     {
-        "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
-        "MetricGroup": "Flops;InsType",
-        "MetricName": "IpFLOP"
+        "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)",
+        "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 7.111111111111111 / 1e6 / duration_time",
+        "MetricName": "upi_data_transmit_bw",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))",
-        "MetricGroup": "Flops;InsType",
-        "MetricName": "IpArith",
-        "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
+        "BriefDescription": "DDR memory read bandwidth (MB/sec)",
+        "MetricExpr": "UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time",
+        "MetricName": "memory_bandwidth_read",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
-        "MetricGroup": "Flops;FpScalar;InsType",
-        "MetricName": "IpArith_Scalar_SP",
-        "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "DDR memory write bandwidth (MB/sec)",
+        "MetricExpr": "UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time",
+        "MetricName": "memory_bandwidth_write",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
-        "MetricGroup": "Flops;FpScalar;InsType",
-        "MetricName": "IpArith_Scalar_DP",
-        "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "DDR memory bandwidth (MB/sec)",
+        "MetricExpr": "(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time",
+        "MetricName": "memory_bandwidth_total",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)",
-        "MetricGroup": "Flops;FpVector;InsType",
-        "MetricName": "IpArith_AVX128",
-        "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
+        "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1e6 / duration_time",
+        "MetricName": "io_bandwidth_disk_or_network_writes",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
-        "MetricGroup": "Flops;FpVector;InsType",
-        "MetricName": "IpArith_AVX256",
-        "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
+        "MetricExpr": "(UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3) * 4 / 1e6 / duration_time",
+        "MetricName": "io_bandwidth_disk_or_network_reads",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
-        "MetricGroup": "Flops;FpVector;InsType",
-        "MetricName": "IpArith_AVX512",
-        "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+        "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
+        "MetricExpr": "IDQ.DSB_UOPS / UOPS_ISSUED.ANY",
+        "MetricName": "percent_uops_delivered_from_decoded_icache",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@",
-        "MetricGroup": "Prefetches",
-        "MetricName": "IpSWPF"
+        "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
+        "MetricExpr": "IDQ.MITE_UOPS / UOPS_ISSUED.ANY",
+        "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
-        "MetricExpr": "INST_RETIRED.ANY",
-        "MetricGroup": "Summary;tma_L1_group",
-        "MetricName": "Instructions"
+        "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
+        "MetricExpr": "IDQ.MS_UOPS / UOPS_ISSUED.ANY",
+        "MetricName": "percent_uops_delivered_from_microcode_sequencer",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
-        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
-        "MetricGroup": "Pipeline;Ret",
-        "MetricName": "Retire"
+        "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.",
+        "MetricExpr": "UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1e6 / duration_time",
+        "MetricName": "llc_miss_local_memory_bandwidth_read",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
-        "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
-        "MetricName": "Execute"
+        "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.",
+        "MetricExpr": "UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1e6 / duration_time",
+        "MetricName": "llc_miss_local_memory_bandwidth_write",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Average number of Uops issued by front-end when it issued something",
-        "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@",
-        "MetricGroup": "Fed;FetchBW",
-        "MetricName": "Fetch_UpC"
+        "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.",
+        "MetricExpr": "UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1e6 / duration_time",
+        "MetricName": "llc_miss_remote_memory_bandwidth_read",
+        "ScaleUnit": "1MB/s"
     },
     {
-        "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
-        "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
-        "MetricGroup": "DSB;Fed;FetchBW",
-        "MetricName": "DSB_Coverage"
+        "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
+        "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS",
+        "MetricGroup": "PGO;TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_frontend_bound",
+        "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
-        "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHES.COUNT",
-        "MetricGroup": "DSBmiss",
-        "MetricName": "DSB_Switch_Cost"
+        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
+        "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS",
+        "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+        "MetricName": "tma_fetch_latency",
+        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
-        "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))",
-        "MetricGroup": "DSBmiss;Fed",
-        "MetricName": "DSB_Misses"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.",
+        "MetricExpr": "(ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_icache_misses",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS",
-        "MetricGroup": "DSBmiss;Fed",
-        "MetricName": "IpDSB_Miss_Ret"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.",
+        "MetricExpr": "ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_itlb_misses",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;BadSpec;BrMispredicts",
-        "MetricName": "IpMispredict"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
+        "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + tma_unknown_branches",
+        "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_branch_resteers",
+        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
-        "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;BrMispredicts",
-        "MetricName": "Branch_Misprediction_Cost"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ",
+        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+        "MetricName": "tma_mispredicts_resteers",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of branches that are non-taken conditionals",
-        "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;Branches;CodeGen;PGO",
-        "MetricName": "Cond_NT"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ",
+        "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+        "MetricName": "tma_clears_resteers",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of branches that are taken conditionals",
-        "MetricExpr": "(BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) / BR_INST_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;Branches;CodeGen;PGO",
-        "MetricName": "Cond_TK"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
+        "MetricExpr": "9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+        "MetricName": "tma_unknown_branches",
+        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of branches that are CALL or RET",
-        "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;Branches",
-        "MetricName": "CallRet"
+        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
+        "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_dsb_switches",
+        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps",
-        "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES",
-        "MetricGroup": "Bad;Branches",
-        "MetricName": "Jump"
+        "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
+        "MetricExpr": "ILD_STALL.LCP / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_lcp",
+        "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
-        "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)",
-        "MetricGroup": "Mem;MemoryBound;MemoryLat",
-        "MetricName": "Load_Miss_Real_Latency"
+        "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
+        "MetricExpr": "2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+        "MetricName": "tma_ms_switches",
+        "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
-        "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
-        "MetricGroup": "Mem;MemoryBW;MemoryBound",
-        "MetricName": "MLP"
+        "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
+        "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
+        "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+        "MetricName": "tma_fetch_bandwidth",
+        "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues.  For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L1MPKI"
+        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
+        "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
+        "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+        "MetricName": "tma_mite",
+        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L1MPKI_Load"
+        "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder",
+        "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=0x1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=0x2@) / CORE_CLKS",
+        "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group",
+        "MetricName": "tma_decoder0_alone",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "Backend;CacheMisses;Mem",
-        "MetricName": "L2MPKI"
+        "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
+        "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2",
+        "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+        "MetricName": "tma_dsb",
+        "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline.  For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem;Offcore",
-        "MetricName": "L2MPKI_All"
+        "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
+        "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+        "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_bad_speculation",
+        "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L2MPKI_Load"
+        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
+        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
+        "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+        "MetricName": "tma_branch_mispredicts",
+        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
-        "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L2HPKI_All"
+        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
+        "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
+        "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+        "MetricName": "tma_machine_clears",
+        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears.  These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.",
+        "ScaleUnit": "100%"
+    },
+    {
+        "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
+        "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+        "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_backend_bound",
+        "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L2 cache hits per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L2HPKI_Load"
+        "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
+        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + UOPS_RETIRED.RETIRE_SLOTS / SLOTS * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound",
+        "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+        "MetricName": "tma_memory_bound",
+        "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "L3MPKI"
+        "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
+        "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CPU_CLK_UNHALTED.THREAD, 0)",
+        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_l1_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache.  The L1 data cache typically has the shortest latency.  However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
-        "MetricGroup": "CacheMisses;Mem",
-        "MetricName": "FB_HPKI"
+        "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
+        "MetricExpr": "min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_dtlb_load",
+        "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
-        "MetricConstraint": "NO_NMI_WATCHDOG",
-        "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING) / (2 * CORE_CLKS)",
-        "MetricGroup": "Mem;MemoryTLB",
-        "MetricName": "Page_Walks_Utilization"
+        "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
+        "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
+        "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group",
+        "MetricName": "tma_load_stlb_hit",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
-        "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L1D_Cache_Fill_BW"
+        "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk",
+        "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group",
+        "MetricName": "tma_load_stlb_miss",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
-        "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L2_Cache_Fill_BW"
+        "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
+        "MetricExpr": "min(13 * LD_BLOCKS.STORE_FORWARD / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_store_fwd_blk",
+        "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L3_Cache_Fill_BW"
+        "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
+        "MetricExpr": "min((12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (11 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_lock_latency",
+        "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time",
-        "MetricGroup": "Mem;MemoryBW;Offcore",
-        "MetricName": "L3_Cache_Access_BW"
+        "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ",
+        "MetricExpr": "min(Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_split_loads",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
-        "MetricExpr": "1000 * L2_LINES_OUT.SILENT / Instructions",
-        "MetricGroup": "L2Evicts;Mem;Server",
-        "MetricName": "L2_Evictions_Silent_PKI"
+        "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
+        "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_4k_aliasing",
+        "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
-        "MetricExpr": "1000 * L2_LINES_OUT.NON_SILENT / Instructions",
-        "MetricGroup": "L2Evicts;Mem;Server",
-        "MetricName": "L2_Evictions_NonSilent_PKI"
+        "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
+        "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group",
+        "MetricName": "tma_fb_full",
+        "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
-        "MetricExpr": "L1D_Cache_Fill_BW",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L1D_Cache_Fill_BW_1T"
+        "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
+        "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD)",
+        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_l2_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
-        "MetricExpr": "L2_Cache_Fill_BW",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L2_Cache_Fill_BW_1T"
+        "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
+        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_l3_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core.  Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "L3_Cache_Fill_BW",
-        "MetricGroup": "Mem;MemoryBW",
-        "MetricName": "L3_Cache_Fill_BW_1T"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
+        "MetricExpr": "min(((47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + (47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_contested_accesses",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "L3_Cache_Access_BW",
-        "MetricGroup": "Mem;MemoryBW;Offcore",
-        "MetricName": "L3_Cache_Access_BW_1T"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
+        "MetricExpr": "min((47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_data_sharing",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average CPU Utilization",
-        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
-        "MetricGroup": "HPC;Summary",
-        "MetricName": "CPU_Utilization"
+        "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
+        "MetricExpr": "min((20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_l3_hit_latency",
+        "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
-        "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
-        "MetricGroup": "Power;Summary",
-        "MetricName": "Average_Frequency"
+        "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
+        "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
+        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group",
+        "MetricName": "tma_sq_full",
+        "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Giga Floating Point Operations Per Second",
-        "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1000000000) / duration_time",
-        "MetricGroup": "Cor;Flops;HPC",
-        "MetricName": "GFLOPs",
-        "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
+        "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
+        "MetricExpr": "min(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound, 1)",
+        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_dram_bound",
+        "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average Frequency Utilization relative nominal frequency",
-        "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
-        "MetricGroup": "Power",
-        "MetricName": "Turbo_Utilization"
+        "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
+        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+        "MetricName": "tma_mem_bandwidth",
+        "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM).  The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0",
-        "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL0_TURBO_LICENSE / CORE_CLKS",
-        "MetricGroup": "Power",
-        "MetricName": "Power_License0_Utilization",
-        "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes."
+        "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
+        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CPU_CLK_UNHALTED.THREAD - tma_mem_bandwidth",
+        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+        "MetricName": "tma_mem_latency",
+        "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM).  This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1",
-        "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL1_TURBO_LICENSE / CORE_CLKS",
-        "MetricGroup": "Power",
-        "MetricName": "Power_License1_Utilization",
-        "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions."
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
+        "MetricExpr": "min((80 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group",
+        "MetricName": "tma_local_dram",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)",
-        "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL2_TURBO_LICENSE / CORE_CLKS",
-        "MetricGroup": "Power",
-        "MetricName": "Power_License2_Utilization",
-        "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX).  This includes high current AVX 512-bit instructions."
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
+        "MetricExpr": "min((147.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+        "MetricName": "tma_remote_dram",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
-        "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
-        "MetricGroup": "SMT",
-        "MetricName": "SMT_2T_Utilization"
+        "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
+        "MetricExpr": "min(((110 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + (110 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+        "MetricName": "tma_remote_cache",
+        "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
-        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
-        "MetricGroup": "OS",
-        "MetricName": "Kernel_Utilization"
+        "BriefDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
+        "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+        "MetricName": "tma_store_bound",
+        "PublicDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
-        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
-        "MetricGroup": "OS",
-        "MetricName": "Kernel_CPI"
+        "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
+        "MetricExpr": "(L2_RQSTS.RFO_HIT * 11 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_store_latency",
+        "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
-        "MetricExpr": "(64 * (uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@) / 1000000000) / duration_time",
-        "MetricGroup": "HPC;Mem;MemoryBW;SoC",
-        "MetricName": "DRAM_BW_Use"
+        "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
+        "MetricExpr": "min((110 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) * (OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM) + 47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) * (OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE)) / CPU_CLK_UNHALTED.THREAD, 1)",
+        "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_false_sharing",
+        "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
-        "MetricExpr": "1000000000 * (cha@event\\=0x36\\,umask\\=0x21\\,config\\=0x40433@ / cha@event\\=0x35\\,umask\\=0x21\\,config\\=0x40433@) / (Socket_CLKS / duration_time)",
-        "MetricGroup": "Mem;MemoryLat;SoC",
-        "MetricName": "MEM_Read_Latency"
+        "BriefDescription": "This metric represents rate of split store accesses",
+        "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CORE_CLKS",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_split_stores",
+        "PublicDescription": "This metric represents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granularity.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
-        "MetricExpr": "cha@event\\=0x36\\,umask\\=0x21\\,config\\=0x40433@ / cha@event\\=0x36\\,umask\\=0x21\\,config\\=0x40433\\,thresh\\=1@",
-        "MetricGroup": "Mem;MemoryBW;SoC",
-        "MetricName": "MEM_Parallel_Reads"
+        "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
+        "MetricExpr": "min((9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CORE_CLKS, 1)",
+        "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group",
+        "MetricName": "tma_dtlb_store",
+        "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead.  Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page.  Try using larger page sizes for large amounts of frequently-used data.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
-        "MetricExpr": "1000000000 * (UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSERTS) / imc_0@event\\=0x0@",
-        "MetricGroup": "Mem;MemoryLat;Server;SoC",
-        "MetricName": "MEM_DRAM_Read_Latency"
+        "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
+        "MetricExpr": "tma_dtlb_store - DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS",
+        "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group",
+        "MetricName": "tma_store_stlb_hit",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]",
-        "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1000000000 / duration_time",
-        "MetricGroup": "IoBW;Mem;Server;SoC",
-        "MetricName": "IO_Write_BW"
+        "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk",
+        "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS",
+        "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group",
+        "MetricName": "tma_store_stlb_miss",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]",
-        "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3) * 4 / 1000000000 / duration_time",
-        "MetricGroup": "IoBW;Mem;Server;SoC",
-        "MetricName": "IO_Read_BW"
+        "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
+        "MetricExpr": "tma_backend_bound - tma_memory_bound",
+        "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+        "MetricName": "tma_core_bound",
+        "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Socket actual clocks when any core is active on that socket",
-        "MetricExpr": "cha_0@event\\=0x0@",
-        "MetricGroup": "SoC",
-        "MetricName": "Socket_CLKS"
+        "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
+        "MetricExpr": "ARITH.DIVIDER_ACTIVE / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group",
+        "MetricName": "tma_divider",
+        "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
-        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
-        "MetricGroup": "Branches;OS",
-        "MetricName": "IpFarBranch"
+        "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
+        "MetricExpr": "((EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + UOPS_RETIRED.RETIRE_SLOTS / SLOTS * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + UOPS_RETIRED.RETIRE_SLOTS / SLOTS * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD)",
+        "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group",
+        "MetricName": "tma_ports_utilization",
+        "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C3 residency percent per core",
-        "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C3_Core_Residency"
+        "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+        "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_NONE / 2 if #SMT_on else CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CORE_CLKS",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_0",
+        "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C6 residency percent per core",
-        "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C6_Core_Residency"
+        "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations",
+        "MetricExpr": "PARTIAL_RAT_STALLS.SCOREBOARD / CPU_CLK_UNHALTED.THREAD",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group",
+        "MetricName": "tma_serializing_operation",
+        "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C7 residency percent per core",
-        "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C7_Core_Residency"
+        "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued",
+        "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY, 1)",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group",
+        "MetricName": "tma_mixing_vectors",
+        "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C2 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C2_Pkg_Residency"
+        "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+        "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2) / 2 if #SMT_on else EXE_ACTIVITY.1_PORTS_UTIL) / CORE_CLKS",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_1",
+        "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C3 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C3_Pkg_Residency"
+        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+        "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3) / 2 if #SMT_on else EXE_ACTIVITY.2_PORTS_UTIL) / CORE_CLKS",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_2",
+        "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C6 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C6_Pkg_Residency"
+        "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
+        "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_3) / CORE_CLKS",
+        "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+        "MetricName": "tma_ports_utilized_3m",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "C7 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
-        "MetricGroup": "Power",
-        "MetricName": "C7_Pkg_Residency"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
+        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+        "MetricName": "tma_alu_op_utilization",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uncore frequency per die [GHZ]",
-        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000",
-        "MetricGroup": "SoC",
-        "MetricName": "UNCORE_FREQ"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS",
+        "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+        "MetricName": "tma_port_0",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "CPU operating frequency (in GHz)",
-        "MetricExpr": "(( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ ) / 1000000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "cpu_operating_frequency",
-        "ScaleUnit": "1GHz"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+        "MetricName": "tma_port_1",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
-        "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "loads_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+        "MetricName": "tma_port_5",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
-        "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "stores_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+        "MetricName": "tma_port_6",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l1d_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations",
+        "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+        "MetricName": "tma_load_op_utilization",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ",
-        "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l1d_demand_data_read_hits_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group",
+        "MetricName": "tma_port_2",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
-        "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group",
+        "MetricName": "tma_port_3",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ",
-        "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_demand_data_read_hits_per_instr",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
+        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+        "MetricName": "tma_store_op_utilization",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)",
+        "MetricExpr": "tma_store_op_utilization",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group",
+        "MetricName": "tma_port_4",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
-        "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_demand_data_read_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)",
+        "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS",
+        "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group",
+        "MetricName": "tma_port_7",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
-        "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "l2_demand_code_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS",
+        "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+        "MetricName": "tma_retiring",
+        "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x12D4043300000000@ / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
+        "MetricExpr": "tma_retiring - (UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / SLOTS",
+        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+        "MetricName": "tma_light_operations",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
-        "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x12CC023300000000@ / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
+        "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD + tma_fp_scalar + tma_fp_vector",
+        "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_fp_arith",
+        "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds",
-        "MetricExpr": "( 1000000000 * ( cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043300000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043300000000@ ) / ( UNC_CHA_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency",
-        "ScaleUnit": "1ns"
+        "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
+        "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD",
+        "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group",
+        "MetricName": "tma_x87_use",
+        "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds",
-        "MetricExpr": "( 1000000000 * ( cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043200000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ ) / ( UNC_CHA_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests",
-        "ScaleUnit": "1ns"
+        "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / UOPS_RETIRED.RETIRE_SLOTS",
+        "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group",
+        "MetricName": "tma_fp_scalar",
+        "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds",
-        "MetricExpr": "( 1000000000 * ( cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043100000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@ ) / ( UNC_CHA_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests",
-        "ScaleUnit": "1ns"
+        "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
+        "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)",
+        "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group",
+        "MetricName": "tma_fp_vector",
+        "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
-        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "itlb_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
+        "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)",
+        "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+        "MetricName": "tma_fp_vector_128b",
+        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
-        "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "itlb_large_page_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
+        "MetricExpr": "min((FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)",
+        "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+        "MetricName": "tma_fp_vector_256b",
+        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
-        "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "dtlb_load_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
+        "MetricExpr": "min((FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)",
+        "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+        "MetricName": "tma_fp_vector_512b",
+        "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.",
-        "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "dtlb_2mb_large_page_load_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.",
+        "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY",
+        "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_memory_operations",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
-        "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
-        "MetricGroup": "",
-        "MetricName": "dtlb_store_mpi",
-        "ScaleUnit": "1per_instr"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions",
+        "MetricExpr": "tma_light_operations * UOPS_RETIRED.MACRO_FUSED / UOPS_RETIRED.RETIRE_SLOTS",
+        "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_fused_instructions",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
-        "MetricExpr": "100 * cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ / ( cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@ )",
-        "MetricGroup": "",
-        "MetricName": "numa_reads_addressed_to_local_dram",
-        "ScaleUnit": "1%"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused",
+        "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS",
+        "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_non_fused_branches",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
-        "MetricExpr": "100 * cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@ / ( cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@ )",
-        "MetricGroup": "",
-        "MetricName": "numa_reads_addressed_to_remote_dram",
-        "ScaleUnit": "1%"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions",
+        "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / UOPS_RETIRED.RETIRE_SLOTS",
+        "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_nop_instructions",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uncore operating frequency in GHz",
-        "MetricExpr": "( UNC_CHA_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) / 1000000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "uncore_frequency",
-        "ScaleUnit": "1GHz"
+        "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting",
+        "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions))",
+        "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+        "MetricName": "tma_other_light_ops",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_UPI_TxL_FLITS.ALL_DATA * (64 / 9.0) / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "upi_data_transmit_bw",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
+        "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / SLOTS",
+        "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+        "MetricName": "tma_heavy_operations",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "DDR memory read bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "memory_bandwidth_read",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops",
+        "MetricExpr": "tma_heavy_operations - UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
+        "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group",
+        "MetricName": "tma_few_uops_instructions",
+        "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "DDR memory write bandwidth (MB/sec)",
-        "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "memory_bandwidth_write",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
+        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
+        "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group",
+        "MetricName": "tma_microcode_sequencer",
+        "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "DDR memory bandwidth (MB/sec)",
-        "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "memory_bandwidth_total",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
+        "MetricExpr": "min(100 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / SLOTS, 1)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+        "MetricName": "tma_assists",
+        "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
-        "MetricExpr": "(( UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 ) * 4 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "io_bandwidth_disk_or_network_writes",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
+        "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
+        "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+        "MetricName": "tma_cisc",
+        "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
-        "MetricExpr": "(( UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3 ) * 4 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "io_bandwidth_disk_or_network_reads",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "C3 residency percent per core",
+        "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C3_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
-        "MetricExpr": "100 * ( IDQ.DSB_UOPS / UOPS_ISSUED.ANY )",
-        "MetricGroup": "",
-        "MetricName": "percent_uops_delivered_from_decoded_icache",
-        "ScaleUnit": "1%"
+        "BriefDescription": "C6 residency percent per core",
+        "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C6_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
-        "MetricExpr": "100 * ( IDQ.MITE_UOPS / UOPS_ISSUED.ANY )",
-        "MetricGroup": "",
-        "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
-        "ScaleUnit": "1%"
+        "BriefDescription": "C7 residency percent per core",
+        "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C7_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
-        "MetricExpr": "100 * ( IDQ.MS_UOPS / UOPS_ISSUED.ANY )",
-        "MetricGroup": "",
-        "MetricName": "percent_uops_delivered_from_microcode_sequencer",
-        "ScaleUnit": "1%"
+        "BriefDescription": "C2 residency percent per package",
+        "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C2_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.",
-        "MetricExpr": "( UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_miss_local_memory_bandwidth_read",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "C3 residency percent per package",
+        "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C3_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.",
-        "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_miss_local_memory_bandwidth_write",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "C6 residency percent per package",
+        "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C6_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
-        "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.",
-        "MetricExpr": "( UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1000000) / duration_time",
-        "MetricGroup": "",
-        "MetricName": "llc_miss_remote_memory_bandwidth_read",
-        "ScaleUnit": "1MB/s"
+        "BriefDescription": "C7 residency percent per package",
+        "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
+        "MetricGroup": "Power",
+        "MetricName": "C7_Pkg_Residency",
+        "ScaleUnit": "100%"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json b/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json
index 62941146e3967..8784118123b49 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json
@@ -1,540 +1,514 @@
 [
-    {
-        "BriefDescription": "DRAM Page Activate commands sent due to a write request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_M_ACT_COUNT.WR",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "All DRAM Read CAS Commands issued (does not include underfills)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.RD_REG",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "DRAM Underfill Read CAS Commands issued",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "All DRAM Read CAS Commands issued (including underfills)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.RD",
-        "PerPkg": "1",
-        "UMask": "0x3",
-        "Unit": "iMC"
-    },
     {
         "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "LLC_MISSES.MEM_READ",
         "PerPkg": "1",
+        "PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per channel basis.  CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every read.  This event includes underfill reads due to partial write requests.  This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write)  is enabled or not.",
         "ScaleUnit": "64Bytes",
         "UMask": "0x3",
         "Unit": "iMC"
     },
-    {
-        "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.WR_WMM",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "All DRAM Write CAS commands issued",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.WR",
-        "PerPkg": "1",
-        "UMask": "0xC",
-        "Unit": "iMC"
-    },
     {
         "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "LLC_MISSES.MEM_WRITE",
         "PerPkg": "1",
+        "PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory channel.  CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.",
         "ScaleUnit": "64Bytes",
-        "UMask": "0xC",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "All DRAM CAS Commands issued",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.ALL",
+        "BriefDescription": "DRAM Activate Count; Activate due to Bypass",
+        "EventCode": "0x1",
+        "EventName": "UNC_M_ACT_COUNT.BYP",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Memory controller clock ticks",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_M_CLOCKTICKS",
+        "BriefDescription": "DRAM Activate Count; Activate due to Read",
+        "EventCode": "0x1",
+        "EventName": "UNC_M_ACT_COUNT.RD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x85",
-        "EventName": "UNC_M_POWER_CHANNEL_PPD",
-        "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.",
-        "MetricName": "power_channel_ppd %",
+        "BriefDescription": "DRAM Page Activate commands sent due to a write request",
+        "EventCode": "0x1",
+        "EventName": "UNC_M_ACT_COUNT.WR",
         "PerPkg": "1",
+        "PublicDescription": "Counts DRAM Page Activate commands sent on this channel due to a write request to the iMC (Memory Controller).  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS (Column Access Select) command.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Cycles Memory is in self refresh power mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x43",
-        "EventName": "UNC_M_POWER_SELF_REFRESH",
-        "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100.",
-        "MetricName": "power_self_refresh %",
+        "BriefDescription": "ACT command issued by 2 cycle bypass",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M_BYP_CMDS.ACT",
         "PerPkg": "1",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Pre-charges due to page misses",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+        "BriefDescription": "CAS command issued by 2 cycle bypass",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M_BYP_CMDS.CAS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Pre-charge for reads",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_M_PRE_COUNT.RD",
+        "BriefDescription": "PRE command issued by 2 cycle bypass",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M_BYP_CMDS.PRE",
         "PerPkg": "1",
         "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Pending Queue Allocations",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x10",
-        "EventName": "UNC_M_RPQ_INSERTS",
+        "BriefDescription": "All DRAM CAS Commands issued",
+        "EventCode": "0x4",
+        "EventName": "UNC_M_CAS_COUNT.ALL",
         "PerPkg": "1",
+        "PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory channel.  CAS commands are issued to specify the address to read or write on DRAM, so this event increments for every read and write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_M_RPQ_OCCUPANCY",
+        "BriefDescription": "All DRAM Read CAS Commands issued (including underfills)",
+        "EventCode": "0x4",
+        "EventName": "UNC_M_CAS_COUNT.RD",
         "PerPkg": "1",
+        "PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per channel basis.  CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every read.  This event includes underfill reads due to partial write requests.  This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write)  is enabled or not.",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Allocations",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_M_WPQ_INSERTS",
+        "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Read ISOCH Mode",
+        "EventCode": "0x4",
+        "EventName": "UNC_M_CAS_COUNT.RD_ISOCH",
         "PerPkg": "1",
+        "UMask": "0x40",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x81",
-        "EventName": "UNC_M_WPQ_OCCUPANCY",
+        "BriefDescription": "All DRAM Read CAS Commands issued (does not include underfills)",
+        "EventCode": "0x4",
+        "EventName": "UNC_M_CAS_COUNT.RD_REG",
         "PerPkg": "1",
+        "PublicDescription": "Counts CAS (Column Access Select) regular read commands issued to DRAM on a per channel basis.  CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every regular read.  This event only counts regular reads and does not includes underfill reads due to partial write requests.  This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write)  is enabled or not.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Activate Count; Activate due to Read",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_M_ACT_COUNT.RD",
+        "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in RMM",
+        "EventCode": "0x4",
+        "EventName": "UNC_M_CAS_COUNT.RD_RMM",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Activate Count; Activate due to Bypass",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_M_ACT_COUNT.BYP",
+        "BriefDescription": "DRAM Underfill Read CAS Commands issued",
+        "EventCode": "0x4",
+        "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts CAS (Column Access Select) underfill read commands issued to DRAM due to a partial write, on a per channel basis.  CAS commands are issued to specify the address to read or write on DRAM, and this command counts underfill reads.  Partial writes must be completed by first reading in the underfill from DRAM and then merging in the partial write data before writing the full line back to DRAM. This event will generally count about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ (due to a previous write request).",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "ACT command issued by 2 cycle bypass",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M_BYP_CMDS.ACT",
+        "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in WMM",
+        "EventCode": "0x4",
+        "EventName": "UNC_M_CAS_COUNT.RD_WMM",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "CAS command issued by 2 cycle bypass",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M_BYP_CMDS.CAS",
+        "BriefDescription": "All DRAM Write CAS commands issued",
+        "EventCode": "0x4",
+        "EventName": "UNC_M_CAS_COUNT.WR",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory channel.  CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "PRE command issued by 2 cycle bypass",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M_BYP_CMDS.PRE",
+        "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Write ISOCH Mode",
+        "EventCode": "0x4",
+        "EventName": "UNC_M_CAS_COUNT.WR_ISOCH",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0x80",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_M_CAS_COUNT.WR_RMM",
         "PerPkg": "1",
+        "PublicDescription": "Counts the total number of Opportunistic DRAM Write CAS commands issued on this channel while in Read-Major-Mode.",
         "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in WMM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.RD_WMM",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in RMM",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
         "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.RD_RMM",
+        "EventName": "UNC_M_CAS_COUNT.WR_WMM",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode.",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Read ISOCH Mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.RD_ISOCH",
+        "BriefDescription": "Memory controller clock ticks",
+        "EventName": "UNC_M_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts clockticks of the fixed frequency clock of the memory controller using one of the programmable counters.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Write ISOCH Mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_M_CAS_COUNT.WR_ISOCH",
+        "BriefDescription": "Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter",
+        "EventCode": "0xff",
+        "EventName": "UNC_M_CLOCKTICKS_F",
         "PerPkg": "1",
-        "UMask": "0x80",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "DRAM Precharge All Commands",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_M_DRAM_PRE_ALL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times that the precharge all command was sent.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Number of DRAM Refreshes Issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
-        "EventName": "UNC_M_DRAM_REFRESH.PANIC",
+        "EventName": "UNC_M_DRAM_REFRESH.HIGH",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the number of refreshes issued.",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Number of DRAM Refreshes Issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
-        "EventName": "UNC_M_DRAM_REFRESH.HIGH",
+        "EventName": "UNC_M_DRAM_REFRESH.PANIC",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the number of refreshes issued.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "ECC Correctable Errors",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of ECC errors detected and corrected by the iMC on this channel.  This counter is only useful with ECC DRAM devices.  This count will increment one time for each correction regardless of the number of bits corrected.  The iMC can correct up to 4 bit errors in independent channel mode and 8 bit errors in lockstep mode.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
         "EventCode": "0x7",
-        "EventName": "UNC_M_MAJOR_MODES.READ",
+        "EventName": "UNC_M_MAJOR_MODES.ISOCH",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group these two modes together so that we can use four counters to track each of the major modes at one time.  These major modes are used whenever there is an ISOCH txn in the memory controller.  In these mode, only ISOCH transactions are processed.",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
         "EventCode": "0x7",
-        "EventName": "UNC_M_MAJOR_MODES.WRITE",
+        "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode is used to drain starved underfill reads.  Regular reads and writes are blocked and only underfill reads will be processed.",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
         "EventCode": "0x7",
-        "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
+        "EventName": "UNC_M_MAJOR_MODES.READ",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode is the default mode for the iMC, as reads are generally more critical to forward progress than writes.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
         "EventCode": "0x7",
-        "EventName": "UNC_M_MAJOR_MODES.ISOCH",
+        "EventName": "UNC_M_MAJOR_MODES.WRITE",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is triggered when the WPQ hits high occupancy and causes writes to be higher priority than reads.  This can cause blips in the available read bandwidth in the system and temporarily increase read latencies in order to achieve better bus utilizations and higher bandwidth.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Channel DLLOFF Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x84",
         "EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode",
+        "EventCode": "0x85",
+        "EventName": "UNC_M_POWER_CHANNEL_PPD",
+        "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100",
+        "MetricName": "power_channel_ppd",
+        "PerPkg": "1",
+        "PublicDescription": "Counts cycles when all the ranks in the channel are in PPD (PreCharge Power Down) mode. If IBT (Input Buffer Terminators)=off is enabled, then this event counts the cycles in PPD mode. If IBT=off is not enabled, then this event counts the number of cycles when being in PPD mode could have been taken advantage of.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x4",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x8",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x10",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x20",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x40",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
         "UMask": "0x80",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Critical Throttle Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x86",
         "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the iMC is in critical thermal throttling.  When this happens, all traffic is blocked.  This should be rare unless something bad is going on in the platform.  There is no filtering by rank for this event.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "UNC_M_POWER_PCU_THROTTLING",
-        "Counter": "0,1,2,3",
         "EventCode": "0x42",
         "EventName": "UNC_M_POWER_PCU_THROTTLING",
         "PerPkg": "1",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "Cycles Memory is in self refresh power mode",
+        "EventCode": "0x43",
+        "EventName": "UNC_M_POWER_SELF_REFRESH",
+        "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100",
+        "MetricName": "power_self_refresh",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the iMC (memory controller) is in self-refresh and has a clock. This happens in some ACPI CPU package C-states for the sleep levels. For example, the PCU (Power Control Unit) may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Intel? Dynamic Power Technology.  Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.; Thermal throttling is performed per DIMM.  We support 3 DIMMs per channel.  This ID allows us to filter by ID.",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x4",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x8",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x10",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x20",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x40",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
-        "Counter": "0,1,2,3",
         "EventCode": "0x41",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
         "UMask": "0x80",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Read Preemption Count; Read over Read Preemption",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts another read.",
         "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Read Preemption Count; Read over Write Preemption",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts a write.",
         "UMask": "0x2",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
+        "EventCode": "0x2",
+        "EventName": "UNC_M_PRE_COUNT.BYP",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
+        "UMask": "0x10",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of the page close counter expiring.  This does not include implicit precharge commands sent in auto-precharge mode.",
         "UMask": "0x2",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "Pre-charges due to page misses",
+        "EventCode": "0x2",
+        "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of explicit DRAM Precharge commands sent on this channel as a result of a DRAM page miss. This does not include the implicit precharge commands sent with CAS commands in Auto-Precharge mode. This does not include Precharge commands sent as a result of a page close counter expiration.",
+        "UMask": "0x1",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Pre-charge for reads",
+        "EventCode": "0x2",
+        "EventName": "UNC_M_PRE_COUNT.RD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of explicit DRAM Precharge commands issued on a per channel basis due to a read, so as to close the previous DRAM page, before opening the requested page.",
+        "UMask": "0x4",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "Pre-charge for writes",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2",
         "EventName": "UNC_M_PRE_COUNT.WR",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
         "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_M_PRE_COUNT.BYP",
+        "BriefDescription": "Read CAS issued with HIGH priority",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Read CAS issued with LOW priority",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA0",
         "EventName": "UNC_M_RD_CAS_PRIO.LOW",
         "PerPkg": "1",
@@ -543,7 +517,6 @@
     },
     {
         "BriefDescription": "Read CAS issued with MEDIUM priority",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA0",
         "EventName": "UNC_M_RD_CAS_PRIO.MED",
         "PerPkg": "1",
@@ -551,26 +524,23 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read CAS issued with HIGH priority",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
         "EventCode": "0xA0",
-        "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
+        "EventName": "UNC_M_RD_CAS_PRIO.PANIC",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M_RD_CAS_PRIO.PANIC",
+        "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK0",
         "PerPkg": "1",
@@ -578,7 +548,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANK1",
         "PerPkg": "1",
@@ -586,143 +555,119 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK2",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK10",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK3",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK11",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK4",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK12",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK5",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK13",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 14",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK6",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK14",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK7",
-        "PerPkg": "1",
-        "UMask": "0x7",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 15",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK8",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK15",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK9",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK2",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK3",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK4",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK5",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK6",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK14",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK7",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.BANK15",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK8",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
         "EventCode": "0xB0",
-        "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
+        "EventName": "UNC_M_RD_CAS_RANK0.BANK9",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANKG0",
         "PerPkg": "1",
@@ -731,7 +676,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANKG1",
         "PerPkg": "1",
@@ -740,7 +684,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANKG2",
         "PerPkg": "1",
@@ -749,16 +692,22 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "UNC_M_RD_CAS_RANK0.BANKG3",
         "PerPkg": "1",
         "UMask": "0x14",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "RD_CAS Access to Rank 1; All Banks",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK0",
         "PerPkg": "1",
@@ -766,16 +715,62 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK1",
         "PerPkg": "1",
         "UMask": "0x1",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 10",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK10",
+        "PerPkg": "1",
+        "UMask": "0xa",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 11",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK11",
+        "PerPkg": "1",
+        "UMask": "0xb",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 12",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK12",
+        "PerPkg": "1",
+        "UMask": "0xc",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 13",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK13",
+        "PerPkg": "1",
+        "UMask": "0xd",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 14",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK14",
+        "PerPkg": "1",
+        "UMask": "0xe",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank 15",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANK15",
+        "PerPkg": "1",
+        "UMask": "0xf",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK2",
         "PerPkg": "1",
@@ -784,7 +779,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK3",
         "PerPkg": "1",
@@ -793,7 +787,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK4",
         "PerPkg": "1",
@@ -802,7 +795,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK5",
         "PerPkg": "1",
@@ -811,7 +803,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK6",
         "PerPkg": "1",
@@ -820,7 +811,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK7",
         "PerPkg": "1",
@@ -829,7 +819,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK8",
         "PerPkg": "1",
@@ -838,7 +827,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 1; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UNC_M_RD_CAS_RANK1.BANK9",
         "PerPkg": "1",
@@ -846,124 +834,110 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANKG0",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x11",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANKG1",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x12",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANKG2",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x13",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
         "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK1.BANKG3",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 14",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK14",
+        "BriefDescription": "RD_CAS Access to Rank 2; All Banks",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M_RD_CAS_RANK2.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank 15",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANK15",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 0",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK0",
         "PerPkg": "1",
-        "UMask": "0xF",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; All Banks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 1",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANKG0",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 10",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK10",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANKG1",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 11",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK11",
         "PerPkg": "1",
-        "UMask": "0x12",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANKG2",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 12",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK12",
         "PerPkg": "1",
-        "UMask": "0x13",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M_RD_CAS_RANK1.BANKG3",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 13",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK13",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 14",
         "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK0",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK14",
         "PerPkg": "1",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank 15",
         "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK1",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANK15",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 2; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_M_RD_CAS_RANK2.BANK2",
         "PerPkg": "1",
@@ -972,7 +946,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 2; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_M_RD_CAS_RANK2.BANK3",
         "PerPkg": "1",
@@ -981,7 +954,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 2; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_M_RD_CAS_RANK2.BANK4",
         "PerPkg": "1",
@@ -990,7 +962,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 2; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_M_RD_CAS_RANK2.BANK5",
         "PerPkg": "1",
@@ -999,7 +970,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 2; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_M_RD_CAS_RANK2.BANK6",
         "PerPkg": "1",
@@ -1008,7 +978,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 2; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_M_RD_CAS_RANK2.BANK7",
         "PerPkg": "1",
@@ -1017,7 +986,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 2; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_M_RD_CAS_RANK2.BANK8",
         "PerPkg": "1",
@@ -1026,7 +994,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 2; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "UNC_M_RD_CAS_RANK2.BANK9",
         "PerPkg": "1",
@@ -1034,124 +1001,110 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 0 (Banks 0-3)",
         "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANKG0",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x11",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 1 (Banks 4-7)",
         "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANKG1",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x12",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 2 (Banks 8-11)",
         "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANKG2",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x13",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 3 (Banks 12-15)",
         "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK2.BANKG3",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 14",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK14",
+        "BriefDescription": "RD_CAS Access to Rank 3; All Banks",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M_RD_CAS_RANK3.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank 15",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANK15",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank 0",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANK0",
         "PerPkg": "1",
-        "UMask": "0xF",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; All Banks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.ALLBANKS",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank 1",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANK1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANKG0",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank 10",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANK10",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANKG1",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank 11",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANK11",
         "PerPkg": "1",
-        "UMask": "0x12",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANKG2",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank 12",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANK12",
         "PerPkg": "1",
-        "UMask": "0x13",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M_RD_CAS_RANK2.BANKG3",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank 13",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANK13",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank 14",
         "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANK0",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANK14",
         "PerPkg": "1",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank 15",
         "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANK1",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANK15",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 3; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_M_RD_CAS_RANK3.BANK2",
         "PerPkg": "1",
@@ -1160,7 +1113,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 3; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_M_RD_CAS_RANK3.BANK3",
         "PerPkg": "1",
@@ -1169,7 +1121,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 3; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_M_RD_CAS_RANK3.BANK4",
         "PerPkg": "1",
@@ -1178,7 +1129,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 3; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_M_RD_CAS_RANK3.BANK5",
         "PerPkg": "1",
@@ -1187,7 +1137,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 3; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_M_RD_CAS_RANK3.BANK6",
         "PerPkg": "1",
@@ -1196,7 +1145,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 3; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_M_RD_CAS_RANK3.BANK7",
         "PerPkg": "1",
@@ -1205,7 +1153,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 3; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_M_RD_CAS_RANK3.BANK8",
         "PerPkg": "1",
@@ -1214,7 +1161,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 3; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB3",
         "EventName": "UNC_M_RD_CAS_RANK3.BANK9",
         "PerPkg": "1",
@@ -1222,124 +1168,110 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 0 (Banks 0-3)",
         "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANKG0",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x11",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 1 (Banks 4-7)",
         "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANKG1",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x12",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 2 (Banks 8-11)",
         "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANKG2",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x13",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 3 (Banks 12-15)",
         "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK3.BANKG3",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank 14",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANK14",
+        "BriefDescription": "RD_CAS Access to Rank 4; All Banks",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank 15",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANK15",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 0",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK0",
         "PerPkg": "1",
-        "UMask": "0xF",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; All Banks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.ALLBANKS",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 1",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANKG0",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 10",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK10",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANKG1",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 11",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK11",
         "PerPkg": "1",
-        "UMask": "0x12",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANKG2",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 12",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK12",
         "PerPkg": "1",
-        "UMask": "0x13",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M_RD_CAS_RANK3.BANKG3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 13",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK13",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 14",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK0",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK14",
         "PerPkg": "1",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank 15",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK1",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANK15",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK2",
         "PerPkg": "1",
@@ -1348,7 +1280,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK3",
         "PerPkg": "1",
@@ -1357,7 +1288,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK4",
         "PerPkg": "1",
@@ -1366,7 +1296,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK5",
         "PerPkg": "1",
@@ -1375,7 +1304,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK6",
         "PerPkg": "1",
@@ -1384,7 +1312,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK7",
         "PerPkg": "1",
@@ -1393,7 +1320,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK8",
         "PerPkg": "1",
@@ -1402,7 +1328,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 4; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "UNC_M_RD_CAS_RANK4.BANK9",
         "PerPkg": "1",
@@ -1410,124 +1335,110 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANKG0",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x11",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANKG1",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x12",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANKG2",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x13",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
         "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK4.BANKG3",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 14",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK14",
+        "BriefDescription": "RD_CAS Access to Rank 5; All Banks",
+        "EventCode": "0xB5",
+        "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank 15",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANK15",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 0",
+        "EventCode": "0xB5",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK0",
         "PerPkg": "1",
-        "UMask": "0xF",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; All Banks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 1",
+        "EventCode": "0xB5",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANKG0",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 10",
+        "EventCode": "0xB5",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK10",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANKG1",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 11",
+        "EventCode": "0xB5",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK11",
         "PerPkg": "1",
-        "UMask": "0x12",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANKG2",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 12",
+        "EventCode": "0xB5",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK12",
         "PerPkg": "1",
-        "UMask": "0x13",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M_RD_CAS_RANK4.BANKG3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 13",
+        "EventCode": "0xB5",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK13",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 14",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK0",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK14",
         "PerPkg": "1",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank 15",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK1",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANK15",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK2",
         "PerPkg": "1",
@@ -1536,7 +1447,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK3",
         "PerPkg": "1",
@@ -1545,7 +1455,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK4",
         "PerPkg": "1",
@@ -1554,7 +1463,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK5",
         "PerPkg": "1",
@@ -1563,7 +1471,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK6",
         "PerPkg": "1",
@@ -1572,7 +1479,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK7",
         "PerPkg": "1",
@@ -1581,7 +1487,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK8",
         "PerPkg": "1",
@@ -1590,7 +1495,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 5; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB5",
         "EventName": "UNC_M_RD_CAS_RANK5.BANK9",
         "PerPkg": "1",
@@ -1598,124 +1502,110 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANKG0",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x11",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANKG1",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x12",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANKG2",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x13",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
         "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK5.BANKG3",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 14",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK14",
+        "BriefDescription": "RD_CAS Access to Rank 6; All Banks",
+        "EventCode": "0xB6",
+        "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank 15",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANK15",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 0",
+        "EventCode": "0xB6",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK0",
         "PerPkg": "1",
-        "UMask": "0xF",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; All Banks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 1",
+        "EventCode": "0xB6",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANKG0",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 10",
+        "EventCode": "0xB6",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK10",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANKG1",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 11",
+        "EventCode": "0xB6",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK11",
         "PerPkg": "1",
-        "UMask": "0x12",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANKG2",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 12",
+        "EventCode": "0xB6",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK12",
         "PerPkg": "1",
-        "UMask": "0x13",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB5",
-        "EventName": "UNC_M_RD_CAS_RANK5.BANKG3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 13",
+        "EventCode": "0xB6",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK13",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 14",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK0",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK14",
         "PerPkg": "1",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank 15",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK1",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANK15",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK2",
         "PerPkg": "1",
@@ -1724,7 +1614,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK3",
         "PerPkg": "1",
@@ -1733,7 +1622,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK4",
         "PerPkg": "1",
@@ -1742,7 +1630,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK5",
         "PerPkg": "1",
@@ -1751,7 +1638,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK6",
         "PerPkg": "1",
@@ -1760,7 +1646,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK7",
         "PerPkg": "1",
@@ -1769,7 +1654,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK8",
         "PerPkg": "1",
@@ -1778,7 +1662,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 6; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB6",
         "EventName": "UNC_M_RD_CAS_RANK6.BANK9",
         "PerPkg": "1",
@@ -1786,124 +1669,110 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK10",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANKG0",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x11",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK11",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANKG1",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x12",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK12",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANKG2",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x13",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
         "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK13",
+        "EventName": "UNC_M_RD_CAS_RANK6.BANKG3",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 14",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK14",
+        "BriefDescription": "RD_CAS Access to Rank 7; All Banks",
+        "EventCode": "0xB7",
+        "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank 15",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANK15",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
+        "EventCode": "0xB7",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK0",
         "PerPkg": "1",
-        "UMask": "0xF",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; All Banks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 1",
+        "EventCode": "0xB7",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANKG0",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 10",
+        "EventCode": "0xB7",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK10",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANKG1",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
+        "EventCode": "0xB7",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK11",
         "PerPkg": "1",
-        "UMask": "0x12",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANKG2",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
+        "EventCode": "0xB7",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK12",
         "PerPkg": "1",
-        "UMask": "0x13",
+        "UMask": "0xc",
         "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB6",
-        "EventName": "UNC_M_RD_CAS_RANK6.BANKG3",
+    },
+    {
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
+        "EventCode": "0xB7",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK13",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK0",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK14",
         "PerPkg": "1",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
         "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK1",
+        "EventName": "UNC_M_RD_CAS_RANK7.BANK15",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK2",
         "PerPkg": "1",
@@ -1912,7 +1781,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK3",
         "PerPkg": "1",
@@ -1921,7 +1789,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK4",
         "PerPkg": "1",
@@ -1930,7 +1797,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK5",
         "PerPkg": "1",
@@ -1939,7 +1805,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK6",
         "PerPkg": "1",
@@ -1948,7 +1813,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK7",
         "PerPkg": "1",
@@ -1957,7 +1821,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK8",
         "PerPkg": "1",
@@ -1966,79 +1829,14 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANK9",
         "PerPkg": "1",
         "UMask": "0x9",
         "Unit": "iMC"
     },
-    {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 10",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK10",
-        "PerPkg": "1",
-        "UMask": "0xA",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK11",
-        "PerPkg": "1",
-        "UMask": "0xB",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK12",
-        "PerPkg": "1",
-        "UMask": "0xC",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK13",
-        "PerPkg": "1",
-        "UMask": "0xD",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK14",
-        "PerPkg": "1",
-        "UMask": "0xE",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.BANK15",
-        "PerPkg": "1",
-        "UMask": "0xF",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "RD_CAS Access to Rank 7; All Banks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB7",
-        "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "iMC"
-    },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANKG0",
         "PerPkg": "1",
@@ -2047,7 +1845,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANKG1",
         "PerPkg": "1",
@@ -2056,7 +1853,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANKG2",
         "PerPkg": "1",
@@ -2065,7 +1861,6 @@
     },
     {
         "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7",
         "EventName": "UNC_M_RD_CAS_RANK7.BANKG3",
         "PerPkg": "1",
@@ -2074,23 +1869,38 @@
     },
     {
         "BriefDescription": "Read Pending Queue Full Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "UNC_M_RPQ_CYCLES_FULL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the Read Pending Queue is full.  When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead.  We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM.  This event only tracks non-ISOC queue entries.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Read Pending Queue Not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0x11",
         "EventName": "UNC_M_RPQ_CYCLES_NE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Read Pending Queue is not empty.  This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Read Pending Queue Allocations",
+        "EventCode": "0x10",
+        "EventName": "UNC_M_RPQ_INSERTS",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of read requests allocated into the Read Pending Queue (RPQ).  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  The requests deallocate after the read CAS command has been issued to DRAM.  This event counts both Isochronous and non-Isochronous requests which were issued to the RPQ.",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Read Pending Queue Occupancy",
+        "EventCode": "0x80",
+        "EventName": "UNC_M_RPQ_OCCUPANCY",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries in the Read Pending Queue (RPQ) at each cycle.  This can then be used to calculate both the average occupancy of the queue (in conjunction with the number of cycles not empty) and the average latency in the queue (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate from the RPQ after the CAS command has been issued to memory.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH",
         "PerPkg": "1",
@@ -2099,7 +1909,6 @@
     },
     {
         "BriefDescription": "Transition from WMM to RMM because of low threshold",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "UNC_M_WMM_TO_RMM.STARVE",
         "PerPkg": "1",
@@ -2108,7 +1917,6 @@
     },
     {
         "BriefDescription": "Transition from WMM to RMM because of low threshold",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY",
         "PerPkg": "1",
@@ -2117,199 +1925,196 @@
     },
     {
         "BriefDescription": "Write Pending Queue Full Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x22",
         "EventName": "UNC_M_WPQ_CYCLES_FULL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC.  This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Write Pending Queue Not Empty",
-        "Counter": "0,1,2,3",
         "EventCode": "0x21",
         "EventName": "UNC_M_WPQ_CYCLES_NE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Write Pending Queue Allocations",
+        "EventCode": "0x20",
+        "EventName": "UNC_M_WPQ_INSERTS",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of writes requests allocated into the Write Pending Queue (WPQ).  The WPQ is used to schedule writes out to the memory controller and to track the requests.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (Memory Controller).  The write requests deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Write Pending Queue Occupancy",
+        "EventCode": "0x81",
+        "EventName": "UNC_M_WPQ_OCCUPANCY",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of entries in the Write Pending Queue (WPQ) at each cycle.  This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The WPQ is used to schedule writes out to the memory controller and to track the requests.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller).  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.  So, we provide filtering based on if the request has posted or not.  By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA.  The 'posted' filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory.  High average occupancies will generally coincide with high write major mode counts. Is there a filter of sorts???",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Write Pending Queue CAM Match",
-        "Counter": "0,1,2,3",
         "EventCode": "0x23",
         "EventName": "UNC_M_WPQ_READ_HIT",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Write Pending Queue CAM Match",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "UNC_M_WPQ_WRITE_HIT",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Not getting the requested Major Mode",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC1",
         "EventName": "UNC_M_WRONG_MM",
         "PerPkg": "1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; All Banks",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
         "PerPkg": "1",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK0",
         "PerPkg": "1",
-        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 1",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK2",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK1",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK3",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK10",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK4",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK11",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK5",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK12",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK6",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK13",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 14",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK7",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK14",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 15",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK8",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK15",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK9",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK2",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 3",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK3",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK4",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 5",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK5",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 6",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK6",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 7",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK14",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK7",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 8",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.BANK15",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK8",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 0; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 0; Bank 9",
         "EventCode": "0xB8",
-        "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
+        "EventName": "UNC_M_WR_CAS_RANK0.BANK9",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANKG0",
         "PerPkg": "1",
@@ -2318,7 +2123,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANKG1",
         "PerPkg": "1",
@@ -2327,7 +2131,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANKG2",
         "PerPkg": "1",
@@ -2336,7 +2139,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "UNC_M_WR_CAS_RANK0.BANKG3",
         "PerPkg": "1",
@@ -2344,160 +2146,142 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; All Banks",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS",
         "PerPkg": "1",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 0",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK0",
         "PerPkg": "1",
-        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 1",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK2",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK1",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 10",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK3",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK10",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 4",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 11",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK4",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK11",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 5",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 12",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK5",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK12",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 6",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 13",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK6",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK13",
         "PerPkg": "1",
-        "UMask": "0x6",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 7",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 14",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK7",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK14",
         "PerPkg": "1",
-        "UMask": "0x7",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 8",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 15",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK8",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK15",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 9",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 2",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK9",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK2",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 3",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK3",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x3",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 4",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK4",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 5",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK5",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x5",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 6",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK6",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x6",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 14",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 7",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK14",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK7",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x7",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; Bank 15",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 8",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.BANK15",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK8",
         "PerPkg": "1",
-        "UMask": "0xF",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 1; All Banks",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 1; Bank 9",
         "EventCode": "0xB9",
-        "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS",
+        "EventName": "UNC_M_WR_CAS_RANK1.BANK9",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x9",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANKG0",
         "PerPkg": "1",
@@ -2506,7 +2290,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANKG1",
         "PerPkg": "1",
@@ -2515,7 +2298,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANKG2",
         "PerPkg": "1",
@@ -2524,16 +2306,22 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB9",
         "EventName": "UNC_M_WR_CAS_RANK1.BANKG3",
         "PerPkg": "1",
         "UMask": "0x14",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 2; All Banks",
+        "EventCode": "0xBA",
+        "EventName": "UNC_M_WR_CAS_RANK2.ALLBANKS",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK0",
         "PerPkg": "1",
@@ -2541,16 +2329,62 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK1",
         "PerPkg": "1",
         "UMask": "0x1",
         "Unit": "iMC"
     },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 2; Bank 10",
+        "EventCode": "0xBA",
+        "EventName": "UNC_M_WR_CAS_RANK2.BANK10",
+        "PerPkg": "1",
+        "UMask": "0xa",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 2; Bank 11",
+        "EventCode": "0xBA",
+        "EventName": "UNC_M_WR_CAS_RANK2.BANK11",
+        "PerPkg": "1",
+        "UMask": "0xb",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 2; Bank 12",
+        "EventCode": "0xBA",
+        "EventName": "UNC_M_WR_CAS_RANK2.BANK12",
+        "PerPkg": "1",
+        "UMask": "0xc",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 2; Bank 13",
+        "EventCode": "0xBA",
+        "EventName": "UNC_M_WR_CAS_RANK2.BANK13",
+        "PerPkg": "1",
+        "UMask": "0xd",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 2; Bank 14",
+        "EventCode": "0xBA",
+        "EventName": "UNC_M_WR_CAS_RANK2.BANK14",
+        "PerPkg": "1",
+        "UMask": "0xe",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "WR_CAS Access to Rank 2; Bank 15",
+        "EventCode": "0xBA",
+        "EventName": "UNC_M_WR_CAS_RANK2.BANK15",
+        "PerPkg": "1",
+        "UMask": "0xf",
+        "Unit": "iMC"
+    },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK2",
         "PerPkg": "1",
@@ -2559,7 +2393,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK3",
         "PerPkg": "1",
@@ -2568,7 +2401,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK4",
         "PerPkg": "1",
@@ -2577,7 +2409,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK5",
         "PerPkg": "1",
@@ -2586,7 +2417,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK6",
         "PerPkg": "1",
@@ -2595,7 +2425,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK7",
         "PerPkg": "1",
@@ -2604,7 +2433,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK8",
         "PerPkg": "1",
@@ -2613,7 +2441,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 2; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBA",
         "EventName": "UNC_M_WR_CAS_RANK2.BANK9",
         "PerPkg": "1",
@@ -2621,124 +2448,110 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 0 (Banks 0-3)",
         "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK2.BANKG0",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x11",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 1 (Banks 4-7)",
         "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK2.BANKG1",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x12",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 2 (Banks 8-11)",
         "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK2.BANKG2",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x13",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 3 (Banks 12-15)",
         "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK2.BANKG3",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; Bank 14",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.BANK14",
+        "BriefDescription": "WR_CAS Access to Rank 3; All Banks",
+        "EventCode": "0xBB",
+        "EventName": "UNC_M_WR_CAS_RANK3.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; Bank 15",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.BANK15",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank 0",
+        "EventCode": "0xBB",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANK0",
         "PerPkg": "1",
-        "UMask": "0xF",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; All Banks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.ALLBANKS",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank 1",
+        "EventCode": "0xBB",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANK1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.BANKG0",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank 10",
+        "EventCode": "0xBB",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANK10",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.BANKG1",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank 11",
+        "EventCode": "0xBB",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANK11",
         "PerPkg": "1",
-        "UMask": "0x12",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.BANKG2",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank 12",
+        "EventCode": "0xBB",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANK12",
         "PerPkg": "1",
-        "UMask": "0x13",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBA",
-        "EventName": "UNC_M_WR_CAS_RANK2.BANKG3",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank 13",
+        "EventCode": "0xBB",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANK13",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank 14",
         "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANK14",
         "PerPkg": "1",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank 15",
         "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANK15",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK2",
         "PerPkg": "1",
@@ -2747,7 +2560,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK3",
         "PerPkg": "1",
@@ -2756,7 +2568,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK4",
         "PerPkg": "1",
@@ -2765,7 +2576,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK5",
         "PerPkg": "1",
@@ -2774,7 +2584,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK6",
         "PerPkg": "1",
@@ -2783,7 +2592,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK7",
         "PerPkg": "1",
@@ -2792,7 +2600,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK8",
         "PerPkg": "1",
@@ -2801,7 +2608,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 3; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBB",
         "EventName": "UNC_M_WR_CAS_RANK3.BANK9",
         "PerPkg": "1",
@@ -2809,124 +2615,110 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 0 (Banks 0-3)",
         "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANKG0",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x11",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 1 (Banks 4-7)",
         "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANKG1",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x12",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 2 (Banks 8-11)",
         "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANKG2",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x13",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 3 (Banks 12-15)",
         "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK3.BANKG3",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank 14",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANK14",
+        "BriefDescription": "WR_CAS Access to Rank 4; All Banks",
+        "EventCode": "0xBC",
+        "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank 15",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANK15",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 0",
+        "EventCode": "0xBC",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK0",
         "PerPkg": "1",
-        "UMask": "0xF",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; All Banks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.ALLBANKS",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 1",
+        "EventCode": "0xBC",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANKG0",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 10",
+        "EventCode": "0xBC",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK10",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANKG1",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 11",
+        "EventCode": "0xBC",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK11",
         "PerPkg": "1",
-        "UMask": "0x12",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANKG2",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 12",
+        "EventCode": "0xBC",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK12",
         "PerPkg": "1",
-        "UMask": "0x13",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBB",
-        "EventName": "UNC_M_WR_CAS_RANK3.BANKG3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 13",
+        "EventCode": "0xBC",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK13",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 14",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK14",
         "PerPkg": "1",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank 15",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANK15",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK2",
         "PerPkg": "1",
@@ -2935,7 +2727,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK3",
         "PerPkg": "1",
@@ -2944,7 +2735,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK4",
         "PerPkg": "1",
@@ -2953,7 +2743,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK5",
         "PerPkg": "1",
@@ -2962,7 +2751,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK6",
         "PerPkg": "1",
@@ -2971,7 +2759,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK7",
         "PerPkg": "1",
@@ -2980,7 +2767,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK8",
         "PerPkg": "1",
@@ -2989,7 +2775,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 4; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBC",
         "EventName": "UNC_M_WR_CAS_RANK4.BANK9",
         "PerPkg": "1",
@@ -2997,124 +2782,110 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANKG0",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x11",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANKG1",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x12",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANKG2",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x13",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
         "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK4.BANKG3",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 14",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK14",
+        "BriefDescription": "WR_CAS Access to Rank 5; All Banks",
+        "EventCode": "0xBD",
+        "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank 15",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANK15",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 0",
+        "EventCode": "0xBD",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK0",
         "PerPkg": "1",
-        "UMask": "0xF",
         "Unit": "iMC"
     },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 4; All Banks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS",
+    {
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 1",
+        "EventCode": "0xBD",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANKG0",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 10",
+        "EventCode": "0xBD",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK10",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANKG1",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 11",
+        "EventCode": "0xBD",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK11",
         "PerPkg": "1",
-        "UMask": "0x12",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANKG2",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 12",
+        "EventCode": "0xBD",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK12",
         "PerPkg": "1",
-        "UMask": "0x13",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBC",
-        "EventName": "UNC_M_WR_CAS_RANK4.BANKG3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 13",
+        "EventCode": "0xBD",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK13",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 14",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK14",
         "PerPkg": "1",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank 15",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANK15",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK2",
         "PerPkg": "1",
@@ -3123,7 +2894,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK3",
         "PerPkg": "1",
@@ -3132,7 +2902,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK4",
         "PerPkg": "1",
@@ -3141,7 +2910,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK5",
         "PerPkg": "1",
@@ -3150,7 +2918,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK6",
         "PerPkg": "1",
@@ -3159,7 +2926,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK7",
         "PerPkg": "1",
@@ -3168,7 +2934,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK8",
         "PerPkg": "1",
@@ -3177,7 +2942,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 5; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBD",
         "EventName": "UNC_M_WR_CAS_RANK5.BANK9",
         "PerPkg": "1",
@@ -3185,124 +2949,110 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANKG0",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x11",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANKG1",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x12",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANKG2",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x13",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
         "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK5.BANKG3",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 14",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK14",
+        "BriefDescription": "WR_CAS Access to Rank 6; All Banks",
+        "EventCode": "0xBE",
+        "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank 15",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANK15",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 0",
+        "EventCode": "0xBE",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK0",
         "PerPkg": "1",
-        "UMask": "0xF",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; All Banks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 1",
+        "EventCode": "0xBE",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANKG0",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 10",
+        "EventCode": "0xBE",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK10",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANKG1",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 11",
+        "EventCode": "0xBE",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK11",
         "PerPkg": "1",
-        "UMask": "0x12",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANKG2",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 12",
+        "EventCode": "0xBE",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK12",
         "PerPkg": "1",
-        "UMask": "0x13",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBD",
-        "EventName": "UNC_M_WR_CAS_RANK5.BANKG3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 13",
+        "EventCode": "0xBE",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK13",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 14",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK14",
         "PerPkg": "1",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank 15",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANK15",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK2",
         "PerPkg": "1",
@@ -3311,7 +3061,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK3",
         "PerPkg": "1",
@@ -3320,7 +3069,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK4",
         "PerPkg": "1",
@@ -3329,7 +3077,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK5",
         "PerPkg": "1",
@@ -3338,7 +3085,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK6",
         "PerPkg": "1",
@@ -3347,7 +3093,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK7",
         "PerPkg": "1",
@@ -3356,7 +3101,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK8",
         "PerPkg": "1",
@@ -3365,7 +3109,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 6; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBE",
         "EventName": "UNC_M_WR_CAS_RANK6.BANK9",
         "PerPkg": "1",
@@ -3373,124 +3116,110 @@
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 10",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK10",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANKG0",
         "PerPkg": "1",
-        "UMask": "0xA",
+        "UMask": "0x11",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 11",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK11",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANKG1",
         "PerPkg": "1",
-        "UMask": "0xB",
+        "UMask": "0x12",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 12",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK12",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANKG2",
         "PerPkg": "1",
-        "UMask": "0xC",
+        "UMask": "0x13",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 13",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
         "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK13",
+        "EventName": "UNC_M_WR_CAS_RANK6.BANKG3",
         "PerPkg": "1",
-        "UMask": "0xD",
+        "UMask": "0x14",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 14",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK14",
+        "BriefDescription": "WR_CAS Access to Rank 7; All Banks",
+        "EventCode": "0xBF",
+        "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS",
         "PerPkg": "1",
-        "UMask": "0xE",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank 15",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANK15",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
+        "EventCode": "0xBF",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK0",
         "PerPkg": "1",
-        "UMask": "0xF",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; All Banks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
+        "EventCode": "0xBF",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANKG0",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 10",
+        "EventCode": "0xBF",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK10",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0xa",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANKG1",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 11",
+        "EventCode": "0xBF",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK11",
         "PerPkg": "1",
-        "UMask": "0x12",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANKG2",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
+        "EventCode": "0xBF",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK12",
         "PerPkg": "1",
-        "UMask": "0x13",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBE",
-        "EventName": "UNC_M_WR_CAS_RANK6.BANKG3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
+        "EventCode": "0xBF",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK13",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "UMask": "0xd",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK0",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK14",
         "PerPkg": "1",
+        "UMask": "0xe",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
         "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK1",
+        "EventName": "UNC_M_WR_CAS_RANK7.BANK15",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK2",
         "PerPkg": "1",
@@ -3499,7 +3228,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 3",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK3",
         "PerPkg": "1",
@@ -3508,7 +3236,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK4",
         "PerPkg": "1",
@@ -3517,7 +3244,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK5",
         "PerPkg": "1",
@@ -3526,7 +3252,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 6",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK6",
         "PerPkg": "1",
@@ -3535,7 +3260,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK7",
         "PerPkg": "1",
@@ -3544,7 +3268,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 8",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK8",
         "PerPkg": "1",
@@ -3553,79 +3276,14 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank 9",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANK9",
         "PerPkg": "1",
         "UMask": "0x9",
         "Unit": "iMC"
     },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 10",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK10",
-        "PerPkg": "1",
-        "UMask": "0xA",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 11",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK11",
-        "PerPkg": "1",
-        "UMask": "0xB",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK12",
-        "PerPkg": "1",
-        "UMask": "0xC",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK13",
-        "PerPkg": "1",
-        "UMask": "0xD",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK14",
-        "PerPkg": "1",
-        "UMask": "0xE",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.BANK15",
-        "PerPkg": "1",
-        "UMask": "0xF",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "WR_CAS Access to Rank 7; All Banks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xBF",
-        "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "iMC"
-    },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANKG0",
         "PerPkg": "1",
@@ -3634,7 +3292,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANKG1",
         "PerPkg": "1",
@@ -3643,7 +3300,6 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANKG2",
         "PerPkg": "1",
@@ -3652,19 +3308,10 @@
     },
     {
         "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xBF",
         "EventName": "UNC_M_WR_CAS_RANK7.BANKG3",
         "PerPkg": "1",
         "UMask": "0x14",
         "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter",
-        "Counter": "FIXED",
-        "EventCode": "0xff",
-        "EventName": "UNC_M_CLOCKTICKS_F",
-        "PerPkg": "1",
-        "Unit": "iMC"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json
index 0d106fe7aae35..37003115c6c72 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json
@@ -1,8248 +1,12229 @@
 [
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CLOCKTICKS",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventName": "UNC_C_CLOCKTICKS",
-        "PerPkg": "1",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Core Cross Snoops Issued; Multiple Core Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE",
-        "PerPkg": "1",
-        "UMask": "0x42",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Core Cross Snoops Issued; Multiple Eviction",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE",
+        "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0",
+        "EventCode": "0x83",
+        "EventName": "LLC_MISSES.PCIE_READ",
+        "FCMask": "0x07",
+        "Filter": "ch_mask=0x1f",
+        "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
+        "MetricName": "LLC_MISSES.PCIE_READ",
         "PerPkg": "1",
-        "UMask": "0x82",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "ScaleUnit": "4Bytes",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x53",
-        "EventName": "UNC_CHA_DIR_LOOKUP.SNP",
+        "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0",
+        "EventCode": "0x83",
+        "EventName": "LLC_MISSES.PCIE_WRITE",
+        "FCMask": "0x07",
+        "Filter": "ch_mask=0x1f",
+        "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
+        "MetricName": "LLC_MISSES.PCIE_WRITE",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "ScaleUnit": "4Bytes",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x53",
-        "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x54",
-        "EventName": "UNC_CHA_DIR_UPDATE.HA",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x54",
-        "EventName": "UNC_CHA_DIR_UPDATE.TOR",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5F",
-        "EventName": "UNC_CHA_HITME_HIT.EX_RDS",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
-        "UMask": "0x3",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
-        "UMask": "0x9",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_C_LLC_VICTIMS.S_STATE",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_C_LLC_VICTIMS.F_STATE",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number of times that an RFO hit in S state",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_CHA_MISC.RFO_HIT_S",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "read requests from home agent",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.READS",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
-        "UMask": "0x03",
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "write requests from home agent",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.WRITES",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "UMask": "0x0C",
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "read requests from local home agent",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.READS_LOCAL",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "write requests from local home agent",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Local requests for exclusive ownership of a cache line  without receiving data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RspIFwd Snoop Responses Received",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5C",
-        "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RspSFwd Snoop Responses Received",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5C",
-        "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Rsp*Fwd*WB Snoop Responses Received",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5C",
-        "EventName": "UNC_CHA_SNOOP_RESP.RSP_FWD_WB",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPCNFLCTS",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5C",
-        "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.IRQ",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
-        "UMask": "0x31",
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA",
-        "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.IRQ",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
-        "UMask": "0x31",
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.REM_ALL",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "UMask": "0x30",
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_FAST_ASSERTED.HORZ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0xA5",
-        "EventName": "UNC_C_FAST_ASSERTED",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations; IRQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.IRQ",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Occupancy; IRQ",
-        "EventCode": "0x11",
-        "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.IRQ_HIT",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.IRQ_MISS",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_HIT",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.PRQ_HIT",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_MISS",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.PRQ_MISS",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0x24",
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_HIT",
-        "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_HIT",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_MISS",
-        "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_MISS",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; Hits from Local IO",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; Misses from Local IO",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0x24",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; All from Local iA",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "UMask": "0x31",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; Hits from Local iA",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; All from Local iA",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
-        "UMask": "0x31",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; Hits from Local iA",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; Misses from Local iA",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCS VN0 Credits",
-        "EventCode": "0x3B",
-        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCS",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "FaST wire asserted; Horizontal",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA5",
-        "EventName": "UNC_CHA_FAST_ASSERTED.HORZ",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Clockticks of the uncore caching & home agent (CHA)",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_CHA_CLOCKTICKS",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Normal priority reads issued to the memory controller from the CHA",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x59",
-        "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5B",
-        "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read requests from a remote socket",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.READS_REMOTE",
+        "BriefDescription": "CHA to iMC Bypass; Intermediate bypass Taken",
+        "EventCode": "0x57",
+        "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the intermediate bypass.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RspI Snoop Responses Received",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5C",
-        "EventName": "UNC_CHA_SNOOP_RESP.RSPI",
+        "BriefDescription": "CHA to iMC Bypass; Not Taken",
+        "EventCode": "0x57",
+        "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Rsp*WB Snoop Responses Received",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5C",
-        "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB",
+        "BriefDescription": "CHA to iMC Bypass; Taken",
+        "EventCode": "0x57",
+        "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the full bypass.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RspCnflct* Snoop Responses Received",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5C",
-        "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCTS",
+        "BriefDescription": "Clockticks of the uncore caching & home agent (CHA)",
+        "EventName": "UNC_CHA_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts clockticks of the clock controlling the uncore caching and home agent (CHA).",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop filter capacity evictions for M-state entries",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3D",
-        "EventName": "UNC_CHA_SF_EVICTION.M_STATE",
+        "BriefDescription": "CMS Clockticks",
+        "EventCode": "0xC0",
+        "EventName": "UNC_CHA_CMS_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop filter capacity evictions for E-state entries",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3D",
-        "EventName": "UNC_CHA_SF_EVICTION.E_STATE",
+        "BriefDescription": "Core PMA Events; C1  State",
+        "EventCode": "0x17",
+        "EventName": "UNC_CHA_CORE_PMA.C1_STATE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop filter capacity evictions for S-state entries",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3D",
-        "EventName": "UNC_CHA_SF_EVICTION.S_STATE",
+        "BriefDescription": "Core PMA Events; C1 Transition",
+        "EventCode": "0x17",
+        "EventName": "UNC_CHA_CORE_PMA.C1_TRANSITION",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL",
+        "BriefDescription": "Core PMA Events; C6 State",
+        "EventCode": "0x17",
+        "EventName": "UNC_CHA_CORE_PMA.C6_STATE",
         "PerPkg": "1",
-        "UMask": "0x30",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized; Lines in M state",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M",
+        "BriefDescription": "Core PMA Events; C6 Transition",
+        "EventCode": "0x17",
+        "EventName": "UNC_CHA_CORE_PMA.C6_TRANSITION",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized; Lines in E state",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E",
+        "BriefDescription": "Core PMA Events; GV",
+        "EventCode": "0x17",
+        "EventName": "UNC_CHA_CORE_PMA.GV",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized; Lines in S State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S",
+        "BriefDescription": "Core Cross Snoops Issued; Any Cycle with Multiple Snoops",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0xe2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized; Lines in F State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_F",
+        "BriefDescription": "Core Cross Snoops Issued; Any Single Snoop",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.ANY_ONE",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0xe1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD",
-        "Filter": "config1=0x40433",
+        "BriefDescription": "Core Cross Snoops Issued; Any Snoop to Remote Node",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.ANY_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0xe4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
-        "Filter": "config1=0x40233",
+        "BriefDescription": "Core Cross Snoops Issued; Multiple Core Requests",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x42",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
-        "Filter": "config1=0x40033",
+        "BriefDescription": "Core Cross Snoops Issued; Single Core Requests",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.CORE_ONE",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x41",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD",
-        "Filter": "config1=0x4b433",
+        "BriefDescription": "Core Cross Snoops Issued; Core Request to Remote Node",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.CORE_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x44",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD",
-        "Filter": "config1=0x4b233",
+        "BriefDescription": "Core Cross Snoops Issued; Multiple Eviction",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x82",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefRFO",
-        "Filter": "config1=0x4b033",
+        "BriefDescription": "Core Cross Snoops Issued; Single Eviction",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x81",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD",
-        "Filter": "config1=0x40433",
+        "BriefDescription": "Core Cross Snoops Issued; Eviction to Remote Node",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.EVICT_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x84",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
-        "Filter": "config1=0x40233",
+        "BriefDescription": "Core Cross Snoops Issued; Multiple External Snoops",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x22",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
-        "Filter": "config1=0x40033",
+        "BriefDescription": "Core Cross Snoops Issued; Single External Snoops",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.EXT_ONE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
         "UMask": "0x21",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD",
-        "Filter": "config1=0x4b433",
+        "BriefDescription": "Core Cross Snoops Issued; External Snoop to Remote Node",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.EXT_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x24",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD",
-        "Filter": "config1=0x4b233",
+        "BriefDescription": "Counter 0 Occupancy",
+        "EventCode": "0x1F",
+        "EventName": "UNC_CHA_COUNTER0_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0.   The filtering available is found in the control register - threshold, invert and edge detect.   E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefRFO",
-        "Filter": "config1=0x4b033",
+        "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed",
+        "EventCode": "0x53",
+        "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
-        "Filter": "config1=0x40433",
+        "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed",
+        "EventCode": "0x53",
+        "EventName": "UNC_CHA_DIR_LOOKUP.SNP",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts  transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
-        "Filter": "config1=0x40233",
+        "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe",
+        "EventCode": "0x54",
+        "EventName": "UNC_CHA_DIR_UPDATE.HA",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
-        "Filter": "config1=0x40033",
+        "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe",
+        "EventCode": "0x54",
+        "EventName": "UNC_CHA_DIR_UPDATE.TOR",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD",
-        "Filter": "config1=0x4b433",
+        "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
+        "EventCode": "0xAE",
+        "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD",
-        "Filter": "config1=0x4b233",
+        "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
+        "EventCode": "0xAE",
+        "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO",
-        "Filter": "config1=0x4b033",
+        "BriefDescription": "FaST wire asserted; Horizontal",
+        "EventCode": "0xA5",
+        "EventName": "UNC_CHA_FAST_ASSERTED.HORZ",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
-        "Filter": "config1=0x40433",
+        "BriefDescription": "FaST wire asserted; Vertical",
+        "EventCode": "0xA5",
+        "EventName": "UNC_CHA_FAST_ASSERTED.VERT",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
-        "Filter": "config1=0x40233",
+        "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state",
+        "EventCode": "0x5F",
+        "EventName": "UNC_CHA_HITME_HIT.EX_RDS",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state.  This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*)",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
-        "Filter": "config1=0x40033",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; Shared hit and op is RdInvOwn, RdInv, Inv*",
+        "EventCode": "0x5F",
+        "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD",
-        "Filter": "config1=0x4b433",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE",
+        "EventCode": "0x5F",
+        "EventName": "UNC_CHA_HITME_HIT.WBMTOE",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD",
-        "Filter": "config1=0x4b233",
+        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
+        "EventCode": "0x5F",
+        "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO",
-        "Filter": "config1=0x4b033",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*",
+        "EventCode": "0x5E",
+        "EventName": "UNC_CHA_HITME_LOOKUP.READ",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Clockticks of the IIO Traffic Controller",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_IIO_CLOCKTICKS",
+        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
+        "EventCode": "0x5E",
+        "EventName": "UNC_CHA_HITME_LOOKUP.WRITE",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
-        "Counter": "0,1",
-        "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0",
-        "FCMask": "0x7",
+        "BriefDescription": "Counts Number of Misses in HitMe Cache; No SF/LLC HitS/F and op is RdInvOwn",
+        "EventCode": "0x60",
+        "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x1",
-        "Unit": "IIO"
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
-        "Counter": "0,1",
-        "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1",
-        "FCMask": "0x7",
+        "BriefDescription": "Counts Number of Misses in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*",
+        "EventCode": "0x60",
+        "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x1",
-        "Unit": "IIO"
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
-        "Counter": "0,1",
-        "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2",
-        "FCMask": "0x7",
+        "BriefDescription": "Counts Number of Misses in HitMe Cache; SF/LLC HitS/F and op is RdInvOwn",
+        "EventCode": "0x60",
+        "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x1",
-        "Unit": "IIO"
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
-        "Counter": "0,1",
-        "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3",
-        "FCMask": "0x7",
+        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Deallocate HtiME$ on Reads without RspFwdI*",
+        "EventCode": "0x61",
+        "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x1",
-        "Unit": "IIO"
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
-        "Counter": "0,1",
-        "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART0",
-        "FCMask": "0x7",
+        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
+        "EventCode": "0x61",
+        "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x4",
-        "Unit": "IIO"
+        "PublicDescription": "Received RspFwdI* for a local request, but converted HitME$ to SF entry",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
-        "Counter": "0,1",
-        "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART1",
-        "FCMask": "0x7",
+        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache on RdInvOwn even if not RspFwdI*",
+        "EventCode": "0x61",
+        "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x4",
-        "Unit": "IIO"
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
-        "Counter": "0,1",
-        "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2",
-        "FCMask": "0x7",
+        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
+        "EventCode": "0x61",
+        "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x4",
-        "Unit": "IIO"
+        "PublicDescription": "Updated HitME$ on RspFwdI* or local HitM/E received for a remote request",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
-        "Counter": "0,1",
-        "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3",
-        "FCMask": "0x7",
+        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache to SHARed",
+        "EventCode": "0x61",
+        "EventName": "UNC_CHA_HITME_UPDATE.SHARED",
         "PerPkg": "1",
-        "PortMask": "0x8",
         "UMask": "0x4",
-        "Unit": "IIO"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
+        "EventCode": "0xA7",
+        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
+        "EventCode": "0xA7",
+        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
+        "EventCode": "0xA7",
+        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
+        "EventCode": "0xA7",
+        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
+        "EventCode": "0xA9",
+        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
+        "EventCode": "0xA9",
+        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
+        "EventCode": "0xA9",
+        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
+        "EventCode": "0xA9",
+        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
+        "EventCode": "0xAB",
+        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
+        "EventCode": "0xAB",
+        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part2",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
+        "EventCode": "0xAB",
+        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part3",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
+        "EventCode": "0xAB",
+        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Horizontal IV Ring in Use; Left",
+        "EventCode": "0xAD",
+        "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Horizontal IV Ring in Use; Right",
+        "EventCode": "0xAD",
+        "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Normal priority reads issued to the memory controller from the CHA",
+        "EventCode": "0x59",
+        "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "HA to iMC Reads Issued; ISOCH",
+        "EventCode": "0x59",
+        "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Count of the number of reads issued to any of the memory controller channels.  This can be filtered by the priority of the reads.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCI Express bandwidth writing at IIO, part 0",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
+        "EventCode": "0x5B",
+        "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCI Express bandwidth writing at IIO, part 1",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Writes Issued to the iMC by the HA; Full Line MIG",
+        "EventCode": "0x5B",
+        "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_MIG",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCI Express bandwidth writing at IIO, part 2",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Full Line",
+        "EventCode": "0x5B",
+        "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
+        "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
     {
-        "BriefDescription": "PCI Express bandwidth writing at IIO, part 3",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Writes Issued to the iMC by the HA; Partial Non-ISOCH",
+        "EventCode": "0x5B",
+        "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "LLC_MISSES.PCIE_WRITE",
-        "FCMask": "0x07",
-        "Filter": "ch_mask=0x1f",
-        "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
-        "MetricName": "LLC_MISSES.PCIE_WRITE",
+        "BriefDescription": "Writes Issued to the iMC by the HA; Partial MIG",
+        "EventCode": "0x5B",
+        "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "ScaleUnit": "4Bytes",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.; Filter for memory controller 5 only.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Partial",
+        "EventCode": "0x5B",
+        "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations",
+        "EventCode": "0x62",
+        "EventName": "UNC_CHA_IODC_ALLOC.INVITOM",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations dropped due to IODC Full",
+        "EventCode": "0x62",
+        "EventName": "UNC_CHA_IODC_ALLOC.IODCFULL",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IDOC allocation dropped due to OSB gate",
+        "EventCode": "0x62",
+        "EventName": "UNC_CHA_IODC_ALLOC.OSBGATED",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCI Express bandwidth reading at IIO, part 0",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to any reason",
+        "EventCode": "0x63",
+        "EventName": "UNC_CHA_IODC_DEALLOC.ALL",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCI Express bandwidth reading at IIO, part 1",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to conflicting transaction",
+        "EventCode": "0x63",
+        "EventName": "UNC_CHA_IODC_DEALLOC.SNPOUT",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCI Express bandwidth reading at IIO, part 2",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoE",
+        "EventCode": "0x63",
+        "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOE",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCI Express bandwidth reading at IIO, part 3",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoI",
+        "EventCode": "0x63",
+        "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOI",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "LLC_MISSES.PCIE_READ",
-        "FCMask": "0x07",
-        "Filter": "ch_mask=0x1f",
-        "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
-        "MetricName": "LLC_MISSES.PCIE_READ",
+        "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbPushMtoI",
+        "EventCode": "0x63",
+        "EventName": "UNC_CHA_IODC_DEALLOC.WBPUSHMTOI",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "ScaleUnit": "4Bytes",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Moved to Cbo section",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Cache and Snoop Filter Lookups; Any Request",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.ANY",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ.  This does not include lookups originating from the ISMQ.",
+        "UMask": "0x11",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Read transactions",
+        "UMask": "0x3",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Cache and Snoop Filter Lookups; Local",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.",
+        "UMask": "0x31",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Cache and Snoop Filter Lookups; Remote",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.",
+        "UMask": "0x91",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Cache and Snoop Filter Lookups; External Snoop Request",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.",
+        "UMask": "0x9",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Cache and Snoop Filter Lookups; Write Requests",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.WRITE",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC  This includes all write transactions -- both Cacheable and UC.",
+        "UMask": "0x5",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E",
+        "Deprecated": "1",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F",
+        "Deprecated": "1",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.F_STATE",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Local - All Lines",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x2f",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Local - Lines in E State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x22",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Local - Lines in F State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_F",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x28",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Local - Lines in M State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Local - Lines in S State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x24",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M",
+        "Deprecated": "1",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
+        "Deprecated": "1",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Remote - All Lines",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x8f",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Remote - Lines in E State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x82",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Remote - Lines in F State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_F",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x88",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Remote - Lines in M State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x81",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Remote - Lines in S State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x84",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S",
+        "Deprecated": "1",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Lines in E state",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Lines in F State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_F",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Lines in M state",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Lines Victimized; Lines in S State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Cbo Misc; CV0 Prefetch Miss",
+        "EventCode": "0x39",
+        "EventName": "UNC_CHA_MISC.CV0_PREF_MISS",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Miscellaneous events in the Cbo.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Cbo Misc; CV0 Prefetch Victim",
+        "EventCode": "0x39",
+        "EventName": "UNC_CHA_MISC.CV0_PREF_VIC",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Miscellaneous events in the Cbo.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Number of times that an RFO hit in S state.",
+        "EventCode": "0x39",
+        "EventName": "UNC_CHA_MISC.RFO_HIT_S",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Counts when a RFO (the Read for Ownership issued before a  write) request hit a cacheline in the S (Shared) state.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is  made by IIO Part1 to Memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
+        "EventCode": "0x39",
+        "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction.  This is useful because this information is lost in the PRE encodings.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Cbo Misc; Write Combining Aliasing",
+        "EventCode": "0x39",
+        "EventName": "UNC_CHA_MISC.WC_ALIASING",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write.  This occurs when there is WC aliasing.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "OSB Snoop Broadcast",
+        "EventCode": "0x55",
+        "EventName": "UNC_CHA_OSB",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC0_SMI2",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.EDC0_SMI2",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 2 only.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC1_SMI3",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.EDC1_SMI3",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 3 only.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x08",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x08",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
-        "FCMask": "0x4",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC2_SMI4",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.EDC2_SMI4",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 4 only.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
-        "FCMask": "0x4",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC3_SMI5",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.EDC3_SMI5",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 5 only.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
-        "FCMask": "0x4",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC0_SMI0",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC0_SMI0",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 0 only.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
-        "FCMask": "0x4",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC1_SMI1",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC1_SMI1",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 1 only.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0",
-        "Counter": "2,3",
-        "EventCode": "0xD5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
-        "FCMask": "0x04",
+        "BriefDescription": "Local requests for exclusive ownership of a cache line  without receiving data",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1",
-        "Counter": "2,3",
-        "EventCode": "0xD5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
-        "FCMask": "0x04",
+        "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2",
-        "Counter": "2,3",
-        "EventCode": "0xD5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
-        "FCMask": "0x04",
+        "BriefDescription": "Read requests",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.READS",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a  write) .",
+        "UMask": "0x3",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3",
-        "Counter": "2,3",
-        "EventCode": "0xD5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
-        "FCMask": "0x04",
+        "BriefDescription": "Read requests from a unit on this socket",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.READS_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a  write).",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",
-        "FCMask": "0x4",
+        "BriefDescription": "Read requests from a remote socket",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.READS_REMOTE",
         "PerPkg": "1",
-        "PortMask": "0x0f",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "PublicDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a  write).",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3",
-        "Counter": "2,3",
-        "EventCode": "0xD5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
-        "FCMask": "0x04",
+        "BriefDescription": "Write requests",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.WRITES",
         "PerPkg": "1",
-        "UMask": "0x0f",
-        "Unit": "IIO"
+        "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
+        "UMask": "0xc",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Total IRP occupancy of inbound read and write requests",
-        "Counter": "0,1",
-        "EventCode": "0xF",
-        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
+        "BriefDescription": "Write Requests from a unit on this socket",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL",
         "PerPkg": "1",
+        "PublicDescription": "Counts  write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
         "UMask": "0x4",
-        "Unit": "IRP"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline",
-        "Counter": "0,1",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.RFO",
+        "BriefDescription": "Read and Write Requests; Writes Remote",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
         "UMask": "0x8",
-        "Unit": "IRP"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline",
-        "Counter": "0,1",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.PCITOM",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
+        "EventCode": "0xA1",
+        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IRP"
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue",
-        "Counter": "0,1",
-        "EventCode": "0x18",
-        "EventName": "UNC_I_FAF_INSERTS",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
+        "EventCode": "0xA1",
+        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Occupancy of the IRP FAF queue",
-        "Counter": "0,1",
-        "EventCode": "0x19",
-        "EventName": "UNC_I_FAF_OCCUPANCY",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
+        "EventCode": "0xA1",
+        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Inbound write (fast path) requests received by the IRP",
-        "Counter": "0,1",
-        "EventCode": "0x11",
-        "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
+        "EventCode": "0xA1",
+        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
         "UMask": "0x8",
-        "Unit": "IRP"
-    },
-    {
-        "BriefDescription": "Clocks of the Intel Ultra Path Interconnect (UPI)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_UPI_CLOCKTICKS",
-        "PerPkg": "1",
-        "Unit": "UPI LL"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data Response packets that go direct to core",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
+        "EventCode": "0xA0",
+        "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
         "UMask": "0x1",
-        "Unit": "UPI LL"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_DIRECT_ATTEMPTS.D2U",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x12",
-        "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
+        "EventCode": "0xA0",
+        "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
         "UMask": "0x2",
-        "Unit": "UPI LL"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles Intel UPI is in L1 power mode (shutdown)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_UPI_L1_POWER_CYCLES",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
+        "EventCode": "0xA0",
+        "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles the Rx of the Intel UPI is in L0p power mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x25",
-        "EventName": "UNC_UPI_RxL0P_POWER_CYCLES",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.",
+        "EventCode": "0xA0",
+        "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x31",
-        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
+        "EventCode": "0xA3",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD",
         "PerPkg": "1",
         "UMask": "0x1",
-        "Unit": "UPI LL"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x31",
-        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
+        "EventCode": "0xA3",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK",
         "PerPkg": "1",
         "UMask": "0x2",
-        "Unit": "UPI LL"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x31",
-        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
+        "EventCode": "0xA3",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "UPI LL"
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.ALL_NULL",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.NULL",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
+        "EventCode": "0xA3",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "UPI LL"
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles in which the Tx of the Intel Ultra Path Interconnect (UPI) is in L0p power mode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x27",
-        "EventName": "UNC_UPI_TxL0P_POWER_CYCLES",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
+        "EventCode": "0xA3",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "FLITs that bypassed the TxL Buffer",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x41",
-        "EventName": "UNC_UPI_TxL_BYPASSED",
+        "BriefDescription": "Sink Starvation on Vertical Ring; AD",
+        "EventCode": "0xA2",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid Flits Sent; Data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.DATA",
+        "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
+        "EventCode": "0xA2",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "UPI LL"
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.ALL_NULL",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.NULL",
+        "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
+        "EventCode": "0xA2",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "UPI LL"
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Protocol header and credit FLITs received from any slot",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
+        "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.",
+        "EventCode": "0xA2",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x97",
-        "Unit": "UPI LL"
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Protocol header and credit FLITs transmitted across any slot",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
+        "BriefDescription": "Source Throttle",
+        "EventCode": "0xA4",
+        "EventName": "UNC_CHA_RING_SRC_THRTL",
         "PerPkg": "1",
-        "UMask": "0x97",
-        "Unit": "UPI LL"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Idle FLITs transmitted",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.IDLE",
+        "BriefDescription": "Ingress (from CMS) Allocations; IPQ",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.IPQ",
         "PerPkg": "1",
-        "UMask": "0x47",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Null FLITs transmitted from any slot",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
+        "BriefDescription": "Ingress (from CMS) Allocations; IRQ",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.IRQ",
         "PerPkg": "1",
-        "UMask": "0x27",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Null FLITs received from any slot",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
+        "BriefDescription": "Ingress (from CMS) Allocations; IRQ Rejected",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ",
         "PerPkg": "1",
-        "UMask": "0x27",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid data FLITs received from any slot",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
+        "BriefDescription": "Ingress (from CMS) Allocations; PRQ",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.PRQ",
         "PerPkg": "1",
-        "UMask": "0x0F",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Valid data FLITs transmitted via any slot",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
+        "BriefDescription": "Ingress (from CMS) Allocations; PRQ",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ",
         "PerPkg": "1",
-        "UMask": "0x0F",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UPI_DATA_BANDWIDTH_TX",
+        "BriefDescription": "Ingress (from CMS) Allocations; RRQ",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.RRQ",
         "PerPkg": "1",
-        "ScaleUnit": "7.11E-06Bytes",
-        "UMask": "0xf",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Data Response packets that go direct to Intel UPI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2U",
+        "BriefDescription": "Ingress (from CMS) Allocations; WBQ",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.WBQ",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Traffic in which the M2M to iMC Bypass was not taken",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Ingress Probe Queue Rejects; AD REQ on VN0",
         "EventCode": "0x22",
-        "EventName": "UNC_M2M_BYPASS_M2M_Egress.NOT_TAKEN",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "Ingress Probe Queue Rejects; AD RSP on VN0",
+        "EventCode": "0x22",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
         "UMask": "0x2",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x24",
-        "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
+        "BriefDescription": "Ingress Probe Queue Rejects; Non UPI AK Request",
+        "EventCode": "0x22",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages sent direct to core (bypassing the CHA)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x23",
-        "EventName": "UNC_M2M_DIRECT2CORE_TAKEN",
+        "BriefDescription": "Ingress Probe Queue Rejects; BL NCB on VN0",
+        "EventCode": "0x22",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number of reads in which direct to core transaction were overridden",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x25",
-        "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
+        "BriefDescription": "Ingress Probe Queue Rejects; BL NCS on VN0",
+        "EventCode": "0x22",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY",
+        "BriefDescription": "Ingress Probe Queue Rejects; BL RSP on VN0",
+        "EventCode": "0x22",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "M2M"
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I",
+        "BriefDescription": "Ingress Probe Queue Rejects; BL WB on VN0",
+        "EventCode": "0x22",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "M2M"
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S",
+        "BriefDescription": "Ingress Probe Queue Rejects; Non UPI IV Request",
+        "EventCode": "0x22",
+        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "M2M"
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A",
+        "BriefDescription": "Ingress Probe Queue Rejects; Allow Snoop",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "M2M"
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory update from/to Any state",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY",
+        "BriefDescription": "Ingress Probe Queue Rejects; ANY0",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0",
         "PerPkg": "1",
         "UMask": "0x1",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory update from I to S",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S",
+        "BriefDescription": "Ingress Probe Queue Rejects; HA",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA",
         "PerPkg": "1",
         "UMask": "0x2",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory update from I to A",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A",
+        "BriefDescription": "Ingress Probe Queue Rejects; Merging these two together to make room for ANY_REJECT_*0",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "M2M"
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory update from S to I",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I",
+        "BriefDescription": "Ingress Probe Queue Rejects; LLC Victim",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "M2M"
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory update from S to A",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A",
+        "BriefDescription": "Ingress Probe Queue Rejects; PhyAddr Match",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory update from A to I",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I",
+        "BriefDescription": "Ingress Probe Queue Rejects; SF Victim",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Multi-socket cacheline Directory update from A to S",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S",
+        "BriefDescription": "Ingress Probe Queue Rejects; Victim",
+        "EventCode": "0x23",
+        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Reads to iMC issued at Normal Priority (Non-Isochronous)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.NORMAL",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
         "UMask": "0x1",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Reads to iMC issued",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.ALL",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "M2M"
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Partial Non-Isochronous writes to the iMC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.PARTIAL",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "M2M"
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Writes to iMC issued",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.ALL",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.NI",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M2M"
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Prefetch requests that got turn into a demand request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x56",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_PROMOTIONS",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Inserts into the Memory Controller Prefetch Queue",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x57",
-        "EventName": "UNC_M2M_PREFCAM_INSERTS",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AD Ingress (from CMS) Queue Inserts",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1",
-        "EventName": "UNC_M2M_RxC_AD_INSERTS",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AD Ingress (from CMS) Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Ingress (from CMS) Allocations",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_M2M_RxC_BL_INSERTS",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Ingress (from CMS) Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6",
-        "EventName": "UNC_M2M_RxC_BL_OCCUPANCY",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Allocations",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9",
-        "EventName": "UNC_M2M_TxC_AD_INSERTS",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Merging these two together to make room for ANY_REJECT_*0",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA",
-        "EventName": "UNC_M2M_TxC_AD_OCCUPANCY",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Allocations; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Occupancy; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x16",
-        "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.ALL",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x28",
-        "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles when direct to Intel UPI was disabled",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x27",
-        "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
+        "BriefDescription": "ISMQ Rejects; AD REQ on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages sent direct to the Intel UPI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x26",
-        "EventName": "UNC_M2M_DIRECT2UPI_TAKEN",
+        "BriefDescription": "ISMQ Rejects; AD RSP on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x29",
-        "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE",
+        "BriefDescription": "ISMQ Rejects; Non UPI AK Request",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Prefetches generated by the flow control queue of the M3UPI unit",
-        "Counter": "0,1,2",
-        "EventCode": "0x29",
-        "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN",
+        "BriefDescription": "ISMQ Rejects; BL NCB on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
-        "Unit": "M3UPI"
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA to iMC Bypass; Taken",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x57",
-        "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN",
+        "BriefDescription": "ISMQ Rejects; BL NCS on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA to iMC Bypass; Intermediate bypass Taken",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x57",
-        "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
+        "BriefDescription": "ISMQ Rejects; BL RSP on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA to iMC Bypass; Not Taken",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x57",
-        "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
+        "BriefDescription": "ISMQ Rejects; BL WB on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued; Single External Snoops",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.EXT_ONE",
+        "BriefDescription": "ISMQ Rejects; Non UPI IV Request",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued; Single Core Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.CORE_ONE",
+        "BriefDescription": "ISMQ Retries; AD REQ on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x41",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued; Single Eviction",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE",
+        "BriefDescription": "ISMQ Retries; AD RSP on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x81",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued; Any Single Snoop",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.ANY_ONE",
+        "BriefDescription": "ISMQ Retries; Non UPI AK Request",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0xE1",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued; Multiple External Snoops",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE",
+        "BriefDescription": "ISMQ Retries; BL NCB on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
         "PerPkg": "1",
-        "UMask": "0x22",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued; Any Cycle with Multiple Snoops",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE",
+        "BriefDescription": "ISMQ Retries; BL NCS on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0xE2",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued; External Snoop to Remote Node",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.EXT_REMOTE",
+        "BriefDescription": "ISMQ Retries; BL RSP on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x24",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued; Core Request to Remote Node",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.CORE_REMOTE",
-        "PerPkg": "1",
-        "UMask": "0x44",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Core Cross Snoops Issued; Eviction to Remote Node",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.EVICT_REMOTE",
+        "BriefDescription": "ISMQ Retries; BL WB on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x84",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued; Any Snoop to Remote Node",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.ANY_REMOTE",
+        "BriefDescription": "ISMQ Retries; Non UPI IV Request",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0xE4",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counter 0 Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1F",
-        "EventName": "UNC_CHA_COUNTER0_OCCUPANCY",
+        "BriefDescription": "ISMQ Rejects; ANY0",
+        "EventCode": "0x25",
+        "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; Shared hit and op is RdInvOwn, RdInv, Inv*",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5F",
-        "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ",
+        "BriefDescription": "ISMQ Rejects; HA",
+        "EventCode": "0x25",
+        "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5F",
-        "EventName": "UNC_CHA_HITME_HIT.WBMTOE",
+        "BriefDescription": "ISMQ Retries; ANY0",
+        "EventCode": "0x2D",
+        "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5F",
-        "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S",
+        "BriefDescription": "ISMQ Retries; HA",
+        "EventCode": "0x2D",
+        "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5E",
-        "EventName": "UNC_CHA_HITME_LOOKUP.READ",
+        "BriefDescription": "Ingress (from CMS) Occupancy; IPQ",
+        "EventCode": "0x11",
+        "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5E",
-        "EventName": "UNC_CHA_HITME_LOOKUP.WRITE",
+        "BriefDescription": "Ingress (from CMS) Occupancy; IRQ",
+        "EventCode": "0x11",
+        "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of Misses in HitMe Cache; SF/LLC HitS/F and op is RdInvOwn",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x60",
-        "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN",
+        "BriefDescription": "Ingress (from CMS) Occupancy; RRQ",
+        "EventCode": "0x11",
+        "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of Misses in HitMe Cache; No SF/LLC HitS/F and op is RdInvOwn",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x60",
-        "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN",
+        "BriefDescription": "Ingress (from CMS) Occupancy; WBQ",
+        "EventCode": "0x11",
+        "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of Misses in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x60",
-        "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV",
+        "BriefDescription": "Other Retries; AD REQ on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x61",
-        "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
+        "BriefDescription": "Other Retries; AD RSP on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x61",
-        "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM",
+        "BriefDescription": "Other Retries; Non UPI AK Request",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache to SHARed",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x61",
-        "EventName": "UNC_CHA_HITME_UPDATE.SHARED",
+        "BriefDescription": "Other Retries; BL NCB on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache on RdInvOwn even if not RspFwdI*",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x61",
-        "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN",
+        "BriefDescription": "Other Retries; BL NCS on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Deallocate HtiME$ on Reads without RspFwdI*",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x61",
-        "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE",
+        "BriefDescription": "Other Retries; BL RSP on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "HA to iMC Reads Issued; ISOCH",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x59",
-        "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY",
+        "BriefDescription": "Other Retries; BL WB on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Writes Issued to the iMC by the HA; Partial Non-ISOCH",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5B",
-        "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
+        "BriefDescription": "Other Retries; Non UPI IV Request",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Full Line",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5B",
-        "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
+        "BriefDescription": "Other Retries; Allow Snoop",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Partial",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5B",
-        "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
+        "BriefDescription": "Other Retries; ANY0",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Writes Issued to the iMC by the HA; Full Line MIG",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5B",
-        "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_MIG",
+        "BriefDescription": "Other Retries; HA",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Writes Issued to the iMC by the HA; Partial MIG",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5B",
-        "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG",
+        "BriefDescription": "Other Retries; Merging these two together to make room for ANY_REJECT_*0",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
         "PerPkg": "1",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x62",
-        "EventName": "UNC_CHA_IODC_ALLOC.INVITOM",
+        "BriefDescription": "Other Retries; LLC Victim",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations dropped due to IODC Full",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x62",
-        "EventName": "UNC_CHA_IODC_ALLOC.IODCFULL",
+        "BriefDescription": "Other Retries; PhyAddr Match",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IDOC allocation dropped due to OSB gate",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x62",
-        "EventName": "UNC_CHA_IODC_ALLOC.OSBGATED",
+        "BriefDescription": "Other Retries; SF Victim",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x63",
-        "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOE",
+        "BriefDescription": "Other Retries; Victim",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x63",
-        "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOI",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbPushMtoI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x63",
-        "EventName": "UNC_CHA_IODC_DEALLOC.WBPUSHMTOI",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to conflicting transaction",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x63",
-        "EventName": "UNC_CHA_IODC_DEALLOC.SNPOUT",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to any reason",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x63",
-        "EventName": "UNC_CHA_IODC_DEALLOC.ALL",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITE",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_C_LLC_LOOKUP.WRITE",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x5",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.ANY",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_C_LLC_LOOKUP.ANY",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOCAL",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_C_LLC_LOOKUP.LOCAL",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x31",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_C_LLC_LOOKUP.REMOTE",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x91",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_C_LLC_VICTIMS.LOCAL",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x2f",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_C_LLC_VICTIMS.REMOTE",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cbo Misc; Write Combining Aliasing",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_CHA_MISC.WC_ALIASING",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC OR SF Way",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cbo Misc; CV0 Prefetch Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_CHA_MISC.CV0_PREF_VIC",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cbo Misc; CV0 Prefetch Miss",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_CHA_MISC.CV0_PREF_MISS",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "OSB Snoop Broadcast",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x55",
-        "EventName": "UNC_CHA_OSB",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC0_SMI0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC0_SMI0",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC1_SMI1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC1_SMI1",
+        "BriefDescription": "Request Queue Retries; AD REQ on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC0_SMI2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.EDC0_SMI2",
+        "BriefDescription": "Request Queue Retries; AD RSP on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC1_SMI3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.EDC1_SMI3",
+        "BriefDescription": "Request Queue Retries; Non UPI AK Request",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC2_SMI4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.EDC2_SMI4",
+        "BriefDescription": "Request Queue Retries; BL NCB on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
         "PerPkg": "1",
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC3_SMI5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.EDC3_SMI5",
+        "BriefDescription": "Request Queue Retries; BL NCS on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
         "PerPkg": "1",
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "write requests from remote home agent",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE",
+        "BriefDescription": "Request Queue Retries; BL RSP on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.ALL",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x51",
-        "EventName": "UNC_H_SNOOPS_SENT.",
+        "BriefDescription": "Request Queue Retries; BL WB on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Local Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x51",
-        "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL",
+        "BriefDescription": "Request Queue Retries; Non UPI IV Request",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Remote Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x51",
-        "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE",
+        "BriefDescription": "Request Queue Retries; Allow Snoop",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x51",
-        "EventName": "UNC_H_SNOOPS_SENT.BCST_LOC",
+        "BriefDescription": "Request Queue Retries; ANY0",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_REMOTE",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x51",
-        "EventName": "UNC_H_SNOOPS_SENT.BCST_REM",
+        "BriefDescription": "Request Queue Retries; HA",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA",
+        "PerPkg": "1",
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "Request Queue Retries; Merging these two together to make room for ANY_REJECT_*0",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
         "PerPkg": "1",
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x51",
-        "EventName": "UNC_H_SNOOPS_SENT.DIRECT_LOC",
+        "BriefDescription": "Request Queue Retries; LLC Victim",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x51",
-        "EventName": "UNC_H_SNOOPS_SENT.DIRECT_REM",
+        "BriefDescription": "Request Queue Retries; PhyAddr Match",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
         "PerPkg": "1",
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
         "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received : RspS",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5C",
-        "EventName": "UNC_CHA_SNOOP_RESP.RSPS",
+        "BriefDescription": "Request Queue Retries; SF Victim",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_WBWB",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5C",
-        "EventName": "UNC_H_SNOOP_RESP.RSP_WB",
+        "BriefDescription": "Request Queue Retries; Victim",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
         "PerPkg": "1",
+        "PublicDescription": "REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received; RspFwd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5C",
-        "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD",
+        "BriefDescription": "RRQ Rejects; AD REQ on VN0",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5D",
-        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPI",
+        "BriefDescription": "RRQ Rejects; AD RSP on VN0",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5D",
-        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPS",
+        "BriefDescription": "RRQ Rejects; Non UPI AK Request",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5D",
-        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPIFWD",
+        "BriefDescription": "RRQ Rejects; BL NCB on VN0",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5D",
-        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPSFWD",
+        "BriefDescription": "RRQ Rejects; BL NCS on VN0",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5D",
-        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_WB",
+        "BriefDescription": "RRQ Rejects; BL RSP on VN0",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5D",
-        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_FWD_WB",
+        "BriefDescription": "RRQ Rejects; BL WB on VN0",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5D",
-        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPCNFLCT",
+        "BriefDescription": "RRQ Rejects; Non UPI IV Request",
+        "EventCode": "0x26",
+        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5D",
-        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPFWD",
+        "BriefDescription": "RRQ Rejects; Allow Snoop",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.EVICT",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.EVICT",
+        "BriefDescription": "RRQ Rejects; ANY0",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.PRQ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.PRQ",
+        "BriefDescription": "RRQ Rejects; HA",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IPQ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.IPQ",
+        "BriefDescription": "RRQ Rejects; Merging these two together to make room for ANY_REJECT_*0",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.HIT",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.HIT",
+        "BriefDescription": "RRQ Rejects; LLC Victim",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.MISS",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.MISS",
+        "BriefDescription": "RRQ Rejects; PhyAddr Match",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.EVICT",
-        "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.EVICT",
+        "BriefDescription": "RRQ Rejects; SF Victim",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.PRQ",
-        "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.PRQ",
+        "BriefDescription": "RRQ Rejects; Victim",
+        "EventCode": "0x27",
+        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IPQ",
-        "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.IPQ",
+        "BriefDescription": "WBQ Rejects; AD REQ on VN0",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.HIT",
-        "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.HIT",
+        "BriefDescription": "WBQ Rejects; AD RSP on VN0",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.MISS",
-        "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.MISS",
+        "BriefDescription": "WBQ Rejects; Non UPI AK Request",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WbPushMtoI; Pushed to LLC",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x56",
-        "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC",
+        "BriefDescription": "WBQ Rejects; BL NCB on VN0",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WbPushMtoI; Pushed to Memory",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x56",
-        "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM",
+        "BriefDescription": "WBQ Rejects; BL NCS on VN0",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC0_SMI0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0",
+        "BriefDescription": "WBQ Rejects; BL RSP on VN0",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC1_SMI1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1",
+        "BriefDescription": "WBQ Rejects; BL WB on VN0",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC0_SMI2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2",
+        "BriefDescription": "WBQ Rejects; Non UPI IV Request",
+        "EventCode": "0x28",
+        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC1_SMI3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3",
+        "BriefDescription": "WBQ Rejects; Allow Snoop",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC2_SMI4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4",
+        "BriefDescription": "WBQ Rejects; ANY0",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC3_SMI5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5",
+        "BriefDescription": "WBQ Rejects; HA",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.LOC_IO",
+        "BriefDescription": "WBQ Rejects; Merging these two together to make room for ANY_REJECT_*0",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMask": "0x34",
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.LOC_IA",
+        "BriefDescription": "WBQ Rejects; LLC Victim",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x31",
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.LOC_ALL",
+        "BriefDescription": "WBQ Rejects; PhyAddr Match",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x37",
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO",
-        "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IO",
+        "BriefDescription": "WBQ Rejects; SF Victim",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x34",
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA",
-        "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IA",
+        "BriefDescription": "WBQ Rejects; Victim",
+        "EventCode": "0x29",
+        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x31",
+        "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.LOC_ALL",
+        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+        "EventCode": "0xB4",
+        "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x37",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core PMA Events; C1  State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x17",
-        "EventName": "UNC_CHA_CORE_PMA.C1_STATE",
+        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+        "EventCode": "0xB4",
+        "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core PMA Events; C1 Transition",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x17",
-        "EventName": "UNC_CHA_CORE_PMA.C1_TRANSITION",
+        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+        "EventCode": "0xB4",
+        "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core PMA Events; C6 State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x17",
-        "EventName": "UNC_CHA_CORE_PMA.C6_STATE",
+        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+        "EventCode": "0xB4",
+        "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core PMA Events; C6 Transition",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x17",
-        "EventName": "UNC_CHA_CORE_PMA.C6_TRANSITION",
+        "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_CHA_RxR_BYPASS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core PMA Events; GV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x17",
-        "EventName": "UNC_CHA_CORE_PMA.GV",
+        "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
+        "EventCode": "0xB2",
+        "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0",
+        "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_CHA_RxR_BYPASS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1",
+        "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_CHA_RxR_BYPASS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2",
+        "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
+        "EventCode": "0xB2",
+        "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3",
+        "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_CHA_RxR_BYPASS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5",
+        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0",
+        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+        "EventCode": "0xB3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+        "EventCode": "0xB3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
+        "EventCode": "0xB3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5",
+        "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0",
+        "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_CHA_RxR_INSERTS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1",
+        "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
+        "EventCode": "0xB1",
+        "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2",
+        "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_CHA_RxR_INSERTS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3",
+        "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_CHA_RxR_INSERTS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4",
+        "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
+        "EventCode": "0xB1",
+        "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5",
+        "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_CHA_RxR_INSERTS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0",
+        "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
+        "EventCode": "0xB0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
+        "EventCode": "0xB0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5",
+        "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0",
+        "BriefDescription": "Snoop filter capacity evictions for E-state entries.",
+        "EventCode": "0x3D",
+        "EventName": "UNC_CHA_SF_EVICTION.E_STATE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1",
+        "BriefDescription": "Snoop filter capacity evictions for M-state entries.",
+        "EventCode": "0x3D",
+        "EventName": "UNC_CHA_SF_EVICTION.M_STATE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2",
+        "BriefDescription": "Snoop filter capacity evictions for S-state entries.",
+        "EventCode": "0x3D",
+        "EventName": "UNC_CHA_SF_EVICTION.S_STATE",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts snoop filter capacity evictions for entries tracking shared lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3",
+        "BriefDescription": "Snoops Sent; All",
+        "EventCode": "0x51",
+        "EventName": "UNC_CHA_SNOOPS_SENT.ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of snoops issued by the HA.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4",
+        "BriefDescription": "Snoops Sent; Broadcast snoop for Local Requests",
+        "EventCode": "0x51",
+        "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast snoops issued by the HA. This filter includes only requests coming from local sockets.",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5",
+        "BriefDescription": "Snoops Sent; Broadcast snoops for Remote Requests",
+        "EventCode": "0x51",
+        "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast snoops issued by the HA.This filter includes only requests coming from remote sockets.",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0",
+        "BriefDescription": "Snoops Sent; Directed snoops for Local Requests",
+        "EventCode": "0x51",
+        "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of directed snoops issued by the HA. This filter includes only requests coming from local sockets.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "Snoops Sent; Directed snoops for Remote Requests",
+        "EventCode": "0x51",
+        "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of directed snoops issued by the HA. This filter includes only requests coming from remote sockets.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Local Requests",
+        "EventCode": "0x51",
+        "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the local socket.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Remote Requests",
+        "EventCode": "0x51",
+        "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the remote socket.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "RspCnflct* Snoop Responses Received",
+        "EventCode": "0x5C",
+        "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCTS",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts when a a transaction with the opcode type RspCnflct* Snoop Response was received. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent. This triggers conflict resolution hardware. This covers both the opcode RspCnflct and RspCnflctWbI.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5",
+        "BriefDescription": "Snoop Responses Received; RspFwd",
+        "EventCode": "0x5C",
+        "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspFwd to a CA request.  This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0",
+        "BriefDescription": "RspI Snoop Responses Received",
+        "EventCode": "0x5C",
+        "EventName": "UNC_CHA_SNOOP_RESP.RSPI",
         "PerPkg": "1",
+        "PublicDescription": "Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data).",
         "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "RspIFwd Snoop Responses Received",
+        "EventCode": "0x5C",
+        "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states.  This is commonly returned with RFO (the Read for Ownership issued before a write) transactions.  The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward)  states.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "Snoop Responses Received : RspS",
+        "EventCode": "0x5C",
+        "EventName": "UNC_CHA_SNOOP_RESP.RSPS",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Snoop Responses Received : RspS : Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for snoop responses of RspS.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "RspSFwd Snoop Responses Received",
+        "EventCode": "0x5C",
+        "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD",
         "PerPkg": "1",
+        "PublicDescription": "Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy.  This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.",
         "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "Rsp*Fwd*WB Snoop Responses Received",
+        "EventCode": "0x5C",
+        "EventName": "UNC_CHA_SNOOP_RESP.RSP_FWD_WB",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to its home socket, and the cacheline was forwarded to the requestor socket.  This snoop response is only used in &gt;= 4 socket systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to its home socket to be written back to memory.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5",
+        "BriefDescription": "Rsp*WB Snoop Responses Received",
+        "EventCode": "0x5C",
+        "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to its home.  This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured.  This response will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0",
+        "BriefDescription": "Snoop Responses Received Local; RspCnflct",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoops responses of RspConflict to local CA requests.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1",
+        "BriefDescription": "Snoop Responses Received Local; RspFwd",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of RspFwd to local CA requests.  This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2",
+        "BriefDescription": "Snoop Responses Received Local; RspI",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoops responses of RspI to local CA requests.  RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3",
+        "BriefDescription": "Snoop Responses Received Local; RspIFwd",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoop responses of RspIFwd to local CA requests.  This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states.  This is commonly returned with RFO transactions.  It can be either a HitM or a HitFE.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4",
+        "BriefDescription": "Snoop Responses Received Local; RspS",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for snoop responses of RspS to local CA requests.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5",
+        "BriefDescription": "Snoop Responses Received Local; RspSFwd",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of RspSFwd to local CA requests.  This is returned when a remote caching agent forwards data but holds on to its current copy.  This is common for data and code reads that hit in a remote socket in E or F state.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CMS_CLOCKTICKS",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_H_CLOCK",
+        "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB",
         "PerPkg": "1",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of Rsp*Fwd*WB to local CA requests.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAE",
-        "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
+        "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of snoop responses received for a Local  request; Filters for a snoop response of RspIWB or RspSWB to local CA requests.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAE",
-        "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA7",
-        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA7",
-        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA7",
-        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA7",
-        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA9",
-        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA9",
-        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA9",
-        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA9",
-        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAB",
-        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAB",
-        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAB",
-        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAB",
-        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use; Left",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAD",
-        "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use; Right",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAD",
-        "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA1",
-        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA1",
-        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA1",
-        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA1",
-        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA0",
-        "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA0",
-        "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA0",
-        "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA0",
-        "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA3",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA3",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK",
+        "BriefDescription": "TOR Inserts; Hits from Local",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.ALL_HIT",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0x15",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA3",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL",
+        "BriefDescription": "TOR Inserts; All from Local iA and IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.ALL_IO_IA",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests",
+        "UMask": "0x35",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA3",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV",
+        "BriefDescription": "TOR Inserts; Misses from Local",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.ALL_MISS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0x25",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA3",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1",
+        "BriefDescription": "TOR Inserts; SF/LLC Evictions",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.EVICT",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; AD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA2",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD",
+        "BriefDescription": "TOR Inserts; Hit (Not a Miss)",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.HIT",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; HITs (hit is defined to be not a miss [see below], as a result for any request allocated into the TOR, one of either HIT or MISS must be true)",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA2",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK",
+        "BriefDescription": "TOR Inserts; All from Local iA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests from iA Cores",
+        "UMask": "0x31",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA2",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL",
+        "BriefDescription": "TOR Inserts; Hits from Local iA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA2",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV",
+        "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
+        "Filter": "config1=0x40233",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SRC_THRTL",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0xA4",
-        "EventName": "UNC_C_RING_SRC_THRTL",
+        "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD",
+        "Filter": "config1=0x40433",
         "PerPkg": "1",
+        "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations; IRQ Rejected",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ",
+        "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD",
+        "Filter": "config1=0x4b233",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations; IPQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.IPQ",
+        "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD",
+        "Filter": "config1=0x4b433",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations; PRQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.PRQ",
+        "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefRFO",
+        "Filter": "config1=0x4b033",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations; PRQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ",
+        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
+        "Filter": "config1=0x40033",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations; RRQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.RRQ",
+        "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x21",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations; WBQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.WBQ",
+        "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
+        "Filter": "config1=0x40233",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x21",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0",
+        "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD",
+        "Filter": "config1=0x40433",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x21",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0",
+        "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD",
+        "Filter": "config1=0x4b233",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x21",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0",
+        "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD",
+        "Filter": "config1=0x4b433",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x21",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0",
+        "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefRFO",
+        "Filter": "config1=0x4b033",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x21",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0",
+        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
+        "Filter": "config1=0x40033",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x21",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0",
+        "BriefDescription": "TOR Inserts; All from Local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally generated IO traffic",
+        "UMask": "0x34",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ANY0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x23",
-        "EventName": "UNC_H_RxC_IPQ1_REJECT.ANY_IPQ0",
+        "BriefDescription": "TOR Inserts; Hits from Local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0x14",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; HA",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA",
+        "BriefDescription": "TOR Inserts; Misses from Local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0x24",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; LLC Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM",
+        "BriefDescription": "TOR Inserts; ItoM misses from Local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
+        "Filter": "config1=0x49033",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO ItoM requests that miss the LLC. An ItoM request is used by IIO to request a data write without first reading the data for ownership.",
+        "UMask": "0x24",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; SF Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM",
+        "BriefDescription": "TOR Inserts; RdCur misses from Local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RDCUR",
+        "Filter": "config1=0x43C33",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO RdCur requests and miss the LLC. A RdCur request is used by IIO to read data without changing state.",
+        "UMask": "0x24",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM",
+        "BriefDescription": "TOR Inserts; RFO misses from Local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
+        "Filter": "config1=0x40033",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO RFO requests that miss the LLC. A read for ownership (RFO) requests a cache line to be cached in E state with the intent to modify.",
+        "UMask": "0x24",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; Merging these two together to make room for ANY_REJECT_*0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
+        "BriefDescription": "TOR Inserts; IPQ",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IPQ",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; Allow Snoop",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IPQ_HIT",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x18",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; PhyAddr Match",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IPQ_MISS",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x28",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
+        "BriefDescription": "TOR Inserts; IRQ",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IRQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x37",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
+        "BriefDescription": "TOR Inserts; Miss",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.MISS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; Misses.  (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to a local memory controller, in the event that the CHA is the home node)).  Basically, if the LLC/SF/MLC complex were not able to service the request without involving another agent...it is a miss.  If only IDI snoops were required, it is not a miss (that means the SF/MLC com",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
+        "BriefDescription": "TOR Inserts; PRQ",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.PRQ",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x30",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ANY0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0x19",
-        "EventName": "UNC_H_RxC_IRQ1_REJECT.ANY_REJECT_IRQ0",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.RRQ_HIT",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x50",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x60",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.WBQ_HIT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x90",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.WBQ_MISS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0xa0",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
+        "BriefDescription": "TOR Occupancy; All from Local",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   There are a number of subevent 'filters' but only a subset of the subevent combinations are valid.  Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set.  If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All remotely generated requests",
+        "UMask": "0x37",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Merging these two together to make room for ANY_REJECT_*0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
+        "BriefDescription": "TOR Occupancy; Hits from Local",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_HIT",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0x17",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
+        "BriefDescription": "TOR Occupancy; Misses from Local",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_MISS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0x27",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects; AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
+        "BriefDescription": "TOR Occupancy; SF/LLC Evictions",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T; TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects; AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
+        "BriefDescription": "TOR Occupancy; Hit (Not a Miss)",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T; HITs (hit is defined to be not a miss [see below], as a result for any request allocated into the TOR, one of either HIT or MISS must be true)",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects; BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
+        "BriefDescription": "TOR Occupancy; All from Local iA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T; All locally initiated requests from iA Cores",
+        "UMask": "0x31",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects; BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
+        "BriefDescription": "TOR Occupancy; Hits from Local iA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects; BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
+        "Filter": "config1=0x40233",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects; BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
+        "Filter": "config1=0x40433",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries; AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD",
+        "Filter": "config1=0x4b233",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries; AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD",
+        "Filter": "config1=0x4b433",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries; BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO",
+        "Filter": "config1=0x4b033",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries; BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
+        "Filter": "config1=0x40033",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries; BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
+        "BriefDescription": "TOR Occupancy; Misses from Local iA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0x21",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries; BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
+        "Filter": "config1=0x40233",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x21",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x25",
-        "EventName": "UNC_H_RxC_ISMQ1_REJECT.ANY_ISMQ0",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
+        "Filter": "config1=0x40433",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x21",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects; HA",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x25",
-        "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD",
+        "Filter": "config1=0x4b233",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x21",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x2D",
-        "EventName": "UNC_H_RxC_ISMQ1_RETRY.ANY",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD",
+        "Filter": "config1=0x4b433",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x21",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries; HA",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2D",
-        "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO",
+        "Filter": "config1=0x4b033",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x21",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Occupancy; IPQ",
-        "EventCode": "0x11",
-        "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ",
+        "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
+        "Filter": "config1=0x40033",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x21",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Occupancy; RRQ",
-        "EventCode": "0x11",
-        "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ",
+        "BriefDescription": "TOR Occupancy; All from Local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T; All locally generated IO traffic",
+        "UMask": "0x34",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Occupancy; WBQ",
-        "EventCode": "0x11",
-        "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ",
+        "BriefDescription": "TOR Occupancy; Hits from Local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0x14",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
+        "BriefDescription": "TOR Occupancy; Misses from Local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0x24",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
+        "BriefDescription": "TOR Occupancy;  ITOM Misses from Local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
+        "Filter": "config1=0x49033",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO ItoM requests that miss the LLC. An ItoM is used by IIO to request a data write without first reading the data for ownership.",
+        "UMask": "0x24",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
+        "BriefDescription": "TOR Occupancy;  RDCUR misses from Local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RDCUR",
+        "Filter": "config1=0x43C33",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RdCur requests that miss the LLC. A RdCur request is used by IIO to read data without changing state.",
+        "UMask": "0x24",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
+        "BriefDescription": "TOR Occupancy;  RFO misses from Local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
+        "Filter": "config1=0x40033",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RFO requests that miss the LLC. A read for ownership (RFO) requests data to be cached in E state with the intent to modify.",
+        "UMask": "0x24",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
+        "BriefDescription": "TOR Occupancy; IPQ",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_HIT",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x18",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ANY0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0x2F",
-        "EventName": "UNC_H_RxC_OTHER1_RETRY.ANY",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_MISS",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x28",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; HA",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA",
+        "BriefDescription": "TOR Occupancy; IRQ",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; LLC Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x37",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; SF Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
+        "BriefDescription": "TOR Occupancy; Miss",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T; Misses.  (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to a local memory controller, in the event that the CHA is the home node)).  Basically, if the LLC/SF/MLC complex were not able to service the request without involving another agent...it is a miss.  If only IDI snoops were required, it is not a miss (that means the SF/MLC com",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
+        "BriefDescription": "TOR Occupancy; PRQ",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; Merging these two together to make room for ANY_REJECT_*0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
+        "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
+        "EventCode": "0x9D",
+        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; Allow Snoop",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
+        "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
+        "EventCode": "0x9D",
+        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; PhyAddr Match",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
+        "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
+        "EventCode": "0x9D",
+        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
+        "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
+        "EventCode": "0x9D",
+        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
+        "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
+        "EventCode": "0x9D",
+        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
+        "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
+        "EventCode": "0x9F",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
+        "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
+        "EventCode": "0x9F",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
+        "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
+        "EventCode": "0x9F",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
+        "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce",
+        "EventCode": "0x9F",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ANY0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x21",
-        "EventName": "UNC_H_RxC_PRQ1_REJECT.ANY_PRQ0",
+        "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit",
+        "EventCode": "0x9F",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA",
+        "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce",
+        "EventCode": "0x9F",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce",
+        "EventCode": "0x96",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit",
+        "EventCode": "0x96",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce",
+        "EventCode": "0x96",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC OR SF Way",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce",
+        "EventCode": "0x96",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit",
+        "EventCode": "0x96",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce",
+        "EventCode": "0x96",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce",
+        "EventCode": "0x97",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit",
+        "EventCode": "0x97",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce",
+        "EventCode": "0x97",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce",
+        "EventCode": "0x97",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit",
+        "EventCode": "0x97",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce",
+        "EventCode": "0x97",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x2B",
-        "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ANY",
+        "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce",
+        "EventCode": "0x95",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; HA",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA",
+        "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit",
+        "EventCode": "0x95",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; LLC Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
+        "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce",
+        "EventCode": "0x95",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; SF Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
+        "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce",
+        "EventCode": "0x95",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
+        "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit",
+        "EventCode": "0x95",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; Merging these two together to make room for ANY_REJECT_*0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
+        "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce",
+        "EventCode": "0x95",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; Allow Snoop",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
+        "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce",
+        "EventCode": "0x99",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; PhyAddr Match",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
+        "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit",
+        "EventCode": "0x99",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0",
+        "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce",
+        "EventCode": "0x99",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0",
+        "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce",
+        "EventCode": "0x99",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0",
+        "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit",
+        "EventCode": "0x99",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0",
+        "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce",
+        "EventCode": "0x99",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce",
+        "EventCode": "0x94",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit",
+        "EventCode": "0x94",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ANY0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x27",
-        "EventName": "UNC_H_RxC_RRQ1_REJECT.ANY_RRQ0",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce",
+        "EventCode": "0x94",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; HA",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce",
+        "EventCode": "0x94",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; LLC Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit",
+        "EventCode": "0x94",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; SF Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce",
+        "EventCode": "0x94",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce",
+        "EventCode": "0x9B",
+        "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; Merging these two together to make room for ANY_REJECT_*0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce",
+        "EventCode": "0x9B",
+        "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; Allow Snoop",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce",
+        "EventCode": "0x9B",
+        "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; PhyAddr Match",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce",
+        "EventCode": "0x9B",
+        "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0",
+        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
+        "EventCode": "0x9C",
+        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0",
+        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0",
+        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
+        "EventCode": "0x9C",
+        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0",
+        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0",
+        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
+        "EventCode": "0x9C",
+        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0",
+        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ANY0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x29",
-        "EventName": "UNC_H_RxC_WBQ1_REJECT.ANY_WBQ0",
+        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
+        "EventCode": "0x9E",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
         "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; HA",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA",
+        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; LLC Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM",
+        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
+        "EventCode": "0x9E",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; SF Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM",
+        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; Victim",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM",
+        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
+        "EventCode": "0x9E",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; Merging these two together to make room for ANY_REJECT_*0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
+        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; Allow Snoop",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP",
+        "BriefDescription": "CMS Vertical ADS Used; IV",
+        "EventCode": "0x9E",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; PhyAddr Match",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB4",
-        "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_BNC",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB4",
-        "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_BNC",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB4",
-        "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB4",
-        "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_CHA_RxR_BYPASS.AD_BNC",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_CHA_RxR_BYPASS.AK_BNC",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV",
+        "EventCode": "0x92",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.IV",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_CHA_RxR_BYPASS.BL_BNC",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0",
+        "EventCode": "0x93",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_CHA_RxR_BYPASS.IV_BNC",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1",
+        "EventCode": "0x93",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0",
+        "EventCode": "0x93",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1",
+        "EventCode": "0x93",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_BNC",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0",
+        "EventCode": "0x93",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.AK_BNC",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1",
+        "EventCode": "0x93",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_BNC",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV",
+        "EventCode": "0x93",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.IV",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.IV_BNC",
+        "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0",
+        "EventCode": "0x91",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD",
+        "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1",
+        "EventCode": "0x91",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD",
+        "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0",
+        "EventCode": "0x91",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV",
+        "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1",
+        "EventCode": "0x91",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_CHA_RxR_INSERTS.AD_BNC",
+        "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0",
+        "EventCode": "0x91",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_CHA_RxR_INSERTS.AK_BNC",
+        "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1",
+        "EventCode": "0x91",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_CHA_RxR_INSERTS.BL_BNC",
+        "BriefDescription": "CMS Vert Egress Allocations; IV",
+        "EventCode": "0x91",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS.IV",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_CHA_RxR_INSERTS.IV_BNC",
+        "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD",
+        "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD",
+        "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_BNC",
+        "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.AK_BNC",
+        "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_BNC",
+        "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.IV_BNC",
+        "BriefDescription": "CMS Vertical Egress NACKs; IV",
+        "EventCode": "0x98",
+        "EventName": "UNC_CHA_TxR_VERT_NACK.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD",
+        "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD",
+        "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+        "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+        "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+        "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+        "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+        "BriefDescription": "CMS Vert Egress Occupancy; IV",
+        "EventCode": "0x90",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.IV",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
+        "EventCode": "0x9A",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED.IV",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+        "BriefDescription": "UPI Ingress Credit Allocations; AD REQ Credits",
+        "EventCode": "0x38",
+        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+        "BriefDescription": "UPI Ingress Credit Allocations; AD RSP VN0 Credits",
+        "EventCode": "0x38",
+        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+        "BriefDescription": "UPI Ingress Credit Allocations; BL NCB Credits",
+        "EventCode": "0x38",
+        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+        "BriefDescription": "UPI Ingress Credit Allocations; BL NCS Credits",
+        "EventCode": "0x38",
+        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+        "BriefDescription": "UPI Ingress Credit Allocations; BL RSP Credits",
+        "EventCode": "0x38",
+        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_RSP",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+        "BriefDescription": "UPI Ingress Credit Allocations; BL DRS Credits",
+        "EventCode": "0x38",
+        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_WB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+        "BriefDescription": "UPI Ingress Credit Allocations; VN0 Credits",
+        "EventCode": "0x38",
+        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+        "BriefDescription": "UPI Ingress Credit Allocations; VNA Credits",
+        "EventCode": "0x38",
+        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VNA",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This can be used with the Credit Occupancy event in order to calculate average credit lifetime.  This event supports filtering to cover the VNA/VN0 credits and the different message classes.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+        "BriefDescription": "UPI Ingress Credits In Use Cycles; AD REQ VN0 Credits",
+        "EventCode": "0x3B",
+        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+        "BriefDescription": "UPI Ingress Credits In Use Cycles; AD RSP VN0 Credits",
+        "EventCode": "0x3B",
+        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+        "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCB VN0 Credits",
+        "EventCode": "0x3B",
+        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+        "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCS VN0 Credits",
+        "EventCode": "0x3B",
+        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9D",
-        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC",
+        "BriefDescription": "UPI Ingress Credits In Use Cycles; BL RSP VN0 Credits",
+        "EventCode": "0x3B",
+        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9D",
-        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC",
+        "BriefDescription": "UPI Ingress Credits In Use Cycles; BL DRS VN0 Credits",
+        "EventCode": "0x3B",
+        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_WB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9D",
-        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC",
+        "BriefDescription": "UPI Ingress Credits In Use Cycles; AD VNA Credits",
+        "EventCode": "0x3B",
+        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_AD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9D",
-        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD",
+        "BriefDescription": "UPI Ingress Credits In Use Cycles; BL VNA Credits",
+        "EventCode": "0x3B",
+        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_BL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring.  In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer.  This stat increments by the number of credits that are available each cycle.  This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime.  This event supports filtering for the different types of credits that are available.  Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9D",
-        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD",
+        "BriefDescription": "Vertical AD Ring In Use; Down and Even",
+        "EventCode": "0xA6",
+        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9F",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_BNC",
+        "BriefDescription": "Vertical AD Ring In Use; Down and Odd",
+        "EventCode": "0xA6",
+        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9F",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK_BNC",
+        "BriefDescription": "Vertical AD Ring In Use; Up and Even",
+        "EventCode": "0xA6",
+        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9F",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_BNC",
+        "BriefDescription": "Vertical AD Ring In Use; Up and Odd",
+        "EventCode": "0xA6",
+        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9F",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV_BNC",
+        "BriefDescription": "Vertical AK Ring In Use; Down and Even",
+        "EventCode": "0xA8",
+        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9F",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD",
+        "BriefDescription": "Vertical AK Ring In Use; Down and Odd",
+        "EventCode": "0xA8",
+        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9F",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD",
+        "BriefDescription": "Vertical AK Ring In Use; Up and Even",
+        "EventCode": "0xA8",
+        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC",
+        "BriefDescription": "Vertical AK Ring In Use; Up and Odd",
+        "EventCode": "0xA8",
+        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC",
+        "BriefDescription": "Vertical BL Ring in Use; Down and Even",
+        "EventCode": "0xAA",
+        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC",
+        "BriefDescription": "Vertical BL Ring in Use; Down and Odd",
+        "EventCode": "0xAA",
+        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC",
+        "BriefDescription": "Vertical BL Ring in Use; Up and Even",
+        "EventCode": "0xAA",
+        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD",
+        "BriefDescription": "Vertical BL Ring in Use; Up and Odd",
+        "EventCode": "0xAA",
+        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD",
+        "BriefDescription": "Vertical IV Ring in Use; Down",
+        "EventCode": "0xAC",
+        "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x97",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC",
+        "BriefDescription": "Vertical IV Ring in Use; Up",
+        "EventCode": "0xAC",
+        "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x97",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC",
+        "BriefDescription": "WbPushMtoI; Pushed to LLC",
+        "EventCode": "0x56",
+        "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of times when the CHA was received WbPushMtoI; Counts the number of times when the CHA was able to push WbPushMToI to LLC",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x97",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC",
+        "BriefDescription": "WbPushMtoI; Pushed to Memory",
+        "EventCode": "0x56",
+        "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of times when the CHA was received WbPushMtoI; Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM)",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x97",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC0_SMI2",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 2 only.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x97",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC1_SMI3",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 3 only.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x97",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC2_SMI4",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 4 only.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x95",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_BNC",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC3_SMI5",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 5 only.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x95",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK_BNC",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC0_SMI0",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 0 only.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x95",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_BNC",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC1_SMI1",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 1 only.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x95",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV_BNC",
+        "BriefDescription": "Core Cross Snoop Responses; Any RspIFwdFE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response I to Fwd F/E",
+        "UMask": "0xe4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x95",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD",
+        "BriefDescription": "Core Cross Snoop Responses",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response I to Fwd M",
+        "UMask": "0xf0",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x95",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD",
+        "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdFE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response S to Fwd F/E",
+        "UMask": "0xe2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x99",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_BNC",
+        "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdM",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response S to Fwd M",
+        "UMask": "0xe8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x99",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.AK_BNC",
+        "BriefDescription": "Core Cross Snoop Responses; Any RspHitFSE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response any to Hit F/S/E",
+        "UMask": "0xe1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x99",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_BNC",
+        "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdFE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response I to Fwd F/E",
+        "UMask": "0x44",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x99",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.IV_BNC",
+        "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdM",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response I to Fwd M",
+        "UMask": "0x50",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x99",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD",
+        "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdFE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response S to Fwd F/E",
+        "UMask": "0x42",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x99",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD",
+        "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdM",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response S to Fwd M",
+        "UMask": "0x48",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC",
+        "BriefDescription": "Core Cross Snoop Responses; Core RspHitFSE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response any to Hit F/S/E",
+        "UMask": "0x41",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC",
+        "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdFE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response I to Fwd F/E",
+        "UMask": "0x84",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC",
+        "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdM",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response I to Fwd M",
+        "UMask": "0x90",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC",
+        "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdFE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response S to Fwd F/E",
+        "UMask": "0x82",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD",
+        "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdM",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response S to Fwd M",
+        "UMask": "0x88",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD",
+        "BriefDescription": "Core Cross Snoop Responses; Evict RspHitFSE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response any to Hit F/S/E",
+        "UMask": "0x81",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9B",
-        "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_BNC",
+        "BriefDescription": "Core Cross Snoop Responses; External RspIFwdFE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response I to Fwd F/E",
+        "UMask": "0x24",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9B",
-        "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK_BNC",
+        "BriefDescription": "Core Cross Snoop Responses; External RspIFwdM",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response I to Fwd M",
+        "UMask": "0x30",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9B",
-        "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_BNC",
+        "BriefDescription": "Core Cross Snoop Responses; External RspSFwdFE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response S to Fwd F/E",
+        "UMask": "0x22",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9B",
-        "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV_BNC",
+        "BriefDescription": "Core Cross Snoop Responses; External RspSFwdM",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response S to Fwd M",
+        "UMask": "0x28",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9C",
-        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0",
+        "BriefDescription": "Core Cross Snoop Responses; External RspHitFSE",
+        "EventCode": "0x32",
+        "EventName": "UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response any to Hit F/S/E",
+        "UMask": "0x21",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9C",
-        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CLOCKTICKS",
+        "Deprecated": "1",
+        "EventName": "UNC_C_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x02",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9C",
-        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_FAST_ASSERTED.HORZ",
+        "Deprecated": "1",
+        "EventCode": "0xA5",
+        "EventName": "UNC_C_FAST_ASSERTED",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9C",
-        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.ANY",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_C_LLC_LOOKUP.ANY",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9C",
-        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x3",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9C",
-        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOCAL",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_C_LLC_LOOKUP.LOCAL",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x31",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9E",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_C_LLC_LOOKUP.REMOTE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x91",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9E",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x9",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9E",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITE",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_C_LLC_LOOKUP.WRITE",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x5",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.IV",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E",
         "Deprecated": "1",
-        "EventCode": "0x9E",
-        "EventName": "UNC_H_TxR_VERT_BYPASS.IV_AG1",
+        "EventCode": "0x37",
+        "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9E",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F",
+        "Deprecated": "1",
+        "EventCode": "0x37",
+        "EventName": "UNC_C_LLC_VICTIMS.F_STATE",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9E",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
+        "Deprecated": "1",
+        "EventCode": "0x37",
+        "EventName": "UNC_C_LLC_VICTIMS.LOCAL",
+        "PerPkg": "1",
+        "UMask": "0x2f",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9E",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M",
+        "Deprecated": "1",
+        "EventCode": "0x37",
+        "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
+        "Deprecated": "1",
+        "EventCode": "0x37",
+        "EventName": "UNC_C_LLC_VICTIMS.REMOTE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S",
+        "Deprecated": "1",
+        "EventCode": "0x37",
+        "EventName": "UNC_C_LLC_VICTIMS.S_STATE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SRC_THRTL",
+        "Deprecated": "1",
+        "EventCode": "0xA4",
+        "EventName": "UNC_C_RING_SRC_THRTL",
         "PerPkg": "1",
-        "UMask": "0x04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.IV",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.EVICT",
         "Deprecated": "1",
-        "EventCode": "0x92",
-        "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.IV_AG0",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.EVICT",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.HIT",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.HIT",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IPQ",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.IPQ",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.IPQ_HIT",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x18",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x93",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.IPQ_MISS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x28",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x93",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.IRQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x31",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x93",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.IRQ_HIT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.IV",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS",
         "Deprecated": "1",
-        "EventCode": "0x93",
-        "EventName": "UNC_H_TxR_VERT_CYCLES_NE.IV_AG0",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.IRQ_MISS",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0x21",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x93",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.LOC_ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x37",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x93",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.LOC_IA",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x31",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x93",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.LOC_IO",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x34",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x91",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.MISS",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.MISS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x91",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.PRQ",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.PRQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x91",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_HIT",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.PRQ_HIT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x14",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.IV",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_MISS",
         "Deprecated": "1",
-        "EventCode": "0x91",
-        "EventName": "UNC_H_TxR_VERT_INSERTS.IV_AG0",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.PRQ_MISS",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0x24",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x91",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG1",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.REM_ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x30",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x91",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG1",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.RRQ_HIT",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x50",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x91",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG1",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.RRQ_MISS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x60",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG0",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.WBQ_HIT",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x90",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG0",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_C_TOR_INSERTS.WBQ_MISS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0xa0",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.EVICT",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.EVICT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK.IV",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.HIT",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.HIT",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IPQ",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.IPQ",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG1",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_HIT",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x18",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG1",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_MISS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x28",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.IRQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x31",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_HIT",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_HIT",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_MISS",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_MISS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x21",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.IV",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0x90",
-        "EventName": "UNC_H_TxR_VERT_OCCUPANCY.IV_AG0",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.LOC_ALL",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0x37",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IA",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x31",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IO",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x34",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.MISS",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.MISS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.PRQ",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.PRQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_HIT",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_HIT",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x14",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_MISS",
+        "Deprecated": "1",
+        "EventCode": "0x36",
+        "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_MISS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x24",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED.IV",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0",
+        "Deprecated": "1",
+        "EventCode": "0x80",
+        "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1",
+        "Deprecated": "1",
+        "EventCode": "0x80",
+        "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2",
+        "Deprecated": "1",
+        "EventCode": "0x80",
+        "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3",
+        "Deprecated": "1",
+        "EventCode": "0x80",
+        "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use; Up and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA6",
-        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4",
+        "Deprecated": "1",
+        "EventCode": "0x80",
+        "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use; Up and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA6",
-        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5",
+        "Deprecated": "1",
+        "EventCode": "0x80",
+        "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use; Down and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA6",
-        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0",
+        "Deprecated": "1",
+        "EventCode": "0x82",
+        "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use; Down and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA6",
-        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1",
+        "Deprecated": "1",
+        "EventCode": "0x82",
+        "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use; Up and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA8",
-        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2",
+        "Deprecated": "1",
+        "EventCode": "0x82",
+        "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use; Up and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA8",
-        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3",
+        "Deprecated": "1",
+        "EventCode": "0x82",
+        "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use; Down and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA8",
-        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4",
+        "Deprecated": "1",
+        "EventCode": "0x82",
+        "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use; Down and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA8",
-        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5",
+        "Deprecated": "1",
+        "EventCode": "0x82",
+        "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use; Up and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAA",
-        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0",
+        "Deprecated": "1",
+        "EventCode": "0x88",
+        "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use; Up and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAA",
-        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1",
+        "Deprecated": "1",
+        "EventCode": "0x88",
+        "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use; Down and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAA",
-        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2",
+        "Deprecated": "1",
+        "EventCode": "0x88",
+        "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use; Down and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAA",
-        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3",
+        "Deprecated": "1",
+        "EventCode": "0x88",
+        "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical IV Ring in Use; Up",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAC",
-        "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4",
+        "Deprecated": "1",
+        "EventCode": "0x88",
+        "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical IV Ring in Use; Down",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAC",
-        "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5",
+        "Deprecated": "1",
+        "EventCode": "0x88",
+        "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; External RspHitFSE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0",
+        "Deprecated": "1",
+        "EventCode": "0x8A",
+        "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Core RspHitFSE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1",
+        "Deprecated": "1",
+        "EventCode": "0x8A",
+        "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "UMask": "0x41",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Evict RspHitFSE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2",
+        "Deprecated": "1",
+        "EventCode": "0x8A",
+        "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0x81",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Any RspHitFSE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3",
+        "Deprecated": "1",
+        "EventCode": "0x8A",
+        "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0xE1",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; External RspSFwdFE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4",
+        "Deprecated": "1",
+        "EventCode": "0x8A",
+        "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
-        "UMask": "0x22",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdFE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5",
+        "Deprecated": "1",
+        "EventCode": "0x8A",
+        "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
-        "UMask": "0x42",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdFE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0",
+        "Deprecated": "1",
+        "EventCode": "0x84",
+        "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "UMask": "0x82",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdFE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1",
+        "Deprecated": "1",
+        "EventCode": "0x84",
+        "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "UMask": "0xE2",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; External RspIFwdFE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2",
+        "Deprecated": "1",
+        "EventCode": "0x84",
+        "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "UMask": "0x24",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdFE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3",
+        "Deprecated": "1",
+        "EventCode": "0x84",
+        "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdFE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4",
+        "Deprecated": "1",
+        "EventCode": "0x84",
+        "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
-        "UMask": "0x84",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Any RspIFwdFE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5",
+        "Deprecated": "1",
+        "EventCode": "0x84",
+        "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
-        "UMask": "0xE4",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; External RspSFwdM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0",
+        "Deprecated": "1",
+        "EventCode": "0x86",
+        "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0x28",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1",
+        "Deprecated": "1",
+        "EventCode": "0x86",
+        "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "UMask": "0x48",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2",
+        "Deprecated": "1",
+        "EventCode": "0x86",
+        "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0x88",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3",
+        "Deprecated": "1",
+        "EventCode": "0x86",
+        "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0xE8",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; External RspIFwdM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4",
+        "Deprecated": "1",
+        "EventCode": "0x86",
+        "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
-        "UMask": "0x30",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5",
+        "Deprecated": "1",
+        "EventCode": "0x86",
+        "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
-        "UMask": "0x50",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0",
+        "Deprecated": "1",
+        "EventCode": "0x8E",
+        "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0x90",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoop Responses",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1",
+        "Deprecated": "1",
+        "EventCode": "0x8E",
+        "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "UMask": "0xF0",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.IPQ_HIT",
+        "EventCode": "0x8E",
+        "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0x18",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.IPQ_MISS",
+        "EventCode": "0x8E",
+        "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0x28",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.RRQ_HIT",
+        "EventCode": "0x8E",
+        "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
-        "UMask": "0x50",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.RRQ_MISS",
+        "EventCode": "0x8E",
+        "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
-        "UMask": "0x60",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.WBQ_HIT",
+        "EventCode": "0x8C",
+        "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "UMask": "0x90",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_C_TOR_INSERTS.WBQ_MISS",
+        "EventCode": "0x8C",
+        "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "UMask": "0xA0",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_HIT",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2",
         "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_HIT",
+        "EventCode": "0x8C",
+        "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3",
         "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_MISS",
+        "EventCode": "0x8C",
+        "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR3",
         "PerPkg": "1",
-        "UMask": "0x24",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4",
         "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_HIT",
+        "EventCode": "0x8C",
+        "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR4",
         "PerPkg": "1",
-        "UMask": "0x18",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5",
         "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_MISS",
+        "EventCode": "0x8C",
+        "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR5",
         "PerPkg": "1",
-        "UMask": "0x28",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; All from Local IO",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
+        "Deprecated": "1",
+        "EventCode": "0x57",
+        "EventName": "UNC_H_BYPASS_CHA_IMC.INTERMEDIATE",
         "PerPkg": "1",
-        "UMask": "0x34",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; All from Local iA and IO",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.ALL_IO_IA",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
+        "Deprecated": "1",
+        "EventCode": "0x57",
+        "EventName": "UNC_H_BYPASS_CHA_IMC.NOT_TAKEN",
         "PerPkg": "1",
-        "UMask": "0x35",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; Hits from Local",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.ALL_HIT",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.TAKEN",
+        "Deprecated": "1",
+        "EventCode": "0x57",
+        "EventName": "UNC_H_BYPASS_CHA_IMC.TAKEN",
         "PerPkg": "1",
-        "UMask": "0x15",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; Misses from Local",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.ALL_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CMS_CLOCKTICKS",
+        "Deprecated": "1",
+        "EventCode": "0xC0",
+        "EventName": "UNC_H_CLOCK",
         "PerPkg": "1",
-        "UMask": "0x25",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; All from Local IO",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C1_STATE",
+        "Deprecated": "1",
+        "EventCode": "0x17",
+        "EventName": "UNC_H_CORE_PMA.C1_STATE",
         "PerPkg": "1",
-        "UMask": "0x34",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; Hits from Local IO",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C1_TRANSITION",
+        "Deprecated": "1",
+        "EventCode": "0x17",
+        "EventName": "UNC_H_CORE_PMA.C1_TRANSITION",
         "PerPkg": "1",
-        "UMask": "0x14",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; Misses from Local IO",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C6_STATE",
+        "Deprecated": "1",
+        "EventCode": "0x17",
+        "EventName": "UNC_H_CORE_PMA.C6_STATE",
         "PerPkg": "1",
-        "UMask": "0x24",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; Hits from Local",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_HIT",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C6_TRANSITION",
+        "Deprecated": "1",
+        "EventCode": "0x17",
+        "EventName": "UNC_H_CORE_PMA.C6_TRANSITION",
         "PerPkg": "1",
-        "UMask": "0x17",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; Misses from Local",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.GV",
+        "Deprecated": "1",
+        "EventCode": "0x17",
+        "EventName": "UNC_H_CORE_PMA.GV",
         "PerPkg": "1",
-        "UMask": "0x27",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credit Allocations; VNA Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VNA",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_GTONE",
+        "Deprecated": "1",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.ANY_GTONE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0xe2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credit Allocations; VN0 Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VN0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_ONE",
+        "Deprecated": "1",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.ANY_ONE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0xe1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credit Allocations; AD REQ Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_REQ",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_REMOTE",
+        "Deprecated": "1",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.ANY_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0xe4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credit Allocations; AD RSP VN0 Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_RSP",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE",
+        "Deprecated": "1",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.CORE_GTONE",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x42",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credit Allocations; BL RSP Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_RSP",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_ONE",
+        "Deprecated": "1",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.CORE_ONE",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x41",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credit Allocations; BL DRS Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_WB",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_REMOTE",
+        "Deprecated": "1",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.CORE_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x44",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credit Allocations; BL NCB Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCB",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE",
+        "Deprecated": "1",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.EVICT_GTONE",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x82",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credit Allocations; BL NCS Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_ONE",
+        "Deprecated": "1",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.EVICT_ONE",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x81",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credits In Use Cycles; AD VNA Credits",
-        "EventCode": "0x3B",
-        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_AD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_REMOTE",
+        "Deprecated": "1",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.EVICT_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x84",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credits In Use Cycles; BL VNA Credits",
-        "EventCode": "0x3B",
-        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_BL",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_GTONE",
+        "Deprecated": "1",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.EXT_GTONE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x22",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credits In Use Cycles; AD REQ VN0 Credits",
-        "EventCode": "0x3B",
-        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_REQ",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_ONE",
+        "Deprecated": "1",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.EXT_ONE",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x21",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credits In Use Cycles; AD RSP VN0 Credits",
-        "EventCode": "0x3B",
-        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_RSP",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_REMOTE",
+        "Deprecated": "1",
+        "EventCode": "0x33",
+        "EventName": "UNC_H_CORE_SNP.EXT_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x24",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credits In Use Cycles; BL RSP VN0 Credits",
-        "EventCode": "0x3B",
-        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_RSP",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_COUNTER0_OCCUPANCY",
+        "Deprecated": "1",
+        "EventCode": "0x1F",
+        "EventName": "UNC_H_COUNTER0_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credits In Use Cycles; BL DRS VN0 Credits",
-        "EventCode": "0x3B",
-        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_WB",
-        "PerPkg": "1",
-        "UMask": "0x20",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP",
+        "Deprecated": "1",
+        "EventCode": "0x53",
+        "EventName": "UNC_H_DIR_LOOKUP.NO_SNP",
+        "PerPkg": "1",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCB VN0 Credits",
-        "EventCode": "0x3B",
-        "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCB",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP",
+        "Deprecated": "1",
+        "EventCode": "0x53",
+        "EventName": "UNC_H_DIR_LOOKUP.SNP",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA",
+        "Deprecated": "1",
+        "EventCode": "0x54",
+        "EventName": "UNC_H_DIR_UPDATE.HA",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x22",
-        "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR",
+        "Deprecated": "1",
+        "EventCode": "0x54",
+        "EventName": "UNC_H_DIR_UPDATE.TOR",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
+        "Deprecated": "1",
+        "EventCode": "0xAE",
+        "EventName": "UNC_H_EGRESS_ORDERING.IV_SNOOPGO_DN",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
+        "Deprecated": "1",
+        "EventCode": "0xAE",
+        "EventName": "UNC_H_EGRESS_ORDERING.IV_SNOOPGO_UP",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects; Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS",
+        "Deprecated": "1",
+        "EventCode": "0x5F",
+        "EventName": "UNC_H_HITME_HIT.EX_RDS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects; Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.SHARED_OWNREQ",
+        "Deprecated": "1",
+        "EventCode": "0x5F",
+        "EventName": "UNC_H_HITME_HIT.SHARED_OWNREQ",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries; Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.WBMTOE",
+        "Deprecated": "1",
+        "EventCode": "0x5F",
+        "EventName": "UNC_H_HITME_HIT.WBMTOE",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries; Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.WBMTOI_OR_S",
+        "Deprecated": "1",
+        "EventCode": "0x5F",
+        "EventName": "UNC_H_HITME_HIT.WBMTOI_OR_S",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_LOOKUP.READ",
+        "Deprecated": "1",
+        "EventCode": "0x5E",
+        "EventName": "UNC_H_HITME_LOOKUP.READ",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_LOOKUP.WRITE",
+        "Deprecated": "1",
+        "EventCode": "0x5E",
+        "EventName": "UNC_H_HITME_LOOKUP.WRITE",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN",
+        "Deprecated": "1",
+        "EventCode": "0x60",
+        "EventName": "UNC_H_HITME_MISS.NOTSHARED_RDINVOWN",
         "PerPkg": "1",
         "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.READ_OR_INV",
+        "Deprecated": "1",
+        "EventCode": "0x60",
+        "EventName": "UNC_H_HITME_MISS.READ_OR_INV",
         "PerPkg": "1",
         "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.SHARED_RDINVOWN",
+        "Deprecated": "1",
+        "EventCode": "0x60",
+        "EventName": "UNC_H_HITME_MISS.SHARED_RDINVOWN",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.DEALLOCATE",
+        "Deprecated": "1",
+        "EventCode": "0x61",
+        "EventName": "UNC_H_HITME_UPDATE.DEALLOCATE",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
+        "Deprecated": "1",
+        "EventCode": "0x61",
+        "EventName": "UNC_H_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x26",
-        "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.RDINVOWN",
+        "Deprecated": "1",
+        "EventCode": "0x61",
+        "EventName": "UNC_H_HITME_UPDATE.RDINVOWN",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.RSPFWDI_REM",
+        "Deprecated": "1",
+        "EventCode": "0x61",
+        "EventName": "UNC_H_HITME_UPDATE.RSPFWDI_REM",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x28",
-        "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.SHARED",
+        "Deprecated": "1",
+        "EventCode": "0x61",
+        "EventName": "UNC_H_HITME_UPDATE.SHARED",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries; ANY0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+        "Deprecated": "1",
+        "EventCode": "0xA7",
+        "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoops Sent; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x51",
-        "EventName": "UNC_CHA_SNOOPS_SENT.ALL",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD",
+        "Deprecated": "1",
+        "EventCode": "0xA7",
+        "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoops Sent; Broadcast snoop for Local Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x51",
-        "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+        "Deprecated": "1",
+        "EventCode": "0xA7",
+        "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoops Sent; Broadcast snoops for Remote Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x51",
-        "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+        "Deprecated": "1",
+        "EventCode": "0xA7",
+        "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoops Sent; Directed snoops for Local Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x51",
-        "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+        "Deprecated": "1",
+        "EventCode": "0xA9",
+        "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoops Sent; Directed snoops for Remote Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x51",
-        "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD",
+        "Deprecated": "1",
+        "EventCode": "0xA9",
+        "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; RspI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+        "Deprecated": "1",
+        "EventCode": "0xA9",
+        "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; RspS",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+        "Deprecated": "1",
+        "EventCode": "0xA9",
+        "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; RspIFwd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+        "Deprecated": "1",
+        "EventCode": "0xAB",
+        "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; RspSFwd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD",
+        "Deprecated": "1",
+        "EventCode": "0xAB",
+        "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+        "Deprecated": "1",
+        "EventCode": "0xAB",
+        "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+        "Deprecated": "1",
+        "EventCode": "0xAB",
+        "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; RspCnflct",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_IV_IN_USE.LEFT",
+        "Deprecated": "1",
+        "EventCode": "0xAD",
+        "EventName": "UNC_H_HORZ_RING_IV_IN_USE.LEFT",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local; RspFwd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT",
+        "Deprecated": "1",
+        "EventCode": "0xAD",
+        "EventName": "UNC_H_HORZ_RING_IV_IN_USE.RIGHT",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Clockticks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_CHA_CMS_CLOCKTICKS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_READS_COUNT.NORMAL",
+        "Deprecated": "1",
+        "EventCode": "0x59",
+        "EventName": "UNC_H_IMC_READS_COUNT.NORMAL",
         "PerPkg": "1",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_READS_COUNT.PRIORITY",
+        "Deprecated": "1",
+        "EventCode": "0x59",
+        "EventName": "UNC_H_IMC_READS_COUNT.PRIORITY",
         "PerPkg": "1",
-        "UMask": "0x03",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cache and Snoop Filter Lookups; Write Requests",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.WRITE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL",
+        "Deprecated": "1",
+        "EventCode": "0x5B",
+        "EventName": "UNC_H_IMC_WRITES_COUNT.FULL",
         "PerPkg": "1",
-        "UMask": "0x05",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cache and Snoop Filter Lookups; External Snoop Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL_MIG",
+        "Deprecated": "1",
+        "EventCode": "0x5B",
+        "EventName": "UNC_H_IMC_WRITES_COUNT.FULL_MIG",
         "PerPkg": "1",
-        "UMask": "0x09",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cache and Snoop Filter Lookups; Any Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.ANY",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
+        "Deprecated": "1",
+        "EventCode": "0x5B",
+        "EventName": "UNC_H_IMC_WRITES_COUNT.FULL_PRIORITY",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cache and Snoop Filter Lookups; Local",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
+        "Deprecated": "1",
+        "EventCode": "0x5B",
+        "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL",
         "PerPkg": "1",
-        "UMask": "0x31",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cache and Snoop Filter Lookups; Remote",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG",
+        "Deprecated": "1",
+        "EventCode": "0x5B",
+        "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL_MIG",
         "PerPkg": "1",
-        "UMask": "0x91",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
         "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE",
+        "EventCode": "0x5B",
+        "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.INVITOM",
         "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE",
+        "EventCode": "0x62",
+        "EventName": "UNC_H_IODC_ALLOC.INVITOM",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.IODCFULL",
         "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE",
+        "EventCode": "0x62",
+        "EventName": "UNC_H_IODC_ALLOC.IODCFULL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.OSBGATED",
         "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.F_STATE",
+        "EventCode": "0x62",
+        "EventName": "UNC_H_IODC_ALLOC.OSBGATED",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized; Local - All Lines",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.ALL",
+        "Deprecated": "1",
+        "EventCode": "0x63",
+        "EventName": "UNC_H_IODC_DEALLOC.ALL",
         "PerPkg": "1",
-        "UMask": "0x2F",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.SNPOUT",
         "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE",
+        "EventCode": "0x63",
+        "EventName": "UNC_H_IODC_DEALLOC.SNPOUT",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; IRQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IRQ",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBMTOE",
+        "Deprecated": "1",
+        "EventCode": "0x63",
+        "EventName": "UNC_H_IODC_DEALLOC.WBMTOE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; SF/LLC Evictions",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.EVICT",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBMTOI",
+        "Deprecated": "1",
+        "EventCode": "0x63",
+        "EventName": "UNC_H_IODC_DEALLOC.WBMTOI",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; PRQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.PRQ",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBPUSHMTOI",
+        "Deprecated": "1",
+        "EventCode": "0x63",
+        "EventName": "UNC_H_IODC_DEALLOC.WBPUSHMTOI",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; IPQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IPQ",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.CV0_PREF_MISS",
+        "Deprecated": "1",
+        "EventCode": "0x39",
+        "EventName": "UNC_H_MISC.CV0_PREF_MISS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; Hit (Not a Miss)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.HIT",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.CV0_PREF_VIC",
+        "Deprecated": "1",
+        "EventCode": "0x39",
+        "EventName": "UNC_H_MISC.CV0_PREF_VIC",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; Miss",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S",
+        "Deprecated": "1",
+        "EventCode": "0x39",
+        "EventName": "UNC_H_MISC.RFO_HIT_S",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RSPI_WAS_FSE",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
+        "EventCode": "0x39",
+        "EventName": "UNC_H_MISC.RSPI_WAS_FSE",
         "PerPkg": "1",
-        "UMask": "0x37",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.WC_ALIASING",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IPQ_HIT",
+        "EventCode": "0x39",
+        "EventName": "UNC_H_MISC.WC_ALIASING",
         "PerPkg": "1",
-        "UMask": "0x18",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_OSB",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IPQ_MISS",
+        "EventCode": "0x55",
+        "EventName": "UNC_H_OSB",
         "PerPkg": "1",
-        "UMask": "0x28",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC0_SMI2",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.RRQ_HIT",
+        "EventCode": "0x58",
+        "EventName": "UNC_H_READ_NO_CREDITS.EDC0_SMI2",
         "PerPkg": "1",
-        "UMask": "0x50",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC1_SMI3",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS",
+        "EventCode": "0x58",
+        "EventName": "UNC_H_READ_NO_CREDITS.EDC1_SMI3",
         "PerPkg": "1",
-        "UMask": "0x60",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC2_SMI4",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.WBQ_HIT",
+        "EventCode": "0x58",
+        "EventName": "UNC_H_READ_NO_CREDITS.EDC2_SMI4",
         "PerPkg": "1",
-        "UMask": "0x90",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC3_SMI5",
         "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.WBQ_MISS",
+        "EventCode": "0x58",
+        "EventName": "UNC_H_READ_NO_CREDITS.EDC3_SMI5",
         "PerPkg": "1",
-        "UMask": "0xA0",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; IRQ",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.MC0_SMI0",
+        "Deprecated": "1",
+        "EventCode": "0x58",
+        "EventName": "UNC_H_READ_NO_CREDITS.MC0_SMI0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; SF/LLC Evictions",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.MC1_SMI1",
+        "Deprecated": "1",
+        "EventCode": "0x58",
+        "EventName": "UNC_H_READ_NO_CREDITS.MC1_SMI1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; PRQ",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL",
+        "Deprecated": "1",
+        "EventCode": "0x50",
+        "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; IPQ",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE",
+        "Deprecated": "1",
+        "EventCode": "0x50",
+        "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; Hit (Not a Miss)",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
+        "BriefDescription": "read requests from home agent",
+        "Deprecated": "1",
+        "EventCode": "0x50",
+        "EventName": "UNC_H_REQUESTS.READS",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x3",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; Miss",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
+        "BriefDescription": "read requests from local home agent",
+        "Deprecated": "1",
+        "EventCode": "0x50",
+        "EventName": "UNC_H_REQUESTS.READS_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC",
+        "BriefDescription": "read requests from remote home agent",
         "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
+        "EventCode": "0x50",
+        "EventName": "UNC_H_REQUESTS.READS_REMOTE",
         "PerPkg": "1",
-        "UMask": "0x37",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
+        "BriefDescription": "write requests from home agent",
         "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_HIT",
+        "EventCode": "0x50",
+        "EventName": "UNC_H_REQUESTS.WRITES",
         "PerPkg": "1",
-        "UMask": "0x18",
+        "UMask": "0xc",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
+        "BriefDescription": "write requests from local home agent",
         "Deprecated": "1",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_MISS",
+        "EventCode": "0x50",
+        "EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x28",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Source Throttle",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA4",
-        "EventName": "UNC_CHA_RING_SRC_THRTL",
+        "BriefDescription": "write requests from remote home agent",
+        "Deprecated": "1",
+        "EventCode": "0x50",
+        "EventName": "UNC_H_REQUESTS.WRITES_REMOTE",
         "PerPkg": "1",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress Probe Queue Rejects; ANY0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x23",
-        "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.AD",
+        "Deprecated": "1",
+        "EventCode": "0xA1",
+        "EventName": "UNC_H_RING_BOUNCES_HORZ.AD",
         "PerPkg": "1",
         "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.AK",
+        "Deprecated": "1",
+        "EventCode": "0xA1",
+        "EventName": "UNC_H_RING_BOUNCES_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects; ANY0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x25",
-        "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.BL",
+        "Deprecated": "1",
+        "EventCode": "0xA1",
+        "EventName": "UNC_H_RING_BOUNCES_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries; ANY0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2D",
-        "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.IV",
+        "Deprecated": "1",
+        "EventCode": "0xA1",
+        "EventName": "UNC_H_RING_BOUNCES_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries; ANY0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.AD",
+        "Deprecated": "1",
+        "EventCode": "0xA0",
+        "EventName": "UNC_H_RING_BOUNCES_VERT.AD",
         "PerPkg": "1",
         "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.AK",
+        "Deprecated": "1",
+        "EventCode": "0xA0",
+        "EventName": "UNC_H_RING_BOUNCES_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "RRQ Rejects; ANY0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x27",
-        "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.BL",
+        "Deprecated": "1",
+        "EventCode": "0xA0",
+        "EventName": "UNC_H_RING_BOUNCES_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WBQ Rejects; ANY0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x29",
-        "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.IV",
+        "Deprecated": "1",
+        "EventCode": "0xA0",
+        "EventName": "UNC_H_RING_BOUNCES_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9E",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV",
-        "PerPkg": "1",
-        "UMask": "0x08",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AD",
+        "Deprecated": "1",
+        "EventCode": "0xA3",
+        "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AD",
+        "PerPkg": "1",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.IV",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AK",
+        "Deprecated": "1",
+        "EventCode": "0xA3",
+        "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1",
+        "Deprecated": "1",
+        "EventCode": "0xA3",
+        "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK_AG1",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.BL",
+        "Deprecated": "1",
+        "EventCode": "0xA3",
+        "EventName": "UNC_H_RING_SINK_STARVED_HORZ.BL",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.IV",
+        "Deprecated": "1",
+        "EventCode": "0xA3",
+        "EventName": "UNC_H_RING_SINK_STARVED_HORZ.IV",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.AD",
+        "Deprecated": "1",
+        "EventCode": "0xA2",
+        "EventName": "UNC_H_RING_SINK_STARVED_VERT.AD",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.AK",
+        "Deprecated": "1",
+        "EventCode": "0xA2",
+        "EventName": "UNC_H_RING_SINK_STARVED_VERT.AK",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.BL",
+        "Deprecated": "1",
+        "EventCode": "0xA2",
+        "EventName": "UNC_H_RING_SINK_STARVED_VERT.BL",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.IV",
+        "Deprecated": "1",
+        "EventCode": "0xA2",
+        "EventName": "UNC_H_RING_SINK_STARVED_VERT.IV",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IPQ",
+        "Deprecated": "1",
+        "EventCode": "0x13",
+        "EventName": "UNC_H_RxC_INSERTS.IPQ",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ",
+        "Deprecated": "1",
+        "EventCode": "0x13",
+        "EventName": "UNC_H_RxC_INSERTS.IRQ",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ_REJ",
+        "Deprecated": "1",
+        "EventCode": "0x13",
+        "EventName": "UNC_H_RxC_INSERTS.IRQ_REJ",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.PRQ",
+        "Deprecated": "1",
+        "EventCode": "0x13",
+        "EventName": "UNC_H_RxC_INSERTS.PRQ",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.PRQ_REJ",
+        "Deprecated": "1",
+        "EventCode": "0x13",
+        "EventName": "UNC_H_RxC_INSERTS.PRQ_REJ",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.RRQ",
+        "Deprecated": "1",
+        "EventCode": "0x13",
+        "EventName": "UNC_H_RxC_INSERTS.RRQ",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.WBQ",
+        "Deprecated": "1",
+        "EventCode": "0x13",
+        "EventName": "UNC_H_RxC_INSERTS.WBQ",
+        "PerPkg": "1",
+        "UMask": "0x80",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x22",
+        "EventName": "UNC_H_RxC_IPQ0_REJECT.AD_REQ_VN0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x22",
+        "EventName": "UNC_H_RxC_IPQ0_REJECT.AD_RSP_VN0",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x22",
+        "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_NCB_VN0",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x22",
+        "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_NCS_VN0",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x22",
+        "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_RSP_VN0",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x22",
+        "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_WB_VN0",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP",
+        "Deprecated": "1",
+        "EventCode": "0x23",
+        "EventName": "UNC_H_RxC_IPQ1_REJECT.ALLOW_SNP",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ANY0",
+        "Deprecated": "1",
+        "EventCode": "0x23",
+        "EventName": "UNC_H_RxC_IPQ1_REJECT.ANY_IPQ0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.HA",
+        "Deprecated": "1",
+        "EventCode": "0x23",
+        "EventName": "UNC_H_RxC_IPQ1_REJECT.HA",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
+        "Deprecated": "1",
+        "EventCode": "0x23",
+        "EventName": "UNC_H_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM",
+        "Deprecated": "1",
+        "EventCode": "0x23",
+        "EventName": "UNC_H_RxC_IPQ1_REJECT.LLC_VICTIM",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH",
+        "Deprecated": "1",
+        "EventCode": "0x23",
+        "EventName": "UNC_H_RxC_IPQ1_REJECT.PA_MATCH",
+        "PerPkg": "1",
+        "UMask": "0x80",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM",
+        "Deprecated": "1",
+        "EventCode": "0x23",
+        "EventName": "UNC_H_RxC_IPQ1_REJECT.SF_VICTIM",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.VICTIM",
+        "Deprecated": "1",
+        "EventCode": "0x23",
+        "EventName": "UNC_H_RxC_IPQ1_REJECT.VICTIM",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x18",
+        "EventName": "UNC_H_RxC_IRQ0_REJECT.AD_REQ_VN0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x18",
+        "EventName": "UNC_H_RxC_IRQ0_REJECT.AD_RSP_VN0",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x18",
+        "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_NCB_VN0",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x18",
+        "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_NCS_VN0",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x18",
+        "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_RSP_VN0",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x18",
+        "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_WB_VN0",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
+        "Deprecated": "1",
+        "EventCode": "0x19",
+        "EventName": "UNC_H_RxC_IRQ1_REJECT.ALLOW_SNP",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ANY0",
+        "Deprecated": "1",
+        "EventCode": "0x19",
+        "EventName": "UNC_H_RxC_IRQ1_REJECT.ANY_REJECT_IRQ0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.HA",
+        "Deprecated": "1",
+        "EventCode": "0x19",
+        "EventName": "UNC_H_RxC_IRQ1_REJECT.HA",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
+        "Deprecated": "1",
+        "EventCode": "0x19",
+        "EventName": "UNC_H_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
+        "Deprecated": "1",
+        "EventCode": "0x19",
+        "EventName": "UNC_H_RxC_IRQ1_REJECT.LLC_VICTIM",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
+        "Deprecated": "1",
+        "EventCode": "0x19",
+        "EventName": "UNC_H_RxC_IRQ1_REJECT.PA_MATCH",
+        "PerPkg": "1",
+        "UMask": "0x80",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
+        "Deprecated": "1",
+        "EventCode": "0x19",
+        "EventName": "UNC_H_RxC_IRQ1_REJECT.SF_VICTIM",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
+        "Deprecated": "1",
+        "EventCode": "0x19",
+        "EventName": "UNC_H_RxC_IRQ1_REJECT.VICTIM",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x24",
+        "EventName": "UNC_H_RxC_ISMQ0_REJECT.AD_REQ_VN0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x24",
+        "EventName": "UNC_H_RxC_ISMQ0_REJECT.AD_RSP_VN0",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x24",
+        "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_NCB_VN0",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x24",
+        "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_NCS_VN0",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x24",
+        "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_RSP_VN0",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x24",
+        "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_WB_VN0",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x2C",
+        "EventName": "UNC_H_RxC_ISMQ0_RETRY.AD_REQ_VN0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x2C",
+        "EventName": "UNC_H_RxC_ISMQ0_RETRY.AD_RSP_VN0",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x2C",
+        "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_NCB_VN0",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x2C",
+        "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_NCS_VN0",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x2C",
+        "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_RSP_VN0",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x2C",
+        "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_WB_VN0",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
+        "Deprecated": "1",
+        "EventCode": "0x25",
+        "EventName": "UNC_H_RxC_ISMQ1_REJECT.ANY_ISMQ0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.HA",
+        "Deprecated": "1",
+        "EventCode": "0x25",
+        "EventName": "UNC_H_RxC_ISMQ1_REJECT.HA",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
+        "Deprecated": "1",
+        "EventCode": "0x2D",
+        "EventName": "UNC_H_RxC_ISMQ1_RETRY.ANY",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.HA",
+        "Deprecated": "1",
+        "EventCode": "0x2D",
+        "EventName": "UNC_H_RxC_ISMQ1_RETRY.HA",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IPQ",
+        "Deprecated": "1",
+        "EventCode": "0x11",
+        "EventName": "UNC_H_RxC_OCCUPANCY.IPQ",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ",
+        "Deprecated": "1",
+        "EventCode": "0x11",
+        "EventName": "UNC_H_RxC_OCCUPANCY.IRQ",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.RRQ",
+        "Deprecated": "1",
+        "EventCode": "0x11",
+        "EventName": "UNC_H_RxC_OCCUPANCY.RRQ",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.WBQ",
+        "Deprecated": "1",
+        "EventCode": "0x11",
+        "EventName": "UNC_H_RxC_OCCUPANCY.WBQ",
+        "PerPkg": "1",
+        "UMask": "0x80",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x2E",
+        "EventName": "UNC_H_RxC_OTHER0_RETRY.AD_REQ_VN0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x2E",
+        "EventName": "UNC_H_RxC_OTHER0_RETRY.AD_RSP_VN0",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x2E",
+        "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_NCB_VN0",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x2E",
+        "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_NCS_VN0",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x2E",
+        "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_RSP_VN0",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x2E",
+        "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_WB_VN0",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
+        "Deprecated": "1",
+        "EventCode": "0x2F",
+        "EventName": "UNC_H_RxC_OTHER1_RETRY.ALLOW_SNP",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ANY0",
+        "Deprecated": "1",
+        "EventCode": "0x2F",
+        "EventName": "UNC_H_RxC_OTHER1_RETRY.ANY",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.HA",
+        "Deprecated": "1",
+        "EventCode": "0x2F",
+        "EventName": "UNC_H_RxC_OTHER1_RETRY.HA",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
+        "Deprecated": "1",
+        "EventCode": "0x2F",
+        "EventName": "UNC_H_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
+        "Deprecated": "1",
+        "EventCode": "0x2F",
+        "EventName": "UNC_H_RxC_OTHER1_RETRY.LLC_VICTIM",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
+        "Deprecated": "1",
+        "EventCode": "0x2F",
+        "EventName": "UNC_H_RxC_OTHER1_RETRY.PA_MATCH",
+        "PerPkg": "1",
+        "UMask": "0x80",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
+        "Deprecated": "1",
+        "EventCode": "0x2F",
+        "EventName": "UNC_H_RxC_OTHER1_RETRY.SF_VICTIM",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
+        "Deprecated": "1",
+        "EventCode": "0x2F",
+        "EventName": "UNC_H_RxC_OTHER1_RETRY.VICTIM",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x20",
+        "EventName": "UNC_H_RxC_PRQ0_REJECT.AD_REQ_VN0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x20",
+        "EventName": "UNC_H_RxC_PRQ0_REJECT.AD_RSP_VN0",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x20",
+        "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_NCB_VN0",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x20",
+        "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_NCS_VN0",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x20",
+        "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_RSP_VN0",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x20",
+        "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_WB_VN0",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
+        "Deprecated": "1",
+        "EventCode": "0x21",
+        "EventName": "UNC_H_RxC_PRQ1_REJECT.ALLOW_SNP",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ANY0",
+        "Deprecated": "1",
+        "EventCode": "0x21",
+        "EventName": "UNC_H_RxC_PRQ1_REJECT.ANY_PRQ0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.HA",
+        "Deprecated": "1",
+        "EventCode": "0x21",
+        "EventName": "UNC_H_RxC_PRQ1_REJECT.HA",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
+        "Deprecated": "1",
+        "EventCode": "0x21",
+        "EventName": "UNC_H_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
+        "Deprecated": "1",
+        "EventCode": "0x21",
+        "EventName": "UNC_H_RxC_PRQ1_REJECT.LLC_VICTIM",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
+        "Deprecated": "1",
+        "EventCode": "0x21",
+        "EventName": "UNC_H_RxC_PRQ1_REJECT.PA_MATCH",
+        "PerPkg": "1",
+        "UMask": "0x80",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
+        "Deprecated": "1",
+        "EventCode": "0x21",
+        "EventName": "UNC_H_RxC_PRQ1_REJECT.SF_VICTIM",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
+        "Deprecated": "1",
+        "EventCode": "0x21",
+        "EventName": "UNC_H_RxC_PRQ1_REJECT.VICTIM",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x2A",
+        "EventName": "UNC_H_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x2A",
+        "EventName": "UNC_H_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x2A",
+        "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x2A",
+        "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x2A",
+        "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x2A",
+        "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_WB_VN0",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
+        "Deprecated": "1",
+        "EventCode": "0x2B",
+        "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ALLOW_SNP",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
+        "Deprecated": "1",
+        "EventCode": "0x2B",
+        "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ANY",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.HA",
+        "Deprecated": "1",
+        "EventCode": "0x2B",
+        "EventName": "UNC_H_RxC_REQ_Q1_RETRY.HA",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
+        "Deprecated": "1",
+        "EventCode": "0x2B",
+        "EventName": "UNC_H_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
+        "Deprecated": "1",
+        "EventCode": "0x2B",
+        "EventName": "UNC_H_RxC_REQ_Q1_RETRY.LLC_VICTIM",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
+        "Deprecated": "1",
+        "EventCode": "0x2B",
+        "EventName": "UNC_H_RxC_REQ_Q1_RETRY.PA_MATCH",
+        "PerPkg": "1",
+        "UMask": "0x80",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
+        "Deprecated": "1",
+        "EventCode": "0x2B",
+        "EventName": "UNC_H_RxC_REQ_Q1_RETRY.SF_VICTIM",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
+        "Deprecated": "1",
+        "EventCode": "0x2B",
+        "EventName": "UNC_H_RxC_REQ_Q1_RETRY.VICTIM",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x26",
+        "EventName": "UNC_H_RxC_RRQ0_REJECT.AD_REQ_VN0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x26",
+        "EventName": "UNC_H_RxC_RRQ0_REJECT.AD_RSP_VN0",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x26",
+        "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_NCB_VN0",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x26",
+        "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_NCS_VN0",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x26",
+        "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_RSP_VN0",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x26",
+        "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_WB_VN0",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP",
+        "Deprecated": "1",
+        "EventCode": "0x27",
+        "EventName": "UNC_H_RxC_RRQ1_REJECT.ALLOW_SNP",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ANY0",
+        "Deprecated": "1",
+        "EventCode": "0x27",
+        "EventName": "UNC_H_RxC_RRQ1_REJECT.ANY_RRQ0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.HA",
+        "Deprecated": "1",
+        "EventCode": "0x27",
+        "EventName": "UNC_H_RxC_RRQ1_REJECT.HA",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
+        "Deprecated": "1",
+        "EventCode": "0x27",
+        "EventName": "UNC_H_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM",
+        "Deprecated": "1",
+        "EventCode": "0x27",
+        "EventName": "UNC_H_RxC_RRQ1_REJECT.LLC_VICTIM",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH",
+        "Deprecated": "1",
+        "EventCode": "0x27",
+        "EventName": "UNC_H_RxC_RRQ1_REJECT.PA_MATCH",
+        "PerPkg": "1",
+        "UMask": "0x80",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM",
+        "Deprecated": "1",
+        "EventCode": "0x27",
+        "EventName": "UNC_H_RxC_RRQ1_REJECT.SF_VICTIM",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.VICTIM",
+        "Deprecated": "1",
+        "EventCode": "0x27",
+        "EventName": "UNC_H_RxC_RRQ1_REJECT.VICTIM",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x28",
+        "EventName": "UNC_H_RxC_WBQ0_REJECT.AD_REQ_VN0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x28",
+        "EventName": "UNC_H_RxC_WBQ0_REJECT.AD_RSP_VN0",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x28",
+        "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_NCB_VN0",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x28",
+        "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_NCS_VN0",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x28",
+        "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_RSP_VN0",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0",
+        "Deprecated": "1",
+        "EventCode": "0x28",
+        "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_WB_VN0",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP",
+        "Deprecated": "1",
+        "EventCode": "0x29",
+        "EventName": "UNC_H_RxC_WBQ1_REJECT.ALLOW_SNP",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ANY0",
+        "Deprecated": "1",
+        "EventCode": "0x29",
+        "EventName": "UNC_H_RxC_WBQ1_REJECT.ANY_WBQ0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.HA",
+        "Deprecated": "1",
+        "EventCode": "0x29",
+        "EventName": "UNC_H_RxC_WBQ1_REJECT.HA",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
+        "Deprecated": "1",
+        "EventCode": "0x29",
+        "EventName": "UNC_H_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM",
+        "Deprecated": "1",
+        "EventCode": "0x29",
+        "EventName": "UNC_H_RxC_WBQ1_REJECT.LLC_VICTIM",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH",
+        "Deprecated": "1",
+        "EventCode": "0x29",
+        "EventName": "UNC_H_RxC_WBQ1_REJECT.PA_MATCH",
+        "PerPkg": "1",
+        "UMask": "0x80",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM",
+        "Deprecated": "1",
+        "EventCode": "0x29",
+        "EventName": "UNC_H_RxC_WBQ1_REJECT.SF_VICTIM",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.VICTIM",
+        "Deprecated": "1",
+        "EventCode": "0x29",
+        "EventName": "UNC_H_RxC_WBQ1_REJECT.VICTIM",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.AD_BNC",
+        "Deprecated": "1",
+        "EventCode": "0xB4",
+        "EventName": "UNC_H_RxR_BUSY_STARVED.AD_BNC",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.AD_CRD",
+        "Deprecated": "1",
+        "EventCode": "0xB4",
+        "EventName": "UNC_H_RxR_BUSY_STARVED.AD_CRD",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.BL_BNC",
+        "Deprecated": "1",
+        "EventCode": "0xB4",
+        "EventName": "UNC_H_RxR_BUSY_STARVED.BL_BNC",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.BL_CRD",
+        "Deprecated": "1",
+        "EventCode": "0xB4",
+        "EventName": "UNC_H_RxR_BUSY_STARVED.BL_CRD",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AD_BNC",
+        "Deprecated": "1",
+        "EventCode": "0xB2",
+        "EventName": "UNC_H_RxR_BYPASS.AD_BNC",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AD_CRD",
+        "Deprecated": "1",
+        "EventCode": "0xB2",
+        "EventName": "UNC_H_RxR_BYPASS.AD_CRD",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AK_BNC",
+        "Deprecated": "1",
+        "EventCode": "0xB2",
+        "EventName": "UNC_H_RxR_BYPASS.AK_BNC",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.BL_BNC",
+        "Deprecated": "1",
+        "EventCode": "0xB2",
+        "EventName": "UNC_H_RxR_BYPASS.BL_BNC",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.BL_CRD",
+        "Deprecated": "1",
+        "EventCode": "0xB2",
+        "EventName": "UNC_H_RxR_BYPASS.BL_CRD",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.IV_BNC",
+        "Deprecated": "1",
+        "EventCode": "0xB2",
+        "EventName": "UNC_H_RxR_BYPASS.IV_BNC",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AD_BNC",
+        "Deprecated": "1",
+        "EventCode": "0xB3",
+        "EventName": "UNC_H_RxR_CRD_STARVED.AD_BNC",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AD_CRD",
+        "Deprecated": "1",
+        "EventCode": "0xB3",
+        "EventName": "UNC_H_RxR_CRD_STARVED.AD_CRD",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AK_BNC",
+        "Deprecated": "1",
+        "EventCode": "0xB3",
+        "EventName": "UNC_H_RxR_CRD_STARVED.AK_BNC",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.BL_BNC",
+        "Deprecated": "1",
+        "EventCode": "0xB3",
+        "EventName": "UNC_H_RxR_CRD_STARVED.BL_BNC",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.BL_CRD",
+        "Deprecated": "1",
+        "EventCode": "0xB3",
+        "EventName": "UNC_H_RxR_CRD_STARVED.BL_CRD",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.IFV",
+        "Deprecated": "1",
+        "EventCode": "0xB3",
+        "EventName": "UNC_H_RxR_CRD_STARVED.IFV",
+        "PerPkg": "1",
+        "UMask": "0x80",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.IV_BNC",
+        "Deprecated": "1",
+        "EventCode": "0xB3",
+        "EventName": "UNC_H_RxR_CRD_STARVED.IV_BNC",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AD_BNC",
+        "Deprecated": "1",
+        "EventCode": "0xB1",
+        "EventName": "UNC_H_RxR_INSERTS.AD_BNC",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AD_CRD",
+        "Deprecated": "1",
+        "EventCode": "0xB1",
+        "EventName": "UNC_H_RxR_INSERTS.AD_CRD",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AK_BNC",
+        "Deprecated": "1",
+        "EventCode": "0xB1",
+        "EventName": "UNC_H_RxR_INSERTS.AK_BNC",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.BL_BNC",
+        "Deprecated": "1",
+        "EventCode": "0xB1",
+        "EventName": "UNC_H_RxR_INSERTS.BL_BNC",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.BL_CRD",
+        "Deprecated": "1",
+        "EventCode": "0xB1",
+        "EventName": "UNC_H_RxR_INSERTS.BL_CRD",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.IV_BNC",
+        "Deprecated": "1",
+        "EventCode": "0xB1",
+        "EventName": "UNC_H_RxR_INSERTS.IV_BNC",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AD_BNC",
+        "Deprecated": "1",
+        "EventCode": "0xB0",
+        "EventName": "UNC_H_RxR_OCCUPANCY.AD_BNC",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AD_CRD",
+        "Deprecated": "1",
+        "EventCode": "0xB0",
+        "EventName": "UNC_H_RxR_OCCUPANCY.AD_CRD",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AK_BNC",
+        "Deprecated": "1",
+        "EventCode": "0xB0",
+        "EventName": "UNC_H_RxR_OCCUPANCY.AK_BNC",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.BL_BNC",
+        "Deprecated": "1",
+        "EventCode": "0xB0",
+        "EventName": "UNC_H_RxR_OCCUPANCY.BL_BNC",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.BL_CRD",
+        "Deprecated": "1",
+        "EventCode": "0xB0",
+        "EventName": "UNC_H_RxR_OCCUPANCY.BL_CRD",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.IV_BNC",
+        "Deprecated": "1",
+        "EventCode": "0xB0",
+        "EventName": "UNC_H_RxR_OCCUPANCY.IV_BNC",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.E_STATE",
+        "Deprecated": "1",
+        "EventCode": "0x3D",
+        "EventName": "UNC_H_SF_EVICTION.E_STATE",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.M_STATE",
+        "Deprecated": "1",
+        "EventCode": "0x3D",
+        "EventName": "UNC_H_SF_EVICTION.M_STATE",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.S_STATE",
+        "Deprecated": "1",
+        "EventCode": "0x3D",
+        "EventName": "UNC_H_SF_EVICTION.S_STATE",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.ALL",
+        "Deprecated": "1",
+        "EventCode": "0x51",
+        "EventName": "UNC_H_SNOOPS_SENT.",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
+        "Deprecated": "1",
+        "EventCode": "0x51",
+        "EventName": "UNC_H_SNOOPS_SENT.BCST_LOC",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_REMOTE",
+        "Deprecated": "1",
+        "EventCode": "0x51",
+        "EventName": "UNC_H_SNOOPS_SENT.BCST_REM",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
+        "Deprecated": "1",
+        "EventCode": "0x51",
+        "EventName": "UNC_H_SNOOPS_SENT.DIRECT_LOC",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE",
+        "Deprecated": "1",
+        "EventCode": "0x51",
+        "EventName": "UNC_H_SNOOPS_SENT.DIRECT_REM",
+        "PerPkg": "1",
+        "UMask": "0x80",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.LOCAL",
+        "Deprecated": "1",
+        "EventCode": "0x51",
+        "EventName": "UNC_H_SNOOPS_SENT.LOCAL",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.REMOTE",
+        "Deprecated": "1",
+        "EventCode": "0x51",
+        "EventName": "UNC_H_SNOOPS_SENT.REMOTE",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPCNFLCTS",
+        "Deprecated": "1",
+        "EventCode": "0x5C",
+        "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPFWD",
+        "Deprecated": "1",
+        "EventCode": "0x5C",
+        "EventName": "UNC_H_SNOOP_RESP.RSPFWD",
+        "PerPkg": "1",
+        "UMask": "0x80",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPI",
+        "Deprecated": "1",
+        "EventCode": "0x5C",
+        "EventName": "UNC_H_SNOOP_RESP.RSPI",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD",
+        "Deprecated": "1",
+        "EventCode": "0x5C",
+        "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPS",
+        "Deprecated": "1",
+        "EventCode": "0x5C",
+        "EventName": "UNC_H_SNOOP_RESP.RSPS",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD",
+        "Deprecated": "1",
+        "EventCode": "0x5C",
+        "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB",
+        "Deprecated": "1",
+        "EventCode": "0x5C",
+        "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_WBWB",
+        "Deprecated": "1",
+        "EventCode": "0x5C",
+        "EventName": "UNC_H_SNOOP_RESP.RSP_WB",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
+        "Deprecated": "1",
+        "EventCode": "0x5D",
+        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPCNFLCT",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
+        "Deprecated": "1",
+        "EventCode": "0x5D",
+        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPFWD",
+        "PerPkg": "1",
+        "UMask": "0x80",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
+        "Deprecated": "1",
+        "EventCode": "0x5D",
+        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPI",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
+        "Deprecated": "1",
+        "EventCode": "0x5D",
+        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPIFWD",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
+        "Deprecated": "1",
+        "EventCode": "0x5D",
+        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPS",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
+        "Deprecated": "1",
+        "EventCode": "0x5D",
+        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPSFWD",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB",
+        "Deprecated": "1",
+        "EventCode": "0x5D",
+        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_FWD_WB",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB",
+        "Deprecated": "1",
+        "EventCode": "0x5D",
+        "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_WB",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+        "Deprecated": "1",
+        "EventCode": "0xD0",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+        "Deprecated": "1",
+        "EventCode": "0xD0",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+        "Deprecated": "1",
+        "EventCode": "0xD0",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+        "Deprecated": "1",
+        "EventCode": "0xD0",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+        "Deprecated": "1",
+        "EventCode": "0xD0",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+        "Deprecated": "1",
+        "EventCode": "0xD0",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+        "Deprecated": "1",
+        "EventCode": "0xD2",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+        "Deprecated": "1",
+        "EventCode": "0xD2",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+        "Deprecated": "1",
+        "EventCode": "0xD2",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+        "Deprecated": "1",
+        "EventCode": "0xD2",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+        "Deprecated": "1",
+        "EventCode": "0xD2",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+        "Deprecated": "1",
+        "EventCode": "0xD2",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+        "Deprecated": "1",
+        "EventCode": "0xD4",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+        "Deprecated": "1",
+        "EventCode": "0xD4",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+        "Deprecated": "1",
+        "EventCode": "0xD4",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+        "Deprecated": "1",
+        "EventCode": "0xD4",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+        "Deprecated": "1",
+        "EventCode": "0xD4",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+        "Deprecated": "1",
+        "EventCode": "0xD4",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+        "Deprecated": "1",
+        "EventCode": "0xD6",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+        "Deprecated": "1",
+        "EventCode": "0xD6",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+        "Deprecated": "1",
+        "EventCode": "0xD6",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+        "Deprecated": "1",
+        "EventCode": "0xD6",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+        "Deprecated": "1",
+        "EventCode": "0xD6",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+        "Deprecated": "1",
+        "EventCode": "0xD6",
+        "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_H_TxR_HORZ_ADS_USED.AD_BNC",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_H_TxR_HORZ_ADS_USED.AD_CRD",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_H_TxR_HORZ_ADS_USED.AK_BNC",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_H_TxR_HORZ_ADS_USED.BL_BNC",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_H_TxR_HORZ_ADS_USED.BL_CRD",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AD_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x9F",
+        "EventName": "UNC_H_TxR_HORZ_BYPASS.AD_BNC",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AD_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x9F",
+        "EventName": "UNC_H_TxR_HORZ_BYPASS.AD_CRD",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AK_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x9F",
+        "EventName": "UNC_H_TxR_HORZ_BYPASS.AK_BNC",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.BL_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x9F",
+        "EventName": "UNC_H_TxR_HORZ_BYPASS.BL_BNC",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.BL_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x9F",
+        "EventName": "UNC_H_TxR_HORZ_BYPASS.BL_CRD",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.IV_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x9F",
+        "EventName": "UNC_H_TxR_HORZ_BYPASS.IV_BNC",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x96",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AD_BNC",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x96",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AD_CRD",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x96",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AK_BNC",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x96",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.BL_BNC",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x96",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.BL_CRD",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x96",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.IV_BNC",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x97",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AD_BNC",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x97",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AD_CRD",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x97",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AK_BNC",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x97",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.BL_BNC",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x97",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.BL_CRD",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x97",
+        "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.IV_BNC",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AD_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x95",
+        "EventName": "UNC_H_TxR_HORZ_INSERTS.AD_BNC",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AD_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x95",
+        "EventName": "UNC_H_TxR_HORZ_INSERTS.AD_CRD",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AK_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x95",
+        "EventName": "UNC_H_TxR_HORZ_INSERTS.AK_BNC",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.BL_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x95",
+        "EventName": "UNC_H_TxR_HORZ_INSERTS.BL_BNC",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.BL_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x95",
+        "EventName": "UNC_H_TxR_HORZ_INSERTS.BL_CRD",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.IV_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x95",
+        "EventName": "UNC_H_TxR_HORZ_INSERTS.IV_BNC",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AD_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x99",
+        "EventName": "UNC_H_TxR_HORZ_NACK.AD_BNC",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AD_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x99",
+        "EventName": "UNC_H_TxR_HORZ_NACK.AD_CRD",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AK_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x99",
+        "EventName": "UNC_H_TxR_HORZ_NACK.AK_BNC",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.BL_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x99",
+        "EventName": "UNC_H_TxR_HORZ_NACK.BL_BNC",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.BL_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x99",
+        "EventName": "UNC_H_TxR_HORZ_NACK.BL_CRD",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.IV_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x99",
+        "EventName": "UNC_H_TxR_HORZ_NACK.IV_BNC",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x94",
+        "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AD_BNC",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x94",
+        "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AD_CRD",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x94",
+        "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AK_BNC",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x94",
+        "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.BL_BNC",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD",
+        "Deprecated": "1",
+        "EventCode": "0x94",
+        "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.BL_CRD",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x94",
+        "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.IV_BNC",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.AD_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x9B",
+        "EventName": "UNC_H_TxR_HORZ_STARVED.AD_BNC",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.AK_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x9B",
+        "EventName": "UNC_H_TxR_HORZ_STARVED.AK_BNC",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.BL_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x9B",
+        "EventName": "UNC_H_TxR_HORZ_STARVED.BL_BNC",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.IV_BNC",
+        "Deprecated": "1",
+        "EventCode": "0x9B",
+        "EventName": "UNC_H_TxR_HORZ_STARVED.IV_BNC",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AD_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_H_TxR_VERT_ADS_USED.AD_AG0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AD_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_H_TxR_VERT_ADS_USED.AD_AG1",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AK_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_H_TxR_VERT_ADS_USED.AK_AG0",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AK_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_H_TxR_VERT_ADS_USED.AK_AG1",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.BL_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_H_TxR_VERT_ADS_USED.BL_AG0",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.BL_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_H_TxR_VERT_ADS_USED.BL_AG1",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AD_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_H_TxR_VERT_BYPASS.AD_AG0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AD_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_H_TxR_VERT_BYPASS.AD_AG1",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AK_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_H_TxR_VERT_BYPASS.AK_AG0",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AK_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_H_TxR_VERT_BYPASS.AK_AG1",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.BL_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_H_TxR_VERT_BYPASS.BL_AG0",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.BL_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_H_TxR_VERT_BYPASS.BL_AG1",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.IV",
+        "Deprecated": "1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_H_TxR_VERT_BYPASS.IV_AG1",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x92",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AD_AG0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x92",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AD_AG1",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x92",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AK_AG0",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x92",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AK_AG1",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x92",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.BL_AG0",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x92",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.BL_AG1",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.IV",
+        "Deprecated": "1",
+        "EventCode": "0x92",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.IV_AG0",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x93",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AD_AG0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x93",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AD_AG1",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x93",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AK_AG0",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x93",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AK_AG1",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x93",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_NE.BL_AG0",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x93",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_NE.BL_AG1",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.IV",
+        "Deprecated": "1",
+        "EventCode": "0x93",
+        "EventName": "UNC_H_TxR_VERT_CYCLES_NE.IV_AG0",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AD_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x91",
+        "EventName": "UNC_H_TxR_VERT_INSERTS.AD_AG0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AD_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x91",
+        "EventName": "UNC_H_TxR_VERT_INSERTS.AD_AG1",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AK_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x91",
+        "EventName": "UNC_H_TxR_VERT_INSERTS.AK_AG0",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AK_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x91",
+        "EventName": "UNC_H_TxR_VERT_INSERTS.AK_AG1",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.BL_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x91",
+        "EventName": "UNC_H_TxR_VERT_INSERTS.BL_AG0",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.BL_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x91",
+        "EventName": "UNC_H_TxR_VERT_INSERTS.BL_AG1",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.IV",
+        "Deprecated": "1",
+        "EventCode": "0x91",
+        "EventName": "UNC_H_TxR_VERT_INSERTS.IV_AG0",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AD_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x98",
+        "EventName": "UNC_H_TxR_VERT_NACK.AD_AG0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AD_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x98",
+        "EventName": "UNC_H_TxR_VERT_NACK.AD_AG1",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AK_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x98",
+        "EventName": "UNC_H_TxR_VERT_NACK.AK_AG0",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AK_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x98",
+        "EventName": "UNC_H_TxR_VERT_NACK.AK_AG1",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.BL_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x98",
+        "EventName": "UNC_H_TxR_VERT_NACK.BL_AG0",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.BL_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x98",
+        "EventName": "UNC_H_TxR_VERT_NACK.BL_AG1",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.IV",
+        "Deprecated": "1",
+        "EventCode": "0x98",
+        "EventName": "UNC_H_TxR_VERT_NACK.IV",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x90",
+        "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AD_AG0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x90",
+        "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AD_AG1",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x90",
+        "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AK_AG0",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x90",
+        "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AK_AG1",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x90",
+        "EventName": "UNC_H_TxR_VERT_OCCUPANCY.BL_AG0",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x90",
+        "EventName": "UNC_H_TxR_VERT_OCCUPANCY.BL_AG1",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.IV",
+        "Deprecated": "1",
+        "EventCode": "0x90",
+        "EventName": "UNC_H_TxR_VERT_OCCUPANCY.IV_AG0",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AD_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_H_TxR_VERT_STARVED.AD_AG0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AD_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_H_TxR_VERT_STARVED.AD_AG1",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AK_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_H_TxR_VERT_STARVED.AK_AG0",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AK_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_H_TxR_VERT_STARVED.AK_AG1",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.BL_AG0",
+        "Deprecated": "1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_H_TxR_VERT_STARVED.BL_AG0",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.BL_AG1",
+        "Deprecated": "1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_H_TxR_VERT_STARVED.BL_AG1",
+        "PerPkg": "1",
+        "UMask": "0x40",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.IV",
+        "Deprecated": "1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_H_TxR_VERT_STARVED.IV",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN",
+        "Deprecated": "1",
+        "EventCode": "0xA6",
+        "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_EVEN",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD",
+        "Deprecated": "1",
+        "EventCode": "0xA6",
+        "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_ODD",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN",
+        "Deprecated": "1",
+        "EventCode": "0xA6",
+        "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_EVEN",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD",
+        "Deprecated": "1",
+        "EventCode": "0xA6",
+        "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_ODD",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN",
+        "Deprecated": "1",
+        "EventCode": "0xA8",
+        "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_EVEN",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD",
+        "Deprecated": "1",
+        "EventCode": "0xA8",
+        "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_ODD",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN",
+        "Deprecated": "1",
+        "EventCode": "0xA8",
+        "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_EVEN",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD",
+        "Deprecated": "1",
+        "EventCode": "0xA8",
+        "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_ODD",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN",
+        "Deprecated": "1",
+        "EventCode": "0xAA",
+        "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_EVEN",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD",
+        "Deprecated": "1",
+        "EventCode": "0xAA",
+        "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_ODD",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN",
+        "Deprecated": "1",
+        "EventCode": "0xAA",
+        "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_EVEN",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD",
+        "Deprecated": "1",
+        "EventCode": "0xAA",
+        "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_ODD",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_IV_IN_USE.DN",
+        "Deprecated": "1",
+        "EventCode": "0xAC",
+        "EventName": "UNC_H_VERT_RING_IV_IN_USE.DN",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_IV_IN_USE.UP",
+        "Deprecated": "1",
+        "EventCode": "0xAC",
+        "EventName": "UNC_H_VERT_RING_IV_IN_USE.UP",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WB_PUSH_MTOI.LLC",
+        "Deprecated": "1",
+        "EventCode": "0x56",
+        "EventName": "UNC_H_WB_PUSH_MTOI.LLC",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WB_PUSH_MTOI.MEM",
+        "Deprecated": "1",
+        "EventCode": "0x56",
+        "EventName": "UNC_H_WB_PUSH_MTOI.MEM",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2",
+        "Deprecated": "1",
+        "EventCode": "0x5A",
+        "EventName": "UNC_H_WRITE_NO_CREDITS.EDC0_SMI2",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3",
+        "Deprecated": "1",
+        "EventCode": "0x5A",
+        "EventName": "UNC_H_WRITE_NO_CREDITS.EDC1_SMI3",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4",
+        "Deprecated": "1",
+        "EventCode": "0x5A",
+        "EventName": "UNC_H_WRITE_NO_CREDITS.EDC2_SMI4",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5",
+        "Deprecated": "1",
+        "EventCode": "0x5A",
+        "EventName": "UNC_H_WRITE_NO_CREDITS.EDC3_SMI5",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0",
+        "Deprecated": "1",
+        "EventCode": "0x5A",
+        "EventName": "UNC_H_WRITE_NO_CREDITS.MC0_SMI0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1",
+        "Deprecated": "1",
+        "EventCode": "0x5A",
+        "EventName": "UNC_H_WRITE_NO_CREDITS.MC1_SMI1",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.ANY_RSPI_FWDFE",
+        "PerPkg": "1",
+        "UMask": "0xe4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.ANY_RSPI_FWDM",
+        "PerPkg": "1",
+        "UMask": "0xf0",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.ANY_RSPS_FWDFE",
+        "PerPkg": "1",
+        "UMask": "0xe2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.ANY_RSPS_FWDM",
+        "PerPkg": "1",
+        "UMask": "0xe8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.ANY_RSP_HITFSE",
+        "PerPkg": "1",
+        "UMask": "0xe1",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.CORE_RSPI_FWDFE",
+        "PerPkg": "1",
+        "UMask": "0x44",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.CORE_RSPI_FWDM",
+        "PerPkg": "1",
+        "UMask": "0x50",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.CORE_RSPS_FWDFE",
+        "PerPkg": "1",
+        "UMask": "0x42",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.CORE_RSPS_FWDM",
+        "PerPkg": "1",
+        "UMask": "0x48",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.CORE_RSP_HITFSE",
+        "PerPkg": "1",
+        "UMask": "0x41",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.EVICT_RSPI_FWDFE",
+        "PerPkg": "1",
+        "UMask": "0x84",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.EVICT_RSPI_FWDM",
+        "PerPkg": "1",
+        "UMask": "0x90",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.EVICT_RSPS_FWDFE",
+        "PerPkg": "1",
+        "UMask": "0x82",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.EVICT_RSPS_FWDM",
+        "PerPkg": "1",
+        "UMask": "0x88",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.EVICT_RSP_HITFSE",
+        "PerPkg": "1",
+        "UMask": "0x81",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.EXT_RSPI_FWDFE",
+        "PerPkg": "1",
+        "UMask": "0x24",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.EXT_RSPI_FWDM",
+        "PerPkg": "1",
+        "UMask": "0x30",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.EXT_RSPS_FWDFE",
+        "PerPkg": "1",
+        "UMask": "0x22",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.EXT_RSPS_FWDM",
+        "PerPkg": "1",
+        "UMask": "0x28",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE",
+        "Deprecated": "1",
+        "EventCode": "0x32",
+        "EventName": "UNC_H_XSNP_RESP.EXT_RSP_HITFSE",
+        "PerPkg": "1",
+        "UMask": "0x21",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "Clockticks of the IIO Traffic Controller",
+        "EventCode": "0x1",
+        "EventName": "UNC_IIO_CLOCKTICKS",
+        "PerPkg": "1",
+        "PublicDescription": "Counts clockticks of the 1GHz trafiic controller clock in the IIO unit.",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",
+        "FCMask": "0x4",
+        "PerPkg": "1",
+        "PortMask": "0x0f",
+        "UMask": "0x3",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
+        "FCMask": "0x4",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "UMask": "0x3",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
+        "FCMask": "0x4",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "UMask": "0x3",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
+        "FCMask": "0x4",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "UMask": "0x3",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
+        "FCMask": "0x4",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "UMask": "0x3",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "PCIe Completion Buffer Inserts; Port 0",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT0",
+        "FCMask": "0x7",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "PCIe Completion Buffer Inserts; Port 1",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT1",
+        "FCMask": "0x7",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "PCIe Completion Buffer Inserts; Port 2",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT2",
+        "FCMask": "0x7",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "PCIe Completion Buffer Inserts; Port 3",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT3",
+        "FCMask": "0x7",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3",
+        "EventCode": "0xD5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
+        "FCMask": "0x04",
+        "PerPkg": "1",
+        "UMask": "0xf",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0",
+        "EventCode": "0xD5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
+        "FCMask": "0x04",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1",
+        "EventCode": "0xD5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
+        "FCMask": "0x04",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2",
+        "EventCode": "0xD5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
+        "FCMask": "0x04",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3",
+        "EventCode": "0xD5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
+        "FCMask": "0x04",
+        "PerPkg": "1",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x40",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1",
+        "UMask": "0x40",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x40",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3",
+        "UMask": "0x40",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+        "UMask": "0x40",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+        "UMask": "0x40",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x10",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1",
+        "UMask": "0x10",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x10",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3",
+        "UMask": "0x10",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+        "UMask": "0x10",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+        "UMask": "0x10",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x80",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1",
+        "UMask": "0x80",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x80",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3",
+        "UMask": "0x80",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+        "UMask": "0x80",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+        "UMask": "0x80",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x20",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1",
+        "UMask": "0x20",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x20",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3",
+        "UMask": "0x20",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+        "UMask": "0x20",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+        "UMask": "0x20",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part2",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part3",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by  a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by  a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit.  In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x10",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1",
+        "UMask": "0x10",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x10",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3",
+        "UMask": "0x10",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+        "UMask": "0x10",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+        "UMask": "0x10",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x20",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1",
+        "UMask": "0x20",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x20",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3",
+        "UMask": "0x20",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "PCI Express bandwidth reading at IIO, part 0",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "PCI Express bandwidth reading at IIO, part 1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "PCI Express bandwidth reading at IIO, part 2",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "PCI Express bandwidth reading at IIO, part 3",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU; Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU; Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "PCI Express bandwidth writing at IIO, part 0",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "PCI Express bandwidth writing at IIO, part 1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "PCI Express bandwidth writing at IIO, part 2",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "PCI Express bandwidth writing at IIO, part 3",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU; Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU; Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU; Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x40",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU; Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1",
+        "UMask": "0x40",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU; Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x40",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU; Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3",
+        "UMask": "0x40",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU; Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+        "UMask": "0x40",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU; Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+        "UMask": "0x40",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PortMask": "0x10",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x93",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.IV",
+        "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "PortMask": "0x20",
+        "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x91",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS.IV",
+        "BriefDescription": "Num Link  Correctable Errors",
+        "EventCode": "0xF",
+        "EventName": "UNC_IIO_LINK_NUM_CORR_ERR",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.IV",
+        "BriefDescription": "Num Link Retries",
+        "EventCode": "0xE",
+        "EventName": "UNC_IIO_LINK_NUM_RETRIES",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "FaST wire asserted; Vertical",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA5",
-        "EventName": "UNC_CHA_FAST_ASSERTED.VERT",
+        "BriefDescription": "Number packets that passed the Mask/Match Filter",
+        "EventCode": "0x21",
+        "EventName": "UNC_IIO_MASK_MATCH",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL",
+        "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus",
+        "EventCode": "0x2",
+        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "PublicDescription": "Asserted if all bits specified by mask match",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Lines Victimized; Local - Lines in M State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M",
+        "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and PCIE bus",
+        "EventCode": "0x2",
+        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1",
         "PerPkg": "1",
-        "UMask": "0x21",
-        "Unit": "CHA"
+        "PublicDescription": "Asserted if all bits specified by mask match",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Lines Victimized; Local - Lines in E State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E",
+        "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)",
+        "EventCode": "0x2",
+        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1",
         "PerPkg": "1",
-        "UMask": "0x22",
-        "Unit": "CHA"
+        "PublicDescription": "Asserted if all bits specified by mask match",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Lines Victimized; Local - Lines in S State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S",
+        "BriefDescription": "AND Mask/match for debug bus; PCIE bus",
+        "EventCode": "0x2",
+        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1",
         "PerPkg": "1",
-        "UMask": "0x24",
-        "Unit": "CHA"
+        "PublicDescription": "Asserted if all bits specified by mask match",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Lines Victimized; Local - Lines in F State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_F",
+        "BriefDescription": "AND Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus",
+        "EventCode": "0x2",
+        "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1",
         "PerPkg": "1",
-        "UMask": "0x28",
-        "Unit": "CHA"
+        "PublicDescription": "Asserted if all bits specified by mask match",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Lines Victimized; Remote - Lines in M State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M",
+        "BriefDescription": "AND Mask/match for debug bus",
+        "EventCode": "0x2",
+        "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1",
         "PerPkg": "1",
-        "UMask": "0x81",
-        "Unit": "CHA"
+        "PublicDescription": "Asserted if all bits specified by mask match",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Lines Victimized; Remote - Lines in E State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E",
+        "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus",
+        "EventCode": "0x3",
+        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0",
         "PerPkg": "1",
-        "UMask": "0x82",
-        "Unit": "CHA"
+        "PublicDescription": "Asserted if any bits specified by mask match",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Lines Victimized; Remote - Lines in S State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S",
+        "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and PCIE bus",
+        "EventCode": "0x3",
+        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1",
         "PerPkg": "1",
-        "UMask": "0x84",
-        "Unit": "CHA"
+        "PublicDescription": "Asserted if any bits specified by mask match",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Lines Victimized; Remote - Lines in F State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_F",
+        "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)",
+        "EventCode": "0x3",
+        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1",
         "PerPkg": "1",
-        "UMask": "0x88",
-        "Unit": "CHA"
+        "PublicDescription": "Asserted if any bits specified by mask match",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Lines Victimized; Remote - All Lines",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
+        "BriefDescription": "OR Mask/match for debug bus; PCIE bus",
+        "EventCode": "0x3",
+        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1",
         "PerPkg": "1",
-        "UMask": "0x8F",
-        "Unit": "CHA"
+        "PublicDescription": "Asserted if any bits specified by mask match",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy; All from Local",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC",
+        "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus",
+        "EventCode": "0x3",
+        "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1",
         "PerPkg": "1",
-        "UMask": "0x37",
-        "Unit": "CHA"
+        "PublicDescription": "Asserted if any bits specified by mask match",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; RdCur misses from Local IO",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RDCUR",
-        "Filter": "config1=0x43C33",
+        "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and !(PCIE bus)",
+        "EventCode": "0x3",
+        "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1",
         "PerPkg": "1",
-        "UMask": "0x24",
-        "Unit": "CHA"
+        "PublicDescription": "Asserted if any bits specified by mask match",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; RFO misses from Local IO",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
-        "Filter": "config1=0x40033",
+        "BriefDescription": "UNC_IIO_NOTHING",
+        "EventName": "UNC_IIO_NOTHING",
         "PerPkg": "1",
-        "UMask": "0x24",
-        "Unit": "CHA"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts; ItoM misses from Local IO",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
-        "Filter": "config1=0x49033",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART0",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x24",
-        "Unit": "CHA"
+        "PortMask": "0x1",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy;  ITOM Misses from Local IO",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
-        "Filter": "config1=0x49033",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART1",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x24",
-        "Unit": "CHA"
+        "PortMask": "0x2",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy;  RDCUR misses from Local IO",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RDCUR",
-        "Filter": "config1=0x43C33",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART2",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x24",
-        "Unit": "CHA"
+        "PortMask": "0x4",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy;  RFO misses from Local IO",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
-        "Filter": "config1=0x40033",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART3",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x24",
-        "Unit": "CHA"
+        "PortMask": "0x8",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts; Port 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x04",
+        "PortMask": "0x10",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts; Port 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x04",
+        "PortMask": "0x20",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts; Port 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT2",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x04",
+        "PortMask": "0x1",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts; Port 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x04",
+        "PortMask": "0x2",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Num Link  Correctable Errors",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xF",
-        "EventName": "UNC_IIO_LINK_NUM_CORR_ERR",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART2",
+        "FCMask": "0x7",
         "PerPkg": "1",
+        "PortMask": "0x4",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Num Link Retries",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xE",
-        "EventName": "UNC_IIO_LINK_NUM_RETRIES",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART3",
+        "FCMask": "0x7",
         "PerPkg": "1",
+        "PortMask": "0x8",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number packets that passed the Mask/Match Filter",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_IIO_MASK_MATCH",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART0",
+        "FCMask": "0x7",
         "PerPkg": "1",
+        "PortMask": "0x1",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART1",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PortMask": "0x2",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "AND Mask/match for debug bus; PCIE bus",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PortMask": "0x4",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3",
+        "FCMask": "0x7",
         "PerPkg": "1",
+        "PortMask": "0x8",
         "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and PCIE bus",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD0",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PortMask": "0x10",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "AND Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD1",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PortMask": "0x20",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "AND Mask/match for debug bus",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PortMask": "0x1",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1",
+        "FCMask": "0x7",
         "PerPkg": "1",
+        "PortMask": "0x2",
         "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "OR Mask/match for debug bus; PCIE bus",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PortMask": "0x4",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PortMask": "0x8",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and PCIE bus",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD0",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PortMask": "0x10",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD1",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PortMask": "0x20",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and !(PCIE bus)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART0",
+        "FCMask": "0x7",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PortMask": "0x1",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "UNC_IIO_NOTHING",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_IIO_NOTHING",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
+        "Deprecated": "1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART1",
+        "FCMask": "0x7",
         "PerPkg": "1",
+        "PortMask": "0x2",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x2",
+        "PortMask": "0x4",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART1",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x2",
+        "PortMask": "0x8",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART2",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x2",
+        "PortMask": "0x10",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART3",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x2",
+        "PortMask": "0x20",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
-        "Counter": "0,1",
         "Deprecated": "1",
         "EventCode": "0x83",
         "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART0",
@@ -8254,7 +12235,6 @@
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
-        "Counter": "0,1",
         "Deprecated": "1",
         "EventCode": "0x83",
         "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART1",
@@ -8266,7 +12246,6 @@
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
-        "Counter": "0,1",
         "Deprecated": "1",
         "EventCode": "0x83",
         "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART2",
@@ -8278,7 +12257,6 @@
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
-        "Counter": "0,1",
         "Deprecated": "1",
         "EventCode": "0x83",
         "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART3",
@@ -8289,784 +12267,697 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
-        "Counter": "0,1",
-        "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART0",
-        "FCMask": "0x7",
-        "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x10",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
-        "Counter": "0,1",
-        "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART1",
-        "FCMask": "0x7",
-        "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x10",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART2",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x10",
+        "PortMask": "0x10",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART3",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x10",
+        "PortMask": "0x20",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x1",
-        "UMask": "0x20",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART1",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x2",
-        "UMask": "0x20",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART2",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x4",
-        "UMask": "0x20",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART3",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x8",
-        "UMask": "0x20",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x40",
+        "PortMask": "0x10",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1",
         "Deprecated": "1",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART1",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x40",
+        "PortMask": "0x20",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART2",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
+        "PortMask": "0x1",
         "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART3",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
+        "PortMask": "0x2",
         "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x1",
+        "PortMask": "0x4",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART1",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x1",
+        "PortMask": "0x8",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART2",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x1",
+        "PortMask": "0x10",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART3",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x1",
+        "PortMask": "0x20",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x1",
-        "UMask": "0x2",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART1",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x2",
-        "UMask": "0x2",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART2",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x4",
-        "UMask": "0x2",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART3",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x8",
-        "UMask": "0x2",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x4",
+        "PortMask": "0x10",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART1",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x4",
+        "PortMask": "0x20",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART2",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x4",
+        "PortMask": "0x1",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART3",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x4",
+        "PortMask": "0x2",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x8",
+        "PortMask": "0x4",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART1",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x8",
+        "PortMask": "0x8",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART2",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x8",
+        "PortMask": "0x10",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART3",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x8",
+        "PortMask": "0x20",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x1",
-        "UMask": "0x10",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART1",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x2",
-        "UMask": "0x10",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART2",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x4",
-        "UMask": "0x10",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART3",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x8",
-        "UMask": "0x10",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
+        "PortMask": "0x10",
         "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART1",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
+        "PortMask": "0x20",
         "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART2",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x20",
+        "PortMask": "0x1",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART3",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x20",
+        "PortMask": "0x2",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x40",
+        "PortMask": "0x4",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART1",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x40",
+        "PortMask": "0x8",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART2",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x40",
+        "PortMask": "0x10",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART3",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x40",
+        "PortMask": "0x20",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x1",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART1",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x2",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART2",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x4",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
         "Deprecated": "1",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART3",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x8",
-        "UMask": "0x80",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Symbol Times on Link",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_IIO_SYMBOL_TIMES",
-        "PerPkg": "1",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART0",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
+        "PortMask": "0x10",
         "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART1",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
+        "PortMask": "0x20",
         "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART2",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x1",
+        "PortMask": "0x1",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART3",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x1",
+        "PortMask": "0x2",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART0",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x2",
+        "PortMask": "0x4",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART1",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x2",
+        "PortMask": "0x8",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART2",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x2",
+        "PortMask": "0x10",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART3",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x2",
+        "PortMask": "0x20",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART0",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x1",
-        "UMask": "0x4",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART1",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x2",
-        "UMask": "0x4",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART2",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x4",
-        "UMask": "0x4",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART3",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x8",
-        "UMask": "0x4",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART0",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x8",
+        "PortMask": "0x10",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART1",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x8",
+        "PortMask": "0x20",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Symbol Times on Link",
+        "EventCode": "0x82",
+        "EventName": "UNC_IIO_SYMBOL_TIMES",
+        "PerPkg": "1",
+        "PublicDescription": "Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
         "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART2",
+        "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x8",
+        "PortMask": "0x1",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
         "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART3",
+        "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x8",
+        "PortMask": "0x2",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
         "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART0",
+        "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
+        "PortMask": "0x4",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
         "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART1",
+        "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
+        "PortMask": "0x8",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
         "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART2",
+        "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
+        "PortMask": "0x10",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
         "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART3",
+        "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
+        "PortMask": "0x20",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
         "EventCode": "0x84",
         "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART0",
@@ -9077,8 +12968,7 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
         "EventCode": "0x84",
         "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART1",
@@ -9089,8 +12979,7 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
         "EventCode": "0x84",
         "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART2",
@@ -9101,8 +12990,7 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
         "EventCode": "0x84",
         "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART3",
@@ -9113,59 +13001,76 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
         "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MSG.PART0",
+        "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x1",
-        "UMask": "0x40",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
         "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MSG.PART1",
+        "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x2",
-        "UMask": "0x40",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
         "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MSG.PART2",
+        "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x4",
-        "UMask": "0x40",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
         "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MSG.PART3",
+        "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x8",
-        "UMask": "0x40",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART0",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD0",
+        "FCMask": "0x7",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD1",
+        "FCMask": "0x7",
+        "PerPkg": "1",
+        "PortMask": "0x20",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
+        "Deprecated": "1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x1",
@@ -9173,11 +13078,10 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x2",
@@ -9185,11 +13089,10 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART2",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x4",
@@ -9197,11 +13100,10 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART3",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x8",
@@ -9209,107 +13111,98 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART0",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x2",
+        "PortMask": "0x10",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x2",
+        "PortMask": "0x20",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART2",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MSG.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x2",
+        "PortMask": "0x1",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART3",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MSG.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x2",
+        "PortMask": "0x2",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART0",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MSG.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x4",
+        "PortMask": "0x4",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MSG.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x4",
+        "PortMask": "0x8",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART2",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MSG.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x4",
+        "PortMask": "0x10",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART3",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.MSG.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x4",
+        "PortMask": "0x20",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART0",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x1",
@@ -9317,11 +13210,10 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x2",
@@ -9329,11 +13221,10 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART2",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x4",
@@ -9341,11 +13232,10 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART3",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x8",
@@ -9353,104 +13243,95 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART0",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x10",
+        "PortMask": "0x10",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x10",
+        "PortMask": "0x20",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART2",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x10",
+        "PortMask": "0x1",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART3",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x10",
+        "PortMask": "0x2",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART0",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x20",
+        "PortMask": "0x4",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART1",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x20",
+        "PortMask": "0x8",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART2",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x20",
+        "PortMask": "0x10",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART3",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x20",
+        "PortMask": "0x20",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
-        "Counter": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xC1",
         "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART0",
@@ -9462,7 +13343,6 @@
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
-        "Counter": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xC1",
         "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART1",
@@ -9474,7 +13354,6 @@
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
-        "Counter": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xC1",
         "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART2",
@@ -9486,7 +13365,6 @@
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
-        "Counter": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xC1",
         "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART3",
@@ -9497,379 +13375,263 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART0",
-        "FCMask": "0x7",
-        "PerPkg": "1",
-        "PortMask": "0x1",
-        "UMask": "0x80",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0",
         "Deprecated": "1",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART1",
+        "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x2",
-        "UMask": "0x80",
+        "PortMask": "0x10",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1",
         "Deprecated": "1",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART2",
+        "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x4",
-        "UMask": "0x80",
+        "PortMask": "0x20",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
         "Deprecated": "1",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART3",
+        "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x8",
-        "UMask": "0x80",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "VTd Access; Vtd hit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_VTD_ACCESS.L4_PAGE_HIT",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "VTd Access; context cache miss",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_VTD_ACCESS.CTXT_MISS",
-        "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "VTd Access; L1 miss",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_VTD_ACCESS.L1_MISS",
-        "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "VTd Access; L2 miss",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_VTD_ACCESS.L2_MISS",
-        "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "VTd Access; L3 miss",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_VTD_ACCESS.L3_MISS",
-        "PerPkg": "1",
+        "PortMask": "0x1",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "VTd Access; TLB miss",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_VTD_ACCESS.TLB_MISS",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "VTd Access; TLB is full",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_VTD_ACCESS.TLB_FULL",
-        "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "VTd Access; TLB miss",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_VTD_ACCESS.TLB1_MISS",
-        "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "VTd Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x40",
-        "EventName": "UNC_IIO_VTD_OCCUPANCY",
-        "PerPkg": "1",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
+        "PortMask": "0x2",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
+        "PortMask": "0x4",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x4",
+        "PortMask": "0x8",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x4",
+        "PortMask": "0x10",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x1",
+        "PortMask": "0x1",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x1",
+        "PortMask": "0x2",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x40",
+        "PortMask": "0x4",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x40",
+        "PortMask": "0x8",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x8",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x8",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x2",
+        "PortMask": "0x1",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1",
-        "Counter": "0,1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
         "Deprecated": "1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x2",
+        "PortMask": "0x2",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x40",
+        "PortMask": "0x4",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x40",
+        "PortMask": "0x8",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x10",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x10",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x80",
+        "PortMask": "0x1",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x80",
+        "PortMask": "0x2",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x20",
+        "PortMask": "0x4",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x20",
+        "PortMask": "0x8",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x10",
@@ -9877,11 +13639,10 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x20",
@@ -9889,203 +13650,186 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
+        "PortMask": "0x1",
         "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
+        "PortMask": "0x2",
         "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x8",
+        "PortMask": "0x4",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x8",
+        "PortMask": "0x8",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x2",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1",
-        "Counter": "2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1",
         "Deprecated": "1",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x2",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
+        "Deprecated": "1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x10",
+        "PortMask": "0x1",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x10",
+        "PortMask": "0x2",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x4",
+        "PortMask": "0x4",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x4",
+        "PortMask": "0x8",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x1",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x1",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MSG.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART0",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x40",
+        "PortMask": "0x1",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.MSG.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART1",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x40",
+        "PortMask": "0x2",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART2",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x8",
+        "PortMask": "0x4",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART3",
         "FCMask": "0x7",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x8",
+        "PortMask": "0x8",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD0",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x10",
@@ -10093,11 +13837,10 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1",
         "Deprecated": "1",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD1",
         "FCMask": "0x7",
         "PerPkg": "1",
         "PortMask": "0x20",
@@ -10105,12643 +13848,12288 @@
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD0",
-        "FCMask": "0x7",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x10",
+        "PortMask": "0x01",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
         "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD1",
-        "FCMask": "0x7",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x20",
+        "PortMask": "0x02",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1",
         "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.VTD0",
-        "FCMask": "0x7",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x10",
+        "PortMask": "0x04",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD0",
-        "FCMask": "0x7",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3",
+        "UMask": "0x40",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0",
+        "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x80",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD1",
-        "FCMask": "0x7",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1",
+        "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x80",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD0",
-        "FCMask": "0x7",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x20",
+        "PortMask": "0x01",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD1",
-        "FCMask": "0x7",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x20",
+        "PortMask": "0x02",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD0",
-        "FCMask": "0x7",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x4",
+        "PortMask": "0x04",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD1",
-        "FCMask": "0x7",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x4",
+        "PortMask": "0x08",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD0",
-        "FCMask": "0x7",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0",
+        "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x1",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD1",
-        "FCMask": "0x7",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD1",
+        "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x1",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD0",
-        "FCMask": "0x7",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x8",
+        "PortMask": "0x01",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD1",
-        "FCMask": "0x7",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x8",
+        "PortMask": "0x02",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1",
+        "UMask": "0x80",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x80",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD0",
-        "FCMask": "0x7",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0",
+        "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x2",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD1",
-        "FCMask": "0x7",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1",
+        "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x2",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x01",
-        "UMask": "0x10",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x02",
-        "UMask": "0x10",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x04",
-        "UMask": "0x10",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x08",
-        "UMask": "0x10",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x01",
+        "PortMask": "0x10",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
         "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x02",
+        "PortMask": "0x20",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
         "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
+        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x20",
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
+        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x20",
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
+        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x40",
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
+        "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x40",
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x40",
+        "PortMask": "0x10",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
+        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x40",
+        "PortMask": "0x20",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
+        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x01",
-        "UMask": "0x80",
+        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
+        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x02",
-        "UMask": "0x80",
+        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
+        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x04",
-        "UMask": "0x80",
+        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
+        "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x08",
-        "UMask": "0x80",
+        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0",
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x40",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1",
+        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x40",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0",
+        "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x10",
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1",
+        "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x10",
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0",
+        "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x80",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1",
+        "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x80",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0",
+        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x20",
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1",
+        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x20",
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0",
+        "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x04",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1",
+        "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x04",
+        "PublicDescription": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0",
+        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x01",
+        "PortMask": "0x01",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1",
+        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x01",
+        "PortMask": "0x02",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0",
+        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x08",
+        "PortMask": "0x04",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1",
+        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x08",
+        "PortMask": "0x08",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0",
+        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x02",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1",
+        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x02",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
+        "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x01",
-        "UMask": "0x10",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
+        "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x02",
-        "UMask": "0x10",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
+        "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x04",
-        "UMask": "0x10",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
+        "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x08",
-        "UMask": "0x10",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0",
+        "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x01",
-        "UMask": "0x20",
+        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1",
+        "BriefDescription": "Read request for up to a 64 byte transaction is  made by IIO Part1 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x02",
-        "UMask": "0x20",
+        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2",
+        "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x04",
-        "UMask": "0x20",
+        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3",
+        "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x08",
-        "UMask": "0x20",
+        "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Messages",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
+        "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x40",
+        "PortMask": "0x10",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Messages",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
+        "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x40",
+        "PortMask": "0x20",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Messages",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
+        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x40",
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Messages",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
+        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x40",
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0",
+        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x10",
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1",
+        "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x10",
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Card reading from DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0",
+        "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x04",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Card reading from DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1",
+        "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x04",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Card writing to DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0",
+        "BriefDescription": "Number Transactions requested of the CPU; Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x01",
+        "PortMask": "0x01",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Card writing to DRAM",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1",
+        "BriefDescription": "Number Transactions requested of the CPU; Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x01",
+        "PortMask": "0x02",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Messages",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0",
+        "BriefDescription": "Number Transactions requested of the CPU; Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x10",
+        "PortMask": "0x04",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
         "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Messages",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1",
+        "BriefDescription": "Number Transactions requested of the CPU; Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x20",
+        "PortMask": "0x08",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3",
         "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0",
+        "BriefDescription": "Number Transactions requested of the CPU; Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x08",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1",
+        "BriefDescription": "Number Transactions requested of the CPU; Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x08",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0",
+        "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x02",
+        "PortMask": "0x01",
+        "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1",
+        "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x02",
+        "PortMask": "0x02",
+        "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
+        "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x10",
+        "PortMask": "0x04",
+        "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
+        "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x10",
+        "PortMask": "0x08",
+        "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
+        "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x10",
+        "PortMask": "0x10",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
+        "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x10",
+        "PortMask": "0x20",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
+        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x01",
-        "UMask": "0x20",
+        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
+        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x02",
-        "UMask": "0x20",
+        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part1 to the MMIO space of an IIO target.In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
+        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x04",
-        "UMask": "0x20",
+        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
+        "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x08",
-        "UMask": "0x20",
+        "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
+        "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x40",
+        "PortMask": "0x10",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
+        "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x40",
+        "PortMask": "0x20",
+        "PublicDescription": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "VTd Access; context cache miss",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_VTD_ACCESS.CTXT_MISS",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x40",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "VTd Access; L1 miss",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_VTD_ACCESS.L1_MISS",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x40",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "VTd Access; L2 miss",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_VTD_ACCESS.L2_MISS",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x80",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "VTd Access; L3 miss",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_VTD_ACCESS.L3_MISS",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x80",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "VTd Access; Vtd hit",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_VTD_ACCESS.L4_PAGE_HIT",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "VTd Access; TLB miss",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_VTD_ACCESS.TLB1_MISS",
         "PerPkg": "1",
-        "PortMask": "0x08",
         "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "VTd Access; TLB is full",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_VTD_ACCESS.TLB_FULL",
         "PerPkg": "1",
-        "PortMask": "0x10",
         "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "VTd Access; TLB miss",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_VTD_ACCESS.TLB_MISS",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x40",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "VTd Occupancy",
+        "EventCode": "0x40",
+        "EventName": "UNC_IIO_VTD_OCCUPANCY",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "Total Write Cache Occupancy; Any Source",
+        "EventCode": "0xF",
+        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.",
+        "UMask": "0x1",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "Total Write Cache Occupancy; Snoops",
+        "EventCode": "0xF",
+        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.",
+        "UMask": "0x2",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "Total IRP occupancy of inbound read and write requests.",
+        "EventCode": "0xF",
+        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Total IRP occupancy of inbound read and write requests.  This is effectively the sum of read occupancy and write occupancy.",
+        "UMask": "0x4",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "IRP Clocks",
+        "EventCode": "0x1",
+        "EventName": "UNC_I_CLOCKTICKS",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "Coherent Ops; CLFlush",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+        "UMask": "0x80",
+        "Unit": "IRP"
+    },
+    {
+        "BriefDescription": "Coherent Ops; CRd",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.CRD",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+        "UMask": "0x2",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "Coherent Ops; DRd",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.DRD",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+        "UMask": "0x4",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "Coherent Ops; PCIDCAHin5t",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+        "UMask": "0x20",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "Coherent Ops; PCIRdCur",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+        "UMask": "0x1",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.PCITOM",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO.  PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.",
+        "UMask": "0x10",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.RFO",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory.  RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.",
+        "UMask": "0x8",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "Coherent Ops; WbMtoI",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+        "UMask": "0x40",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "FAF RF full",
+        "EventCode": "0x17",
+        "EventName": "UNC_I_FAF_FULL",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.",
+        "EventCode": "0x18",
+        "EventName": "UNC_I_FAF_INSERTS",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "Occupancy of the IRP FAF queue.",
+        "EventCode": "0x19",
+        "EventName": "UNC_I_FAF_OCCUPANCY",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "FAF allocation -- sent to ADQ",
+        "EventCode": "0x16",
+        "EventName": "UNC_I_FAF_TRANSACTIONS",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "All Inserts Inbound (p2p + faf + cset)",
+        "EventCode": "0x1E",
+        "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "All Inserts Outbound (BL, AK, Snoops)",
+        "EventCode": "0x1E",
+        "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
+        "EventCode": "0x1C",
+        "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "UMask": "0x10",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
+        "EventCode": "0x1C",
+        "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "UMask": "0x4",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
+        "EventCode": "0x1C",
+        "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "UMask": "0x8",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
+        "EventCode": "0x1C",
+        "EventName": "UNC_I_MISC0.FAST_REJ",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
+        "EventCode": "0x1C",
+        "EventName": "UNC_I_MISC0.FAST_REQ",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
+        "EventCode": "0x1C",
+        "EventName": "UNC_I_MISC0.FAST_XFER",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "UMask": "0x20",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
+        "EventCode": "0x1C",
+        "EventName": "UNC_I_MISC0.PF_ACK_HINT",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "UMask": "0x40",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Misc Events - Set 0",
+        "EventCode": "0x1C",
+        "EventName": "UNC_I_MISC0.UNKNOWN",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "UMask": "0x80",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "Misc Events - Set 1; Lost Forward",
+        "EventCode": "0x1D",
+        "EventName": "UNC_I_MISC1.LOST_FWD",
         "PerPkg": "1",
-        "PortMask": "0x10",
+        "PublicDescription": "Snoop pulled away ownership before a write was committed",
         "UMask": "0x10",
-        "Unit": "IIO"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "Misc Events - Set 1; Received Invalid",
+        "EventCode": "0x1D",
+        "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
+        "UMask": "0x20",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Misc Events - Set 1; Received Valid",
+        "EventCode": "0x1D",
+        "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
+        "UMask": "0x40",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
+        "EventCode": "0x1D",
+        "EventName": "UNC_I_MISC1.SLOW_E",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
+        "UMask": "0x4",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
+        "EventCode": "0x1D",
+        "EventName": "UNC_I_MISC1.SLOW_I",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
+        "UMask": "0x1",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
+        "EventCode": "0x1D",
+        "EventName": "UNC_I_MISC1.SLOW_M",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
+        "UMask": "0x8",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Messages",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
+        "EventCode": "0x1D",
+        "EventName": "UNC_I_MISC1.SLOW_S",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
+        "UMask": "0x2",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Messages",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "P2P Requests",
+        "EventCode": "0x14",
+        "EventName": "UNC_I_P2P_INSERTS",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "P2P requests from the ITC",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Messages",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "P2P Occupancy",
+        "EventCode": "0x15",
+        "EventName": "UNC_I_P2P_OCCUPANCY",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "P2P B & S Queue Occupancy",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Messages",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "P2P Transactions; P2P completions",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "UMask": "0x8",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Messages",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD0",
-        "FCMask": "0x07",
+        "BriefDescription": "P2P Transactions; match if local only",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.LOC",
         "PerPkg": "1",
-        "PortMask": "0x10",
         "UMask": "0x40",
-        "Unit": "IIO"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU; Messages",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD1",
-        "FCMask": "0x07",
+        "BriefDescription": "P2P Transactions; match if local and target matches",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "UMask": "0x80",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Total Write Cache Occupancy; Any Source",
-        "Counter": "0,1",
-        "EventCode": "0xF",
-        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
+        "BriefDescription": "P2P Transactions; P2P Message",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.MSG",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x4",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Total Write Cache Occupancy; Snoops",
-        "Counter": "0,1",
-        "EventCode": "0xF",
-        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q",
+        "BriefDescription": "P2P Transactions; P2P reads",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.RD",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "UMask": "0x1",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "IRP Clocks",
-        "Counter": "0,1",
-        "EventCode": "0x1",
-        "EventName": "UNC_I_CLOCKTICKS",
+        "BriefDescription": "P2P Transactions; Match if remote only",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.REM",
         "PerPkg": "1",
+        "UMask": "0x10",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Coherent Ops; PCIRdCur",
-        "Counter": "0,1",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
+        "BriefDescription": "P2P Transactions; match if remote and target matches",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x20",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Coherent Ops; CRd",
-        "Counter": "0,1",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.CRD",
+        "BriefDescription": "P2P Transactions; P2P Writes",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.WR",
         "PerPkg": "1",
         "UMask": "0x2",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Coherent Ops; DRd",
-        "Counter": "0,1",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.DRD",
+        "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO",
+        "UMask": "0x7e",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Coherent Ops; PCIDCAHin5t",
-        "Counter": "0,1",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
+        "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache",
+        "UMask": "0x74",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Coherent Ops; WbMtoI",
-        "Counter": "0,1",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
+        "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache",
+        "UMask": "0x72",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Coherent Ops; CLFlush",
-        "Counter": "0,1",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
+        "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache",
+        "UMask": "0x78",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "FAF RF full",
-        "Counter": "0,1",
-        "EventCode": "0x17",
-        "EventName": "UNC_I_FAF_FULL",
+        "BriefDescription": "Responses to snoops of any type that miss the IIO cache",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.ALL_MISS",
         "PerPkg": "1",
+        "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that miss the IIO cache",
+        "UMask": "0x71",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "FAF allocation -- sent to ADQ",
-        "Counter": "0,1",
-        "EventCode": "0x16",
-        "EventName": "UNC_I_FAF_TRANSACTIONS",
+        "BriefDescription": "Snoop Responses; Hit E or S",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
         "PerPkg": "1",
+        "UMask": "0x4",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "All Inserts Inbound (p2p + faf + cset)",
-        "Counter": "0,1",
-        "EventCode": "0x1E",
-        "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
+        "BriefDescription": "Snoop Responses; Hit I",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.HIT_I",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "UMask": "0x2",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "All Inserts Outbound (BL, AK, Snoops)",
-        "Counter": "0,1",
-        "EventCode": "0x1E",
-        "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS",
+        "BriefDescription": "Snoop Responses; Hit M",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.HIT_M",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "UMask": "0x8",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
-        "Counter": "0,1",
-        "EventCode": "0x1C",
-        "EventName": "UNC_I_MISC0.FAST_REQ",
+        "BriefDescription": "Snoop Responses; Miss",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.MISS",
         "PerPkg": "1",
         "UMask": "0x1",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
-        "Counter": "0,1",
-        "EventCode": "0x1C",
-        "EventName": "UNC_I_MISC0.FAST_REJ",
+        "BriefDescription": "Snoop Responses; SnpCode",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "UMask": "0x10",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
-        "Counter": "0,1",
-        "EventCode": "0x1C",
-        "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
+        "BriefDescription": "Snoop Responses; SnpData",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "UMask": "0x20",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
-        "Counter": "0,1",
-        "EventCode": "0x1C",
-        "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
+        "BriefDescription": "Snoop Responses; SnpInv",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.SNPINV",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "UMask": "0x40",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
-        "Counter": "0,1",
-        "EventCode": "0x1C",
-        "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
+        "BriefDescription": "Inbound Transaction Count; Atomic",
+        "EventCode": "0x11",
+        "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions",
         "UMask": "0x10",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
-        "Counter": "0,1",
-        "EventCode": "0x1C",
-        "EventName": "UNC_I_MISC0.FAST_XFER",
+        "BriefDescription": "Inbound Transaction Count; Other",
+        "EventCode": "0x11",
+        "EventName": "UNC_I_TRANSACTIONS.OTHER",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions.",
         "UMask": "0x20",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
-        "Counter": "0,1",
-        "EventCode": "0x1C",
-        "EventName": "UNC_I_MISC0.PF_ACK_HINT",
+        "BriefDescription": "Inbound Transaction Count; Read Prefetches",
+        "EventCode": "0x11",
+        "EventName": "UNC_I_TRANSACTIONS.RD_PREF",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.",
+        "UMask": "0x4",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 0",
-        "Counter": "0,1",
-        "EventCode": "0x1C",
-        "EventName": "UNC_I_MISC0.UNKNOWN",
+        "BriefDescription": "Inbound Transaction Count; Reads",
+        "EventCode": "0x11",
+        "EventName": "UNC_I_TRANSACTIONS.READS",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).",
+        "UMask": "0x1",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
-        "Counter": "0,1",
-        "EventCode": "0x1D",
-        "EventName": "UNC_I_MISC1.SLOW_I",
+        "BriefDescription": "Inbound Transaction Count; Writes",
+        "EventCode": "0x11",
+        "EventName": "UNC_I_TRANSACTIONS.WRITES",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests.  Each write request should have a prefetch, so there is no need to explicitly track these requests.  For writes that are tickled and have to retry, the counter will be incremented for each retry.",
+        "UMask": "0x2",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
-        "Counter": "0,1",
-        "EventCode": "0x1D",
-        "EventName": "UNC_I_MISC1.SLOW_S",
+        "BriefDescription": "Inbound write (fast path) requests received by the IRP.",
+        "EventCode": "0x11",
+        "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.",
+        "UMask": "0x8",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
-        "Counter": "0,1",
-        "EventCode": "0x1D",
-        "EventName": "UNC_I_MISC1.SLOW_E",
+        "BriefDescription": "AK Egress Allocations",
+        "EventCode": "0xB",
+        "EventName": "UNC_I_TxC_AK_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x4",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
-        "Counter": "0,1",
-        "EventCode": "0x1D",
-        "EventName": "UNC_I_MISC1.SLOW_M",
+        "BriefDescription": "BL DRS Egress Cycles Full",
+        "EventCode": "0x5",
+        "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL",
         "PerPkg": "1",
-        "UMask": "0x8",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Lost Forward",
-        "Counter": "0,1",
-        "EventCode": "0x1D",
-        "EventName": "UNC_I_MISC1.LOST_FWD",
+        "BriefDescription": "BL DRS Egress Inserts",
+        "EventCode": "0x2",
+        "EventName": "UNC_I_TxC_BL_DRS_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x10",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Received Invalid",
-        "Counter": "0,1",
-        "EventCode": "0x1D",
-        "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
+        "BriefDescription": "BL DRS Egress Occupancy",
+        "EventCode": "0x8",
+        "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x20",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Misc Events - Set 1; Received Valid",
-        "Counter": "0,1",
-        "EventCode": "0x1D",
-        "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
+        "BriefDescription": "BL NCB Egress Cycles Full",
+        "EventCode": "0x6",
+        "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL",
         "PerPkg": "1",
-        "UMask": "0x40",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "P2P Requests",
-        "Counter": "0,1",
-        "EventCode": "0x14",
-        "EventName": "UNC_I_P2P_INSERTS",
+        "BriefDescription": "BL NCB Egress Inserts",
+        "EventCode": "0x3",
+        "EventName": "UNC_I_TxC_BL_NCB_INSERTS",
         "PerPkg": "1",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "P2P Occupancy",
-        "Counter": "0,1",
-        "EventCode": "0x15",
-        "EventName": "UNC_I_P2P_OCCUPANCY",
+        "BriefDescription": "BL NCB Egress Occupancy",
+        "EventCode": "0x9",
+        "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY",
         "PerPkg": "1",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "P2P Transactions; P2P reads",
-        "Counter": "0,1",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.RD",
+        "BriefDescription": "BL NCS Egress Cycles Full",
+        "EventCode": "0x7",
+        "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL",
         "PerPkg": "1",
-        "UMask": "0x1",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "P2P Transactions; P2P Writes",
-        "Counter": "0,1",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.WR",
+        "BriefDescription": "BL NCS Egress Inserts",
+        "EventCode": "0x4",
+        "EventName": "UNC_I_TxC_BL_NCS_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x2",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "P2P Transactions; P2P Message",
-        "Counter": "0,1",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.MSG",
+        "BriefDescription": "BL NCS Egress Occupancy",
+        "EventCode": "0xA",
+        "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x4",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "P2P Transactions; P2P completions",
-        "Counter": "0,1",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL",
+        "BriefDescription": "No AD Egress Credit Stalls",
+        "EventCode": "0x1A",
+        "EventName": "UNC_I_TxR2_AD_STALL_CREDIT_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "P2P Transactions; Match if remote only",
-        "Counter": "0,1",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.REM",
+        "BriefDescription": "No BL Egress Credit Stalls",
+        "EventCode": "0x1B",
+        "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "P2P Transactions; match if remote and target matches",
-        "Counter": "0,1",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH",
+        "BriefDescription": "Outbound Read Requests",
+        "EventCode": "0xD",
+        "EventName": "UNC_I_TxS_DATA_INSERTS_NCB",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "P2P Transactions; match if local only",
-        "Counter": "0,1",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.LOC",
+        "BriefDescription": "Outbound Read Requests",
+        "EventCode": "0xE",
+        "EventName": "UNC_I_TxS_DATA_INSERTS_NCS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "P2P Transactions; match if local and target matches",
-        "Counter": "0,1",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH",
+        "BriefDescription": "Outbound Request Queue Occupancy",
+        "EventCode": "0xC",
+        "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices).  This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Snoop Responses; Miss",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.MISS",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x1",
-        "Unit": "IRP"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Snoop Responses; Hit I",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.HIT_I",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x2",
-        "Unit": "IRP"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Snoop Responses; Hit E or S",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR2",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x4",
-        "Unit": "IRP"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Snoop Responses; Hit M",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.HIT_M",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x8",
-        "Unit": "IRP"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Snoop Responses; SnpCode",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x10",
-        "Unit": "IRP"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Snoop Responses; SnpData",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x20",
-        "Unit": "IRP"
-    },
-    {
-        "BriefDescription": "Snoop Responses; SnpInv",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.SNPINV",
-        "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "IRP"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Inbound Transaction Count; Reads",
-        "Counter": "0,1",
-        "EventCode": "0x11",
-        "EventName": "UNC_I_TRANSACTIONS.READS",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x1",
-        "Unit": "IRP"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Inbound Transaction Count; Writes",
-        "Counter": "0,1",
-        "EventCode": "0x11",
-        "EventName": "UNC_I_TRANSACTIONS.WRITES",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x2",
-        "Unit": "IRP"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Inbound Transaction Count; Read Prefetches",
-        "Counter": "0,1",
-        "EventCode": "0x11",
-        "EventName": "UNC_I_TRANSACTIONS.RD_PREF",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x4",
-        "Unit": "IRP"
-    },
-    {
-        "BriefDescription": "Inbound Transaction Count; Atomic",
-        "Counter": "0,1",
-        "EventCode": "0x11",
-        "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IRP"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Inbound Transaction Count; Other",
-        "Counter": "0,1",
-        "EventCode": "0x11",
-        "EventName": "UNC_I_TRANSACTIONS.OTHER",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IRP"
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "No AD Egress Credit Stalls",
-        "Counter": "0,1",
-        "EventCode": "0x1A",
-        "EventName": "UNC_I_TxR2_AD_STALL_CREDIT_CYCLES",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress Allocations",
-        "Counter": "0,1",
-        "EventCode": "0xB",
-        "EventName": "UNC_I_TxC_AK_INSERTS",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL DRS Egress Cycles Full",
-        "Counter": "0,1",
-        "EventCode": "0x5",
-        "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL DRS Egress Inserts",
-        "Counter": "0,1",
-        "EventCode": "0x2",
-        "EventName": "UNC_I_TxC_BL_DRS_INSERTS",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL DRS Egress Occupancy",
-        "Counter": "0,1",
-        "EventCode": "0x8",
-        "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL NCB Egress Cycles Full",
-        "Counter": "0,1",
-        "EventCode": "0x6",
-        "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL NCB Egress Inserts",
-        "Counter": "0,1",
-        "EventCode": "0x3",
-        "EventName": "UNC_I_TxC_BL_NCB_INSERTS",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL NCB Egress Occupancy",
-        "Counter": "0,1",
-        "EventCode": "0x9",
-        "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL NCS Egress Cycles Full",
-        "Counter": "0,1",
-        "EventCode": "0x7",
-        "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL NCS Egress Inserts",
-        "Counter": "0,1",
-        "EventCode": "0x4",
-        "EventName": "UNC_I_TxC_BL_NCS_INSERTS",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL NCS Egress Occupancy",
-        "Counter": "0,1",
-        "EventCode": "0xA",
-        "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "No BL Egress Credit Stalls",
-        "Counter": "0,1",
-        "EventCode": "0x1B",
-        "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Outbound Read Requests",
-        "Counter": "0,1",
-        "EventCode": "0xD",
-        "EventName": "UNC_I_TxS_DATA_INSERTS_NCB",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Outbound Read Requests",
-        "Counter": "0,1",
-        "EventCode": "0xE",
-        "EventName": "UNC_I_TxS_DATA_INSERTS_NCS",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Outbound Request Queue Occupancy",
-        "Counter": "0,1",
-        "EventCode": "0xC",
-        "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "UMask": "0x72",
-        "Unit": "IRP"
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "UMask": "0x74",
-        "Unit": "IRP"
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
-        "UMask": "0x78",
-        "Unit": "IRP"
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
-        "UMask": "0x7e",
-        "Unit": "IRP"
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Responses to snoops of any type that miss the IIO cache",
-        "Counter": "0,1",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.ALL_MISS",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
-        "UMask": "0x71",
-        "Unit": "IRP"
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
         "UMask": "0x1",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
         "UMask": "0x8",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
         "UMask": "0x10",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR5",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
         "UMask": "0x1",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
         "UMask": "0x2",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
         "UMask": "0x4",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
         "UMask": "0x8",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
         "UMask": "0x10",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x16",
-        "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR0",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x1",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR1",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x2",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR2",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x4",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR3",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x8",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x10",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x20",
-        "Unit": "UPI LL"
-    },
-    {
-        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
-        "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "UPI LL"
-    },
-    {
-        "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_UPI_PHY_INIT_CYCLES",
-        "PerPkg": "1",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "L1 Req Nack",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x23",
-        "EventName": "UNC_UPI_POWER_L1_NACK",
+        "BriefDescription": "Traffic in which the M2M to iMC Bypass was not taken",
+        "EventCode": "0x22",
+        "EventName": "UNC_M2M_BYPASS_M2M_Egress.NOT_TAKEN",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts traffic in which the M2M (Mesh to Memory) to iMC (Memory Controller) bypass was not taken",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "L1 Req (same as L1 Ack)",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "M2M to iMC Bypass; Taken",
         "EventCode": "0x22",
-        "EventName": "UNC_UPI_POWER_L1_REQ",
+        "EventName": "UNC_M2M_BYPASS_M2M_Egress.TAKEN",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x46",
-        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
+        "BriefDescription": "M2M to iMC Bypass; Not Taken",
+        "EventCode": "0x21",
+        "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "UPI LL"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x46",
-        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
+        "BriefDescription": "M2M to iMC Bypass; Taken",
+        "EventCode": "0x21",
+        "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "UPI LL"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x46",
-        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
+        "BriefDescription": "Cycles - at UCLK",
+        "EventName": "UNC_M2M_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x46",
-        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
+        "BriefDescription": "CMS Clockticks",
+        "EventCode": "0xC0",
+        "EventName": "UNC_M2M_CMS_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles in L0. Receive side",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled",
         "EventCode": "0x24",
-        "EventName": "UNC_UPI_RxL0_POWER_CYCLES",
+        "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts cycles when direct to core mode (which bypasses the CHA) was disabled",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "CRC Errors Detected",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB",
-        "EventName": "UNC_UPI_RxL_CRC_ERRORS",
+        "BriefDescription": "Messages sent direct to core (bypassing the CHA)",
+        "EventCode": "0x23",
+        "EventName": "UNC_M2M_DIRECT2CORE_TAKEN",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts when messages were sent direct to core (bypassing the CHA)",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "LLR Requests Sent",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8",
-        "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT",
+        "BriefDescription": "Number of reads in which direct to core transaction were overridden",
+        "EventCode": "0x25",
+        "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts reads in which direct to core transactions (which would have bypassed the CHA) were overridden",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "VN0 Credit Consumed",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0",
+        "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden",
+        "EventCode": "0x28",
+        "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts reads in which direct to Intel Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overridden",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "VN1 Credit Consumed",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3A",
-        "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1",
+        "BriefDescription": "Cycles when direct to Intel UPI was disabled",
+        "EventCode": "0x27",
+        "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts cycles when the ability to send messages direct to the Intel Ultra Path Interconnect (bypassing the CHA) was disabled",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "VNA Credit Consumed",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA",
+        "BriefDescription": "Messages sent direct to the Intel UPI",
+        "EventCode": "0x26",
+        "EventName": "UNC_M2M_DIRECT2UPI_TAKEN",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts when messages were sent direct to the Intel Ultra Path Interconnect (bypassing the CHA)",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Valid Flits Received; Slot 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.SLOT0",
+        "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden",
+        "EventCode": "0x29",
+        "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts when a read message that was sent direct to the Intel Ultra Path Interconnect (bypassing the CHA) was overridden",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Valid Flits Received; Slot 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.SLOT1",
+        "BriefDescription": "Directory Hit; On NonDirty Line in A State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "UPI LL"
+        "UMask": "0x80",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Valid Flits Received; Slot 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.SLOT2",
+        "BriefDescription": "Directory Hit; On NonDirty Line in I State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "UPI LL"
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Valid Flits Received; Data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.DATA",
+        "BriefDescription": "Directory Hit; On NonDirty Line in L State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P",
         "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "UPI LL"
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Valid Flits Received; LLCRD Not Empty",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.LLCRD",
+        "BriefDescription": "Directory Hit; On NonDirty Line in S State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "UPI LL"
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Valid Flits Received; LLCTRL",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.LLCTRL",
+        "BriefDescription": "Directory Hit; On Dirty Line in A State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "UPI LL"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.PROTHDR",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.PROT_HDR",
+        "BriefDescription": "Directory Hit; On Dirty Line in I State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "UPI LL"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_HDR_MATCH.REQ",
+        "BriefDescription": "Directory Hit; On Dirty Line in L State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P",
         "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "UPI LL"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_HDR_MATCH.SNP",
+        "BriefDescription": "Directory Hit; On Dirty Line in S State",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S",
         "PerPkg": "1",
-        "UMask": "0x9",
-        "Unit": "UPI LL"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_HDR_MATCH.RSP",
+        "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY",
         "PerPkg": "1",
-        "UMask": "0xA",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in Any State (A, I, S or unused)",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_HDR_MATCH.WB",
+    {
+        "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A",
         "PerPkg": "1",
-        "UMask": "0xB",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in the A (SnoopAll) state, indicating the cacheline is stored in another socket in any state, and we must snoop the other sockets to make sure we get the latest data.  The data may be stored in any state in the local socket.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_HDR_MATCH.NCB",
+        "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I",
         "PerPkg": "1",
-        "UMask": "0xC",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the I (Invalid) state indicating the cacheline is not stored in another socket, and so there is no need to snoop the other sockets for the latest data.  The data may be stored in any state in the local socket.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_HDR_MATCH.NCS",
+        "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S",
         "PerPkg": "1",
-        "UMask": "0xD",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the S (Shared) state indicating the cacheline is either stored in another socket in the S(hared) state , and so there is no need to snoop the other sockets for the latest data.  The data may be stored in any state in the local socket.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "RxQ Occupancy - All Packets; Slot 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0",
+        "BriefDescription": "Directory Miss; On NonDirty Line in A State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "UPI LL"
+        "UMask": "0x80",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "RxQ Occupancy - All Packets; Slot 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1",
+        "BriefDescription": "Directory Miss; On NonDirty Line in I State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "UPI LL"
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "RxQ Occupancy - All Packets; Slot 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x32",
-        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2",
+        "BriefDescription": "Directory Miss; On NonDirty Line in L State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "UPI LL"
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
+        "BriefDescription": "Directory Miss; On NonDirty Line in S State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "UPI LL"
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
+        "BriefDescription": "Directory Miss; On Dirty Line in A State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "UPI LL"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
+        "BriefDescription": "Directory Miss; On Dirty Line in I State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "UPI LL"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
+        "BriefDescription": "Directory Miss; On Dirty Line in L State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P",
         "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "UPI LL"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
+        "BriefDescription": "Directory Miss; On Dirty Line in S State",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "UPI LL"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x33",
-        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
+        "BriefDescription": "Multi-socket cacheline Directory update from A to I",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I",
         "PerPkg": "1",
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to I (Invalid)",
         "UMask": "0x20",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
+        "BriefDescription": "Multi-socket cacheline Directory update from A to S",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to S (Shared)",
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
+        "BriefDescription": "Multi-socket cacheline Directory update from/to Any state",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory to a new state",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
+        "BriefDescription": "Multi-socket cacheline Directory update from I to A",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A",
         "PerPkg": "1",
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to A (SnoopAll)",
         "UMask": "0x4",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
+        "BriefDescription": "Multi-socket cacheline Directory update from I to S",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S",
         "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to S (Shared)",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
+        "BriefDescription": "Multi-socket cacheline Directory update from S to A",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A",
         "PerPkg": "1",
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to A (SnoopAll)",
         "UMask": "0x10",
-        "Unit": "UPI LL"
-    },
-    {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
+        "BriefDescription": "Multi-socket cacheline Directory update from S to I",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to I (Invalid)",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
+        "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
+        "EventCode": "0xAE",
+        "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x28",
-        "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
+        "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
+        "EventCode": "0xAE",
+        "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x29",
-        "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
+        "BriefDescription": "FaST wire asserted; Horizontal",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M2M_FAST_ASSERTED.HORZ",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles in L0. Transmit side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x26",
-        "EventName": "UNC_UPI_TxL0_POWER_CYCLES",
+        "BriefDescription": "FaST wire asserted; Vertical",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M2M_FAST_ASSERTED.VERT",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Valid Flits Sent; Slot 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.SLOT0",
+        "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
         "UMask": "0x1",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Valid Flits Sent; Slot 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.SLOT1",
+        "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
         "UMask": "0x2",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Valid Flits Sent; Slot 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.SLOT2",
+        "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
         "UMask": "0x4",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Valid Flits Sent; LLCRD Not Empty",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.LLCRD",
+        "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
+        "EventCode": "0xA9",
+        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+        "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Valid Flits Sent; LLCTRL",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.LLCTRL",
+        "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
+        "EventCode": "0xA9",
+        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.PROTHDR",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.PROT_HDR",
+        "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
+        "EventCode": "0xA9",
+        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.REQ",
+        "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
+        "EventCode": "0xA9",
+        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
         "UMask": "0x8",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.SNP",
+        "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x9",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.WB",
+        "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0xC",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.NCB",
+        "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0xE",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.NCS",
+        "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0xF",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Tx Flit Buffer Allocations",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x40",
-        "EventName": "UNC_UPI_TxL_INSERTS",
+        "BriefDescription": "Horizontal IV Ring in Use; Left",
+        "EventCode": "0xAD",
+        "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Tx Flit Buffer Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x42",
-        "EventName": "UNC_UPI_TxL_OCCUPANCY",
+        "BriefDescription": "Horizontal IV Ring in Use; Right",
+        "EventCode": "0xAD",
+        "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x45",
-        "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
+        "BriefDescription": "Reads to iMC issued",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.ALL",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller).",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "VNA Credits Pending Return - Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x44",
-        "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY",
+        "BriefDescription": "M2M Reads Issued to iMC; All, regardless of priority.",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.FROM_TRANSGRESS",
         "PerPkg": "1",
-        "Unit": "UPI LL"
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
+        "BriefDescription": "M2M Reads Issued to iMC; Critical Priority",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.ISOCH",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "UPI LL"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Valid Flits Received; Protocol Header",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.PROTHDR",
+        "BriefDescription": "Reads to iMC issued at Normal Priority (Non-Isochronous)",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.NORMAL",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller).  It only counts  normal priority non-isochronous reads.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Valid Flits Sent; Protocol Header",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2",
-        "EventName": "UNC_UPI_TxL_FLITS.PROTHDR",
+        "BriefDescription": "Writes to iMC issued",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.ALL",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) issues writes to the iMC (Memory Controller).",
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
+        "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority.",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.FROM_TRANSGRESS",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "UPI LL"
+        "UMask": "0x40",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
+        "BriefDescription": "M2M Writes Issued to iMC; Full Line Non-ISOCH",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.FULL",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "UPI LL"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.LOC",
+        "BriefDescription": "M2M Writes Issued to iMC; ISOCH Full Line",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH",
         "PerPkg": "1",
-        "UMaskExt": "0x02",
-        "Unit": "UPI LL"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.REM",
+        "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority.",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.NI",
         "PerPkg": "1",
-        "UMaskExt": "0x04",
-        "Unit": "UPI LL"
+        "UMask": "0x80",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.DATA_HDR",
+        "BriefDescription": "Partial Non-Isochronous writes to the iMC",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.PARTIAL",
         "PerPkg": "1",
-        "UMaskExt": "0x08",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) issues partial writes to the iMC (Memory Controller).  It only counts normal priority non-isochronous writes.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.NON_DATA_HDR",
+        "BriefDescription": "M2M Writes Issued to iMC; ISOCH Partial",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH",
         "PerPkg": "1",
-        "UMaskExt": "0x10",
-        "Unit": "UPI LL"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.DUAL_SLOT_HDR",
+        "BriefDescription": "Number Packet Header Matches; MC Match",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M2M_PKT_MATCH.MC",
         "PerPkg": "1",
-        "UMaskExt": "0x20",
-        "Unit": "UPI LL"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.SGL_SLOT_HDR",
+        "BriefDescription": "Number Packet Header Matches; Mesh Match",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M2M_PKT_MATCH.MESH",
         "PerPkg": "1",
-        "UMaskExt": "0x40",
-        "Unit": "UPI LL"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_NODATA",
+        "BriefDescription": "Prefetch CAM Cycles Full",
+        "EventCode": "0x53",
+        "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL",
         "PerPkg": "1",
-        "UMask": "0xA",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_DATA",
+        "BriefDescription": "Prefetch CAM Cycles Not Empty",
+        "EventCode": "0x54",
+        "EventName": "UNC_M2M_PREFCAM_CYCLES_NE",
         "PerPkg": "1",
-        "UMask": "0xC",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Valid Flits Received; Idle",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_UPI_RxL_FLITS.IDLE",
+        "BriefDescription": "Prefetch requests that got turn into a demand request",
+        "EventCode": "0x56",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_PROMOTIONS",
         "PerPkg": "1",
-        "UMask": "0x47",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) promotes a outstanding request in the prefetch queue due to a subsequent demand read request that entered the M2M with the same address.  Explanatory Side Note: The Prefetch queue is made of CAM (Content Addressable Memory)",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
+        "BriefDescription": "Inserts into the Memory Controller Prefetch Queue",
+        "EventCode": "0x57",
+        "EventName": "UNC_M2M_PREFCAM_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts when the M2M (Mesh to Memory) receives a prefetch request and inserts it into its outstanding prefetch queue.  Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Request Opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC",
+        "BriefDescription": "Prefetch CAM Occupancy",
+        "EventCode": "0x55",
+        "EventName": "UNC_M2M_PREFCAM_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x0108",
-        "UMaskExt": "0x01",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Snoop",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x09",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Snoop Opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x0109",
-        "UMaskExt": "0x01",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x0A",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x010A",
-        "UMaskExt": "0x01",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD",
         "PerPkg": "1",
-        "UMask": "0x0C",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x010C",
-        "UMaskExt": "0x01",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Writeback",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x0D",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Writeback",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x010D",
-        "UMaskExt": "0x01",
-        "Unit": "UPI LL"
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x0E",
-        "Unit": "UPI LL"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x010E",
-        "UMaskExt": "0x01",
-        "Unit": "UPI LL"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x0F",
-        "Unit": "UPI LL"
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x010F",
-        "UMaskExt": "0x01",
-        "Unit": "UPI LL"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "UPI LL"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Request Opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC",
+        "BriefDescription": "Sink Starvation on Vertical Ring; AD",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD",
         "PerPkg": "1",
-        "UMask": "0x108",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
+        "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x09",
-        "Unit": "UPI LL"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop Opcode",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC",
+        "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x109",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
+        "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x0A",
-        "Unit": "UPI LL"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
+        "BriefDescription": "Source Throttle",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M2M_RING_SRC_THRTL",
         "PerPkg": "1",
-        "UMask": "0x10A",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0",
+        "Deprecated": "1",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
         "PerPkg": "1",
-        "UMask": "0x0C",
-        "Unit": "UPI LL"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1",
+        "Deprecated": "1",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
         "PerPkg": "1",
-        "UMask": "0x10C",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2",
+        "Deprecated": "1",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
         "PerPkg": "1",
-        "UMask": "0x0D",
-        "Unit": "UPI LL"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC",
+        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 0",
+        "EventCode": "0x43",
+        "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN0",
         "PerPkg": "1",
-        "UMask": "0x10D",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
+        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 1",
+        "EventCode": "0x43",
+        "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN1",
         "PerPkg": "1",
-        "UMask": "0x0E",
-        "Unit": "UPI LL"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
+        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 2",
+        "EventCode": "0x43",
+        "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN2",
         "PerPkg": "1",
-        "UMask": "0x10E",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
+        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 0",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0",
         "PerPkg": "1",
-        "UMask": "0x0F",
-        "Unit": "UPI LL"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
+        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 1",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1",
         "PerPkg": "1",
-        "UMask": "0x10F",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Response - Conflict",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT",
+        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 2",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2",
         "PerPkg": "1",
-        "UMask": "0x01AA",
-        "UMaskExt": "0x01",
-        "Unit": "UPI LL"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Receive path of a UPI Port; Response - Invalid",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x5",
-        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI",
+        "BriefDescription": "AD Ingress (from CMS) Full",
+        "EventCode": "0x4",
+        "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL",
         "PerPkg": "1",
-        "UMask": "0x012A",
-        "UMaskExt": "0x01",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "RxQ Flit Buffer Allocations; Slot 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x30",
-        "EventName": "UNC_UPI_RxL_INSERTS.SLOT0",
+        "BriefDescription": "AD Ingress (from CMS) Not Empty",
+        "EventCode": "0x3",
+        "EventName": "UNC_M2M_RxC_AD_CYCLES_NE",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "RxQ Flit Buffer Allocations; Slot 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x30",
-        "EventName": "UNC_UPI_RxL_INSERTS.SLOT1",
+        "BriefDescription": "AD Ingress (from CMS) Queue Inserts",
+        "EventCode": "0x1",
+        "EventName": "UNC_M2M_RxC_AD_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "UPI LL"
+        "PublicDescription": "Counts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop).  This is generally used for reads, and",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "RxQ Flit Buffer Allocations; Slot 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x30",
-        "EventName": "UNC_UPI_RxL_INSERTS.SLOT2",
+        "BriefDescription": "AD Ingress (from CMS) Occupancy",
+        "EventCode": "0x2",
+        "EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Conflict",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT",
+        "BriefDescription": "BL Ingress (from CMS) Full",
+        "EventCode": "0x8",
+        "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL",
         "PerPkg": "1",
-        "UMask": "0x1AA",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Invalid",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI",
+        "BriefDescription": "BL Ingress (from CMS) Not Empty",
+        "EventCode": "0x7",
+        "EventName": "UNC_M2M_RxC_BL_CYCLES_NE",
         "PerPkg": "1",
-        "UMask": "0x12A",
-        "UMaskExt": "0x1",
-        "Unit": "UPI LL"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2M to iMC Bypass; Taken",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x22",
-        "EventName": "UNC_M2M_BYPASS_M2M_Egress.TAKEN",
+        "BriefDescription": "BL Ingress (from CMS) Allocations",
+        "EventCode": "0x5",
+        "EventName": "UNC_M2M_RxC_BL_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles - at UCLK",
-        "Counter": "0,1,2,3",
-        "EventName": "UNC_M2M_CLOCKTICKS",
+        "BriefDescription": "BL Ingress (from CMS) Occupancy",
+        "EventCode": "0x6",
+        "EventName": "UNC_M2M_RxC_BL_OCCUPANCY",
         "PerPkg": "1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Directory Hit; On Dirty Line in I State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I",
+        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
         "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Directory Hit; On Dirty Line in S State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S",
+        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Directory Hit; On Dirty Line in L State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P",
+        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
         "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Directory Hit; On Dirty Line in A State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A",
+        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Directory Hit; On NonDirty Line in I State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I",
+        "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M2M_RxR_BYPASS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Directory Hit; On NonDirty Line in S State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S",
+        "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Directory Hit; On NonDirty Line in L State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P",
+        "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M2M_RxR_BYPASS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Directory Hit; On NonDirty Line in A State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A",
+        "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M2M_RxR_BYPASS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Directory Miss; On Dirty Line in I State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I",
+        "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Directory Miss; On Dirty Line in S State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S",
+        "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M2M_RxR_BYPASS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Directory Miss; On Dirty Line in L State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P",
+        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Directory Miss; On Dirty Line in A State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A",
+        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Directory Miss; On NonDirty Line in I State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I",
+        "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Directory Miss; On NonDirty Line in S State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S",
+        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Directory Miss; On NonDirty Line in L State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P",
+        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
         "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Directory Miss; On NonDirty Line in A State",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A",
+        "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV",
         "PerPkg": "1",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
         "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC; Critical Priority",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.ISOCH",
+        "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC; All, regardless of priority",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.FROM_TRANSGRESS",
+        "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M2M_RxR_INSERTS.AD_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
         "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC; Full Line Non-ISOCH",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.FULL",
+        "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M2M_RxR_INSERTS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC; ISOCH Full Line",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH",
+        "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M2M_RxR_INSERTS.BL_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
         "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC; ISOCH Partial",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH",
+        "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.FROM_TRANSGRESS",
+        "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M2M_RxR_INSERTS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Packet Header Matches; Mesh Match",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M2M_PKT_MATCH.MESH",
+        "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
         "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number Packet Header Matches; MC Match",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M2M_PKT_MATCH.MC",
+        "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD",
+        "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.AK_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
         "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Prefetch CAM Cycles Full",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x53",
-        "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL",
+        "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Prefetch CAM Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x54",
-        "EventName": "UNC_M2M_PREFCAM_CYCLES_NE",
+        "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Prefetch CAM Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x55",
-        "EventName": "UNC_M2M_PREFCAM_OCCUPANCY",
+        "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.IV_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number AD Ingress Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x41",
-        "EventName": "UNC_M2M_TGR_AD_CREDITS",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number BL Ingress Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x42",
-        "EventName": "UNC_M2M_TGR_BL_CREDITS",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Tracker Cycles Full; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x45",
-        "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH0",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+        "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Tracker Cycles Full; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x45",
-        "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH1",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Tracker Cycles Full; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x45",
-        "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH2",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Tracker Cycles Not Empty; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH0",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Tracker Cycles Not Empty; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH1",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Tracker Cycles Not Empty; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH2",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Tracker Inserts; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x49",
-        "EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Tracker Inserts; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x49",
-        "EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Tracker Inserts; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x49",
-        "EventName": "UNC_M2M_TRACKER_INSERTS.CH2",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Tracker Occupancy; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x47",
-        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "Tracker Occupancy; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x47",
-        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Tracker Occupancy; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x47",
-        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Pending Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x48",
-        "EventName": "UNC_M2M_TRACKER_PENDING_OCCUPANCY",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Full; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH0",
-        "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "Write Tracker Cycles Full; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH1",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
         "PerPkg": "1",
-        "UMask": "0x2",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Full; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH2",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Not Empty; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH0",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Not Empty; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH1",
+        "BriefDescription": "Number AD Ingress Credits",
+        "EventCode": "0x41",
+        "EventName": "UNC_M2M_TGR_AD_CREDITS",
         "PerPkg": "1",
-        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Not Empty; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH2",
+        "BriefDescription": "Number BL Ingress Credits",
+        "EventCode": "0x42",
+        "EventName": "UNC_M2M_TGR_BL_CREDITS",
         "PerPkg": "1",
-        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Inserts; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x61",
-        "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH0",
+        "BriefDescription": "Tracker Cycles Full; Channel 0",
+        "EventCode": "0x45",
+        "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH0",
         "PerPkg": "1",
         "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Inserts; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x61",
-        "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH1",
+        "BriefDescription": "Tracker Cycles Full; Channel 1",
+        "EventCode": "0x45",
+        "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH1",
         "PerPkg": "1",
         "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Inserts; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x61",
-        "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH2",
+        "BriefDescription": "Tracker Cycles Full; Channel 2",
+        "EventCode": "0x45",
+        "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH2",
         "PerPkg": "1",
         "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Occupancy; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x60",
-        "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH0",
+        "BriefDescription": "Tracker Cycles Not Empty; Channel 0",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH0",
         "PerPkg": "1",
         "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Occupancy; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x60",
-        "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH1",
+        "BriefDescription": "Tracker Cycles Not Empty; Channel 1",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH1",
         "PerPkg": "1",
         "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Occupancy; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x60",
-        "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH2",
+        "BriefDescription": "Tracker Cycles Not Empty; Channel 2",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH2",
         "PerPkg": "1",
         "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR0",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR1",
-        "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR2",
+        "BriefDescription": "Tracker Inserts; Channel 0",
+        "EventCode": "0x49",
+        "EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR3",
+        "BriefDescription": "Tracker Inserts; Channel 1",
+        "EventCode": "0x49",
+        "EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR4",
+        "BriefDescription": "Tracker Inserts; Channel 2",
+        "EventCode": "0x49",
+        "EventName": "UNC_M2M_TRACKER_INSERTS.CH2",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR5",
+        "BriefDescription": "Tracker Occupancy; Channel 0",
+        "EventCode": "0x47",
+        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR0",
+        "BriefDescription": "Tracker Occupancy; Channel 1",
+        "EventCode": "0x47",
+        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "Tracker Occupancy; Channel 2",
+        "EventCode": "0x47",
+        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "Data Pending Occupancy",
+        "EventCode": "0x48",
+        "EventName": "UNC_M2M_TRACKER_PENDING_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x04",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "AD Egress (to CMS) Credit Acquired",
+        "EventCode": "0xD",
+        "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED",
         "PerPkg": "1",
-        "UMask": "0x08",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "AD Egress (to CMS) Credits Occupancy",
+        "EventCode": "0xE",
+        "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR5",
+        "BriefDescription": "AD Egress (to CMS) Full",
+        "EventCode": "0xC",
+        "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL",
         "PerPkg": "1",
-        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR0",
+        "BriefDescription": "AD Egress (to CMS) Not Empty",
+        "EventCode": "0xB",
+        "EventName": "UNC_M2M_TxC_AD_CYCLES_NE",
         "PerPkg": "1",
-        "UMask": "0x01",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR1",
+        "BriefDescription": "AD Egress (to CMS) Allocations",
+        "EventCode": "0x9",
+        "EventName": "UNC_M2M_TxC_AD_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x02",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR2",
+        "BriefDescription": "Cycles with No AD Egress (to CMS) Credits",
+        "EventCode": "0xF",
+        "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x04",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR3",
+        "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits",
+        "EventCode": "0x10",
+        "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED",
         "PerPkg": "1",
-        "UMask": "0x08",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR4",
+        "BriefDescription": "AD Egress (to CMS) Occupancy",
+        "EventCode": "0xA",
+        "EventName": "UNC_M2M_TxC_AD_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR5",
+        "BriefDescription": "Outbound Ring Transactions on AK; CRD Transactions to Cbo",
+        "EventCode": "0x39",
+        "EventName": "UNC_M2M_TxC_AK.CRD_CBO",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR0",
+        "BriefDescription": "Outbound Ring Transactions on AK; NDR Transactions",
+        "EventCode": "0x39",
+        "EventName": "UNC_M2M_TxC_AK.NDR",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side",
+        "EventCode": "0x1E",
+        "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side",
+        "EventCode": "0x1E",
+        "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR5",
+        "BriefDescription": "AK Egress (to CMS) Full; All",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x3",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR0",
+        "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Near Side",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR1",
+        "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Far Side",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR2",
+        "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR3",
+        "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x88",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR4",
+        "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR5",
+        "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0xa0",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR0",
+        "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x90",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "AK Egress (to CMS) Not Empty; All",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x3",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Near Side",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Far Side",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR5",
+        "BriefDescription": "AK Egress (to CMS) Not Empty; Read Credit Request",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR0",
+        "BriefDescription": "AK Egress (to CMS) Not Empty; Write Compare Request",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "AK Egress (to CMS) Not Empty; Write Credit Request",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "AK Egress (to CMS) Allocations; All",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x3",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Near Side",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Far Side",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR5",
+        "BriefDescription": "AK Egress (to CMS) Allocations; Prefetch Read Cam Hit",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR0",
+        "BriefDescription": "AK Egress (to CMS) Allocations; Read Credit Request",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR1",
+        "BriefDescription": "AK Egress (to CMS) Allocations; Write Compare Request",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR2",
+        "BriefDescription": "AK Egress (to CMS) Allocations; Write Credit Request",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR3",
+        "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side",
+        "EventCode": "0x1F",
+        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR4",
+        "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side",
+        "EventCode": "0x1F",
+        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR5",
+        "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side",
+        "EventCode": "0x20",
+        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAE",
-        "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN",
+        "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side",
+        "EventCode": "0x20",
+        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAE",
-        "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP",
+        "BriefDescription": "AK Egress (to CMS) Occupancy; All",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x3",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+        "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Near Side",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD",
+        "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Far Side",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "AK Egress (to CMS) Occupancy; Read Credit Request",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+        "BriefDescription": "AK Egress (to CMS) Occupancy; Write Compare Request",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA9",
-        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+        "BriefDescription": "AK Egress (to CMS) Occupancy; Write Credit Request",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA9",
-        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD",
+        "BriefDescription": "AK Egress (to CMS) Sideband",
+        "EventCode": "0x6B",
+        "EventName": "UNC_M2M_TxC_AK_SIDEBAND.RD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA9",
-        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "AK Egress (to CMS) Sideband",
+        "EventCode": "0x6B",
+        "EventName": "UNC_M2M_TxC_AK_SIDEBAND.WR",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA9",
-        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2M_TxC_BL.DRS_CACHE",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2M_TxC_BL.DRS_CORE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD",
+        "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2M_TxC_BL.DRS_UPI",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+        "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use; Left",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAD",
-        "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT",
+        "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side",
+        "EventCode": "0x1A",
+        "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use; Right",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAD",
-        "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT",
+        "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side",
+        "EventCode": "0x1A",
+        "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD",
+        "BriefDescription": "BL Egress (to CMS) Full; All",
+        "EventCode": "0x18",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x3",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK",
+        "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Near Side",
+        "EventCode": "0x18",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL",
+        "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Far Side",
+        "EventCode": "0x18",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV",
+        "BriefDescription": "BL Egress (to CMS) Not Empty; All",
+        "EventCode": "0x17",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x3",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD",
+        "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Near Side",
+        "EventCode": "0x17",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK",
+        "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Far Side",
+        "EventCode": "0x17",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL",
+        "BriefDescription": "BL Egress (to CMS) Allocations; All",
+        "EventCode": "0x15",
+        "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x3",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV",
+        "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Near Side",
+        "EventCode": "0x15",
+        "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD",
+        "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Far Side",
+        "EventCode": "0x15",
+        "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK",
+        "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side",
+        "EventCode": "0x1B",
+        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1",
+        "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side",
+        "EventCode": "0x1B",
+        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL",
+        "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV",
+        "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; AD",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD",
+        "BriefDescription": "BL Egress (to CMS) Occupancy; All",
+        "EventCode": "0x16",
+        "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x3",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK",
+        "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Near Side",
+        "EventCode": "0x16",
+        "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL",
+        "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Far Side",
+        "EventCode": "0x16",
+        "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV",
+        "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Source Throttle",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M2M_RING_SRC_THRTL",
+        "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AD Ingress (from CMS) Full",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4",
-        "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL",
+        "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AK_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AD Ingress (from CMS) Not Empty",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x3",
-        "EventName": "UNC_M2M_RxC_AD_CYCLES_NE",
+        "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Ingress (from CMS) Full",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x8",
-        "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL",
+        "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Ingress (from CMS) Not Empty",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x7",
-        "EventName": "UNC_M2M_RxC_BL_CYCLES_NE",
+        "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_BNC",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_BNC",
+        "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD",
+        "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_BNC",
+        "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD",
+        "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
         "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M2M_RxR_BYPASS.AD_BNC",
+        "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_BNC",
+        "PerPkg": "1",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M2M_RxR_BYPASS.AK_BNC",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M2M_RxR_BYPASS.BL_BNC",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M2M_RxR_BYPASS.IV_BNC",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_BNC",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce",
+        "EventCode": "0x97",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit",
+        "EventCode": "0x97",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.AK_BNC",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce",
+        "EventCode": "0x97",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_BNC",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce",
+        "EventCode": "0x97",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit",
+        "EventCode": "0x97",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce",
+        "EventCode": "0x97",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.IV_BNC",
+        "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce",
+        "EventCode": "0x95",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M2M_RxR_INSERTS.AD_BNC",
+        "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit",
+        "EventCode": "0x95",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD",
+        "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce",
+        "EventCode": "0x95",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M2M_RxR_INSERTS.AK_BNC",
+        "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce",
+        "EventCode": "0x95",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M2M_RxR_INSERTS.BL_BNC",
+        "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit",
+        "EventCode": "0x95",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD",
+        "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce",
+        "EventCode": "0x95",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M2M_RxR_INSERTS.IV_BNC",
+        "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce",
+        "EventCode": "0x99",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_BNC",
+        "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit",
+        "EventCode": "0x99",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD",
+        "PerPkg": "1",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce",
+        "EventCode": "0x99",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD",
+        "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce",
+        "EventCode": "0x99",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.AK_BNC",
+        "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit",
+        "EventCode": "0x99",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_BNC",
+        "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce",
+        "EventCode": "0x99",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.IV_BNC",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
         "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
         "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+        "BriefDescription": "CMS Vertical ADS Used; IV",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
         "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Credits Occupancy",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xE",
-        "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Credit Acquired",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xD",
-        "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG0",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Full",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC",
-        "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Not Empty",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xB",
-        "EventName": "UNC_M2M_TxC_AD_CYCLES_NE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.IV",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles with No AD Egress (to CMS) Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xF",
-        "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0",
+        "EventCode": "0x93",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG0",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x10",
-        "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1",
+        "EventCode": "0x93",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Outbound Ring Transactions on AK; CRD Transactions to Cbo",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_M2M_TxC_AK.CRD_CBO",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0",
+        "EventCode": "0x93",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Outbound Ring Transactions on AK; NDR Transactions",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x39",
-        "EventName": "UNC_M2M_TxC_AK.NDR",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1",
+        "EventCode": "0x93",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1E",
-        "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS0",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0",
+        "EventCode": "0x93",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1E",
-        "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS1",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1",
+        "EventCode": "0x93",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV",
+        "EventCode": "0x93",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.IV",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1",
+        "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0",
+        "EventCode": "0x91",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1F",
-        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0",
+        "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1",
+        "EventCode": "0x91",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1F",
-        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1",
+        "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0",
+        "EventCode": "0x91",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0",
+        "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1",
+        "EventCode": "0x91",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x20",
-        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1",
+        "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0",
+        "EventCode": "0x91",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2M_TxC_BL.DRS_CACHE",
+        "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1",
+        "EventCode": "0x91",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2M_TxC_BL.DRS_CORE",
+        "BriefDescription": "CMS Vert Egress Allocations; IV",
+        "EventCode": "0x91",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS.IV",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1A",
-        "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS0",
+        "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1A",
-        "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS1",
+        "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0",
+        "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1",
+        "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Full; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL",
+        "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x03",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0",
+        "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x18",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1",
+        "BriefDescription": "CMS Vertical Egress NACKs; IV",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK.IV",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Not Empty; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x17",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL",
+        "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x03",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x17",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0",
+        "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x17",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1",
+        "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0",
+        "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x15",
-        "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1",
+        "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1B",
-        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0",
+        "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1B",
-        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1",
+        "BriefDescription": "CMS Vert Egress Occupancy; IV",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.IV",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x16",
-        "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS0",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x16",
-        "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS1",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_BNC",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AK_BNC",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED.IV",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_BNC",
+        "BriefDescription": "Vertical AD Ring In Use; Down and Even",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD",
+        "BriefDescription": "Vertical AD Ring In Use; Down and Odd",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9F",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_BNC",
+        "BriefDescription": "Vertical AD Ring In Use; Up and Even",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9F",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD",
+        "BriefDescription": "Vertical AD Ring In Use; Up and Odd",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9F",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK_BNC",
+        "BriefDescription": "Vertical AK Ring In Use; Down and Even",
+        "EventCode": "0xA8",
+        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9F",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_BNC",
+        "BriefDescription": "Vertical AK Ring In Use; Down and Odd",
+        "EventCode": "0xA8",
+        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9F",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD",
+        "BriefDescription": "Vertical AK Ring In Use; Up and Even",
+        "EventCode": "0xA8",
+        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9F",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV_BNC",
+        "BriefDescription": "Vertical AK Ring In Use; Up and Odd",
+        "EventCode": "0xA8",
+        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_BNC",
+        "BriefDescription": "Vertical BL Ring in Use; Down and Even",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD",
+        "BriefDescription": "Vertical BL Ring in Use; Down and Odd",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK_BNC",
+        "BriefDescription": "Vertical BL Ring in Use; Up and Even",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_BNC",
+        "BriefDescription": "Vertical BL Ring in Use; Up and Odd",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD",
+        "BriefDescription": "Vertical IV Ring in Use; Down",
+        "EventCode": "0xAC",
+        "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV_BNC",
+        "BriefDescription": "Vertical IV Ring in Use; Up",
+        "EventCode": "0xAC",
+        "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x97",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0",
+        "Deprecated": "1",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x97",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1",
+        "Deprecated": "1",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x97",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2",
+        "Deprecated": "1",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x97",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_BNC",
+        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x97",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD",
+        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x97",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV_BNC",
+        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x95",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_BNC",
+        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 0",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x95",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD",
+        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 1",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x95",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK_BNC",
+        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 2",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN2",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x95",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_BNC",
+        "BriefDescription": "Write Tracker Cycles Full; Channel 0",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x95",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD",
+        "BriefDescription": "Write Tracker Cycles Full; Channel 1",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x95",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV_BNC",
+        "BriefDescription": "Write Tracker Cycles Full; Channel 2",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH2",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x99",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_BNC",
+        "BriefDescription": "Write Tracker Cycles Not Empty; Channel 0",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x99",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD",
+        "BriefDescription": "Write Tracker Cycles Not Empty; Channel 1",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x99",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.AK_BNC",
+        "BriefDescription": "Write Tracker Cycles Not Empty; Channel 2",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH2",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x99",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_BNC",
+        "BriefDescription": "Write Tracker Inserts; Channel 0",
+        "EventCode": "0x61",
+        "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x99",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD",
+        "BriefDescription": "Write Tracker Inserts; Channel 1",
+        "EventCode": "0x61",
+        "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x99",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.IV_BNC",
+        "BriefDescription": "Write Tracker Inserts; Channel 2",
+        "EventCode": "0x61",
+        "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH2",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_BNC",
+        "BriefDescription": "Write Tracker Occupancy; Channel 0",
+        "EventCode": "0x60",
+        "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD",
+        "BriefDescription": "Write Tracker Occupancy; Channel 1",
+        "EventCode": "0x60",
+        "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK_BNC",
+        "BriefDescription": "Write Tracker Occupancy; Channel 2",
+        "EventCode": "0x60",
+        "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH2",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_BNC",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
+        "EventCode": "0x80",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
+        "EventCode": "0x80",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
+        "EventCode": "0x80",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR2",
+        "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV_BNC",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
+        "EventCode": "0x80",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9B",
-        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_BNC",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
+        "EventCode": "0x80",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9B",
-        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK_BNC",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
+        "EventCode": "0x80",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9B",
-        "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_BNC",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
+        "EventCode": "0x82",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9B",
-        "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV_BNC",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
+        "EventCode": "0x82",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
+        "EventCode": "0x82",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
+        "EventCode": "0x82",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG0",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
+        "EventCode": "0x82",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG1",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
+        "EventCode": "0x82",
+        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x20",
-        "Unit": "M2M"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
+        "EventCode": "0x88",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
+        "EventCode": "0x88",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
+        "EventCode": "0x88",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
+        "EventCode": "0x88",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
+        "EventCode": "0x88",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
+        "EventCode": "0x88",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x20",
-        "Unit": "M2M"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG0",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG1",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
         "UMask": "0x10",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG0",
-        "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG1",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
         "UMask": "0x20",
-        "Unit": "M2M"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG0",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
+        "EventCode": "0x84",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG1",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
+        "EventCode": "0x84",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.IV",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
+        "EventCode": "0x84",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x93",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG0",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
+        "EventCode": "0x84",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR3",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x93",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG1",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
+        "EventCode": "0x84",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x10",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x93",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG0",
-        "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x93",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG1",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
+        "EventCode": "0x84",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x20",
-        "Unit": "M2M"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x93",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG0",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
+        "EventCode": "0x86",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x93",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG1",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
+        "EventCode": "0x86",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x93",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.IV",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
+        "EventCode": "0x86",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x91",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG0",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
+        "EventCode": "0x86",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x91",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG1",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
+        "EventCode": "0x86",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
         "UMask": "0x10",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x91",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG0",
-        "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x91",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG1",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
+        "EventCode": "0x86",
+        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
         "UMask": "0x20",
-        "Unit": "M2M"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x91",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG0",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x91",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG1",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR1",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x91",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS.IV",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR2",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG0",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR3",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG1",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG0",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR5",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG1",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR0",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG0",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR1",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG1",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR2",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG0",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR3",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG1",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG0",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR5",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG1",
+        "BriefDescription": "CBox AD Credits Empty; Requests",
+        "EventCode": "0x22",
+        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG0",
+        "BriefDescription": "CBox AD Credits Empty; Snoops",
+        "EventCode": "0x22",
+        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG1",
+        "BriefDescription": "CBox AD Credits Empty; VNA Messages",
+        "EventCode": "0x22",
+        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.IV",
+        "BriefDescription": "CBox AD Credits Empty; Writebacks",
+        "EventCode": "0x22",
+        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG0",
+        "BriefDescription": "Number of uclks in domain",
+        "EventCode": "0x1",
+        "EventName": "UNC_M3UPI_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of uclks in the M3 uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG1",
+        "BriefDescription": "CMS Clockticks",
+        "EventCode": "0xC0",
+        "EventName": "UNC_M3UPI_CMS_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG0",
+        "BriefDescription": "D2C Sent",
+        "EventCode": "0x2B",
+        "EventName": "UNC_M3UPI_D2C_SENT",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Count cases BL sends direct to core",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG1",
+        "BriefDescription": "D2U Sent",
+        "EventCode": "0x2A",
+        "EventName": "UNC_M3UPI_D2U_SENT",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "Cases where SMI3 sends D2U command",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG0",
+        "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
+        "EventCode": "0xAE",
+        "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG1",
+        "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
+        "EventCode": "0xAE",
+        "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use; Down and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN",
+        "BriefDescription": "FaST wire asserted; Horizontal",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M3UPI_FAST_ASSERTED.HORZ",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use; Down and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD",
+        "BriefDescription": "FaST wire asserted; Vertical",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M3UPI_FAST_ASSERTED.VERT",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use; Up and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN",
+        "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use; Up and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD",
+        "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use; Down and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA8",
-        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN",
+        "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use; Down and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA8",
-        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD",
+        "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use; Up and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA8",
-        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN",
+        "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
+        "EventCode": "0xA9",
+        "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use; Up and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA8",
-        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD",
+        "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
+        "EventCode": "0xA9",
+        "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use; Down and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAA",
-        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN",
+        "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
+        "EventCode": "0xA9",
+        "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use; Down and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAA",
-        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD",
+        "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
+        "EventCode": "0xA9",
+        "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use; Up and Even",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAA",
-        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN",
+        "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use; Up and Odd",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAA",
-        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD",
+        "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical IV Ring in Use; Down",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAC",
-        "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN",
+        "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Vertical IV Ring in Use; Up",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xAC",
-        "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP",
+        "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_TxC_BL.DRS_UPI",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x40",
-        "EventName": "UNC_NoUnit_TxC_BL.DRS_UPI",
+        "BriefDescription": "Horizontal IV Ring in Use; Left",
+        "EventCode": "0xAD",
+        "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0",
+        "BriefDescription": "Horizontal IV Ring in Use; Right",
+        "EventCode": "0xAD",
+        "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1",
+        "BriefDescription": "M2 BL Credits Empty; IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)",
+        "EventCode": "0x23",
+        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO0_IIO1_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "No vn0 and vna credits available to send to M2",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2",
+        "BriefDescription": "M2 BL Credits Empty; IIO2",
+        "EventCode": "0x23",
+        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "No vn0 and vna credits available to send to M2",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2M_TxC_BL.DRS_UPI",
+        "BriefDescription": "M2 BL Credits Empty; IIO3",
+        "EventCode": "0x23",
+        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "No vn0 and vna credits available to send to M2",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK.IV",
+        "BriefDescription": "M2 BL Credits Empty; IIO4",
+        "EventCode": "0x23",
+        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "No vn0 and vna credits available to send to M2",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED.IV",
+        "BriefDescription": "M2 BL Credits Empty; IIO5",
+        "EventCode": "0x23",
+        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "No vn0 and vna credits available to send to M2",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0",
+        "BriefDescription": "M2 BL Credits Empty; All IIO targets for NCS are in single mask. ORs them together",
+        "EventCode": "0x23",
+        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "No vn0 and vna credits available to send to M2",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1",
+        "BriefDescription": "M2 BL Credits Empty; Selected M2p BL NCS credits",
+        "EventCode": "0x23",
+        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "No vn0 and vna credits available to send to M2",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2",
+        "BriefDescription": "Multi Slot Flit Received; AD - Slot 0",
+        "EventCode": "0x3E",
+        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M to iMC Bypass; Taken",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN",
+        "BriefDescription": "Multi Slot Flit Received; AD - Slot 1",
+        "EventCode": "0x3E",
+        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M to iMC Bypass; Not Taken",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x21",
-        "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN",
+        "BriefDescription": "Multi Slot Flit Received; AD - Slot 2",
+        "EventCode": "0x3E",
+        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Clockticks",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xC0",
-        "EventName": "UNC_M2M_CMS_CLOCKTICKS",
+        "BriefDescription": "Multi Slot Flit Received; AK - Slot 0",
+        "EventCode": "0x3E",
+        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN0",
+        "BriefDescription": "Multi Slot Flit Received; AK - Slot 2",
+        "EventCode": "0x3E",
+        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN1",
+        "BriefDescription": "Multi Slot Flit Received; BL - Slot 0",
+        "EventCode": "0x3E",
+        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN2",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "FaST wire asserted; Vertical",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M2M_FAST_ASSERTED.VERT",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "FaST wire asserted; Horizontal",
-        "Counter": "0,1,2,3",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M2M_FAST_ASSERTED.HORZ",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 0",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x43",
-        "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN0",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 1",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x43",
-        "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN1",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 2",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x43",
-        "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN2",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1",
         "PerPkg": "1",
         "UMask": "0x20",
-        "Unit": "M2M"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x88",
-        "Unit": "M2M"
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1",
+        "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x90",
-        "Unit": "M2M"
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1",
+        "BriefDescription": "Sink Starvation on Vertical Ring; AD",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD",
         "PerPkg": "1",
-        "UMask": "0xA0",
-        "Unit": "M2M"
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL",
+        "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0",
+        "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1",
+        "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty; Read Credit Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD",
+        "BriefDescription": "Source Throttle",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M3UPI_RING_SRC_THRTL",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty; Write Credit Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD",
+        "BriefDescription": "Lost Arb for VN0; REQ on AD",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2M"
+        "PublicDescription": "VN0 message requested but lost arbitration; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty; Write Compare Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP",
+        "BriefDescription": "Lost Arb for VN0; RSP on AD",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "VN0 message requested but lost arbitration; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL",
+        "BriefDescription": "Lost Arb for VN0; SNP on AD",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "PublicDescription": "VN0 message requested but lost arbitration; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0",
+        "BriefDescription": "Lost Arb for VN0; NCB on BL",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "VN0 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1",
+        "BriefDescription": "Lost Arb for VN0; NCS on BL",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "VN0 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations; Read Credit Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD",
+        "BriefDescription": "Lost Arb for VN0; RSP on BL",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "VN0 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations; Write Credit Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD",
+        "BriefDescription": "Lost Arb for VN0; WB on BL",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB",
         "PerPkg": "1",
+        "PublicDescription": "VN0 message requested but lost arbitration; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations; Write Compare Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP",
+        "BriefDescription": "Lost Arb for VN1; REQ on AD",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "VN1 message requested but lost arbitration; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations; Prefetch Read Cam Hit",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT",
+        "BriefDescription": "Lost Arb for VN1; RSP on AD",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2M"
+        "PublicDescription": "VN1 message requested but lost arbitration; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL",
+        "BriefDescription": "Lost Arb for VN1; SNP on AD",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "PublicDescription": "VN1 message requested but lost arbitration; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0",
+        "BriefDescription": "Lost Arb for VN1; NCB on BL",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "VN1 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1",
+        "BriefDescription": "Lost Arb for VN1; NCS on BL",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "VN1 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy; Read Credit Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD",
+        "BriefDescription": "Lost Arb for VN1; RSP on BL",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "VN1 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy; Write Credit Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD",
+        "BriefDescription": "Lost Arb for VN1; WB on BL",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB",
         "PerPkg": "1",
+        "PublicDescription": "VN1 message requested but lost arbitration; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
         "UMask": "0x10",
-        "Unit": "M2M"
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy; Write Compare Request",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP",
+        "BriefDescription": "Arb Miscellaneous; AD, BL Parallel Win",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2M"
+        "PublicDescription": "AD and BL messages won arbitration concurrently / in parallel",
+        "UMask": "0x40",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy; All",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL",
+        "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN0",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "PublicDescription": "Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Sideband",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6B",
-        "EventName": "UNC_M2M_TxC_AK_SIDEBAND.RD",
+        "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN1",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Sideband",
-        "Counter": "0,1,2,3",
-        "EventCode": "0x6B",
-        "EventName": "UNC_M2M_TxC_AK_SIDEBAND.WR",
+        "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN0",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UPI0 AD Credits Empty; VNA",
-        "Counter": "0,1,2",
-        "EventCode": "0x20",
-        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA",
+        "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN1",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1",
+        "PerPkg": "1",
+        "PublicDescription": "Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN0",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN0",
         "PerPkg": "1",
+        "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win to vn0, delaying vn1 win, because vn0 offered parallel ad/bl",
         "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UPI0 AD Credits Empty; VN0 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x20",
-        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ",
+        "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN1",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN1",
         "PerPkg": "1",
+        "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win to vn1, delaying vn0 win, because vn1 offered parallel ad/bl",
         "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UPI0 AD Credits Empty; VN0 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x20",
-        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP",
+        "BriefDescription": "Can't Arb for VN0; REQ on AD",
+        "EventCode": "0x49",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x4",
+        "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UPI0 AD Credits Empty; VN0 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x20",
-        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP",
+        "BriefDescription": "Can't Arb for VN0; RSP on AD",
+        "EventCode": "0x49",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UPI0 AD Credits Empty; VN1 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x20",
-        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ",
+        "BriefDescription": "Can't Arb for VN0; SNP on AD",
+        "EventCode": "0x49",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UPI0 AD Credits Empty; VN1 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x20",
-        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP",
+        "BriefDescription": "Can't Arb for VN0; NCB on BL",
+        "EventCode": "0x49",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCB",
         "PerPkg": "1",
+        "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UPI0 AD Credits Empty; VN1 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x20",
-        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP",
+        "BriefDescription": "Can't Arb for VN0; NCS on BL",
+        "EventCode": "0x49",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCS",
         "PerPkg": "1",
+        "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL.",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UPI0 BL Credits Empty; VN1 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x21",
-        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP",
+        "BriefDescription": "Can't Arb for VN0; RSP on BL",
+        "EventCode": "0x49",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UPI0 BL Credits Empty; VN1 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x21",
-        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB",
+        "BriefDescription": "Can't Arb for VN0; WB on BL",
+        "EventCode": "0x49",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UPI0 BL Credits Empty; VN1 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x21",
-        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB",
+        "BriefDescription": "Can't Arb for VN1; REQ on AD",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN0",
-        "EventCode": "0x3C",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI0",
+        "BriefDescription": "Can't Arb for VN1; RSP on AD",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x1",
+        "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN0",
-        "EventCode": "0x3C",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI1",
+        "BriefDescription": "Can't Arb for VN1; SNP on AD",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_SNP",
         "PerPkg": "1",
+        "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
         "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN1",
-        "EventCode": "0x3C",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI0",
+        "BriefDescription": "Can't Arb for VN1; NCB on BL",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x8",
+        "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN1",
-        "EventCode": "0x3C",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI1",
+        "BriefDescription": "Can't Arb for VN1; NCS on BL",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CBox AD Credits Empty; VNA Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x22",
-        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA",
+        "BriefDescription": "Can't Arb for VN1; RSP on BL",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CBox AD Credits Empty; Writebacks",
-        "Counter": "0,1,2",
-        "EventCode": "0x22",
-        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB",
+        "BriefDescription": "Can't Arb for VN1; WB on BL",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CBox AD Credits Empty; Requests",
-        "Counter": "0,1,2",
-        "EventCode": "0x22",
-        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ",
+        "BriefDescription": "No Credits to Arb for VN0; REQ on AD",
+        "EventCode": "0x47",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CBox AD Credits Empty; Snoops",
-        "Counter": "0,1,2",
-        "EventCode": "0x22",
-        "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP",
+        "BriefDescription": "No Credits to Arb for VN0; RSP on AD",
+        "EventCode": "0x47",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Number of uclks in domain",
-        "Counter": "0,1,2",
-        "EventCode": "0x1",
-        "EventName": "UNC_M3UPI_CLOCKTICKS",
+        "BriefDescription": "No Credits to Arb for VN0; SNP on AD",
+        "EventCode": "0x47",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_SNP",
         "PerPkg": "1",
+        "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "D2U Sent",
-        "Counter": "0,1,2",
-        "EventCode": "0x2A",
-        "EventName": "UNC_M3UPI_D2U_SENT",
+        "BriefDescription": "No Credits to Arb for VN0; NCB on BL",
+        "EventCode": "0x47",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCB",
         "PerPkg": "1",
+        "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2 BL Credits Empty; IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)",
-        "Counter": "0,1,2",
-        "EventCode": "0x23",
-        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO0_IIO1_NCB",
+        "BriefDescription": "No Credits to Arb for VN0; NCS on BL",
+        "EventCode": "0x47",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2 BL Credits Empty; IIO2",
-        "Counter": "0,1,2",
-        "EventCode": "0x23",
-        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB",
+        "BriefDescription": "No Credits to Arb for VN0; RSP on BL",
+        "EventCode": "0x47",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2 BL Credits Empty; IIO3",
-        "Counter": "0,1,2",
-        "EventCode": "0x23",
-        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB",
+        "BriefDescription": "No Credits to Arb for VN0; WB on BL",
+        "EventCode": "0x47",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2 BL Credits Empty; IIO4",
-        "Counter": "0,1,2",
-        "EventCode": "0x23",
-        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB",
+        "BriefDescription": "No Credits to Arb for VN1; REQ on AD",
+        "EventCode": "0x48",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2 BL Credits Empty; IIO5",
-        "Counter": "0,1,2",
-        "EventCode": "0x23",
-        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB",
+        "BriefDescription": "No Credits to Arb for VN1; RSP on AD",
+        "EventCode": "0x48",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2 BL Credits Empty; All IIO targets for NCS are in single mask. ORs them together",
-        "Counter": "0,1,2",
-        "EventCode": "0x23",
-        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS",
+        "BriefDescription": "No Credits to Arb for VN1; SNP on AD",
+        "EventCode": "0x48",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "M2 BL Credits Empty; Selected M2p BL NCS credits",
-        "Counter": "0,1,2",
-        "EventCode": "0x23",
-        "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL",
+        "BriefDescription": "No Credits to Arb for VN1; NCB on BL",
+        "EventCode": "0x48",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Multi Slot Flit Received; AD - Slot 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x3E",
-        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0",
+        "BriefDescription": "No Credits to Arb for VN1; NCS on BL",
+        "EventCode": "0x48",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Multi Slot Flit Received; AD - Slot 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x3E",
-        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1",
+        "BriefDescription": "No Credits to Arb for VN1; RSP on BL",
+        "EventCode": "0x48",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Multi Slot Flit Received; AD - Slot 2",
-        "Counter": "0,1,2",
-        "EventCode": "0x3E",
-        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2",
+        "BriefDescription": "No Credits to Arb for VN1; WB on BL",
+        "EventCode": "0x48",
+        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Multi Slot Flit Received; BL - Slot 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x3E",
-        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0",
+        "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on BL Arb",
+        "EventCode": "0x40",
+        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while bl message is in arbitration",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Multi Slot Flit Received; AK - Slot 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x3E",
-        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0",
+        "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on Idle",
+        "EventCode": "0x40",
+        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while pipeline is idle",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Multi Slot Flit Received; AK - Slot 2",
-        "Counter": "0,1,2",
-        "EventCode": "0x3E",
-        "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2",
+        "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 1",
+        "EventCode": "0x40",
+        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 1 while merging with bl message in same flit",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for AD; VN0 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ",
+        "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 2",
+        "EventCode": "0x40",
+        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 2 while merging with bl message in same flit",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for AD; VN0 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP",
+        "BriefDescription": "VN0 message lost contest for flit; REQ on AD",
+        "EventCode": "0x50",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for AD; VN0 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP",
+        "BriefDescription": "VN0 message lost contest for flit; RSP on AD",
+        "EventCode": "0x50",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for AD; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB",
+        "BriefDescription": "VN0 message lost contest for flit; SNP on AD",
+        "EventCode": "0x50",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for AD; VN1 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ",
+        "BriefDescription": "VN0 message lost contest for flit; NCB on BL",
+        "EventCode": "0x50",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for AD; VN1 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP",
+        "BriefDescription": "VN0 message lost contest for flit; NCS on BL",
+        "EventCode": "0x50",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for AD; VN1 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP",
+        "BriefDescription": "VN0 message lost contest for flit; RSP on BL",
+        "EventCode": "0x50",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for AD; VN1 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x30",
-        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB",
+        "BriefDescription": "VN0 message lost contest for flit; WB on BL",
+        "EventCode": "0x50",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD FlowQ Bypass",
-        "Counter": "0,1,2",
-        "EventCode": "0x2C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0",
+        "BriefDescription": "VN1 message lost contest for flit; REQ on AD",
+        "EventCode": "0x51",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD FlowQ Bypass",
-        "Counter": "0,1,2",
-        "EventCode": "0x2C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1",
+        "BriefDescription": "VN1 message lost contest for flit; RSP on AD",
+        "EventCode": "0x51",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD FlowQ Bypass",
-        "Counter": "0,1,2",
-        "EventCode": "0x2C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2",
+        "BriefDescription": "VN1 message lost contest for flit; SNP on AD",
+        "EventCode": "0x51",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD FlowQ Bypass",
-        "Counter": "0,1,2",
-        "EventCode": "0x2C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP",
+        "BriefDescription": "VN1 message lost contest for flit; NCB on BL",
+        "EventCode": "0x51",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty; VN0 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ",
+        "BriefDescription": "VN1 message lost contest for flit; NCS on BL",
+        "EventCode": "0x51",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty; VN0 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP",
+        "BriefDescription": "VN1 message lost contest for flit; RSP on BL",
+        "EventCode": "0x51",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty; VN0 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP",
+        "BriefDescription": "VN1 message lost contest for flit; WB on BL",
+        "EventCode": "0x51",
+        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB",
+        "BriefDescription": "Miscellaneous Credit Events; Any In BGF FIFO",
+        "EventCode": "0x60",
+        "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Indication that at least one packet (flit) is in the bgf (fifo only)",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty; VN1 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ",
+        "BriefDescription": "Miscellaneous Credit Events; Any in BGF Path",
+        "EventCode": "0x60",
+        "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo)",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty; VN1 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP",
+        "BriefDescription": "Miscellaneous Credit Events; No D2K For Arb",
+        "EventCode": "0x60",
+        "EventName": "UNC_M3UPI_RxC_CRD_MISC.NO_D2K_FOR_ARB",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "VN0 or VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty; VN1 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP",
+        "BriefDescription": "Credit Occupancy; D2K Credits",
+        "EventCode": "0x61",
+        "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "D2K completion fifo credit occupancy (credits in use), accumulated across all cycles",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Not Empty; VN1 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x27",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB",
+        "BriefDescription": "Credit Occupancy; Packets in BGF FIFO",
+        "EventCode": "0x61",
+        "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Occupancy of m3upi ingress -&gt; upi link layer bgf; packets (flits) in fifo",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Inserts; VN0 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ",
+        "BriefDescription": "Credit Occupancy; Packets in BGF Path",
+        "EventCode": "0x61",
+        "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Occupancy of m3upi ingress -&gt; upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo)",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Inserts; VN0 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP",
+        "BriefDescription": "Credit Occupancy",
+        "EventCode": "0x61",
+        "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "count of bl messages in pump-1-pending state, in completion fifo only",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Inserts; VN0 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP",
+        "BriefDescription": "Credit Occupancy",
+        "EventCode": "0x61",
+        "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "count of bl messages in pump-1-pending state, in marker table and in fifo",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Inserts; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB",
+        "BriefDescription": "Credit Occupancy; Transmit Credits",
+        "EventCode": "0x61",
+        "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Inserts; VN1 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ",
+        "BriefDescription": "Credit Occupancy; VNA In Use",
+        "EventCode": "0x61",
+        "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Inserts; VN1 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD",
+        "EventCode": "0x43",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Inserts; VN1 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2D",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD",
+        "EventCode": "0x43",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Occupancy; VN0 REQ Messages",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD",
+        "EventCode": "0x43",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Occupancy; VN0 SNP Messages",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL",
+        "EventCode": "0x43",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Occupancy; VN0 RSP Messages",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL",
+        "EventCode": "0x43",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Occupancy; VN0 WB Messages",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL",
+        "EventCode": "0x43",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Occupancy; VN1 REQ Messages",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL",
+        "EventCode": "0x43",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Occupancy; VN1 SNP Messages",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD",
+        "EventCode": "0x44",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AD Flow Q Occupancy; VN1 RSP Messages",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD",
+        "EventCode": "0x44",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN0 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x34",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_REQ",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD",
+        "EventCode": "0x44",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN0 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x34",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_SNP",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL",
+        "EventCode": "0x44",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x34",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_WB",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL",
+        "EventCode": "0x44",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN1 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x34",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_REQ",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL",
+        "EventCode": "0x44",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN1 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x34",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_SNP",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL",
+        "EventCode": "0x44",
+        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN1 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x34",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_WB",
+        "BriefDescription": "Data Flit Not Sent; All",
+        "EventCode": "0x57",
+        "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.ALL",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Data flit is ready for transmission but could not be sent",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - New Message; VN0 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x33",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_REQ",
+        "BriefDescription": "Data Flit Not Sent; No BGF Credits",
+        "EventCode": "0x57",
+        "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_BGF",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Data flit is ready for transmission but could not be sent",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - New Message; VN0 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x33",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_SNP",
+        "BriefDescription": "Data Flit Not Sent; No TxQ Credits",
+        "EventCode": "0x57",
+        "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_TXQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Data flit is ready for transmission but could not be sent",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - New Message; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x33",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_WB",
+        "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 0",
+        "EventCode": "0x59",
+        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "generating bl data flit sequence; waiting for data pump 0",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - New Message; VN1 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x33",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_REQ",
+        "BriefDescription": "Generating BL Data Flit Sequence",
+        "EventCode": "0x59",
+        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT",
         "PerPkg": "1",
+        "PublicDescription": "pump-1-pending logic is at capacity (pending table plus completion fifo at limit)",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - New Message; VN1 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x33",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_SNP",
+        "BriefDescription": "Generating BL Data Flit Sequence",
+        "EventCode": "0x59",
+        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "pump-1-pending logic is tracking at least one message",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - New Message; VN1 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x33",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_WB",
+        "BriefDescription": "Generating BL Data Flit Sequence",
+        "EventCode": "0x59",
+        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "pump-1-pending completion fifo is full",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - No Credit; VN0 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x32",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_REQ",
+        "BriefDescription": "Generating BL Data Flit Sequence",
+        "EventCode": "0x59",
+        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - No Credit; VN0 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x32",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_SNP",
+        "BriefDescription": "Generating BL Data Flit Sequence",
+        "EventCode": "0x59",
+        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "a bl message finished but is in limbo and moved to pump-1-pending logic",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - No Credit; VN0 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x32",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_RSP",
+        "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 1",
+        "EventCode": "0x59",
+        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "generating bl data flit sequence; waiting for data pump 1",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - No Credit; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x32",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_WB",
+        "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC",
+        "EventCode": "0x5A",
+        "EventName": "UNC_M3UPI_RxC_FLITS_MISC",
         "PerPkg": "1",
-        "UMask": "0x08",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - No Credit; VN1 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x32",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_REQ",
+        "BriefDescription": "Sent Header Flit; One Message",
+        "EventCode": "0x56",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "One message in flit; VNA or non-VNA flit",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - No Credit; VN1 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x32",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_SNP",
+        "BriefDescription": "Sent Header Flit; One Message in non-VNA",
+        "EventCode": "0x56",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG_VNX",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "One message in flit; non-VNA flit",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - No Credit; VN1 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x32",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_RSP",
+        "BriefDescription": "Sent Header Flit; Two Messages",
+        "EventCode": "0x56",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.2_MSGS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Two messages in flit; VNA flit",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD  - No Credit; VN1 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x32",
-        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_WB",
+        "BriefDescription": "Sent Header Flit; Three Messages",
+        "EventCode": "0x56",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.3_MSGS",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Three messages in flit; VNA flit",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Flow Q Inserts",
-        "Counter": "0,1,2",
-        "EventCode": "0x2F",
-        "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS",
+        "BriefDescription": "Sent Header Flit",
+        "EventCode": "0x56",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_1",
         "PerPkg": "1",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "AK Flow Q Occupancy",
-        "EventCode": "0x1E",
-        "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY",
+        "BriefDescription": "Sent Header Flit",
+        "EventCode": "0x56",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_2",
         "PerPkg": "1",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for BL; VN0 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP",
+        "BriefDescription": "Sent Header Flit",
+        "EventCode": "0x56",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_3",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for BL; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB",
+        "BriefDescription": "Slotting BL Message Into Header Flit; All",
+        "EventCode": "0x58",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for BL; VN0 NCB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB",
+        "BriefDescription": "Slotting BL Message Into Header Flit; Needs Data Flit",
+        "EventCode": "0x58",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "BL message requires data flit sequence",
+        "UMask": "0x2",
         "Unit": "M3UPI"
-    },
-    {
-        "BriefDescription": "Failed ARB for BL; VN0 NCS Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS",
+    },
+    {
+        "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 0",
+        "EventCode": "0x58",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Waiting for header pump 0",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for BL; VN1 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP",
+        "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1",
+        "EventCode": "0x58",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ",
         "PerPkg": "1",
+        "PublicDescription": "Header pump 1 is not required for flit",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for BL; VN1 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB",
+        "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Bubble",
+        "EventCode": "0x58",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE",
         "PerPkg": "1",
+        "PublicDescription": "Header pump 1 is not required for flit but flit transmission delayed",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for BL; VN1 NCS Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB",
+        "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Not Avail",
+        "EventCode": "0x58",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL",
         "PerPkg": "1",
+        "PublicDescription": "Header pump 1 is not required for flit and not available",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Failed ARB for BL; VN1 NCB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x35",
-        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS",
+        "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 1",
+        "EventCode": "0x58",
+        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Waiting for header pump 1",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty; VN0 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ",
+        "BriefDescription": "Flit Gen - Header 1; Acumullate",
+        "EventCode": "0x53",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty; VN0 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP",
+        "BriefDescription": "Flit Gen - Header 1; Accumulate Ready",
+        "EventCode": "0x53",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Events related to Header Flit Generation - Set 1; header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty; VN0 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP",
+        "BriefDescription": "Flit Gen - Header 1; Accumulate Wasted",
+        "EventCode": "0x53",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Events related to Header Flit Generation - Set 1; Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB",
+        "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Blocked",
+        "EventCode": "0x53",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty; VN1 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ",
+        "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Message",
+        "EventCode": "0x53",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG",
         "PerPkg": "1",
+        "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting is in run-ahead to start new flit, and message is actually slotted into new flit",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty; VN1 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP",
+        "BriefDescription": "Flit Gen - Header 1; Parallel Ok",
+        "EventCode": "0x53",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR",
         "PerPkg": "1",
+        "PublicDescription": "Events related to Header Flit Generation - Set 1; New header flit construction may proceed in parallel with data flit sequence",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty; VN1 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP",
+        "BriefDescription": "Flit Gen - Header 1; Parallel Flit Finished",
+        "EventCode": "0x53",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_FLIT",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit finished assembly in parallel with data flit sequence",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Not Empty; VN1 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x28",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB",
+        "BriefDescription": "Flit Gen - Header 1; Parallel Message",
+        "EventCode": "0x53",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_MSG",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Events related to Header Flit Generation - Set 1; Message is slotted into header flit in parallel with data flit sequence",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts; VN0 NCS Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP",
+        "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall",
+        "EventCode": "0x54",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Events related to Header Flit Generation - Set 2; Rate-matching stall injected",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts; VN0 NCB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB",
+        "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall - No Message",
+        "EventCode": "0x54",
+        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Events related to Header Flit Generation - Set 2; Rate matching stall injected, but no additional message slotted during stall cycle",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts; VN0 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB",
+        "BriefDescription": "Header Not Sent; All",
+        "EventCode": "0x55",
+        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "header flit is ready for transmission but could not be sent",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS",
+        "BriefDescription": "Header Not Sent; No BGF Credits",
+        "EventCode": "0x55",
+        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "header flit is ready for transmission but could not be sent; No BGF credits available",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts; VN1_NCB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP",
+        "BriefDescription": "Header Not Sent; No BGF Credits + No Extra Message Slotted",
+        "EventCode": "0x55",
+        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_NO_MSG",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "header flit is ready for transmission but could not be sent; No BGF credits available; no additional message slotted into flit",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts; VN1_NCS Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB",
+        "BriefDescription": "Header Not Sent; No TxQ Credits",
+        "EventCode": "0x55",
+        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_CRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "header flit is ready for transmission but could not be sent; No TxQ credits available",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts; VN1 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB",
+        "BriefDescription": "Header Not Sent; No TxQ Credits + No Extra Message Slotted",
+        "EventCode": "0x55",
+        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_NO_MSG",
         "PerPkg": "1",
+        "PublicDescription": "header flit is ready for transmission but could not be sent; No TxQ credits available; no additional message slotted into flit",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Inserts; VN1 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x2E",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS",
+        "BriefDescription": "Header Not Sent; Sent - One Slot Taken",
+        "EventCode": "0x55",
+        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ONE_TAKEN",
         "PerPkg": "1",
+        "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with only one slot taken (two slots free)",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy; VN0 RSP Messages",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP",
+        "BriefDescription": "Header Not Sent; Sent - Three Slots Taken",
+        "EventCode": "0x55",
+        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.THREE_TAKEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with three slots taken (no slots free)",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy; VN0 WB Messages",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB",
+        "BriefDescription": "Header Not Sent; Sent - Two Slots Taken",
+        "EventCode": "0x55",
+        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.TWO_TAKEN",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with only two slots taken (one slots free)",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy; VN0 NCB Messages",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB",
+        "BriefDescription": "Message Held; Can't Slot AD",
+        "EventCode": "0x52",
+        "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "some AD message could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1})",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy; VN0 NCS Messages",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS",
+        "BriefDescription": "Message Held; Can't Slot BL",
+        "EventCode": "0x52",
+        "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "some BL message could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1})",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy; VN1 RSP Messages",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP",
+        "BriefDescription": "Message Held; Parallel AD Lost",
+        "EventCode": "0x52",
+        "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_AD_LOST",
         "PerPkg": "1",
+        "PublicDescription": "some AD message lost contest for slot 0 (logical OR of all AD events under INGR_SLOT_LOST_MC_VN{0,1})",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy; VN1 WB Messages",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB",
+        "BriefDescription": "Message Held; Parallel Attempt",
+        "EventCode": "0x52",
+        "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT",
+        "PerPkg": "1",
+        "PublicDescription": "ad and bl messages attempted to slot into the same flit in parallel",
+        "UMask": "0x4",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "Message Held; Parallel BL Lost",
+        "EventCode": "0x52",
+        "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_BL_LOST",
         "PerPkg": "1",
+        "PublicDescription": "some BL message lost contest for slot 0 (logical OR of all BL events under INGR_SLOT_LOST_MC_VN{0,1})",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy; VN1_NCS Messages",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB",
+        "BriefDescription": "Message Held; Parallel Success",
+        "EventCode": "0x52",
+        "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "ad and bl messages were actually slotted into the same flit in paralle",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "BL Flow Q Occupancy; VN1_NCB Messages",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS",
+        "BriefDescription": "Message Held; VN0",
+        "EventCode": "0x52",
+        "EventName": "UNC_M3UPI_RxC_HELD.VN0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "vn0 message(s) that couldn't be slotted into last vn0 flit are held in slotting stage while processing vn1 flit",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for BL  - New Message; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x38",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_WB",
+        "BriefDescription": "Message Held; VN1",
+        "EventCode": "0x52",
+        "EventName": "UNC_M3UPI_RxC_HELD.VN1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "vn1 message(s) that couldn't be slotted into last vn1 flit are held in slotting stage while processing vn0 flit",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for BL  - New Message; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x38",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCB",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; REQ on AD",
+        "EventCode": "0x41",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for BL  - New Message; VN0 NCS Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x38",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCS",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on AD",
+        "EventCode": "0x41",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for BL  - New Message; VN1 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x38",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_WB",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; SNP on AD",
+        "EventCode": "0x41",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for BL  - New Message; VN1 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x38",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCB",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCB on BL",
+        "EventCode": "0x41",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for BL  - New Message; VN1 NCB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x38",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCS",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCS on BL",
+        "EventCode": "0x41",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x37",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_RSP",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on BL",
+        "EventCode": "0x41",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x37",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_WB",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; WB on BL",
+        "EventCode": "0x41",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x37",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCB",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; REQ on AD",
+        "EventCode": "0x42",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCS Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x37",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCS",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on AD",
+        "EventCode": "0x42",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x37",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_RSP",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; SNP on AD",
+        "EventCode": "0x42",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 WB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x37",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_WB",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCB on BL",
+        "EventCode": "0x42",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCS Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x37",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCB",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCS on BL",
+        "EventCode": "0x42",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCB Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x37",
-        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCS",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on BL",
+        "EventCode": "0x42",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Credit Used; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5C",
-        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; WB on BL",
+        "EventCode": "0x42",
+        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Credit Used; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5C",
-        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; REQ on AD",
+        "EventCode": "0x45",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Credit Used; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5C",
-        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on AD",
+        "EventCode": "0x45",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Credit Used; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5C",
-        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; SNP on AD",
+        "EventCode": "0x45",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Credit Used; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5C",
-        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCB on BL",
+        "EventCode": "0x45",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Credit Used; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5C",
-        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCS on BL",
+        "EventCode": "0x45",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 No Credits; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5E",
-        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on BL",
+        "EventCode": "0x45",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 No Credits; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5E",
-        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP",
+        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; WB on BL",
+        "EventCode": "0x45",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 No Credits; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5E",
-        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; REQ on AD",
+        "EventCode": "0x46",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 No Credits; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5E",
-        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on AD",
+        "EventCode": "0x46",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 No Credits; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5E",
-        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; SNP on AD",
+        "EventCode": "0x46",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 No Credits; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5E",
-        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCB on BL",
+        "EventCode": "0x46",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB",
         "PerPkg": "1",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Credit Used; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5D",
-        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCS on BL",
+        "EventCode": "0x46",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Credit Used; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5D",
-        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on BL",
+        "EventCode": "0x46",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Credit Used; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5D",
-        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP",
+        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; WB on BL",
+        "EventCode": "0x46",
+        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Credit Used; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5D",
-        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB",
+        "BriefDescription": "VN0 message can't slot into flit; REQ on AD",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Credit Used; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5D",
-        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB",
+        "BriefDescription": "VN0 message can't slot into flit; RSP on AD",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Credit Used; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5D",
-        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS",
+        "BriefDescription": "VN0 message can't slot into flit; SNP on AD",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 No Credits; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5F",
-        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ",
+        "BriefDescription": "VN0 message can't slot into flit; NCB on BL",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 No Credits; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5F",
-        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP",
+        "BriefDescription": "VN0 message can't slot into flit; NCS on BL",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Standard (NCS) messages on BL.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 No Credits; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x5F",
-        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP",
+        "BriefDescription": "VN0 message can't slot into flit; RSP on BL",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 No Credits; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5F",
-        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB",
+        "BriefDescription": "VN0 message can't slot into flit; WB on BL",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 No Credits; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5F",
-        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB",
+        "BriefDescription": "VN1 message can't slot into flit; REQ on AD",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 No Credits; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x5F",
-        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS",
+        "BriefDescription": "VN1 message can't slot into flit; RSP on AD",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Number of Snoop Targets; CHA on VN0",
-        "EventCode": "0x3C",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_CHA",
+        "BriefDescription": "VN1 message can't slot into flit; SNP on AD",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Number of Snoop Targets; CHA on VN1",
-        "EventCode": "0x3C",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_CHA",
+        "BriefDescription": "VN1 message can't slot into flit; NCB on BL",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB",
         "PerPkg": "1",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN0",
-        "EventCode": "0x3C",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_NON_IDLE",
+        "BriefDescription": "VN1 message can't slot into flit; NCS on BL",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS",
         "PerPkg": "1",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Standard (NCS) messages on BL.",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN1",
-        "EventCode": "0x3C",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_NON_IDLE",
+        "BriefDescription": "VN1 message can't slot into flit; RSP on BL",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP",
+        "PerPkg": "1",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "VN1 message can't slot into flit; WB on BL",
+        "EventCode": "0x4F",
+        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Snoop Arbitration; FlowQ Won",
-        "Counter": "0,1,2",
-        "EventCode": "0x3D",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_NONSNP",
+        "BriefDescription": "SMI3 Prefetch Messages; Lost Arbitration",
+        "EventCode": "0x62",
+        "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARB_LOST",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Snoop Arbitration; FlowQ Won",
-        "Counter": "0,1,2",
-        "EventCode": "0x3D",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_NONSNP",
+        "BriefDescription": "SMI3 Prefetch Messages; Arrived",
+        "EventCode": "0x62",
+        "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARRIVED",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won",
-        "Counter": "0,1,2",
-        "EventCode": "0x3D",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_VN2SNP",
+        "BriefDescription": "SMI3 Prefetch Messages; Dropped - Old",
+        "EventCode": "0x62",
+        "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_OLD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won",
-        "Counter": "0,1,2",
-        "EventCode": "0x3D",
-        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_VN0SNP",
+        "BriefDescription": "SMI3 Prefetch Messages; Dropped - Wrap",
+        "EventCode": "0x62",
+        "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_WRAP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Dropped because it was overwritten by new message while prefetch queue was full",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x80",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR0",
+        "BriefDescription": "SMI3 Prefetch Messages; Slotted",
+        "EventCode": "0x62",
+        "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.SLOTTED",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x80",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR1",
+        "BriefDescription": "Remote VNA Credits; Any In Use",
+        "EventCode": "0x5B",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "At least one remote vna credit is in use",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2",
-        "EventCode": "0x80",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR2",
+        "BriefDescription": "Remote VNA Credits; Corrected",
+        "EventCode": "0x5B",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of remote vna credits corrected (local return) per cycle",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2",
-        "EventCode": "0x80",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR3",
+        "BriefDescription": "Remote VNA Credits; Level &lt; 1",
+        "EventCode": "0x5B",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Remote vna credit level is less than 1 (i.e. no vna credits available)",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2",
-        "EventCode": "0x80",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR4",
+        "BriefDescription": "Remote VNA Credits; Level &lt; 4",
+        "EventCode": "0x5B",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2",
-        "EventCode": "0x80",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR5",
+        "BriefDescription": "Remote VNA Credits; Level &lt; 5",
+        "EventCode": "0x5B",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x82",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR0",
+        "BriefDescription": "Remote VNA Credits; Used",
+        "EventCode": "0x5B",
+        "EventName": "UNC_M3UPI_RxC_VNA_CRD.USED",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of remote vna credits consumed per cycle",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x82",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
-        "Counter": "0,1,2",
-        "EventCode": "0x82",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
-        "Counter": "0,1,2",
-        "EventCode": "0x82",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
-        "Counter": "0,1,2",
-        "EventCode": "0x82",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
-        "Counter": "0,1,2",
-        "EventCode": "0x82",
-        "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR5",
+        "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M3UPI_RxR_BYPASS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x88",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR0",
+        "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x88",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR1",
+        "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M3UPI_RxR_BYPASS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2",
-        "EventCode": "0x88",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR2",
+        "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M3UPI_RxR_BYPASS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2",
-        "EventCode": "0x88",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR3",
+        "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2",
-        "EventCode": "0x88",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR4",
+        "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M3UPI_RxR_BYPASS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of packets bypassing the CMS Ingress",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2",
-        "EventCode": "0x88",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR5",
+        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR0",
+        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
-        "Counter": "0,1,2",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
-        "Counter": "0,1,2",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
-        "Counter": "0,1,2",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
-        "Counter": "0,1,2",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR5",
+        "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x84",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR0",
+        "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M3UPI_RxR_INSERTS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x84",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR1",
+        "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2",
-        "EventCode": "0x84",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR2",
+        "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M3UPI_RxR_INSERTS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2",
-        "EventCode": "0x84",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR3",
+        "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M3UPI_RxR_INSERTS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2",
-        "EventCode": "0x84",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR4",
+        "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2",
-        "EventCode": "0x84",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR5",
+        "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M3UPI_RxR_INSERTS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x86",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR0",
+        "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x86",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
-        "Counter": "0,1,2",
-        "EventCode": "0x86",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
-        "Counter": "0,1,2",
-        "EventCode": "0x86",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
-        "Counter": "0,1,2",
-        "EventCode": "0x86",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
-        "Counter": "0,1,2",
-        "EventCode": "0x86",
-        "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR5",
+        "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR0",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR1",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR2",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR3",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR4",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR5",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD0",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR0",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR1",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
-        "Counter": "0,1,2",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR2",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
-        "Counter": "0,1,2",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR3",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
-        "Counter": "0,1,2",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR4",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
-        "Counter": "0,1,2",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR5",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD2",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "CMS Clockticks",
-        "Counter": "0,1,2",
-        "EventCode": "0xC0",
-        "EventName": "UNC_M3UPI_CMS_CLOCKTICKS",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
-        "Counter": "0,1,2",
-        "EventCode": "0xAE",
-        "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
-        "Counter": "0,1,2",
-        "EventCode": "0xAE",
-        "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xA9",
-        "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xA9",
-        "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xA9",
-        "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xA9",
-        "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD",
+        "BriefDescription": "Failed ARB for AD; VN0 REQ Messages",
+        "EventCode": "0x30",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "AD arb but no win; arb request asserted but not won",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Failed ARB for AD; VN0 RSP Messages",
+        "EventCode": "0x30",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "AD arb but no win; arb request asserted but not won",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Failed ARB for AD; VN0 SNP Messages",
+        "EventCode": "0x30",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "AD arb but no win; arb request asserted but not won",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use; Left",
-        "Counter": "0,1,2",
-        "EventCode": "0xAD",
-        "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT",
+        "BriefDescription": "Failed ARB for AD; VN0 WB Messages",
+        "EventCode": "0x30",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "AD arb but no win; arb request asserted but not won",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use; Right",
-        "Counter": "0,1,2",
-        "EventCode": "0xAD",
-        "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT",
+        "BriefDescription": "Failed ARB for AD; VN1 REQ Messages",
+        "EventCode": "0x30",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "AD arb but no win; arb request asserted but not won",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
-        "Counter": "0,1,2",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD",
+        "BriefDescription": "Failed ARB for AD; VN1 RSP Messages",
+        "EventCode": "0x30",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "AD arb but no win; arb request asserted but not won",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
-        "Counter": "0,1,2",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK",
+        "BriefDescription": "Failed ARB for AD; VN1 SNP Messages",
+        "EventCode": "0x30",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP",
+        "PerPkg": "1",
+        "PublicDescription": "AD arb but no win; arb request asserted but not won",
+        "UMask": "0x20",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "Failed ARB for AD; VN1 WB Messages",
+        "EventCode": "0x30",
+        "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "AD arb but no win; arb request asserted but not won",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
-        "Counter": "0,1,2",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL",
+        "BriefDescription": "AD FlowQ Bypass",
+        "EventCode": "0x2C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
-        "Counter": "0,1,2",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV",
+        "BriefDescription": "AD FlowQ Bypass",
+        "EventCode": "0x2C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
-        "Counter": "0,1,2",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD",
+        "BriefDescription": "AD FlowQ Bypass",
+        "EventCode": "0x2C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
-        "Counter": "0,1,2",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK",
+        "BriefDescription": "AD FlowQ Bypass",
+        "EventCode": "0x2C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
-        "Counter": "0,1,2",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL",
+        "BriefDescription": "AD Flow Q Not Empty; VN0 REQ Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache",
-        "Counter": "0,1,2",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV",
+        "BriefDescription": "AD Flow Q Not Empty; VN0 RSP Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
-        "Counter": "0,1,2",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD",
+        "BriefDescription": "AD Flow Q Not Empty; VN0 SNP Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
-        "Counter": "0,1,2",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK",
+        "BriefDescription": "AD Flow Q Not Empty; VN0 WB Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
-        "Counter": "0,1,2",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL",
+        "BriefDescription": "AD Flow Q Not Empty; VN1 REQ Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
-        "Counter": "0,1,2",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV",
+        "BriefDescription": "AD Flow Q Not Empty; VN1 RSP Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1",
+        "BriefDescription": "AD Flow Q Not Empty; VN1 SNP Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; AD",
-        "Counter": "0,1,2",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD",
+        "BriefDescription": "AD Flow Q Not Empty; VN1 WB Messages",
+        "EventCode": "0x27",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
-        "Counter": "0,1,2",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK",
+        "BriefDescription": "AD Flow Q Inserts; VN0 REQ Messages",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
-        "Counter": "0,1,2",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL",
+        "BriefDescription": "AD Flow Q Inserts; VN0 RSP Messages",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache",
-        "Counter": "0,1,2",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV",
+        "BriefDescription": "AD Flow Q Inserts; VN0 SNP Messages",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Source Throttle",
-        "Counter": "0,1,2",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M3UPI_RING_SRC_THRTL",
+        "BriefDescription": "AD Flow Q Inserts; VN0 WB Messages",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN0; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ",
+        "BriefDescription": "AD Flow Q Inserts; VN1 REQ Messages",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN0; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP",
+        "BriefDescription": "AD Flow Q Inserts; VN1 RSP Messages",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN0; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP",
+        "BriefDescription": "AD Flow Q Inserts; VN1 SNP Messages",
+        "EventCode": "0x2D",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN0; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP",
+        "BriefDescription": "AD Flow Q Occupancy; VN0 REQ Messages",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN0; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB",
+        "BriefDescription": "AD Flow Q Occupancy; VN0 RSP Messages",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN0; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB",
+        "BriefDescription": "AD Flow Q Occupancy; VN0 SNP Messages",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN0; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS",
+        "BriefDescription": "AD Flow Q Occupancy; VN0 WB Messages",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN1; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ",
+        "BriefDescription": "AD Flow Q Occupancy; VN1 REQ Messages",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN1; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP",
+        "BriefDescription": "AD Flow Q Occupancy; VN1 RSP Messages",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN1; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP",
+        "BriefDescription": "AD Flow Q Occupancy; VN1 SNP Messages",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN1; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP",
+        "BriefDescription": "Number of Snoop Targets; CHA on VN0",
+        "EventCode": "0x3C",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_CHA",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to CHA",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN1; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB",
+        "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN0",
+        "EventCode": "0x3C",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_NON_IDLE",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of non-idle cycles in issuing Vn0 Snpf",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN1; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB",
+        "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN0",
+        "EventCode": "0x3C",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to peer UPI0",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Lost Arb for VN1; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS",
+        "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN0",
+        "EventCode": "0x3C",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to peer UPI1",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN0",
-        "Counter": "0,1,2",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN0",
+        "BriefDescription": "Number of Snoop Targets; CHA on VN1",
+        "EventCode": "0x3C",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_CHA",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to CHA",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN1",
-        "Counter": "0,1,2",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN1",
+        "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN1",
+        "EventCode": "0x3C",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_NON_IDLE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of non-idle cycles in issuing Vn1 Snpf",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN0",
-        "Counter": "0,1,2",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0",
+        "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN1",
+        "EventCode": "0x3C",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to peer UPI0",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN1",
-        "Counter": "0,1,2",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1",
+        "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN1",
+        "EventCode": "0x3C",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to peer UPI1",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN0",
-        "Counter": "0,1,2",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0",
+        "BriefDescription": "Snoop Arbitration; FlowQ Won",
+        "EventCode": "0x3D",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_NONSNP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn0",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN1",
-        "Counter": "0,1,2",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1",
+        "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won",
+        "EventCode": "0x3D",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_VN2SNP",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ Vn0 SnpF issued when SnpF pending on Vn1",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Arb Miscellaneous; AD, BL Parallel Win",
-        "Counter": "0,1,2",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN",
+        "BriefDescription": "Snoop Arbitration; FlowQ Won",
+        "EventCode": "0x3D",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_NONSNP",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn1",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN0; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x49",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_REQ",
+        "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won",
+        "EventCode": "0x3D",
+        "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_VN0SNP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ Vn1 SnpF issued when SnpF pending on Vn0",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN0; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x49",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_SNP",
+        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN0 REQ Messages",
+        "EventCode": "0x34",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_REQ",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN0; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x49",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_RSP",
+        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN0 SNP Messages",
+        "EventCode": "0x34",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_SNP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN0; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x49",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_RSP",
+        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN0 WB Messages",
+        "EventCode": "0x34",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN0; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x49",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_WB",
+        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN1 REQ Messages",
+        "EventCode": "0x34",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_REQ",
         "PerPkg": "1",
+        "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN0; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x49",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCB",
+        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN1 SNP Messages",
+        "EventCode": "0x34",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_SNP",
         "PerPkg": "1",
+        "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN0; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x49",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCS",
+        "BriefDescription": "Speculative ARB for AD  -  Credit Available; VN1 WB Messages",
+        "EventCode": "0x34",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_WB",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN1; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_REQ",
+        "BriefDescription": "Speculative ARB for AD  - New Message; VN0 REQ Messages",
+        "EventCode": "0x33",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_REQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN1; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_SNP",
+        "BriefDescription": "Speculative ARB for AD  - New Message; VN0 SNP Messages",
+        "EventCode": "0x33",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_SNP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN1; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_RSP",
+        "BriefDescription": "Speculative ARB for AD  - New Message; VN0 WB Messages",
+        "EventCode": "0x33",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN1; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_RSP",
+        "BriefDescription": "Speculative ARB for AD  - New Message; VN1 REQ Messages",
+        "EventCode": "0x33",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_REQ",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN1; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_WB",
+        "BriefDescription": "Speculative ARB for AD  - New Message; VN1 SNP Messages",
+        "EventCode": "0x33",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_SNP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN1; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCB",
+        "BriefDescription": "Speculative ARB for AD  - New Message; VN1 WB Messages",
+        "EventCode": "0x33",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_WB",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Can't Arb for VN1; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCS",
+        "BriefDescription": "Speculative ARB for AD  - No Credit; VN0 REQ Messages",
+        "EventCode": "0x32",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_REQ",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN0; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x47",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_REQ",
+        "BriefDescription": "Speculative ARB for AD  - No Credit; VN0 RSP Messages",
+        "EventCode": "0x32",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN0; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x47",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_SNP",
+        "BriefDescription": "Speculative ARB for AD  - No Credit; VN0 SNP Messages",
+        "EventCode": "0x32",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_SNP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN0; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x47",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_RSP",
+        "BriefDescription": "Speculative ARB for AD  - No Credit; VN0 WB Messages",
+        "EventCode": "0x32",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN0; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x47",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_RSP",
+        "BriefDescription": "Speculative ARB for AD  - No Credit; VN1 REQ Messages",
+        "EventCode": "0x32",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_REQ",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN0; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x47",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_WB",
+        "BriefDescription": "Speculative ARB for AD  - No Credit; VN1 RSP Messages",
+        "EventCode": "0x32",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_RSP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN0; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x47",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCB",
+        "BriefDescription": "Speculative ARB for AD  - No Credit; VN1 SNP Messages",
+        "EventCode": "0x32",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_SNP",
         "PerPkg": "1",
+        "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN0; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x47",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCS",
+        "BriefDescription": "Speculative ARB for AD  - No Credit; VN1 WB Messages",
+        "EventCode": "0x32",
+        "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_WB",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN1; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x48",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_REQ",
+        "BriefDescription": "AK Flow Q Inserts",
+        "EventCode": "0x2F",
+        "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x01",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN1; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x48",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_SNP",
+        "BriefDescription": "AK Flow Q Occupancy",
+        "EventCode": "0x1E",
+        "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x02",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN1; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x48",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_RSP",
+        "BriefDescription": "Failed ARB for BL; VN0 NCB Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "BL arb but no win; arb request asserted but not won",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN1; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x48",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_RSP",
+        "BriefDescription": "Failed ARB for BL; VN0 NCS Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "BL arb but no win; arb request asserted but not won",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN1; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x48",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_WB",
+        "BriefDescription": "Failed ARB for BL; VN0 RSP Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "BL arb but no win; arb request asserted but not won",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN1; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x48",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCB",
+        "BriefDescription": "Failed ARB for BL; VN0 WB Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "BL arb but no win; arb request asserted but not won",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "No Credits to Arb for VN1; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x48",
-        "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCS",
+        "BriefDescription": "Failed ARB for BL; VN1 NCS Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB",
         "PerPkg": "1",
+        "PublicDescription": "BL arb but no win; arb request asserted but not won",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on Idle",
-        "Counter": "0,1,2",
-        "EventCode": "0x40",
-        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE",
+        "BriefDescription": "Failed ARB for BL; VN1 NCB Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "BL arb but no win; arb request asserted but not won",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on BL Arb",
-        "Counter": "0,1,2",
-        "EventCode": "0x40",
-        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB",
+        "BriefDescription": "Failed ARB for BL; VN1 RSP Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "BL arb but no win; arb request asserted but not won",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x40",
-        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT",
+        "BriefDescription": "Failed ARB for BL; VN1 WB Messages",
+        "EventCode": "0x35",
+        "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "BL arb but no win; arb request asserted but not won",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 2",
-        "Counter": "0,1,2",
-        "EventCode": "0x40",
-        "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT",
+        "BriefDescription": "BL Flow Q Not Empty; VN0 REQ Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message lost contest for flit; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x50",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_REQ",
+        "BriefDescription": "BL Flow Q Not Empty; VN0 RSP Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message lost contest for flit; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x50",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_SNP",
+        "BriefDescription": "BL Flow Q Not Empty; VN0 SNP Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message lost contest for flit; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x50",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_RSP",
+        "BriefDescription": "BL Flow Q Not Empty; VN0 WB Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message lost contest for flit; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x50",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_RSP",
+        "BriefDescription": "BL Flow Q Not Empty; VN1 REQ Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message lost contest for flit; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x50",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_WB",
+        "BriefDescription": "BL Flow Q Not Empty; VN1 RSP Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message lost contest for flit; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x50",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCB",
+        "BriefDescription": "BL Flow Q Not Empty; VN1 SNP Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message lost contest for flit; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x50",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCS",
+        "BriefDescription": "BL Flow Q Not Empty; VN1 WB Messages",
+        "EventCode": "0x28",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message lost contest for flit; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x51",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_REQ",
+        "BriefDescription": "BL Flow Q Inserts; VN0 RSP Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message lost contest for flit; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x51",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_SNP",
+        "BriefDescription": "BL Flow Q Inserts; VN0 WB Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message lost contest for flit; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x51",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_RSP",
+        "BriefDescription": "BL Flow Q Inserts; VN0 NCS Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message lost contest for flit; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x51",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_RSP",
+        "BriefDescription": "BL Flow Q Inserts; VN0 NCB Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message lost contest for flit; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x51",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_WB",
+        "BriefDescription": "BL Flow Q Inserts; VN1 RSP Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message lost contest for flit; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x51",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCB",
+        "BriefDescription": "BL Flow Q Inserts; VN1 WB Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message lost contest for flit; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x51",
-        "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCS",
+        "BriefDescription": "BL Flow Q Inserts; VN1_NCB Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Miscellaneous Credit Events; Any In BGF FIFO",
-        "Counter": "0,1,2",
-        "EventCode": "0x60",
-        "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO",
+        "BriefDescription": "BL Flow Q Inserts; VN1_NCS Messages",
+        "EventCode": "0x2E",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Miscellaneous Credit Events; Any in BGF Path",
-        "Counter": "0,1,2",
-        "EventCode": "0x60",
-        "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH",
+        "BriefDescription": "BL Flow Q Occupancy; VN0 NCB Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Miscellaneous Credit Events; No D2K For Arb",
-        "Counter": "0,1,2",
-        "EventCode": "0x60",
-        "EventName": "UNC_M3UPI_RxC_CRD_MISC.NO_D2K_FOR_ARB",
+        "BriefDescription": "BL Flow Q Occupancy; VN0 NCS Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Credit Occupancy; VNA In Use",
-        "Counter": "0,1,2",
-        "EventCode": "0x61",
-        "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE",
+        "BriefDescription": "BL Flow Q Occupancy; VN0 RSP Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Credit Occupancy; Packets in BGF FIFO",
-        "Counter": "0,1,2",
-        "EventCode": "0x61",
-        "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO",
+        "BriefDescription": "BL Flow Q Occupancy; VN0 WB Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Credit Occupancy; Packets in BGF Path",
-        "Counter": "0,1,2",
-        "EventCode": "0x61",
-        "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH",
+        "BriefDescription": "BL Flow Q Occupancy; VN1_NCS Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Credit Occupancy; Transmit Credits",
-        "Counter": "0,1,2",
-        "EventCode": "0x61",
-        "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD",
+        "BriefDescription": "BL Flow Q Occupancy; VN1_NCB Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Credit Occupancy; D2K Credits",
-        "Counter": "0,1,2",
-        "EventCode": "0x61",
-        "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD",
+        "BriefDescription": "BL Flow Q Occupancy; VN1 RSP Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Credit Occupancy",
-        "Counter": "0,1,2",
-        "EventCode": "0x61",
-        "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL",
+        "BriefDescription": "BL Flow Q Occupancy; VN1 WB Messages",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB",
         "PerPkg": "1",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Credit Occupancy",
-        "Counter": "0,1,2",
-        "EventCode": "0x61",
-        "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO",
+        "BriefDescription": "Speculative ARB for BL  - New Message; VN0 WB Messages",
+        "EventCode": "0x38",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCB",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x43",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ",
+        "BriefDescription": "Speculative ARB for BL  - New Message; VN0 NCS Messages",
+        "EventCode": "0x38",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x43",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP",
+        "BriefDescription": "Speculative ARB for BL  - New Message; VN0 WB Messages",
+        "EventCode": "0x38",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x43",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP",
+        "BriefDescription": "Speculative ARB for BL  - New Message; VN1 WB Messages",
+        "EventCode": "0x38",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x43",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP",
+        "BriefDescription": "Speculative ARB for BL  - New Message; VN1 NCB Messages",
+        "EventCode": "0x38",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x43",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB",
+        "BriefDescription": "Speculative ARB for BL  - New Message; VN1 RSP Messages",
+        "EventCode": "0x38",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_WB",
         "PerPkg": "1",
+        "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x43",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB",
+        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCB Messages",
+        "EventCode": "0x37",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCB",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x43",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS",
+        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCS Messages",
+        "EventCode": "0x37",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x44",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ",
+        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 RSP Messages",
+        "EventCode": "0x37",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x44",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP",
+        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 WB Messages",
+        "EventCode": "0x37",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x44",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP",
+        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCS Messages",
+        "EventCode": "0x37",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x44",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP",
+        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCB Messages",
+        "EventCode": "0x37",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+        "UMask": "0x80",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x44",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB",
+        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 RSP Messages",
+        "EventCode": "0x37",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_RSP",
         "PerPkg": "1",
+        "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x44",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB",
+        "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 WB Messages",
+        "EventCode": "0x37",
+        "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_WB",
         "PerPkg": "1",
+        "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x44",
-        "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS",
+        "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Data Flit Not Sent; All",
-        "Counter": "0,1,2",
-        "EventCode": "0x57",
-        "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.ALL",
+        "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD",
+        "PerPkg": "1",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
+        "Unit": "M3UPI"
+    },
+    {
+        "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Data Flit Not Sent; No BGF Credits",
-        "Counter": "0,1,2",
-        "EventCode": "0x57",
-        "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_BGF",
+        "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Data Flit Not Sent; No TxQ Credits",
-        "Counter": "0,1,2",
-        "EventCode": "0x57",
-        "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_TXQ",
+        "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x59",
-        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT",
+        "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x59",
-        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT",
+        "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Generating BL Data Flit Sequence",
-        "Counter": "0,1,2",
-        "EventCode": "0x59",
-        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO",
+        "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Generating BL Data Flit Sequence",
-        "Counter": "0,1,2",
-        "EventCode": "0x59",
-        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY",
+        "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Generating BL Data Flit Sequence",
-        "Counter": "0,1,2",
-        "EventCode": "0x59",
-        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT",
+        "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Generating BL Data Flit Sequence",
-        "Counter": "0,1,2",
-        "EventCode": "0x59",
-        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0",
+        "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce",
+        "EventCode": "0x9F",
+        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Generating BL Data Flit Sequence",
-        "Counter": "0,1,2",
-        "EventCode": "0x59",
-        "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce",
+        "EventCode": "0x96",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC",
-        "Counter": "0,1,2",
-        "EventCode": "0x5A",
-        "EventName": "UNC_M3UPI_RxC_FLITS_MISC",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit",
+        "EventCode": "0x96",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sent Header Flit; One Message",
-        "Counter": "0,1,2",
-        "EventCode": "0x56",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce",
+        "EventCode": "0x96",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sent Header Flit; Two Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x56",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.2_MSGS",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce",
+        "EventCode": "0x96",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sent Header Flit; Three Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x56",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.3_MSGS",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit",
+        "EventCode": "0x96",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Sent Header Flit; One Message in non-VNA",
-        "Counter": "0,1,2",
-        "EventCode": "0x56",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG_VNX",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce",
+        "EventCode": "0x96",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Slotting BL Message Into Header Flit; All",
-        "Counter": "0,1,2",
-        "EventCode": "0x58",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce",
+        "EventCode": "0x97",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Slotting BL Message Into Header Flit; Needs Data Flit",
-        "Counter": "0,1,2",
-        "EventCode": "0x58",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit",
+        "EventCode": "0x97",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x58",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce",
+        "EventCode": "0x97",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x58",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce",
+        "EventCode": "0x97",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x58",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit",
+        "EventCode": "0x97",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Bubble",
-        "Counter": "0,1,2",
-        "EventCode": "0x58",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce",
+        "EventCode": "0x97",
+        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Not Avail",
-        "Counter": "0,1,2",
-        "EventCode": "0x58",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL",
+        "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce",
+        "EventCode": "0x95",
+        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1; Acumullate",
-        "Counter": "0,1,2",
-        "EventCode": "0x53",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM",
+        "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit",
+        "EventCode": "0x95",
+        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1; Accumulate Ready",
-        "Counter": "0,1,2",
-        "EventCode": "0x53",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ",
+        "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce",
+        "EventCode": "0x95",
+        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1; Accumulate Wasted",
-        "Counter": "0,1,2",
-        "EventCode": "0x53",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED",
+        "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce",
+        "EventCode": "0x95",
+        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Blocked",
-        "Counter": "0,1,2",
-        "EventCode": "0x53",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED",
+        "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit",
+        "EventCode": "0x95",
+        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Message",
-        "Counter": "0,1,2",
-        "EventCode": "0x53",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG",
+        "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce",
+        "EventCode": "0x95",
+        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1; Parallel Ok",
-        "Counter": "0,1,2",
-        "EventCode": "0x53",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR",
+        "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce",
+        "EventCode": "0x99",
+        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1; Parallel Message",
-        "Counter": "0,1,2",
-        "EventCode": "0x53",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_MSG",
+        "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit",
+        "EventCode": "0x99",
+        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Flit Gen - Header 1; Parallel Flit Finished",
-        "Counter": "0,1,2",
-        "EventCode": "0x53",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_FLIT",
+        "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce",
+        "EventCode": "0x99",
+        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall",
-        "Counter": "0,1,2",
-        "EventCode": "0x54",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL",
+        "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce",
+        "EventCode": "0x99",
+        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall - No Message",
-        "Counter": "0,1,2",
-        "EventCode": "0x54",
-        "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG",
+        "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit",
+        "EventCode": "0x99",
+        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Header Not Sent; All",
-        "Counter": "0,1,2",
-        "EventCode": "0x55",
-        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ALL",
+        "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce",
+        "EventCode": "0x99",
+        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Header Not Sent; No BGF Credits",
-        "Counter": "0,1,2",
-        "EventCode": "0x55",
-        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_CRD",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce",
+        "EventCode": "0x94",
+        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Header Not Sent; No TxQ Credits",
-        "Counter": "0,1,2",
-        "EventCode": "0x55",
-        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_CRD",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit",
+        "EventCode": "0x94",
+        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
-    {
-        "BriefDescription": "Header Not Sent; No BGF Credits + No Extra Message Slotted",
-        "Counter": "0,1,2",
-        "EventCode": "0x55",
-        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_NO_MSG",
+    {
+        "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce",
+        "EventCode": "0x94",
+        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Header Not Sent; No TxQ Credits + No Extra Message Slotted",
-        "Counter": "0,1,2",
-        "EventCode": "0x55",
-        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_NO_MSG",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce",
+        "EventCode": "0x94",
+        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Header Not Sent; Sent - One Slot Taken",
-        "Counter": "0,1,2",
-        "EventCode": "0x55",
-        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ONE_TAKEN",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit",
+        "EventCode": "0x94",
+        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Header Not Sent; Sent - Two Slots Taken",
-        "Counter": "0,1,2",
-        "EventCode": "0x55",
-        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.TWO_TAKEN",
+        "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce",
+        "EventCode": "0x94",
+        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Header Not Sent; Sent - Three Slots Taken",
-        "Counter": "0,1,2",
-        "EventCode": "0x55",
-        "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.THREE_TAKEN",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_BNC",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Message Held; VN0",
-        "Counter": "0,1,2",
-        "EventCode": "0x52",
-        "EventName": "UNC_M3UPI_RxC_HELD.VN0",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK_BNC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Message Held; VN1",
-        "Counter": "0,1,2",
-        "EventCode": "0x52",
-        "EventName": "UNC_M3UPI_RxC_HELD.VN1",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_BNC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Message Held; Parallel Attempt",
-        "Counter": "0,1,2",
-        "EventCode": "0x52",
-        "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV_BNC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Message Held; Parallel Success",
-        "Counter": "0,1,2",
-        "EventCode": "0x52",
-        "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS",
+        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Message Held; Parallel AD Lost",
-        "Counter": "0,1,2",
-        "EventCode": "0x52",
-        "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_AD_LOST",
+        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Message Held; Parallel BL Lost",
-        "Counter": "0,1,2",
-        "EventCode": "0x52",
-        "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_BL_LOST",
+        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Message Held; Can't Slot AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x52",
-        "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD",
+        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Message Held; Can't Slot BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x52",
-        "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL",
+        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x41",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ",
+        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x41",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP",
+        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x41",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP",
+        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x41",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP",
+        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x41",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB",
+        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x41",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB",
+        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x41",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS",
+        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x42",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ",
+        "BriefDescription": "CMS Vertical ADS Used; IV",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x42",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x42",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x42",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x42",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x42",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x42",
-        "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x45",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV",
+        "EventCode": "0x92",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.IV",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x45",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0",
+        "EventCode": "0x93",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x45",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1",
+        "EventCode": "0x93",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x45",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0",
+        "EventCode": "0x93",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x45",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1",
+        "EventCode": "0x93",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x45",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0",
+        "EventCode": "0x93",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x45",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1",
+        "EventCode": "0x93",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x46",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV",
+        "EventCode": "0x93",
+        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.IV",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x46",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP",
+        "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0",
+        "EventCode": "0x91",
+        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x46",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP",
+        "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1",
+        "EventCode": "0x91",
+        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x46",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP",
+        "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0",
+        "EventCode": "0x91",
+        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x46",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB",
+        "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1",
+        "EventCode": "0x91",
+        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x46",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB",
+        "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0",
+        "EventCode": "0x91",
+        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x46",
-        "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS",
+        "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1",
+        "EventCode": "0x91",
+        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message can't slot into flit; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ",
+        "BriefDescription": "CMS Vert Egress Allocations; IV",
+        "EventCode": "0x91",
+        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.IV",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message can't slot into flit; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP",
+        "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message can't slot into flit; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP",
+        "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message can't slot into flit; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP",
+        "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message can't slot into flit; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB",
+        "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message can't slot into flit; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB",
+        "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN0 message can't slot into flit; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS",
+        "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message can't slot into flit; REQ on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ",
+        "BriefDescription": "CMS Vertical Egress NACKs; IV",
+        "EventCode": "0x98",
+        "EventName": "UNC_M3UPI_TxR_VERT_NACK.IV",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message can't slot into flit; SNP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP",
+        "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message can't slot into flit; RSP on AD",
-        "Counter": "0,1,2",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP",
+        "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message can't slot into flit; RSP on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP",
+        "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message can't slot into flit; WB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB",
+        "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message can't slot into flit; NCB on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB",
+        "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "VN1 message can't slot into flit; NCS on BL",
-        "Counter": "0,1,2",
-        "EventCode": "0x4F",
-        "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS",
+        "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "SMI3 Prefetch Messages; Arrived",
-        "Counter": "0,1,2",
-        "EventCode": "0x62",
-        "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARRIVED",
+        "BriefDescription": "CMS Vert Egress Occupancy; IV",
+        "EventCode": "0x90",
+        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.IV",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "SMI3 Prefetch Messages; Lost Arbitration",
-        "Counter": "0,1,2",
-        "EventCode": "0x62",
-        "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARB_LOST",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "SMI3 Prefetch Messages; Slotted",
-        "Counter": "0,1,2",
-        "EventCode": "0x62",
-        "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.SLOTTED",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "SMI3 Prefetch Messages; Dropped - Old",
-        "Counter": "0,1,2",
-        "EventCode": "0x62",
-        "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_OLD",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "SMI3 Prefetch Messages; Dropped - Wrap",
-        "Counter": "0,1,2",
-        "EventCode": "0x62",
-        "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_WRAP",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Remote VNA Credits; Used",
-        "Counter": "0,1,2",
-        "EventCode": "0x5B",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD.USED",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Remote VNA Credits; Corrected",
-        "Counter": "0,1,2",
-        "EventCode": "0x5B",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Remote VNA Credits; Level &lt; 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x5B",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.IV",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Remote VNA Credits; Level &lt; 4",
-        "Counter": "0,1,2",
-        "EventCode": "0x5B",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4",
+        "BriefDescription": "UPI0 AD Credits Empty; VN0 REQ Messages",
+        "EventCode": "0x20",
+        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Remote VNA Credits; Level &lt; 5",
-        "Counter": "0,1,2",
-        "EventCode": "0x5B",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5",
+        "BriefDescription": "UPI0 AD Credits Empty; VN0 RSP Messages",
+        "EventCode": "0x20",
+        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Remote VNA Credits; Any In Use",
-        "Counter": "0,1,2",
-        "EventCode": "0x5B",
-        "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE",
+        "BriefDescription": "UPI0 AD Credits Empty; VN0 SNP Messages",
+        "EventCode": "0x20",
+        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_BNC",
+        "BriefDescription": "UPI0 AD Credits Empty; VN1 REQ Messages",
+        "EventCode": "0x20",
+        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+        "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_BNC",
+        "BriefDescription": "UPI0 AD Credits Empty; VN1 RSP Messages",
+        "EventCode": "0x20",
+        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+        "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD",
+        "BriefDescription": "UPI0 AD Credits Empty; VN1 SNP Messages",
+        "EventCode": "0x20",
+        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD",
+        "BriefDescription": "UPI0 AD Credits Empty; VNA",
+        "EventCode": "0x20",
+        "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M3UPI_RxR_BYPASS.AD_BNC",
+        "BriefDescription": "UPI0 BL Credits Empty; VN0 RSP Messages",
+        "EventCode": "0x21",
+        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M3UPI_RxR_BYPASS.AK_BNC",
+        "BriefDescription": "UPI0 BL Credits Empty; VN0 REQ Messages",
+        "EventCode": "0x21",
+        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M3UPI_RxR_BYPASS.BL_BNC",
+        "BriefDescription": "UPI0 BL Credits Empty; VN0 SNP Messages",
+        "EventCode": "0x21",
+        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M3UPI_RxR_BYPASS.IV_BNC",
+        "BriefDescription": "UPI0 BL Credits Empty; VN1 RSP Messages",
+        "EventCode": "0x21",
+        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD",
+        "BriefDescription": "UPI0 BL Credits Empty; VN1 REQ Messages",
+        "EventCode": "0x21",
+        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD",
+        "BriefDescription": "UPI0 BL Credits Empty; VN1 SNP Messages",
+        "EventCode": "0x21",
+        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB",
         "PerPkg": "1",
+        "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
         "UMask": "0x40",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_BNC",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
-    },
-    {
-        "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK_BNC",
+        "BriefDescription": "UPI0 BL Credits Empty; VNA",
+        "EventCode": "0x21",
+        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_BNC",
+        "BriefDescription": "Prefetches generated by the flow control queue of the M3UPI unit.",
+        "EventCode": "0x29",
+        "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Count cases where flow control queue that sits between the Intel Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller)",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV_BNC",
+        "BriefDescription": "Vertical AD Ring In Use; Down and Even",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD",
+        "BriefDescription": "Vertical AD Ring In Use; Down and Odd",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD",
+        "BriefDescription": "Vertical AD Ring In Use; Up and Even",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV",
+        "BriefDescription": "Vertical AD Ring In Use; Up and Odd",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M3UPI_RxR_INSERTS.AD_BNC",
+        "BriefDescription": "Vertical AK Ring In Use; Down and Even",
+        "EventCode": "0xA8",
+        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M3UPI_RxR_INSERTS.AK_BNC",
+        "BriefDescription": "Vertical AK Ring In Use; Down and Odd",
+        "EventCode": "0xA8",
+        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M3UPI_RxR_INSERTS.BL_BNC",
+        "BriefDescription": "Vertical AK Ring In Use; Up and Even",
+        "EventCode": "0xA8",
+        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M3UPI_RxR_INSERTS.IV_BNC",
+        "BriefDescription": "Vertical AK Ring In Use; Up and Odd",
+        "EventCode": "0xA8",
+        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD",
+        "BriefDescription": "Vertical BL Ring in Use; Down and Even",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD",
+        "BriefDescription": "Vertical BL Ring in Use; Down and Odd",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_BNC",
+        "BriefDescription": "Vertical BL Ring in Use; Up and Even",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK_BNC",
+        "BriefDescription": "Vertical BL Ring in Use; Up and Odd",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_BNC",
+        "BriefDescription": "Vertical IV Ring in Use; Down",
+        "EventCode": "0xAC",
+        "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV_BNC",
+        "BriefDescription": "Vertical IV Ring in Use; Up",
+        "EventCode": "0xAC",
+        "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD",
+        "BriefDescription": "VN0 Credit Used; WB on BL",
+        "EventCode": "0x5C",
+        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD",
+        "BriefDescription": "VN0 Credit Used; NCB on BL",
+        "EventCode": "0x5C",
+        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
+        "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+        "BriefDescription": "VN0 Credit Used; REQ on AD",
+        "EventCode": "0x5C",
+        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+        "BriefDescription": "VN0 Credit Used; RSP on AD",
+        "EventCode": "0x5C",
+        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+        "BriefDescription": "VN0 Credit Used; SNP on AD",
+        "EventCode": "0x5C",
+        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+        "BriefDescription": "VN0 Credit Used; RSP on BL",
+        "EventCode": "0x5C",
+        "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+        "BriefDescription": "VN0 No Credits; WB on BL",
+        "EventCode": "0x5E",
+        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Number of Cycles there were no VN0 Credits; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2",
-        "EventCode": "0xD0",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+        "BriefDescription": "VN0 No Credits; NCB on BL",
+        "EventCode": "0x5E",
+        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Number of Cycles there were no VN0 Credits; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+        "BriefDescription": "VN0 No Credits; REQ on AD",
+        "EventCode": "0x5E",
+        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of Cycles there were no VN0 Credits; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+        "BriefDescription": "VN0 No Credits; RSP on AD",
+        "EventCode": "0x5E",
+        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of Cycles there were no VN0 Credits; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+        "BriefDescription": "VN0 No Credits; SNP on AD",
+        "EventCode": "0x5E",
+        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of Cycles there were no VN0 Credits; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+        "BriefDescription": "VN0 No Credits; RSP on BL",
+        "EventCode": "0x5E",
+        "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of Cycles there were no VN0 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+        "BriefDescription": "VN1 Credit Used; WB on BL",
+        "EventCode": "0x5D",
+        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2",
-        "EventCode": "0xD2",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+        "BriefDescription": "VN1 Credit Used; NCB on BL",
+        "EventCode": "0x5D",
+        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+        "BriefDescription": "VN1 Credit Used; REQ on AD",
+        "EventCode": "0x5D",
+        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+        "BriefDescription": "VN1 Credit Used; RSP on AD",
+        "EventCode": "0x5D",
+        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+        "BriefDescription": "VN1 Credit Used; SNP on AD",
+        "EventCode": "0x5D",
+        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+        "BriefDescription": "VN1 Credit Used; RSP on BL",
+        "EventCode": "0x5D",
+        "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+        "BriefDescription": "VN1 No Credits; WB on BL",
+        "EventCode": "0x5F",
+        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB",
         "PerPkg": "1",
+        "PublicDescription": "Number of Cycles there were no VN1 Credits; Data Response (WB) messages on BL.  WB is generally used to transmit data with coherency.  For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
         "UMask": "0x10",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+        "BriefDescription": "VN1 No Credits; NCB on BL",
+        "EventCode": "0x5F",
+        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS",
         "PerPkg": "1",
+        "PublicDescription": "Number of Cycles there were no VN1 Credits; Non-Coherent Broadcast (NCB) messages on BL.  NCB is generally used to transmit data without coherency.  For example, non-coherent read data returns.",
         "UMask": "0x20",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
-        "Counter": "0,1,2",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+        "BriefDescription": "VN1 No Credits; REQ on AD",
+        "EventCode": "0x5F",
+        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Number of Cycles there were no VN1 Credits; Home (REQ) messages on AD.  REQ is generally used to send requests, request responses, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
-        "Counter": "0,1,2",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+        "BriefDescription": "VN1 No Credits; RSP on AD",
+        "EventCode": "0x5F",
+        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Number of Cycles there were no VN1 Credits; Response (RSP) messages on AD.  RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x4",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
-        "Counter": "0,1,2",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+        "BriefDescription": "VN1 No Credits; SNP on AD",
+        "EventCode": "0x5F",
+        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Number of Cycles there were no VN1 Credits; Snoops (SNP) messages on AD.  SNP is used for outgoing snoops.",
+        "UMask": "0x2",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
-        "Counter": "0,1,2",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+        "BriefDescription": "VN1 No Credits; RSP on BL",
+        "EventCode": "0x5F",
+        "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Number of Cycles there were no VN1 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+        "UMask": "0x8",
         "Unit": "M3UPI"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
-        "Counter": "0,1,2",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_TxC_BL.DRS_UPI",
+        "Deprecated": "1",
+        "EventCode": "0x40",
+        "EventName": "UNC_NoUnit_TxC_BL.DRS_UPI",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
-        "Counter": "0,1,2",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+        "BriefDescription": "Clocks of the Intel Ultra Path Interconnect (UPI)",
+        "EventCode": "0x1",
+        "EventName": "UNC_UPI_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts clockticks of the fixed frequency clock controlling the Intel Ultra Path Interconnect (UPI).  This clock runs at1/8th the 'GT/s' speed of the UPI link.  For example, a  9.6GT/s  link will have a fixed Frequency of 1.2 Ghz.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_BNC",
+        "BriefDescription": "Data Response packets that go direct to core",
+        "EventCode": "0x12",
+        "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to core bypassing the CHA.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AK_BNC",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_DIRECT_ATTEMPTS.D2U",
+        "Deprecated": "1",
+        "EventCode": "0x12",
+        "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_BNC",
+        "BriefDescription": "Data Response packets that go direct to Intel UPI",
+        "EventCode": "0x12",
+        "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2U",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to Intel Ultra Path Interconnect (UPI) bypassing the CHA .",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD",
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD",
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x9F",
-        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_BNC",
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x9F",
-        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK_BNC",
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "UMask": "0x10",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x9F",
-        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_BNC",
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "UMask": "0x20",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x9F",
-        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV_BNC",
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "UMask": "0x40",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x9F",
-        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD",
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "UMask": "0x80",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x9F",
-        "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD",
+        "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
+        "EventCode": "0x18",
+        "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x96",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_BNC",
+        "BriefDescription": "Cycles Intel UPI is in L1 power mode (shutdown)",
+        "EventCode": "0x21",
+        "EventName": "UNC_UPI_L1_POWER_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts cycles when the Intel Ultra Path Interconnect (UPI) is in L1 power mode.  L1 is a mode that totally shuts down the UPI link.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdown.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x96",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK_BNC",
+        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
+        "EventCode": "0x14",
+        "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x96",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_BNC",
+        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
+        "EventCode": "0x14",
+        "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x96",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV_BNC",
+        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
+        "EventCode": "0x14",
+        "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x96",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD",
+        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
+        "EventCode": "0x14",
+        "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x96",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD",
+        "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
+        "EventCode": "0x14",
+        "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "UMask": "0x10",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x97",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_BNC",
+        "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
+        "EventCode": "0x16",
+        "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x97",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK_BNC",
+        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
+        "EventCode": "0x15",
+        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "UMask": "0x20",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x97",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_BNC",
+        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
+        "EventCode": "0x15",
+        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x97",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV_BNC",
+        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
+        "EventCode": "0x15",
+        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x97",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD",
+        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
+        "EventCode": "0x15",
+        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
         "PerPkg": "1",
         "UMask": "0x10",
-        "Unit": "M3UPI"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x97",
-        "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD",
+        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
+        "EventCode": "0x15",
+        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x95",
-        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_BNC",
+        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
+        "EventCode": "0x15",
+        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x95",
-        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK_BNC",
+        "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
+        "EventCode": "0x15",
+        "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "UMask": "0x40",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x95",
-        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_BNC",
+        "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1",
+        "EventCode": "0x20",
+        "EventName": "UNC_UPI_PHY_INIT_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x95",
-        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV_BNC",
+        "BriefDescription": "L1 Req Nack",
+        "EventCode": "0x23",
+        "EventName": "UNC_UPI_POWER_L1_NACK",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts the number of times a link sends/receives a LinkReqNAck.  When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states.  This requests can either be accepted or denied.  If the Rx side replies with an Ack, the power mode will change.  If it replies with NAck, no change will take place.  This can be filtered based on Rx and Tx.  An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change).  A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x95",
-        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD",
+        "BriefDescription": "L1 Req (same as L1 Ack).",
+        "EventCode": "0x22",
+        "EventName": "UNC_UPI_POWER_L1_REQ",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts the number of times a link sends/receives a LinkReqAck.  When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states.  This requests can either be accepted or denied.  If the Rx side replies with an Ack, the power mode will change.  If it replies with NAck, no change will take place.  This can be filtered based on Rx and Tx.  An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change).  A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x95",
-        "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD",
+        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
+        "EventCode": "0x46",
+        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x99",
-        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_BNC",
+        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
+        "EventCode": "0x46",
+        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x99",
-        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK_BNC",
+        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
+        "EventCode": "0x46",
+        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x99",
-        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_BNC",
+        "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
+        "EventCode": "0x46",
+        "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x99",
-        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV_BNC",
+        "BriefDescription": "Cycles the Rx of the Intel UPI is in L0p power mode",
+        "EventCode": "0x25",
+        "EventName": "UNC_UPI_RxL0P_POWER_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts cycles when the receive side (Rx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x99",
-        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD",
+        "BriefDescription": "Cycles in L0. Receive side.",
+        "EventCode": "0x24",
+        "EventName": "UNC_UPI_RxL0_POWER_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "Number of UPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x99",
-        "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - NCB",
+        "UMask": "0xe",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x94",
-        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_BNC",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - NCB",
+        "UMask": "0x10e",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x94",
-        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK_BNC",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - NCS",
+        "UMask": "0xf",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x94",
-        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_BNC",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - NCS",
+        "UMask": "0x10f",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x94",
-        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV_BNC",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Request",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "REQ Message Class",
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x94",
-        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Request Opcode",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match REQ Opcodes - Specified in Umask[7:4]",
+        "UMask": "0x108",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit",
-        "Counter": "0,1,2",
-        "EventCode": "0x94",
-        "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Response - Conflict",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "UMask": "0x1aa",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x9B",
-        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_BNC",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Response - Invalid",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "UMask": "0x12a",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x9B",
-        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK_BNC",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class -WB",
+        "UMask": "0xc",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x9B",
-        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_BNC",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class -WB",
+        "UMask": "0x10c",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce",
-        "Counter": "0,1,2",
-        "EventCode": "0x9B",
-        "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV_BNC",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - RSP",
+        "UMask": "0xa",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - RSP",
+        "UMask": "0x10a",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG0",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Snoop",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "SNP Message Class",
+        "UMask": "0x9",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Snoop Opcode",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match SNP Opcodes - Specified in Umask[7:4]",
+        "UMask": "0x109",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Writeback",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class -WB",
+        "UMask": "0xd",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG1",
+        "BriefDescription": "Matches on Receive path of a UPI Port; Writeback",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class -WB",
+        "UMask": "0x10d",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1",
+        "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
+        "EventCode": "0x31",
+        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0",
+        "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
+        "EventCode": "0x31",
+        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer  (Receive Queue) and passed directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0",
+        "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
+        "EventCode": "0x31",
+        "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot2 RxQ buffer (Receive Queue)  and passed directly to the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0",
+        "BriefDescription": "CRC Errors Detected",
+        "EventCode": "0xB",
+        "EventName": "UNC_UPI_RxL_CRC_ERRORS",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Number of CRC errors detected in the UPI Agent.  Each UPI flit incorporates 8 bits of CRC for error detection.  This counts the number of flits where the CRC was able to detect an error.  After an error has been detected, the UPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; IV",
-        "Counter": "0,1,2",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV",
+        "BriefDescription": "LLR Requests Sent",
+        "EventCode": "0x8",
+        "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Number of LLR Requests were transmitted.  This should generally be &lt;= the number of CRC errors detected.  If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1",
+        "BriefDescription": "VN0 Credit Consumed",
+        "EventCode": "0x39",
+        "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1",
+        "BriefDescription": "VN1 Credit Consumed",
+        "EventCode": "0x3A",
+        "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1",
+        "BriefDescription": "VNA Credit Consumed",
+        "EventCode": "0x38",
+        "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x92",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG0",
+        "BriefDescription": "Valid data FLITs received from any slot",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts valid data FLITs  (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.",
+        "UMask": "0xf",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x92",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG0",
+        "BriefDescription": "Null FLITs received from any slot",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.",
+        "UMask": "0x27",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x92",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG0",
+        "BriefDescription": "Valid Flits Received; Data",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.DATA",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV",
-        "Counter": "0,1,2",
-        "EventCode": "0x92",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.IV",
+        "BriefDescription": "Valid Flits Received; Idle",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.IDLE",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).",
+        "UMask": "0x47",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x92",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG1",
+        "BriefDescription": "Valid Flits Received; LLCRD Not Empty",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.LLCRD",
         "PerPkg": "1",
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
         "UMask": "0x10",
-        "Unit": "M3UPI"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x92",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG1",
+        "BriefDescription": "Valid Flits Received; LLCTRL",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.LLCTRL",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Equivalent to an idle packet.  Enables counting of slot 0 LLCTRL messages.",
+        "UMask": "0x40",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x92",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG1",
+        "BriefDescription": "Protocol header and credit FLITs received from any slot",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts protocol header and credit FLITs  (80 bit FLow control unITs) received from any of the 3 UPI slots on this UPI unit.",
+        "UMask": "0x97",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x93",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.ALL_NULL",
+        "Deprecated": "1",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.NULL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "UMask": "0x20",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x93",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG0",
+        "BriefDescription": "Valid Flits Received; Protocol Header",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.PROTHDR",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
+        "UMask": "0x80",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x93",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.PROTHDR",
+        "Deprecated": "1",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.PROT_HDR",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "UMask": "0x80",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV",
-        "Counter": "0,1,2",
-        "EventCode": "0x93",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.IV",
+        "BriefDescription": "Valid Flits Received; Slot 0",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.SLOT0",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 0 - Other mask bits determine types of headers to count.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x93",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG1",
+        "BriefDescription": "Valid Flits Received; Slot 1",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.SLOT1",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 1 - Other mask bits determine types of headers to count.",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x93",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG1",
+        "BriefDescription": "Valid Flits Received; Slot 2",
+        "EventCode": "0x3",
+        "EventName": "UNC_UPI_RxL_FLITS.SLOT2",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 2 - Other mask bits determine types of headers to count.",
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x93",
-        "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG1",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
+        "Deprecated": "1",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_HDR_MATCH.NCB",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "UMask": "0xc",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x91",
-        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
+        "Deprecated": "1",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_HDR_MATCH.NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "UMask": "0xd",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x91",
-        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
+        "Deprecated": "1",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_HDR_MATCH.REQ",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x91",
-        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG0",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
+        "Deprecated": "1",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_HDR_MATCH.RSP",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "UMask": "0xa",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; IV",
-        "Counter": "0,1,2",
-        "EventCode": "0x91",
-        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.IV",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
+        "Deprecated": "1",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_HDR_MATCH.SNP",
+        "PerPkg": "1",
+        "UMask": "0x9",
+        "Unit": "UPI LL"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
+        "Deprecated": "1",
+        "EventCode": "0x5",
+        "EventName": "UNC_UPI_RxL_HDR_MATCH.WB",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "UMask": "0xb",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x91",
-        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG1",
+        "BriefDescription": "RxQ Flit Buffer Allocations; Slot 0",
+        "EventCode": "0x30",
+        "EventName": "UNC_UPI_RxL_INSERTS.SLOT0",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x91",
-        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG1",
+        "BriefDescription": "RxQ Flit Buffer Allocations; Slot 1",
+        "EventCode": "0x30",
+        "EventName": "UNC_UPI_RxL_INSERTS.SLOT1",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x91",
-        "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG1",
+        "BriefDescription": "RxQ Flit Buffer Allocations; Slot 2",
+        "EventCode": "0x30",
+        "EventName": "UNC_UPI_RxL_INSERTS.SLOT2",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x98",
-        "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG0",
+        "BriefDescription": "RxQ Occupancy - All Packets; Slot 0",
+        "EventCode": "0x32",
+        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x98",
-        "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG0",
+        "BriefDescription": "RxQ Occupancy - All Packets; Slot 1",
+        "EventCode": "0x32",
+        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x98",
-        "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG0",
+        "BriefDescription": "RxQ Occupancy - All Packets; Slot 2",
+        "EventCode": "0x32",
+        "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x98",
-        "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG1",
+        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
+        "EventCode": "0x33",
+        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x98",
-        "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG1",
+        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
+        "EventCode": "0x33",
+        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x98",
-        "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG1",
+        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
+        "EventCode": "0x33",
+        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x90",
-        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG0",
+        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
+        "EventCode": "0x33",
+        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x90",
-        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG0",
+        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
+        "EventCode": "0x33",
+        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "UMask": "0x10",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x90",
-        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG0",
+        "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
+        "EventCode": "0x33",
+        "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "UMask": "0x20",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; IV",
-        "Counter": "0,1,2",
-        "EventCode": "0x90",
-        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.IV",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x90",
-        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG1",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "UMask": "0x40",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x90",
-        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG1",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
         "PerPkg": "1",
         "UMask": "0x20",
-        "Unit": "M3UPI"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x90",
-        "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG1",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG0",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG0",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0",
-        "Counter": "0,1,2",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG0",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "UMask": "0x80",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG1",
+        "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
+        "EventCode": "0x2A",
+        "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
         "PerPkg": "1",
         "UMask": "0x10",
-        "Unit": "M3UPI"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG1",
+        "BriefDescription": "Cycles in which the Tx of the Intel Ultra Path Interconnect (UPI) is in L0p power mode",
+        "EventCode": "0x27",
+        "EventName": "UNC_UPI_TxL0P_POWER_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts cycles when the transmit side (Tx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1",
-        "Counter": "0,1,2",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG1",
+        "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
+        "EventCode": "0x28",
+        "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use; Up and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN",
+        "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
+        "EventCode": "0x29",
+        "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use; Up and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD",
+        "BriefDescription": "Cycles in L0. Transmit side.",
+        "EventCode": "0x26",
+        "EventName": "UNC_UPI_TxL0_POWER_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Number of UPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use; Down and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - NCB",
+        "UMask": "0xe",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use; Down and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - NCB",
+        "UMask": "0x10e",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use; Up and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xA8",
-        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - NCS",
+        "UMask": "0xf",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use; Up and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xA8",
-        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - NCS",
+        "UMask": "0x10f",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use; Down and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xA8",
-        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Request",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "REQ Message Class",
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use; Down and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xA8",
-        "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Request Opcode",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match REQ Opcodes - Specified in Umask[7:4]",
+        "UMask": "0x108",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use; Up and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xAA",
-        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Conflict",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "UMask": "0x1aa",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use; Up and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xAA",
-        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Invalid",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "UMask": "0x12a",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use; Down and Even",
-        "Counter": "0,1,2",
-        "EventCode": "0xAA",
-        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class -WB",
+        "UMask": "0xc",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use; Down and Odd",
-        "Counter": "0,1,2",
-        "EventCode": "0xAA",
-        "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class -WB",
+        "UMask": "0x10c",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical IV Ring in Use; Up",
-        "Counter": "0,1,2",
-        "EventCode": "0xAC",
-        "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - RSP",
+        "UMask": "0xa",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Vertical IV Ring in Use; Down",
-        "Counter": "0,1,2",
-        "EventCode": "0xAC",
-        "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class - RSP",
+        "UMask": "0x10a",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "D2C Sent",
-        "Counter": "0,1,2",
-        "EventCode": "0x2B",
-        "EventName": "UNC_M3UPI_D2C_SENT",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
         "PerPkg": "1",
-        "Unit": "M3UPI"
+        "PublicDescription": "SNP Message Class",
+        "UMask": "0x9",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "FaST wire asserted; Vertical",
-        "Counter": "0,1,2",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M3UPI_FAST_ASSERTED.VERT",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop Opcode",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match SNP Opcodes - Specified in Umask[7:4]",
+        "UMask": "0x109",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "FaST wire asserted; Horizontal",
-        "Counter": "0,1,2",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M3UPI_FAST_ASSERTED.HORZ",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class -WB",
+        "UMask": "0xd",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Sent Header Flit",
-        "Counter": "0,1,2",
-        "EventCode": "0x56",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_1",
+        "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M3UPI"
+        "PublicDescription": "Match Message Class -WB",
+        "UMask": "0x10d",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Sent Header Flit",
-        "Counter": "0,1,2",
-        "EventCode": "0x56",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_2",
+        "BriefDescription": "FLITs that bypassed the TxL Buffer",
+        "EventCode": "0x41",
+        "EventName": "UNC_UPI_TxL_BYPASSED",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR  mode, increasing latency to transfer out to the link.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Sent Header Flit",
-        "Counter": "0,1,2",
-        "EventCode": "0x56",
-        "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_3",
+        "BriefDescription": "Valid data FLITs transmitted via any slot",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel Ultra Path Interconnect (UPI) slots on this UPI unit.",
+        "UMask": "0xf",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs; IV",
-        "Counter": "0,1,2",
-        "EventCode": "0x98",
-        "EventName": "UNC_M3UPI_TxR_VERT_NACK.IV",
+        "BriefDescription": "Null FLITs transmitted from any slot",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel Ulra Path Interconnect (UPI) slots on this UPI unit.",
+        "UMask": "0x27",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
-        "Counter": "0,1,2",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M3UPI_TxR_VERT_STARVED.IV",
+        "BriefDescription": "Valid Flits Sent; Data",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.DATA",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UPI0 BL Credits Empty; VNA",
-        "Counter": "0,1,2",
-        "EventCode": "0x21",
-        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA",
+        "BriefDescription": "Idle FLITs transmitted",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.IDLE",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts when the Intel Ultra Path Interconnect(UPI) transmits an idle FLIT(80 bit FLow control unITs).  Every UPI cycle must be sending either data FLITs, protocol/credit FLITs or idle FLITs.",
+        "UMask": "0x47",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UPI0 BL Credits Empty; VN0 REQ Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x21",
-        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP",
+        "BriefDescription": "Valid Flits Sent; LLCRD Not Empty",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.LLCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M3UPI"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
+        "UMask": "0x10",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UPI0 BL Credits Empty; VN0 RSP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x21",
-        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB",
+        "BriefDescription": "Valid Flits Sent; LLCTRL",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.LLCTRL",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M3UPI"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Equivalent to an idle packet.  Enables counting of slot 0 LLCTRL messages.",
+        "UMask": "0x40",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UPI0 BL Credits Empty; VN0 SNP Messages",
-        "Counter": "0,1,2",
-        "EventCode": "0x21",
-        "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB",
+        "BriefDescription": "Protocol header and credit FLITs transmitted across any slot",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M3UPI"
+        "PublicDescription": "Counts protocol header and credit FLITs (80 bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Interconnect) slots on this UPI unit.",
+        "UMask": "0x97",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Message Received; VLW",
-        "Counter": "0,1",
-        "EventCode": "0x42",
-        "EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.ALL_NULL",
+        "Deprecated": "1",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.NULL",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "UBOX"
+        "UMask": "0x20",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Message Received; MSI",
-        "Counter": "0,1",
-        "EventCode": "0x42",
-        "EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
+        "BriefDescription": "Valid Flits Sent; Protocol Header",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.PROTHDR",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "UBOX"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
+        "UMask": "0x80",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Message Received; IPI",
-        "Counter": "0,1",
-        "EventCode": "0x42",
-        "EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.PROTHDR",
+        "Deprecated": "1",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.PROT_HDR",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "UBOX"
+        "UMask": "0x80",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Message Received",
-        "Counter": "0,1",
-        "EventCode": "0x42",
-        "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
+        "BriefDescription": "Valid Flits Sent; Slot 0",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.SLOT0",
         "PerPkg": "1",
-        "UMask": "0x8",
-        "Unit": "UBOX"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 0 - Other mask bits determine types of headers to count.",
+        "UMask": "0x1",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Message Received",
-        "Counter": "0,1",
-        "EventCode": "0x42",
-        "EventName": "UNC_U_EVENT_MSG.INT_PRIO",
+        "BriefDescription": "Valid Flits Sent; Slot 1",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.SLOT1",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "UBOX"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 1 - Other mask bits determine types of headers to count.",
+        "UMask": "0x2",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "IDI Lock/SplitLock Cycles",
-        "Counter": "0,1",
-        "EventCode": "0x44",
-        "EventName": "UNC_U_LOCK_CYCLES",
+        "BriefDescription": "Valid Flits Sent; Slot 2",
+        "EventCode": "0x2",
+        "EventName": "UNC_UPI_TxL_FLITS.SLOT2",
         "PerPkg": "1",
-        "Unit": "UBOX"
+        "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 2 - Other mask bits determine types of headers to count.",
+        "UMask": "0x4",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
-        "Counter": "0,1",
-        "EventCode": "0x45",
-        "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.DATA_HDR",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "UBOX"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UNC_U_RACU_DRNG.RDRAND",
-        "Counter": "0,1",
-        "EventCode": "0x4C",
-        "EventName": "UNC_U_RACU_DRNG.RDRAND",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.DUAL_SLOT_HDR",
         "PerPkg": "1",
-        "UMask": "0x1",
-        "Unit": "UBOX"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UNC_U_RACU_DRNG.RDSEED",
-        "Counter": "0,1",
-        "EventCode": "0x4C",
-        "EventName": "UNC_U_RACU_DRNG.RDSEED",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.LOC",
         "PerPkg": "1",
-        "UMask": "0x2",
-        "Unit": "UBOX"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
-        "Counter": "0,1",
-        "EventCode": "0x4C",
-        "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
+        "Deprecated": "1",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.NCB",
         "PerPkg": "1",
-        "UMask": "0x4",
-        "Unit": "UBOX"
+        "UMask": "0xe",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "RACU Request",
-        "Counter": "0,1",
-        "EventCode": "0x46",
-        "EventName": "UNC_U_RACU_REQUESTS",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
+        "Deprecated": "1",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.NCS",
         "PerPkg": "1",
-        "Unit": "UBOX"
+        "UMask": "0xf",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
-        "Counter": "FIXED",
-        "EventCode": "0xff",
-        "EventName": "UNC_U_CLOCKTICKS",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.NON_DATA_HDR",
         "PerPkg": "1",
-        "Unit": "UBOX"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0x33",
-        "EventName": "UNC_H_CORE_SNP.CORE_GTONE",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.REM",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE",
-        "UMask": "0x42",
-        "Unit": "CHA"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
         "Deprecated": "1",
-        "EventCode": "0x33",
-        "EventName": "UNC_H_CORE_SNP.EVICT_GTONE",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.REQ",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE",
-        "UMask": "0x82",
-        "Unit": "CHA"
+        "UMask": "0x8",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
         "Deprecated": "1",
-        "EventCode": "0x53",
-        "EventName": "UNC_H_DIR_LOOKUP.NO_SNP",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_DATA",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP",
-        "UMask": "0x2",
-        "Unit": "CHA"
+        "UMask": "0xc",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
         "Deprecated": "1",
-        "EventCode": "0x53",
-        "EventName": "UNC_H_DIR_LOOKUP.SNP",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_NODATA",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP",
-        "UMask": "0x1",
-        "Unit": "CHA"
+        "UMask": "0xa",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated.",
         "Deprecated": "1",
-        "EventCode": "0x54",
-        "EventName": "UNC_H_DIR_UPDATE.HA",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.SGL_SLOT_HDR",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA",
-        "UMask": "0x1",
-        "Unit": "CHA"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
         "Deprecated": "1",
-        "EventCode": "0x54",
-        "EventName": "UNC_H_DIR_UPDATE.TOR",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.SNP",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR",
-        "UMask": "0x2",
-        "Unit": "CHA"
+        "UMask": "0x9",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
         "Deprecated": "1",
-        "EventCode": "0x5F",
-        "EventName": "UNC_H_HITME_HIT.EX_RDS",
+        "EventCode": "0x4",
+        "EventName": "UNC_UPI_TxL_HDR_MATCH.WB",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS",
-        "UMask": "0x1",
-        "Unit": "CHA"
+        "UMask": "0xc",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x39",
-        "EventName": "UNC_H_MISC.RFO_HIT_S",
+        "BriefDescription": "Tx Flit Buffer Allocations",
+        "EventCode": "0x40",
+        "EventName": "UNC_UPI_TxL_INSERTS",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S",
-        "UMask": "0x8",
-        "Unit": "CHA"
+        "PublicDescription": "Number of allocations into the UPI Tx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x50",
-        "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
+        "BriefDescription": "Tx Flit Buffer Occupancy",
+        "EventCode": "0x42",
+        "EventName": "UNC_UPI_TxL_OCCUPANCY",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL",
-        "UMask": "0x10",
-        "Unit": "CHA"
+        "PublicDescription": "Accumulates the number of flits in the TxQ.  Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x50",
-        "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
+        "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
+        "EventCode": "0x45",
+        "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x50",
-        "EventName": "UNC_H_REQUESTS.READS",
+        "BriefDescription": "VNA Credits Pending Return - Occupancy",
+        "EventCode": "0x44",
+        "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS",
-        "UMask": "0x3",
-        "Unit": "CHA"
+        "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.",
+        "Unit": "UPI LL"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS_LOCAL",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x50",
-        "EventName": "UNC_H_REQUESTS.READS_LOCAL",
+        "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
+        "EventCode": "0xff",
+        "EventName": "UNC_U_CLOCKTICKS",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS_LOCAL",
-        "UMask": "0x1",
-        "Unit": "CHA"
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x50",
-        "EventName": "UNC_H_REQUESTS.WRITES",
+        "BriefDescription": "Message Received",
+        "EventCode": "0x42",
+        "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES",
-        "UMask": "0xC",
-        "Unit": "CHA"
+        "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.",
+        "UMask": "0x8",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES_LOCAL",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x50",
-        "EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
+        "BriefDescription": "Message Received",
+        "EventCode": "0x42",
+        "EventName": "UNC_U_EVENT_MSG.INT_PRIO",
+        "PerPkg": "1",
+        "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.",
+        "UMask": "0x10",
+        "Unit": "UBOX"
+    },
+    {
+        "BriefDescription": "Message Received; IPI",
+        "EventCode": "0x42",
+        "EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES_LOCAL",
+        "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.; Inter Processor Interrupts",
         "UMask": "0x4",
-        "Unit": "CHA"
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x13",
-        "EventName": "UNC_H_RxC_INSERTS.IRQ",
+        "BriefDescription": "Message Received; MSI",
+        "EventCode": "0x42",
+        "EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
+        "PerPkg": "1",
+        "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.; Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)",
+        "UMask": "0x2",
+        "Unit": "UBOX"
+    },
+    {
+        "BriefDescription": "Message Received; VLW",
+        "EventCode": "0x42",
+        "EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ",
+        "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.",
         "UMask": "0x1",
-        "Unit": "CHA"
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x19",
-        "EventName": "UNC_H_RxC_IRQ1_REJECT.PA_MATCH",
+        "BriefDescription": "IDI Lock/SplitLock Cycles",
+        "EventCode": "0x44",
+        "EventName": "UNC_U_LOCK_CYCLES",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
-        "UMask": "0x80",
-        "Unit": "CHA"
+        "PublicDescription": "Number of times an IDI Lock/SplitLock sequence was started",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ",
-        "Deprecated": "1",
-        "EventCode": "0x11",
-        "EventName": "UNC_H_RxC_OCCUPANCY.IRQ",
+        "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
+        "EventCode": "0x45",
+        "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ",
+        "PublicDescription": "PHOLD cycles.",
         "UMask": "0x1",
-        "Unit": "CHA"
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5C",
-        "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
+        "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+        "EventCode": "0x4C",
+        "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD",
         "UMask": "0x4",
-        "Unit": "CHA"
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5C",
-        "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
+        "BriefDescription": "UNC_U_RACU_DRNG.RDRAND",
+        "EventCode": "0x4C",
+        "EventName": "UNC_U_RACU_DRNG.RDRAND",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD",
-        "UMask": "0x8",
-        "Unit": "CHA"
+        "UMask": "0x1",
+        "Unit": "UBOX"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB",
-        "Counter": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0x5C",
-        "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
+        "BriefDescription": "UNC_U_RACU_DRNG.RDSEED",
+        "EventCode": "0x4C",
+        "EventName": "UNC_U_RACU_DRNG.RDSEED",
         "PerPkg": "1",
-        "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB",
-        "UMask": "0x20",
-        "Unit": "CHA"
+        "UMask": "0x2",
+        "Unit": "UBOX"
+    },
+    {
+        "BriefDescription": "RACU Request",
+        "EventCode": "0x46",
+        "EventName": "UNC_U_RACU_REQUESTS",
+        "PerPkg": "1",
+        "PublicDescription": "Number outstanding register requests within message channel tracker",
+        "Unit": "UBOX"
+    },
+    {
+        "BriefDescription": "UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data",
+        "EventCode": "0x2",
+        "EventName": "UPI_DATA_BANDWIDTH_TX",
+        "PerPkg": "1",
+        "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel Ultra Path Interconnect (UPI) slots on this UPI unit.",
+        "ScaleUnit": "7.11E-06Bytes",
+        "UMask": "0xf",
+        "Unit": "UPI LL"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-power.json b/tools/perf/pmu-events/arch/x86/skylakex/uncore-power.json
index 64301a600ede7..8e21dc3eff161 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-power.json
@@ -1,14 +1,13 @@
 [
     {
         "BriefDescription": "pclk Cycles",
-        "Counter": "0,1,2,3",
         "EventName": "UNC_P_CLOCKTICKS",
         "PerPkg": "1",
+        "PublicDescription": "The PCU runs off a fixed 1 GHz clock.  This event counts the number of pclk cycles measured while the counter was enabled.  The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "UNC_P_CORE_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -16,7 +15,6 @@
     },
     {
         "BriefDescription": "UNC_P_DEMOTIONS",
-        "Counter": "0,1,2,3",
         "EventCode": "0x30",
         "EventName": "UNC_P_DEMOTIONS",
         "PerPkg": "1",
@@ -24,71 +22,70 @@
     },
     {
         "BriefDescription": "Phase Shed 0 Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x75",
         "EventName": "UNC_P_FIVR_PS_PS0_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Cycles spent in phase-shedding power state 0",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Phase Shed 1 Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x76",
         "EventName": "UNC_P_FIVR_PS_PS1_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Cycles spent in phase-shedding power state 1",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Phase Shed 2 Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x77",
         "EventName": "UNC_P_FIVR_PS_PS2_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Cycles spent in phase-shedding power state 2",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Phase Shed 3 Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x78",
         "EventName": "UNC_P_FIVR_PS_PS3_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Cycles spent in phase-shedding power state 3",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Thermal Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when thermal conditions are the upper limit on frequency.  This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature.  This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Power Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when power is the upper limit on frequency.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x73",
         "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower.  This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW.  This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Cycles spent changing Frequency",
-        "Counter": "0,1,2,3",
         "EventCode": "0x74",
         "EventName": "UNC_P_FREQ_TRANS_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the system is changing frequency.  This can not be filtered by thread ID.  One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "UNC_P_MCP_PROCHOT_CYCLES",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "UNC_P_MCP_PROCHOT_CYCLES",
         "PerPkg": "1",
@@ -96,47 +93,46 @@
     },
     {
         "BriefDescription": "Memory Phase Shedding Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2F",
         "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that the PCU has triggered memory phase shedding.  This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2A",
         "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the package was in C0.  This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C2E",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2B",
         "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the package was in C2E.  This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2C",
         "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the package was in C3.  This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C6",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2D",
         "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles when the package was in C6.  This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "UNC_P_PMAX_THROTTLED_CYCLES",
         "PerPkg": "1",
@@ -144,55 +140,54 @@
     },
     {
         "BriefDescription": "Number of cores in C-State; C0 and C1",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
         "PerPkg": "1",
+        "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Number of cores in C-State; C3",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
         "PerPkg": "1",
+        "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Number of cores in C-State; C6 and C7",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
         "PerPkg": "1",
+        "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "External Prochot",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA",
         "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that we are in external PROCHOT mode.  This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Internal Prochot",
-        "Counter": "0,1,2,3",
         "EventCode": "0x9",
         "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Counts the number of cycles that we are in Internal PROCHOT mode.  This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Total Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x72",
         "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Number of cycles spent performing core C state transitions across all cores.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "VR Hot",
-        "Counter": "0,1,2,3",
         "EventCode": "0x42",
         "EventName": "UNC_P_VR_HOT_CYCLES",
         "PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/virtual-memory.json b/tools/perf/pmu-events/arch/x86/skylakex/virtual-memory.json
index dd334b416c57d..f59405877ae8b 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/virtual-memory.json
@@ -1,8 +1,6 @@
 [
     {
         "BriefDescription": "Load misses in all DTLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
         "PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
@@ -11,8 +9,6 @@
     },
     {
         "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
         "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
@@ -21,8 +17,6 @@
     },
     {
         "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
@@ -32,8 +26,6 @@
     },
     {
         "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
         "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -42,8 +34,6 @@
     },
     {
         "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
         "PublicDescription": "Counts completed page walks  (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -52,8 +42,6 @@
     },
     {
         "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
         "PublicDescription": "Counts completed page walks  (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -62,8 +50,6 @@
     },
     {
         "BriefDescription": "Page walk completed due to a demand data load to a 4K page",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
         "PublicDescription": "Counts completed page walks  (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -72,8 +58,6 @@
     },
     {
         "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
         "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture.",
@@ -82,8 +66,6 @@
     },
     {
         "BriefDescription": "Store misses in all DTLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
         "PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
@@ -92,8 +74,6 @@
     },
     {
         "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT",
         "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
@@ -102,8 +82,6 @@
     },
     {
         "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
@@ -113,8 +91,6 @@
     },
     {
         "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
         "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -123,8 +99,6 @@
     },
     {
         "BriefDescription": "Page walk completed due to a demand data store to a 1G page",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
         "PublicDescription": "Counts completed page walks  (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -133,8 +107,6 @@
     },
     {
         "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
         "PublicDescription": "Counts completed page walks  (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -143,8 +115,6 @@
     },
     {
         "BriefDescription": "Page walk completed due to a demand data store to a 4K page",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
         "PublicDescription": "Counts completed page walks  (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -153,8 +123,6 @@
     },
     {
         "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
         "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture.",
@@ -163,8 +131,6 @@
     },
     {
         "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x4f",
         "EventName": "EPT.WALK_PENDING",
         "PublicDescription": "Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type.",
@@ -173,8 +139,6 @@
     },
     {
         "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xAE",
         "EventName": "ITLB.ITLB_FLUSH",
         "PublicDescription": "Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
@@ -183,8 +147,6 @@
     },
     {
         "BriefDescription": "Misses at all ITLB levels that cause page walks",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
         "PublicDescription": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed.",
@@ -193,8 +155,6 @@
     },
     {
         "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT",
         "SampleAfterValue": "100003",
@@ -202,8 +162,6 @@
     },
     {
         "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_ACTIVE",
@@ -213,8 +171,6 @@
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
         "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -223,8 +179,6 @@
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
         "PublicDescription": "Counts completed page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -233,8 +187,6 @@
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
         "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -243,8 +195,6 @@
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
         "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -253,8 +203,6 @@
     },
     {
         "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_PENDING",
         "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.",
@@ -263,8 +211,6 @@
     },
     {
         "BriefDescription": "DTLB flush attempts of the thread-specific entries",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.DTLB_THREAD",
         "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
@@ -273,8 +219,6 @@
     },
     {
         "BriefDescription": "STLB flush attempts",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
         "EventCode": "0xBD",
         "EventName": "TLB_FLUSH.STLB_ANY",
         "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
-- 
GitLab


From 9b4240831af775ef0730a2fb8f529b4a66d4fc46 Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:55:06 -0800
Subject: [PATCH 590/875] perf vendor events intel: Refresh snowridgex events

Update the snowridgex events using the new tooling from:

  https://github.com/intel/perfmon

The events are unchanged but unused json values are removed and
descriptions improved. This increases consistency across the json
files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-20-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../pmu-events/arch/x86/snowridgex/cache.json |   252 -
 .../arch/x86/snowridgex/floating-point.json   |    11 -
 .../arch/x86/snowridgex/frontend.json         |    36 -
 .../arch/x86/snowridgex/memory.json           |    84 -
 .../pmu-events/arch/x86/snowridgex/other.json |   143 -
 .../arch/x86/snowridgex/pipeline.json         |   213 -
 .../arch/x86/snowridgex/uncore-memory.json    |   624 +-
 .../arch/x86/snowridgex/uncore-other.json     | 26334 +++++++---------
 .../arch/x86/snowridgex/uncore-power.json     |   114 +-
 .../arch/x86/snowridgex/virtual-memory.json   |   117 -
 10 files changed, 11934 insertions(+), 15994 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/cache.json b/tools/perf/pmu-events/arch/x86/snowridgex/cache.json
index d674ee88c3a5d..0ab90e3bf76b0 100644
--- a/tools/perf/pmu-events/arch/x86/snowridgex/cache.json
+++ b/tools/perf/pmu-events/arch/x86/snowridgex/cache.json
@@ -1,1137 +1,885 @@
 [
     {
         "BriefDescription": "Counts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a full condition.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x31",
         "EventName": "CORE_REJECT_L2Q.ANY",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L2Q.  It also counts requests that would have gone directly to the External Queue (XQ), but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link.  The L2Q may also reject transactions  from a core to ensure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops.  (Note that L2 prefetcher requests that are dropped are not counted by this event).  Counts on a per core basis.",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x51",
         "EventName": "DL1.DIRTY_EVICTION",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.  Does not count evictions or dirty writebacks caused by snoops.  Does not count a replacement unless a (dirty) line was written back.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_XQ.ANY",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link.  The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims).",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_REQUEST.ALL",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects  front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only.  Counts on a per core basis.",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_REQUEST.HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front door request only (does not include rejects or recycles), Counts on a per core basis.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_REQUEST.MISS",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of L2 Cache accesses that resulted in a miss from a front door request only (does not include rejects or recycles). Counts on a per core basis.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of L2 Cache accesses that miss the L2 and get rejected. Counts on a per core basis.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_REQUEST.REJECTS",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of L2 Cache accesses that miss the L2 and get BBL reject  short and long rejects (includes those counted in L2_reject_XQ.any). Counts on a per core basis.",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2e",
         "EventName": "LONGEST_LAT_CACHE.MISS",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
         "SampleAfterValue": "200003",
         "UMask": "0x41"
     },
     {
         "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2e",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
         "SampleAfterValue": "200003",
         "UMask": "0x4f"
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "MEM_BOUND_STALLS.IFETCH",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x38"
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM).",
         "SampleAfterValue": "200003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.",
         "SampleAfterValue": "200003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
         "SampleAfterValue": "200003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "MEM_BOUND_STALLS.LOAD",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x7"
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to a store buffer being full.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "MEM_BOUND_STALLS.STORE_BUFFER_FULL",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Counts the number of load uops retired that hit in DRAM.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache, in which a snoop was required and modified data was forwarded from another core or module.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.HITM",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Counts the number of load uops retired that hit in the L1 data cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of load uops retired that miss in the L1 data cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of load uops retired that miss in the L2 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of memory uops retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.ALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of memory uops retired.  A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST)",
         "SampleAfterValue": "200003",
         "UMask": "0x83"
     },
     {
         "BriefDescription": "Counts the number of load uops retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of load uops retired.",
         "SampleAfterValue": "200003",
         "UMask": "0x81"
     },
     {
         "BriefDescription": "Counts the number of store uops retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of store uops retired.",
         "SampleAfterValue": "200003",
         "UMask": "0x82"
     },
     {
         "BriefDescription": "Counts the number of load uops retired that performed one or more locks.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x21"
     },
     {
         "BriefDescription": "Counts the number of memory uops retired that were splits.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x43"
     },
     {
         "BriefDescription": "Counts the number of retired split load uops.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x41"
     },
     {
         "BriefDescription": "Counts the number of retired split store uops.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x42"
     },
     {
         "BriefDescription": "Counts all code reads that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1F803C0044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.COREWB_M.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3001F803C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1F803C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1F803C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1F803C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1F803C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.FULL_STREAMING_WR.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x801F803C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1F803C0040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1F803C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1F803C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.L1WB_M.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1001F803C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.L2WB_M.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2001F803C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.PARTIAL_STREAMING_WR.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x401F803C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1F803C0477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003C0477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003C0477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003C0477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.STREAMING_WR.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1F803C0800",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x101F803C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010003C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004003C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1008003C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent but the snoop missed.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1002003C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where no snoop was needed to satisfy the request.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.L3_HIT.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1001003C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory writes that were supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_WR.L3_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x201F803C0000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "TOPDOWN_FE_BOUND.ICACHE",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x20"
     }
diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/floating-point.json b/tools/perf/pmu-events/arch/x86/snowridgex/floating-point.json
index 2e1b80c714fd8..88522244b7609 100644
--- a/tools/perf/pmu-events/arch/x86/snowridgex/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/snowridgex/floating-point.json
@@ -1,36 +1,25 @@
 [
     {
         "BriefDescription": "Counts the number of cycles the floating point divider is busy.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xcd",
         "EventName": "CYCLES_DIV_BUSY.FPDIV",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles the floating point divider is busy.  Does not imply a stall waiting for the divider.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.FP_ASSIST",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",
         "SampleAfterValue": "20003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.FPDIV",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "2000003",
         "UMask": "0x8"
     }
diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/frontend.json b/tools/perf/pmu-events/arch/x86/snowridgex/frontend.json
index 5d938a5dafcf9..5ba998e06592c 100644
--- a/tools/perf/pmu-events/arch/x86/snowridgex/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/snowridgex/frontend.json
@@ -1,103 +1,67 @@
 [
     {
         "BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xe6",
         "EventName": "BACLEARS.ANY",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend.  Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of BACLEARS due to a conditional jump.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xe6",
         "EventName": "BACLEARS.COND",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts the number of BACLEARS due to an indirect branch.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xe6",
         "EventName": "BACLEARS.INDIRECT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of BACLEARS due to a return branch.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xe6",
         "EventName": "BACLEARS.RETURN",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts the number of BACLEARS due to a direct, unconditional jump.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xe6",
         "EventName": "BACLEARS.UNCOND",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of times a decode restriction reduces the decode throughput due to wrong instruction length prediction.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xe9",
         "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "ICACHE.ACCESSES",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of requests to the instruction cache.  The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one.  Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
         "SampleAfterValue": "200003",
         "UMask": "0x3"
     },
     {
         "BriefDescription": "Counts the number of instruction cache hits.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "ICACHE.HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of requests that hit in the instruction cache.  The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one.  Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of instruction cache misses.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "ICACHE.MISSES",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of missed requests to the instruction cache.  The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one.  Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/memory.json b/tools/perf/pmu-events/arch/x86/snowridgex/memory.json
index 15eba23796e4b..18621909d1a90 100644
--- a/tools/perf/pmu-events/arch/x86/snowridgex/memory.json
+++ b/tools/perf/pmu-events/arch/x86/snowridgex/memory.json
@@ -1,441 +1,357 @@
 [
     {
         "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "20003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of misaligned load uops that are 4K page splits.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of misaligned store uops that are 4K page splits.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.COREWB_M.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3002184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.COREWB_M.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3002184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.FULL_STREAMING_WR.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x802184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.FULL_STREAMING_WR.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x802184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.L1WB_M.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1002184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.L1WB_M.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1002184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.L2WB_M.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2002184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.L2WB_M.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2002184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.OTHER.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.OTHER.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184008000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x402184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x402184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all hardware and software prefetches that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.PREFETCHES.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000470",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.STREAMING_WR.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000800",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2184000800",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x102184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x102184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_WR.L3_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x202184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_WR.L3_MISS_LOCAL",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x202184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     }
diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/other.json b/tools/perf/pmu-events/arch/x86/snowridgex/other.json
index 4a1b7cc5aa23c..00ae180ded25c 100644
--- a/tools/perf/pmu-events/arch/x86/snowridgex/other.json
+++ b/tools/perf/pmu-events/arch/x86/snowridgex/other.json
@@ -1,674 +1,531 @@
 [
     {
         "BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.SELF_LOCKS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EdgeDetect": "1",
         "EventCode": "0x63",
         "EventName": "BUS_LOCK.ALL",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x63",
         "EventName": "BUS_LOCK.BLOCK_CYCLES",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores. Counts on a per core basis.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.BLOCK_CYCLES",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x63",
         "EventName": "BUS_LOCK.CYCLES_OTHER_BLOCK",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.LOCK_CYCLES",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x63",
         "EventName": "BUS_LOCK.CYCLES_SELF_BLOCK",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x63",
         "EventName": "BUS_LOCK.LOCK_CYCLES",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued. Counts on a per core basis.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EdgeDetect": "1",
         "EventCode": "0x63",
         "EventName": "BUS_LOCK.SELF_LOCKS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks. Counts on a per core basis.",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_DRAM_HIT",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "C0_STALLS.LOAD_DRAM_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_L2_HIT",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "C0_STALLS.LOAD_L2_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_LLC_HIT",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x34",
         "EventName": "C0_STALLS.LOAD_LLC_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of core cycles during which interrupts are masked (disabled).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xcb",
         "EventName": "HW_INTERRUPTS.MASKED",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xcb",
         "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled). Increments by 1 each core cycle that both EFLAGS.IF is 0 and an INTR is pending (which means the APIC is telling the ROB to cause an INTR). This event does not increment if EFLAGS.IF is 0 but all interrupt in the APICs Interrupt Request Register (IRR) are inhibited by the PPR (thus either by ISRV or TPR)  because in these cases the interrupts would be held up in the APIC and would not be pended to the ROB. This event does count when an interrupt is only inhibited by MOV/POP SS state machines or the STI state machine. These extra inhibits only last for a single instructions and would not be important.",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of hardware interrupts received by the processor.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xcb",
         "EventName": "HW_INTERRUPTS.RECEIVED",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "203",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all code reads that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all code reads that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all code reads that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all code reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.ALL_CODE_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x8000000000000044",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.COREWB_M.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3000000010000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.COREWB_M.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x8003000000000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_CODE_RD.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000004",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x8000000000000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_DATA_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x8000000000000001",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.DEMAND_RFO.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x8000000000000002",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.FULL_STREAMING_WR.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x800000010000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10400",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_CODE_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x8000000000000040",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_DATA_RD.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000010",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.HWPF_L2_RFO.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x8000000000000020",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.L1WB_M.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1000000010000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.L2WB_M.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2000000010000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.OTHER.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x18000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x400000010000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all hardware and software prefetches that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.PREFETCHES.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10470",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x184000477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.READS_TO_CORE.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x8000000000000477",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts streaming stores that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10800",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100000010000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that were supplied by DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x100184000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_RD.OUTSTANDING",
         "MSRIndex": "0x1a6",
         "MSRValue": "0x8000100000000000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts uncached memory writes that have any type of response.",
-        "Counter": "0,1,2,3",
         "EventCode": "0XB7",
         "EventName": "OCR.UC_WR.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x200000010000",
-        "Offcore": "1",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     }
diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/pipeline.json b/tools/perf/pmu-events/arch/x86/snowridgex/pipeline.json
index 09919fdb9a381..9dd8c909faccf 100644
--- a/tools/perf/pmu-events/arch/x86/snowridgex/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/snowridgex/pipeline.json
@@ -1,662 +1,449 @@
 [
     {
         "BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires.  All branch type instructions are accounted for.",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Counts the number of near CALL branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.CALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0xf9"
     },
     {
         "BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.FAR_BRANCH",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0xbf"
     },
     {
         "BriefDescription": "Counts the number of near indirect CALL branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.IND_CALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0xfb"
     },
     {
         "BriefDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.JCC",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x7e"
     },
     {
         "BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.NON_RETURN_IND",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0xeb"
     },
     {
         "BriefDescription": "Counts the number of near relative CALL branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.REL_CALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0xfd"
     },
     {
         "BriefDescription": "Counts the number of near RET branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.RETURN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0xf7"
     },
     {
         "BriefDescription": "Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.TAKEN_JCC",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0xfe"
     },
     {
         "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of mispredicted branch instructions retired.  All branch type instructions are accounted for.  Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP.    A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.IND_CALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0xfb"
     },
     {
         "BriefDescription": "Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.JCC",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x7e"
     },
     {
         "BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0xeb"
     },
     {
         "BriefDescription": "Counts the number of mispredicted near RET branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.RETURN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0xf7"
     },
     {
         "BriefDescription": "Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.TAKEN_JCC",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0xfe"
     },
     {
         "BriefDescription": "Counts the total number of BTCLEARS.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xe8",
         "EventName": "BTCLEAR.ANY",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.CORE",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "33",
         "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of unhalted core clock cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_UNHALTED.CORE_P",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_UNHALTED.REF",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 2",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "34",
         "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
         "SampleAfterValue": "2000003",
         "UMask": "0x3"
     },
     {
         "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "This event is deprecated.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xcd",
         "EventName": "CYCLES_DIV_BUSY.ANY",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Counts the number of cycles the integer divider is busy.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xcd",
         "EventName": "CYCLES_DIV_BUSY.IDIV",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles the integer divider is busy.  Does not imply a stall waiting for the divider.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the total number of instructions retired. (Fixed event)",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 0",
         "EventName": "INST_RETIRED.ANY",
         "PEBS": "1",
-        "PEBScounters": "32",
         "PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the total number of instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc0",
         "EventName": "INST_RETIRED.ANY_P",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter.",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.4K_ALIAS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of retired loads that are blocked for any of the following reasons:  DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.ALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.DATA_UNKNOWN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of retired loads that are blocked because its address partially overlapped with an older store.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.STORE_FORWARD",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assist.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.ANY",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "20003"
     },
     {
         "BriefDescription": "Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.DISAMBIGUATION",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "20003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts the number of machine clears due to a page fault.  Counts both I-Side and D-Side (Loads/Stores) page faults.  A page fault occurs when either the page is not present, or an access violation occurs.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.PAGE_FAULT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "20003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.SMC",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "20003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x73",
         "EventName": "TOPDOWN_BAD_SPECULATION.ALL",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
         "SampleAfterValue": "1000003",
         "UMask": "0x6"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x73",
         "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x73",
         "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS",
-        "PDIR_COUNTER": "na",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x73",
         "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x73",
         "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x74",
         "EventName": "TOPDOWN_BE_BOUND.ALL",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x74",
         "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x74",
         "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x74",
         "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x74",
         "EventName": "TOPDOWN_BE_BOUND.REGISTER",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x74",
         "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x74",
         "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "This event is deprecated.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x74",
         "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to frontend stalls.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "TOPDOWN_FE_BOUND.ALL",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
         "SampleAfterValue": "1000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
         "SampleAfterValue": "1000003",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "TOPDOWN_FE_BOUND.CISC",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "TOPDOWN_FE_BOUND.DECODE",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "TOPDOWN_FE_BOUND.ITLB",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.",
         "SampleAfterValue": "1000003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "TOPDOWN_FE_BOUND.OTHER",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x71",
         "EventName": "TOPDOWN_FE_BOUND.PREDECODE",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the total number of consumed retirement slots.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc2",
         "EventName": "TOPDOWN_RETIRING.ALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003"
     },
     {
         "BriefDescription": "Counts the number of uops issued by the front end every cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x0e",
         "EventName": "UOPS_ISSUED.ANY",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2.  Uops_issued correlates to the number of ROB entries.  If uop takes 2 ROB slots it counts as 2 uops_issued.",
         "SampleAfterValue": "200003"
     },
     {
         "BriefDescription": "Counts the total number of uops retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.ALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Counts the number of integer divide uops retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.IDIV",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "2000003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.MS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of x87 uops retired, includes those in MS flows.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.X87",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     }
diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json
index f2c17f19299f4..7dc0910694ed2 100644
--- a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json
@@ -1,619 +1,545 @@
 [
-    {
-        "BriefDescription": "Pre-charge for reads",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_M_PRE_COUNT.RD",
-        "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "Pre-charge for writes",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_M_PRE_COUNT.WR",
-        "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "iMC"
-    },
     {
         "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x04",
         "EventName": "LLC_MISSES.MEM_READ",
         "PerPkg": "1",
+        "PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issued on this channel.  This includes underfills.",
         "ScaleUnit": "64Bytes",
-        "UMask": "0x0f",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "read requests to memory controller",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
         "EventCode": "0x04",
-        "EventName": "UNC_M_CAS_COUNT.RD",
+        "EventName": "LLC_MISSES.MEM_WRITE",
         "PerPkg": "1",
+        "PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel.",
         "ScaleUnit": "64Bytes",
-        "UMask": "0x0f",
+        "UMask": "0x30",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "LLC_MISSES.MEM_WRITE",
+        "BriefDescription": "DRAM Activate Count : All Activates",
+        "EventCode": "0x01",
+        "EventName": "UNC_M_ACT_COUNT.ALL",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x30",
+        "PublicDescription": "DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+        "UMask": "0xb",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "write requests to memory controller",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_M_CAS_COUNT.WR",
+        "BriefDescription": "DRAM Activate Count : Activate due to Bypass",
+        "EventCode": "0x01",
+        "EventName": "UNC_M_ACT_COUNT.BYP",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0x30",
+        "PublicDescription": "DRAM Activate Count : Activate due to Bypass : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "All DRAM CAS commands issued",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x04",
         "EventName": "UNC_M_CAS_COUNT.ALL",
         "PerPkg": "1",
+        "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.",
         "UMask": "0x3f",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Number of DRAM Refreshes Issued",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M_DRAM_REFRESH.OPPORTUNISTIC",
+        "BriefDescription": "All DRAM read CAS commands issued (including underfills)",
+        "EventCode": "0x04",
+        "EventName": "UNC_M_CAS_COUNT.RD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issued on this channel.  This includes underfills.",
+        "UMask": "0xf",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Number of DRAM Refreshes Issued",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M_DRAM_REFRESH.PANIC",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
+        "EventCode": "0x04",
+        "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the total number or DRAM Read CAS commands issued on this channel.  This includes both regular RD CAS commands as well as those with explicit Precharge.  AutoPre is only used in systems that are using closed page policy.  We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Number of DRAM Refreshes Issued",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M_DRAM_REFRESH.HIGH",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.",
+        "EventCode": "0x04",
+        "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Pending Queue Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_M_RPQ_INSERTS.PCH0",
+        "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)",
+        "EventCode": "0x04",
+        "EventName": "UNC_M_CAS_COUNT.RD_REG",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the total number of DRAM Read CAS commands issued on this channel.  This includes both regular RD CAS commands as well as those with implicit Precharge.   We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Pending Queue Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_M_RPQ_INSERTS.PCH1",
+        "BriefDescription": "DRAM underfill read CAS commands issued",
+        "EventCode": "0x04",
+        "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts the total of DRAM Read CAS commands issued due to an underfill",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_M_WPQ_INSERTS.PCH0",
+        "BriefDescription": "All DRAM write CAS commands issued",
+        "EventCode": "0x04",
+        "EventName": "UNC_M_CAS_COUNT.WR",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel.",
+        "UMask": "0x30",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_M_WPQ_INSERTS.PCH1",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre",
+        "EventCode": "0x04",
+        "EventName": "UNC_M_CAS_COUNT.WR_NONPRE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge commands. : Precharge due to page table",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_M_PRE_COUNT.PGT",
+        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre",
+        "EventCode": "0x04",
+        "EventName": "UNC_M_CAS_COUNT.WR_PRE",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre : DRAM RD_CAS and WR_CAS Commands",
+        "UMask": "0x20",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Memory controller clock ticks",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventName": "UNC_M_CLOCKTICKS",
         "PerPkg": "1",
+        "PublicDescription": "Clockticks of the integrated memory controller (IMC)",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Half clockticks for IMC",
-        "Counter": "FIXED",
-        "CounterType": "FIXED",
-        "EventCode": "0xff",
-        "EventName": "UNC_M_HCLOCKTICKS",
-        "PerPkg": "1",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "Read Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0",
-        "PerPkg": "1",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "Read Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x81",
-        "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1",
-        "PerPkg": "1",
-        "Unit": "iMC"
-    },
-    {
-        "BriefDescription": "Write Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0",
+        "BriefDescription": "Free running counter that increments for the Memory Controller",
+        "EventName": "UNC_M_CLOCKTICKS_FREERUN",
         "PerPkg": "1",
+        "PublicDescription": "UNC_M_CLOCKTICKS_FREERUN",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1",
+        "BriefDescription": "DRAM Precharge All Commands",
+        "EventCode": "0x44",
+        "EventName": "UNC_M_DRAM_PRE_ALL",
         "PerPkg": "1",
+        "PublicDescription": "DRAM Precharge All Commands : Counts the number of times that the precharge all command was sent.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Activate Count : All Activates",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x01",
-        "EventName": "UNC_M_ACT_COUNT.ALL",
+        "BriefDescription": "Number of DRAM Refreshes Issued",
+        "EventCode": "0x45",
+        "EventName": "UNC_M_DRAM_REFRESH.HIGH",
         "PerPkg": "1",
-        "UMask": "0x0B",
+        "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge commands",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_M_PRE_COUNT.ALL",
+        "BriefDescription": "Number of DRAM Refreshes Issued",
+        "EventCode": "0x45",
+        "EventName": "UNC_M_DRAM_REFRESH.OPPORTUNISTIC",
         "PerPkg": "1",
-        "UMask": "0x1C",
+        "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Data Buffer Inserts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x17",
-        "EventName": "UNC_M_RDB_INSERTS",
+        "BriefDescription": "Number of DRAM Refreshes Issued",
+        "EventCode": "0x45",
+        "EventName": "UNC_M_DRAM_REFRESH.PANIC",
         "PerPkg": "1",
+        "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_M_CAS_COUNT.RD_REG",
+        "BriefDescription": "Half clockticks for IMC",
+        "EventCode": "0xff",
+        "EventName": "UNC_M_HCLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x01",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM underfill read CAS commands issued",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
+        "BriefDescription": "UNC_M_PARITY_ERRORS",
+        "EventCode": "0x2c",
+        "EventName": "UNC_M_PARITY_ERRORS",
         "PerPkg": "1",
-        "UMask": "0x04",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Activate Count : Activate due to Bypass",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x01",
-        "EventName": "UNC_M_ACT_COUNT.BYP",
+        "BriefDescription": "UNC_M_PCLS.RD",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M_PCLS.RD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG",
+        "BriefDescription": "UNC_M_PCLS.TOTAL",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M_PCLS.TOTAL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL",
+        "BriefDescription": "UNC_M_PCLS.WR",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M_PCLS.WR",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_M_CAS_COUNT.WR_PRE",
+        "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode",
+        "EventCode": "0x85",
+        "EventName": "UNC_M_POWER_CHANNEL_PPD",
+        "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100",
+        "MetricName": "power_channel_ppd",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Channel PPD Cycles : Number of cycles when all the ranks in the channel are in PPD mode.  If IBT=off is enabled, then this can be used to count those cycles.  If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x47",
         "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x47",
         "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x47",
         "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x47",
         "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x86",
         "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. : Thermal throttling is performed per DIMM.  We support 3 DIMMs per channel.  This ID allows us to filter by ID.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x86",
         "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+        "UMask": "0x2",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Cycles Memory is in self refresh power mode",
+        "EventCode": "0x43",
+        "EventName": "UNC_M_POWER_SELF_REFRESH",
+        "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100",
+        "MetricName": "power_self_refresh",
+        "PerPkg": "1",
+        "PublicDescription": "Clock-Enabled Self-Refresh : Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock.  This happens in some package C-states.  For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing.  One use of this is for Monroe technology.  Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x46",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. : Thermal throttling is performed per DIMM.  We support 3 DIMMs per channel.  This ID allows us to filter by ID.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
         "BriefDescription": "Throttle Cycles for Rank 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x46",
         "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Pending Queue Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M_RPQ_CYCLES_NE.PCH0",
+        "BriefDescription": "DRAM Precharge commands.",
+        "EventCode": "0x02",
+        "EventName": "UNC_M_PRE_COUNT.ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
+        "UMask": "0x1c",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Pending Queue Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M_RPQ_CYCLES_NE.PCH1",
+        "BriefDescription": "Pre-charges due to page misses",
+        "EventCode": "0x02",
+        "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "DRAM Precharge commands. : Precharge due to page miss : Counts the number of DRAM Precharge commands sent on this channel. : Pages Misses are due to precharges from bank scheduler (rd/wr requests)",
+        "UMask": "0xc",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_M_WPQ_CYCLES_NE.PCH0",
+        "BriefDescription": "DRAM Precharge commands. : Precharge due to page table",
+        "EventCode": "0x02",
+        "EventName": "UNC_M_PRE_COUNT.PGT",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel. : Prechages from Page Table",
+        "UMask": "0x10",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_M_WPQ_CYCLES_NE.PCH1",
+        "BriefDescription": "Pre-charge for reads",
+        "EventCode": "0x02",
+        "EventName": "UNC_M_PRE_COUNT.RD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler",
+        "UMask": "0x4",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue CAM Match",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M_WPQ_READ_HIT.PCH0",
+        "BriefDescription": "Pre-charge for writes",
+        "EventCode": "0x02",
+        "EventName": "UNC_M_PRE_COUNT.WR",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler",
+        "UMask": "0x8",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue CAM Match",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M_WPQ_READ_HIT.PCH1",
+        "BriefDescription": "Read Data Buffer Full",
+        "EventCode": "0x19",
+        "EventName": "UNC_M_RDB_FULL",
         "PerPkg": "1",
-        "UMask": "0x02",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue CAM Match",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_M_WPQ_WRITE_HIT.PCH0",
+        "BriefDescription": "Read Data Buffer Inserts",
+        "EventCode": "0x17",
+        "EventName": "UNC_M_RDB_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x01",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue CAM Match",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_M_WPQ_WRITE_HIT.PCH1",
+        "BriefDescription": "Read Data Buffer Not Empty",
+        "EventCode": "0x18",
+        "EventName": "UNC_M_RDB_NOT_EMPTY",
         "PerPkg": "1",
-        "UMask": "0x02",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "UNC_M_PCLS.RD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M_PCLS.RD",
+        "BriefDescription": "Read Data Buffer Occupancy",
+        "EventCode": "0x1A",
+        "EventName": "UNC_M_RDB_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x01",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "UNC_M_PCLS.WR",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M_PCLS.WR",
+        "BriefDescription": "Read Pending Queue Full Cycles",
+        "EventCode": "0x12",
+        "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Read Pending Queue Full Cycles : Counts the number of cycles when the Read Pending Queue is full.  When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead.  We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM.  This event only tracks non-ISOC queue entries.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "UNC_M_PCLS.TOTAL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M_PCLS.TOTAL",
+        "BriefDescription": "Read Pending Queue Full Cycles",
+        "EventCode": "0x15",
+        "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Read Pending Queue Full Cycles : Counts the number of cycles when the Read Pending Queue is full.  When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead.  We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM.  This event only tracks non-ISOC queue entries.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM Precharge All Commands",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M_DRAM_PRE_ALL",
+        "BriefDescription": "Read Pending Queue Not Empty",
+        "EventCode": "0x11",
+        "EventName": "UNC_M_RPQ_CYCLES_NE.PCH0",
         "PerPkg": "1",
+        "PublicDescription": "Read Pending Queue Not Empty : Counts the number of cycles that the Read Pending Queue is not empty.  This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "UNC_M_PARITY_ERRORS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2c",
-        "EventName": "UNC_M_PARITY_ERRORS",
+        "BriefDescription": "Read Pending Queue Not Empty",
+        "EventCode": "0x11",
+        "EventName": "UNC_M_RPQ_CYCLES_NE.PCH1",
         "PerPkg": "1",
+        "PublicDescription": "Read Pending Queue Not Empty : Counts the number of cycles that the Read Pending Queue is not empty.  This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_M_POWER_CHANNEL_PPD",
-        "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.",
-        "MetricName": "power_channel_ppd %",
+        "BriefDescription": "Read Pending Queue Allocations",
+        "EventCode": "0x10",
+        "EventName": "UNC_M_RPQ_INSERTS.PCH0",
         "PerPkg": "1",
+        "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Cycles Memory is in self refresh power mode",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_M_POWER_SELF_REFRESH",
-        "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100.",
-        "MetricName": "power_self_refresh %",
+        "BriefDescription": "Read Pending Queue Allocations",
+        "EventCode": "0x10",
+        "EventName": "UNC_M_RPQ_INSERTS.PCH1",
         "PerPkg": "1",
+        "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Data Buffer Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_M_RDB_FULL",
+        "BriefDescription": "Read Pending Queue Occupancy",
+        "EventCode": "0x80",
+        "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0",
         "PerPkg": "1",
+        "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle.  This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Data Buffer Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_M_RDB_NOT_EMPTY",
+        "BriefDescription": "Read Pending Queue Occupancy",
+        "EventCode": "0x81",
+        "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1",
         "PerPkg": "1",
+        "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle.  This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Data Buffer Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1A",
-        "EventName": "UNC_M_RDB_OCCUPANCY",
+        "BriefDescription": "Write Pending Queue Full Cycles",
+        "EventCode": "0x22",
+        "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH0",
         "PerPkg": "1",
+        "PublicDescription": "Write Pending Queue Full Cycles : Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC.  This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Pending Queue Full Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH0",
+        "BriefDescription": "Write Pending Queue Full Cycles",
+        "EventCode": "0x16",
+        "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH1",
         "PerPkg": "1",
+        "PublicDescription": "Write Pending Queue Full Cycles : Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC.  This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Read Pending Queue Full Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH1",
+        "BriefDescription": "Write Pending Queue Not Empty",
+        "EventCode": "0x21",
+        "EventName": "UNC_M_WPQ_CYCLES_NE.PCH0",
         "PerPkg": "1",
+        "PublicDescription": "Write Pending Queue Not Empty : Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Full Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x22",
-        "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH0",
+        "BriefDescription": "Write Pending Queue Not Empty",
+        "EventCode": "0x21",
+        "EventName": "UNC_M_WPQ_CYCLES_NE.PCH1",
         "PerPkg": "1",
+        "PublicDescription": "Write Pending Queue Not Empty : Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Write Pending Queue Full Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x16",
-        "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH1",
+        "BriefDescription": "Write Pending Queue Allocations",
+        "EventCode": "0x20",
+        "EventName": "UNC_M_WPQ_INSERTS.PCH0",
         "PerPkg": "1",
+        "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue.  This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.",
+        "UMask": "0x1",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_M_CAS_COUNT.WR_NONPRE",
+        "BriefDescription": "Write Pending Queue Allocations",
+        "EventCode": "0x20",
+        "EventName": "UNC_M_WPQ_INSERTS.PCH1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue.  This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.",
+        "UMask": "0x2",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Pre-charges due to page misses",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+        "BriefDescription": "Write Pending Queue Occupancy",
+        "EventCode": "0x82",
+        "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0",
         "PerPkg": "1",
-        "UMask": "0x0c",
+        "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle.  This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.  So, we provide filtering based on if the request has posted or not.  By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA.  The posted filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory.  High average occupancies will generally coincide with high write major mode counts.",
         "Unit": "iMC"
     },
     {
-        "BriefDescription": "Free running counter that increments for the Memory Controller",
-        "Counter": "4",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_M_CLOCKTICKS_FREERUN",
+        "BriefDescription": "Write Pending Queue Occupancy",
+        "EventCode": "0x83",
+        "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1",
+        "PerPkg": "1",
+        "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle.  This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.  So, we provide filtering based on if the request has posted or not.  By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA.  The posted filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory.  High average occupancies will generally coincide with high write major mode counts.",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Write Pending Queue CAM Match",
+        "EventCode": "0x23",
+        "EventName": "UNC_M_WPQ_READ_HIT.PCH0",
+        "PerPkg": "1",
+        "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+        "UMask": "0x1",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Write Pending Queue CAM Match",
+        "EventCode": "0x23",
+        "EventName": "UNC_M_WPQ_READ_HIT.PCH1",
+        "PerPkg": "1",
+        "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+        "UMask": "0x2",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Write Pending Queue CAM Match",
+        "EventCode": "0x24",
+        "EventName": "UNC_M_WPQ_WRITE_HIT.PCH0",
+        "PerPkg": "1",
+        "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+        "UMask": "0x1",
+        "Unit": "iMC"
+    },
+    {
+        "BriefDescription": "Write Pending Queue CAM Match",
+        "EventCode": "0x24",
+        "EventName": "UNC_M_WPQ_WRITE_HIT.PCH1",
         "PerPkg": "1",
+        "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+        "UMask": "0x2",
         "Unit": "iMC"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json
index 1701db46696db..3b35e08e24d6b 100644
--- a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json
@@ -1,25060 +1,21961 @@
 [
     {
-        "BriefDescription": "Uncore cache clock ticks",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventName": "UNC_CHA_CLOCKTICKS",
+        "BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.ia_miss",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.MMIO_READ",
+        "Filter": "config1=0x40040e33",
         "PerPkg": "1",
+        "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Normal priority reads issued to the memory controller from the CHA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x59",
-        "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL",
+        "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.MMIO_WRITE",
+        "Filter": "config1=0x40041e33",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5B",
-        "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL",
+        "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0",
+        "EventCode": "0x83",
+        "EventName": "LLC_MISSES.PCIE_READ",
+        "FCMask": "0x07",
+        "Filter": "ch_mask=0x1f",
+        "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
+        "MetricName": "LLC_MISSES.PCIE_READ",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "ScaleUnit": "4Bytes",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Lines Victimized : All Lines Victimized",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.ALL",
+        "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0",
+        "EventCode": "0x83",
+        "EventName": "LLC_MISSES.PCIE_WRITE",
+        "FCMask": "0x07",
+        "Filter": "ch_mask=0x1f",
+        "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
+        "MetricName": "LLC_MISSES.PCIE_WRITE",
         "PerPkg": "1",
-        "UMask": "0x0F",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "ScaleUnit": "4Bytes",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.READS",
+        "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss",
+        "EventCode": "0x35",
+        "EventName": "LLC_MISSES.UNCACHEABLE",
+        "Filter": "config1=0x40e33",
         "PerPkg": "1",
-        "UMask": "0x03",
+        "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Local write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.WRITES",
+        "BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss",
+        "EventCode": "0x35",
+        "EventName": "LLC_REFERENCES.STREAMING_FULL",
+        "Filter": "config1=0x41833",
         "PerPkg": "1",
-        "UMask": "0x0c",
+        "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0xc001fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop filter capacity evictions for E-state entries",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x3D",
-        "EventName": "UNC_CHA_SF_EVICTION.E_STATE",
+        "BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss",
+        "EventCode": "0x35",
+        "EventName": "LLC_REFERENCES.STREAMING_PARTIAL",
+        "Filter": "config1=0x41a33",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "ScaleUnit": "64Bytes",
+        "UMask": "0xc001fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop filter capacity evictions for M-state entries",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x3D",
-        "EventName": "UNC_CHA_SF_EVICTION.M_STATE",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop filter capacity evictions for S-state entries",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x3D",
-        "EventName": "UNC_CHA_SF_EVICTION.S_STATE",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All requests from iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0xC001FF01",
-        "UMaskExt": "0xC001FF",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0xC001FD01",
-        "UMaskExt": "0xC001FD",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
-        "UMask": "0xC80FFD01",
-        "UMaskExt": "0xC80FFD",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
-        "UMask": "0xC807FD01",
-        "UMaskExt": "0xC807FD",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
-        "UMask": "0xC001FE01",
-        "UMaskExt": "0xC001FE",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "LLC_MISSES.UNCACHEABLE",
-        "Filter": "config1=0x40e33",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
+        "EventCode": "0x80",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
-        "UMask": "0xC001FE01",
-        "UMaskExt": "0xC001FE",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.ia_miss",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "LLC_MISSES.MMIO_READ",
-        "Filter": "config1=0x40040e33",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
+        "EventCode": "0x81",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0xC001FE01",
-        "UMaskExt": "0xC001FE",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "LLC_MISSES.MMIO_WRITE",
-        "Filter": "config1=0x40041e33",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
+        "EventCode": "0x81",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0xC001FE01",
-        "UMaskExt": "0xC001FE",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "LLC_REFERENCES.STREAMING_FULL",
-        "Filter": "config1=0x41833",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
+        "EventCode": "0x81",
+        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0xC001FE01",
-        "UMaskExt": "0xC001FE",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "LLC_REFERENCES.STREAMING_PARTIAL",
-        "Filter": "config1=0x41a33",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "ScaleUnit": "64Bytes",
-        "UMask": "0xC001FE01",
-        "UMaskExt": "0xC001FE",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0xC80FFE01",
-        "UMaskExt": "0xC80FFE",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0xC807FE01",
-        "UMaskExt": "0xC807FE",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All requests from IO Devices",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "UMask": "0xC001FF04",
-        "UMaskExt": "0xC001FF",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All requests from IO Devices that hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
-        "UMask": "0xC001FD04",
-        "UMaskExt": "0xC001FD",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All requests from IO Devices that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
-        "UMask": "0xC001FE04",
-        "UMaskExt": "0xC001FE",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : All requests from iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
-        "UMask": "0xC001FF01",
-        "UMaskExt": "0xC001FF",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
+        "EventCode": "0x82",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
-        "UMask": "0xC001FD01",
-        "UMaskExt": "0xC001FD",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
+        "EventCode": "0x83",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "UMask": "0xC001FE01",
-        "UMaskExt": "0xC001FE",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
+        "EventCode": "0x83",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0xC80FFE01",
-        "UMaskExt": "0xC80FFE",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
+        "EventCode": "0x83",
+        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "UMask": "0xC807FE01",
-        "UMaskExt": "0xC807FE",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : All requests from IO Devices",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "UMask": "0xC001FF04",
-        "UMaskExt": "0xC001FF",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "UMask": "0xC001FD04",
-        "UMaskExt": "0xC001FD",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0xC001FE04",
-        "UMaskExt": "0xC001FE",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0xCC43FE04",
-        "UMaskExt": "0xCC43FE",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Clockticks",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_CHA_CMS_CLOCKTICKS",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
-        "UMask": "0xC88FFD01",
-        "UMaskExt": "0xC88FFD",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
-        "UMask": "0xC827FD01",
-        "UMaskExt": "0xC827FD",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
+        "EventCode": "0x88",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
-        "UMask": "0xC8A7FD01",
-        "UMaskExt": "0xC8A7FD",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
+        "EventCode": "0x89",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0xC887FD01",
-        "UMaskExt": "0xC887FD",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
+        "EventCode": "0x89",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0xC88FFE01",
-        "UMaskExt": "0xC88FFE",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
+        "EventCode": "0x89",
+        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMask": "0xC827FE01",
-        "UMaskExt": "0xC827FE",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0xC8A7FE01",
-        "UMaskExt": "0xC8A7FE",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0xC887FE01",
-        "UMaskExt": "0xC887FE",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0xC827FD01",
-        "UMaskExt": "0xC827FD",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "UMask": "0xC8A7FD01",
-        "UMaskExt": "0xC8A7FD",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
-        "UMask": "0xC827FE01",
-        "UMaskExt": "0xC827FE",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
-        "UMask": "0xCC43FD04",
-        "UMaskExt": "0xCC43FD",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
-        "UMask": "0xCC43FF04",
-        "UMaskExt": "0xCC43FF",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
+        "EventCode": "0x8A",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
-        "UMask": "0xC887FF01",
-        "UMaskExt": "0xC887FF",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
+        "EventCode": "0x8B",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "UMask": "0xC807FF01",
-        "UMaskExt": "0xC807FF",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
+        "EventCode": "0x8B",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0xC827FF01",
-        "UMaskExt": "0xC827FF",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
+        "EventCode": "0x8B",
+        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "UMask": "0xC8A7FF01",
-        "UMaskExt": "0xC8A7FF",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : CRDs issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "UMask": "0xC80FFF01",
-        "UMaskExt": "0xC80FFF",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "UMask": "0xC807FF01",
-        "UMaskExt": "0xC807FF",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0xC827FF01",
-        "UMaskExt": "0xC827FF",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0xC8A7FF01",
-        "UMaskExt": "0xC8A7FF",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
-        "UMask": "0xC80FFF01",
-        "UMaskExt": "0xC80FFF",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
-        "UMask": "0xC8C7FF01",
-        "UMaskExt": "0xC8C7FF",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
-        "UMask": "0xCD43FF04",
-        "UMaskExt": "0xCD43FF",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
+        "EventCode": "0x84",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
-        "UMask": "0xCD43FD04",
-        "UMaskExt": "0xCD43FD",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
+        "EventCode": "0x85",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0xCD43FE04",
-        "UMaskExt": "0xCD43FE",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
+        "EventCode": "0x85",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0xc867fe01",
-        "UMaskExt": "0xc867fe",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; WCiL misses from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
+        "EventCode": "0x85",
+        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMask": "0xc86ffe01",
-        "UMaskExt": "0xc86ffe",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0xC86FFE01",
-        "UMaskExt": "0xC86FFE",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0xC87FDE01",
-        "UMaskExt": "0xC87FDE",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0xC877DE01",
-        "UMaskExt": "0xC877DE",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "UMask": "0xC8F3FE04",
-        "UMaskExt": "0xC8F3FE",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
-        "UMask": "0xc8f3fe04",
-        "UMaskExt": "0xc8f3fe",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
-        "UMask": "0xC8F3FD04",
-        "UMaskExt": "0xC8F3FD",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
-        "UMask": "0xC8F3FF04",
-        "UMaskExt": "0xC8F3FF",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
+        "EventCode": "0x86",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
-        "UMask": "0xC8F3FF04",
-        "UMaskExt": "0xC8F3FF",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
+        "EventCode": "0x87",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "UMask": "0xC867FE01",
-        "UMaskExt": "0xC867FE",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
+        "EventCode": "0x87",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x1BC1FF",
-        "UMaskExt": "0x1BC1",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x01",
-        "EventName": "UNC_IIO_CLOCKTICKS",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
+        "EventCode": "0x87",
+        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCI Express bandwidth writing at IIO, part 0",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "ScaleUnit": "4Bytes",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCI Express bandwidth writing at IIO, part 1",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "ScaleUnit": "4Bytes",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "PCI Express bandwidth writing at IIO, part 2",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x04",
-        "ScaleUnit": "4Bytes",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "PCI Express bandwidth writing at IIO, part 3",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x08",
-        "ScaleUnit": "4Bytes",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "LLC_MISSES.PCIE_WRITE",
-        "FCMask": "0x07",
-        "Filter": "ch_mask=0x1f",
-        "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
-        "MetricName": "LLC_MISSES.PCIE_WRITE",
-        "PerPkg": "1",
-        "PortMask": "0x01",
-        "ScaleUnit": "4Bytes",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "PCI Express bandwidth reading at IIO, part 0",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x01",
-        "ScaleUnit": "4Bytes",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "PCI Express bandwidth reading at IIO, part 1",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x02",
-        "ScaleUnit": "4Bytes",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "PCI Express bandwidth reading at IIO, part 2",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x04",
-        "ScaleUnit": "4Bytes",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "PCI Express bandwidth reading at IIO, part 3",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x08",
-        "ScaleUnit": "4Bytes",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "LLC_MISSES.PCIE_READ",
-        "FCMask": "0x07",
-        "Filter": "ch_mask=0x1f",
-        "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
-        "MetricName": "LLC_MISSES.PCIE_READ",
-        "PerPkg": "1",
-        "PortMask": "0x01",
-        "ScaleUnit": "4Bytes",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x80",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x80",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x80",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x80",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x80",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x80",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x80",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x80",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x80",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x80",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x80",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x80",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number requests PCIe makes of the main die : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+        "EventCode": "0x8C",
+        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
+        "EventCode": "0x8D",
+        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
+        "EventCode": "0x8D",
+        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
+        "EventCode": "0x8D",
+        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
+        "EventCode": "0x8E",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
-        "PortMask": "0x20",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
         "UMask": "0x80",
-        "Unit": "IIO"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
+        "EventCode": "0x8F",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
+        "EventCode": "0x8F",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Free running counter that increments for IIO clocktick",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_CLOCKTICKS_FREERUN",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
+        "EventCode": "0x8F",
+        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "Unit": "IIO"
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
-        "FCMask": "0x04",
+        "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken",
+        "EventCode": "0x57",
+        "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "PublicDescription": "CHA to iMC Bypass : Intermediate bypass Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the intermediate bypass.",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
-        "FCMask": "0x04",
+        "BriefDescription": "CHA to iMC Bypass : Not Taken",
+        "EventCode": "0x57",
+        "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "PublicDescription": "CHA to iMC Bypass : Not Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
-        "FCMask": "0x04",
+        "BriefDescription": "CHA to iMC Bypass : Taken",
+        "EventCode": "0x57",
+        "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "PublicDescription": "CHA to iMC Bypass : Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the full bypass.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
-        "FCMask": "0x04",
+        "BriefDescription": "Uncore cache clock ticks",
+        "EventName": "UNC_CHA_CLOCKTICKS",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4",
-        "FCMask": "0x04",
+        "BriefDescription": "CMS Clockticks",
+        "EventCode": "0xc0",
+        "EventName": "UNC_CHA_CMS_CLOCKTICKS",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5",
-        "FCMask": "0x04",
+        "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "PublicDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0xf2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6",
-        "FCMask": "0x04",
+        "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.ANY_ONE",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "PublicDescription": "Core Cross Snoops Issued : Any Single Snoop : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0xf1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7",
-        "FCMask": "0x04",
+        "BriefDescription": "Core Cross Snoops Issued : Multiple Core Requests",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "PublicDescription": "Core Cross Snoops Issued : Multiple Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x42",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
-        "FCMask": "0x04",
+        "BriefDescription": "Core Cross Snoops Issued : Single Core Requests",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.CORE_ONE",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "IIO"
+        "PublicDescription": "Core Cross Snoops Issued : Single Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x41",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 7",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7",
-        "FCMask": "0x04",
+        "BriefDescription": "Core Cross Snoops Issued : Multiple Eviction",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "IIO"
+        "PublicDescription": "Core Cross Snoops Issued : Multiple Eviction : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x82",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 6",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6",
-        "FCMask": "0x04",
+        "BriefDescription": "Core Cross Snoops Issued : Single Eviction",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "IIO"
+        "PublicDescription": "Core Cross Snoops Issued : Single Eviction : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x81",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 5",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5",
-        "FCMask": "0x04",
+        "BriefDescription": "Core Cross Snoops Issued : Multiple External Snoops",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IIO"
+        "PublicDescription": "Core Cross Snoops Issued : Multiple External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x22",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4",
-        "FCMask": "0x04",
+        "BriefDescription": "Core Cross Snoops Issued : Single External Snoops",
+        "EventCode": "0x33",
+        "EventName": "UNC_CHA_CORE_SNP.EXT_ONE",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IIO"
+        "PublicDescription": "Core Cross Snoops Issued : Single External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
+        "UMask": "0x21",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 3",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
-        "FCMask": "0x04",
+        "BriefDescription": "Counter 0 Occupancy",
+        "EventCode": "0x1F",
+        "EventName": "UNC_CHA_COUNTER0_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "IIO"
+        "PublicDescription": "Counter 0 Occupancy : Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0.   The filtering available is found in the control register - threshold, invert and edge detect.   E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 2",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
-        "FCMask": "0x04",
+        "BriefDescription": "Direct GO",
+        "EventCode": "0x6E",
+        "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "IIO"
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 1",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
-        "FCMask": "0x04",
+        "BriefDescription": "Direct GO",
+        "EventCode": "0x6E",
+        "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IIO"
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",
-        "FCMask": "0x04",
+        "BriefDescription": "Direct GO",
+        "EventCode": "0x6E",
+        "EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC",
         "PerPkg": "1",
-        "PortMask": "0xff",
-        "UMask": "0x03",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
-        "FCMask": "0x04",
+        "BriefDescription": "Direct GO",
+        "EventCode": "0x6D",
+        "EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP",
         "PerPkg": "1",
-        "UMask": "0xff",
-        "Unit": "IIO"
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Misc Events - Set 1 : Lost Forward",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1F",
-        "EventName": "UNC_I_MISC1.LOST_FWD",
+        "BriefDescription": "Direct GO",
+        "EventCode": "0x6D",
+        "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO",
         "PerPkg": "1",
         "UMask": "0x10",
-        "Unit": "IRP"
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.PCITOM",
+        "BriefDescription": "Direct GO",
+        "EventCode": "0x6D",
+        "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IRP"
+        "UMask": "0x20",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Coherent Ops : WbMtoI",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
+        "BriefDescription": "Direct GO",
+        "EventCode": "0x6D",
+        "EventName": "UNC_CHA_DIRECT_GO_OPC.GO",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "IRP"
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0f",
-        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
+        "BriefDescription": "Direct GO",
+        "EventCode": "0x6D",
+        "EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "IRP"
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
+        "BriefDescription": "Direct GO",
+        "EventCode": "0x6D",
+        "EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "IRP"
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Inbound write (fast path) requests received by the IRP",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
+        "BriefDescription": "Direct GO",
+        "EventCode": "0x6D",
+        "EventName": "UNC_CHA_DIRECT_GO_OPC.NOP",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "IRP"
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Clockticks of the IO coherency tracker (IRP)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x01",
-        "EventName": "UNC_I_CLOCKTICKS",
+        "BriefDescription": "Direct GO",
+        "EventCode": "0x6D",
+        "EventName": "UNC_CHA_DIRECT_GO_OPC.PULL",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "FAF RF full",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x17",
-        "EventName": "UNC_I_FAF_FULL",
+        "BriefDescription": "Distress signal asserted : DPT Local",
+        "EventCode": "0xAF",
+        "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_LOCAL",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_I_FAF_INSERTS",
+        "BriefDescription": "Distress signal asserted : DPT Remote",
+        "EventCode": "0xAF",
+        "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_NONLOCAL",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
+        "UMask": "0x8",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Occupancy of the IRP FAF queue",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_I_FAF_OCCUPANCY",
+        "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
+        "EventCode": "0xAF",
+        "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_IV",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
+        "UMask": "0x40",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "FAF allocation -- sent to ADQ",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x16",
-        "EventName": "UNC_I_FAF_TRANSACTIONS",
+        "BriefDescription": "Distress signal asserted : DPT Stalled -  No Credit",
+        "EventCode": "0xAF",
+        "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PublicDescription": "Distress signal asserted : DPT Stalled -  No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
+        "UMask": "0x80",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M",
+        "BriefDescription": "Distress signal asserted : Horizontal",
+        "EventCode": "0xAF",
+        "EventName": "UNC_CHA_DISTRESS_ASSERTED.HORZ",
         "PerPkg": "1",
-        "UMask": "0x78",
-        "Unit": "IRP"
+        "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
+        "UMask": "0x2",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Clockticks of the mesh to memory (M2M)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventName": "UNC_M2M_CLOCKTICKS",
+        "BriefDescription": "Distress signal asserted : Vertical",
+        "EventCode": "0xAF",
+        "EventName": "UNC_CHA_DISTRESS_ASSERTED.VERT",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Clockticks",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_M2M_CMS_CLOCKTICKS",
+        "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+        "EventCode": "0xBA",
+        "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Clockticks of the mesh to PCI (M2P)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x01",
-        "EventName": "UNC_M2P_CLOCKTICKS",
+        "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+        "EventCode": "0xBA",
+        "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
         "PerPkg": "1",
-        "Unit": "M2PCIe"
+        "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Clockticks",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc0",
-        "EventName": "UNC_M2P_CMS_CLOCKTICKS",
+        "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
+        "EventCode": "0xB6",
+        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "Unit": "M2PCIe"
+        "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
-        "Counter": "FIXED",
-        "CounterType": "FIXED",
-        "EventCode": "0xff",
-        "EventName": "UNC_U_CLOCKTICKS",
+        "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
+        "EventCode": "0xB6",
+        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD",
+        "PerPkg": "1",
+        "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
+        "EventCode": "0xB6",
+        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "Unit": "UBOX"
+        "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
+        "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized : Local - All Lines",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
+        "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
+        "EventCode": "0xB6",
+        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x200F",
-        "UMaskExt": "0x20",
+        "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Counter 0 Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1F",
-        "EventName": "UNC_CHA_COUNTER0_OCCUPANCY",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+        "EventCode": "0xBB",
+        "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Number of times that an RFO hit in S state",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x39",
-        "EventName": "UNC_CHA_MISC.RFO_HIT_S",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+        "EventCode": "0xBB",
+        "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and remote INVITOE requests sent to the CHA's home agent",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x50",
-        "EventName": "UNC_CHA_REQUESTS.INVITOE",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+        "EventCode": "0xBB",
+        "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x30",
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+        "EventCode": "0xBB",
+        "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.ALL",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+        "EventCode": "0xB7",
+        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC001FFff",
-        "UMaskExt": "0xC001FF",
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+        "EventCode": "0xB7",
+        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0xC80FFD01",
-        "UMaskExt": "0xC80FFD",
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+        "EventCode": "0xB7",
+        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0xC807FD01",
-        "UMaskExt": "0xC807FD",
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+        "EventCode": "0xB7",
+        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0xc803fe04",
-        "UMaskExt": "0xc803fe",
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
+        "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
+        "EventCode": "0xB8",
+        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0xc803fe04",
-        "UMaskExt": "0xc803fe",
+        "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
+        "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
+        "EventCode": "0xB8",
+        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0xcc43fe04",
-        "UMaskExt": "0xcc43fe",
+        "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA to iMC Bypass : Taken",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x57",
-        "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN",
+        "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
+        "EventCode": "0xB8",
+        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x57",
-        "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
+        "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
+        "EventCode": "0xB8",
+        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA to iMC Bypass : Not Taken",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x57",
-        "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
+        "BriefDescription": "Horizontal IV Ring in Use : Left",
+        "EventCode": "0xB9",
+        "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued : Single External Snoops",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.EXT_ONE",
+        "BriefDescription": "Horizontal IV Ring in Use : Right",
+        "EventCode": "0xB9",
+        "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT",
         "PerPkg": "1",
-        "UMask": "0x21",
+        "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued : Single Core Requests",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.CORE_ONE",
+        "BriefDescription": "Normal priority reads issued to the memory controller from the CHA",
+        "EventCode": "0x59",
+        "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL",
         "PerPkg": "1",
-        "UMask": "0x41",
+        "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued : Single Eviction",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE",
+        "BriefDescription": "HA to iMC Reads Issued : ISOCH",
+        "EventCode": "0x59",
+        "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY",
         "PerPkg": "1",
-        "UMask": "0x81",
+        "PublicDescription": "HA to iMC Reads Issued : ISOCH : Count of the number of reads issued to any of the memory controller channels.  This can be filtered by the priority of the reads.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.ANY_ONE",
+        "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH",
+        "EventCode": "0x5B",
+        "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL",
         "PerPkg": "1",
-        "UMask": "0xF1",
+        "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to any of the memory controller channels.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued : Multiple External Snoops",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE",
+        "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line",
+        "EventCode": "0x5B",
+        "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
         "PerPkg": "1",
-        "UMask": "0x22",
+        "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line : Counts the total number of full line writes issued from the HA into the memory controller.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued : Multiple Core Requests",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE",
+        "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH",
+        "EventCode": "0x5B",
+        "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
         "PerPkg": "1",
-        "UMask": "0x42",
+        "PublicDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH : Counts the total number of full line writes issued from the HA into the memory controller.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued : Multiple Eviction",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE",
+        "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial",
+        "EventCode": "0x5B",
+        "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
         "PerPkg": "1",
-        "UMask": "0x82",
+        "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial : Counts the total number of full line writes issued from the HA into the memory controller.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE",
+        "BriefDescription": "Cache and Snoop Filter Lookups; Any Request",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.ALL",
         "PerPkg": "1",
-        "UMask": "0xF2",
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ.  This does not include lookups originating from the ISMQ.",
+        "UMask": "0x1fffff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Direct GO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC",
+        "BriefDescription": "Cache Lookups : All Request Filter",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.ANY_F",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cache Lookups : All Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Any local or remote transaction to the LLC, including prefetch.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Direct GO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.CODE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1bd0ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Direct GO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD",
+        "BriefDescription": "Cache Lookups : Code Reads",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cache Lookups : Code Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x1bd0ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Direct GO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP",
+        "BriefDescription": "Cache Lookups : CRd Request Filter",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cache Lookups : CRd Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC.  This includes CRd prefetch.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Direct GO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_CHA_DIRECT_GO_OPC.PULL",
+        "BriefDescription": "Cache Lookups : Code Read Misses",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_MISS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cache Lookups : Code Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x1bd001",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Direct GO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_CHA_DIRECT_GO_OPC.GO",
+        "BriefDescription": "Cache Lookups : Local request Filter",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cache Lookups : Local request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Any local transaction to the LLC, including prefetches from the Core",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Direct GO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1bc1ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Direct GO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO",
+        "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
+        "UMask": "0x1bc1ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Direct GO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x1fc1ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Direct GO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_CHA_DIRECT_GO_OPC.NOP",
+        "BriefDescription": "Cache Lookups : Data Read Request Filter",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Cache Lookups : Data Read Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Read transactions.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Direct GO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS",
+        "BriefDescription": "Cache Lookups : Data Read Misses",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Cache Lookups : Data Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x1bc101",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "HA to iMC Reads Issued : ISOCH",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x59",
-        "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.DMND_READ_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x841ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5B",
-        "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
+        "BriefDescription": "Cache Lookups : E State",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.E",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cache Lookups : E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Hit Exclusive State",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5B",
-        "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
+        "BriefDescription": "Cache Lookups : F State",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.F",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cache Lookups : F State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Hit Forward State",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5B",
-        "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
+        "BriefDescription": "Cache Lookups : Flush or Invalidate Requests",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV",
+        "PerPkg": "1",
+        "PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x1a44ff",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "Cache Lookups : Flush or Invalidate Filter",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cache Lookups : Flush or Invalidate Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized : Lines in M state",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE",
+        "BriefDescription": "Cache Lookups : I State",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.I",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cache Lookups : I State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Miss",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized : Lines in E state",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE",
+        "BriefDescription": "Cache Lookups : Transactions homed locally Filter",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cache Lookups : Transactions homed locally Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Transaction whose address resides in the local MC.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized : Lines in S State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE",
+        "BriefDescription": "Cache Lookups : M State",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.M",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cache Lookups : M State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Hit Modified State",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized : Local Only",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY",
+        "BriefDescription": "Cache Lookups : All Misses",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL",
         "PerPkg": "1",
-        "UMaskExt": "0x20",
+        "PublicDescription": "Cache Lookups : All Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x1fe001",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized : Local - Lines in M State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M",
+        "BriefDescription": "Cache Lookups : Write Request Filter",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F",
         "PerPkg": "1",
-        "UMask": "0x2001",
-        "UMaskExt": "0x20",
+        "PublicDescription": "Cache Lookups : Write Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Writeback transactions to the LLC  This includes all write transactions -- both Cacheable and UC.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized : Local - Lines in E State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E",
+        "BriefDescription": "Cache Lookups : Reads",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.READ",
         "PerPkg": "1",
-        "UMask": "0x2002",
-        "UMaskExt": "0x20",
+        "PublicDescription": "Cache Lookups : Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x1bd9ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Lines Victimized : Local - Lines in S State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S",
+        "BriefDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_LOC_HOM",
         "PerPkg": "1",
-        "UMask": "0x2004",
-        "UMaskExt": "0x20",
+        "PublicDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x9d9ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cbo Misc : Silent Snoop Eviction",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x39",
-        "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE",
+        "BriefDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_REM_HOM",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x11d9ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cbo Misc : Write Combining Aliasing",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x39",
-        "EventName": "UNC_CHA_MISC.WC_ALIASING",
+        "BriefDescription": "Cache Lookups : Read Misses",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cache Lookups : Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x1bd901",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cbo Misc : CV0 Prefetch Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x39",
-        "EventName": "UNC_CHA_MISC.CV0_PREF_VIC",
+        "BriefDescription": "Cache Lookups : Locally HOMed Read Misses",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_LOC_HOM",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cache Lookups : Locally HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0xbd901",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cbo Misc : CV0 Prefetch Miss",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x39",
-        "EventName": "UNC_CHA_MISC.CV0_PREF_MISS",
+        "BriefDescription": "Cache Lookups : Remotely HOMed Read Misses",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_REM_HOM",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Cache Lookups : Remotely HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x13d901",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.RMW_SETMATCH",
+        "BriefDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.READ_OR_SNOOP_REMOTE_MISS_REM_HOM",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x161901",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_PAMATCH",
+        "BriefDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.READ_REMOTE_LOC_HOM",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0xa19ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLOWSNP",
+        "BriefDescription": "Cache Lookups : Reads that Hit the Snoop Filter",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.READ_SF_HIT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cache Lookups : Reads that Hit the Snoop Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x1bd90e",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_WAYMATCH",
+        "BriefDescription": "Cache Lookups : RFO Requests",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.RFO",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC.  This includes RFO prefetch.",
+        "UMask": "0x1bc8ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLWAYRSV",
+        "BriefDescription": "Cache Lookups : RFO Request Filter",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.RFO_F",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cache Lookups : RFO Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC.  This includes RFO prefetch.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.PTL_INPIPE",
+        "BriefDescription": "Cache Lookups : RFO Misses",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.RFO_MISS",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Cache Lookups : RFO Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing.",
+        "UMask": "0x1bc801",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.IRQ_SETMATCH_VICP",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.RFO_LOCAL",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.RFO_PREF_LOCAL",
         "PerPkg": "1",
-        "UMaskExt": "0x01",
+        "UMask": "0x888ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.FSF_VICP",
+        "BriefDescription": "Cache Lookups : S State",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.S",
         "PerPkg": "1",
-        "UMaskExt": "0x02",
+        "PublicDescription": "Cache Lookups : S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : Hit Shared State",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.ONE_FSF_VIC",
+        "BriefDescription": "Cache Lookups : SnoopFilter - E State",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.SF_E",
         "PerPkg": "1",
-        "UMaskExt": "0x04",
+        "PublicDescription": "Cache Lookups : SnoopFilter - E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : SF Hit Exclusive State",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.TORID_MATCH_GO_P",
+        "BriefDescription": "Cache Lookups : SnoopFilter - H State",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.SF_H",
         "PerPkg": "1",
-        "UMaskExt": "0x10",
+        "PublicDescription": "Cache Lookups : SnoopFilter - H State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : SF Hit HitMe State",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.IPQ_SETMATCH_VICP",
+        "BriefDescription": "Cache Lookups : SnoopFilter - S State",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.SF_S",
         "PerPkg": "1",
-        "UMaskExt": "0x20",
+        "PublicDescription": "Cache Lookups : SnoopFilter - S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS select a state or states (in the umask field) to match.  Otherwise, the event will count nothing. : SF Hit Shared State",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.WAY_MATCH",
+        "BriefDescription": "Cache Lookups : Filters Requests for those that write info into the cache",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
         "PerPkg": "1",
-        "UMaskExt": "0x40",
+        "PublicDescription": "Cache Lookups : Write Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing. : Writeback transactions from L2 to the LLC  This includes all write transactions -- both Cacheable and UC.",
+        "UMask": "0x1a42ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.ONE_RSP_CON",
+        "BriefDescription": "This event is deprecated.",
+        "Deprecated": "1",
+        "EventCode": "0x34",
+        "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL",
         "PerPkg": "1",
-        "UMaskExt": "0x80",
+        "UMask": "0x842ff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.IDX_INPIPE",
+        "BriefDescription": "Lines Victimized : All Lines Victimized",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.ALL",
         "PerPkg": "1",
-        "UMaskExt": "0x100",
+        "PublicDescription": "Lines Victimized : All Lines Victimized : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0xf",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.SETMATCHENTRYWSCT",
+        "BriefDescription": "Lines Victimized : Lines in E state",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE",
         "PerPkg": "1",
-        "UMaskExt": "0x200",
+        "PublicDescription": "Lines Victimized : Lines in E state : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.ALLRSFWAYS_RES",
+        "BriefDescription": "Lines Victimized : Local - All Lines",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
         "PerPkg": "1",
-        "UMaskExt": "0x800",
+        "PublicDescription": "Lines Victimized : Local - All Lines : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x200f",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.RRQ_SETMATCH_VICP",
+        "BriefDescription": "Lines Victimized : Local - Lines in E State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E",
         "PerPkg": "1",
-        "UMaskExt": "0x1000",
+        "PublicDescription": "Lines Victimized : Local - Lines in E State : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x2002",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.ISMQ_SETMATCH_VICP",
+        "BriefDescription": "Lines Victimized : Local - Lines in M State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M",
         "PerPkg": "1",
-        "UMaskExt": "0x2000",
+        "PublicDescription": "Lines Victimized : Local - Lines in M State : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x2001",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.SF_WAYS_RES",
+        "BriefDescription": "Lines Victimized : Local Only",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY",
         "PerPkg": "1",
-        "UMaskExt": "0x4000",
+        "PublicDescription": "Lines Victimized : Local Only : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.LLC_WAYS_RES",
+        "BriefDescription": "Lines Victimized : Local - Lines in S State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S",
         "PerPkg": "1",
-        "UMaskExt": "0x8000",
+        "PublicDescription": "Lines Victimized : Local - Lines in S State : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x2004",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.NOTALLOWSNOOP",
+        "BriefDescription": "Lines Victimized : Lines in M state",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE",
         "PerPkg": "1",
-        "UMaskExt": "0x10000",
+        "PublicDescription": "Lines Victimized : Lines in M state : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.TOPA_MATCH",
+        "BriefDescription": "Lines Victimized : Lines in S State",
+        "EventCode": "0x37",
+        "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE",
         "PerPkg": "1",
-        "UMaskExt": "0x20000",
+        "PublicDescription": "Lines Victimized : Lines in S State : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.IVEGRCREDIT",
+        "BriefDescription": "Cbo Misc : CV0 Prefetch Miss",
+        "EventCode": "0x39",
+        "EventName": "UNC_CHA_MISC.CV0_PREF_MISS",
         "PerPkg": "1",
-        "UMaskExt": "0x40000",
+        "PublicDescription": "Cbo Misc : CV0 Prefetch Miss : Miscellaneous events in the Cbo.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.BLEGRCREDIT",
+        "BriefDescription": "Cbo Misc : CV0 Prefetch Victim",
+        "EventCode": "0x39",
+        "EventName": "UNC_CHA_MISC.CV0_PREF_VIC",
         "PerPkg": "1",
-        "UMaskExt": "0x80000",
+        "PublicDescription": "Cbo Misc : CV0 Prefetch Victim : Miscellaneous events in the Cbo.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.ADEGRCREDIT",
+        "BriefDescription": "Number of times that an RFO hit in S state.",
+        "EventCode": "0x39",
+        "EventName": "UNC_CHA_MISC.RFO_HIT_S",
         "PerPkg": "1",
-        "UMaskExt": "0x100000",
+        "PublicDescription": "Counts when a RFO (the Read for Ownership issued before a  write) request hit a cacheline in the S (Shared) state.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.AKEGRCREDIT",
+        "BriefDescription": "Cbo Misc : Silent Snoop Eviction",
+        "EventCode": "0x39",
+        "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE",
         "PerPkg": "1",
-        "UMaskExt": "0x200000",
+        "PublicDescription": "Cbo Misc : Silent Snoop Eviction : Miscellaneous events in the Cbo. : Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction.  This is useful because this information is lost in the PRE encodings.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.HACREDIT",
+        "BriefDescription": "Cbo Misc : Write Combining Aliasing",
+        "EventCode": "0x39",
+        "EventName": "UNC_CHA_MISC.WC_ALIASING",
         "PerPkg": "1",
-        "UMaskExt": "0x400000",
+        "PublicDescription": "Cbo Misc : Write Combining Aliasing : Miscellaneous events in the Cbo. : Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write.  This occurs when there is WC aliasing.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_REQ",
+        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
+        "EventCode": "0xE6",
+        "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST0",
         "PerPkg": "1",
-        "UMaskExt": "0x800000",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_RSP",
+        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
+        "EventCode": "0xE6",
+        "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST1",
         "PerPkg": "1",
-        "UMaskExt": "0x1000000",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_RSP",
+        "EventName": "UNC_CHA_PIPE_REJECT.ADEGRCREDIT",
         "PerPkg": "1",
-        "UMaskExt": "0x2000000",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_WB",
+        "EventName": "UNC_CHA_PIPE_REJECT.AKEGRCREDIT",
         "PerPkg": "1",
-        "UMaskExt": "0x4000000",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCB",
+        "EventName": "UNC_CHA_PIPE_REJECT.ALLRSFWAYS_RES",
         "PerPkg": "1",
-        "UMaskExt": "0x8000000",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Pipe Rejects",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x42",
-        "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCS",
+        "EventName": "UNC_CHA_PIPE_REJECT.BLEGRCREDIT",
         "PerPkg": "1",
-        "UMaskExt": "0x10000000",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC0",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.FSF_VICP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC1",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLOWSNP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC2",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLWAYRSV",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC3",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_PAMATCH",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC4",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_WAYMATCH",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC5",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.HACREDIT",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC6",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.IDX_INPIPE",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC7",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.IPQ_SETMATCH_VICP",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC8",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.IRQ_SETMATCH_VICP",
         "PerPkg": "1",
-        "UMaskExt": "0x01",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC9",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.ISMQ_SETMATCH_VICP",
         "PerPkg": "1",
-        "UMaskExt": "0x02",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC10",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.IVEGRCREDIT",
         "PerPkg": "1",
-        "UMaskExt": "0x04",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC11",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC11",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.LLC_WAYS_RES",
         "PerPkg": "1",
-        "UMaskExt": "0x08",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC12",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC12",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.NOTALLOWSNOOP",
         "PerPkg": "1",
-        "UMaskExt": "0x10",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC13",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_CHA_READ_NO_CREDITS.MC13",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.ONE_FSF_VIC",
         "PerPkg": "1",
-        "UMaskExt": "0x20",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations : IRQ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.IRQ",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.ONE_RSP_CON",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.PTL_INPIPE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations : PRQ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.PRQ",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.RMW_SETMATCH",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Allocations : PRQ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.RRQ_SETMATCH_VICP",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.SETMATCHENTRYWSCT",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.SF_WAYS_RES",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.TOPA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.TORID_MATCH_GO_P",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_REQ",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_RSP",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCB",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCS",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_RSP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_WB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
+        "BriefDescription": "Pipe Rejects",
+        "EventCode": "0x42",
+        "EventName": "UNC_CHA_PIPE_REJECT.WAY_MATCH",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC0 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 0 only.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC1 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 1 only.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC10",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC10",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC10 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 10 only.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC11",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC11",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC11 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 11 only.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC12",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC12",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC12 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 12 only.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC13",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC13",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC13 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 13 only.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC2 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 2 only.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC3 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 3 only.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
-    {
-        "BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
+    {
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC4",
         "PerPkg": "1",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC4 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 4 only.",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC5",
         "PerPkg": "1",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC5 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 5 only.",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC6",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC6",
         "PerPkg": "1",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC6 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 6 only.",
         "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC7",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC7",
         "PerPkg": "1",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC7 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 7 only.",
         "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC8",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC8",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC8 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 8 only.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
+        "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC9",
+        "EventCode": "0x58",
+        "EventName": "UNC_CHA_READ_NO_CREDITS.MC9",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC9 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 9 only.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
+        "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and remote INVITOE requests sent to the CHA's home agent",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.INVITOE",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
+        "UMask": "0x30",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
+        "BriefDescription": "Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.READS",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a  write) .",
+        "UMask": "0x3",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
+        "BriefDescription": "Local write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent",
+        "EventCode": "0x50",
+        "EventName": "UNC_CHA_REQUESTS.WRITES",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
+        "UMask": "0xc",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
+        "EventCode": "0xAC",
+        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2C",
-        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
+        "EventCode": "0xAC",
+        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects - Set 1 : ANY0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x25",
-        "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
+        "EventCode": "0xAC",
+        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Rejects - Set 1 : HA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x25",
-        "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
+        "EventCode": "0xAC",
+        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries - Set 1 : ANY0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2D",
-        "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
+        "EventCode": "0xAA",
+        "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "ISMQ Retries - Set 1 : HA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2D",
-        "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
+        "EventCode": "0xAA",
+        "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Occupancy : IRQ",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.",
+        "EventCode": "0xAA",
+        "EventName": "UNC_CHA_RING_BOUNCES_VERT.AKC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 0 : AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
+        "EventCode": "0xAA",
+        "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 0 : AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
+        "EventCode": "0xAA",
+        "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 0 : BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
+        "EventCode": "0xAD",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 0 : BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
+        "EventCode": "0xAD",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 0 : BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
+        "EventCode": "0xAD",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 0 : BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
+        "EventCode": "0xAD",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 0 : Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
+        "EventCode": "0xAD",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 0 : Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2E",
-        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI",
+        "BriefDescription": "Sink Starvation on Vertical Ring : AD",
+        "EventCode": "0xAB",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 1 : ANY0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0",
+        "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
+        "EventCode": "0xAB",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 1 : HA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA",
+        "BriefDescription": "Sink Starvation on Vertical Ring",
+        "EventCode": "0xAB",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AKC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 1 : LLC Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
+        "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
+        "EventCode": "0xAB",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 1 : SF Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
+        "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
+        "EventCode": "0xAB",
+        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 1 : Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
+        "BriefDescription": "Source Throttle",
+        "EventCode": "0xae",
+        "EventName": "UNC_CHA_RING_SRC_THRTL",
         "PerPkg": "1",
-        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 1 : LLC OR SF Way",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
+        "BriefDescription": "Ingress (from CMS) Allocations : IRQ",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.IRQ",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Ingress (from CMS) Allocations : IRQ : Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 1 : Allow Snoop",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
+        "BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Ingress (from CMS) Allocations : IRQ Rejected : Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Other Retries - Set 1 : PhyAddr Match",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2F",
-        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
+        "BriefDescription": "Ingress (from CMS) Allocations : PRQ",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.PRQ",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
+        "BriefDescription": "Ingress (from CMS) Allocations : PRQ",
+        "EventCode": "0x13",
+        "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
+        "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
+        "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
+        "EventCode": "0x18",
+        "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IRQ0 Reject counter was true",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way : Way conflict with another request that caused the reject",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
+        "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
+        "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Victim",
+        "EventCode": "0x19",
+        "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
+        "BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
+        "BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
+        "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
+        "BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
+        "PublicDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
+        "BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
+        "PublicDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI",
+        "BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2A",
-        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI",
+        "BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "ISMQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 1 : ANY0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
+        "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request",
+        "EventCode": "0x24",
+        "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 1 : HA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA",
+        "BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "ISMQ Retries - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 1 : LLC Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
+        "BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "ISMQ Retries - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 1 : SF Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
+        "BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "ISMQ Retries - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 1 : Victim",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
+        "BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
         "PerPkg": "1",
+        "PublicDescription": "ISMQ Retries - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
+        "BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
         "PerPkg": "1",
+        "PublicDescription": "ISMQ Retries - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
+        "BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "ISMQ Retries - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2B",
-        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
+        "BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
+        "PerPkg": "1",
+        "PublicDescription": "ISMQ Retries - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request",
+        "EventCode": "0x2C",
+        "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI",
         "PerPkg": "1",
+        "PublicDescription": "ISMQ Retries - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message",
         "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoops Sent : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x51",
-        "EventName": "UNC_CHA_SNOOPS_SENT.ALL",
+        "BriefDescription": "ISMQ Rejects - Set 1 : ANY0",
+        "EventCode": "0x25",
+        "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "ISMQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoops Sent : Snoops sent for Local Requests",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x51",
-        "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL",
+        "BriefDescription": "ISMQ Rejects - Set 1 : HA",
+        "EventCode": "0x25",
+        "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "ISMQ Rejects - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoops Sent : Broadcast snoops for Local Requests",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x51",
-        "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
+        "BriefDescription": "ISMQ Retries - Set 1 : ANY0",
+        "EventCode": "0x2D",
+        "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "ISMQ Retries - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoops Sent : Directed snoops for Local Requests",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x51",
-        "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
+        "BriefDescription": "ISMQ Retries - Set 1 : HA",
+        "EventCode": "0x2D",
+        "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "ISMQ Retries - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local : RspI",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
+        "BriefDescription": "Ingress (from CMS) Occupancy : IRQ",
+        "EventCode": "0x11",
+        "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Ingress (from CMS) Occupancy : IRQ : Counts number of entries in the specified Ingress queue in each cycle.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local : RspS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
+        "BriefDescription": "Other Retries - Set 0 : AD REQ on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Other Retries - Set 0 : AD REQ on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a request",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local : RspIFwd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
+        "BriefDescription": "Other Retries - Set 0 : AD RSP on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Other Retries - Set 0 : AD RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a response",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local : RspSFwd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
+        "BriefDescription": "Other Retries - Set 0 : Non UPI AK Request",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Other Retries - Set 0 : Non UPI AK Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject AK ring message",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local : Rsp*WB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB",
+        "BriefDescription": "Other Retries - Set 0 : BL NCB on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
         "PerPkg": "1",
+        "PublicDescription": "Other Retries - Set 0 : BL NCB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCB",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB",
+        "BriefDescription": "Other Retries - Set 0 : BL NCS on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
         "PerPkg": "1",
+        "PublicDescription": "Other Retries - Set 0 : BL NCS on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCS",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local : RspCnflct",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
+        "BriefDescription": "Other Retries - Set 0 : BL RSP on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Other Retries - Set 0 : BL RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a response",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Snoop Responses Received Local : RspFwd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
+        "BriefDescription": "Other Retries - Set 0 : BL WB on VN0",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Other Retries - Set 0 : BL WB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a writeback",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6B",
-        "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM",
+        "BriefDescription": "Other Retries - Set 0 : Non UPI IV Request",
+        "EventCode": "0x2E",
+        "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Other Retries - Set 0 : Non UPI IV Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject IV ring message",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Misc Snoop Responses Received : MtoI RspIDataM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6B",
-        "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM",
+        "BriefDescription": "Other Retries - Set 1 : Allow Snoop",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Other Retries - Set 1 : Allow Snoop : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit SF",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6B",
-        "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF",
+        "BriefDescription": "Other Retries - Set 1 : ANY0",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Other Retries - Set 1 : ANY0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Any condition listed in the Other0 Reject counter was true",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6B",
-        "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC",
+        "BriefDescription": "Other Retries - Set 1 : HA",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Other Retries - Set 1 : HA : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit SF",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6B",
-        "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF",
+        "BriefDescription": "Other Retries - Set 1 : LLC OR SF Way",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Other Retries - Set 1 : LLC OR SF Way : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Way conflict with another request that caused the reject",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6B",
-        "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC",
+        "BriefDescription": "Other Retries - Set 1 : LLC Victim",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Other Retries - Set 1 : LLC Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WbPushMtoI : Pushed to LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x56",
-        "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC",
+        "BriefDescription": "Other Retries - Set 1 : PhyAddr Match",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Other Retries - Set 1 : PhyAddr Match : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Address match with an outstanding request that was rejected.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "WbPushMtoI : Pushed to Memory",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x56",
-        "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM",
+        "BriefDescription": "Other Retries - Set 1 : SF Victim",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Other Retries - Set 1 : SF Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Requests did not generate Snoop filter victim",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0",
+        "BriefDescription": "Other Retries - Set 1 : Victim",
+        "EventCode": "0x2F",
+        "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Other Retries - Set 1 : Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
         "PerPkg": "1",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
         "PerPkg": "1",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC6",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC7",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
+        "PerPkg": "1",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback",
+        "UMask": "0x8",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
+        "EventCode": "0x20",
+        "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI",
         "PerPkg": "1",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message",
         "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC8",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
         "PerPkg": "1",
-        "UMaskExt": "0x01",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC9",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0",
         "PerPkg": "1",
-        "UMaskExt": "0x02",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the PRQ0 Reject counter was true",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC10",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA",
         "PerPkg": "1",
-        "UMaskExt": "0x04",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC11",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC11",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMaskExt": "0x08",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC12",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC12",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
         "PerPkg": "1",
-        "UMaskExt": "0x10",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC13",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5A",
-        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC13",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
         "PerPkg": "1",
-        "UMaskExt": "0x20",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "XPT Prefetches : Sent (on 0?)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6f",
-        "EventName": "UNC_CHA_XPT_PREF.SENT0",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6f",
-        "EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD",
+        "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Victim",
+        "EventCode": "0x21",
+        "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6f",
-        "EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT",
+        "BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Request Queue Retries - Set 0 : AD REQ on VN0 : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a request",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "XPT Prefetches : Sent (on 1?)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6f",
-        "EventName": "UNC_CHA_XPT_PREF.SENT1",
+        "BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Request Queue Retries - Set 0 : AD RSP on VN0 : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a response",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6f",
-        "EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD",
+        "BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Request",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI",
         "PerPkg": "1",
+        "PublicDescription": "Request Queue Retries - Set 0 : Non UPI AK Request : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject AK ring message",
         "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6f",
-        "EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT",
+        "BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Request Queue Retries - Set 0 : BL NCB on VN0 : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCB",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cache Lookups : I State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.I",
+        "BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Request Queue Retries - Set 0 : BL NCS on VN0 : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCS",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cache Lookups : SnoopFilter - S State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.SF_S",
+        "BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Request Queue Retries - Set 0 : BL RSP on VN0 : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a response",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cache Lookups : SnoopFilter - E State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.SF_E",
+        "BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Request Queue Retries - Set 0 : BL WB on VN0 : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a writeback",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cache Lookups : SnoopFilter - H State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.SF_H",
+        "BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Request",
+        "EventCode": "0x2A",
+        "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Request Queue Retries - Set 0 : Non UPI IV Request : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject IV ring message",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cache Lookups : S State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.S",
+        "BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Request Queue Retries - Set 1 : Allow Snoop : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cache Lookups : E State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.E",
+        "BriefDescription": "Request Queue Retries - Set 1 : ANY0",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Request Queue Retries - Set 1 : ANY0 : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Any condition listed in the WBQ0 Reject counter was true",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cache Lookups : M State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.M",
+        "BriefDescription": "Request Queue Retries - Set 1 : HA",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Request Queue Retries - Set 1 : HA : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cache Lookups : F State",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.F",
+        "BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Request Queue Retries - Set 1 : LLC OR SF Way : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Way conflict with another request that caused the reject",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cache Lookups : RFO Requests",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.RFO",
+        "BriefDescription": "Request Queue Retries - Set 1 : LLC Victim",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x1BC8FF",
-        "UMaskExt": "0x1BC8",
+        "PublicDescription": "Request Queue Retries - Set 1 : LLC Victim : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : IRQ - iA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA",
+        "BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
+        "PerPkg": "1",
+        "PublicDescription": "Request Queue Retries - Set 1 : PhyAddr Match : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Address match with an outstanding request that was rejected.",
+        "UMask": "0x80",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "Request Queue Retries - Set 1 : SF Victim",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Request Queue Retries - Set 1 : SF Victim : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Requests did not generate Snoop filter victim",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : SF/LLC Evictions",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.EVICT",
+        "BriefDescription": "Request Queue Retries - Set 1 : Victim",
+        "EventCode": "0x2B",
+        "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Request Queue Retries - Set 1 : Victim : REQUESTQ includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : PRQ - IOSF",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF",
+        "BriefDescription": "Transgress Injection Starvation : AD - All",
+        "EventCode": "0xE5",
+        "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : IRQ - Non iA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA",
+        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+        "EventCode": "0xE5",
+        "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : PRQ - Non IOSF",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF",
+        "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+        "EventCode": "0xE5",
+        "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All from Local IO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO",
+        "BriefDescription": "Transgress Injection Starvation : BL - All",
+        "EventCode": "0xE5",
+        "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0xC000FF04",
-        "UMaskExt": "0xC000FF",
+        "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All from Local iA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA",
+        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
+        "EventCode": "0xE5",
+        "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0xC000FF01",
-        "UMaskExt": "0xC000FF",
+        "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : All from Local iA and IO",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
+        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+        "EventCode": "0xE5",
+        "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0xC000FF05",
-        "UMaskExt": "0xC000FF",
+        "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : Just Hits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.HIT",
+        "BriefDescription": "Transgress Ingress Bypass : AD - All",
+        "EventCode": "0xE2",
+        "EventName": "UNC_CHA_RxR_BYPASS.AD_ALL",
         "PerPkg": "1",
-        "UMaskExt": "0x01",
+        "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : Just Misses",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.MISS",
+        "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
+        "EventCode": "0xE2",
+        "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMaskExt": "0x02",
+        "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.DDR",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.DDR4",
+        "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
+        "EventCode": "0xE2",
+        "EventName": "UNC_CHA_RxR_BYPASS.AD_UNCRD",
         "PerPkg": "1",
-        "UMaskExt": "0x04",
+        "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : MMCFG Access",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.MMCFG",
+        "BriefDescription": "Transgress Ingress Bypass : AK",
+        "EventCode": "0xE2",
+        "EventName": "UNC_CHA_RxR_BYPASS.AK",
         "PerPkg": "1",
-        "UMaskExt": "0x20",
+        "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : Just Local Targets",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT",
+        "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
+        "EventCode": "0xE2",
+        "EventName": "UNC_CHA_RxR_BYPASS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMaskExt": "0x80",
+        "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC",
+        "BriefDescription": "Transgress Ingress Bypass : BL - All",
+        "EventCode": "0xE2",
+        "EventName": "UNC_CHA_RxR_BYPASS.BL_ALL",
         "PerPkg": "1",
-        "UMaskExt": "0x200",
+        "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC",
+        "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
+        "EventCode": "0xE2",
+        "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "UMaskExt": "0x400",
+        "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : Just NearMem",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.NEARMEM",
+        "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
+        "EventCode": "0xE2",
+        "EventName": "UNC_CHA_RxR_BYPASS.BL_UNCRD",
         "PerPkg": "1",
-        "UMaskExt": "0x400000",
+        "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : Just NotNearMem",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM",
+        "BriefDescription": "Transgress Ingress Bypass : IV",
+        "EventCode": "0xE2",
+        "EventName": "UNC_CHA_RxR_BYPASS.IV",
         "PerPkg": "1",
-        "UMaskExt": "0x800000",
+        "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : Just NonCoherent",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.NONCOH",
+        "BriefDescription": "Transgress Injection Starvation : AD - All",
+        "EventCode": "0xE3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_ALL",
         "PerPkg": "1",
-        "UMaskExt": "0x1000000",
+        "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : Just ISOC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.ISOC",
+        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+        "EventCode": "0xE3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMaskExt": "0x2000000",
+        "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : IRQ - iA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA",
+        "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+        "EventCode": "0xE3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : SF/LLC Evictions",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
+        "BriefDescription": "Transgress Injection Starvation : AK",
+        "EventCode": "0xE3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : PRQ - IOSF",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
+        "BriefDescription": "Transgress Injection Starvation : BL - All",
+        "EventCode": "0xE3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : IRQ - Non iA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA",
+        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
+        "EventCode": "0xE3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : PRQ - Non IOSF",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF",
+        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+        "EventCode": "0xE3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : All from Local IO",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO",
+        "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
+        "EventCode": "0xE3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV",
         "PerPkg": "1",
-        "UMask": "0xC000FF04",
-        "UMaskExt": "0xC000FF",
+        "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : All from Local iA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA",
+        "BriefDescription": "Transgress Injection Starvation : IV",
+        "EventCode": "0xE3",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED.IV",
         "PerPkg": "1",
-        "UMask": "0xC000FF01",
-        "UMaskExt": "0xC000FF",
+        "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : All from Local iA and IO",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
+        "BriefDescription": "Transgress Injection Starvation",
+        "EventCode": "0xe4",
+        "EventName": "UNC_CHA_RxR_CRD_STARVED_1",
         "PerPkg": "1",
-        "UMask": "0xC000FF05",
-        "UMaskExt": "0xC000FF",
+        "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : Just Hits",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
+        "BriefDescription": "Transgress Ingress Allocations : AD - All",
+        "EventCode": "0xE1",
+        "EventName": "UNC_CHA_RxR_INSERTS.AD_ALL",
         "PerPkg": "1",
-        "UMaskExt": "0x01",
+        "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : Just Misses",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
+        "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
+        "EventCode": "0xE1",
+        "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMaskExt": "0x02",
+        "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : MMCFG Access",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG",
+        "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
+        "EventCode": "0xE1",
+        "EventName": "UNC_CHA_RxR_INSERTS.AD_UNCRD",
         "PerPkg": "1",
-        "UMaskExt": "0x20",
+        "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : Just Local Targets",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT",
+        "BriefDescription": "Transgress Ingress Allocations : AK",
+        "EventCode": "0xE1",
+        "EventName": "UNC_CHA_RxR_INSERTS.AK",
         "PerPkg": "1",
-        "UMaskExt": "0x80",
+        "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC",
+        "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
+        "EventCode": "0xE1",
+        "EventName": "UNC_CHA_RxR_INSERTS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMaskExt": "0x200",
+        "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC",
+        "BriefDescription": "Transgress Ingress Allocations : BL - All",
+        "EventCode": "0xE1",
+        "EventName": "UNC_CHA_RxR_INSERTS.BL_ALL",
         "PerPkg": "1",
-        "UMaskExt": "0x400",
+        "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : Just NearMem",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM",
+        "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
+        "EventCode": "0xE1",
+        "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMaskExt": "0x400000",
+        "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : Just NotNearMem",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM",
+        "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
+        "EventCode": "0xE1",
+        "EventName": "UNC_CHA_RxR_INSERTS.BL_UNCRD",
         "PerPkg": "1",
-        "UMaskExt": "0x800000",
+        "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : Just NonCoherent",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH",
+        "BriefDescription": "Transgress Ingress Allocations : IV",
+        "EventCode": "0xE1",
+        "EventName": "UNC_CHA_RxR_INSERTS.IV",
         "PerPkg": "1",
-        "UMaskExt": "0x1000000",
+        "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : Just ISOC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC",
+        "BriefDescription": "Transgress Ingress Occupancy : AD - All",
+        "EventCode": "0xE0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_ALL",
         "PerPkg": "1",
-        "UMaskExt": "0x2000000",
+        "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
+        "EventCode": "0xE0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
-    {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR1",
+    {
+        "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
+        "EventCode": "0xE0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "Transgress Ingress Occupancy : AK",
+        "EventCode": "0xE0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.AK",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
+        "EventCode": "0xE0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "Transgress Ingress Occupancy : BL - All",
+        "EventCode": "0xE0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
+        "EventCode": "0xE0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
+        "EventCode": "0xE0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "Transgress Ingress Occupancy : IV",
+        "EventCode": "0xE0",
+        "EventName": "UNC_CHA_RxR_OCCUPANCY.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x81",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "Snoop filter capacity evictions for E-state entries.",
+        "EventCode": "0x3D",
+        "EventName": "UNC_CHA_SF_EVICTION.E_STATE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x81",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "Snoop filter capacity evictions for M-state entries.",
+        "EventCode": "0x3D",
+        "EventName": "UNC_CHA_SF_EVICTION.M_STATE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x81",
-        "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "Snoop filter capacity evictions for S-state entries.",
+        "EventCode": "0x3D",
+        "EventName": "UNC_CHA_SF_EVICTION.S_STATE",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Counts snoop filter capacity evictions for entries tracking shared lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR0",
+        "BriefDescription": "Snoops Sent : All",
+        "EventCode": "0x51",
+        "EventName": "UNC_CHA_SNOOPS_SENT.ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Snoops Sent : All : Counts the number of snoops issued by the HA.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "Snoops Sent : Broadcast snoops for Local Requests",
+        "EventCode": "0x51",
+        "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Snoops Sent : Broadcast snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA responding to local requests",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "Snoops Sent : Directed snoops for Local Requests",
+        "EventCode": "0x51",
+        "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Snoops Sent : Directed snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA responding to local requests",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "Snoops Sent : Snoops sent for Local Requests",
+        "EventCode": "0x51",
+        "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Snoops Sent : Snoops sent for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA responding to local requests",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "Snoop Responses Received Local : RspCnflct",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Snoop Responses Received Local : RspCnflct : Number of snoop responses received for a Local  request : Filters for snoops responses of RspConflict to local CA requests.  This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent.  This triggers conflict resolution hardware.  This covers both RspCnflct and RspCnflctWbI.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "Snoop Responses Received Local : RspFwd",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Snoop Responses Received Local : RspFwd : Number of snoop responses received for a Local  request : Filters for a snoop response of RspFwd to local CA requests.  This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Snoop Responses Received Local : Rsp*FWD*WB : Number of snoop responses received for a Local  request : Filters for a snoop response of Rsp*Fwd*WB to local CA requests.  This snoop response is only used in 4s systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "Snoop Responses Received Local : RspI",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Snoop Responses Received Local : RspI : Number of snoop responses received for a Local  request : Filters for snoops responses of RspI to local CA requests.  RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "Snoop Responses Received Local : RspIFwd",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Snoop Responses Received Local : RspIFwd : Number of snoop responses received for a Local  request : Filters for snoop responses of RspIFwd to local CA requests.  This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states.  This is commonly returned with RFO transactions.  It can be either a HitM or a HitFE.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "Snoop Responses Received Local : RspS",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Snoop Responses Received Local : RspS : Number of snoop responses received for a Local  request : Filters for snoop responses of RspS to local CA requests.  RspS is returned when a remote cache has data but is not forwarding it.  It is a way to let the requesting socket know that it cannot allocate the data in E state.  No data is sent with S RspS.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "Snoop Responses Received Local : RspSFwd",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Snoop Responses Received Local : RspSFwd : Number of snoop responses received for a Local  request : Filters for a snoop response of RspSFwd to local CA requests.  This is returned when a remote caching agent forwards data but holds on to its currently copy.  This is common for data and code reads that hit in a remote socket in E or F state.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "Snoop Responses Received Local : Rsp*WB",
+        "EventCode": "0x5D",
+        "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Snoop Responses Received Local : Rsp*WB : Number of snoop responses received for a Local  request : Filters for a snoop response of RspIWB or RspSWB to local CA requests.  This is returned when a non-RFO request hits in M state.  Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured.  InvItoE transactions will also return RspIWB because they must acquire ownership.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR1",
+        "BriefDescription": "Misc Snoop Responses Received : MtoI RspIDataM",
+        "EventCode": "0x6B",
+        "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM",
+        "EventCode": "0x6B",
+        "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit LLC",
+        "EventCode": "0x6B",
+        "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit SF",
+        "EventCode": "0x6B",
+        "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit LLC",
+        "EventCode": "0x6B",
+        "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit SF",
+        "EventCode": "0x6B",
+        "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x89",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x89",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x89",
-        "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR0",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
+        "EventCode": "0xD0",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8B",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8B",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8B",
-        "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
+        "EventCode": "0xD2",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR1",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
+        "EventCode": "0xD4",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR0",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
+        "EventCode": "0xD6",
+        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
+        "EventCode": "0xD1",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
+        "EventCode": "0xD1",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
+        "EventCode": "0xD1",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
+        "EventCode": "0xD3",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
+        "EventCode": "0xD3",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
+        "EventCode": "0xD3",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
+        "EventCode": "0xD5",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR1",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
+        "EventCode": "0xD5",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
+        "EventCode": "0xD5",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
+        "EventCode": "0xD7",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
+        "EventCode": "0xD7",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
+        "EventCode": "0xD7",
+        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "TOR Inserts : All",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.ALL",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "TOR Inserts : All : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001ffff",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "TOR Inserts : DDR4 Access",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.DDR",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "TOR Inserts : DDR4 Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8D",
-        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.DDR",
+        "Deprecated": "1",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.DDR4",
         "PerPkg": "1",
-        "UMask": "0x01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8D",
-        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "TOR Inserts : SF/LLC Evictions",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.EVICT",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Inserts : SF/LLC Evictions : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8D",
-        "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "TOR Inserts : Just Hits",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.HIT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Inserts : Just Hits : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR0",
+        "BriefDescription": "TOR Inserts : All requests from iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Inserts : All requests from iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Inserts : CLFlushes issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8c7ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "TOR Inserts : CLFlushOpts issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Inserts : CLFlushOpts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8d7ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "TOR Inserts : CRDs issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "TOR Inserts : CRDs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc80fff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "TOR Inserts; CRd Pref from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc88fff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc837ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc827ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8a7ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8F",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8F",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc80ffd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8F",
-        "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc88ffd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Distress signal asserted : Vertical",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_CHA_DISTRESS_ASSERTED.VERT",
+        "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to page walks that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc837fd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Distress signal asserted : Horizontal",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_CHA_DISTRESS_ASSERTED.HORZ",
+        "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc827fd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Local",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_LOCAL",
+        "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8a7fd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Remote",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_NONLOCAL",
+        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc807fd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_IV",
+        "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc887fd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Stalled -  No Credit",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
+        "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBA",
-        "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
+        "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc80ffe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBA",
-        "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
+        "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc88ffe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB6",
-        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+        "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc837fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB6",
-        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD",
+        "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc827fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB6",
-        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8a7fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB6",
-        "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+        "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc867fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBB",
-        "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
+        "BriefDescription": "TOR Inserts; WCiL misses from local IA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc86ffe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBB",
-        "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_ODD",
+        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc807fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBB",
-        "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc887fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBB",
-        "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
+        "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc877de01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB7",
-        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86ffe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB7",
-        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD",
+        "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc867fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB7",
-        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc87fde01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB7",
-        "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+        "BriefDescription": "TOR Inserts : RFOs issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "TOR Inserts : RFOs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc807ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB8",
-        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+        "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc887ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB8",
-        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD",
+        "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core.  Non Modified Write Backs",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "WbEFtoEs issued by iA Cores .  (Non Modified Write Backs)  :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.  Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc3fff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB8",
-        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "TOR Inserts : WBEFtoIs issued by an IA Core.  Non Modified Write Backs",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "WbEFtoIs issued by iA Cores .  (Non Modified Write Backs)  :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.  Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc37ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB8",
-        "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+        "BriefDescription": "TOR Inserts : WBMtoEs issued by an IA Core.  Non Modified Write Backs",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "WbMtoEs issued by iA Cores .  (Non Modified Write Backs)  :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.  Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc2fff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use : Left",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB9",
-        "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT",
+        "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "WbMtoIs issued by iA Cores .  (Modified Write Backs)  :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.  Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc27ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use : Right",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB9",
-        "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT",
+        "BriefDescription": "TOR Inserts : WBStoIs issued by an IA Core.  Non Modified Write Backs",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "WbStoIs issued by iA Cores .  (Non Modified Write Backs)  :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.  Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc67ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE6",
-        "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST0",
+        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86fff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE6",
-        "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST1",
+        "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc867ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAC",
-        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD",
+        "BriefDescription": "TOR Inserts : All requests from IO Devices",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Inserts : All requests from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001ff04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAC",
-        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK",
+        "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Inserts : CLFlushes issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8c3ff04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAC",
-        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL",
+        "BriefDescription": "TOR Inserts : All requests from IO Devices that hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Inserts : All requests from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fd04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAC",
-        "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV",
+        "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc43fd04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAA",
-        "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD",
+        "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcd43fd04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAA",
-        "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK",
+        "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8f3fd04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAA",
-        "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL",
+        "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc803fd04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAA",
-        "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV",
+        "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc43ff04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAA",
-        "EventName": "UNC_CHA_RING_BOUNCES_VERT.AKC",
+        "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcd43ff04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAD",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD",
+        "BriefDescription": "TOR Inserts : All requests from IO Devices that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Inserts : All requests from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fe04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAD",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK",
+        "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc43fe04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAD",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL",
+        "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcd43fe04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAD",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV",
+        "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8f3fe04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAD",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1",
+        "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc803fe04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAB",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD",
+        "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8f3ff04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAB",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK",
+        "BriefDescription": "TOR Inserts : RFOs issued by IO Devices",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc803ff04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAB",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL",
+        "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Inserts : WbMtoIs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc23ff04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAB",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV",
+        "BriefDescription": "TOR Inserts : IRQ - iA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "TOR Inserts : IRQ - iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts. : From an iA Core",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAB",
-        "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AKC",
+        "BriefDescription": "TOR Inserts : IRQ - Non iA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA",
         "PerPkg": "1",
+        "PublicDescription": "TOR Inserts : IRQ - Non iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_UNCRD",
+        "BriefDescription": "TOR Inserts : Just ISOC",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.ISOC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Inserts : Just ISOC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_UNCRD",
+        "BriefDescription": "TOR Inserts : Just Local Targets",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Inserts : Just Local Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD",
+        "BriefDescription": "TOR Inserts : All from Local iA and IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "TOR Inserts : All from Local iA and IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts. : All locally initiated requests",
+        "UMask": "0xc000ff05",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD",
+        "BriefDescription": "TOR Inserts : All from Local iA",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "TOR Inserts : All from Local iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores",
+        "UMask": "0xc000ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_ALL",
+        "BriefDescription": "TOR Inserts : All from Local IO",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "TOR Inserts : All from Local IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic",
+        "UMask": "0xc000ff04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_ALL",
+        "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_CHA_RxR_BYPASS.AD_UNCRD",
+        "BriefDescription": "TOR Inserts : Just Misses",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.MISS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Inserts : Just Misses : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_CHA_RxR_BYPASS.AK",
+        "BriefDescription": "TOR Inserts : MMCFG Access",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.MMCFG",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Inserts : MMCFG Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_CHA_RxR_BYPASS.BL_UNCRD",
+        "BriefDescription": "TOR Inserts : Just NearMem",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.NEARMEM",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Inserts : Just NearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_CHA_RxR_BYPASS.IV",
+        "BriefDescription": "TOR Inserts : Just NonCoherent",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.NONCOH",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "TOR Inserts : Just NonCoherent : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD",
+        "BriefDescription": "TOR Inserts : Just NotNearMem",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "TOR Inserts : Just NotNearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD",
+        "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_CHA_RxR_BYPASS.AKC_UNCRD",
+        "BriefDescription": "TOR Inserts : PRQ - IOSF",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "TOR Inserts : PRQ - IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts. : From a PCIe Device",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_CHA_RxR_BYPASS.AD_ALL",
+        "BriefDescription": "TOR Inserts : PRQ - Non IOSF",
+        "EventCode": "0x35",
+        "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "TOR Inserts : PRQ - Non IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_CHA_RxR_BYPASS.BL_ALL",
+        "BriefDescription": "TOR Occupancy : DDR4 Access",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "TOR Occupancy : DDR4 Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_UNCRD",
+        "BriefDescription": "TOR Occupancy : SF/LLC Evictions",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Occupancy : SF/LLC Evictions : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.AK",
+        "BriefDescription": "TOR Occupancy : Just Hits",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Occupancy : Just Hits : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_UNCRD",
+        "BriefDescription": "TOR Occupancy : All requests from iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.IV",
+        "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8c7ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD",
+        "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8d7ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD",
+        "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "TOR Occupancy : CRDs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc80fff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV",
+        "BriefDescription": "TOR Occupancy; CRd Pref from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter",
+        "UMask": "0xc88fff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_ALL",
+        "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc837ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_ALL",
+        "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc827ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_CHA_RxR_INSERTS.AD_UNCRD",
+        "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8a7ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_CHA_RxR_INSERTS.AK",
+        "BriefDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_CHA_RxR_INSERTS.BL_UNCRD",
+        "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc80ffd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_CHA_RxR_INSERTS.IV",
+        "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc88ffd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD",
+        "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc837fd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD",
+        "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc827fd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_CHA_RxR_INSERTS.AKC_UNCRD",
+        "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8a7fd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_CHA_RxR_INSERTS.AD_ALL",
+        "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc807fd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_CHA_RxR_INSERTS.BL_ALL",
+        "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc887fd01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_UNCRD",
+        "BriefDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.AK",
+        "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc80ffe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_UNCRD",
+        "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc88ffe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.IV",
+        "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc837fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD",
+        "BriefDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc827fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD",
+        "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8a7fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.AKC_UNCRD",
+        "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc867fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_ALL",
+        "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+        "UMask": "0xc86ffe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_ALL",
+        "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc807fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+        "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc887fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+        "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc877de01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86ffe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+        "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc867fe01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+        "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc87fde01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+        "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc807ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
+        "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc887ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
+        "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc27ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc86fff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+        "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc867ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+        "BriefDescription": "TOR Occupancy : All requests from IO Devices",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001ff04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+        "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Devices",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8c3ff04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+        "BriefDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fd04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+        "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc43fd04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
+        "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcd43fd04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD2",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
+        "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8f3fd04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+        "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc803fd04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+        "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc43ff04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+        "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcd43ff04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+        "BriefDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc001fe04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+        "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc43fe04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+        "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcd43fe04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
+        "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8f3fe04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+        "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc803fe04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+        "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc8f3ff04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+        "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xc803ff04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+        "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0xcc23ff04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+        "BriefDescription": "TOR Occupancy : IRQ - iA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "TOR Occupancy : IRQ - iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts. : From an iA Core",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+        "BriefDescription": "TOR Occupancy : IRQ - Non iA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA",
         "PerPkg": "1",
+        "PublicDescription": "TOR Occupancy : IRQ - Non iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
         "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+        "BriefDescription": "TOR Occupancy : Just ISOC",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "TOR Occupancy : Just ISOC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+        "BriefDescription": "TOR Occupancy : Just Local Targets",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "TOR Occupancy : Just Local Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+        "BriefDescription": "TOR Occupancy : All from Local iA and IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "TOR Occupancy : All from Local iA and IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts. : All locally initiated requests",
+        "UMask": "0xc000ff05",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD1",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+        "BriefDescription": "TOR Occupancy : All from Local iA",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Occupancy : All from Local iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores",
+        "UMask": "0xc000ff01",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD1",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+        "BriefDescription": "TOR Occupancy : All from Local IO",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Occupancy : All from Local IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic",
+        "UMask": "0xc000ff04",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD1",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+        "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD3",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+        "BriefDescription": "TOR Occupancy : Just Misses",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Occupancy : Just Misses : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD3",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+        "BriefDescription": "TOR Occupancy : MMCFG Access",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Occupancy : MMCFG Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD3",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+        "BriefDescription": "TOR Occupancy : Just NearMem",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Occupancy : Just NearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD5",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+        "BriefDescription": "TOR Occupancy : Just NonCoherent",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Occupancy : Just NonCoherent : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD5",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+        "BriefDescription": "TOR Occupancy : Just NotNearMem",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Occupancy : Just NotNearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD5",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+        "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD7",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+        "BriefDescription": "TOR Occupancy : PRQ - IOSF",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "TOR Occupancy : PRQ - IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts. : From a PCIe Device",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD7",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+        "BriefDescription": "TOR Occupancy : PRQ - Non IOSF",
+        "EventCode": "0x36",
+        "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "TOR Occupancy : PRQ - Non IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interrupts.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD7",
-        "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+        "BriefDescription": "CMS Horizontal ADS Used : AD - All",
+        "EventCode": "0xA6",
+        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
         "EventCode": "0xA6",
-        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_UNCRD",
+        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
         "EventCode": "0xA6",
-        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_UNCRD",
+        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal ADS Used : BL - All",
         "EventCode": "0xA6",
-        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD",
+        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xA6",
         "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
         "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
         "EventCode": "0xA6",
-        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_ALL",
+        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_UNCRD",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
+        "Unit": "CHA"
+    },
+    {
+        "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
+        "EventCode": "0xA7",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_ALL",
+        "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
+        "EventCode": "0xA7",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xA7",
         "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Bypass Used : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xA7",
         "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
         "EventCode": "0xA7",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_UNCRD",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
         "EventCode": "0xA7",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
         "EventCode": "0xA7",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
         "EventCode": "0xA7",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Bypass Used : IV",
         "EventCode": "0xA7",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AKC_UNCRD",
+        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_ALL",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
+        "EventCode": "0xA2",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_ALL",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
+        "EventCode": "0xA2",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xA2",
         "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xA2",
         "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
         "EventCode": "0xA2",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
         "EventCode": "0xA2",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
         "EventCode": "0xA2",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
         "EventCode": "0xA2",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
         "EventCode": "0xA2",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_ALL",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
+        "EventCode": "0xA3",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_ALL",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
+        "EventCode": "0xA3",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xA3",
         "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xA3",
         "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
         "EventCode": "0xA3",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_UNCRD",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
         "EventCode": "0xA3",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
         "EventCode": "0xA3",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
         "EventCode": "0xA3",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
         "EventCode": "0xA3",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
+        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_ALL",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
+        "EventCode": "0xA1",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_ALL",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
+        "EventCode": "0xA1",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xA1",
         "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Inserts : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xA1",
         "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
         "EventCode": "0xA1",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_UNCRD",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
         "EventCode": "0xA1",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
         "EventCode": "0xA1",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
         "EventCode": "0xA1",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Inserts : IV",
         "EventCode": "0xA1",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AKC_UNCRD",
+        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_ALL",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
+        "EventCode": "0xA4",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_ALL",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
+        "EventCode": "0xA4",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xA4",
         "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress NACKs : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xA4",
         "EventName": "UNC_CHA_TxR_HORZ_NACK.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
         "EventCode": "0xA4",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_UNCRD",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
         "EventCode": "0xA4",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.IV",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
         "EventCode": "0xA4",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
         "EventCode": "0xA4",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress NACKs : IV",
         "EventCode": "0xA4",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.AKC_UNCRD",
+        "EventName": "UNC_CHA_TxR_HORZ_NACK.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_ALL",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
+        "EventCode": "0xA0",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_ALL",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
+        "EventCode": "0xA0",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xA0",
         "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xA0",
         "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_UNCRD",
-        "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
         "EventCode": "0xA0",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
         "EventCode": "0xA0",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xA0",
         "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
         "EventCode": "0xA0",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
         "EventCode": "0xA0",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_ALL",
+        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_ALL",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
+        "EventCode": "0xA5",
+        "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xA5",
         "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xA5",
         "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_UNCRD",
-        "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
         "EventCode": "0xA5",
-        "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV",
+        "EventName": "UNC_CHA_TxR_HORZ_STARVED.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
         "EventCode": "0xA5",
-        "EventName": "UNC_CHA_TxR_HORZ_STARVED.AKC_UNCRD",
+        "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
         "EventCode": "0xA5",
-        "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_ALL",
+        "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
         "EventCode": "0xA5",
-        "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_ALL",
+        "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9C",
         "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
         "EventCode": "0x9C",
-        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
         "EventCode": "0x9C",
-        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9C",
         "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
         "UMask": "0x40",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9D",
         "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
         "EventCode": "0x9D",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
         "EventCode": "0x9D",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
         "EventCode": "0x9D",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
         "EventCode": "0x9D",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
         "EventCode": "0x9D",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
         "EventCode": "0x9D",
-        "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV_AG1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9E",
         "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9E",
         "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x94",
         "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
         "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
         "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
         "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.IV_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
         "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
         "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
         "EventCode": "0x94",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x95",
         "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x95",
         "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x96",
         "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
         "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
         "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
         "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.IV_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
         "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
         "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
         "EventCode": "0x96",
-        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x97",
         "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x97",
         "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x92",
         "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
         "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
         "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
         "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.IV_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
         "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
         "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
         "EventCode": "0x92",
-        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_INSERTS0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x93",
         "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x93",
         "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x98",
         "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
         "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
         "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
         "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK0.IV_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
         "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
         "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress NACKs : IV",
         "EventCode": "0x98",
-        "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_NACK0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x99",
         "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x99",
         "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x90",
         "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
         "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
         "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
         "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.IV_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
         "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
         "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
         "EventCode": "0x90",
-        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x91",
         "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x91",
         "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9A",
         "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
         "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
         "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
         "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED0.IV_AG0",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
         "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
         "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
         "EventCode": "0x9A",
-        "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG1",
+        "EventName": "UNC_CHA_TxR_VERT_STARVED0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9B",
         "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9B",
         "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9B",
         "EventName": "UNC_CHA_TxR_VERT_STARVED1.TGC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Vertical AD Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB0",
-        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB0",
-        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD",
-        "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical AD Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB0",
         "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB0",
         "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB4",
-        "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_EVEN",
+        "BriefDescription": "Vertical AD Ring In Use : Up and Even",
+        "EventCode": "0xB0",
+        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB4",
-        "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_ODD",
+        "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
+        "EventCode": "0xB0",
+        "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB4",
         "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB4",
         "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB1",
-        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN",
+        "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
+        "EventCode": "0xB4",
+        "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB1",
-        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD",
+        "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
+        "EventCode": "0xB4",
+        "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical AK Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB1",
         "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB1",
         "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB2",
-        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN",
+        "BriefDescription": "Vertical AK Ring In Use : Up and Even",
+        "EventCode": "0xB1",
+        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB2",
-        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD",
+        "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
+        "EventCode": "0xB1",
+        "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical BL Ring in Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB2",
         "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB2",
         "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical IV Ring in Use : Up",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB3",
-        "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP",
+        "BriefDescription": "Vertical BL Ring in Use : Up and Even",
+        "EventCode": "0xB2",
+        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical IV Ring in Use : Down",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB3",
-        "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN",
+        "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
+        "EventCode": "0xB2",
+        "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB5",
-        "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_EVEN",
+        "BriefDescription": "Vertical IV Ring in Use : Down",
+        "EventCode": "0xB3",
+        "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB5",
-        "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_ODD",
+        "BriefDescription": "Vertical IV Ring in Use : Up",
+        "EventCode": "0xB3",
+        "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB5",
         "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
         "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xB5",
         "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Source Throttle",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xae",
-        "EventName": "UNC_CHA_RING_SRC_THRTL",
-        "PerPkg": "1",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Transgress Injection Starvation",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe4",
-        "EventName": "UNC_CHA_RxR_CRD_STARVED_1",
-        "PerPkg": "1",
-        "Unit": "CHA"
-    },
-    {
-        "BriefDescription": "Cache and Snoop Filter Lookups; Any Request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.ALL",
-        "PerPkg": "1",
-        "UMask": "0x1FFFFF",
-        "UMaskExt": "0x1FFF",
+        "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD",
+        "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
+        "EventCode": "0xB5",
+        "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x1bc1ff",
-        "UMaskExt": "0x1bc1",
+        "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cache Lookups : Flush or Invalidate Requests",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV",
+        "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
+        "EventCode": "0xB5",
+        "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x1A44FF",
-        "UMaskExt": "0x1A44",
+        "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.CODE",
+        "BriefDescription": "WbPushMtoI : Pushed to LLC",
+        "EventCode": "0x56",
+        "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC",
         "PerPkg": "1",
-        "UMask": "0x1bd0ff",
-        "UMaskExt": "0x1bd0",
+        "PublicDescription": "WbPushMtoI : Pushed to LLC : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was able to push WbPushMToI to LLC",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF",
+        "BriefDescription": "WbPushMtoI : Pushed to Memory",
+        "EventCode": "0x56",
+        "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM",
         "PerPkg": "1",
-        "UMask": "0xC88FFD01",
-        "UMaskExt": "0xC88FFD",
+        "PublicDescription": "WbPushMtoI : Pushed to Memory : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM)",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0",
         "PerPkg": "1",
-        "UMask": "0xC887FD01",
-        "UMaskExt": "0xC887FD",
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC0 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 0 only.",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1",
         "PerPkg": "1",
-        "UMask": "0xC88FFE01",
-        "UMaskExt": "0xC88FFE",
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC1 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 1 only.",
+        "UMask": "0x2",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC10",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC10",
         "PerPkg": "1",
-        "UMask": "0xC8A7FE01",
-        "UMaskExt": "0xC8A7FE",
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC10 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 10 only.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC11",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC11",
         "PerPkg": "1",
-        "UMask": "0xC887FE01",
-        "UMaskExt": "0xC887FE",
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC11 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 11 only.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC12",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC12",
         "PerPkg": "1",
-        "UMask": "0xC803FD04",
-        "UMaskExt": "0xC803FD",
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC12 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 12 only.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC13",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC13",
         "PerPkg": "1",
-        "UMask": "0xCC43FD04",
-        "UMaskExt": "0xCC43FD",
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC13 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 13 only.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2",
         "PerPkg": "1",
-        "UMask": "0xC803FD04",
-        "UMaskExt": "0xC803FD",
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC2 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 2 only.",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : RFOs issued by IO Devices",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3",
         "PerPkg": "1",
-        "UMask": "0xC803FF04",
-        "UMaskExt": "0xC803FF",
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC3 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 3 only.",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts; CRd Pref from local IA",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4",
         "PerPkg": "1",
-        "UMask": "0xC88FFF01",
-        "UMaskExt": "0xC88FFF",
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC4 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 4 only.",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5",
         "PerPkg": "1",
-        "UMask": "0xC803FF04",
-        "UMaskExt": "0xC803FF",
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC5 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 5 only.",
+        "UMask": "0x20",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC6",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC6",
         "PerPkg": "1",
-        "UMask": "0xCC43FF04",
-        "UMaskExt": "0xCC43FF",
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC6 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 6 only.",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC7",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC7",
         "PerPkg": "1",
-        "UMask": "0xC887FF01",
-        "UMaskExt": "0xC887FF",
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC7 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 7 only.",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; CRd Pref from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC8",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC8",
         "PerPkg": "1",
-        "UMask": "0xC88FFF01",
-        "UMaskExt": "0xC88FFF",
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC8 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 8 only.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : CLFlushOpts issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT",
+        "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC9",
+        "EventCode": "0x5A",
+        "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC9",
         "PerPkg": "1",
-        "UMask": "0xC8D7FF01",
-        "UMaskExt": "0xC8D7FF",
+        "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC9 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 9 only.",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI",
+        "BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict",
+        "EventCode": "0x6f",
+        "EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT",
         "PerPkg": "1",
-        "UMask": "0xCC23FF04",
-        "UMaskExt": "0xCC23FF",
+        "PublicDescription": "XPT Prefetches : Dropped (on 0?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention",
+        "UMask": "0x8",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH",
+        "BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits",
+        "EventCode": "0x6f",
+        "EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD",
         "PerPkg": "1",
-        "UMask": "0xC8C3FF04",
-        "UMaskExt": "0xC8C3FF",
+        "PublicDescription": "XPT Prefetches : Dropped (on 0?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits",
+        "UMask": "0x4",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI",
+        "BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict",
+        "EventCode": "0x6f",
+        "EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT",
         "PerPkg": "1",
-        "UMask": "0xcc27ff01",
-        "UMaskExt": "0xcc27ff",
+        "PublicDescription": "XPT Prefetches : Dropped (on 1?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention",
+        "UMask": "0x80",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR",
+        "BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits",
+        "EventCode": "0x6f",
+        "EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD",
         "PerPkg": "1",
-        "UMask": "0xc867fe01",
-        "UMaskExt": "0xc867fe",
+        "PublicDescription": "XPT Prefetches : Dropped (on 1?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits",
+        "UMask": "0x40",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR",
+        "BriefDescription": "XPT Prefetches : Sent (on 0?)",
+        "EventCode": "0x6f",
+        "EventName": "UNC_CHA_XPT_PREF.SENT0",
         "PerPkg": "1",
-        "UMask": "0xc86ffe01",
-        "UMaskExt": "0xc86ffe",
+        "PublicDescription": "XPT Prefetches : Sent (on 0?) : Number of XPT prefetches sent",
+        "UMask": "0x1",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cache Lookups : RFO Request Filter",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.RFO_F",
+        "BriefDescription": "XPT Prefetches : Sent (on 1?)",
+        "EventCode": "0x6f",
+        "EventName": "UNC_CHA_XPT_PREF.SENT1",
         "PerPkg": "1",
-        "UMaskExt": "0x08",
+        "PublicDescription": "XPT Prefetches : Sent (on 1?) : Number of XPT prefetches sent",
+        "UMask": "0x10",
         "Unit": "CHA"
     },
     {
-        "BriefDescription": "Cache Lookups : Transactions homed locally Filter",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN",
         "PerPkg": "1",
-        "UMaskExt": "0x800",
-        "Unit": "CHA"
+        "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : All Request Filter",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.ANY_F",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN",
         "PerPkg": "1",
-        "UMaskExt": "0x20",
-        "Unit": "CHA"
+        "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : Data Read Request Filter",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN",
         "PerPkg": "1",
-        "UMaskExt": "0x01",
-        "Unit": "CHA"
+        "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : Write Request Filter",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN",
         "PerPkg": "1",
-        "UMaskExt": "0x02",
-        "Unit": "CHA"
+        "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : Flush or Invalidate Filter",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN",
         "PerPkg": "1",
-        "UMaskExt": "0x04",
-        "Unit": "CHA"
+        "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : CRd Request Filter",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN",
         "PerPkg": "1",
-        "UMaskExt": "0x10",
-        "Unit": "CHA"
+        "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : Local request Filter",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN",
         "PerPkg": "1",
-        "UMaskExt": "0x40",
-        "Unit": "CHA"
+        "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : All Misses",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x1fe001",
-        "UMaskExt": "0x1fe0",
-        "Unit": "CHA"
+        "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART0_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x1fc1ff",
-        "UMaskExt": "0x1fc1",
-        "Unit": "CHA"
+        "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART0_FREERUN",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : Data Read Misses",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART1_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x1bc101",
-        "UMaskExt": "0x1bc1",
-        "Unit": "CHA"
+        "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART1_FREERUN",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.DMND_READ_LOCAL",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART2_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x841ff",
-        "UMaskExt": "0x841",
-        "Unit": "CHA"
+        "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART2_FREERUN",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. ",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART3_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x842ff",
-        "UMaskExt": "0x842",
-        "Unit": "CHA"
+        "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART3_FREERUN",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.RFO_LOCAL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "Deprecated": "1",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.RFO_PREF_LOCAL",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART4_FREERUN",
         "PerPkg": "1",
-        "UMask": "0x888ff",
-        "UMaskExt": "0x888",
-        "Unit": "CHA"
+        "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART4_FREERUN",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART5_FREERUN",
+        "PerPkg": "1",
+        "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART5_FREERUN",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART6_FREERUN",
         "PerPkg": "1",
-        "UMask": "0xC867FF01",
-        "UMaskExt": "0xC867FF",
-        "Unit": "CHA"
+        "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART6_FREERUN",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL",
+        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART7_FREERUN",
         "PerPkg": "1",
-        "UMask": "0xC86FFF01",
-        "UMaskExt": "0xC86FFF",
-        "Unit": "CHA"
+        "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART7_FREERUN",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : DDR4 Access",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.DDR",
+        "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller",
+        "EventCode": "0x01",
+        "EventName": "UNC_IIO_CLOCKTICKS",
         "PerPkg": "1",
-        "UMaskExt": "0x04",
-        "Unit": "CHA"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : DDR4 Access",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR",
+        "BriefDescription": "Free running counter that increments for IIO clocktick",
+        "EventName": "UNC_IIO_CLOCKTICKS_FREERUN",
         "PerPkg": "1",
-        "UMaskExt": "0x04",
-        "Unit": "CHA"
+        "PublicDescription": "Free running counter that increments for integrated IO (IIO) traffic controller clockticks",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR",
+        "BriefDescription": "PCIe Completion Buffer Inserts : All Ports",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0xC8F3FD04",
-        "UMaskExt": "0xC8F3FD",
-        "Unit": "CHA"
+        "PortMask": "0xFF",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0xC867FE01",
-        "UMaskExt": "0xC867FE",
-        "Unit": "CHA"
+        "PortMask": "0xff",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0xC86FFE01",
-        "UMaskExt": "0xC86FFE",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0xC8C7FF01",
-        "UMaskExt": "0xC8C7FF",
-        "Unit": "CHA"
+        "PortMask": "0x02",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0xC8D7FF01",
-        "UMaskExt": "0xC8D7FF",
-        "Unit": "CHA"
+        "PortMask": "0x04",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0xCC27FF01",
-        "UMaskExt": "0xCC27FF",
-        "Unit": "CHA"
+        "PortMask": "0x08",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0xC877DE01",
-        "UMaskExt": "0xC877DE",
-        "Unit": "CHA"
+        "PortMask": "0x10",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0xC87FDE01",
-        "UMaskExt": "0xC87FDE",
-        "Unit": "CHA"
+        "PortMask": "0x20",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0xC867FF01",
-        "UMaskExt": "0xC867FF",
-        "Unit": "CHA"
+        "PortMask": "0x40",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL",
+        "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0xC86FFF01",
-        "UMaskExt": "0xC86FFF",
-        "Unit": "CHA"
+        "PortMask": "0x80",
+        "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7",
+        "UMask": "0x3",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI",
+        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
+        "EventCode": "0xD5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0xCC23FF04",
-        "UMaskExt": "0xCC23FF",
-        "Unit": "CHA"
+        "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7",
+        "UMask": "0xff",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Devices",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH",
+        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
+        "EventCode": "0xd5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0xC8C3FF04",
-        "UMaskExt": "0xC8C3FF",
-        "Unit": "CHA"
+        "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7",
+        "UMask": "0xff",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR",
+        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0",
+        "EventCode": "0xd5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0xCD43FF04",
-        "UMaskExt": "0xCD43FF",
-        "Unit": "CHA"
+        "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR",
+        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 1",
+        "EventCode": "0xd5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0xCD43FD04",
-        "UMaskExt": "0xCD43FD",
-        "Unit": "CHA"
+        "PublicDescription": "PCIe Completion Buffer Occupancy : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR",
+        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 2",
+        "EventCode": "0xd5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0xCD43FE04",
-        "UMaskExt": "0xCD43FE",
-        "Unit": "CHA"
+        "PublicDescription": "PCIe Completion Buffer Occupancy : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core.  Non Modified Write Backs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE",
+        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 3",
+        "EventCode": "0xd5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0xcc3fff01",
-        "UMaskExt": "0xcc3fff",
-        "Unit": "CHA"
+        "PublicDescription": "PCIe Completion Buffer Occupancy : Part 3 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE",
+        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4",
+        "EventCode": "0xd5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0xC837FE01",
-        "UMaskExt": "0xC837FE",
-        "Unit": "CHA"
+        "PublicDescription": "PCIe Completion Buffer Occupancy : Part 4 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE",
+        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 5",
+        "EventCode": "0xd5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0xC837FD01",
-        "UMaskExt": "0xC837FD",
-        "Unit": "CHA"
+        "PublicDescription": "PCIe Completion Buffer Occupancy : Part 5 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5",
+        "UMask": "0x20",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE",
+        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 6",
+        "EventCode": "0xd5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0xC837FF01",
-        "UMaskExt": "0xC837FF",
-        "Unit": "CHA"
+        "PublicDescription": "PCIe Completion Buffer Occupancy : Part 6 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : WBStoIs issued by an IA Core.  Non Modified Write Backs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI",
+        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 7",
+        "EventCode": "0xd5",
+        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7",
+        "FCMask": "0x04",
         "PerPkg": "1",
-        "UMask": "0xcc67ff01",
-        "UMaskExt": "0xcc67ff",
-        "Unit": "CHA"
+        "PublicDescription": "PCIe Completion Buffer Occupancy : Part 7 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7",
+        "UMask": "0x80",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : WBEFtoIs issued by an IA Core.  Non Modified Write Backs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0xcc37ff01",
-        "UMaskExt": "0xcc37ff",
-        "Unit": "CHA"
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Inserts : WBMtoEs issued by an IA Core.  Non Modified Write Backs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x35",
-        "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0xcc2fff01",
-        "UMaskExt": "0xcc2fff",
-        "Unit": "CHA"
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0xC837FF01",
-        "UMaskExt": "0xC837FF",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0xC837FD01",
-        "UMaskExt": "0xC837FD",
-        "Unit": "CHA"
+        "PortMask": "0x02",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x36",
-        "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0xC837FE01",
-        "UMaskExt": "0xC837FE",
-        "Unit": "CHA"
+        "PortMask": "0x04",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : Code Read Misses",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_MISS",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x1BD001",
-        "UMaskExt": "0x1BD0",
-        "Unit": "CHA"
+        "PortMask": "0x08",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : RFO Misses",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.RFO_MISS",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x1BC801",
-        "UMaskExt": "0x1BC8",
-        "Unit": "CHA"
+        "PortMask": "0x10",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : Reads",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.READ",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x1BD9FF",
-        "UMaskExt": "0x1BD9",
-        "Unit": "CHA"
+        "PortMask": "0x20",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : Read Misses",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x1BD901",
-        "UMaskExt": "0x1BD9",
-        "Unit": "CHA"
+        "PortMask": "0x40",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : Locally HOMed Read Misses",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_LOC_HOM",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x0BD901",
-        "UMaskExt": "0x0BD9",
-        "Unit": "CHA"
+        "PortMask": "0x80",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : Remotely HOMed Read Misses",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_REM_HOM",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x13D901",
-        "UMaskExt": "0x13D9",
-        "Unit": "CHA"
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_LOC_HOM",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x09D9FF",
-        "UMaskExt": "0x09D9",
-        "Unit": "CHA"
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.READ_REMOTE_LOC_HOM",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x0A19FF",
-        "UMaskExt": "0x0A19",
-        "Unit": "CHA"
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_REM_HOM",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x11D9FF",
-        "UMaskExt": "0x11D9",
-        "Unit": "CHA"
+        "PortMask": "0x02",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : Reads that Hit the Snoop Filter",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.READ_SF_HIT",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x1BD90E",
-        "UMaskExt": "0x1BD9",
-        "Unit": "CHA"
+        "PortMask": "0x04",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.READ_OR_SNOOP_REMOTE_MISS_REM_HOM",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x161901",
-        "UMaskExt": "0x1619",
-        "Unit": "CHA"
+        "PortMask": "0x08",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : Filters Requests for those that write info into the cache",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x1A42FF",
-        "UMaskExt": "0x1A42",
-        "Unit": "CHA"
+        "PortMask": "0x10",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Cache Lookups : Code Reads",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x1BD0FF",
-        "UMaskExt": "0x1BD0",
-        "Unit": "CHA"
+        "PortMask": "0x20",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x10",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x02",
+        "PortMask": "0x40",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x02",
+        "PortMask": "0x80",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x02",
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x02",
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x01",
-        "UMask": "0x08",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x02",
-        "UMask": "0x08",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x04",
-        "UMask": "0x08",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x80",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART4",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x80",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x08",
+        "PortMask": "0x20",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x02",
+        "PortMask": "0x40",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x02",
+        "PortMask": "0x80",
+        "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x02",
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x02",
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x01",
-        "UMask": "0x08",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x02",
-        "UMask": "0x08",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x04",
-        "UMask": "0x08",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x08",
-        "UMask": "0x08",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x02",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x02",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x40",
-        "UMask": "0x02",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x80",
-        "UMask": "0x02",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x08",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5",
-        "FCMask": "0x07",
-        "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x08",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x08",
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x08",
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
+        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x01",
-        "UMask": "0x10",
+        "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
+        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x02",
-        "UMask": "0x10",
+        "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
+        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x04",
-        "UMask": "0x10",
+        "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
+        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x08",
-        "UMask": "0x10",
+        "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART4",
+        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x10",
+        "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART5",
+        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x10",
+        "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART6",
+        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x40",
-        "UMask": "0x10",
+        "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART7",
+        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+        "EventCode": "0xc0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x80",
-        "UMask": "0x10",
+        "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x20",
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x20",
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x20",
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x20",
+        "PortMask": "0x02",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART4",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x20",
+        "PortMask": "0x04",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART5",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x20",
+        "PortMask": "0x08",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART6",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x20",
+        "PortMask": "0x10",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART7",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x20",
+        "PortMask": "0x20",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x40",
+        "PortMask": "0x40",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x40",
+        "PortMask": "0x80",
+        "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x40",
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x40",
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART4",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x40",
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART5",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x40",
+        "PortMask": "0x02",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART6",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x40",
+        "PortMask": "0x04",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART7",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x40",
+        "PortMask": "0x08",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x80",
+        "PortMask": "0x10",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x80",
+        "PortMask": "0x20",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x80",
+        "PortMask": "0x40",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x80",
+        "PortMask": "0x80",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART4",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x80",
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART5",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x80",
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART6",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x80",
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
         "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART7",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x80",
+        "PortMask": "0x02",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x02",
+        "PortMask": "0x04",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x02",
+        "PortMask": "0x08",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x02",
+        "PortMask": "0x10",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x02",
+        "PortMask": "0x20",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x08",
+        "PortMask": "0x40",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5",
+        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC0",
+        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x08",
+        "PortMask": "0x80",
+        "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x08",
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x08",
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
         "EventCode": "0x83",
         "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x01",
+        "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
         "EventCode": "0x83",
         "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x02",
+        "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
         "EventCode": "0x83",
         "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x04",
+        "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
         "EventCode": "0x83",
         "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x08",
+        "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
         "EventCode": "0x83",
         "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x10",
+        "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
         "EventCode": "0x83",
         "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x20",
+        "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
         "EventCode": "0x83",
         "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x40",
+        "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
         "EventCode": "0x83",
         "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x80",
+        "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Messages",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x40",
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Messages",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x40",
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Messages",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x40",
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Messages",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x40",
+        "PortMask": "0x02",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Messages",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART4",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x40",
+        "PortMask": "0x04",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Messages",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART5",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x40",
+        "PortMask": "0x08",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Messages",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART6",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x40",
+        "PortMask": "0x10",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Messages",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
         "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART7",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x40",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": IOTLB lookups first",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": IOTLB lookups all",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS",
-        "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": IOTLB Hits to a 4K Page",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_IIO_IOMMU0.4K_HITS",
-        "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": IOTLB Hits to a 2M Page",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_IIO_IOMMU0.2M_HITS",
-        "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": IOTLB Hits to a 1G Page",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_IIO_IOMMU0.1G_HITS",
-        "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": IOTLB Fills (same as IOTLB miss)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_IIO_IOMMU0.MISSES",
-        "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": Context cache lookups",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS",
-        "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": Context cache hits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS",
-        "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": PageWalk cache lookup",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": IOMMU memory access",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES",
-        "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": Cycles PWT full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_IOMMU1.CYC_PWT_FULL",
-        "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
         "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": ": Interrupt Entry cache lookup",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS",
-        "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "IIO"
-    },
-    {
-        "BriefDescription": ": Interrupt Entry cache hit",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x40",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
         "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0",
+        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PortMask": "0x80",
+        "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "AND Mask/match for debug bus : PCIE bus",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1",
+        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1",
+        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1",
+        "BriefDescription": "PCI Express bandwidth reading at IIO, part 0",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PortMask": "0x01",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1",
+        "BriefDescription": "PCI Express bandwidth reading at IIO, part 1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PortMask": "0x02",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1",
+        "BriefDescription": "PCI Express bandwidth reading at IIO, part 2",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PortMask": "0x04",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0",
+        "BriefDescription": "PCI Express bandwidth reading at IIO, part 3",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PortMask": "0x08",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "OR Mask/match for debug bus : PCIE bus",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1",
+        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PortMask": "0x10",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1",
+        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PortMask": "0x20",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1",
+        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PortMask": "0x40",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1",
+        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PortMask": "0x80",
+        "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1",
+        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number requests PCIe makes of the main die : Drop request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_IIO_NUM_REQ_OF_CPU.ALL.DROP",
+        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x02",
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
+        "BriefDescription": "PCI Express bandwidth writing at IIO, part 0",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x01",
-        "UMask": "0x02",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
+        "BriefDescription": "PCI Express bandwidth writing at IIO, part 1",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x02",
-        "UMask": "0x02",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
+        "BriefDescription": "PCI Express bandwidth writing at IIO, part 2",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x04",
-        "UMask": "0x02",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
+        "BriefDescription": "PCI Express bandwidth writing at IIO, part 3",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x08",
-        "UMask": "0x02",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4",
+        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x02",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5",
+        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x02",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6",
+        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x40",
-        "UMask": "0x02",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7",
+        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x80",
-        "UMask": "0x02",
+        "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
+        "BriefDescription": "Data requested of the CPU : Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x40",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU : Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x40",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU : Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x01",
-        "UMask": "0x08",
+        "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
+        "BriefDescription": "Data requested of the CPU : Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x02",
-        "UMask": "0x08",
+        "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
+        "BriefDescription": "Data requested of the CPU : Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x04",
-        "UMask": "0x08",
+        "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
+        "BriefDescription": "Data requested of the CPU : Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x08",
-        "UMask": "0x08",
+        "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART4",
+        "BriefDescription": "Data requested of the CPU : Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x08",
+        "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART5",
+        "BriefDescription": "Data requested of the CPU : Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x08",
+        "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART6",
+        "BriefDescription": "Data requested of the CPU : Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x40",
-        "UMask": "0x08",
+        "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART7",
+        "BriefDescription": "Data requested of the CPU : Messages",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x80",
-        "UMask": "0x08",
+        "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
+        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x01",
-        "UMask": "0x10",
+        "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
+        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x02",
-        "UMask": "0x10",
+        "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
+        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x04",
-        "UMask": "0x10",
+        "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
+        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x08",
-        "UMask": "0x10",
+        "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART4",
+        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x10",
+        "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART5",
+        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x10",
+        "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART6",
+        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x40",
-        "UMask": "0x10",
+        "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART7",
+        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x80",
-        "UMask": "0x10",
+        "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU0",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x100",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU1",
+        "FCMask": "0x07",
+        "PerPkg": "1",
+        "PortMask": "0x200",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x01",
-        "UMask": "0x20",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x02",
-        "UMask": "0x20",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x04",
-        "UMask": "0x20",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x08",
-        "UMask": "0x20",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART4",
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x10",
-        "UMask": "0x20",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART5",
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x20",
-        "UMask": "0x20",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART6",
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x40",
-        "UMask": "0x20",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART7",
+        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x83",
+        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x80",
-        "UMask": "0x20",
+        "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
+        "BriefDescription": "Incoming arbitration requests : Passing data to be written",
+        "EventCode": "0x86",
+        "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x40",
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests : Passing data to be written : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
+        "BriefDescription": "Incoming arbitration requests : Issuing final read or write of line",
+        "EventCode": "0x86",
+        "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x40",
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests : Issuing final read or write of line : How often different queues (e.g. channel / fc) ask to send request into pipeline",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
+        "BriefDescription": "Incoming arbitration requests : Processing response from IOMMU",
+        "EventCode": "0x86",
+        "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x40",
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests : Processing response from IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
+        "BriefDescription": "Incoming arbitration requests : Issuing to IOMMU",
+        "EventCode": "0x86",
+        "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x40",
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests : Issuing to IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART4",
+        "BriefDescription": "Incoming arbitration requests : Request Ownership",
+        "EventCode": "0x86",
+        "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x40",
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests : Request Ownership : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART5",
+        "BriefDescription": "Incoming arbitration requests : Writing line",
+        "EventCode": "0x86",
+        "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x40",
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests : Writing line : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART6",
+        "BriefDescription": "Incoming arbitration requests granted : Passing data to be written",
+        "EventCode": "0x87",
+        "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x40",
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests granted : Passing data to be written : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART7",
+        "BriefDescription": "Incoming arbitration requests granted : Issuing final read or write of line",
+        "EventCode": "0x87",
+        "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x40",
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests granted : Issuing final read or write of line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
+        "BriefDescription": "Incoming arbitration requests granted : Processing response from IOMMU",
+        "EventCode": "0x87",
+        "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x80",
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests granted : Processing response from IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
+        "BriefDescription": "Incoming arbitration requests granted : Issuing to IOMMU",
+        "EventCode": "0x87",
+        "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x80",
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests granted : Issuing to IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
+        "BriefDescription": "Incoming arbitration requests granted : Request Ownership",
+        "EventCode": "0x87",
+        "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x80",
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests granted : Request Ownership : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
+        "BriefDescription": "Incoming arbitration requests granted : Writing line",
+        "EventCode": "0x87",
+        "EventName": "UNC_IIO_INBOUND_ARB_WON.WR",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x80",
+        "PortMask": "0xFF",
+        "PublicDescription": "Incoming arbitration requests granted : Writing line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": ": IOTLB Hits to a 1G Page",
+        "EventCode": "0x40",
+        "EventName": "UNC_IIO_IOMMU0.1G_HITS",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x80",
+        "PublicDescription": ": IOTLB Hits to a 1G Page : Counts if a transaction to a 1G page, on its first lookup, hits the IOTLB.",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": ": IOTLB Hits to a 2M Page",
+        "EventCode": "0x40",
+        "EventName": "UNC_IIO_IOMMU0.2M_HITS",
+        "PerPkg": "1",
+        "PublicDescription": ": IOTLB Hits to a 2M Page : Counts if a transaction to a 2M page, on its first lookup, hits the IOTLB.",
+        "UMask": "0x8",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": ": IOTLB Hits to a 4K Page",
+        "EventCode": "0x40",
+        "EventName": "UNC_IIO_IOMMU0.4K_HITS",
+        "PerPkg": "1",
+        "PublicDescription": ": IOTLB Hits to a 4K Page : Counts if a transaction to a 4K page, on its first lookup, hits the IOTLB.",
+        "UMask": "0x4",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": ": IOTLB lookups all",
+        "EventCode": "0x40",
+        "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS",
+        "PerPkg": "1",
+        "PublicDescription": ": IOTLB lookups all : Some transactions have to look up IOTLB multiple times.  Counts every time a request looks up IOTLB.",
+        "UMask": "0x2",
+        "Unit": "IIO"
+    },
+    {
+        "BriefDescription": ": Context cache hits",
+        "EventCode": "0x40",
+        "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS",
         "PerPkg": "1",
-        "PortMask": "0x20",
+        "PublicDescription": ": Context cache hits : Counts each time a first look up of the transaction hits the RCC.",
         "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": ": Context cache lookups",
+        "EventCode": "0x40",
+        "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x80",
+        "PublicDescription": ": Context cache lookups : Counts each time a transaction looks up root context cache.",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": ": IOTLB lookups first",
+        "EventCode": "0x40",
+        "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x80",
+        "PublicDescription": ": IOTLB lookups first : Some transactions have to look up IOTLB multiple times.  Counts the first time a request looks up IOTLB.",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": ": IOTLB Fills (same as IOTLB miss)",
+        "EventCode": "0x40",
+        "EventName": "UNC_IIO_IOMMU0.MISSES",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x02",
+        "PublicDescription": ": IOTLB Fills (same as IOTLB miss) : When a transaction misses IOTLB, it does a page walk to look up memory and bring in the relevant page translation. Counts when this page translation is written to IOTLB.",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": ": Cycles PWT full",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_IOMMU1.CYC_PWT_FULL",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x02",
+        "PublicDescription": ": Cycles PWT full : Counts cycles the IOMMU has reached its maximum limit for outstanding page walks.",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": ": IOMMU memory access",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x02",
+        "PublicDescription": ": IOMMU memory access : IOMMU sends out memory fetches when it misses the cache look up which is indicated by this signal.  M2IOSF only uses low priority channel",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": ": PWC Hit to a 1G page",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x02",
+        "PublicDescription": ": PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": ": PWC Hit to a 2M page",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x02",
+        "PublicDescription": ": PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": ": PWC Hit to a 4K page",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_IOMMU1.PWC_4K_HITS",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x02",
+        "PublicDescription": ": PWC Hit to a 4K page : Counts each time a transaction's first look up hits the SLPWC at the 4K level",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": ": PWT Hit to a 256T page",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x02",
+        "PublicDescription": ": PWT Hit to a 256T page : Counts each time a transaction's first look up hits the SLPWC at the 512G level",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": ": PageWalk cache fill",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x02",
+        "PublicDescription": ": PageWalk cache fill : When a transaction misses SLPWC, it does a page walk to look up memory and bring in the relevant page translation. When this page translation is written to SLPWC, ObsPwcFillValid_nnnH is asserted.",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": ": PageWalk cache lookup",
+        "EventCode": "0x41",
+        "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x08",
+        "PublicDescription": ": PageWalk cache lookup : Counts each time a transaction looks up second level page walk cache.",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": ": Interrupt Entry cache hit",
+        "EventCode": "0x43",
+        "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x08",
+        "PublicDescription": ": Interrupt Entry cache hit : Counts each time a transaction's first look up hits the IEC.",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": ": Interrupt Entry cache lookup",
+        "EventCode": "0x43",
+        "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x08",
+        "PublicDescription": ": Interrupt Entry cache lookup : Counts the number of transaction looks up that interrupt remapping cache.",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": ": Device-selective Context cache invalidation cycles",
+        "EventCode": "0x43",
+        "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DEVICE",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x08",
+        "PublicDescription": ": Device-selective Context cache invalidation cycles : Counts number of Device selective context cache invalidation events",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": ": Domain-selective Context cache invalidation cycles",
+        "EventCode": "0x43",
+        "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DOMAIN",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x08",
+        "PublicDescription": ": Domain-selective Context cache invalidation cycles : Counts number of Domain selective context cache invalidation events",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": ": Context cache global invalidation cycles",
+        "EventCode": "0x43",
+        "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_GBL",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x08",
+        "PublicDescription": ": Context cache global invalidation cycles : Counts number of Context Cache global invalidation events",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": ": Domain-selective IOTLB invalidation cycles",
+        "EventCode": "0x43",
+        "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_DOMAIN",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x08",
+        "PublicDescription": ": Domain-selective IOTLB invalidation cycles : Counts number of Domain selective invalidation events",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": ": Global IOTLB invalidation cycles",
+        "EventCode": "0x43",
+        "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_GBL",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x08",
+        "PublicDescription": ": Global IOTLB invalidation cycles : Indicates that IOMMU is doing global invalidation.",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": ": Page-selective IOTLB invalidation cycles",
+        "EventCode": "0x43",
+        "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PAGE",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x10",
+        "PublicDescription": ": Page-selective IOTLB invalidation cycles : Counts number of Page-selective within Domain Invalidation events",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus",
+        "EventCode": "0x02",
+        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x10",
+        "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus : Asserted if all bits specified by mask match",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus",
+        "EventCode": "0x02",
+        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x10",
+        "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if all bits specified by mask match",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
+        "EventCode": "0x02",
+        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x10",
+        "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if all bits specified by mask match",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "AND Mask/match for debug bus : PCIE bus",
+        "EventCode": "0x02",
+        "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x10",
+        "PublicDescription": "AND Mask/match for debug bus : PCIE bus : Asserted if all bits specified by mask match",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
+        "EventCode": "0x02",
+        "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1",
         "PerPkg": "1",
-        "PortMask": "0x20",
+        "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if all bits specified by mask match",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART6",
-        "FCMask": "0x07",
+        "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
+        "EventCode": "0x02",
+        "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x10",
+        "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if all bits specified by mask match",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART7",
-        "FCMask": "0x07",
+        "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus",
+        "EventCode": "0x03",
+        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x10",
+        "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus : Asserted if any bits specified by mask match",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0",
-        "FCMask": "0x07",
+        "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus",
+        "EventCode": "0x03",
+        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1",
         "PerPkg": "1",
-        "PortMask": "0x01",
-        "UMask": "0x40",
+        "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if any bits specified by mask match",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1",
-        "FCMask": "0x07",
+        "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
+        "EventCode": "0x03",
+        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1",
         "PerPkg": "1",
-        "PortMask": "0x02",
-        "UMask": "0x40",
+        "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if any bits specified by mask match",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2",
-        "FCMask": "0x07",
+        "BriefDescription": "OR Mask/match for debug bus : PCIE bus",
+        "EventCode": "0x03",
+        "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1",
         "PerPkg": "1",
-        "PortMask": "0x04",
-        "UMask": "0x40",
+        "PublicDescription": "OR Mask/match for debug bus : PCIE bus : Asserted if any bits specified by mask match",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3",
-        "FCMask": "0x07",
+        "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
+        "EventCode": "0x03",
+        "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1",
         "PerPkg": "1",
-        "PortMask": "0x08",
-        "UMask": "0x40",
+        "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if any bits specified by mask match",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART4",
-        "FCMask": "0x07",
+        "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
+        "EventCode": "0x03",
+        "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1",
         "PerPkg": "1",
-        "PortMask": "0x10",
-        "UMask": "0x40",
+        "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if any bits specified by mask match",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART5",
-        "FCMask": "0x07",
+        "BriefDescription": "Counting disabled",
+        "EventCode": "0x80",
+        "EventName": "UNC_IIO_NOTHING",
         "PerPkg": "1",
-        "PortMask": "0x20",
-        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART6",
+        "BriefDescription": "Occupancy of outbound request queue : To device",
+        "EventCode": "0xC5",
+        "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x40",
-        "UMask": "0x40",
+        "PortMask": "0xFF",
+        "PublicDescription": "Occupancy of outbound request queue : To device : Counts number of outbound requests/completions IIO is currently processing",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART7",
+        "BriefDescription": ": Passing data to be written",
+        "EventCode": "0x88",
+        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x80",
-        "UMask": "0x40",
+        "PortMask": "0xFF",
+        "PublicDescription": ": Passing data to be written : Only for posted requests",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0",
+        "BriefDescription": ": Issuing final read or write of line",
+        "EventCode": "0x88",
+        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x01",
+        "PortMask": "0xFF",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1",
+        "BriefDescription": ": Processing response from IOMMU",
+        "EventCode": "0x88",
+        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x01",
+        "PortMask": "0xFF",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU0",
+        "BriefDescription": ": Issuing to IOMMU",
+        "EventCode": "0x88",
+        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x02",
+        "PortMask": "0xFF",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU1",
+        "BriefDescription": ": Request Ownership",
+        "EventCode": "0x88",
+        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x02",
+        "PortMask": "0xFF",
+        "PublicDescription": ": Request Ownership : Only for posted requests",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU0",
+        "BriefDescription": ": Writing line",
+        "EventCode": "0x88",
+        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x04",
+        "PortMask": "0xFF",
+        "PublicDescription": ": Writing line : Only for posted requests",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU1",
+        "BriefDescription": "Number requests sent to PCIe from main die : From IRP",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.IRP",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x04",
+        "PortMask": "0xFF",
+        "PublicDescription": "Number requests sent to PCIe from main die : From IRP : Captures Posted/Non-posted allocations from IRP. i.e. either non-confined P2P traffic or from the CPU",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU0",
+        "BriefDescription": "Number requests sent to PCIe from main die : From ITC",
+        "EventCode": "0xC2",
+        "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.ITC",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x08",
+        "PortMask": "0xFF",
+        "PublicDescription": "Number requests sent to PCIe from main die : From ITC : Confined P2P",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU1",
+        "BriefDescription": "Number requests sent to PCIe from main die : Completion allocations",
+        "EventCode": "0xc2",
+        "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.PREALLOC",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x08",
+        "PortMask": "0xFF",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU0",
+        "BriefDescription": "Number requests PCIe makes of the main die : Drop request",
+        "EventCode": "0x85",
+        "EventName": "UNC_IIO_NUM_REQ_OF_CPU.ALL.DROP",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x10",
+        "PortMask": "0xFF",
+        "PublicDescription": "Number requests PCIe makes of the main die : Drop request : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU. : Packet error detected, must be dropped",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU1",
+        "BriefDescription": "Number requests PCIe makes of the main die : All",
+        "EventCode": "0x85",
+        "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x10",
+        "PortMask": "0xFF",
+        "PublicDescription": "Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU.",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU0",
+        "BriefDescription": "Num requests sent by PCIe - by target : Abort",
+        "EventCode": "0x8E",
+        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x20",
+        "PortMask": "0xFF",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU1",
+        "BriefDescription": "Num requests sent by PCIe - by target : Confined P2P",
+        "EventCode": "0x8E",
+        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x20",
+        "PortMask": "0xFF",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU0",
+        "BriefDescription": "Num requests sent by PCIe - by target : Local P2P",
+        "EventCode": "0x8E",
+        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x40",
+        "PortMask": "0xFF",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU1",
+        "BriefDescription": "Num requests sent by PCIe - by target : Multi-cast",
+        "EventCode": "0x8E",
+        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x40",
+        "PortMask": "0xFF",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU0",
+        "BriefDescription": "Num requests sent by PCIe - by target : Memory",
+        "EventCode": "0x8E",
+        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x80",
+        "PortMask": "0xFF",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC0",
-        "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU1",
+        "BriefDescription": "Num requests sent by PCIe - by target : MsgB",
+        "EventCode": "0x8E",
+        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x80",
+        "PortMask": "0xFF",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU0",
+        "BriefDescription": "Num requests sent by PCIe - by target : Remote P2P",
+        "EventCode": "0x8E",
+        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x01",
+        "PortMask": "0xFF",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU1",
+        "BriefDescription": "Num requests sent by PCIe - by target : Ubox",
+        "EventCode": "0x8E",
+        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x01",
+        "PortMask": "0xFF",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU0",
-        "FCMask": "0x07",
+        "BriefDescription": "ITC address map 1",
+        "EventCode": "0x8F",
+        "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x02",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU1",
+        "BriefDescription": "Outbound cacheline requests issued : 64B requests issued to device",
+        "EventCode": "0xD0",
+        "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x02",
+        "PortMask": "0xFF",
+        "PublicDescription": "Outbound cacheline requests issued : 64B requests issued to device : Each outbound cacheline granular request may need to make multiple passes through the pipeline.  Each time a cacheline completes all its passes it advances line",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU0",
+        "BriefDescription": "Outbound TLP (transaction layer packet) requests issued : To device",
+        "EventCode": "0xD1",
+        "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x04",
+        "PortMask": "0xFF",
+        "PublicDescription": "Outbound TLP (transaction layer packet) requests issued : To device : Each time an outbound completes all its passes it advances the pointer",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU1",
-        "FCMask": "0x07",
+        "BriefDescription": "PWT occupancy",
+        "EventCode": "0x42",
+        "EventName": "UNC_IIO_PWT_OCCUPANCY",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x04",
+        "PublicDescription": "PWT occupancy : Indicates how many page walks are outstanding at any point in time.",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU0",
+        "BriefDescription": "PCIe Request - cacheline complete : Passing data to be written",
+        "EventCode": "0x91",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x08",
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request - cacheline complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU1",
+        "BriefDescription": "PCIe Request - cacheline complete : Issuing final read or write of line",
+        "EventCode": "0x91",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x08",
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request - cacheline complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU0",
+        "BriefDescription": "PCIe Request - cacheline complete : Request Ownership",
+        "EventCode": "0x91",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x10",
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request - cacheline complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU1",
+        "BriefDescription": "PCIe Request - cacheline complete : Writing line",
+        "EventCode": "0x91",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request - cacheline complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Messages",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU0",
+        "BriefDescription": "PCIe Request complete : Passing data to be written",
+        "EventCode": "0x92",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.DATA",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x40",
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : Messages",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU1",
+        "BriefDescription": "PCIe Request complete : Issuing final read or write of line",
+        "EventCode": "0x92",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x40",
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU0",
+        "BriefDescription": "PCIe Request complete : Processing response from IOMMU",
+        "EventCode": "0x92",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x80",
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request complete : Processing response from IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU1",
+        "BriefDescription": "PCIe Request complete : Issuing to IOMMU",
+        "EventCode": "0x92",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x80",
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request complete : Issuing to IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU0",
+        "BriefDescription": "PCIe Request complete : Request Ownership",
+        "EventCode": "0x92",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x01",
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU1",
+        "BriefDescription": "PCIe Request complete : Writing line",
+        "EventCode": "0x92",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.WR",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x01",
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.IOMMU0",
+        "BriefDescription": "PCIe Request - pass complete : Passing data to be written",
+        "EventCode": "0x90",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x02",
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request - pass complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU0",
+        "BriefDescription": "PCIe Request - pass complete : Issuing final read or write of line",
+        "EventCode": "0x90",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x04",
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request - pass complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU1",
+        "BriefDescription": "PCIe Request - pass complete : Request Ownership",
+        "EventCode": "0x90",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x04",
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request - pass complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU0",
+        "BriefDescription": "PCIe Request - pass complete : Writing line",
+        "EventCode": "0x90",
+        "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x08",
+        "PortMask": "0xFF",
+        "PublicDescription": "PCIe Request - pass complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast).   Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU1",
-        "FCMask": "0x07",
+        "BriefDescription": "Symbol Times on Link",
+        "EventCode": "0x82",
+        "EventName": "UNC_IIO_SYMBOL_TIMES",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x08",
+        "PublicDescription": "Symbol Times on Link : Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU0",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x100",
-        "UMask": "0x10",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x200",
-        "UMask": "0x10",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU0",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x20",
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x20",
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU0",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
         "UMask": "0x40",
         "Unit": "IIO"
     },
     {
         "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
         "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU0",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x80",
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
         "EventCode": "0xC1",
-        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x80",
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU0",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x01",
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU1",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x01",
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x40",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU0",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x100",
-        "UMask": "0x02",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU1",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x200",
-        "UMask": "0x02",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU0",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x04",
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU1",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x04",
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU0",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x08",
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU1",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x08",
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU0",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU1",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU0",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x100",
-        "UMask": "0x40",
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : Messages",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU1",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0x200",
-        "UMask": "0x40",
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU0",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU0",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x100",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
         "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU1",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU1",
         "FCMask": "0x07",
         "PerPkg": "1",
         "PortMask": "0x200",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
         "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Counting disabled",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_IIO_NOTHING",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "PWT occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_IIO_PWT_OCCUPANCY",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Symbol Times on Link",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_IIO_SYMBOL_TIMES",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "1",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "2",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "3",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "4",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "5",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "6",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x100",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "7",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x200",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "8",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "9",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART0_FREERUN",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "13",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART4_FREERUN",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "12",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART3_FREERUN",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "11",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART2_FREERUN",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "10",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART1_FREERUN",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "15",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART6_FREERUN",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "14",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART5_FREERUN",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x20",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
-        "Counter": "16",
-        "CounterType": "FREERUN",
-        "EventName": "UNC_IIO_BANDWIDTH_OUT.PART7_FREERUN",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x100",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": ": PWC Hit to a 4K page",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_IOMMU1.PWC_4K_HITS",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PortMask": "0x200",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": ": PWC Hit to a 2M page",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": ": PWC Hit to a 1G page",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": ": PWT Hit to a 256T page",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": ": PageWalk cache fill",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": ": Global IOTLB invalidation cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_GBL",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": ": Domain-selective IOTLB invalidation cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_DOMAIN",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": ": Page-selective IOTLB invalidation cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PAGE",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": ": Context cache global invalidation cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_GBL",
+        "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": ": Domain-selective Context cache invalidation cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DOMAIN",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PortMask": "0x100",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": ": Device-selective Context cache invalidation cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DEVICE",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PortMask": "0x200",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Num requests sent by PCIe - by target : MsgB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x01",
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Num requests sent by PCIe - by target : Multi-cast",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x02",
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Num requests sent by PCIe - by target : Ubox",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x04",
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Num requests sent by PCIe - by target : Memory",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x08",
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Num requests sent by PCIe - by target : Remote P2P",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x10",
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Num requests sent by PCIe - by target : Local P2P",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x20",
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Num requests sent by PCIe - by target : Confined P2P",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x40",
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Num requests sent by PCIe - by target : Abort",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT",
+        "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+        "EventCode": "0xc1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x80",
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x1",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "ITC address map 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8F",
-        "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x100",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": ": Issuing to IOMMU",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x01",
+        "PortMask": "0x200",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": ": Processing response from IOMMU",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x02",
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": ": Request Ownership",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x04",
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": ": Issuing final read or write of line",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x08",
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": ": Writing line",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x10",
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": ": Passing data to be written",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x20",
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Occupancy of outbound request queue : To device",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC5",
-        "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x08",
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Request - cacheline complete : Request Ownership",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x91",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x04",
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Request - cacheline complete : Issuing final read or write of line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x91",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x08",
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x8",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Request - cacheline complete : Writing line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x91",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.IOMMU0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x10",
+        "PortMask": "0x200",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Request - cacheline complete : Passing data to be written",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x91",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x20",
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Request complete : Issuing to IOMMU",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x01",
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Request complete : Processing response from IOMMU",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x02",
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Request complete : Request Ownership",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x04",
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Request complete : Issuing final read or write of line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x08",
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Request complete : Writing line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.WR",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x10",
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Request complete : Passing data to be written",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.DATA",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x20",
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Request - pass complete : Request Ownership",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN",
+        "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+        "EventCode": "0xC1",
+        "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x04",
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x2",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Request - pass complete : Issuing final read or write of line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR",
+        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x08",
+        "PortMask": "0x100",
+        "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Request - pass complete : Writing line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR",
+        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
+        "PortMask": "0x200",
+        "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Request - pass complete : Passing data to be written",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA",
+        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x20",
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Incoming arbitration requests : Issuing to IOMMU",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ",
+        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x01",
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Incoming arbitration requests : Processing response from IOMMU",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT",
+        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x02",
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Incoming arbitration requests : Request Ownership",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN",
+        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x04",
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Incoming arbitration requests : Issuing final read or write of line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR",
+        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x08",
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Incoming arbitration requests : Writing line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR",
+        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
         "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Incoming arbitration requests : Passing data to be written",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA",
+        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x20",
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Incoming arbitration requests granted : Issuing to IOMMU",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ",
+        "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x01",
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x10",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Incoming arbitration requests granted : Processing response from IOMMU",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT",
+        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x02",
+        "PortMask": "0x100",
+        "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Incoming arbitration requests granted : Request Ownership",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN",
+        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x04",
+        "PortMask": "0x200",
+        "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Incoming arbitration requests granted : Issuing final read or write of line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR",
+        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x08",
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Incoming arbitration requests granted : Writing line",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_IIO_INBOUND_ARB_WON.WR",
+        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x10",
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Incoming arbitration requests granted : Passing data to be written",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA",
+        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x20",
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Outbound cacheline requests issued : 64B requests issued to device",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD0",
-        "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO",
+        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x08",
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Outbound TLP (transaction layer packet) requests issued : To device",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD1",
-        "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO",
+        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x08",
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number requests sent to PCIe from main die : From IRP",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.IRP",
+        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x01",
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number requests sent to PCIe from main die : From ITC",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.ITC",
+        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x02",
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Number requests sent to PCIe from main die : Completion allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xc2",
-        "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.PREALLOC",
+        "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7",
         "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x04",
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x80",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Inserts : All Ports",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xC2",
-        "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL",
-        "FCMask": "0x04",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "PortMask": "0xFF",
-        "UMask": "0x03",
+        "PortMask": "0x100",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
-        "Counter": "2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD5",
-        "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL",
-        "FCMask": "0x04",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0xFF",
+        "PortMask": "0x200",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x4",
         "Unit": "IIO"
     },
     {
-        "BriefDescription": "Snoop Responses : Hit M",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.HIT_M",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "IRP"
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.RFO",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "IRP"
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Total Write Cache Occupancy : Any Source",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0F",
-        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "IRP"
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Total Write Cache Occupancy : Snoops",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0F",
-        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IRP"
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Coherent Ops : CLFlush",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "IRP"
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IRP"
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_I_IRP_ALL.EVICTS",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "IRP"
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1e",
-        "EventName": "UNC_I_MISC0.FAST_REQ",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "IRP"
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x4",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1E",
-        "EventName": "UNC_I_MISC0.FAST_REJ",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IRP"
+        "PortMask": "0x100",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1e",
-        "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "IRP"
+        "PortMask": "0x200",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1e",
-        "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "IRP"
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1E",
-        "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IRP"
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1E",
-        "EventName": "UNC_I_MISC0.FAST_XFER",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IRP"
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1E",
-        "EventName": "UNC_I_MISC0.PF_ACK_HINT",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "IRP"
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1E",
-        "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "IRP"
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1f",
-        "EventName": "UNC_I_MISC1.SLOW_I",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "IRP"
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1f",
-        "EventName": "UNC_I_MISC1.SLOW_S",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IRP"
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1f",
-        "EventName": "UNC_I_MISC1.SLOW_E",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "IRP"
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x1",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1f",
-        "EventName": "UNC_I_MISC1.SLOW_M",
+        "BriefDescription": "Number Transactions requested of the CPU : Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "IRP"
+        "PortMask": "0x100",
+        "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Misc Events - Set 1 : Received Invalid",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1F",
-        "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
+        "BriefDescription": "Number Transactions requested of the CPU : Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IRP"
+        "PortMask": "0x200",
+        "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Misc Events - Set 1 : Received Valid",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1F",
-        "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
+        "BriefDescription": "Number Transactions requested of the CPU : Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
         "UMask": "0x40",
-        "Unit": "IRP"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "P2P Transactions : P2P reads",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.RD",
+        "BriefDescription": "Number Transactions requested of the CPU : Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "IRP"
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "P2P Transactions : P2P Writes",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.WR",
+        "BriefDescription": "Number Transactions requested of the CPU : Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IRP"
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "P2P Transactions : P2P Message",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.MSG",
+        "BriefDescription": "Number Transactions requested of the CPU : Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "IRP"
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "P2P Transactions : P2P completions",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL",
+        "BriefDescription": "Number Transactions requested of the CPU : Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "IRP"
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "P2P Transactions : Match if remote only",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.REM",
+        "BriefDescription": "Number Transactions requested of the CPU : Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IRP"
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "P2P Transactions : match if remote and target matches",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH",
+        "BriefDescription": "Number Transactions requested of the CPU : Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IRP"
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x40",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "P2P Transactions : match if local only",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.LOC",
+        "BriefDescription": "Number Transactions requested of the CPU : Messages",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
         "UMask": "0x40",
-        "Unit": "IRP"
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "P2P Transactions : match if local and target matches",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "IRP"
+        "PortMask": "0x100",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Snoop Responses : Miss",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.MISS",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "IRP"
+        "PortMask": "0x200",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Snoop Responses : Hit I",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.HIT_I",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IRP"
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Snoop Responses : Hit E or S",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "IRP"
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Snoop Responses : SnpCode",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IRP"
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Snoop Responses : SnpData",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IRP"
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Snoop Responses : SnpInv",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.SNPINV",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "IRP"
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Inbound Transaction Count : Writes",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_I_TRANSACTIONS.WRITES",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "IRP"
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Inbound Transaction Count : Atomic",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "IRP"
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Inbound Transaction Count : Other",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_I_TRANSACTIONS.OTHER",
+        "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "IRP"
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x8",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "Inbound Transaction Count : Select Source",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "IRP"
+        "PortMask": "0x100",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "P2P Requests",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_I_P2P_INSERTS",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PortMask": "0x200",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "P2P Occupancy",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_I_P2P_OCCUPANCY",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PortMask": "0x01",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "AK Egress Allocations",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0B",
-        "EventName": "UNC_I_TxC_AK_INSERTS",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PortMask": "0x02",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL DRS Egress Cycles Full",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PortMask": "0x04",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL DRS Egress Inserts",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_I_TxC_BL_DRS_INSERTS",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PortMask": "0x08",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL DRS Egress Occupancy",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x08",
-        "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PortMask": "0x10",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL NCB Egress Cycles Full",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x06",
-        "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PortMask": "0x20",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL NCB Egress Inserts",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_I_TxC_BL_NCB_INSERTS",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PortMask": "0x40",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL NCB Egress Occupancy",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x09",
-        "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY",
+        "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+        "EventCode": "0x84",
+        "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7",
+        "FCMask": "0x07",
         "PerPkg": "1",
-        "Unit": "IRP"
+        "PortMask": "0x80",
+        "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+        "UMask": "0x2",
+        "Unit": "IIO"
     },
     {
-        "BriefDescription": "BL NCS Egress Cycles Full",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x07",
-        "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL",
+        "BriefDescription": "Total Write Cache Occupancy : Any Source",
+        "EventCode": "0x0F",
+        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
         "PerPkg": "1",
+        "PublicDescription": "Total Write Cache Occupancy : Any Source : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events. : Tracks all requests from any source port.",
+        "UMask": "0x1",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "BL NCS Egress Inserts",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_I_TxC_BL_NCS_INSERTS",
+        "BriefDescription": "Total Write Cache Occupancy : Snoops",
+        "EventCode": "0x0F",
+        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q",
         "PerPkg": "1",
+        "PublicDescription": "Total Write Cache Occupancy : Snoops : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.",
+        "UMask": "0x2",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "BL NCS Egress Occupancy",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0A",
-        "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY",
+        "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.",
+        "EventCode": "0x0f",
+        "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
         "PerPkg": "1",
+        "PublicDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.  This is effectively the sum of read occupancy and write occupancy.",
+        "UMask": "0x4",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1C",
-        "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
+        "BriefDescription": "Clockticks of the IO coherency tracker (IRP)",
+        "EventCode": "0x01",
+        "EventName": "UNC_I_CLOCKTICKS",
         "PerPkg": "1",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "No AD0 Egress Credits Stalls",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1A",
-        "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES",
+        "BriefDescription": "Coherent Ops : CLFlush",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
         "PerPkg": "1",
+        "PublicDescription": "Coherent Ops : CLFlush : Counts the number of coherency related operations servied by the IRP",
+        "UMask": "0x80",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "No AD1 Egress Credits Stalls",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1B",
-        "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES",
+        "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.PCITOM",
         "PerPkg": "1",
+        "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO.  PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.",
+        "UMask": "0x10",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "No BL Egress Credit Stalls",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1D",
-        "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES",
+        "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.RFO",
         "PerPkg": "1",
+        "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory.  RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.",
+        "UMask": "0x8",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Outbound Read Requests",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0D",
-        "EventName": "UNC_I_TxS_DATA_INSERTS_NCB",
+        "BriefDescription": "Coherent Ops : WbMtoI",
+        "EventCode": "0x10",
+        "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
         "PerPkg": "1",
+        "PublicDescription": "Coherent Ops : WbMtoI : Counts the number of coherency related operations servied by the IRP",
+        "UMask": "0x40",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Outbound Read Requests",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0E",
-        "EventName": "UNC_I_TxS_DATA_INSERTS_NCS",
+        "BriefDescription": "FAF RF full",
+        "EventCode": "0x17",
+        "EventName": "UNC_I_FAF_FULL",
         "PerPkg": "1",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Outbound Request Queue Occupancy",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0C",
-        "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY",
+        "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.",
+        "EventCode": "0x18",
+        "EventName": "UNC_I_FAF_INSERTS",
         "PerPkg": "1",
+        "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Responses to snoops of any type that miss the IIO cache",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.ALL_MISS",
+        "BriefDescription": "Occupancy of the IRP FAF queue.",
+        "EventCode": "0x19",
+        "EventName": "UNC_I_FAF_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x71",
+        "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT",
+        "BriefDescription": "FAF allocation -- sent to ADQ",
+        "EventCode": "0x16",
+        "EventName": "UNC_I_FAF_TRANSACTIONS",
         "PerPkg": "1",
-        "UMask": "0x7e",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES",
+        "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
+        "EventCode": "0x20",
+        "EventName": "UNC_I_IRP_ALL.EVICTS",
         "PerPkg": "1",
-        "UMask": "0x74",
+        "UMask": "0x4",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I",
+        "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)",
+        "EventCode": "0x20",
+        "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x72",
+        "UMask": "0x1",
         "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M to iMC Bypass : Not Taken",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x22",
-        "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.NOT_TAKEN",
+        "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
+        "EventCode": "0x20",
+        "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x2",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
+        "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
+        "EventCode": "0x1E",
+        "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "UMask": "0x10",
+        "Unit": "IRP"
     },
-    {
-        "BriefDescription": "Number of reads in which direct to core transaction was overridden",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x25",
-        "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
+    {
+        "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
+        "EventCode": "0x1e",
+        "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "UMask": "0x4",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.ALL",
+        "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
+        "EventCode": "0x1e",
+        "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
         "PerPkg": "1",
-        "UMask": "0x0704",
-        "UMaskExt": "0x07",
-        "Unit": "M2M"
+        "UMask": "0x8",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.NORMAL",
+        "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
+        "EventCode": "0x1E",
+        "EventName": "UNC_I_MISC0.FAST_REJ",
         "PerPkg": "1",
-        "UMask": "0x0701",
-        "UMaskExt": "0x07",
-        "Unit": "M2M"
+        "UMask": "0x2",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : All Writes - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.ALL",
+        "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
+        "EventCode": "0x1e",
+        "EventName": "UNC_I_MISC0.FAST_REQ",
         "PerPkg": "1",
-        "UMask": "0x1C10",
-        "UMaskExt": "0x1C",
-        "Unit": "M2M"
+        "UMask": "0x1",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.FULL",
+        "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
+        "EventCode": "0x1E",
+        "EventName": "UNC_I_MISC0.FAST_XFER",
         "PerPkg": "1",
-        "UMask": "0x1C01",
-        "UMaskExt": "0x1C",
-        "Unit": "M2M"
+        "UMask": "0x20",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.PARTIAL",
+        "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary",
+        "EventCode": "0x1E",
+        "EventName": "UNC_I_MISC0.PF_ACK_HINT",
         "PerPkg": "1",
-        "UMask": "0x1C02",
-        "UMaskExt": "0x1C",
-        "Unit": "M2M"
+        "UMask": "0x40",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "AD Ingress (from CMS) Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x01",
-        "EventName": "UNC_M2M_RxC_AD_INSERTS",
+        "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch",
+        "EventCode": "0x1E",
+        "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "UMask": "0x80",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "AD Ingress (from CMS) Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x02",
-        "EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
+        "BriefDescription": "Misc Events - Set 1 : Lost Forward",
+        "EventCode": "0x1F",
+        "EventName": "UNC_I_MISC1.LOST_FWD",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed",
+        "UMask": "0x10",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "BL Ingress (from CMS) Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x05",
-        "EventName": "UNC_M2M_RxC_BL_INSERTS",
+        "BriefDescription": "Misc Events - Set 1 : Received Invalid",
+        "EventCode": "0x1F",
+        "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Misc Events - Set 1 : Received Invalid : Secondary received a transfer that did not have sufficient MESI state",
+        "UMask": "0x20",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "BL Ingress (from CMS) Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x06",
-        "EventName": "UNC_M2M_RxC_BL_OCCUPANCY",
+        "BriefDescription": "Misc Events - Set 1 : Received Valid",
+        "EventCode": "0x1F",
+        "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Misc Events - Set 1 : Received Valid : Secondary received a transfer that did have sufficient MESI state",
+        "UMask": "0x40",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x09",
-        "EventName": "UNC_M2M_TxC_AD_INSERTS",
+        "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line",
+        "EventCode": "0x1f",
+        "EventName": "UNC_I_MISC1.SLOW_E",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Misc Events - Set 1 : Slow Transfer of E Line : Secondary received a transfer that did have sufficient MESI state",
+        "UMask": "0x4",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0A",
-        "EventName": "UNC_M2M_TxC_AD_OCCUPANCY",
+        "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line",
+        "EventCode": "0x1f",
+        "EventName": "UNC_I_MISC1.SLOW_I",
         "PerPkg": "1",
-        "Unit": "M2M"
+        "PublicDescription": "Misc Events - Set 1 : Slow Transfer of I Line : Snoop took cacheline ownership before write from data was committed.",
+        "UMask": "0x1",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Allocations : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL",
+        "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line",
+        "EventCode": "0x1f",
+        "EventName": "UNC_I_MISC1.SLOW_M",
         "PerPkg": "1",
-        "UMask": "0x03",
-        "Unit": "M2M"
+        "PublicDescription": "Misc Events - Set 1 : Slow Transfer of M Line : Snoop took cacheline ownership before write from data was committed.",
+        "UMask": "0x8",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M to iMC Bypass : Taken",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x22",
-        "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.TAKEN",
+        "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line",
+        "EventCode": "0x1f",
+        "EventName": "UNC_I_MISC1.SLOW_S",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Misc Events - Set 1 : Slow Transfer of S Line : Secondary received a transfer that did not have sufficient MESI state",
+        "UMask": "0x2",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M to iMC Bypass : Taken",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN",
+        "BriefDescription": "P2P Requests",
+        "EventCode": "0x14",
+        "EventName": "UNC_I_P2P_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "P2P Requests : P2P requests from the ITC",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M to iMC Bypass : Not Taken",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x21",
-        "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN",
+        "BriefDescription": "P2P Occupancy",
+        "EventCode": "0x15",
+        "EventName": "UNC_I_P2P_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "P2P Occupancy : P2P B & S Queue Occupancy",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL",
+        "BriefDescription": "P2P Transactions : P2P completions",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL",
         "PerPkg": "1",
-        "UMask": "0x0101",
-        "UMaskExt": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x8",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH",
+        "BriefDescription": "P2P Transactions : match if local only",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.LOC",
         "PerPkg": "1",
-        "UMask": "0x0102",
-        "UMaskExt": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x40",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.CH0_ALL",
+        "BriefDescription": "P2P Transactions : match if local and target matches",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH",
         "PerPkg": "1",
-        "UMask": "0x0104",
-        "UMaskExt": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x80",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR",
+        "BriefDescription": "P2P Transactions : P2P Message",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.MSG",
         "PerPkg": "1",
-        "UMask": "0x0140",
-        "UMaskExt": "0x01",
-        "Unit": "M2M"
+        "UMask": "0x4",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL",
+        "BriefDescription": "P2P Transactions : P2P reads",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.RD",
         "PerPkg": "1",
-        "UMask": "0x0201",
-        "UMaskExt": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x1",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH",
+        "BriefDescription": "P2P Transactions : Match if remote only",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.REM",
         "PerPkg": "1",
-        "UMask": "0x0202",
-        "UMaskExt": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x10",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.CH1_ALL",
+        "BriefDescription": "P2P Transactions : match if remote and target matches",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH",
         "PerPkg": "1",
-        "UMask": "0x0204",
-        "UMaskExt": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x20",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR",
+        "BriefDescription": "P2P Transactions : P2P Writes",
+        "EventCode": "0x13",
+        "EventName": "UNC_I_P2P_TRANSACTIONS.WR",
         "PerPkg": "1",
-        "UMask": "0x0240",
-        "UMaskExt": "0x02",
-        "Unit": "M2M"
+        "UMask": "0x2",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL",
+        "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT",
         "PerPkg": "1",
-        "UMask": "0x0401",
-        "UMaskExt": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO",
+        "UMask": "0x7e",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL",
+        "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES",
         "PerPkg": "1",
-        "UMask": "0x0402",
-        "UMaskExt": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache",
+        "UMask": "0x74",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH",
+        "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I",
         "PerPkg": "1",
-        "UMask": "0x0404",
-        "UMaskExt": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache",
+        "UMask": "0x72",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH",
+        "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M",
         "PerPkg": "1",
-        "UMask": "0x0408",
-        "UMaskExt": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache",
+        "UMask": "0x78",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL",
+        "BriefDescription": "Responses to snoops of any type that miss the IIO cache",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.ALL_MISS",
         "PerPkg": "1",
-        "UMask": "0x0410",
-        "UMaskExt": "0x04",
-        "Unit": "M2M"
+        "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that miss the IIO cache",
+        "UMask": "0x71",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR",
+        "BriefDescription": "Snoop Responses : Hit E or S",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
         "PerPkg": "1",
-        "UMaskExt": "0x05",
-        "Unit": "M2M"
+        "UMask": "0x4",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL",
+        "BriefDescription": "Snoop Responses : Hit I",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.HIT_I",
         "PerPkg": "1",
-        "UMask": "0x0801",
-        "UMaskExt": "0x08",
-        "Unit": "M2M"
+        "UMask": "0x2",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL",
+        "BriefDescription": "Snoop Responses : Hit M",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.HIT_M",
         "PerPkg": "1",
-        "UMask": "0x0802",
-        "UMaskExt": "0x08",
-        "Unit": "M2M"
+        "UMask": "0x8",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH",
+        "BriefDescription": "Snoop Responses : Miss",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.MISS",
         "PerPkg": "1",
-        "UMask": "0x0804",
-        "UMaskExt": "0x08",
-        "Unit": "M2M"
+        "UMask": "0x1",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH",
+        "BriefDescription": "Snoop Responses : SnpCode",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
         "PerPkg": "1",
-        "UMask": "0x0808",
-        "UMaskExt": "0x08",
-        "Unit": "M2M"
+        "UMask": "0x10",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL",
+        "BriefDescription": "Snoop Responses : SnpData",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
         "PerPkg": "1",
-        "UMask": "0x0810",
-        "UMaskExt": "0x08",
-        "Unit": "M2M"
+        "UMask": "0x20",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR",
+        "BriefDescription": "Snoop Responses : SnpInv",
+        "EventCode": "0x12",
+        "EventName": "UNC_I_SNOOP_RESP.SNPINV",
         "PerPkg": "1",
-        "UMaskExt": "0x09",
-        "Unit": "M2M"
+        "UMask": "0x40",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Packet Header Matches : Mesh Match",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M2M_PKT_MATCH.MESH",
+        "BriefDescription": "Inbound Transaction Count : Atomic",
+        "EventCode": "0x11",
+        "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Inbound Transaction Count : Atomic : Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of atomic transactions",
+        "UMask": "0x10",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Number Packet Header Matches : MC Match",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4C",
-        "EventName": "UNC_M2M_PKT_MATCH.MC",
+        "BriefDescription": "Inbound Transaction Count : Other",
+        "EventCode": "0x11",
+        "EventName": "UNC_I_TRANSACTIONS.OTHER",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Inbound Transaction Count : Other : Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of 'other' kinds of transactions.",
+        "UMask": "0x20",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH0",
+        "BriefDescription": "Inbound Transaction Count : Writes",
+        "EventCode": "0x11",
+        "EventName": "UNC_I_TRANSACTIONS.WRITES",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Inbound Transaction Count : Writes : Counts the number of Inbound transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Trackes only write requests.  Each write request should have a prefetch, so there is no need to explicitly track these requests.  For writes that are tickled and have to retry, the counter will be incremented for each retry.",
+        "UMask": "0x2",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x43",
-        "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH1",
+        "BriefDescription": "Inbound write (fast path) requests received by the IRP.",
+        "EventCode": "0x11",
+        "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.",
+        "UMask": "0x8",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH0",
+        "BriefDescription": "AK Egress Allocations",
+        "EventCode": "0x0B",
+        "EventName": "UNC_I_TxC_AK_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH1",
+        "BriefDescription": "BL DRS Egress Cycles Full",
+        "EventCode": "0x05",
+        "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Tracker Cycles Full : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M2M_TRACKER_FULL.CH0",
+        "BriefDescription": "BL DRS Egress Inserts",
+        "EventCode": "0x02",
+        "EventName": "UNC_I_TxC_BL_DRS_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Tracker Cycles Full : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M2M_TRACKER_FULL.CH1",
+        "BriefDescription": "BL DRS Egress Occupancy",
+        "EventCode": "0x08",
+        "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Tracker Inserts : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x49",
-        "EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
+        "BriefDescription": "BL NCB Egress Cycles Full",
+        "EventCode": "0x06",
+        "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Tracker Inserts : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x49",
-        "EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
+        "BriefDescription": "BL NCB Egress Inserts",
+        "EventCode": "0x03",
+        "EventName": "UNC_I_TxC_BL_NCB_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Tracker Cycles Not Empty : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2M_TRACKER_NE.CH0",
+        "BriefDescription": "BL NCB Egress Occupancy",
+        "EventCode": "0x09",
+        "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Tracker Cycles Not Empty : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2M_TRACKER_NE.CH1",
+        "BriefDescription": "BL NCS Egress Cycles Full",
+        "EventCode": "0x07",
+        "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Tracker Occupancy : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
+        "BriefDescription": "BL NCS Egress Inserts",
+        "EventCode": "0x04",
+        "EventName": "UNC_I_TxC_BL_NCS_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Tracker Occupancy : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
+        "BriefDescription": "BL NCS Egress Occupancy",
+        "EventCode": "0x0A",
+        "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Outbound Ring Transactions on AK : NDR Transactions",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x39",
-        "EventName": "UNC_M2M_TxC_AK.NDR",
+        "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
+        "EventCode": "0x1C",
+        "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": ": Counts the number times when it is not possible to issue a request to the M2PCIe because there are no Egress Credits available on AD0, A1 or AD0&AD1 both. Stalls on both AD0 and AD1 will count as 2",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "Outbound Ring Transactions on AK : CRD Transactions to Cbo",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x39",
-        "EventName": "UNC_M2M_TxC_AK.CRD_CBO",
+        "BriefDescription": "No AD0 Egress Credits Stalls",
+        "EventCode": "0x1A",
+        "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "No AD0 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD0 Egress Credits available.",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1D",
-        "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0",
+        "BriefDescription": "No AD1 Egress Credits Stalls",
+        "EventCode": "0x1B",
+        "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "No AD1 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD1 Egress Credits available.",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "No BL Egress Credit Stalls",
         "EventCode": "0x1D",
-        "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1",
+        "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "No BL Egress Credit Stalls : Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0",
+        "BriefDescription": "Outbound Read Requests",
+        "EventCode": "0x0D",
+        "EventName": "UNC_I_TxS_DATA_INSERTS_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2M"
+        "PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1",
+        "BriefDescription": "Outbound Read Requests",
+        "EventCode": "0x0E",
+        "EventName": "UNC_I_TxS_DATA_INSERTS_NCS",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
+        "PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0",
+        "BriefDescription": "Outbound Request Queue Occupancy",
+        "EventCode": "0x0C",
+        "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2M"
+        "PublicDescription": "Outbound Request Queue Occupancy : Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices).  This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.",
+        "Unit": "IRP"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x88",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x90",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
-        "UMask": "0xA0",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Full : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x03",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
+        "EventCode": "0x81",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
+        "EventCode": "0x81",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
+        "EventCode": "0x81",
+        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Not Empty : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x13",
-        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x03",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x03",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1F",
-        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
+        "EventCode": "0x83",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1F",
-        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
+        "EventCode": "0x83",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
+        "EventCode": "0x83",
+        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x20",
-        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Occupancy : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x12",
-        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x03",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Cache",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2M_TxC_BL.DRS_CACHE",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2M_TxC_BL.DRS_CORE",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
+        "EventCode": "0x89",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
+        "EventCode": "0x89",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
+        "EventCode": "0x89",
+        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Full : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x03",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x17",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x17",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Not Empty : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x17",
-        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x03",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
+        "EventCode": "0x8A",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1B",
-        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
+        "EventCode": "0x8B",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1B",
-        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
+        "EventCode": "0x8B",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
+        "EventCode": "0x8B",
+        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR9",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR0",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR1",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1C",
-        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "WPQ Flush : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_M2M_WPQ_FLUSH.CH0",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "WPQ Flush : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x58",
-        "EventName": "UNC_M2M_WPQ_FLUSH.CH1",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2M-&gt;iMC WPQ Cycles w/Credits - Regular : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2M-&gt;iMC WPQ Cycles w/Credits - Regular : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2M-&gt;iMC WPQ Cycles w/Credits - Regular : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4D",
-        "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN2",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
+        "EventCode": "0x85",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2M-&gt;iMC WPQ Cycles w/Credits - Special : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
+        "EventCode": "0x85",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2M-&gt;iMC WPQ Cycles w/Credits - Special : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
+        "EventCode": "0x85",
+        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2M-&gt;iMC WPQ Cycles w/Credits - Special : Channel 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4E",
-        "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN2",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Full : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M2M_WR_TRACKER_FULL.CH0",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Full : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M2M_WR_TRACKER_FULL.CH1",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Full : Mirror",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4A",
-        "EventName": "UNC_M2M_WR_TRACKER_FULL.MIRR",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Inserts : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x56",
-        "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Inserts : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x56",
-        "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M2M_WR_TRACKER_NE.CH0",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M2M_WR_TRACKER_NE.CH1",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Not Empty : Mirror",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
+        "EventCode": "0x87",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x63",
-        "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
+        "EventCode": "0x87",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x63",
-        "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
+        "EventCode": "0x87",
+        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x62",
-        "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x62",
-        "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Occupancy : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH0",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Occupancy : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH1",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Occupancy : Mirror",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Posted Inserts : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5E",
-        "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Posted Inserts : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5E",
-        "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Posted Occupancy : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+        "EventCode": "0x8C",
+        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Posted Occupancy : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5D",
-        "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
+        "EventCode": "0x8D",
+        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
+        "EventCode": "0x8D",
+        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMaskExt": "0x20",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
+        "EventCode": "0x8D",
+        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMaskExt": "0x0C",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Prefetch CAM Cycles Full : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6B",
-        "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH0",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Prefetch CAM Cycles Full : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6B",
-        "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH1",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6C",
-        "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH0",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6C",
-        "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH1",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Prefetch CAM Deallocs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA0_INVAL",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Prefetch CAM Deallocs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA1_INVAL",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Prefetch CAM Deallocs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_MISS_INVAL",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Prefetch CAM Deallocs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_RSP_PDRESET",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
+        "EventCode": "0x8E",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Prefetch CAM Deallocs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA0_INVAL",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
+        "EventCode": "0x8F",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Prefetch CAM Deallocs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA1_INVAL",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
+        "EventCode": "0x8F",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Prefetch CAM Deallocs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_MISS_INVAL",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
+        "EventCode": "0x8F",
+        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Prefetch CAM Deallocs",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6E",
-        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_RSP_PDRESET",
+        "BriefDescription": "M2M to iMC Bypass : Not Taken",
+        "EventCode": "0x22",
+        "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.NOT_TAKEN",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped : XPT - Ch 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6F",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT",
+        "BriefDescription": "M2M to iMC Bypass : Taken",
+        "EventCode": "0x22",
+        "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.TAKEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped : XPT - Ch 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6F",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT",
+        "BriefDescription": "M2M to iMC Bypass : Not Taken",
+        "EventCode": "0x21",
+        "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - Ch 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x74",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPT",
+        "BriefDescription": "M2M to iMC Bypass : Taken",
+        "EventCode": "0x21",
+        "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - Ch 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x74",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPT",
+        "BriefDescription": "Clockticks of the mesh to memory (M2M)",
+        "EventName": "UNC_M2M_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x04",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT - Ch 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x75",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPT",
+        "BriefDescription": "CMS Clockticks",
+        "EventCode": "0xc0",
+        "EventName": "UNC_M2M_CMS_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x01",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT - Ch 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x75",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPT",
+        "BriefDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled",
+        "EventCode": "0x24",
+        "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
         "PerPkg": "1",
-        "UMask": "0x04",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_SECURE_DROP",
+        "BriefDescription": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
+        "EventCode": "0x60",
+        "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
         "PerPkg": "1",
-        "UMask": "0x01",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.NOT_PF_SAD_REGION",
+        "BriefDescription": "Number of reads in which direct to core transaction was overridden",
+        "EventCode": "0x25",
+        "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
         "PerPkg": "1",
-        "UMask": "0x02",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_HIT",
+        "BriefDescription": "Distress signal asserted : DPT Local",
+        "EventCode": "0xAF",
+        "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.STOP_B2B",
+        "BriefDescription": "Distress signal asserted : DPT Remote",
+        "EventCode": "0xAF",
+        "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_NONLOCAL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.ERRORBLK_RxC",
+        "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
+        "EventCode": "0xAF",
+        "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_IV",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_AD_CRD",
+        "BriefDescription": "Distress signal asserted : DPT Stalled -  No Credit",
+        "EventCode": "0xAF",
+        "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Distress signal asserted : DPT Stalled -  No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_FULL",
+        "BriefDescription": "Distress signal asserted : Horizontal",
+        "EventCode": "0xAF",
+        "EventName": "UNC_M2M_DISTRESS_ASSERTED.HORZ",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.WPQ_PROXY",
+        "BriefDescription": "Distress signal asserted : Vertical",
+        "EventCode": "0xAF",
+        "EventName": "UNC_M2M_DISTRESS_ASSERTED.VERT",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.RPQ_PROXY",
+        "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+        "EventCode": "0xBA",
+        "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN",
         "PerPkg": "1",
-        "UMaskExt": "0x01",
+        "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x70",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.XPT_THRESH",
+        "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+        "EventCode": "0xBA",
+        "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP",
         "PerPkg": "1",
-        "UMaskExt": "0x02",
+        "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x71",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_SECURE_DROP",
+        "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
+        "EventCode": "0xB6",
+        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x71",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.NOT_PF_SAD_REGION",
+        "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
+        "EventCode": "0xB6",
+        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x71",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_HIT",
+        "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
+        "EventCode": "0xB6",
+        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x71",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.STOP_B2B",
+        "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
+        "EventCode": "0xB6",
+        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x71",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.ERRORBLK_RxC",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+        "EventCode": "0xBB",
+        "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x71",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_AD_CRD",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+        "EventCode": "0xBB",
+        "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x71",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_FULL",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+        "EventCode": "0xBB",
+        "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x71",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.WPQ_PROXY",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+        "EventCode": "0xBB",
+        "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x71",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.RPQ_PROXY",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+        "EventCode": "0xB7",
+        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMaskExt": "0x01",
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x71",
-        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.XPT_THRESH",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+        "EventCode": "0xB7",
+        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMaskExt": "0x02",
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+        "EventCode": "0xB7",
+        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+        "EventCode": "0xB7",
+        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Prefetch CAM Occupancy : Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6A",
-        "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0",
+        "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Prefetch CAM Occupancy : Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6A",
-        "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1",
+        "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": ": Channel 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x76",
-        "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0",
+        "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": ": Channel 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x76",
-        "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1",
+        "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
+        "EventCode": "0xB8",
+        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7A",
-        "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
+        "BriefDescription": "Horizontal IV Ring in Use : Left",
+        "EventCode": "0xB9",
+        "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7A",
-        "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
+        "BriefDescription": "Horizontal IV Ring in Use : Right",
+        "EventCode": "0xB9",
+        "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x7A",
-        "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
+        "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - All Channels",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x704",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR",
+        "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch0",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.CH0_ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x104",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4B",
-        "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR",
+        "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch0",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR",
+        "PerPkg": "1",
+        "UMask": "0x140",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch0",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x102",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_NONTGR",
+        "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch0",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x101",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x55",
-        "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_PWR",
+        "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch1",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.CH1_ALL",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x204",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch1",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x240",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR1",
+        "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch1",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x202",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch1",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x201",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "M2M Reads Issued to iMC : From TGR - All Channels",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.FROM_TGR",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x740",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - All Channels",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.ISOCH",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x702",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - All Channels",
+        "EventCode": "0x37",
+        "EventName": "UNC_M2M_IMC_READS.NORMAL",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x701",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "M2M Writes Issued to iMC : All Writes - All Channels",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.ALL",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x1c10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch0",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x410",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x81",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch0",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR",
         "PerPkg": "1",
-        "UMask": "0x01",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x81",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch0",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x401",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x81",
-        "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch0",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x404",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR0",
+        "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch0",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS",
         "PerPkg": "1",
-        "UMask": "0x01",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch0",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x402",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch0",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x408",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch1",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x810",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch1",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR",
         "PerPkg": "1",
-        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch1",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x801",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch1",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x804",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch1",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS",
         "PerPkg": "1",
-        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch1",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x802",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch1",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x808",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "M2M Writes Issued to iMC : From TGR - All Channels",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR",
         "PerPkg": "1",
-        "UMask": "0x04",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - All Channels",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.FULL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1c01",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR1",
+        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - All Channels",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1c04",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - All Channels",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.NI_MISS",
         "PerPkg": "1",
-        "UMask": "0x04",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - All Channels",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.PARTIAL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1c02",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - All Channels",
+        "EventCode": "0x38",
+        "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1c08",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "Write Tracker Inserts",
+        "EventCode": "0x64",
+        "EventName": "UNC_M2M_MIRR_WRQ_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "Write Tracker Occupancy",
+        "EventCode": "0x65",
+        "EventName": "UNC_M2M_MIRR_WRQ_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
+        "EventCode": "0xE6",
+        "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x89",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
+        "EventCode": "0xE6",
+        "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x89",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "Number Packet Header Matches : MC Match",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M2M_PKT_MATCH.MC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x89",
-        "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "Number Packet Header Matches : Mesh Match",
+        "EventCode": "0x4C",
+        "EventName": "UNC_M2M_PKT_MATCH.MESH",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR0",
+        "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS",
+        "EventCode": "0x73",
+        "EventName": "UNC_M2M_PREFCAM_CIS_DROPS",
         "PerPkg": "1",
-        "UMask": "0x01",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "Prefetch CAM Cycles Full : All Channels",
+        "EventCode": "0x6B",
+        "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.ALLCH",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x7",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "Prefetch CAM Cycles Full : Channel 0",
+        "EventCode": "0x6B",
+        "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "Prefetch CAM Cycles Full : Channel 1",
+        "EventCode": "0x6B",
+        "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "Prefetch CAM Cycles Not Empty : All Channels",
+        "EventCode": "0x6C",
+        "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.ALLCH",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x7",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 0",
+        "EventCode": "0x6C",
+        "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 1",
+        "EventCode": "0x6C",
+        "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8A",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "Prefetch CAM Deallocs",
+        "EventCode": "0x6E",
+        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA0_INVAL",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8B",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "Prefetch CAM Deallocs",
+        "EventCode": "0x6E",
+        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA1_INVAL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8B",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "Prefetch CAM Deallocs",
+        "EventCode": "0x6E",
+        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_MISS_INVAL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8B",
-        "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "Prefetch CAM Deallocs",
+        "EventCode": "0x6E",
+        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_RSP_PDRESET",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "Prefetch CAM Deallocs",
+        "EventCode": "0x6E",
+        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA0_INVAL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR1",
+        "BriefDescription": "Prefetch CAM Deallocs",
+        "EventCode": "0x6E",
+        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA1_INVAL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "Prefetch CAM Deallocs",
+        "EventCode": "0x6E",
+        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_MISS_INVAL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "Prefetch CAM Deallocs",
+        "EventCode": "0x6E",
+        "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_RSP_PDRESET",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "Data Prefetches Dropped : XPT - Ch 0",
+        "EventCode": "0x6F",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "Data Prefetches Dropped : XPT - Ch 1",
+        "EventCode": "0x6F",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "Data Prefetches Dropped : XPT - All Channels",
+        "EventCode": "0x6f",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x15",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - Ch 0",
+        "EventCode": "0x74",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPT",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 0",
+        "EventCode": "0x74",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPTUPI",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 0",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - Ch 1",
+        "EventCode": "0x74",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPT",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 1",
+        "EventCode": "0x74",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPTUPI",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 1",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR0",
+        "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 2",
+        "EventCode": "0x74",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH2_XPTUPI",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 2",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- All Channels",
+        "EventCode": "0x74",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPTUPI_ALLCH",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - All Channels",
+        "UMask": "0x15",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - All Channels",
+        "EventCode": "0x74",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPT_ALLCH",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x15",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT - Ch 0",
+        "EventCode": "0x75",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPT",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 0",
+        "EventCode": "0x75",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPTUPI",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 0",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT - Ch 1",
+        "EventCode": "0x75",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPT",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 1",
+        "EventCode": "0x75",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPTUPI",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 1",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 2",
+        "EventCode": "0x75",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH2_XPTUPI",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - All Channels",
+        "EventCode": "0x75",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPTUPI_ALLCH",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x15",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT - All Channels",
+        "EventCode": "0x75",
+        "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPT_ALLCH",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x15",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+        "EventCode": "0x70",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.ERRORBLK_RxC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+        "EventCode": "0x70",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.NOT_PF_SAD_REGION",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR1",
+        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+        "EventCode": "0x70",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+        "EventCode": "0x70",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_FULL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+        "EventCode": "0x70",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_HIT",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+        "EventCode": "0x70",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_SECURE_DROP",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+        "EventCode": "0x70",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.RPQ_PROXY",
         "PerPkg": "1",
-        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+        "EventCode": "0x70",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.STOP_B2B",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8C",
-        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+        "EventCode": "0x70",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.WPQ_PROXY",
         "PerPkg": "1",
         "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8D",
-        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+        "EventCode": "0x70",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.XPT_THRESH",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+        "EventCode": "0x71",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.ERRORBLK_RxC",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8D",
-        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+        "EventCode": "0x71",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.NOT_PF_SAD_REGION",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8D",
-        "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+        "EventCode": "0x71",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR0",
+        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+        "EventCode": "0x71",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_FULL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+        "EventCode": "0x71",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_HIT",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+        "EventCode": "0x71",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_SECURE_DROP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+        "EventCode": "0x71",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.RPQ_PROXY",
         "PerPkg": "1",
-        "UMask": "0x08",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+        "EventCode": "0x71",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.STOP_B2B",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+        "EventCode": "0x71",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.WPQ_PROXY",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+        "EventCode": "0x71",
+        "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.XPT_THRESH",
         "PerPkg": "1",
-        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8E",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0",
+        "EventCode": "0x6D",
+        "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8F",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1",
+        "EventCode": "0x6D",
+        "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8F",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels",
+        "EventCode": "0x6D",
+        "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x15",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8F",
-        "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "Prefetch CAM Occupancy : All Channels",
+        "EventCode": "0x6A",
+        "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x7",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Distress signal asserted : Vertical",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_M2M_DISTRESS_ASSERTED.VERT",
+        "BriefDescription": "Prefetch CAM Occupancy : Channel 0",
+        "EventCode": "0x6A",
+        "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Distress signal asserted : Horizontal",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_M2M_DISTRESS_ASSERTED.HORZ",
+        "BriefDescription": "Prefetch CAM Occupancy : Channel 1",
+        "EventCode": "0x6A",
+        "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Local",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_LOCAL",
+        "BriefDescription": ": All Channels",
+        "EventCode": "0x76",
+        "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x7",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Remote",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_NONLOCAL",
+        "BriefDescription": ": Channel 0",
+        "EventCode": "0x76",
+        "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_IV",
+        "BriefDescription": ": Channel 1",
+        "EventCode": "0x76",
+        "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Stalled -  No Credit",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAF",
-        "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
+        "BriefDescription": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
+        "EventCode": "0x79",
+        "EventName": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
         "PerPkg": "1",
-        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBA",
-        "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP",
+        "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
+        "EventCode": "0x7A",
+        "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBA",
-        "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN",
+        "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
+        "EventCode": "0x7A",
+        "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB6",
-        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+        "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
+        "EventCode": "0x7A",
+        "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB6",
-        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD",
+        "BriefDescription": "UNC_M2M_PREFCAM_RxC_INSERTS",
+        "EventCode": "0x78",
+        "EventName": "UNC_M2M_PREFCAM_RxC_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x02",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB6",
-        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
+        "EventCode": "0x77",
+        "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x04",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB6",
-        "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
+        "EventCode": "0xAC",
+        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBB",
-        "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
+        "EventCode": "0xAC",
+        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBB",
-        "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_ODD",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
+        "EventCode": "0xAC",
+        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBB",
-        "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
+        "EventCode": "0xAC",
+        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xBB",
-        "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB7",
-        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB7",
-        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M2M_RING_BOUNCES_VERT.AKC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB7",
-        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB7",
-        "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
+        "EventCode": "0xAA",
+        "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
+        "EventCode": "0xAD",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
+        "EventCode": "0xAD",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
+        "EventCode": "0xAD",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB8",
-        "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
+        "EventCode": "0xAD",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use : Left",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB9",
-        "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
+        "EventCode": "0xAD",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use : Right",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB9",
-        "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT",
+        "BriefDescription": "Sink Starvation on Vertical Ring : AD",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE6",
-        "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST0",
+        "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE6",
-        "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST1",
+        "BriefDescription": "Sink Starvation on Vertical Ring",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AKC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAC",
-        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD",
+        "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAC",
-        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK",
+        "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
+        "EventCode": "0xAB",
+        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAC",
-        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL",
+        "BriefDescription": "Source Throttle",
+        "EventCode": "0xae",
+        "EventName": "UNC_M2M_RING_SRC_THRTL",
         "PerPkg": "1",
-        "UMask": "0x04",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAC",
-        "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV",
+        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 0",
+        "EventCode": "0x43",
+        "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAA",
-        "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD",
+        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 1",
+        "EventCode": "0x43",
+        "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAA",
-        "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK",
+        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 0",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAA",
-        "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL",
+        "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 1",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAA",
-        "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV",
+        "BriefDescription": "AD Ingress (from CMS) Full",
+        "EventCode": "0x04",
+        "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL",
         "PerPkg": "1",
-        "UMask": "0x08",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAA",
-        "EventName": "UNC_M2M_RING_BOUNCES_VERT.AKC",
+        "BriefDescription": "AD Ingress (from CMS) Not Empty",
+        "EventCode": "0x03",
+        "EventName": "UNC_M2M_RxC_AD_CYCLES_NE",
         "PerPkg": "1",
-        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAD",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD",
+        "BriefDescription": "AD Ingress (from CMS) Allocations",
+        "EventCode": "0x01",
+        "EventName": "UNC_M2M_RxC_AD_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x01",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAD",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK",
+        "BriefDescription": "AD Ingress (from CMS) Occupancy",
+        "EventCode": "0x02",
+        "EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x02",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAD",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL",
+        "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches",
+        "EventCode": "0x77",
+        "EventName": "UNC_M2M_RxC_AD_PREF_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x04",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAD",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV",
+        "BriefDescription": "AK Egress (to CMS) Allocations",
+        "EventCode": "0x5C",
+        "EventName": "UNC_M2M_RxC_AK_WR_CMP",
         "PerPkg": "1",
-        "UMask": "0x08",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAD",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1",
+        "BriefDescription": "BL Ingress (from CMS) Full",
+        "EventCode": "0x08",
+        "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL",
         "PerPkg": "1",
-        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD",
+        "BriefDescription": "BL Ingress (from CMS) Not Empty",
+        "EventCode": "0x07",
+        "EventName": "UNC_M2M_RxC_BL_CYCLES_NE",
         "PerPkg": "1",
-        "UMask": "0x01",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK",
+        "BriefDescription": "BL Ingress (from CMS) Allocations",
+        "EventCode": "0x05",
+        "EventName": "UNC_M2M_RxC_BL_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x02",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL",
+        "BriefDescription": "BL Ingress (from CMS) Occupancy",
+        "EventCode": "0x06",
+        "EventName": "UNC_M2M_RxC_BL_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x04",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV",
+        "BriefDescription": "Transgress Injection Starvation : AD - All",
+        "EventCode": "0xE5",
+        "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xAB",
-        "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AKC",
+        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+        "EventCode": "0xE5",
+        "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
         "UMask": "0x10",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xE5",
         "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Injection Starvation : BL - All",
         "EventCode": "0xE5",
-        "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_UNCRD",
+        "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
         "EventCode": "0xE5",
-        "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD",
+        "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
         "EventCode": "0xE5",
-        "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD",
+        "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_ALL",
+        "BriefDescription": "Transgress Ingress Bypass : AD - All",
+        "EventCode": "0xE2",
+        "EventName": "UNC_M2M_RxR_BYPASS.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE5",
-        "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_ALL",
+        "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
+        "EventCode": "0xE2",
+        "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xE2",
         "EventName": "UNC_M2M_RxR_BYPASS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Transgress Ingress Bypass : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xE2",
         "EventName": "UNC_M2M_RxR_BYPASS.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
         "EventCode": "0xE2",
-        "EventName": "UNC_M2M_RxR_BYPASS.BL_UNCRD",
+        "EventName": "UNC_M2M_RxR_BYPASS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Bypass : BL - All",
         "EventCode": "0xE2",
-        "EventName": "UNC_M2M_RxR_BYPASS.IV",
+        "EventName": "UNC_M2M_RxR_BYPASS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
         "EventCode": "0xE2",
-        "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD",
+        "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
         "EventCode": "0xE2",
-        "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD",
+        "EventName": "UNC_M2M_RxR_BYPASS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Bypass : IV",
         "EventCode": "0xE2",
-        "EventName": "UNC_M2M_RxR_BYPASS.AKC_UNCRD",
+        "EventName": "UNC_M2M_RxR_BYPASS.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_M2M_RxR_BYPASS.AD_ALL",
+        "BriefDescription": "Transgress Injection Starvation : AD - All",
+        "EventCode": "0xE3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE2",
-        "EventName": "UNC_M2M_RxR_BYPASS.BL_ALL",
+        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+        "EventCode": "0xE3",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xE3",
         "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Transgress Injection Starvation : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xE3",
         "EventName": "UNC_M2M_RxR_CRD_STARVED.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Injection Starvation : BL - All",
         "EventCode": "0xE3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_UNCRD",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
         "EventCode": "0xE3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.IV",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
         "EventCode": "0xE3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
         "EventCode": "0xE3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Injection Starvation : IV",
         "EventCode": "0xE3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_ALL",
+        "BriefDescription": "Transgress Injection Starvation",
+        "EventCode": "0xe4",
+        "EventName": "UNC_M2M_RxR_CRD_STARVED_1",
+        "PerPkg": "1",
+        "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Transgress Ingress Allocations : AD - All",
+        "EventCode": "0xE1",
+        "EventName": "UNC_M2M_RxR_INSERTS.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE3",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_ALL",
+        "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
+        "EventCode": "0xE1",
+        "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xE1",
         "EventName": "UNC_M2M_RxR_INSERTS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Transgress Ingress Allocations : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xE1",
         "EventName": "UNC_M2M_RxR_INSERTS.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
         "EventCode": "0xE1",
-        "EventName": "UNC_M2M_RxR_INSERTS.BL_UNCRD",
+        "EventName": "UNC_M2M_RxR_INSERTS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Allocations : BL - All",
         "EventCode": "0xE1",
-        "EventName": "UNC_M2M_RxR_INSERTS.IV",
+        "EventName": "UNC_M2M_RxR_INSERTS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
         "EventCode": "0xE1",
-        "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD",
+        "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
         "EventCode": "0xE1",
-        "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD",
+        "EventName": "UNC_M2M_RxR_INSERTS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Allocations : IV",
         "EventCode": "0xE1",
-        "EventName": "UNC_M2M_RxR_INSERTS.AKC_UNCRD",
+        "EventName": "UNC_M2M_RxR_INSERTS.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_M2M_RxR_INSERTS.AD_ALL",
+        "BriefDescription": "Transgress Ingress Occupancy : AD - All",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE1",
-        "EventName": "UNC_M2M_RxR_INSERTS.BL_ALL",
+        "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
+        "EventCode": "0xE0",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xE0",
         "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Transgress Ingress Occupancy : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xE0",
         "EventName": "UNC_M2M_RxR_OCCUPANCY.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_UNCRD",
-        "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
         "EventCode": "0xE0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.IV",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Occupancy : BL - All",
         "EventCode": "0xE0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xE0",
         "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
         "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xE0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.AKC_UNCRD",
-        "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M2M"
-    },
-    {
-        "BriefDescription": "Transgress Ingress Occupancy : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
         "EventCode": "0xE0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_ALL",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Occupancy : IV",
         "EventCode": "0xE0",
-        "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_ALL",
+        "EventName": "UNC_M2M_RxR_OCCUPANCY.IV",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xD0",
         "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xD0",
         "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xD0",
         "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xD0",
         "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xD0",
         "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x10",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xD0",
         "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x20",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xD0",
         "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x40",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xD0",
         "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x80",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xD2",
         "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xD2",
         "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xD2",
         "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xD2",
         "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xD2",
         "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x10",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xD2",
         "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x20",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xD2",
         "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x40",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xD2",
         "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x80",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xD4",
         "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xD4",
         "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xD4",
         "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xD4",
         "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xD4",
         "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x10",
         "Unit": "M2M"
     },
     {
         "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xD4",
         "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x40",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
+        "EventCode": "0xD4",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x80",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x10",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x40",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
+        "EventCode": "0xD6",
+        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x80",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
+        "EventCode": "0xD1",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
+        "EventCode": "0xD1",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
+        "EventCode": "0xD1",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
+        "EventCode": "0xD3",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
+        "EventCode": "0xD3",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
+        "EventCode": "0xD3",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
+        "EventCode": "0xD5",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
+        "EventCode": "0xD5",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
+        "EventCode": "0xD5",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
+        "EventCode": "0xD7",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
+        "EventCode": "0xD7",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
+        "EventCode": "0xD7",
+        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Number AD Ingress Credits",
+        "EventCode": "0x41",
+        "EventName": "UNC_M2M_TGR_AD_CREDITS",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Number BL Ingress Credits",
+        "EventCode": "0x42",
+        "EventName": "UNC_M2M_TGR_BL_CREDITS",
+        "PerPkg": "1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Tracker Cycles Full : Channel 0",
+        "EventCode": "0x45",
+        "EventName": "UNC_M2M_TRACKER_FULL.CH0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Tracker Cycles Full : Channel 1",
+        "EventCode": "0x45",
+        "EventName": "UNC_M2M_TRACKER_FULL.CH1",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Tracker Inserts : Channel 0",
+        "EventCode": "0x49",
+        "EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "Tracker Inserts : Channel 1",
+        "EventCode": "0x49",
+        "EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
+        "PerPkg": "1",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
+        "BriefDescription": "Tracker Cycles Not Empty : Channel 0",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2M_TRACKER_NE.CH0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD4",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+        "BriefDescription": "Tracker Cycles Not Empty : Channel 1",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2M_TRACKER_NE.CH1",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+        "BriefDescription": "Tracker Occupancy : Channel 0",
+        "EventCode": "0x47",
+        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+        "BriefDescription": "Tracker Occupancy : Channel 1",
+        "EventCode": "0x47",
+        "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+        "BriefDescription": "AD Egress (to CMS) Credit Acquired",
+        "EventCode": "0x0d",
+        "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED",
         "PerPkg": "1",
-        "UMask": "0x04",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+        "BriefDescription": "AD Egress (to CMS) Credits Occupancy",
+        "EventCode": "0x0e",
+        "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x08",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+        "BriefDescription": "AD Egress (to CMS) Full",
+        "EventCode": "0x0c",
+        "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL",
         "PerPkg": "1",
-        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+        "BriefDescription": "AD Egress (to CMS) Not Empty",
+        "EventCode": "0x0b",
+        "EventName": "UNC_M2M_TxC_AD_CYCLES_NE",
         "PerPkg": "1",
-        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+        "BriefDescription": "AD Egress (to CMS) Allocations",
+        "EventCode": "0x09",
+        "EventName": "UNC_M2M_TxC_AD_INSERTS",
         "PerPkg": "1",
-        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD6",
-        "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+        "BriefDescription": "Cycles with No AD Egress (to CMS) Credits",
+        "EventCode": "0x0f",
+        "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD1",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+        "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits",
+        "EventCode": "0x10",
+        "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED",
         "PerPkg": "1",
-        "UMask": "0x01",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD1",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+        "BriefDescription": "AD Egress (to CMS) Occupancy",
+        "EventCode": "0x0A",
+        "EventName": "UNC_M2M_TxC_AD_OCCUPANCY",
         "PerPkg": "1",
-        "UMask": "0x02",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD1",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+        "BriefDescription": "Outbound Ring Transactions on AK : CRD Transactions to Cbo",
+        "EventCode": "0x39",
+        "EventName": "UNC_M2M_TxC_AK.CRD_CBO",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD3",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+        "BriefDescription": "Outbound Ring Transactions on AK : NDR Transactions",
+        "EventCode": "0x39",
+        "EventName": "UNC_M2M_TxC_AK.NDR",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD3",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+        "BriefDescription": "AKC Credits",
+        "EventCode": "0x5F",
+        "EventName": "UNC_M2M_TxC_AKC_CREDITS",
         "PerPkg": "1",
-        "UMask": "0x02",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD3",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+        "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD5",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+        "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
+        "EventCode": "0x1D",
+        "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD5",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+        "BriefDescription": "AK Egress (to CMS) Full : All",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x3",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD5",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+        "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Near Side",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD7",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+        "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Far Side",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD7",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+        "BriefDescription": "AK Egress (to CMS) Full",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xD7",
-        "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+        "BriefDescription": "AK Egress (to CMS) Full",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x88",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_UNCRD",
+        "BriefDescription": "AK Egress (to CMS) Full",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_UNCRD",
+        "BriefDescription": "AK Egress (to CMS) Full",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0xa0",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD",
+        "BriefDescription": "AK Egress (to CMS) Full",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0",
         "PerPkg": "1",
         "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD",
+        "BriefDescription": "AK Egress (to CMS) Full",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x90",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_ALL",
+        "BriefDescription": "AK Egress (to CMS) Not Empty : All",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0x3",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA6",
-        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_ALL",
+        "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_UNCRD",
+        "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK",
+        "BriefDescription": "AK Egress (to CMS) Not Empty",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_UNCRD",
+        "BriefDescription": "AK Egress (to CMS) Not Empty",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV",
+        "BriefDescription": "AK Egress (to CMS) Not Empty",
+        "EventCode": "0x13",
+        "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD",
+        "BriefDescription": "AK Egress (to CMS) Allocations : All",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x3",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD",
+        "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AKC_UNCRD",
+        "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_ALL",
+        "BriefDescription": "AK Egress (to CMS) Allocations",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA7",
-        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_ALL",
+        "BriefDescription": "AK Egress (to CMS) Allocations",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
+        "BriefDescription": "AK Egress (to CMS) Allocations",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP",
+        "PerPkg": "1",
+        "UMask": "0x20",
+        "Unit": "M2M"
+    },
+    {
+        "BriefDescription": "AK Egress (to CMS) Allocations",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK",
+        "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+        "EventCode": "0x1F",
+        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
+        "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+        "EventCode": "0x1F",
+        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV",
+        "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+        "EventCode": "0x20",
+        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD",
+        "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+        "EventCode": "0x20",
+        "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD",
+        "BriefDescription": "AK Egress (to CMS) Occupancy : All",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x3",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
+        "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Near Side",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_ALL",
+        "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Far Side",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA2",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_ALL",
+        "BriefDescription": "AK Egress (to CMS) Occupancy",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_UNCRD",
+        "BriefDescription": "AK Egress (to CMS) Occupancy",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK",
+        "BriefDescription": "AK Egress (to CMS) Occupancy",
+        "EventCode": "0x12",
+        "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_UNCRD",
+        "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Cache",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2M_TxC_BL.DRS_CACHE",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV",
+        "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Core",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2M_TxC_BL.DRS_CORE",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD",
+        "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD",
+        "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
+        "BriefDescription": "BL Egress (to CMS) Full : All",
+        "EventCode": "0x18",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x3",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_ALL",
+        "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Near Side",
+        "EventCode": "0x18",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA3",
-        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_ALL",
+        "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Far Side",
+        "EventCode": "0x18",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_UNCRD",
+        "BriefDescription": "BL Egress (to CMS) Not Empty : All",
+        "EventCode": "0x17",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x3",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK",
+        "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
+        "EventCode": "0x17",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_UNCRD",
+        "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
+        "EventCode": "0x17",
+        "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV",
+        "BriefDescription": "BL Egress (to CMS) Allocations : All",
+        "EventCode": "0x15",
+        "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x3",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD",
+        "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
+        "EventCode": "0x15",
+        "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD",
+        "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
+        "EventCode": "0x15",
+        "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AKC_UNCRD",
+        "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+        "EventCode": "0x1B",
+        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_ALL",
+        "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+        "EventCode": "0x1B",
+        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA1",
-        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_ALL",
+        "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_UNCRD",
+        "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+        "EventCode": "0x1C",
+        "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.AK",
+        "BriefDescription": "CMS Horizontal ADS Used : AD - All",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_UNCRD",
+        "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.IV",
+        "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD",
+        "BriefDescription": "CMS Horizontal ADS Used : BL - All",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD",
+        "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
         "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.AKC_UNCRD",
+        "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
+        "EventCode": "0xA6",
+        "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_ALL",
+        "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA4",
-        "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_ALL",
+        "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_UNCRD",
+        "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK",
+        "BriefDescription": "CMS Horizontal Bypass Used : AK",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_UNCRD",
+        "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV",
+        "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD",
+        "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD",
+        "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
+        "BriefDescription": "CMS Horizontal Bypass Used : IV",
+        "EventCode": "0xA7",
+        "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_ALL",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA0",
-        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_ALL",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_UNCRD",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_UNCRD",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AKC_UNCRD",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_ALL",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xA5",
-        "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_ALL",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
+        "EventCode": "0xA2",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9C",
-        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV_AG1",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
+        "EventCode": "0xA3",
+        "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9D",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG0",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9E",
-        "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG1",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AK",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG0",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG0",
+        "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG0",
+        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.IV_AG0",
+        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG1",
+        "BriefDescription": "CMS Horizontal Egress Inserts : IV",
+        "EventCode": "0xA1",
+        "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG1",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x94",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG1",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x95",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG0",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x95",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG1",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AK",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG0",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG0",
+        "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG0",
+        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.IV_AG0",
+        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG1",
+        "BriefDescription": "CMS Horizontal Egress NACKs : IV",
+        "EventCode": "0xA4",
+        "EventName": "UNC_M2M_TxR_HORZ_NACK.IV",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG1",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x96",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG1",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x97",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG0",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x97",
-        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG1",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG0",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG0",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG0",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.IV_AG0",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG1",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
+        "EventCode": "0xA0",
+        "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG1",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x92",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG1",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x93",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG0",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x93",
-        "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG1",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M2M_TxR_HORZ_STARVED.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x80",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG0",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG0",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG0",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
+        "EventCode": "0xA5",
+        "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK0.IV_AG0",
+        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG1",
+        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
         "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG1",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG1",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+        "EventCode": "0x9C",
+        "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
         "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x99",
-        "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG0",
+        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x99",
-        "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG1",
+        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG0",
+        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG0",
+        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG0",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.IV_AG0",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG1",
+        "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
+        "EventCode": "0x9D",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV_AG1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG1",
+        "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x90",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG1",
+        "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
+        "EventCode": "0x9E",
+        "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x91",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG0",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x91",
-        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG1",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG0",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG0",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG0",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED0.IV_AG0",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG1",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
+        "EventCode": "0x94",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG1",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
+        "EventCode": "0x95",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9A",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG1",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
+        "EventCode": "0x95",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9B",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG0",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9B",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG1",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x9B",
-        "EventName": "UNC_M2M_TxR_VERT_STARVED1.TGC",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB0",
-        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
+        "EventCode": "0x96",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_EVEN",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
+        "EventCode": "0x97",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_ODD",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
+        "EventCode": "0x97",
+        "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_EVEN",
+        "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB4",
-        "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_ODD",
+        "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN",
+        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD",
+        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN",
+        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB1",
-        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD",
+        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN",
+        "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
+        "EventCode": "0x92",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD",
+        "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
+        "EventCode": "0x93",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN",
+        "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
+        "EventCode": "0x93",
+        "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB2",
-        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD",
+        "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical IV Ring in Use : Up",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP",
+        "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical IV Ring in Use : Down",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB3",
-        "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN",
+        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB5",
-        "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_EVEN",
+        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB5",
-        "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_ODD",
+        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB5",
-        "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_EVEN",
+        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xB5",
-        "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_ODD",
+        "BriefDescription": "CMS Vertical Egress NACKs : IV",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2M_TxR_VERT_NACK0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x60",
-        "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
+        "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
+        "EventCode": "0x99",
+        "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG0",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Inserts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x64",
-        "EventName": "UNC_M2M_MIRR_WRQ_INSERTS",
+        "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
+        "EventCode": "0x99",
+        "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Write Tracker Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x65",
-        "EventName": "UNC_M2M_MIRR_WRQ_OCCUPANCY",
+        "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG0",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x73",
-        "EventName": "UNC_M2M_PREFCAM_CIS_DROPS",
+        "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x79",
-        "EventName": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
+        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG0",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_M2M_PREFCAM_RxC_INSERTS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x78",
-        "EventName": "UNC_M2M_PREFCAM_RxC_INSERTS",
+        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x77",
-        "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
+        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG0",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Source Throttle",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xae",
-        "EventName": "UNC_M2M_RING_SRC_THRTL",
+        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AD Ingress (from CMS) Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x04",
-        "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL",
+        "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
+        "EventCode": "0x90",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.IV_AG0",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AD Ingress (from CMS) Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x03",
-        "EventName": "UNC_M2M_RxC_AD_CYCLES_NE",
+        "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
+        "EventCode": "0x91",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG0",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AK Egress (to CMS) Allocations",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5C",
-        "EventName": "UNC_M2M_RxC_AK_WR_CMP",
+        "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
+        "EventCode": "0x91",
+        "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Ingress (from CMS) Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x08",
-        "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG0",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "BL Ingress (from CMS) Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x07",
-        "EventName": "UNC_M2M_RxC_BL_CYCLES_NE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x10",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe4",
-        "EventName": "UNC_M2M_RxR_CRD_STARVED_1",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG0",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number AD Ingress Credits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_M2M_TGR_AD_CREDITS",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x20",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Number BL Ingress Credits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_M2M_TGR_BL_CREDITS",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG0",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Credit Acquired",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0d",
-        "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x40",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Credits Occupancy",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0e",
-        "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
+        "EventCode": "0x9A",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED0.IV_AG0",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0c",
-        "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG0",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AD Egress (to CMS) Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0b",
-        "EventName": "UNC_M2M_TxC_AD_CYCLES_NE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles with No AD Egress (to CMS) Credits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0f",
-        "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+        "EventCode": "0x9B",
+        "EventName": "UNC_M2M_TxR_VERT_STARVED1.TGC",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED",
+        "BriefDescription": "Vertical AD Ring In Use : Down and Even",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AKC Credits",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x5F",
-        "EventName": "UNC_M2M_TxC_AKC_CREDITS",
+        "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.ISOCH",
+        "BriefDescription": "Vertical AD Ring In Use : Up and Even",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x0702",
-        "UMaskExt": "0x07",
+        "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2M Reads Issued to iMC : From TGR - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x37",
-        "EventName": "UNC_M2M_IMC_READS.FROM_TGR",
+        "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
+        "EventCode": "0xB0",
+        "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x0740",
-        "UMaskExt": "0x07",
+        "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH",
+        "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x1C04",
-        "UMaskExt": "0x1C",
+        "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH",
+        "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x1C08",
-        "UMaskExt": "0x1C",
+        "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : From TGR - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR",
+        "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMaskExt": "0x1D",
+        "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x38",
-        "EventName": "UNC_M2M_IMC_WRITES.NI_MISS",
+        "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
+        "EventCode": "0xB4",
+        "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMaskExt": "0x1C",
+        "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Prefetch CAM Cycles Full : All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6B",
-        "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.ALLCH",
+        "BriefDescription": "Vertical AK Ring In Use : Down and Even",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x07",
+        "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Prefetch CAM Cycles Not Empty : All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6C",
-        "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.ALLCH",
+        "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x07",
+        "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Data Prefetches Dropped : XPT - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6f",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH",
+        "BriefDescription": "Vertical AK Ring In Use : Up and Even",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x15",
+        "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x75",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPT_ALLCH",
+        "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
+        "EventCode": "0xB1",
+        "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x15",
+        "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Prefetch CAM Occupancy : All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6A",
-        "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH",
+        "BriefDescription": "Vertical BL Ring in Use : Down and Even",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x07",
+        "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": ": All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x76",
-        "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH",
+        "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x07",
+        "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x74",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPT_ALLCH",
+        "BriefDescription": "Vertical BL Ring in Use : Up and Even",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x15",
+        "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x6D",
-        "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH",
+        "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
+        "EventCode": "0xB2",
+        "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x15",
+        "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x77",
-        "EventName": "UNC_M2M_RxC_AD_PREF_OCCUPANCY",
+        "BriefDescription": "Vertical IV Ring in Use : Down",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN",
         "PerPkg": "1",
+        "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x74",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPTUPI",
+        "BriefDescription": "Vertical IV Ring in Use : Up",
+        "EventCode": "0xB3",
+        "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x75",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPTUPI_ALLCH",
+        "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
+        "EventCode": "0xB5",
+        "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x15",
+        "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x75",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH2_XPTUPI",
+        "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
+        "EventCode": "0xB5",
+        "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x75",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPTUPI",
+        "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
+        "EventCode": "0xB5",
+        "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x75",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPTUPI",
+        "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
+        "EventCode": "0xB5",
+        "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- All Channels",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x74",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPTUPI_ALLCH",
+        "BriefDescription": "WPQ Flush : Channel 0",
+        "EventCode": "0x58",
+        "EventName": "UNC_M2M_WPQ_FLUSH.CH0",
         "PerPkg": "1",
-        "UMask": "0x15",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x74",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH2_XPTUPI",
+        "BriefDescription": "WPQ Flush : Channel 1",
+        "EventCode": "0x58",
+        "EventName": "UNC_M2M_WPQ_FLUSH.CH1",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x74",
-        "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPTUPI",
+        "BriefDescription": "M2M-&gt;iMC WPQ Cycles w/Credits - Regular : Channel 0",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0",
+        "BriefDescription": "M2M-&gt;iMC WPQ Cycles w/Credits - Regular : Channel 1",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1",
+        "BriefDescription": "M2M-&gt;iMC WPQ Cycles w/Credits - Regular : Channel 2",
+        "EventCode": "0x4D",
+        "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN2",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0",
+        "BriefDescription": "M2M-&gt;iMC WPQ Cycles w/Credits - Special : Channel 0",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1",
+        "BriefDescription": "M2M-&gt;iMC WPQ Cycles w/Credits - Special : Channel 1",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0",
+        "BriefDescription": "M2M-&gt;iMC WPQ Cycles w/Credits - Special : Channel 2",
+        "EventCode": "0x4E",
+        "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN2",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "UMask": "0x4",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x33",
-        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1",
+        "BriefDescription": "Write Tracker Cycles Full : Channel 0",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M2M_WR_TRACKER_FULL.CH0",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS",
+        "BriefDescription": "Write Tracker Cycles Full : Channel 1",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M2M_WR_TRACKER_FULL.CH1",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB",
+        "BriefDescription": "Write Tracker Cycles Full : Mirror",
+        "EventCode": "0x4A",
+        "EventName": "UNC_M2M_WR_TRACKER_FULL.MIRR",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x34",
-        "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS",
+        "BriefDescription": "Write Tracker Inserts : Channel 0",
+        "EventCode": "0x56",
+        "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x32",
-        "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0",
+        "BriefDescription": "Write Tracker Inserts : Channel 1",
+        "EventCode": "0x56",
+        "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x32",
-        "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1",
+        "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M2M_WR_TRACKER_NE.CH0",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x32",
-        "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0",
+        "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M2M_WR_TRACKER_NE.CH1",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x32",
-        "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1",
+        "BriefDescription": "Write Tracker Cycles Not Empty : Mirror",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "M2PCIe"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x32",
-        "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0",
+        "BriefDescription": "Write Tracker Cycles Not Empty",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR",
         "PerPkg": "1",
         "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x32",
-        "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1",
+        "BriefDescription": "Write Tracker Cycles Not Empty",
+        "EventCode": "0x4B",
+        "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR",
         "PerPkg": "1",
         "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB",
+        "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0",
+        "EventCode": "0x63",
+        "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS",
+        "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1",
+        "EventCode": "0x63",
+        "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2PCIe"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL",
+        "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 0",
+        "EventCode": "0x62",
+        "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M2PCIe"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Inserts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB",
+        "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 1",
+        "EventCode": "0x62",
+        "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Inserts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS",
+        "BriefDescription": "Write Tracker Occupancy : Channel 0",
+        "EventCode": "0x55",
+        "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH0",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2PCIe"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Inserts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2P_RxC_INSERTS.ALL",
+        "BriefDescription": "Write Tracker Occupancy : Channel 1",
+        "EventCode": "0x55",
+        "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH1",
         "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M2PCIe"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x25",
-        "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_0",
+        "BriefDescription": "Write Tracker Occupancy : Mirror",
+        "EventCode": "0x55",
+        "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "UMask": "0x8",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x25",
-        "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_0",
+        "BriefDescription": "Write Tracker Occupancy",
+        "EventCode": "0x55",
+        "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_NONTGR",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
+        "UMask": "0x10",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x25",
-        "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_0",
+        "BriefDescription": "Write Tracker Occupancy",
+        "EventCode": "0x55",
+        "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_PWR",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
+        "UMask": "0x20",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x25",
-        "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_1",
+        "BriefDescription": "Write Tracker Posted Inserts : Channel 0",
+        "EventCode": "0x5E",
+        "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0",
         "PerPkg": "1",
-        "UMask": "0x10",
-        "Unit": "M2PCIe"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x25",
-        "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_1",
+        "BriefDescription": "Write Tracker Posted Inserts : Channel 1",
+        "EventCode": "0x5E",
+        "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1",
         "PerPkg": "1",
-        "UMask": "0x20",
-        "Unit": "M2PCIe"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Full",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x25",
-        "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_1",
+        "BriefDescription": "Write Tracker Posted Occupancy : Channel 0",
+        "EventCode": "0x5D",
+        "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0",
         "PerPkg": "1",
-        "UMask": "0x40",
-        "Unit": "M2PCIe"
+        "UMask": "0x1",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_0",
+        "BriefDescription": "Write Tracker Posted Occupancy : Channel 1",
+        "EventCode": "0x5D",
+        "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
+        "UMask": "0x2",
+        "Unit": "M2M"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_0",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_0",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_1",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_1",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x23",
-        "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_1",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Egress (to CMS) Ingress",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_M2P_TxC_INSERTS.AD_0",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Egress (to CMS) Ingress",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_M2P_TxC_INSERTS.BL_0",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Egress (to CMS) Ingress",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_0",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
+        "EventCode": "0x80",
+        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Egress (to CMS) Ingress",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_M2P_TxC_INSERTS.AD_1",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
+        "EventCode": "0x81",
+        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Egress (to CMS) Ingress",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_M2P_TxC_INSERTS.BL_1",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
+        "EventCode": "0x81",
+        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Egress (to CMS) Ingress",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x24",
-        "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_1",
+        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
+        "EventCode": "0x81",
+        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x46",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
+        "EventCode": "0x82",
+        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
         "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
+        "EventCode": "0x83",
+        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
+        "EventCode": "0x83",
+        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
+        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
+        "EventCode": "0x83",
+        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x47",
-        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
+        "EventCode": "0x88",
+        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x19",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
+        "EventCode": "0x89",
+        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1a",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
+        "EventCode": "0x89",
+        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1a",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS",
+        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
+        "EventCode": "0x89",
+        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1a",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
+        "EventCode": "0x8a",
+        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x1a",
-        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
+        "EventCode": "0x8a",
+        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local P2P Shared Credits Returned : Agent0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x17",
-        "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
+        "EventCode": "0x8a",
+        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local P2P Shared Credits Returned : Agent1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x17",
-        "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
+        "EventCode": "0x8a",
+        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local P2P Shared Credits Returned : Agent2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x17",
-        "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
+        "EventCode": "0x8a",
+        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
+        "EventCode": "0x8a",
+        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
+        "EventCode": "0x8a",
+        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
+        "EventCode": "0x8a",
+        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
+        "EventCode": "0x8b",
+        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
+        "EventCode": "0x8b",
+        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5",
+        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
+        "EventCode": "0x8b",
+        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x40",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
+        "EventCode": "0x84",
+        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
         "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
-    },
-    {
-        "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
+        "EventCode": "0x85",
+        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
+        "EventCode": "0x85",
+        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x41",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
+        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
+        "EventCode": "0x85",
+        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4a",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4a",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4a",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4a",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4a",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
         "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4a",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
         "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4a",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
         "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4a",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
+        "EventCode": "0x86",
+        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
         "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4b",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
-    },
-    {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4b",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
+        "EventCode": "0x87",
+        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4b",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
+        "EventCode": "0x87",
+        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4b",
-        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS",
+        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
+        "EventCode": "0x87",
+        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "P2P Credit Occupancy : Local NCB",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
+        "EventCode": "0x8c",
+        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "P2P Credit Occupancy : Local NCS",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
+        "EventCode": "0x8c",
+        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "P2P Credit Occupancy : Remote NCB",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
+        "EventCode": "0x8c",
+        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "P2P Credit Occupancy : Remote NCS",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
+        "EventCode": "0x8c",
+        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "P2P Credit Occupancy : All",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x14",
-        "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+        "EventCode": "0x8c",
+        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
         "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Dedicated Credits Received : Local NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x16",
-        "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+        "EventCode": "0x8c",
+        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Dedicated Credits Received : Local NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x16",
-        "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+        "EventCode": "0x8c",
+        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Dedicated Credits Received : Remote NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x16",
-        "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+        "EventCode": "0x8c",
+        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Dedicated Credits Received : Remote NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x16",
-        "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
+        "EventCode": "0x8d",
+        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Dedicated Credits Received : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x16",
-        "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
+        "EventCode": "0x8d",
+        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Shared Credits  Received : Local NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB",
+        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
+        "EventCode": "0x8d",
+        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Shared Credits  Received : Local NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
+        "EventCode": "0x8e",
+        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Shared Credits  Received : Remote NCB",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
+        "EventCode": "0x8e",
+        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Shared Credits  Received : Remote NCS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
+        "EventCode": "0x8e",
+        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Shared Credits  Received : All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x15",
-        "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
+        "EventCode": "0x8e",
+        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Remote P2P Shared Credits Returned : Agent0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
+        "EventCode": "0x8e",
+        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR4",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Remote P2P Shared Credits Returned : Agent1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
+        "EventCode": "0x8e",
+        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR5",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Remote P2P Shared Credits Returned : Agent2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x18",
-        "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
+        "EventCode": "0x8e",
+        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR6",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
+        "EventCode": "0x8e",
+        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR7",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
+        "EventCode": "0x8f",
+        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR10",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
+        "EventCode": "0x8f",
+        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR8",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI",
+        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
+        "EventCode": "0x8f",
+        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR9",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB",
+        "BriefDescription": "Clockticks of the mesh to PCI (M2P)",
+        "EventCode": "0x01",
+        "EventName": "UNC_M2P_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x02",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x10",
-        "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS",
+        "BriefDescription": "CMS Clockticks",
+        "EventCode": "0xc0",
+        "EventName": "UNC_M2P_CMS_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x04",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Inserts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI",
+        "BriefDescription": "Distress signal asserted : DPT Local",
+        "EventCode": "0xaf",
+        "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_LOCAL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Inserts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB",
+        "BriefDescription": "Distress signal asserted : DPT Remote",
+        "EventCode": "0xaf",
+        "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_NONLOCAL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Ingress (from CMS) Queue Inserts",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x11",
-        "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS",
+        "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
+        "EventCode": "0xaf",
+        "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_IV",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x2d",
-        "EventName": "UNC_M2P_TxC_CREDITS.PRQ",
+        "BriefDescription": "Distress signal asserted : DPT Stalled -  No Credit",
+        "EventCode": "0xaf",
+        "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Distress signal asserted : DPT Stalled -  No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "Distress signal asserted : Horizontal",
+        "EventCode": "0xaf",
+        "EventName": "UNC_M2P_DISTRESS_ASSERTED.HORZ",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR1",
+        "BriefDescription": "Distress signal asserted : Vertical",
+        "EventCode": "0xaf",
+        "EventName": "UNC_M2P_DISTRESS_ASSERTED.VERT",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+        "EventCode": "0xba",
+        "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+        "EventCode": "0xba",
+        "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
+        "EventCode": "0xb6",
+        "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
+        "EventCode": "0xb6",
+        "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
+        "EventCode": "0xb6",
+        "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
+        "EventCode": "0xb6",
+        "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x81",
-        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+        "EventCode": "0xbb",
+        "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x81",
-        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+        "EventCode": "0xbb",
+        "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x81",
-        "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+        "EventCode": "0xbb",
+        "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR0",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+        "EventCode": "0xbb",
+        "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+        "EventCode": "0xb7",
+        "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+        "EventCode": "0xb7",
+        "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+        "EventCode": "0xb7",
+        "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+        "EventCode": "0xb7",
+        "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
+        "EventCode": "0xb8",
+        "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
+        "EventCode": "0xb8",
+        "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_ODD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x82",
-        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
+        "EventCode": "0xb8",
+        "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
+        "EventCode": "0xb8",
+        "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_ODD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "Horizontal IV Ring in Use : Left",
+        "EventCode": "0xb9",
+        "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.LEFT",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x83",
-        "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "Horizontal IV Ring in Use : Right",
+        "EventCode": "0xb9",
+        "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.RIGHT",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
+        "EventCode": "0x33",
+        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR1",
+        "BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
+        "EventCode": "0x33",
+        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
+        "EventCode": "0x33",
+        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
+        "EventCode": "0x33",
+        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
+        "EventCode": "0x33",
+        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0",
         "PerPkg": "1",
+        "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.",
         "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
+        "EventCode": "0x33",
+        "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1",
         "PerPkg": "1",
+        "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.",
         "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS",
+        "EventCode": "0x34",
+        "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the DRS message class.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x88",
-        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB",
+        "EventCode": "0x34",
+        "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCB message class.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x89",
-        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS",
+        "EventCode": "0x34",
+        "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCS message class.",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x89",
-        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0",
+        "EventCode": "0x32",
+        "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x89",
-        "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1",
+        "EventCode": "0x32",
+        "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1",
+        "PerPkg": "1",
+        "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0",
+        "EventCode": "0x32",
+        "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8a",
-        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR0",
+        "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1",
+        "EventCode": "0x32",
+        "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8a",
-        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0",
+        "EventCode": "0x32",
+        "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8a",
-        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1",
+        "EventCode": "0x32",
+        "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use.  Transactions from the BL ring going into the IIO Agent must first acquire a credit.  These credits are for either the NCB or NCS message classes.  NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common).  NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8a",
-        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCB",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8a",
-        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCS",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8a",
-        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCB",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8a",
-        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCS",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8a",
-        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCB",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8b",
-        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCS",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8b",
-        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCB",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8b",
-        "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCS",
+        "EventCode": "0x46",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCB",
+        "EventCode": "0x47",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR1",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCS",
+        "EventCode": "0x47",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCB",
+        "EventCode": "0x47",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCS",
+        "EventCode": "0x47",
+        "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCB",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCS",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCB",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x84",
-        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCS",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCB",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCS",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x85",
-        "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR0",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS",
+        "EventCode": "0x19",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCB",
+        "EventCode": "0x1a",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCS",
+        "EventCode": "0x1a",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCB",
+        "EventCode": "0x1a",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCS",
+        "EventCode": "0x1a",
+        "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "Local P2P Shared Credits Returned : Agent0",
+        "EventCode": "0x17",
+        "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "Local P2P Shared Credits Returned : Agent1",
+        "EventCode": "0x17",
+        "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x86",
-        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "Local P2P Shared Credits Returned : Agent2",
+        "EventCode": "0x17",
+        "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent0",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent1",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x87",
-        "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent2",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8c",
-        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR0",
+        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent3",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8c",
-        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR1",
+        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent4",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8c",
-        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR2",
+        "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent5",
+        "EventCode": "0x44",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8c",
-        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR3",
+        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCB",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8c",
-        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR4",
+        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCS",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8c",
-        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR5",
+        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCB",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8c",
-        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR6",
+        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCS",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8c",
-        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR7",
+        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCB",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8d",
-        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR8",
+        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCS",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8d",
-        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR9",
+        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCB",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8d",
-        "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR10",
+        "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCS",
+        "EventCode": "0x40",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8e",
-        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR0",
+        "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCB",
+        "EventCode": "0x41",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8e",
-        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR1",
+        "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCS",
+        "EventCode": "0x41",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8e",
-        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR2",
+        "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCB",
+        "EventCode": "0x41",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8e",
-        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR3",
+        "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCS",
+        "EventCode": "0x41",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8e",
-        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR4",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCB",
+        "EventCode": "0x4a",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8e",
-        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR5",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCS",
+        "EventCode": "0x4a",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8e",
-        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR6",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCB",
+        "EventCode": "0x4a",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8e",
-        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR7",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCS",
+        "EventCode": "0x4a",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8f",
-        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR8",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCB",
+        "EventCode": "0x4a",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8f",
-        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR9",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCS",
+        "EventCode": "0x4a",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x8f",
-        "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR10",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCB",
+        "EventCode": "0x4a",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Distress signal asserted : Vertical",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xaf",
-        "EventName": "UNC_M2P_DISTRESS_ASSERTED.VERT",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCS",
+        "EventCode": "0x4a",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Distress signal asserted : Horizontal",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xaf",
-        "EventName": "UNC_M2P_DISTRESS_ASSERTED.HORZ",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCB",
+        "EventCode": "0x4b",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Local",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xaf",
-        "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_LOCAL",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCS",
+        "EventCode": "0x4b",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Remote",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xaf",
-        "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_NONLOCAL",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCB",
+        "EventCode": "0x4b",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xaf",
-        "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_IV",
+        "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCS",
+        "EventCode": "0x4b",
+        "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Distress signal asserted : DPT Stalled -  No Credit",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xaf",
-        "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
+        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
+        "EventCode": "0xe6",
+        "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST0",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xba",
-        "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP",
+        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
+        "EventCode": "0xe6",
+        "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xba",
-        "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN",
+        "BriefDescription": "P2P Credit Occupancy : All",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb6",
-        "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+        "BriefDescription": "P2P Credit Occupancy : Local NCB",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb6",
-        "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_ODD",
+        "BriefDescription": "P2P Credit Occupancy : Local NCS",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb6",
-        "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "P2P Credit Occupancy : Remote NCB",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb6",
-        "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+        "BriefDescription": "P2P Credit Occupancy : Remote NCS",
+        "EventCode": "0x14",
+        "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xbb",
-        "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Dedicated Credits Received : All",
+        "EventCode": "0x16",
+        "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xbb",
-        "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_ODD",
+        "BriefDescription": "Dedicated Credits Received : Local NCB",
+        "EventCode": "0x16",
+        "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xbb",
-        "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Dedicated Credits Received : Local NCS",
+        "EventCode": "0x16",
+        "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xbb",
-        "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Dedicated Credits Received : Remote NCB",
+        "EventCode": "0x16",
+        "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb7",
-        "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Dedicated Credits Received : Remote NCS",
+        "EventCode": "0x16",
+        "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb7",
-        "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_ODD",
+        "BriefDescription": "Shared Credits  Received : All",
+        "EventCode": "0x15",
+        "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb7",
-        "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Shared Credits  Received : Local NCB",
+        "EventCode": "0x15",
+        "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb7",
-        "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Shared Credits  Received : Local NCS",
+        "EventCode": "0x15",
+        "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb8",
-        "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+        "BriefDescription": "Shared Credits  Received : Remote NCB",
+        "EventCode": "0x15",
+        "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb8",
-        "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_ODD",
+        "BriefDescription": "Shared Credits  Received : Remote NCS",
+        "EventCode": "0x15",
+        "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb8",
-        "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+        "BriefDescription": "Remote P2P Shared Credits Returned : Agent0",
+        "EventCode": "0x18",
+        "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb8",
-        "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+        "BriefDescription": "Remote P2P Shared Credits Returned : Agent1",
+        "EventCode": "0x18",
+        "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use : Left",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb9",
-        "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.LEFT",
+        "BriefDescription": "Remote P2P Shared Credits Returned : Agent2",
+        "EventCode": "0x18",
+        "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Horizontal IV Ring in Use : Right",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb9",
-        "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.RIGHT",
+        "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent0",
+        "EventCode": "0x45",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe6",
-        "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST0",
+        "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent1",
+        "EventCode": "0x45",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe6",
-        "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST1",
+        "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent2",
+        "EventCode": "0x45",
+        "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xac",
         "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xac",
         "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xac",
         "EventName": "UNC_M2P_RING_BOUNCES_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xac",
         "EventName": "UNC_M2P_RING_BOUNCES_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xaa",
         "EventName": "UNC_M2P_RING_BOUNCES_VERT.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xaa",
         "EventName": "UNC_M2P_RING_BOUNCES_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Messages that bounced on the Vertical Ring.",
         "EventCode": "0xaa",
-        "EventName": "UNC_M2P_RING_BOUNCES_VERT.BL",
+        "EventName": "UNC_M2P_RING_BOUNCES_VERT.AKC",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
         "EventCode": "0xaa",
-        "EventName": "UNC_M2P_RING_BOUNCES_VERT.IV",
+        "EventName": "UNC_M2P_RING_BOUNCES_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Messages that bounced on the Vertical Ring",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
         "EventCode": "0xaa",
-        "EventName": "UNC_M2P_RING_BOUNCES_VERT.AKC",
+        "EventName": "UNC_M2P_RING_BOUNCES_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xad",
         "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xad",
         "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
         "EventCode": "0xad",
-        "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.BL",
+        "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
         "EventCode": "0xad",
-        "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.IV",
+        "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.BL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
         "EventCode": "0xad",
-        "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK_AG1",
+        "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.IV",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Sink Starvation on Vertical Ring : AD",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xab",
         "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xab",
         "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Sink Starvation on Vertical Ring",
+        "EventCode": "0xab",
+        "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AKC",
+        "PerPkg": "1",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xab",
         "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.BL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
         "EventCode": "0xab",
         "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.IV",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Sink Starvation on Vertical Ring",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xab",
-        "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AKC",
+        "BriefDescription": "Source Throttle",
+        "EventCode": "0xae",
+        "EventName": "UNC_M2P_RING_SRC_THRTL",
         "PerPkg": "1",
-        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe5",
-        "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_UNCRD",
+        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+        "EventCode": "0x10",
+        "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+        "EventCode": "0x10",
+        "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI",
+        "PerPkg": "1",
+        "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+        "EventCode": "0x10",
+        "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB",
+        "PerPkg": "1",
+        "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+        "EventCode": "0x10",
+        "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS",
+        "PerPkg": "1",
+        "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+        "EventCode": "0x10",
+        "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB",
+        "PerPkg": "1",
+        "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+        "UMask": "0x20",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+        "EventCode": "0x10",
+        "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS",
+        "PerPkg": "1",
+        "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+        "UMask": "0x40",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Ingress (from CMS) Queue Inserts",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2P_RxC_INSERTS.ALL",
+        "PerPkg": "1",
+        "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+        "UMask": "0x80",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Ingress (from CMS) Queue Inserts",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI",
+        "PerPkg": "1",
+        "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Ingress (from CMS) Queue Inserts",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB",
+        "PerPkg": "1",
+        "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Ingress (from CMS) Queue Inserts",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS",
+        "PerPkg": "1",
+        "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Ingress (from CMS) Queue Inserts",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB",
+        "PerPkg": "1",
+        "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+        "UMask": "0x20",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Ingress (from CMS) Queue Inserts",
+        "EventCode": "0x11",
+        "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS",
+        "PerPkg": "1",
+        "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+        "UMask": "0x40",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Transgress Injection Starvation : AD - All",
         "EventCode": "0xe5",
-        "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_UNCRD",
+        "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Transgress Injection Starvation : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xe5",
         "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
         "UMask": "0x10",
         "Unit": "M2PCIe"
     },
+    {
+        "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+        "EventCode": "0xe5",
+        "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_UNCRD",
+        "PerPkg": "1",
+        "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Transgress Injection Starvation : BL - All",
+        "EventCode": "0xe5",
+        "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_ALL",
+        "PerPkg": "1",
+        "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+        "UMask": "0x44",
+        "Unit": "M2PCIe"
+    },
     {
         "BriefDescription": "Transgress Injection Starvation : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xe5",
         "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
         "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
         "EventCode": "0xe5",
-        "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_ALL",
+        "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_UNCRD",
+        "PerPkg": "1",
+        "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Transgress Ingress Bypass : AD - All",
+        "EventCode": "0xe2",
+        "EventName": "UNC_M2P_RxR_BYPASS.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe5",
-        "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_ALL",
+        "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
+        "EventCode": "0xe2",
+        "EventName": "UNC_M2P_RxR_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xe2",
         "EventName": "UNC_M2P_RxR_BYPASS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Transgress Ingress Bypass : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xe2",
         "EventName": "UNC_M2P_RxR_BYPASS.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
         "EventCode": "0xe2",
-        "EventName": "UNC_M2P_RxR_BYPASS.BL_UNCRD",
+        "EventName": "UNC_M2P_RxR_BYPASS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Bypass : BL - All",
         "EventCode": "0xe2",
-        "EventName": "UNC_M2P_RxR_BYPASS.IV",
+        "EventName": "UNC_M2P_RxR_BYPASS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
         "EventCode": "0xe2",
-        "EventName": "UNC_M2P_RxR_BYPASS.AD_CRD",
+        "EventName": "UNC_M2P_RxR_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
         "EventCode": "0xe2",
-        "EventName": "UNC_M2P_RxR_BYPASS.BL_CRD",
+        "EventName": "UNC_M2P_RxR_BYPASS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Bypass : IV",
         "EventCode": "0xe2",
-        "EventName": "UNC_M2P_RxR_BYPASS.AKC_UNCRD",
+        "EventName": "UNC_M2P_RxR_BYPASS.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe2",
-        "EventName": "UNC_M2P_RxR_BYPASS.AD_ALL",
+        "BriefDescription": "Transgress Injection Starvation : AD - All",
+        "EventCode": "0xe3",
+        "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Bypass : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe2",
-        "EventName": "UNC_M2P_RxR_BYPASS.BL_ALL",
+        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+        "EventCode": "0xe3",
+        "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xe3",
         "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Transgress Injection Starvation : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xe3",
         "EventName": "UNC_M2P_RxR_CRD_STARVED.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
-    },
-    {
-        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe3",
-        "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_UNCRD",
-        "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Injection Starvation : BL - All",
         "EventCode": "0xe3",
-        "EventName": "UNC_M2P_RxR_CRD_STARVED.IV",
+        "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
         "EventCode": "0xe3",
-        "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_CRD",
+        "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
         "EventCode": "0xe3",
-        "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_CRD",
+        "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xe3",
         "EventName": "UNC_M2P_RxR_CRD_STARVED.IFV",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
         "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Injection Starvation : IV",
         "EventCode": "0xe3",
-        "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_ALL",
+        "EventName": "UNC_M2P_RxR_CRD_STARVED.IV",
+        "PerPkg": "1",
+        "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Transgress Injection Starvation",
+        "EventCode": "0xe4",
+        "EventName": "UNC_M2P_RxR_CRD_STARVED_1",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Transgress Ingress Allocations : AD - All",
+        "EventCode": "0xe1",
+        "EventName": "UNC_M2P_RxR_INSERTS.AD_ALL",
+        "PerPkg": "1",
+        "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe3",
-        "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_ALL",
+        "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
+        "EventCode": "0xe1",
+        "EventName": "UNC_M2P_RxR_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xe1",
         "EventName": "UNC_M2P_RxR_INSERTS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Transgress Ingress Allocations : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xe1",
         "EventName": "UNC_M2P_RxR_INSERTS.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
         "EventCode": "0xe1",
-        "EventName": "UNC_M2P_RxR_INSERTS.BL_UNCRD",
+        "EventName": "UNC_M2P_RxR_INSERTS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Allocations : BL - All",
         "EventCode": "0xe1",
-        "EventName": "UNC_M2P_RxR_INSERTS.IV",
+        "EventName": "UNC_M2P_RxR_INSERTS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
         "EventCode": "0xe1",
-        "EventName": "UNC_M2P_RxR_INSERTS.AD_CRD",
+        "EventName": "UNC_M2P_RxR_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
         "EventCode": "0xe1",
-        "EventName": "UNC_M2P_RxR_INSERTS.BL_CRD",
+        "EventName": "UNC_M2P_RxR_INSERTS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Allocations : IV",
         "EventCode": "0xe1",
-        "EventName": "UNC_M2P_RxR_INSERTS.AKC_UNCRD",
+        "EventName": "UNC_M2P_RxR_INSERTS.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe1",
-        "EventName": "UNC_M2P_RxR_INSERTS.AD_ALL",
+        "BriefDescription": "Transgress Ingress Occupancy : AD - All",
+        "EventCode": "0xe0",
+        "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Allocations : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe1",
-        "EventName": "UNC_M2P_RxR_INSERTS.BL_ALL",
+        "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
+        "EventCode": "0xe0",
+        "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xe0",
         "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Transgress Ingress Occupancy : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xe0",
         "EventName": "UNC_M2P_RxR_OCCUPANCY.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
-    },
-    {
-        "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe0",
-        "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_UNCRD",
-        "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
         "EventCode": "0xe0",
-        "EventName": "UNC_M2P_RxR_OCCUPANCY.IV",
+        "EventName": "UNC_M2P_RxR_OCCUPANCY.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Occupancy : BL - All",
         "EventCode": "0xe0",
-        "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_CRD",
+        "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xe0",
         "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
         "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe0",
-        "EventName": "UNC_M2P_RxR_OCCUPANCY.AKC_UNCRD",
-        "PerPkg": "1",
-        "UMask": "0x80",
-        "Unit": "M2PCIe"
-    },
-    {
-        "BriefDescription": "Transgress Ingress Occupancy : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
         "EventCode": "0xe0",
-        "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_ALL",
+        "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Ingress Occupancy : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Transgress Ingress Occupancy : IV",
         "EventCode": "0xe0",
-        "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_ALL",
+        "EventName": "UNC_M2P_RxR_OCCUPANCY.IV",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd0",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd0",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd0",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd0",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd0",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd0",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd0",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd0",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd2",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd2",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd2",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd2",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd2",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd2",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd2",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd2",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd4",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd4",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd4",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd4",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd4",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd4",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd4",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd4",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd6",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd6",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd6",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd6",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd6",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd6",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd6",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd6",
         "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
         "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
         "UMask": "0x80",
         "Unit": "M2PCIe"
     },
+    {
+        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
+        "EventCode": "0xd1",
+        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
+    },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd1",
         "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xd1",
         "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
+        "EventCode": "0xd3",
+        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
+        "EventCode": "0xd3",
+        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
+        "EventCode": "0xd3",
+        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
+        "EventCode": "0xd5",
+        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
+        "EventCode": "0xd5",
+        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
+        "EventCode": "0xd5",
+        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
+        "EventCode": "0xd7",
+        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
+        "EventCode": "0xd7",
+        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
+        "EventCode": "0xd7",
+        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+        "PerPkg": "1",
+        "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ",
+        "EventCode": "0x2d",
+        "EventName": "UNC_M2P_TxC_CREDITS.PRQ",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Egress (to CMS) Cycles Full",
+        "EventCode": "0x25",
+        "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_0",
+        "PerPkg": "1",
+        "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Egress (to CMS) Cycles Full",
+        "EventCode": "0x25",
+        "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_1",
+        "PerPkg": "1",
+        "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+        "UMask": "0x10",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Egress (to CMS) Cycles Full",
+        "EventCode": "0x25",
+        "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_0",
+        "PerPkg": "1",
+        "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Egress (to CMS) Cycles Full",
+        "EventCode": "0x25",
+        "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_1",
+        "PerPkg": "1",
+        "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+        "UMask": "0x20",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Egress (to CMS) Cycles Full",
+        "EventCode": "0x25",
+        "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_0",
+        "PerPkg": "1",
+        "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Egress (to CMS) Cycles Full",
+        "EventCode": "0x25",
+        "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_1",
+        "PerPkg": "1",
+        "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+        "UMask": "0x40",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+        "EventCode": "0x23",
+        "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_0",
+        "PerPkg": "1",
+        "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple egress buffers can be tracked at a given time using multiple counters.",
+        "UMask": "0x1",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+        "EventCode": "0x23",
+        "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_1",
+        "PerPkg": "1",
+        "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple egress buffers can be tracked at a given time using multiple counters.",
+        "UMask": "0x10",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+        "EventCode": "0x23",
+        "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_0",
+        "PerPkg": "1",
+        "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple egress buffers can be tracked at a given time using multiple counters.",
+        "UMask": "0x2",
+        "Unit": "M2PCIe"
+    },
+    {
+        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+        "EventCode": "0x23",
+        "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_1",
+        "PerPkg": "1",
+        "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple egress buffers can be tracked at a given time using multiple counters.",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd1",
-        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+        "EventCode": "0x23",
+        "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple egress buffers can be tracked at a given time using multiple counters.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd3",
-        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+        "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+        "EventCode": "0x23",
+        "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple egress buffers can be tracked at a given time using multiple counters.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd3",
-        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+        "BriefDescription": "Egress (to CMS) Ingress",
+        "EventCode": "0x24",
+        "EventName": "UNC_M2P_TxC_INSERTS.AD_0",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the  the M2PCIe Egress queue.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd3",
-        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+        "BriefDescription": "Egress (to CMS) Ingress",
+        "EventCode": "0x24",
+        "EventName": "UNC_M2P_TxC_INSERTS.AD_1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the  the M2PCIe Egress queue.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+        "BriefDescription": "Egress (to CMS) Ingress",
+        "EventCode": "0x24",
+        "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the  the M2PCIe Egress queue.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+        "BriefDescription": "Egress (to CMS) Ingress",
+        "EventCode": "0x24",
+        "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the  the M2PCIe Egress queue.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd5",
-        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+        "BriefDescription": "Egress (to CMS) Ingress",
+        "EventCode": "0x24",
+        "EventName": "UNC_M2P_TxC_INSERTS.BL_0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the  the M2PCIe Egress queue.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd7",
-        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+        "BriefDescription": "Egress (to CMS) Ingress",
+        "EventCode": "0x24",
+        "EventName": "UNC_M2P_TxC_INSERTS.BL_1",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the  the M2PCIe Egress queue.  This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.  This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd7",
-        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+        "BriefDescription": "CMS Horizontal ADS Used : AD - All",
+        "EventCode": "0xa6",
+        "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xd7",
-        "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+        "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
+        "EventCode": "0xa6",
+        "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa6",
         "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal ADS Used : BL - All",
         "EventCode": "0xa6",
-        "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
         "EventCode": "0xa6",
-        "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
         "EventCode": "0xa6",
-        "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa6",
-        "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_ALL",
+        "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
+        "EventCode": "0xa7",
+        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal ADS Used : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa6",
-        "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_ALL",
+        "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
+        "EventCode": "0xa7",
+        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa7",
         "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal Bypass Used : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa7",
         "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
         "EventCode": "0xa7",
-        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
         "EventCode": "0xa7",
-        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.IV",
+        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
         "EventCode": "0xa7",
-        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
         "EventCode": "0xa7",
-        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Bypass Used : IV",
         "EventCode": "0xa7",
-        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AKC_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa7",
-        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_ALL",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
+        "EventCode": "0xa2",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa7",
-        "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_ALL",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
+        "EventCode": "0xa2",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa2",
         "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa2",
         "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
         "EventCode": "0xa2",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
         "EventCode": "0xa2",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.IV",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
         "EventCode": "0xa2",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
         "EventCode": "0xa2",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
         "EventCode": "0xa2",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa2",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_ALL",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
+        "EventCode": "0xa3",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa2",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_ALL",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
+        "EventCode": "0xa3",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa3",
         "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa3",
         "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
         "EventCode": "0xa3",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
         "EventCode": "0xa3",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.IV",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
         "EventCode": "0xa3",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
         "EventCode": "0xa3",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
         "EventCode": "0xa3",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa3",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_ALL",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
+        "EventCode": "0xa1",
+        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa3",
-        "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_ALL",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
+        "EventCode": "0xa1",
+        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa1",
         "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Inserts : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa1",
         "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
         "EventCode": "0xa1",
-        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
         "EventCode": "0xa1",
-        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.IV",
+        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
         "EventCode": "0xa1",
-        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
         "EventCode": "0xa1",
-        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Inserts : IV",
         "EventCode": "0xa1",
-        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AKC_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa1",
-        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_ALL",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
+        "EventCode": "0xa4",
+        "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa1",
-        "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_ALL",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
+        "EventCode": "0xa4",
+        "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa4",
         "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal Egress NACKs : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa4",
         "EventName": "UNC_M2P_TxR_HORZ_NACK.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
         "EventCode": "0xa4",
-        "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_NACK.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
         "EventCode": "0xa4",
-        "EventName": "UNC_M2P_TxR_HORZ_NACK.IV",
+        "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
         "EventCode": "0xa4",
-        "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_CRD",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
         "EventCode": "0xa4",
-        "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress NACKs : IV",
         "EventCode": "0xa4",
-        "EventName": "UNC_M2P_TxR_HORZ_NACK.AKC_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_NACK.IV",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa4",
-        "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_ALL",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
+        "EventCode": "0xa0",
+        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_ALL",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
         "UMask": "0x11",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa4",
-        "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_ALL",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
+        "EventCode": "0xa0",
+        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_CRD",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa0",
         "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa0",
         "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
-    },
-    {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa0",
-        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_UNCRD",
-        "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
         "EventCode": "0xa0",
-        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.IV",
+        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
         "EventCode": "0xa0",
-        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_CRD",
+        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+        "UMask": "0x44",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa0",
         "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_CRD",
         "PerPkg": "1",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
         "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
         "EventCode": "0xa0",
-        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
         "EventCode": "0xa0",
-        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_ALL",
+        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.IV",
         "PerPkg": "1",
-        "UMask": "0x11",
+        "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa0",
-        "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_ALL",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
+        "EventCode": "0xa5",
+        "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_ALL",
         "PerPkg": "1",
-        "UMask": "0x44",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa5",
         "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xa5",
         "EventName": "UNC_M2P_TxR_HORZ_STARVED.AK",
         "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "M2PCIe"
-    },
-    {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xa5",
-        "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_UNCRD",
-        "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
         "EventCode": "0xa5",
-        "EventName": "UNC_M2P_TxR_HORZ_STARVED.IV",
+        "EventName": "UNC_M2P_TxR_HORZ_STARVED.AKC_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x80",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
         "EventCode": "0xa5",
-        "EventName": "UNC_M2P_TxR_HORZ_STARVED.AKC_UNCRD",
+        "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_ALL",
         "PerPkg": "1",
-        "UMask": "0x80",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
         "EventCode": "0xa5",
-        "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_ALL",
+        "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_UNCRD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
         "EventCode": "0xa5",
-        "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_ALL",
+        "EventName": "UNC_M2P_TxR_HORZ_STARVED.IV",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9c",
         "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
         "EventCode": "0x9c",
-        "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
         "EventCode": "0x9c",
-        "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9c",
         "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
         "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9d",
         "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
         "EventCode": "0x9d",
-        "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
         "EventCode": "0x9d",
-        "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
         "EventCode": "0x9d",
-        "EventName": "UNC_M2P_TxR_VERT_BYPASS.IV_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
         "EventCode": "0x9d",
-        "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
         "EventCode": "0x9d",
-        "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
         "EventCode": "0x9d",
-        "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_BYPASS.IV_AG1",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9e",
         "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9e",
         "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x94",
         "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
         "EventCode": "0x94",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
         "EventCode": "0x94",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
         "EventCode": "0x94",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.IV_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
         "EventCode": "0x94",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
         "EventCode": "0x94",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
         "EventCode": "0x94",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x95",
         "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x95",
         "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x96",
         "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
         "EventCode": "0x96",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
         "EventCode": "0x96",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
         "EventCode": "0x96",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.IV_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
         "EventCode": "0x96",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
         "EventCode": "0x96",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
         "EventCode": "0x96",
-        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x97",
         "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x97",
         "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x92",
         "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
         "EventCode": "0x92",
-        "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
         "EventCode": "0x92",
-        "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
         "EventCode": "0x92",
-        "EventName": "UNC_M2P_TxR_VERT_INSERTS0.IV_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
         "EventCode": "0x92",
-        "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
         "EventCode": "0x92",
-        "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
         "EventCode": "0x92",
-        "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_INSERTS0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x93",
         "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x93",
         "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x98",
         "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
-    },
-    {
-        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG0",
-        "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x98",
-        "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG0",
-        "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
-    },
-    {
-        "BriefDescription": "CMS Vertical Egress NACKs : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
         "EventCode": "0x98",
-        "EventName": "UNC_M2P_TxR_VERT_NACK0.IV_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
         "EventCode": "0x98",
-        "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x98",
         "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
         "UMask": "0x20",
         "Unit": "M2PCIe"
     },
+    {
+        "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG0",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x4",
+        "Unit": "M2PCIe"
+    },
     {
         "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x98",
         "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG1",
         "PerPkg": "1",
+        "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
         "UMask": "0x40",
         "Unit": "M2PCIe"
     },
+    {
+        "BriefDescription": "CMS Vertical Egress NACKs : IV",
+        "EventCode": "0x98",
+        "EventName": "UNC_M2P_TxR_VERT_NACK0.IV_AG0",
+        "PerPkg": "1",
+        "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x8",
+        "Unit": "M2PCIe"
+    },
     {
         "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x99",
         "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x99",
         "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x90",
         "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
         "EventCode": "0x90",
-        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring.  This is commonly used for outbound requests.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
         "EventCode": "0x90",
-        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
         "EventCode": "0x90",
-        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.IV_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
         "EventCode": "0x90",
-        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring.  This is commonly used to send data from the cache to various destinations.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
         "EventCode": "0x90",
-        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring.  This is commonly used for transferring writeback data to the cache.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
         "EventCode": "0x90",
-        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring.  This is commonly used for snoops to the cores.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x91",
         "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring.  Some example include outbound requests, snoop requests, and snoop responses.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x91",
         "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring.  This is commonly used for credit returns and GO responses.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9a",
         "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
         "EventCode": "0x9a",
-        "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x10",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
         "EventCode": "0x9a",
-        "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG0",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
         "EventCode": "0x9a",
-        "EventName": "UNC_M2P_TxR_VERT_STARVED0.IV_AG0",
+        "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG1",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x20",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
         "EventCode": "0x9a",
-        "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG0",
         "PerPkg": "1",
-        "UMask": "0x10",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
         "EventCode": "0x9a",
-        "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG1",
         "PerPkg": "1",
-        "UMask": "0x20",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x40",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
         "EventCode": "0x9a",
-        "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG1",
+        "EventName": "UNC_M2P_TxR_VERT_STARVED0.IV_AG0",
         "PerPkg": "1",
-        "UMask": "0x40",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9b",
         "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG0",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9b",
         "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG1",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x9b",
         "EventName": "UNC_M2P_TxR_VERT_STARVED1.TGC",
         "PerPkg": "1",
-        "UMask": "0x04",
-        "Unit": "M2PCIe"
-    },
-    {
-        "BriefDescription": "Vertical AD Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb0",
-        "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_EVEN",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "M2PCIe"
-    },
-    {
-        "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb0",
-        "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_ODD",
-        "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Vertical AD Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xb0",
         "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xb0",
         "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb4",
-        "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_EVEN",
+        "BriefDescription": "Vertical AD Ring In Use : Up and Even",
+        "EventCode": "0xb0",
+        "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb4",
-        "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_ODD",
+        "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
+        "EventCode": "0xb0",
+        "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xb4",
         "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xb4",
         "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb1",
-        "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_EVEN",
+        "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
+        "EventCode": "0xb4",
+        "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb1",
-        "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_ODD",
+        "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
+        "EventCode": "0xb4",
+        "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Vertical AK Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xb1",
         "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xb1",
         "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb2",
-        "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_EVEN",
+        "BriefDescription": "Vertical AK Ring In Use : Up and Even",
+        "EventCode": "0xb1",
+        "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb2",
-        "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_ODD",
+        "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
+        "EventCode": "0xb1",
+        "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Vertical BL Ring in Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xb2",
         "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xb2",
         "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical IV Ring in Use : Up",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb3",
-        "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.UP",
+        "BriefDescription": "Vertical BL Ring in Use : Up and Even",
+        "EventCode": "0xb2",
+        "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_EVEN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical IV Ring in Use : Down",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb3",
-        "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.DN",
+        "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
+        "EventCode": "0xb2",
+        "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_ODD",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb5",
-        "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_EVEN",
+        "BriefDescription": "Vertical IV Ring in Use : Down",
+        "EventCode": "0xb3",
+        "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.DN",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xb5",
-        "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_ODD",
+        "BriefDescription": "Vertical IV Ring in Use : Up",
+        "EventCode": "0xb3",
+        "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.UP",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN.  To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xb5",
         "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_EVEN",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x4",
         "Unit": "M2PCIe"
     },
     {
         "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0xb5",
         "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_ODD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x8",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Source Throttle",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xae",
-        "EventName": "UNC_M2P_RING_SRC_THRTL",
+        "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
+        "EventCode": "0xb5",
+        "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_EVEN",
         "PerPkg": "1",
+        "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x1",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Transgress Injection Starvation",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0xe4",
-        "EventName": "UNC_M2P_RxR_CRD_STARVED_1",
+        "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
+        "EventCode": "0xb5",
+        "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_ODD",
         "PerPkg": "1",
+        "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+        "UMask": "0x2",
         "Unit": "M2PCIe"
     },
     {
-        "BriefDescription": "Message Received : VLW",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
-        "PerPkg": "1",
-        "UMask": "0x01",
-        "Unit": "UBOX"
-    },
-    {
-        "BriefDescription": "Message Received : MSI",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
-        "PerPkg": "1",
-        "UMask": "0x02",
-        "Unit": "UBOX"
-    },
-    {
-        "BriefDescription": "Message Received : IPI",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
+        "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
+        "EventCode": "0xff",
+        "EventName": "UNC_U_CLOCKTICKS",
         "PerPkg": "1",
-        "UMask": "0x04",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "Message Received : Doorbell",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
         "EventCode": "0x42",
         "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
         "PerPkg": "1",
-        "UMask": "0x08",
+        "UMask": "0x8",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "Message Received : Interrupt",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
         "EventCode": "0x42",
         "EventName": "UNC_U_EVENT_MSG.INT_PRIO",
         "PerPkg": "1",
+        "PublicDescription": "Message Received : Interrupt : Interrupts",
         "UMask": "0x10",
         "Unit": "UBOX"
     },
     {
-        "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x45",
-        "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
+        "BriefDescription": "Message Received : IPI",
+        "EventCode": "0x42",
+        "EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Message Received : IPI : Inter Processor Interrupts",
+        "UMask": "0x4",
         "Unit": "UBOX"
     },
     {
-        "BriefDescription": "UNC_U_RACU_DRNG.RDRAND",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4C",
-        "EventName": "UNC_U_RACU_DRNG.RDRAND",
+        "BriefDescription": "Message Received : MSI",
+        "EventCode": "0x42",
+        "EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "PublicDescription": "Message Received : MSI : Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)",
+        "UMask": "0x2",
         "Unit": "UBOX"
     },
     {
-        "BriefDescription": "UNC_U_RACU_DRNG.RDSEED",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4C",
-        "EventName": "UNC_U_RACU_DRNG.RDSEED",
+        "BriefDescription": "Message Received : VLW",
+        "EventCode": "0x42",
+        "EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "PublicDescription": "Message Received : VLW : Virtual Logical Wire (legacy) message were received from Uncore.",
+        "UMask": "0x1",
         "Unit": "UBOX"
     },
     {
-        "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4C",
-        "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+        "BriefDescription": "IDI Lock/SplitLock Cycles",
+        "EventCode": "0x44",
+        "EventName": "UNC_U_LOCK_CYCLES",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "PublicDescription": "IDI Lock/SplitLock Cycles : Number of times an IDI Lock/SplitLock sequence was started",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
         "EventCode": "0x4D",
         "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
         "EventCode": "0x4D",
         "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
         "EventCode": "0x4D",
         "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB",
         "PerPkg": "1",
@@ -25063,8 +21964,6 @@
     },
     {
         "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
         "EventCode": "0x4D",
         "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS",
         "PerPkg": "1",
@@ -25072,59 +21971,39 @@
         "Unit": "UBOX"
     },
     {
-        "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
         "EventCode": "0x4E",
-        "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
+        "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x2",
         "Unit": "UBOX"
     },
     {
-        "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
+        "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
         "EventCode": "0x4E",
-        "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
+        "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x1",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
         "EventCode": "0x4E",
         "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB",
         "PerPkg": "1",
-        "UMask": "0x04",
+        "UMask": "0x4",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
         "EventCode": "0x4E",
         "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS",
         "PerPkg": "1",
-        "UMask": "0x08",
-        "Unit": "UBOX"
-    },
-    {
-        "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x4E",
-        "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
-        "PerPkg": "1",
-        "UMask": "0x10",
+        "UMask": "0x8",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
         "EventCode": "0x4E",
         "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK",
         "PerPkg": "1",
@@ -25133,18 +22012,22 @@
     },
     {
         "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
         "EventCode": "0x4E",
         "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC",
         "PerPkg": "1",
         "UMask": "0x40",
         "Unit": "UBOX"
     },
+    {
+        "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
+        "EventCode": "0x4E",
+        "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
+        "PerPkg": "1",
+        "UMask": "0x10",
+        "Unit": "UBOX"
+    },
     {
         "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
         "EventCode": "0x4E",
         "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL",
         "PerPkg": "1",
@@ -25153,40 +22036,59 @@
     },
     {
         "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
         "EventCode": "0x4F",
         "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK",
         "PerPkg": "1",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
         "EventCode": "0x4F",
         "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC",
         "PerPkg": "1",
-        "UMask": "0x02",
+        "UMask": "0x2",
         "Unit": "UBOX"
     },
     {
-        "BriefDescription": "IDI Lock/SplitLock Cycles",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x44",
-        "EventName": "UNC_U_LOCK_CYCLES",
+        "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK",
+        "EventCode": "0x45",
+        "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
+        "PerPkg": "1",
+        "PublicDescription": "Cycles PHOLD Assert to Ack : Assert to ACK : PHOLD cycles.",
+        "UMask": "0x1",
+        "Unit": "UBOX"
+    },
+    {
+        "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+        "EventCode": "0x4C",
+        "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+        "PerPkg": "1",
+        "UMask": "0x4",
+        "Unit": "UBOX"
+    },
+    {
+        "BriefDescription": "UNC_U_RACU_DRNG.RDRAND",
+        "EventCode": "0x4C",
+        "EventName": "UNC_U_RACU_DRNG.RDRAND",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "UBOX"
+    },
+    {
+        "BriefDescription": "UNC_U_RACU_DRNG.RDSEED",
+        "EventCode": "0x4C",
+        "EventName": "UNC_U_RACU_DRNG.RDSEED",
         "PerPkg": "1",
+        "UMask": "0x2",
         "Unit": "UBOX"
     },
     {
         "BriefDescription": "RACU Request",
-        "Counter": "0,1",
-        "CounterType": "PGMABLE",
         "EventCode": "0x46",
         "EventName": "UNC_U_RACU_REQUESTS",
         "PerPkg": "1",
+        "PublicDescription": "RACU Request : Number outstanding register requests within message channel tracker",
         "Unit": "UBOX"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-power.json b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-power.json
index 281f3605881d2..27fc155f12234 100644
--- a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-power.json
@@ -1,16 +1,12 @@
 [
     {
         "BriefDescription": "Clockticks of the power control unit (PCU)",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventName": "UNC_P_CLOCKTICKS",
         "PerPkg": "1",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x60",
         "EventName": "UNC_P_CORE_TRANSITION_CYCLES",
         "PerPkg": "1",
@@ -18,8 +14,6 @@
     },
     {
         "BriefDescription": "UNC_P_DEMOTIONS",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x30",
         "EventName": "UNC_P_DEMOTIONS",
         "PerPkg": "1",
@@ -27,44 +21,38 @@
     },
     {
         "BriefDescription": "Phase Shed 0 Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x75",
         "EventName": "UNC_P_FIVR_PS_PS0_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Phase Shed 1 Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x76",
         "EventName": "UNC_P_FIVR_PS_PS1_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Phase Shed 2 Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x77",
         "EventName": "UNC_P_FIVR_PS_PS2_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Phase Shed 3 Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x78",
         "EventName": "UNC_P_FIVR_PS_PS3_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "AVX256 Frequency Clipping",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x49",
         "EventName": "UNC_P_FREQ_CLIP_AVX256",
         "PerPkg": "1",
@@ -72,8 +60,6 @@
     },
     {
         "BriefDescription": "AVX512 Frequency Clipping",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x4a",
         "EventName": "UNC_P_FREQ_CLIP_AVX512",
         "PerPkg": "1",
@@ -81,155 +67,137 @@
     },
     {
         "BriefDescription": "Thermal Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x04",
         "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Thermal Strongest Upper Limit Cycles : Number of cycles any frequency is reduced due to a thermal limit.  Count only if throttling is occurring.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Power Strongest Upper Limit Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x05",
         "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Power Strongest Upper Limit Cycles : Counts the number of cycles when power is the upper limit on frequency.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x73",
         "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "IO P Limit Strongest Lower Limit Cycles : Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower.  This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW.  This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Cycles spent changing Frequency",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x74",
         "EventName": "UNC_P_FREQ_TRANS_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Cycles spent changing Frequency : Counts the number of cycles when the system is changing frequency.  This can not be filtered by thread ID.  One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Memory Phase Shedding Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x2F",
         "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has triggered memory phase shedding.  This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C0",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x2A",
         "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Package C State Residency - C0 : Counts the number of cycles when the package was in C0.  This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C2E",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x2B",
         "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Package C State Residency - C2E : Counts the number of cycles when the package was in C2E.  This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x2C",
         "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Package C State Residency - C3 : Counts the number of cycles when the package was in C3.  This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "Package C State Residency - C6",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x2D",
         "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Package C State Residency - C6 : Counts the number of cycles when the package was in C6.  This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert).  Residency events do not include transition times.",
         "Unit": "PCU"
     },
     {
         "BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
         "EventCode": "0x06",
         "EventName": "UNC_P_PMAX_THROTTLED_CYCLES",
         "PerPkg": "1",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "External Prochot",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x0A",
-        "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
+        "BriefDescription": "Number of cores in C-State : C0 and C1",
+        "EventCode": "0x80",
+        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
         "PerPkg": "1",
+        "PublicDescription": "Number of cores in C-State : C0 and C1 : This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "Internal Prochot",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x09",
-        "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
+        "BriefDescription": "Number of cores in C-State : C3",
+        "EventCode": "0x80",
+        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
         "PerPkg": "1",
+        "PublicDescription": "Number of cores in C-State : C3 : This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "Total Core C State Transition Cycles",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x72",
-        "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
+        "BriefDescription": "Number of cores in C-State : C6 and C7",
+        "EventCode": "0x80",
+        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
         "PerPkg": "1",
+        "PublicDescription": "Number of cores in C-State : C6 and C7 : This is an occupancy event that tracks the number of cores that are in the chosen C-State.  It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "VR Hot",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x42",
-        "EventName": "UNC_P_VR_HOT_CYCLES",
+        "BriefDescription": "External Prochot",
+        "EventCode": "0x0A",
+        "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "External Prochot : Counts the number of cycles that we are in external PROCHOT mode.  This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "Number of cores in C-State : C0 and C1",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
+        "BriefDescription": "Internal Prochot",
+        "EventCode": "0x09",
+        "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Internal Prochot : Counts the number of cycles that we are in Internal PROCHOT mode.  This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "Number of cores in C-State : C3",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
+        "BriefDescription": "Total Core C State Transition Cycles",
+        "EventCode": "0x72",
+        "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "Total Core C State Transition Cycles : Number of cycles spent performing core C state transitions across all cores.",
         "Unit": "PCU"
     },
     {
-        "BriefDescription": "Number of cores in C-State : C6 and C7",
-        "Counter": "0,1,2,3",
-        "CounterType": "PGMABLE",
-        "EventCode": "0x80",
-        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
+        "BriefDescription": "VR Hot",
+        "EventCode": "0x42",
+        "EventName": "UNC_P_VR_HOT_CYCLES",
         "PerPkg": "1",
+        "PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR is hot.  Does not cover DRAM VRs",
         "Unit": "PCU"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/virtual-memory.json b/tools/perf/pmu-events/arch/x86/snowridgex/virtual-memory.json
index b82f11591f133..cabe29e70e796 100644
--- a/tools/perf/pmu-events/arch/x86/snowridgex/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/snowridgex/virtual-memory.json
@@ -1,363 +1,246 @@
 [
     {
         "BriefDescription": "Counts the number of page walks due to loads that miss the PDE (Page Directory Entry) cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Account for all page sizes. Will result in a DTLB write from STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
         "SampleAfterValue": "200003",
         "UMask": "0xe"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1GB pages. Includes page walks that page fault.",
         "SampleAfterValue": "200003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for demand loads every cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for demand loads every cycle.  A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
         "SampleAfterValue": "200003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts the number of page walks due to stores that miss the PDE (Page Directory Entry) cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "2000003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Account for all pages sizes. Will result in a DTLB write from STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "2000003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size.  Includes page walks that page fault.",
         "SampleAfterValue": "200003",
         "UMask": "0xe"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages.  Includes page walks that page fault.",
         "SampleAfterValue": "200003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 2M or 4M page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages.  Includes page walks that page fault.",
         "SampleAfterValue": "2000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages.  Includes page walks that page fault.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.  A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
         "SampleAfterValue": "200003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts the number of Extended Page Directory Entry hits.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4f",
         "EventName": "EPT.EPDE_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of Extended Page Directory Entry hits.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of Extended Page Directory Entry misses.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4f",
         "EventName": "EPT.EPDE_MISS",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number Extended Page Directory Entry misses.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of Extended Page Directory Pointer Entry hits.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4f",
         "EventName": "EPT.EPDPE_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number Extended Page Directory Pointer Entry hits.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
         "SampleAfterValue": "2000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of Extended Page Directory Pointer Entry misses.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4f",
         "EventName": "EPT.EPDPE_MISS",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number Extended Page Directory Pointer Entry misses.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
         "SampleAfterValue": "2000003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4f",
         "EventName": "EPT.WALK_PENDING",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
         "SampleAfterValue": "200003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts the number of times there was an ITLB miss and a new translation was filled into the ITLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x81",
         "EventName": "ITLB.FILLS",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and a new translation was filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.PDE_CACHE_MISS",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "2000003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "2000003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size.  Includes page walks that page fault.",
         "SampleAfterValue": "200003",
         "UMask": "0xe"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 1G page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages.  Includes page walks that page fault.",
         "SampleAfterValue": "200003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages.  Includes page walks that page fault.",
         "SampleAfterValue": "2000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 4K page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages.  Includes page walks that page fault.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_PENDING",
-        "PDIR_COUNTER": "NA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle.  A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk).",
         "SampleAfterValue": "200003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts the number of retired loads that are blocked due to a first level TLB miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.DTLB_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts the number of memory uops retired that missed in the second level TLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.DTLB_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x13"
     },
     {
         "BriefDescription": "Counts the number of load uops retired that miss in the second Level TLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x11"
     },
     {
         "BriefDescription": "Counts the number of store uops retired that miss in the second level TLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "200003",
         "UMask": "0x12"
     }
-- 
GitLab


From 69f685e0c125a9811b5489c2ece21708878fa6f9 Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:55:07 -0800
Subject: [PATCH 591/875] perf vendor events intel: Refresh tigerlake metrics
 and events

Update the tigerlake metrics and events using the new tooling from:

  https://github.com/intel/perfmon

The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1".  The
events are updated to version 1.08 and unused json values are
removed. The formatting changes increase consistency across the json
files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-21-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/pmu-events/arch/x86/mapfile.csv    |   2 +-
 .../pmu-events/arch/x86/tigerlake/cache.json  | 210 +------------
 .../arch/x86/tigerlake/floating-point.json    |  27 --
 .../arch/x86/tigerlake/frontend.json          | 125 --------
 .../pmu-events/arch/x86/tigerlake/memory.json |  77 -----
 .../pmu-events/arch/x86/tigerlake/other.json  |  13 -
 .../arch/x86/tigerlake/pipeline.json          | 287 +-----------------
 .../arch/x86/tigerlake/tgl-metrics.json       | 141 +++++----
 .../arch/x86/tigerlake/uncore-other.json      |  96 ++++--
 .../arch/x86/tigerlake/virtual-memory.json    |  60 ----
 10 files changed, 157 insertions(+), 881 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index a5de68bcebcd0..b9ed4eb0b9160 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -26,7 +26,7 @@ GenuineIntel-6-(37|4A|4C|4D|5A),v14,silvermont,core
 GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v53,skylake,core
 GenuineIntel-6-55-[01234],v1.28,skylakex,core
 GenuineIntel-6-86,v1.20,snowridgex,core
-GenuineIntel-6-8[CD],v1.07,tigerlake,core
+GenuineIntel-6-8[CD],v1.08,tigerlake,core
 GenuineIntel-6-2C,v2,westmereep-dp,core
 GenuineIntel-6-25,v3,westmereep-sp,core
 GenuineIntel-6-2F,v3,westmereex,core
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/cache.json b/tools/perf/pmu-events/arch/x86/tigerlake/cache.json
index 5ccf0edc29acf..738249a6f4881 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/cache.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/cache.json
@@ -1,747 +1,551 @@
 [
     {
         "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x51",
         "EventName": "L1D.REPLACEMENT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.FB_FULL",
-        "PEBScounters": "0,1,2,3",
-        "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
+        "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
         "SampleAfterValue": "1000003",
         "UMask": "0x2"
     },
     {
-        "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS",
-        "PEBScounters": "0,1,2,3",
-        "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
+        "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
         "SampleAfterValue": "1000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.L2_STALL",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
         "SampleAfterValue": "1000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of L1D misses that are outstanding",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
         "SampleAfterValue": "1000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles with L1D load Misses outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x48",
         "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
         "SampleAfterValue": "1000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "L2 cache lines filling L2",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xf1",
         "EventName": "L2_LINES_IN.ALL",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
         "SampleAfterValue": "100003",
         "UMask": "0x1f"
     },
     {
         "BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xf2",
         "EventName": "L2_LINES_OUT.NON_SILENT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xf2",
         "EventName": "L2_LINES_OUT.SILENT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "L2 code requests",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_CODE_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of L2 code requests.",
         "SampleAfterValue": "200003",
         "UMask": "0xe4"
     },
     {
         "BriefDescription": "Demand Data Read access L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.",
         "SampleAfterValue": "200003",
         "UMask": "0xe1"
     },
     {
         "BriefDescription": "RFO requests to L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.ALL_RFO",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
         "SampleAfterValue": "200003",
         "UMask": "0xe2"
     },
     {
         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
         "SampleAfterValue": "200003",
         "UMask": "0xc4"
     },
     {
         "BriefDescription": "L2 cache misses when fetching instructions",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.CODE_RD_MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts L2 cache misses when fetching instructions.",
         "SampleAfterValue": "200003",
         "UMask": "0x24"
     },
     {
         "BriefDescription": "Demand Data Read requests that hit L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
         "SampleAfterValue": "200003",
         "UMask": "0xc1"
     },
     {
         "BriefDescription": "Demand Data Read miss L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once.",
         "SampleAfterValue": "200003",
         "UMask": "0x21"
     },
     {
         "BriefDescription": "Read requests with true-miss in L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses.",
         "SampleAfterValue": "200003",
         "UMask": "0x3f"
     },
     {
         "BriefDescription": "All accesses to L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.REFERENCES",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses.",
         "SampleAfterValue": "200003",
         "UMask": "0xff"
     },
     {
         "BriefDescription": "RFO requests that hit L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
         "SampleAfterValue": "200003",
         "UMask": "0xc2"
     },
     {
         "BriefDescription": "RFO requests that miss L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
         "SampleAfterValue": "200003",
         "UMask": "0x22"
     },
     {
         "BriefDescription": "SW prefetch requests that hit L2 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.SWPF_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
         "SampleAfterValue": "200003",
         "UMask": "0xc8"
     },
     {
         "BriefDescription": "SW prefetch requests that miss L2 cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.SWPF_MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
         "SampleAfterValue": "200003",
         "UMask": "0x28"
     },
     {
         "BriefDescription": "L2 writebacks that access L2 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xf0",
         "EventName": "L2_TRANS.L2_WB",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts L2 writebacks that access L2 cache.",
         "SampleAfterValue": "200003",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Cycles when L1D is locked",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x63",
         "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Core-originated cacheable requests that missed L3  (Except hardware prefetches to the L3)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x2e",
         "EventName": "LONGEST_LAT_CACHE.MISS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2.  It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
         "SampleAfterValue": "100003",
         "UMask": "0x41"
     },
     {
-        "BriefDescription": "All retired load instructions.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Retired load instructions.",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.ALL_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
-        "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions for loads.",
+        "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",
         "SampleAfterValue": "1000003",
         "UMask": "0x81"
     },
     {
-        "BriefDescription": "All retired store instructions.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
+        "BriefDescription": "Retired store instructions.",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.ALL_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
-        "PublicDescription": "Counts all retired store instructions. This event account for SW prefetch instructions and PREFETCHW instruction for stores.",
+        "PublicDescription": "Counts all retired store instructions.",
         "SampleAfterValue": "1000003",
         "UMask": "0x82"
     },
     {
         "BriefDescription": "All retired memory instructions.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.ANY",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts all retired memory instructions - loads and stores.",
         "SampleAfterValue": "1000003",
         "UMask": "0x83"
     },
     {
         "BriefDescription": "Retired load instructions with locked access.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.LOCK_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with locked access.",
         "SampleAfterValue": "100007",
         "UMask": "0x21"
     },
     {
         "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",
         "SampleAfterValue": "100003",
         "UMask": "0x41"
     },
     {
         "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.SPLIT_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
         "SampleAfterValue": "100003",
         "UMask": "0x42"
     },
     {
         "BriefDescription": "Retired load instructions that miss the STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).",
         "SampleAfterValue": "100003",
         "UMask": "0x11"
     },
     {
         "BriefDescription": "Retired store instructions that miss the STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd0",
         "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
-        "L1_Hit_Indication": "1",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).",
         "SampleAfterValue": "100003",
         "UMask": "0x12"
     },
     {
         "BriefDescription": "Snoop hit a modified(HITM) or clean line(HIT_W_FWD) in another on-pkg core which forwarded the data back due to a retired load instruction.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions where a cross-core snoop hit in another cores caches on this socket, the data was forwarded back to the requesting core as the data was modified (SNOOP_HITM) or the L3 did not have the data(SNOOP_HIT_WITH_FWD).",
         "SampleAfterValue": "20011",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
         "SampleAfterValue": "20011",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.",
         "SampleAfterValue": "100003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Snoop hit without forwarding in another on-pkg core due to a retired load instruction, data was supplied by the L3.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd2",
         "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions in which the L3 supplied the data and a cross-core snoop hit in another cores caches on this socket but that other core did not forward the data back (SNOOP_HIT_NO_FWD).",
         "SampleAfterValue": "20011",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.FB_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.",
         "SampleAfterValue": "100007",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L1_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.",
         "SampleAfterValue": "1000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired load instructions missed L1 cache as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L1_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
         "SampleAfterValue": "200003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L2_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Retired load instructions missed L2 cache as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L2_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
         "SampleAfterValue": "100021",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L3_HIT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.",
         "SampleAfterValue": "100021",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Retired load instructions missed L3 cache as data sources",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "Data_LA": "1",
         "EventCode": "0xd1",
         "EventName": "MEM_LOAD_RETIRED.L3_MISS",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.",
         "SampleAfterValue": "50021",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0001",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003C0001",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10003C0002",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Demand and prefetch data reads",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb0",
         "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
         "SampleAfterValue": "100003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Any memory transaction that reached the SQ.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb0",
         "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..",
         "SampleAfterValue": "100003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Demand Data Read requests sent to uncore",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb0",
         "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
         "SampleAfterValue": "100003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
         "SampleAfterValue": "1000003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
         "SampleAfterValue": "1000003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
         "SampleAfterValue": "1000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Demand Data Read transactions pending for off-core. Highly correlated.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of off-core outstanding Demand Data Read transactions every cycle. A transaction is considered to be in the Off-core outstanding state between L2 cache miss and data-return to the core.",
         "SampleAfterValue": "1000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "6",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Store Read transactions pending for off-core. Highly correlated.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x60",
         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion.",
         "SampleAfterValue": "1000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Cycles the superQ cannot take any more entries.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xf4",
         "EventName": "SQ_MISC.SQ_FULL",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the cycles for which the thread is active and the superQ cannot take any more entries.",
         "SampleAfterValue": "100003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of PREFETCHNTA instructions executed.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.NTA",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of PREFETCHW instructions executed.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
         "SampleAfterValue": "100003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Number of PREFETCHT0 instructions executed.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.T0",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
         "SampleAfterValue": "100003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x32",
         "EventName": "SW_PREFETCH_ACCESS.T1_T2",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
         "SampleAfterValue": "100003",
         "UMask": "0x4"
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json b/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json
index 978b494c7458d..655342dadac66 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json
@@ -1,99 +1,72 @@
 [
     {
         "BriefDescription": "Counts all microcode FP assists.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc1",
         "EventName": "ASSISTS.FP",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts all microcode Floating Point assists.",
         "SampleAfterValue": "100003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc7",
         "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
         "SampleAfterValue": "100003",
         "UMask": "0x2"
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/frontend.json b/tools/perf/pmu-events/arch/x86/tigerlake/frontend.json
index ccdd8fd995561..23b8528590b34 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/frontend.json
@@ -1,476 +1,351 @@
 [
     {
         "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xe6",
         "EventName": "BACLEARS.ANY",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xab",
         "EventName": "DSB2MITE_SWITCHES.COUNT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.",
         "SampleAfterValue": "100003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xab",
         "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.",
         "SampleAfterValue": "100003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Retired Instructions who experienced DSB miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x1",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.DSB_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x11",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.ITLB_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x14",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.L1I_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x12",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.L2_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x13",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x500106",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x508006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x501006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x500206",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x510006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x100206",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x502006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x500406",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x520006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x504006",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x500806",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc6",
         "EventName": "FRONTEND_RETIRED.STLB_MISS",
         "MSRIndex": "0x3F7",
         "MSRValue": "0x15",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "ICACHE_16B.IFDATA_STALL",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.",
         "SampleAfterValue": "500009",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "ICACHE_64B.IFTAG_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.",
         "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "ICACHE_64B.IFTAG_MISS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.",
         "SampleAfterValue": "200003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x83",
         "EventName": "ICACHE_64B.IFTAG_STALL",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
         "SampleAfterValue": "200003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_CYCLES_ANY",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
         "SampleAfterValue": "2000003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Cycles DSB is delivering optimal number of Uops",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "5",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_CYCLES_OK",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
         "SampleAfterValue": "2000003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x79",
         "EventName": "IDQ.DSB_UOPS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
         "SampleAfterValue": "2000003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Cycles MITE is delivering any Uop",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_CYCLES_ANY",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
         "SampleAfterValue": "2000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Cycles MITE is delivering optimal number of Uops",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "5",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_CYCLES_OK",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
         "SampleAfterValue": "2000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x79",
         "EventName": "IDQ.MITE_UOPS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
         "SampleAfterValue": "2000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_CYCLES_ANY",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
         "SampleAfterValue": "2000003",
         "UMask": "0x30"
     },
     {
         "BriefDescription": "Number of switches from DSB or MITE to the MS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_SWITCHES",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
         "SampleAfterValue": "100003",
         "UMask": "0x30"
     },
     {
         "BriefDescription": "Uops delivered to IDQ while MS is busy",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x79",
         "EventName": "IDQ.MS_UOPS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
         "SampleAfterValue": "100003",
         "UMask": "0x30"
     },
     {
         "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x9c",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
         "SampleAfterValue": "1000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "5",
         "EventCode": "0x9c",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
         "SampleAfterValue": "1000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x9c",
         "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
         "SampleAfterValue": "1000003",
         "UMask": "0x1"
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/memory.json b/tools/perf/pmu-events/arch/x86/tigerlake/memory.json
index 6071794cbd327..8848fcbcc35c1 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/memory.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/memory.json
@@ -1,293 +1,216 @@
 [
     {
         "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "6",
         "EventCode": "0xa3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x6"
     },
     {
         "BriefDescription": "Number of machine clears due to memory ordering conflicts.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
         "SampleAfterValue": "100003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x80",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "1009",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x10",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "20011",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x100",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "503",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x20",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "100007",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x4",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "100003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x200",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "101",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x40",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "2003",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "Data_LA": "1",
         "EventCode": "0xcd",
         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
         "MSRIndex": "0x3F6",
         "MSRValue": "0x8",
         "PEBS": "2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
         "SampleAfterValue": "50021",
-        "TakenAlone": "1",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Demand Data Read requests who miss L3 cache",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xb0",
         "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Demand Data Read requests who miss L3 cache.",
         "SampleAfterValue": "100003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times RTM abort was triggered.",
         "SampleAfterValue": "100003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_EVENTS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
         "SampleAfterValue": "100003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MEM",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
         "SampleAfterValue": "100003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
         "SampleAfterValue": "100003",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
         "SampleAfterValue": "100003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Number of times an RTM execution successfully committed",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.COMMIT",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times RTM commit succeeded.",
         "SampleAfterValue": "100003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of times an RTM execution started.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc9",
         "EventName": "RTM_RETIRED.START",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",
         "SampleAfterValue": "100003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5d",
         "EventName": "TX_EXEC.MISC3",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.",
         "SampleAfterValue": "100003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CAPACITY_READ",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
         "SampleAfterValue": "100003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
         "SampleAfterValue": "100003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x54",
         "EventName": "TX_MEM.ABORT_CONFLICT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/other.json b/tools/perf/pmu-events/arch/x86/tigerlake/other.json
index 3ed22dbd0982c..55f3048bcfa6d 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/other.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/other.json
@@ -1,47 +1,34 @@
 [
     {
         "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
         "SampleAfterValue": "200003",
         "UMask": "0x7"
     },
     {
         "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
         "SampleAfterValue": "200003",
         "UMask": "0x18"
     },
     {
         "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture).  This includes high current AVX 512-bit instructions.",
         "SampleAfterValue": "200003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Counts streaming stores that have any type of response.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10800",
-        "Offcore": "1",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     }
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json b/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json
index 1f273144f8e8c..9d43decd75ecf 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json
@@ -1,675 +1,498 @@
 [
     {
         "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x14",
         "EventName": "ARITH.DIVIDER_ACTIVE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
         "SampleAfterValue": "1000003",
         "UMask": "0x9"
     },
     {
         "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc1",
         "EventName": "ASSISTS.ANY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
         "SampleAfterValue": "100003",
         "UMask": "0x7"
     },
     {
         "BriefDescription": "All branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts all branch instructions retired.",
         "SampleAfterValue": "400009"
     },
     {
         "BriefDescription": "Conditional branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.COND",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts conditional branch instructions retired.",
         "SampleAfterValue": "400009",
         "UMask": "0x11"
     },
     {
         "BriefDescription": "Not taken branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.COND_NTAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts not taken branch instructions retired.",
         "SampleAfterValue": "400009",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Taken conditional branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.COND_TAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts taken conditional branch instructions retired.",
         "SampleAfterValue": "400009",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Far branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.FAR_BRANCH",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts far branch instructions retired.",
         "SampleAfterValue": "100007",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Indirect near branch instructions retired (excluding returns)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.INDIRECT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.",
         "SampleAfterValue": "100003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Direct and indirect near call instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts both direct and indirect near call instructions retired.",
         "SampleAfterValue": "100007",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Return instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.NEAR_RETURN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts return instructions retired.",
         "SampleAfterValue": "100007",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Taken branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc4",
         "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts taken branch instructions retired.",
         "SampleAfterValue": "400009",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "All mispredicted branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch.  When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
         "SampleAfterValue": "50021"
     },
     {
         "BriefDescription": "Mispredicted conditional branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.COND",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts mispredicted conditional branch instructions retired.",
         "SampleAfterValue": "50021",
         "UMask": "0x11"
     },
     {
         "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.COND_NTAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.",
         "SampleAfterValue": "50021",
         "UMask": "0x10"
     },
     {
-        "BriefDescription": "number of branch instructions retired that were mispredicted and taken. Non PEBS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
+        "BriefDescription": "number of branch instructions retired that were mispredicted and taken.",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.COND_TAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts taken conditional mispredicted branch instructions retired.",
         "SampleAfterValue": "50021",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.INDIRECT",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
         "SampleAfterValue": "50021",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Mispredicted indirect CALL instructions retired.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.INDIRECT_CALL",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.",
         "SampleAfterValue": "50021",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc5",
         "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.",
         "SampleAfterValue": "50021",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xec",
         "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0.  A hyperthread becomes inactive when it executes the HLT or MWAIT instructions.  If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.",
         "SampleAfterValue": "25003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
         "SampleAfterValue": "2000003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Reference cycles when the core is not in halt state.",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 2",
         "EventName": "CPU_CLK_UNHALTED.REF_TSC",
-        "PEBScounters": "34",
         "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
         "SampleAfterValue": "2000003",
         "UMask": "0x3"
     },
     {
         "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts core crystal clock cycles when the thread is unhalted.",
         "SampleAfterValue": "25003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Core cycles when the thread is not in halt state",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 1",
         "EventName": "CPU_CLK_UNHALTED.THREAD",
-        "PEBScounters": "33",
         "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Thread cycles when thread is not in halt state",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x3c",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
         "SampleAfterValue": "2000003"
     },
     {
         "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "8",
         "EventCode": "0xa3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xa3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "16",
         "EventCode": "0xa3",
         "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "12",
         "EventCode": "0xa3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0xc"
     },
     {
         "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "5",
         "EventCode": "0xa3",
         "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
-        "PEBScounters": "0,1,2,3",
         "SampleAfterValue": "1000003",
         "UMask": "0x5"
     },
     {
         "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "20",
         "EventCode": "0xa3",
         "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
         "UMask": "0x14"
     },
     {
         "BriefDescription": "Total execution stalls.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xa3",
         "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "1000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa6",
         "EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa6",
         "EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
         "SampleAfterValue": "2000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa6",
         "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
         "SampleAfterValue": "2000003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa6",
         "EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
         "SampleAfterValue": "2000003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "5",
         "EventCode": "0xa6",
         "EventName": "EXE_ACTIVITY.BOUND_ON_LOADS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycle.",
         "SampleAfterValue": "2000003",
         "UMask": "0x21"
     },
     {
         "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xa6",
         "EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.",
         "SampleAfterValue": "1000003",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Cycles no uop executed while RS was not empty, the SB was not full and there was no outstanding load.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa6",
         "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of cycles total of 0 uops executed on all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) was not full and there was no outstanding load.",
         "SampleAfterValue": "1000003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.LCP",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
         "SampleAfterValue": "500009",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Instruction decoders utilized in a cycle",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x55",
         "EventName": "INST_DECODED.DECODERS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 0",
         "EventName": "INST_RETIRED.ANY",
         "PEBS": "1",
-        "PEBScounters": "32",
         "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of instructions retired. General Counter - architectural event",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc0",
         "EventName": "INST_RETIRED.ANY_P",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
         "SampleAfterValue": "2000003"
     },
     {
-        "BriefDescription": "Number of all retired NOP instructions.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
+        "BriefDescription": "Retired NOP instructions.",
         "EventCode": "0xc0",
         "EventName": "INST_RETIRED.NOP",
         "PEBS": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
+        "PublicDescription": "Counts all retired NOP or ENDBR32/64 instructions",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 0",
         "EventName": "INST_RETIRED.PREC_DIST",
         "PEBS": "1",
-        "PEBScounters": "32",
         "PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0d",
         "EventName": "INT_MISC.ALL_RECOVERY_CYCLES",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
         "SampleAfterValue": "2000003",
         "UMask": "0x3"
     },
     {
         "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0d",
         "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
         "SampleAfterValue": "500009",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0d",
         "EventName": "INT_MISC.RECOVERY_CYCLES",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
         "SampleAfterValue": "500009",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "TMA slots where uops got dropped",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0d",
         "EventName": "INT_MISC.UOP_DROPPING",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons",
         "SampleAfterValue": "1000003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.NO_SR",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
         "SampleAfterValue": "100003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x03",
         "EventName": "LD_BLOCKS.STORE_FORWARD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
         "SampleAfterValue": "100003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "False dependencies in MOB due to partial compare on address.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x07",
         "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4c",
         "EventName": "LOAD_HIT_PREFETCH.SWPF",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xa8",
         "EventName": "LSD.CYCLES_ACTIVE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "5",
         "EventCode": "0xa8",
         "EventName": "LSD.CYCLES_OK",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of Uops delivered by the LSD.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xa8",
         "EventName": "LSD.UOPS",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of machine clears (nukes) of any type.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.COUNT",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of machine clears (nukes) of any type.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Self-modifying code (SMC) detected.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc3",
         "EventName": "MACHINE_CLEARS.SMC",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
         "SampleAfterValue": "100003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Increments whenever there is an update to the LBR array.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xcc",
         "EventName": "MISC_RETIRED.LBR_INSERTS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.",
         "SampleAfterValue": "100003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xcc",
         "EventName": "MISC_RETIRED.PAUSE_INST",
         "PublicDescription": "Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.",
@@ -678,391 +501,289 @@
     },
     {
         "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa2",
         "EventName": "RESOURCE_STALLS.SB",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
         "SampleAfterValue": "100003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa2",
         "EventName": "RESOURCE_STALLS.SCOREBOARD",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "100003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x5e",
         "EventName": "RS_EVENTS.EMPTY_CYCLES",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)",
         "SampleAfterValue": "1000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x5e",
         "EventName": "RS_EVENTS.EMPTY_END",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa4",
         "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's  slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
         "SampleAfterValue": "10000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa4",
         "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.",
         "SampleAfterValue": "10000003",
         "UMask": "0x8"
     },
     {
         "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
-        "CollectPEBSRecord": "2",
-        "Counter": "Fixed counter 3",
         "EventName": "TOPDOWN.SLOTS",
-        "PEBScounters": "35",
         "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
         "SampleAfterValue": "10000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa4",
         "EventName": "TOPDOWN.SLOTS_P",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
         "SampleAfterValue": "10000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x56",
         "EventName": "UOPS_DECODED.DEC0",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Uops exclusively fetched by decoder 0",
         "SampleAfterValue": "1000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of uops executed on port 0",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa1",
         "EventName": "UOPS_DISPATCHED.PORT_0",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Number of uops executed on port 1",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa1",
         "EventName": "UOPS_DISPATCHED.PORT_1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of uops executed on port 2 and 3",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa1",
         "EventName": "UOPS_DISPATCHED.PORT_2_3",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3.",
         "SampleAfterValue": "2000003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Number of uops executed on port 4 and 9",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa1",
         "EventName": "UOPS_DISPATCHED.PORT_4_9",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9.",
         "SampleAfterValue": "2000003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Number of uops executed on port 5",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa1",
         "EventName": "UOPS_DISPATCHED.PORT_5",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.",
         "SampleAfterValue": "2000003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Number of uops executed on port 6",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa1",
         "EventName": "UOPS_DISPATCHED.PORT_6",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
         "SampleAfterValue": "2000003",
         "UMask": "0x40"
     },
     {
         "BriefDescription": "Number of uops executed on port 7 and 8",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xa1",
         "EventName": "UOPS_DISPATCHED.PORT_7_8",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8.",
         "SampleAfterValue": "2000003",
         "UMask": "0x80"
     },
     {
         "BriefDescription": "Number of uops executed on the core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of uops executed from any thread.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "2",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_2",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "3",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_3",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "4",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.CYCLES_GE_4",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.STALL_CYCLES",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.THREAD",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Counts the number of x87 uops dispatched.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xb1",
         "EventName": "UOPS_EXECUTED.X87",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of x87 uops executed.",
         "SampleAfterValue": "2000003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Uops that RAT issues to RS",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0e",
         "EventName": "UOPS_ISSUED.ANY",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
         "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Cycles when RAT does not issue Uops to RS for the thread",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0x0e",
         "EventName": "UOPS_ISSUED.STALL_CYCLES",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.",
         "SampleAfterValue": "1000003",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x0e",
         "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.",
         "SampleAfterValue": "100003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Retirement slots used.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.SLOTS",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "Counts the retirement slots used each cycle.",
         "SampleAfterValue": "2000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles without actually retired uops.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "1",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.STALL_CYCLES",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
         "PublicDescription": "This event counts cycles without actually retired uops.",
         "SampleAfterValue": "1000003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Cycles with less than 10 actually retired uops.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3,4,5,6,7",
         "CounterMask": "10",
         "EventCode": "0xc2",
         "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
         "Invert": "1",
-        "PEBScounters": "0,1,2,3,4,5,6,7",
-        "PublicDescription": "Counts the number of cycles using always true condition (uops_ret &amp;lt; 16) applied to non PEBS uops retired event.",
+        "PublicDescription": "Counts the number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.",
         "SampleAfterValue": "1000003",
         "UMask": "0x2"
     }
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json b/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json
index 79b8b101b68fc..7e22a91271565 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json
@@ -41,7 +41,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage",
-        "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
+        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
         "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group",
         "MetricName": "tma_mispredicts_resteers",
         "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage.  Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
@@ -49,7 +49,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears",
-        "MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT))) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
+        "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
         "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group",
         "MetricName": "tma_clears_resteers",
         "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears.  Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
@@ -143,7 +143,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
-        "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
+        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
         "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
         "MetricName": "tma_branch_mispredicts",
         "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
@@ -159,7 +159,7 @@
     },
     {
         "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
-        "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + (5 * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=1\\,edge@) / SLOTS",
+        "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=1\\,edge@ / SLOTS",
         "MetricGroup": "TopdownL1;tma_L1_group",
         "MetricName": "tma_backend_bound",
         "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS",
@@ -167,7 +167,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
-        "MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * tma_backend_bound",
+        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound",
         "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
         "MetricName": "tma_memory_bound",
         "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@@ -213,7 +213,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
-        "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
+        "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
         "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
         "MetricName": "tma_lock_latency",
         "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS",
@@ -245,7 +245,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
-        "MetricExpr": "((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / ((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + L1D_PEND_MISS.FB_FULL_PERIODS)) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS)",
+        "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS)",
         "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_l2_bound",
         "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads.  Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS",
@@ -261,7 +261,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
-        "MetricExpr": "((49 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + (48 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+        "MetricExpr": "(49 * Average_Frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 48 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
         "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_contested_accesses",
         "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
@@ -269,7 +269,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
-        "MetricExpr": "(48 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD)))) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+        "MetricExpr": "48 * Average_Frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
         "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_data_sharing",
         "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
@@ -277,7 +277,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
-        "MetricExpr": "(17.5 * Average_Frequency) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+        "MetricExpr": "17.5 * Average_Frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
         "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_l3_hit_latency",
         "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
@@ -293,7 +293,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
-        "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS) - tma_l2_bound)",
+        "MetricExpr": "CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS - tma_l2_bound",
         "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_dram_bound",
         "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS",
@@ -325,7 +325,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
-        "MetricExpr": "((L2_RQSTS.RFO_HIT * 10 * (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES))) + (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
+        "MetricExpr": "(L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
         "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
         "MetricName": "tma_store_latency",
         "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
@@ -333,7 +333,7 @@
     },
     {
         "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
-        "MetricExpr": "(54 * Average_Frequency) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
+        "MetricExpr": "54 * Average_Frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
         "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
         "MetricName": "tma_false_sharing",
         "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line.  Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
@@ -395,7 +395,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
-        "MetricExpr": "(cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if (ARITH.DIVIDER_ACTIVE < (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY)) else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CLKS",
+        "MetricExpr": "((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CLKS)",
         "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
         "MetricName": "tma_ports_utilization",
         "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@@ -508,7 +508,7 @@
     },
     {
         "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
-        "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
+        "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS",
         "MetricGroup": "TopdownL1;tma_L1_group",
         "MetricName": "tma_retiring",
         "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided.  Sample with: UOPS_RETIRED.SLOTS",
@@ -625,7 +625,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
-        "MetricExpr": "((tma_retiring * SLOTS) / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
+        "MetricExpr": "tma_retiring * SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
         "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
         "MetricName": "tma_microcode_sequencer",
         "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
@@ -655,19 +655,19 @@
     },
     {
         "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) ",
+        "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))",
         "MetricGroup": "Mem;MemoryBW;Offcore",
         "MetricName": "Memory_Bandwidth"
     },
     {
         "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + (tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)))",
+        "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound))",
         "MetricGroup": "Mem;MemoryLat;Offcore",
         "MetricName": "Memory_Latency"
     },
     {
         "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) ",
+        "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))",
         "MetricGroup": "Mem;MemoryTLB;Offcore",
         "MetricName": "Memory_Data_TLBs"
     },
@@ -697,13 +697,13 @@
     },
     {
         "BriefDescription": "Uops Per Instruction",
-        "MetricExpr": "(tma_retiring * SLOTS) / INST_RETIRED.ANY",
+        "MetricExpr": "tma_retiring * SLOTS / INST_RETIRED.ANY",
         "MetricGroup": "Pipeline;Ret;Retire",
         "MetricName": "UPI"
     },
     {
         "BriefDescription": "Instruction per taken branch",
-        "MetricExpr": "(tma_retiring * SLOTS) / BR_INST_RETIRED.NEAR_TAKEN",
+        "MetricExpr": "tma_retiring * SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
         "MetricGroup": "Branches;Fed;FetchBW",
         "MetricName": "UpTB"
     },
@@ -727,7 +727,7 @@
     },
     {
         "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
-        "MetricExpr": "SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1",
+        "MetricExpr": "(SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)",
         "MetricGroup": "SMT;tma_L1_group",
         "MetricName": "Slots_Utilization"
     },
@@ -746,26 +746,26 @@
     },
     {
         "BriefDescription": "Floating Point Operations Per Cycle",
-        "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS",
         "MetricGroup": "Flops;Ret",
         "MetricName": "FLOPc"
     },
     {
         "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
-        "MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
         "MetricGroup": "Cor;Flops;HPC",
         "MetricName": "FP_Arith_Utilization",
         "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
     },
     {
         "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / ((UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
         "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
         "MetricName": "ILP"
     },
     {
         "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
-        "MetricExpr": "(1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0",
+        "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)",
         "MetricGroup": "Cor;SMT",
         "MetricName": "Core_Bound_Likely"
     },
@@ -813,13 +813,13 @@
     },
     {
         "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
         "MetricGroup": "Flops;InsType",
         "MetricName": "IpFLOP"
     },
     {
         "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))",
         "MetricGroup": "Flops;InsType",
         "MetricName": "IpArith",
         "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
@@ -873,7 +873,7 @@
     },
     {
         "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
-        "MetricExpr": "(tma_retiring * SLOTS) / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
+        "MetricExpr": "tma_retiring * SLOTS / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
         "MetricGroup": "Pipeline;Ret",
         "MetricName": "Retire"
     },
@@ -927,7 +927,7 @@
     },
     {
         "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
-        "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
+        "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
         "MetricGroup": "Bad;BrMispredicts",
         "MetricName": "Branch_Misprediction_Cost"
     },
@@ -975,55 +975,55 @@
     },
     {
         "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L1MPKI"
     },
     {
         "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L1MPKI_Load"
     },
     {
         "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
         "MetricGroup": "Backend;CacheMisses;Mem",
         "MetricName": "L2MPKI"
     },
     {
         "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem;Offcore",
         "MetricName": "L2MPKI_All"
     },
     {
         "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L2MPKI_Load"
     },
     {
         "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
-        "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L2HPKI_All"
     },
     {
         "BriefDescription": "L2 cache hits per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L2HPKI_Load"
     },
     {
         "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L3MPKI"
     },
     {
         "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "FB_HPKI"
     },
@@ -1036,25 +1036,25 @@
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
-        "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
+        "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L1D_Cache_Fill_BW"
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
-        "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
+        "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L2_Cache_Fill_BW"
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
+        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L3_Cache_Fill_BW"
     },
     {
         "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time",
+        "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW;Offcore",
         "MetricName": "L3_Cache_Access_BW"
     },
@@ -1084,19 +1084,19 @@
     },
     {
         "BriefDescription": "Average CPU Utilization",
-        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
+        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
         "MetricGroup": "HPC;Summary",
         "MetricName": "CPU_Utilization"
     },
     {
         "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
-        "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
+        "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
         "MetricGroup": "Power;Summary",
         "MetricName": "Average_Frequency"
     },
     {
         "BriefDescription": "Giga Floating Point Operations Per Second",
-        "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1000000000) / duration_time",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time",
         "MetricGroup": "Cor;Flops;HPC",
         "MetricName": "GFLOPs",
         "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
@@ -1130,7 +1130,7 @@
     },
     {
         "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
-        "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0",
+        "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)",
         "MetricGroup": "SMT",
         "MetricName": "SMT_2T_Utilization"
     },
@@ -1148,7 +1148,7 @@
     },
     {
         "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
-        "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1000000 / duration_time / 1000",
+        "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1e6 / duration_time / 1e3",
         "MetricGroup": "HPC;Mem;MemoryBW;SoC",
         "MetricName": "DRAM_BW_Use"
     },
@@ -1166,56 +1166,65 @@
     },
     {
         "BriefDescription": "C6 residency percent per core",
-        "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C6_Core_Residency"
+        "MetricName": "C6_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C7 residency percent per core",
-        "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C7_Core_Residency"
+        "MetricName": "C7_Core_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C2 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C2_Pkg_Residency"
+        "MetricName": "C2_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C3 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C3_Pkg_Residency"
+        "MetricName": "C3_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C6 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C6_Pkg_Residency"
+        "MetricName": "C6_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C7 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C7_Pkg_Residency"
+        "MetricName": "C7_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C8 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c8\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C8_Pkg_Residency"
+        "MetricName": "C8_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C9 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c9\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C9_Pkg_Residency"
+        "MetricName": "C9_Pkg_Residency",
+        "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "C10 residency percent per package",
-        "MetricExpr": "(cstate_pkg@c10\\-residency@ / msr@tsc@) * 100",
+        "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC",
         "MetricGroup": "Power",
-        "MetricName": "C10_Pkg_Residency"
+        "MetricName": "C10_Pkg_Residency",
+        "ScaleUnit": "100%"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json
index 734b1845c8e2c..e2ea5ccfe3bcb 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json
@@ -1,65 +1,109 @@
 [
+    {
+        "BriefDescription": "UNC_ARB_COH_TRK_REQUESTS.ALL",
+        "EventCode": "0x84",
+        "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "ARB"
+    },
+    {
+        "BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core.",
+        "EventCode": "0x85",
+        "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "ARB"
+    },
+    {
+        "BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core.",
+        "EventCode": "0x85",
+        "EventName": "UNC_ARB_DAT_OCCUPANCY.RD",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "ARB"
+    },
+    {
+        "BriefDescription": "Number of coherent read requests sent to memory controller that were issued by any core.",
+        "EventCode": "0x81",
+        "EventName": "UNC_ARB_DAT_REQUESTS.RD",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "ARB"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL",
+        "EventCode": "0x85",
+        "EventName": "UNC_ARB_IFA_OCCUPANCY.ALL",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "ARB"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_REQUESTS.RD",
+        "EventCode": "0x81",
+        "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD",
+        "PerPkg": "1",
+        "UMask": "0x2",
+        "Unit": "ARB"
+    },
     {
         "BriefDescription": "Each cycle count number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from it's allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.",
-        "CounterType": "PGMABLE",
         "EventCode": "0x80",
         "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
         "PerPkg": "1",
-        "PublicDescription": "UNC_ARB_TRK_OCCUPANCY.ALL",
-        "UMask": "0x01",
+        "UMask": "0x1",
         "Unit": "ARB"
     },
+    {
+        "BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL",
+        "EventCode": "0x81",
+        "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
+        "PerPkg": "1",
+        "UMask": "0x1",
+        "Unit": "ARB"
+    },
+    {
+        "BriefDescription": "UNC_CLOCK.SOCKET",
+        "EventCode": "0xff",
+        "EventName": "UNC_CLOCK.SOCKET",
+        "PerPkg": "1",
+        "Unit": "CLOCK"
+    },
     {
         "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
-        "Counter": "1",
-        "CounterType": "FREERUN",
         "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
         "PerPkg": "1",
-        "PublicDescription": "UNC_MC0_RDCAS_COUNT_FREERUN",
-        "Unit": "h_imc"
+        "Unit": "imc"
     },
     {
         "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
-        "CounterType": "FREERUN",
         "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN",
         "PerPkg": "1",
-        "PublicDescription": "UNC_MC0_TOTAL_REQCOUNT_FREERUN",
-        "Unit": "h_imc"
+        "Unit": "imc"
     },
     {
         "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
-        "Counter": "2",
-        "CounterType": "FREERUN",
         "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
         "PerPkg": "1",
-        "PublicDescription": "UNC_MC0_WRCAS_COUNT_FREERUN",
-        "Unit": "h_imc"
+        "Unit": "imc"
     },
     {
         "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
-        "Counter": "4",
-        "CounterType": "FREERUN",
         "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
         "PerPkg": "1",
-        "PublicDescription": "UNC_MC1_RDCAS_COUNT_FREERUN",
-        "Unit": "h_imc"
+        "Unit": "imc"
     },
     {
         "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
-        "Counter": "3",
-        "CounterType": "FREERUN",
         "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN",
         "PerPkg": "1",
-        "PublicDescription": "UNC_MC1_TOTAL_REQCOUNT_FREERUN",
-        "Unit": "h_imc"
+        "Unit": "imc"
     },
     {
         "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
-        "Counter": "5",
-        "CounterType": "FREERUN",
         "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
         "PerPkg": "1",
-        "PublicDescription": "UNC_MC1_WRCAS_COUNT_FREERUN",
-        "Unit": "h_imc"
+        "Unit": "imc"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/virtual-memory.json b/tools/perf/pmu-events/arch/x86/tigerlake/virtual-memory.json
index fd364abf80025..adb2f6b3e77c5 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/virtual-memory.json
@@ -1,223 +1,163 @@
 [
     {
         "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
         "SampleAfterValue": "100003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.",
         "SampleAfterValue": "100003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
         "UMask": "0xe"
     },
     {
         "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x08",
         "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
         "SampleAfterValue": "100003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.STLB_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
         "SampleAfterValue": "100003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
         "SampleAfterValue": "100003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
         "UMask": "0xe"
     },
     {
         "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages.  The page walks can end with or without a page fault.",
         "SampleAfterValue": "100003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault.",
         "SampleAfterValue": "100003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.",
         "SampleAfterValue": "100003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.STLB_HIT",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).",
         "SampleAfterValue": "100003",
         "UMask": "0x20"
     },
     {
         "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_ACTIVE",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
         "SampleAfterValue": "100003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
         "UMask": "0xe"
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
         "UMask": "0x4"
     },
     {
         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
         "SampleAfterValue": "100003",
         "UMask": "0x2"
     },
     {
         "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_PENDING",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.",
         "SampleAfterValue": "100003",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "DTLB flush attempts of the thread-specific entries",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xbd",
         "EventName": "TLB_FLUSH.DTLB_THREAD",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
         "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "STLB flush attempts",
-        "CollectPEBSRecord": "2",
-        "Counter": "0,1,2,3",
         "EventCode": "0xbd",
         "EventName": "TLB_FLUSH.STLB_ANY",
-        "PEBScounters": "0,1,2,3",
         "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
         "SampleAfterValue": "100007",
         "UMask": "0x20"
-- 
GitLab


From 598020743153cb4db77f7a1a0edc476a76a1e50a Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:55:08 -0800
Subject: [PATCH 592/875] perf vendor events intel: Refresh westmereep-dp
 events

Update the westmereep-dp events using the new tooling from:

  https://github.com/intel/perfmon

The events are unchanged, unused json values are removed and the
version number bumped to v3 to match the perfmon mapfile.csv. This
increases consistency across the json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-22-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/pmu-events/arch/x86/mapfile.csv    |   2 +-
 .../arch/x86/westmereep-dp/cache.json         | 445 ------------------
 .../x86/westmereep-dp/floating-point.json     |  28 --
 .../arch/x86/westmereep-dp/frontend.json      |   3 -
 .../arch/x86/westmereep-dp/memory.json        | 137 ------
 .../arch/x86/westmereep-dp/other.json         |  22 -
 .../arch/x86/westmereep-dp/pipeline.json      | 129 +----
 .../x86/westmereep-dp/virtual-memory.json     |  21 -
 8 files changed, 6 insertions(+), 781 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index b9ed4eb0b9160..a515d9594ced2 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -27,7 +27,7 @@ GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v53,skylake,core
 GenuineIntel-6-55-[01234],v1.28,skylakex,core
 GenuineIntel-6-86,v1.20,snowridgex,core
 GenuineIntel-6-8[CD],v1.08,tigerlake,core
-GenuineIntel-6-2C,v2,westmereep-dp,core
+GenuineIntel-6-2C,v3,westmereep-dp,core
 GenuineIntel-6-25,v3,westmereep-sp,core
 GenuineIntel-6-2F,v3,westmereex,core
 AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json
index 37ed2742fec64..5c897da3cd6bc 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Cycles L1D locked",
-        "Counter": "0,1",
         "EventCode": "0x63",
         "EventName": "CACHE_LOCK_CYCLES.L1D",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Cycles L1D and L2 locked",
-        "Counter": "0,1",
         "EventCode": "0x63",
         "EventName": "CACHE_LOCK_CYCLES.L1D_L2",
         "SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "L1D cache lines replaced in M state",
-        "Counter": "0,1",
         "EventCode": "0x51",
         "EventName": "L1D.M_EVICT",
         "SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "L1D cache lines allocated in the M state",
-        "Counter": "0,1",
         "EventCode": "0x51",
         "EventName": "L1D.M_REPL",
         "SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "L1D snoop eviction of cache lines in M state",
-        "Counter": "0,1",
         "EventCode": "0x51",
         "EventName": "L1D.M_SNOOP_EVICT",
         "SampleAfterValue": "2000000",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "L1 data cache lines allocated",
-        "Counter": "0,1",
         "EventCode": "0x51",
         "EventName": "L1D.REPL",
         "SampleAfterValue": "2000000",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "L1D prefetch load lock accepted in fill buffer",
-        "Counter": "0,1",
         "EventCode": "0x52",
         "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
         "SampleAfterValue": "2000000",
@@ -57,7 +50,6 @@
     },
     {
         "BriefDescription": "L1D hardware prefetch misses",
-        "Counter": "0,1",
         "EventCode": "0x4E",
         "EventName": "L1D_PREFETCH.MISS",
         "SampleAfterValue": "200000",
@@ -65,7 +57,6 @@
     },
     {
         "BriefDescription": "L1D hardware prefetch requests",
-        "Counter": "0,1",
         "EventCode": "0x4E",
         "EventName": "L1D_PREFETCH.REQUESTS",
         "SampleAfterValue": "200000",
@@ -73,7 +64,6 @@
     },
     {
         "BriefDescription": "L1D hardware prefetch requests triggered",
-        "Counter": "0,1",
         "EventCode": "0x4E",
         "EventName": "L1D_PREFETCH.TRIGGERS",
         "SampleAfterValue": "200000",
@@ -81,7 +71,6 @@
     },
     {
         "BriefDescription": "L1 writebacks to L2 in E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.E_STATE",
         "SampleAfterValue": "100000",
@@ -89,7 +78,6 @@
     },
     {
         "BriefDescription": "L1 writebacks to L2 in I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.I_STATE",
         "SampleAfterValue": "100000",
@@ -97,7 +85,6 @@
     },
     {
         "BriefDescription": "All L1 writebacks to L2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.MESI",
         "SampleAfterValue": "100000",
@@ -105,7 +92,6 @@
     },
     {
         "BriefDescription": "L1 writebacks to L2 in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.M_STATE",
         "SampleAfterValue": "100000",
@@ -113,7 +99,6 @@
     },
     {
         "BriefDescription": "L1 writebacks to L2 in S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.S_STATE",
         "SampleAfterValue": "100000",
@@ -121,7 +106,6 @@
     },
     {
         "BriefDescription": "All L2 data requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.ANY",
         "SampleAfterValue": "200000",
@@ -129,7 +113,6 @@
     },
     {
         "BriefDescription": "L2 data demand loads in E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
         "SampleAfterValue": "200000",
@@ -137,7 +120,6 @@
     },
     {
         "BriefDescription": "L2 data demand loads in I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
         "SampleAfterValue": "200000",
@@ -145,7 +127,6 @@
     },
     {
         "BriefDescription": "L2 data demand requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.MESI",
         "SampleAfterValue": "200000",
@@ -153,7 +134,6 @@
     },
     {
         "BriefDescription": "L2 data demand loads in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
         "SampleAfterValue": "200000",
@@ -161,7 +141,6 @@
     },
     {
         "BriefDescription": "L2 data demand loads in S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
         "SampleAfterValue": "200000",
@@ -169,7 +148,6 @@
     },
     {
         "BriefDescription": "L2 data prefetches in E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
         "SampleAfterValue": "200000",
@@ -177,7 +155,6 @@
     },
     {
         "BriefDescription": "L2 data prefetches in the I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
         "SampleAfterValue": "200000",
@@ -185,7 +162,6 @@
     },
     {
         "BriefDescription": "All L2 data prefetches",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
         "SampleAfterValue": "200000",
@@ -193,7 +169,6 @@
     },
     {
         "BriefDescription": "L2 data prefetches in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
         "SampleAfterValue": "200000",
@@ -201,7 +176,6 @@
     },
     {
         "BriefDescription": "L2 data prefetches in the S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
         "SampleAfterValue": "200000",
@@ -209,7 +183,6 @@
     },
     {
         "BriefDescription": "L2 lines alloacated",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.ANY",
         "SampleAfterValue": "100000",
@@ -217,7 +190,6 @@
     },
     {
         "BriefDescription": "L2 lines allocated in the E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.E_STATE",
         "SampleAfterValue": "100000",
@@ -225,7 +197,6 @@
     },
     {
         "BriefDescription": "L2 lines allocated in the S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.S_STATE",
         "SampleAfterValue": "100000",
@@ -233,7 +204,6 @@
     },
     {
         "BriefDescription": "L2 lines evicted",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.ANY",
         "SampleAfterValue": "100000",
@@ -241,7 +211,6 @@
     },
     {
         "BriefDescription": "L2 lines evicted by a demand request",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
         "SampleAfterValue": "100000",
@@ -249,7 +218,6 @@
     },
     {
         "BriefDescription": "L2 modified lines evicted by a demand request",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
         "SampleAfterValue": "100000",
@@ -257,7 +225,6 @@
     },
     {
         "BriefDescription": "L2 lines evicted by a prefetch request",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
         "SampleAfterValue": "100000",
@@ -265,7 +232,6 @@
     },
     {
         "BriefDescription": "L2 modified lines evicted by a prefetch request",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
         "SampleAfterValue": "100000",
@@ -273,7 +239,6 @@
     },
     {
         "BriefDescription": "L2 instruction fetches",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.IFETCHES",
         "SampleAfterValue": "200000",
@@ -281,7 +246,6 @@
     },
     {
         "BriefDescription": "L2 instruction fetch hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.IFETCH_HIT",
         "SampleAfterValue": "200000",
@@ -289,7 +253,6 @@
     },
     {
         "BriefDescription": "L2 instruction fetch misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.IFETCH_MISS",
         "SampleAfterValue": "200000",
@@ -297,7 +260,6 @@
     },
     {
         "BriefDescription": "L2 load hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.LD_HIT",
         "SampleAfterValue": "200000",
@@ -305,7 +267,6 @@
     },
     {
         "BriefDescription": "L2 load misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.LD_MISS",
         "SampleAfterValue": "200000",
@@ -313,7 +274,6 @@
     },
     {
         "BriefDescription": "L2 requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.LOADS",
         "SampleAfterValue": "200000",
@@ -321,7 +281,6 @@
     },
     {
         "BriefDescription": "All L2 misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.MISS",
         "SampleAfterValue": "200000",
@@ -329,7 +288,6 @@
     },
     {
         "BriefDescription": "All L2 prefetches",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PREFETCHES",
         "SampleAfterValue": "200000",
@@ -337,7 +295,6 @@
     },
     {
         "BriefDescription": "L2 prefetch hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PREFETCH_HIT",
         "SampleAfterValue": "200000",
@@ -345,7 +302,6 @@
     },
     {
         "BriefDescription": "L2 prefetch misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PREFETCH_MISS",
         "SampleAfterValue": "200000",
@@ -353,7 +309,6 @@
     },
     {
         "BriefDescription": "All L2 requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.REFERENCES",
         "SampleAfterValue": "200000",
@@ -361,7 +316,6 @@
     },
     {
         "BriefDescription": "L2 RFO requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFOS",
         "SampleAfterValue": "200000",
@@ -369,7 +323,6 @@
     },
     {
         "BriefDescription": "L2 RFO hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_HIT",
         "SampleAfterValue": "200000",
@@ -377,7 +330,6 @@
     },
     {
         "BriefDescription": "L2 RFO misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_MISS",
         "SampleAfterValue": "200000",
@@ -385,7 +337,6 @@
     },
     {
         "BriefDescription": "All L2 transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.ANY",
         "SampleAfterValue": "200000",
@@ -393,7 +344,6 @@
     },
     {
         "BriefDescription": "L2 fill transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.FILL",
         "SampleAfterValue": "200000",
@@ -401,7 +351,6 @@
     },
     {
         "BriefDescription": "L2 instruction fetch transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.IFETCH",
         "SampleAfterValue": "200000",
@@ -409,7 +358,6 @@
     },
     {
         "BriefDescription": "L1D writeback to L2 transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.L1D_WB",
         "SampleAfterValue": "200000",
@@ -417,7 +365,6 @@
     },
     {
         "BriefDescription": "L2 Load transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.LOAD",
         "SampleAfterValue": "200000",
@@ -425,7 +372,6 @@
     },
     {
         "BriefDescription": "L2 prefetch transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.PREFETCH",
         "SampleAfterValue": "200000",
@@ -433,7 +379,6 @@
     },
     {
         "BriefDescription": "L2 RFO transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.RFO",
         "SampleAfterValue": "200000",
@@ -441,7 +386,6 @@
     },
     {
         "BriefDescription": "L2 writeback to LLC transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.WB",
         "SampleAfterValue": "200000",
@@ -449,7 +393,6 @@
     },
     {
         "BriefDescription": "L2 demand lock RFOs in E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.E_STATE",
         "SampleAfterValue": "100000",
@@ -457,7 +400,6 @@
     },
     {
         "BriefDescription": "All demand L2 lock RFOs that hit the cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.HIT",
         "SampleAfterValue": "100000",
@@ -465,7 +407,6 @@
     },
     {
         "BriefDescription": "L2 demand lock RFOs in I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.I_STATE",
         "SampleAfterValue": "100000",
@@ -473,7 +414,6 @@
     },
     {
         "BriefDescription": "All demand L2 lock RFOs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.MESI",
         "SampleAfterValue": "100000",
@@ -481,7 +421,6 @@
     },
     {
         "BriefDescription": "L2 demand lock RFOs in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.M_STATE",
         "SampleAfterValue": "100000",
@@ -489,7 +428,6 @@
     },
     {
         "BriefDescription": "L2 demand lock RFOs in S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.S_STATE",
         "SampleAfterValue": "100000",
@@ -497,7 +435,6 @@
     },
     {
         "BriefDescription": "All L2 demand store RFOs that hit the cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.HIT",
         "SampleAfterValue": "100000",
@@ -505,7 +442,6 @@
     },
     {
         "BriefDescription": "L2 demand store RFOs in I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.I_STATE",
         "SampleAfterValue": "100000",
@@ -513,7 +449,6 @@
     },
     {
         "BriefDescription": "All L2 demand store RFOs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.MESI",
         "SampleAfterValue": "100000",
@@ -521,7 +456,6 @@
     },
     {
         "BriefDescription": "L2 demand store RFOs in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.M_STATE",
         "SampleAfterValue": "100000",
@@ -529,7 +463,6 @@
     },
     {
         "BriefDescription": "L2 demand store RFOs in S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.S_STATE",
         "SampleAfterValue": "100000",
@@ -537,7 +470,6 @@
     },
     {
         "BriefDescription": "Longest latency cache miss",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.MISS",
         "SampleAfterValue": "100000",
@@ -545,7 +477,6 @@
     },
     {
         "BriefDescription": "Longest latency cache reference",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
         "SampleAfterValue": "200000",
@@ -553,18 +484,15 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
         "MSRIndex": "0x3F6",
-        "MSRValue": "0x0",
         "PEBS": "2",
         "SampleAfterValue": "2000000",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
         "MSRIndex": "0x3F6",
@@ -575,7 +503,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
         "MSRIndex": "0x3F6",
@@ -586,7 +513,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
         "MSRIndex": "0x3F6",
@@ -597,7 +523,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
         "MSRIndex": "0x3F6",
@@ -608,7 +533,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
         "MSRIndex": "0x3F6",
@@ -619,7 +543,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
         "MSRIndex": "0x3F6",
@@ -630,7 +553,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
         "MSRIndex": "0x3F6",
@@ -641,7 +563,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
         "MSRIndex": "0x3F6",
@@ -652,7 +573,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
         "MSRIndex": "0x3F6",
@@ -663,7 +583,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
         "MSRIndex": "0x3F6",
@@ -674,7 +593,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
         "MSRIndex": "0x3F6",
@@ -685,7 +603,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
         "MSRIndex": "0x3F6",
@@ -696,7 +613,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
         "MSRIndex": "0x3F6",
@@ -707,7 +623,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
         "MSRIndex": "0x3F6",
@@ -718,7 +633,6 @@
     },
     {
         "BriefDescription": "Instructions retired which contains a load (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LOADS",
         "PEBS": "1",
@@ -727,7 +641,6 @@
     },
     {
         "BriefDescription": "Instructions retired which contains a store (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.STORES",
         "PEBS": "1",
@@ -736,7 +649,6 @@
     },
     {
         "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.HIT_LFB",
         "PEBS": "1",
@@ -745,7 +657,6 @@
     },
     {
         "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.L1D_HIT",
         "PEBS": "1",
@@ -754,7 +665,6 @@
     },
     {
         "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.L2_HIT",
         "PEBS": "1",
@@ -763,7 +673,6 @@
     },
     {
         "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.LLC_MISS",
         "PEBS": "1",
@@ -772,7 +681,6 @@
     },
     {
         "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
         "PEBS": "1",
@@ -781,7 +689,6 @@
     },
     {
         "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
         "PEBS": "1",
@@ -790,7 +697,6 @@
     },
     {
         "BriefDescription": "All offcore requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ANY",
         "SampleAfterValue": "100000",
@@ -798,7 +704,6 @@
     },
     {
         "BriefDescription": "Offcore read requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ANY.READ",
         "SampleAfterValue": "100000",
@@ -806,7 +711,6 @@
     },
     {
         "BriefDescription": "Offcore RFO requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ANY.RFO",
         "SampleAfterValue": "100000",
@@ -814,7 +718,6 @@
     },
     {
         "BriefDescription": "Offcore demand code read requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE",
         "SampleAfterValue": "100000",
@@ -822,7 +725,6 @@
     },
     {
         "BriefDescription": "Offcore demand data read requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA",
         "SampleAfterValue": "100000",
@@ -830,7 +732,6 @@
     },
     {
         "BriefDescription": "Offcore demand RFO requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND.RFO",
         "SampleAfterValue": "100000",
@@ -838,7 +739,6 @@
     },
     {
         "BriefDescription": "Offcore L1 data cache writebacks",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
         "SampleAfterValue": "100000",
@@ -906,7 +806,6 @@
     },
     {
         "BriefDescription": "Offcore requests blocked due to Super Queue full",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "OFFCORE_REQUESTS_SQ_FULL",
         "SampleAfterValue": "100000",
@@ -914,1877 +813,1536 @@
     },
     {
         "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7f11",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATION",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xff11",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIO",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_CORE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x111",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x211",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x411",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x711",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x811",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7f44",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATION",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xff44",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIO",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x144",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x244",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x444",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x744",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x844",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x50ff",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7fff",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATION",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xffff",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIO",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80ff",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_CORE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1ff",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2ff",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4ff",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7ff",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10ff",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8ff",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7f22",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_LOCATION",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xff22",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY RFO and RESPONSE = IO_CSR_MMIO",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x122",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x222",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x422",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_CACHE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x722",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x822",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7f08",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_LOCATION",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xff08",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = CORE_WB and RESPONSE = IO_CSR_MMIO",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_CORE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x108",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x208",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x408",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_CACHE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x708",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x808",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7f77",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATION",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xff77",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIO",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x177",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x277",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x477",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x777",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x877",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7f33",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_LOCATION",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xff33",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IN and RESPONSE = IO_CSR_MMIO",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_CORE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x133",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x233",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x433",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_CACHE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x733",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x833",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7f03",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATION",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xff03",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIO",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x203",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x403",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x703",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7f01",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATION",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xff01",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIO",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x101",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x201",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x401",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x701",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x801",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7f04",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATION",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xff04",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIO",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x704",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7f02",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATION",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xff02",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIO",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x102",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x202",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x402",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x702",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x802",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5080",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7f80",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_LOCATION",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xff80",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = OTHER and RESPONSE = IO_CSR_MMIO",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8080",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_CORE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x180",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x280",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x480",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_CACHE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x780",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1080",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x880",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5050",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7f50",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_LOCATION",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xff50",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIO",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8050",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x150",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x250",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x450",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_CACHE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x750",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1050",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x850",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7f10",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATION",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xff10",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIO",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x710",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7f40",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LOCATION",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xff40",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_RFO and RESPONSE = IO_CSR_MMIO",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x140",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x240",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x440",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_CACHE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x740",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x840",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7f20",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATION",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xff20",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIO",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x120",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x220",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x420",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x720",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x820",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7f70",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LOCATION",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xff70",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PREFETCH and RESPONSE = IO_CSR_MMIO",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x170",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x270",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x470",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_CACHE",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x770",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x870",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Super Queue LRU hints sent to LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF4",
         "EventName": "SQ_MISC.LRU_HINTS",
         "SampleAfterValue": "2000000",
@@ -2792,7 +2350,6 @@
     },
     {
         "BriefDescription": "Super Queue lock splits across a cache line",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF4",
         "EventName": "SQ_MISC.SPLIT_LOCK",
         "SampleAfterValue": "2000000",
@@ -2800,7 +2357,6 @@
     },
     {
         "BriefDescription": "Loads delayed with at-Retirement block code",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "STORE_BLOCKS.AT_RET",
         "SampleAfterValue": "200000",
@@ -2808,7 +2364,6 @@
     },
     {
         "BriefDescription": "Cacheable loads delayed with L1D block code",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "STORE_BLOCKS.L1D_BLOCK",
         "SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json
index 666e466d351c4..c03f8990fa82a 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "X87 Floating point assists (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF7",
         "EventName": "FP_ASSIST.ALL",
         "PEBS": "1",
@@ -10,7 +9,6 @@
     },
     {
         "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF7",
         "EventName": "FP_ASSIST.INPUT",
         "PEBS": "1",
@@ -19,7 +17,6 @@
     },
     {
         "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF7",
         "EventName": "FP_ASSIST.OUTPUT",
         "PEBS": "1",
@@ -28,7 +25,6 @@
     },
     {
         "BriefDescription": "MMX Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.MMX",
         "SampleAfterValue": "2000000",
@@ -36,7 +32,6 @@
     },
     {
         "BriefDescription": "SSE2 integer Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
         "SampleAfterValue": "2000000",
@@ -44,7 +39,6 @@
     },
     {
         "BriefDescription": "SSE* FP double precision Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
         "SampleAfterValue": "2000000",
@@ -52,7 +46,6 @@
     },
     {
         "BriefDescription": "SSE and SSE2 FP Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_FP",
         "SampleAfterValue": "2000000",
@@ -60,7 +53,6 @@
     },
     {
         "BriefDescription": "SSE FP packed Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
         "SampleAfterValue": "2000000",
@@ -68,7 +60,6 @@
     },
     {
         "BriefDescription": "SSE FP scalar Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
         "SampleAfterValue": "2000000",
@@ -76,7 +67,6 @@
     },
     {
         "BriefDescription": "SSE* FP single precision Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
         "SampleAfterValue": "2000000",
@@ -84,7 +74,6 @@
     },
     {
         "BriefDescription": "Computational floating-point operations executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.X87",
         "SampleAfterValue": "2000000",
@@ -92,7 +81,6 @@
     },
     {
         "BriefDescription": "All Floating Point to and from MMX transitions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCC",
         "EventName": "FP_MMX_TRANS.ANY",
         "SampleAfterValue": "2000000",
@@ -100,7 +88,6 @@
     },
     {
         "BriefDescription": "Transitions from MMX to Floating Point instructions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCC",
         "EventName": "FP_MMX_TRANS.TO_FP",
         "SampleAfterValue": "2000000",
@@ -108,7 +95,6 @@
     },
     {
         "BriefDescription": "Transitions from Floating Point to MMX instructions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCC",
         "EventName": "FP_MMX_TRANS.TO_MMX",
         "SampleAfterValue": "2000000",
@@ -116,7 +102,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer pack operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACK",
         "SampleAfterValue": "200000",
@@ -124,7 +109,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer arithmetic operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_ARITH",
         "SampleAfterValue": "200000",
@@ -132,7 +116,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer logical operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_LOGICAL",
         "SampleAfterValue": "200000",
@@ -140,7 +123,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer multiply operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_MPY",
         "SampleAfterValue": "200000",
@@ -148,7 +130,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer shift operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_SHIFT",
         "SampleAfterValue": "200000",
@@ -156,7 +137,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer shuffle/move operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.SHUFFLE_MOVE",
         "SampleAfterValue": "200000",
@@ -164,7 +144,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer unpack operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.UNPACK",
         "SampleAfterValue": "200000",
@@ -172,7 +151,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit pack operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACK",
         "SampleAfterValue": "200000",
@@ -180,7 +158,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit arithmetic operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_ARITH",
         "SampleAfterValue": "200000",
@@ -188,7 +165,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit logical operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_LOGICAL",
         "SampleAfterValue": "200000",
@@ -196,7 +172,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit packed multiply operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_MPY",
         "SampleAfterValue": "200000",
@@ -204,7 +179,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit shift operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_SHIFT",
         "SampleAfterValue": "200000",
@@ -212,7 +186,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit shuffle/move operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.SHUFFLE_MOVE",
         "SampleAfterValue": "200000",
@@ -220,7 +193,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit unpack operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.UNPACK",
         "SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json
index c561ac24d91d1..f7f28510e3ae9 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MACRO_INSTS.DECODED",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Macro-fused instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA6",
         "EventName": "MACRO_INSTS.FUSIONS_DECODED",
         "SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "Two Uop instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "TWO_UOP_INSTS_DECODED",
         "SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json
index 7e529b367c210..7085c3307c917 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Misaligned store references",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.STORE",
         "SampleAfterValue": "200000",
@@ -9,749 +8,613 @@
     },
     {
         "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_DRAM AND REMOTE_FWD",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM_AND_REMOTE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LLC_MISS",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xf811",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = OTHER_LOCAL_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.OTHER_LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM_AND_REMOTE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LLC_MISS",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xf844",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = OTHER_LOCAL_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.OTHER_LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_DRAM AND REMOTE_FWD",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM_AND_REMOTE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x30ff",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LLC_MISS",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xf8ff",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = OTHER_LOCAL_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OTHER_LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x40ff",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x20ff",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM_AND_REMOTE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_LLC_MISS",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xf822",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY RFO and RESPONSE = OTHER_LOCAL_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.OTHER_LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = ANY RFO and RESPONSE = REMOTE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_DRAM AND REMOTE_FWD",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM_AND_REMOTE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_LLC_MISS",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xf808",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = CORE_WB and RESPONSE = OTHER_LOCAL_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.OTHER_LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = CORE_WB and RESPONSE = REMOTE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM_AND_REMOTE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_LLC_MISS",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xf877",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = OTHER_LOCAL_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.OTHER_LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = REMOTE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_DRAM AND REMOTE_FWD",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM_AND_REMOTE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_LLC_MISS",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xf833",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IN and RESPONSE = OTHER_LOCAL_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.OTHER_LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DATA_IN and RESPONSE = REMOTE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM_AND_REMOTE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_LLC_MISS",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xf803",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = OTHER_LOCAL_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.OTHER_LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = REMOTE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM_AND_REMOTE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LLC_MISS",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xf801",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OTHER_LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM_AND_REMOTE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LLC_MISS",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xf804",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = OTHER_LOCAL_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.OTHER_LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM_AND_REMOTE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_LLC_MISS",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xf802",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = OTHER_LOCAL_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OTHER_LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = REMOTE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_DRAM AND REMOTE_FWD",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM_AND_REMOTE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3080",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_LLC_MISS",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xf880",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = OTHER and RESPONSE = OTHER_LOCAL_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.OTHER_LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4080",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = OTHER and RESPONSE = REMOTE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2080",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM_AND_REMOTE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3050",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_LLC_MISS",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xf850",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA and RESPONSE = OTHER_LOCAL_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.OTHER_LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4050",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2050",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM_AND_REMOTE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LLC_MISS",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xf810",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.OTHER_LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM_AND_REMOTE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LLC_MISS",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xf840",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_RFO and RESPONSE = OTHER_LOCAL_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.OTHER_LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM_AND_REMOTE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LLC_MISS",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xf820",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = OTHER_LOCAL_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.OTHER_LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM_AND_REMOTE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x3070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LLC_MISS",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xf870",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PREFETCH and RESPONSE = OTHER_LOCAL_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.OTHER_LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     }
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json
index 67bc34984fa80..4882749805646 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "ES segment renames",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD5",
         "EventName": "ES_REG_RENAMES",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "I/O transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6C",
         "EventName": "IO_TRANSACTIONS",
         "SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "L1I instruction fetch stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.CYCLES_STALLED",
         "SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "L1I instruction fetch hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.HITS",
         "SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "L1I instruction fetch misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.MISSES",
         "SampleAfterValue": "2000000",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "L1I Instruction fetches",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.READS",
         "SampleAfterValue": "2000000",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "Large ITLB hit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x82",
         "EventName": "LARGE_ITLB.HIT",
         "SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
     },
     {
         "BriefDescription": "Loads that partially overlap an earlier store",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "LOAD_BLOCK.OVERLAP_STORE",
         "SampleAfterValue": "200000",
@@ -65,7 +57,6 @@
     },
     {
         "BriefDescription": "All loads dispatched",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.ANY",
         "SampleAfterValue": "2000000",
@@ -73,7 +64,6 @@
     },
     {
         "BriefDescription": "Loads dispatched from the MOB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.MOB",
         "SampleAfterValue": "2000000",
@@ -81,7 +71,6 @@
     },
     {
         "BriefDescription": "Loads dispatched that bypass the MOB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.RS",
         "SampleAfterValue": "2000000",
@@ -89,7 +78,6 @@
     },
     {
         "BriefDescription": "Loads dispatched from stage 305",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.RS_DELAYED",
         "SampleAfterValue": "2000000",
@@ -97,7 +85,6 @@
     },
     {
         "BriefDescription": "False dependencies due to partial address aliasing",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "PARTIAL_ADDRESS_ALIAS",
         "SampleAfterValue": "200000",
@@ -105,7 +92,6 @@
     },
     {
         "BriefDescription": "All Store buffer stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "SB_DRAIN.ANY",
         "SampleAfterValue": "200000",
@@ -113,7 +99,6 @@
     },
     {
         "BriefDescription": "Segment rename stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD4",
         "EventName": "SEG_RENAME_STALLS",
         "SampleAfterValue": "2000000",
@@ -121,7 +106,6 @@
     },
     {
         "BriefDescription": "Snoop code requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "SNOOPQ_REQUESTS.CODE",
         "SampleAfterValue": "100000",
@@ -129,7 +113,6 @@
     },
     {
         "BriefDescription": "Snoop data requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "SNOOPQ_REQUESTS.DATA",
         "SampleAfterValue": "100000",
@@ -137,7 +120,6 @@
     },
     {
         "BriefDescription": "Snoop invalidate requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "SNOOPQ_REQUESTS.INVALIDATE",
         "SampleAfterValue": "100000",
@@ -190,7 +172,6 @@
     },
     {
         "BriefDescription": "Thread responded HIT to snoop",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "SNOOP_RESPONSE.HIT",
         "SampleAfterValue": "100000",
@@ -198,7 +179,6 @@
     },
     {
         "BriefDescription": "Thread responded HITE to snoop",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "SNOOP_RESPONSE.HITE",
         "SampleAfterValue": "100000",
@@ -206,7 +186,6 @@
     },
     {
         "BriefDescription": "Thread responded HITM to snoop",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "SNOOP_RESPONSE.HITM",
         "SampleAfterValue": "100000",
@@ -214,7 +193,6 @@
     },
     {
         "BriefDescription": "Super Queue full stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF6",
         "EventName": "SQ_FULL_STALL_CYCLES",
         "SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json
index 403fb2b87fc4d..a29ed35227794 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Cycles the divider is busy",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "ARITH.CYCLES_DIV_BUSY",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Divide Operations executed",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x14",
@@ -20,7 +18,6 @@
     },
     {
         "BriefDescription": "Multiply operations executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "ARITH.MUL",
         "SampleAfterValue": "2000000",
@@ -28,7 +25,6 @@
     },
     {
         "BriefDescription": "BACLEAR asserted with bad target address",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE6",
         "EventName": "BACLEAR.BAD_TARGET",
         "SampleAfterValue": "2000000",
@@ -36,7 +32,6 @@
     },
     {
         "BriefDescription": "BACLEAR asserted, regardless of cause",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE6",
         "EventName": "BACLEAR.CLEAR",
         "SampleAfterValue": "2000000",
@@ -44,7 +39,6 @@
     },
     {
         "BriefDescription": "Instruction queue forced BACLEAR",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA7",
         "EventName": "BACLEAR_FORCE_IQ",
         "SampleAfterValue": "2000000",
@@ -52,7 +46,6 @@
     },
     {
         "BriefDescription": "Early Branch Prediciton Unit clears",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE8",
         "EventName": "BPU_CLEARS.EARLY",
         "SampleAfterValue": "2000000",
@@ -60,7 +53,6 @@
     },
     {
         "BriefDescription": "Late Branch Prediction Unit clears",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE8",
         "EventName": "BPU_CLEARS.LATE",
         "SampleAfterValue": "2000000",
@@ -68,7 +60,6 @@
     },
     {
         "BriefDescription": "Branch prediction unit missed call or return",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE5",
         "EventName": "BPU_MISSED_CALL_RET",
         "SampleAfterValue": "2000000",
@@ -76,7 +67,6 @@
     },
     {
         "BriefDescription": "Branch instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE0",
         "EventName": "BR_INST_DECODED",
         "SampleAfterValue": "2000000",
@@ -84,7 +74,6 @@
     },
     {
         "BriefDescription": "Branch instructions executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ANY",
         "SampleAfterValue": "200000",
@@ -92,7 +81,6 @@
     },
     {
         "BriefDescription": "Conditional branch instructions executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.COND",
         "SampleAfterValue": "200000",
@@ -100,7 +88,6 @@
     },
     {
         "BriefDescription": "Unconditional branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.DIRECT",
         "SampleAfterValue": "200000",
@@ -108,7 +95,6 @@
     },
     {
         "BriefDescription": "Unconditional call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
         "SampleAfterValue": "20000",
@@ -116,7 +102,6 @@
     },
     {
         "BriefDescription": "Indirect call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
         "SampleAfterValue": "20000",
@@ -124,7 +109,6 @@
     },
     {
         "BriefDescription": "Indirect non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
         "SampleAfterValue": "20000",
@@ -132,7 +116,6 @@
     },
     {
         "BriefDescription": "Call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.NEAR_CALLS",
         "SampleAfterValue": "20000",
@@ -140,7 +123,6 @@
     },
     {
         "BriefDescription": "All non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.NON_CALLS",
         "SampleAfterValue": "200000",
@@ -148,7 +130,6 @@
     },
     {
         "BriefDescription": "Indirect return branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.RETURN_NEAR",
         "SampleAfterValue": "20000",
@@ -156,7 +137,6 @@
     },
     {
         "BriefDescription": "Taken branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN",
         "SampleAfterValue": "200000",
@@ -164,7 +144,6 @@
     },
     {
         "BriefDescription": "Retired branch instructions (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
@@ -173,7 +152,6 @@
     },
     {
         "BriefDescription": "Retired conditional branch instructions (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -182,7 +160,6 @@
     },
     {
         "BriefDescription": "Retired near call instructions (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -191,7 +168,6 @@
     },
     {
         "BriefDescription": "Mispredicted branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ANY",
         "SampleAfterValue": "20000",
@@ -199,7 +175,6 @@
     },
     {
         "BriefDescription": "Mispredicted conditional branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.COND",
         "SampleAfterValue": "20000",
@@ -207,7 +182,6 @@
     },
     {
         "BriefDescription": "Mispredicted unconditional branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.DIRECT",
         "SampleAfterValue": "20000",
@@ -215,7 +189,6 @@
     },
     {
         "BriefDescription": "Mispredicted non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
         "SampleAfterValue": "2000",
@@ -223,7 +196,6 @@
     },
     {
         "BriefDescription": "Mispredicted indirect call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
         "SampleAfterValue": "2000",
@@ -231,7 +203,6 @@
     },
     {
         "BriefDescription": "Mispredicted indirect non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
         "SampleAfterValue": "2000",
@@ -239,7 +210,6 @@
     },
     {
         "BriefDescription": "Mispredicted call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.NEAR_CALLS",
         "SampleAfterValue": "2000",
@@ -247,7 +217,6 @@
     },
     {
         "BriefDescription": "Mispredicted non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.NON_CALLS",
         "SampleAfterValue": "20000",
@@ -255,7 +224,6 @@
     },
     {
         "BriefDescription": "Mispredicted return branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.RETURN_NEAR",
         "SampleAfterValue": "2000",
@@ -263,7 +231,6 @@
     },
     {
         "BriefDescription": "Mispredicted taken branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN",
         "SampleAfterValue": "20000",
@@ -271,7 +238,6 @@
     },
     {
         "BriefDescription": "Mispredicted retired branch instructions (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
@@ -280,7 +246,6 @@
     },
     {
         "BriefDescription": "Mispredicted conditional retired branches (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -289,7 +254,6 @@
     },
     {
         "BriefDescription": "Mispredicted near retired calls (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -298,15 +262,11 @@
     },
     {
         "BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
-        "Counter": "Fixed counter 3",
-        "EventCode": "0x0",
         "EventName": "CPU_CLK_UNHALTED.REF",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_P",
         "SampleAfterValue": "100000",
@@ -314,33 +274,25 @@
     },
     {
         "BriefDescription": "Cycles when thread is not halted (fixed counter)",
-        "Counter": "Fixed counter 2",
-        "EventCode": "0x0",
         "EventName": "CPU_CLK_UNHALTED.THREAD",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Cycles when thread is not halted (programmable counter)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Total CPU cycles",
-        "Counter": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
         "Invert": "1",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Any Instruction Length Decoder stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.ANY",
         "SampleAfterValue": "2000000",
@@ -348,7 +300,6 @@
     },
     {
         "BriefDescription": "Instruction Queue full stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.IQ_FULL",
         "SampleAfterValue": "2000000",
@@ -356,7 +307,6 @@
     },
     {
         "BriefDescription": "Length Change Prefix stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.LCP",
         "SampleAfterValue": "2000000",
@@ -364,7 +314,6 @@
     },
     {
         "BriefDescription": "Stall cycles due to BPU MRU bypass",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.MRU",
         "SampleAfterValue": "2000000",
@@ -372,7 +321,6 @@
     },
     {
         "BriefDescription": "Regen stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.REGEN",
         "SampleAfterValue": "2000000",
@@ -380,7 +328,6 @@
     },
     {
         "BriefDescription": "Instructions that must be decoded by decoder 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "INST_DECODED.DEC0",
         "SampleAfterValue": "2000000",
@@ -388,7 +335,6 @@
     },
     {
         "BriefDescription": "Instructions written to instruction queue.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x17",
         "EventName": "INST_QUEUE_WRITES",
         "SampleAfterValue": "2000000",
@@ -396,7 +342,6 @@
     },
     {
         "BriefDescription": "Cycles instructions are written to the instruction queue",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
         "EventName": "INST_QUEUE_WRITE_CYCLES",
         "SampleAfterValue": "2000000",
@@ -404,15 +349,11 @@
     },
     {
         "BriefDescription": "Instructions retired (fixed counter)",
-        "Counter": "Fixed counter 1",
-        "EventCode": "0x0",
         "EventName": "INST_RETIRED.ANY",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.ANY_P",
         "PEBS": "1",
@@ -421,7 +362,6 @@
     },
     {
         "BriefDescription": "Retired MMX instructions (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.MMX",
         "PEBS": "1",
@@ -430,7 +370,6 @@
     },
     {
         "BriefDescription": "Total cycles (Precise Event)",
-        "Counter": "0,1,2,3",
         "CounterMask": "16",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.TOTAL_CYCLES",
@@ -441,7 +380,6 @@
     },
     {
         "BriefDescription": "Total cycles (Precise Event)",
-        "Counter": "0,1,2,3",
         "CounterMask": "16",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
@@ -452,7 +390,6 @@
     },
     {
         "BriefDescription": "Retired floating-point operations (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.X87",
         "PEBS": "1",
@@ -461,7 +398,6 @@
     },
     {
         "BriefDescription": "Load operations conflicting with software prefetches",
-        "Counter": "0,1",
         "EventCode": "0x4C",
         "EventName": "LOAD_HIT_PRE",
         "SampleAfterValue": "200000",
@@ -469,7 +405,6 @@
     },
     {
         "BriefDescription": "Cycles when uops were delivered by the LSD",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.ACTIVE",
@@ -478,7 +413,6 @@
     },
     {
         "BriefDescription": "Cycles no uops were delivered by the LSD",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.INACTIVE",
@@ -488,7 +422,6 @@
     },
     {
         "BriefDescription": "Loops that can't stream from the instruction queue",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "LSD_OVERFLOW",
         "SampleAfterValue": "2000000",
@@ -496,7 +429,6 @@
     },
     {
         "BriefDescription": "Cycles machine clear asserted",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.CYCLES",
         "SampleAfterValue": "20000",
@@ -504,7 +436,6 @@
     },
     {
         "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MEM_ORDER",
         "SampleAfterValue": "20000",
@@ -512,7 +443,6 @@
     },
     {
         "BriefDescription": "Self-Modifying Code detected",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.SMC",
         "SampleAfterValue": "20000",
@@ -520,7 +450,6 @@
     },
     {
         "BriefDescription": "All RAT stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.ANY",
         "SampleAfterValue": "2000000",
@@ -528,7 +457,6 @@
     },
     {
         "BriefDescription": "Flag stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.FLAGS",
         "SampleAfterValue": "2000000",
@@ -536,7 +464,6 @@
     },
     {
         "BriefDescription": "Partial register stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.REGISTERS",
         "SampleAfterValue": "2000000",
@@ -544,7 +471,6 @@
     },
     {
         "BriefDescription": "ROB read port stalls cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.ROB_READ_PORT",
         "SampleAfterValue": "2000000",
@@ -552,7 +478,6 @@
     },
     {
         "BriefDescription": "Scoreboard stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.SCOREBOARD",
         "SampleAfterValue": "2000000",
@@ -560,7 +485,6 @@
     },
     {
         "BriefDescription": "Resource related stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ANY",
         "SampleAfterValue": "2000000",
@@ -568,7 +492,6 @@
     },
     {
         "BriefDescription": "FPU control word write stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.FPCW",
         "SampleAfterValue": "2000000",
@@ -576,7 +499,6 @@
     },
     {
         "BriefDescription": "Load buffer stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.LOAD",
         "SampleAfterValue": "2000000",
@@ -584,7 +506,6 @@
     },
     {
         "BriefDescription": "MXCSR rename stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.MXCSR",
         "SampleAfterValue": "2000000",
@@ -592,7 +513,6 @@
     },
     {
         "BriefDescription": "Other Resource related stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.OTHER",
         "SampleAfterValue": "2000000",
@@ -600,7 +520,6 @@
     },
     {
         "BriefDescription": "ROB full stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ROB_FULL",
         "SampleAfterValue": "2000000",
@@ -608,7 +527,6 @@
     },
     {
         "BriefDescription": "Reservation Station full stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.RS_FULL",
         "SampleAfterValue": "2000000",
@@ -616,7 +534,6 @@
     },
     {
         "BriefDescription": "Store buffer stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.STORE",
         "SampleAfterValue": "2000000",
@@ -624,7 +541,6 @@
     },
     {
         "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
         "PEBS": "1",
@@ -633,7 +549,6 @@
     },
     {
         "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
         "PEBS": "1",
@@ -642,7 +557,6 @@
     },
     {
         "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
         "PEBS": "1",
@@ -651,7 +565,6 @@
     },
     {
         "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
         "PEBS": "1",
@@ -660,7 +573,6 @@
     },
     {
         "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
         "PEBS": "1",
@@ -669,7 +581,6 @@
     },
     {
         "BriefDescription": "Stack pointer instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "UOPS_DECODED.ESP_FOLDING",
         "SampleAfterValue": "2000000",
@@ -677,7 +588,6 @@
     },
     {
         "BriefDescription": "Stack pointer sync operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "UOPS_DECODED.ESP_SYNC",
         "SampleAfterValue": "2000000",
@@ -685,7 +595,6 @@
     },
     {
         "BriefDescription": "Uops decoded by Microcode Sequencer",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xD1",
         "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
@@ -694,7 +603,6 @@
     },
     {
         "BriefDescription": "Cycles no Uops are decoded",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xD1",
         "EventName": "UOPS_DECODED.STALL_CYCLES",
@@ -705,7 +613,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles Uops executed on any port (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
@@ -715,7 +622,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
@@ -725,7 +631,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops executed on any port (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xB1",
@@ -737,7 +642,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops executed on ports 0-4 (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xB1",
@@ -749,7 +653,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles no Uops issued on any port (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
@@ -760,7 +663,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
@@ -770,7 +672,6 @@
     },
     {
         "BriefDescription": "Uops executed on port 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT0",
         "SampleAfterValue": "2000000",
@@ -778,7 +679,6 @@
     },
     {
         "BriefDescription": "Uops issued on ports 0, 1 or 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT015",
         "SampleAfterValue": "2000000",
@@ -786,7 +686,6 @@
     },
     {
         "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
@@ -796,7 +695,6 @@
     },
     {
         "BriefDescription": "Uops executed on port 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT1",
         "SampleAfterValue": "2000000",
@@ -805,7 +703,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops issued on ports 2, 3 or 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT234_CORE",
         "SampleAfterValue": "2000000",
@@ -814,7 +711,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops executed on port 2 (core count)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT2_CORE",
         "SampleAfterValue": "2000000",
@@ -823,7 +719,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops executed on port 3 (core count)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT3_CORE",
         "SampleAfterValue": "2000000",
@@ -832,7 +727,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops executed on port 4 (core count)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT4_CORE",
         "SampleAfterValue": "2000000",
@@ -840,7 +734,6 @@
     },
     {
         "BriefDescription": "Uops executed on port 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT5",
         "SampleAfterValue": "2000000",
@@ -848,7 +741,6 @@
     },
     {
         "BriefDescription": "Uops issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.ANY",
         "SampleAfterValue": "2000000",
@@ -857,7 +749,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles no Uops were issued on any thread",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -868,7 +759,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles Uops were issued on either thread",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
@@ -877,7 +767,6 @@
     },
     {
         "BriefDescription": "Fused Uops issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.FUSED",
         "SampleAfterValue": "2000000",
@@ -885,7 +774,6 @@
     },
     {
         "BriefDescription": "Cycles no Uops were issued",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -895,7 +783,6 @@
     },
     {
         "BriefDescription": "Cycles Uops are being retired",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
@@ -905,7 +792,6 @@
     },
     {
         "BriefDescription": "Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ANY",
         "PEBS": "1",
@@ -914,7 +800,6 @@
     },
     {
         "BriefDescription": "Macro-fused Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.MACRO_FUSED",
         "PEBS": "1",
@@ -923,7 +808,6 @@
     },
     {
         "BriefDescription": "Retirement slots used (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
         "PEBS": "1",
@@ -932,7 +816,6 @@
     },
     {
         "BriefDescription": "Cycles Uops are not retiring (Precise Event)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -943,7 +826,6 @@
     },
     {
         "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
-        "Counter": "0,1,2,3",
         "CounterMask": "16",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
@@ -954,7 +836,6 @@
     },
     {
         "BriefDescription": "Uop unfusions due to FP exceptions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xDB",
         "EventName": "UOP_UNFUSION",
         "SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json
index 8099e6700e316..ef635bff1522a 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "DTLB load misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.ANY",
         "SampleAfterValue": "200000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "DTLB load miss large page walks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "DTLB load miss caused by low part of address",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.PDE_MISS",
         "SampleAfterValue": "200000",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "DTLB second level hit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
         "SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "DTLB load miss page walks complete",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "DTLB load miss page walk cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",
         "SampleAfterValue": "200000",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "DTLB misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.ANY",
         "SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
     },
     {
         "BriefDescription": "DTLB miss large page walks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -65,7 +57,6 @@
     },
     {
         "BriefDescription": "DTLB misses casued by low part of address",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.PDE_MISS",
         "SampleAfterValue": "200000",
@@ -73,7 +64,6 @@
     },
     {
         "BriefDescription": "DTLB first level misses but second level hit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.STLB_HIT",
         "SampleAfterValue": "200000",
@@ -81,7 +71,6 @@
     },
     {
         "BriefDescription": "DTLB miss page walks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -89,7 +78,6 @@
     },
     {
         "BriefDescription": "DTLB miss page walk cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.WALK_CYCLES",
         "SampleAfterValue": "2000000",
@@ -97,7 +85,6 @@
     },
     {
         "BriefDescription": "Extended Page Table walk cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4F",
         "EventName": "EPT.WALK_CYCLES",
         "SampleAfterValue": "2000000",
@@ -105,7 +92,6 @@
     },
     {
         "BriefDescription": "ITLB flushes",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAE",
         "EventName": "ITLB_FLUSH",
         "SampleAfterValue": "2000000",
@@ -113,7 +99,6 @@
     },
     {
         "BriefDescription": "ITLB miss",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.ANY",
         "SampleAfterValue": "200000",
@@ -121,7 +106,6 @@
     },
     {
         "BriefDescription": "ITLB miss large page walks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -129,7 +113,6 @@
     },
     {
         "BriefDescription": "ITLB miss page walks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -137,7 +120,6 @@
     },
     {
         "BriefDescription": "ITLB miss page walk cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_CYCLES",
         "SampleAfterValue": "2000000",
@@ -145,7 +127,6 @@
     },
     {
         "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC8",
         "EventName": "ITLB_MISS_RETIRED",
         "PEBS": "1",
@@ -154,7 +135,6 @@
     },
     {
         "BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
         "PEBS": "1",
@@ -163,7 +143,6 @@
     },
     {
         "BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC",
         "EventName": "MEM_STORE_RETIRED.DTLB_MISS",
         "PEBS": "1",
-- 
GitLab


From bcea0838b9dbf70df424d4665feedad95be86d13 Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:55:09 -0800
Subject: [PATCH 593/875] perf vendor events intel: Refresh westmereep-sp
 events

Update the westmereep-sp events using the new tooling from:

  https://github.com/intel/perfmon

The events are unchanged but unused json values are removed. This
increases consistency across the json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-23-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../arch/x86/westmereep-sp/cache.json         | 517 ------------------
 .../x86/westmereep-sp/floating-point.json     |  28 -
 .../arch/x86/westmereep-sp/frontend.json      |   3 -
 .../arch/x86/westmereep-sp/memory.json        | 134 -----
 .../arch/x86/westmereep-sp/other.json         |  22 -
 .../arch/x86/westmereep-sp/pipeline.json      | 129 +----
 .../x86/westmereep-sp/virtual-memory.json     |  18 -
 7 files changed, 5 insertions(+), 846 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json
index c5f33fe2a3ce2..e00c301640f37 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Cycles L1D locked",
-        "Counter": "0,1",
         "EventCode": "0x63",
         "EventName": "CACHE_LOCK_CYCLES.L1D",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Cycles L1D and L2 locked",
-        "Counter": "0,1",
         "EventCode": "0x63",
         "EventName": "CACHE_LOCK_CYCLES.L1D_L2",
         "SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "L1D cache lines replaced in M state",
-        "Counter": "0,1",
         "EventCode": "0x51",
         "EventName": "L1D.M_EVICT",
         "SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "L1D cache lines allocated in the M state",
-        "Counter": "0,1",
         "EventCode": "0x51",
         "EventName": "L1D.M_REPL",
         "SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "L1D snoop eviction of cache lines in M state",
-        "Counter": "0,1",
         "EventCode": "0x51",
         "EventName": "L1D.M_SNOOP_EVICT",
         "SampleAfterValue": "2000000",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "L1 data cache lines allocated",
-        "Counter": "0,1",
         "EventCode": "0x51",
         "EventName": "L1D.REPL",
         "SampleAfterValue": "2000000",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "L1D prefetch load lock accepted in fill buffer",
-        "Counter": "0,1",
         "EventCode": "0x52",
         "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
         "SampleAfterValue": "2000000",
@@ -57,7 +50,6 @@
     },
     {
         "BriefDescription": "L1D hardware prefetch misses",
-        "Counter": "0,1",
         "EventCode": "0x4E",
         "EventName": "L1D_PREFETCH.MISS",
         "SampleAfterValue": "200000",
@@ -65,7 +57,6 @@
     },
     {
         "BriefDescription": "L1D hardware prefetch requests",
-        "Counter": "0,1",
         "EventCode": "0x4E",
         "EventName": "L1D_PREFETCH.REQUESTS",
         "SampleAfterValue": "200000",
@@ -73,7 +64,6 @@
     },
     {
         "BriefDescription": "L1D hardware prefetch requests triggered",
-        "Counter": "0,1",
         "EventCode": "0x4E",
         "EventName": "L1D_PREFETCH.TRIGGERS",
         "SampleAfterValue": "200000",
@@ -81,7 +71,6 @@
     },
     {
         "BriefDescription": "L1 writebacks to L2 in E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.E_STATE",
         "SampleAfterValue": "100000",
@@ -89,7 +78,6 @@
     },
     {
         "BriefDescription": "L1 writebacks to L2 in I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.I_STATE",
         "SampleAfterValue": "100000",
@@ -97,7 +85,6 @@
     },
     {
         "BriefDescription": "All L1 writebacks to L2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.MESI",
         "SampleAfterValue": "100000",
@@ -105,7 +92,6 @@
     },
     {
         "BriefDescription": "L1 writebacks to L2 in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.M_STATE",
         "SampleAfterValue": "100000",
@@ -113,7 +99,6 @@
     },
     {
         "BriefDescription": "L1 writebacks to L2 in S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.S_STATE",
         "SampleAfterValue": "100000",
@@ -121,7 +106,6 @@
     },
     {
         "BriefDescription": "All L2 data requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.ANY",
         "SampleAfterValue": "200000",
@@ -129,7 +113,6 @@
     },
     {
         "BriefDescription": "L2 data demand loads in E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
         "SampleAfterValue": "200000",
@@ -137,7 +120,6 @@
     },
     {
         "BriefDescription": "L2 data demand loads in I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
         "SampleAfterValue": "200000",
@@ -145,7 +127,6 @@
     },
     {
         "BriefDescription": "L2 data demand requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.MESI",
         "SampleAfterValue": "200000",
@@ -153,7 +134,6 @@
     },
     {
         "BriefDescription": "L2 data demand loads in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
         "SampleAfterValue": "200000",
@@ -161,7 +141,6 @@
     },
     {
         "BriefDescription": "L2 data demand loads in S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
         "SampleAfterValue": "200000",
@@ -169,7 +148,6 @@
     },
     {
         "BriefDescription": "L2 data prefetches in E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
         "SampleAfterValue": "200000",
@@ -177,7 +155,6 @@
     },
     {
         "BriefDescription": "L2 data prefetches in the I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
         "SampleAfterValue": "200000",
@@ -185,7 +162,6 @@
     },
     {
         "BriefDescription": "All L2 data prefetches",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
         "SampleAfterValue": "200000",
@@ -193,7 +169,6 @@
     },
     {
         "BriefDescription": "L2 data prefetches in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
         "SampleAfterValue": "200000",
@@ -201,7 +176,6 @@
     },
     {
         "BriefDescription": "L2 data prefetches in the S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
         "SampleAfterValue": "200000",
@@ -209,7 +183,6 @@
     },
     {
         "BriefDescription": "L2 lines alloacated",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.ANY",
         "SampleAfterValue": "100000",
@@ -217,7 +190,6 @@
     },
     {
         "BriefDescription": "L2 lines allocated in the E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.E_STATE",
         "SampleAfterValue": "100000",
@@ -225,7 +197,6 @@
     },
     {
         "BriefDescription": "L2 lines allocated in the S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.S_STATE",
         "SampleAfterValue": "100000",
@@ -233,7 +204,6 @@
     },
     {
         "BriefDescription": "L2 lines evicted",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.ANY",
         "SampleAfterValue": "100000",
@@ -241,7 +211,6 @@
     },
     {
         "BriefDescription": "L2 lines evicted by a demand request",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
         "SampleAfterValue": "100000",
@@ -249,7 +218,6 @@
     },
     {
         "BriefDescription": "L2 modified lines evicted by a demand request",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
         "SampleAfterValue": "100000",
@@ -257,7 +225,6 @@
     },
     {
         "BriefDescription": "L2 lines evicted by a prefetch request",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
         "SampleAfterValue": "100000",
@@ -265,7 +232,6 @@
     },
     {
         "BriefDescription": "L2 modified lines evicted by a prefetch request",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
         "SampleAfterValue": "100000",
@@ -273,7 +239,6 @@
     },
     {
         "BriefDescription": "L2 instruction fetches",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.IFETCHES",
         "SampleAfterValue": "200000",
@@ -281,7 +246,6 @@
     },
     {
         "BriefDescription": "L2 instruction fetch hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.IFETCH_HIT",
         "SampleAfterValue": "200000",
@@ -289,7 +253,6 @@
     },
     {
         "BriefDescription": "L2 instruction fetch misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.IFETCH_MISS",
         "SampleAfterValue": "200000",
@@ -297,7 +260,6 @@
     },
     {
         "BriefDescription": "L2 load hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.LD_HIT",
         "SampleAfterValue": "200000",
@@ -305,7 +267,6 @@
     },
     {
         "BriefDescription": "L2 load misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.LD_MISS",
         "SampleAfterValue": "200000",
@@ -313,7 +274,6 @@
     },
     {
         "BriefDescription": "L2 requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.LOADS",
         "SampleAfterValue": "200000",
@@ -321,7 +281,6 @@
     },
     {
         "BriefDescription": "All L2 misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.MISS",
         "SampleAfterValue": "200000",
@@ -329,7 +288,6 @@
     },
     {
         "BriefDescription": "All L2 prefetches",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PREFETCHES",
         "SampleAfterValue": "200000",
@@ -337,7 +295,6 @@
     },
     {
         "BriefDescription": "L2 prefetch hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PREFETCH_HIT",
         "SampleAfterValue": "200000",
@@ -345,7 +302,6 @@
     },
     {
         "BriefDescription": "L2 prefetch misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PREFETCH_MISS",
         "SampleAfterValue": "200000",
@@ -353,7 +309,6 @@
     },
     {
         "BriefDescription": "All L2 requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.REFERENCES",
         "SampleAfterValue": "200000",
@@ -361,7 +316,6 @@
     },
     {
         "BriefDescription": "L2 RFO requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFOS",
         "SampleAfterValue": "200000",
@@ -369,7 +323,6 @@
     },
     {
         "BriefDescription": "L2 RFO hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_HIT",
         "SampleAfterValue": "200000",
@@ -377,7 +330,6 @@
     },
     {
         "BriefDescription": "L2 RFO misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_MISS",
         "SampleAfterValue": "200000",
@@ -385,7 +337,6 @@
     },
     {
         "BriefDescription": "All L2 transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.ANY",
         "SampleAfterValue": "200000",
@@ -393,7 +344,6 @@
     },
     {
         "BriefDescription": "L2 fill transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.FILL",
         "SampleAfterValue": "200000",
@@ -401,7 +351,6 @@
     },
     {
         "BriefDescription": "L2 instruction fetch transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.IFETCH",
         "SampleAfterValue": "200000",
@@ -409,7 +358,6 @@
     },
     {
         "BriefDescription": "L1D writeback to L2 transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.L1D_WB",
         "SampleAfterValue": "200000",
@@ -417,7 +365,6 @@
     },
     {
         "BriefDescription": "L2 Load transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.LOAD",
         "SampleAfterValue": "200000",
@@ -425,7 +372,6 @@
     },
     {
         "BriefDescription": "L2 prefetch transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.PREFETCH",
         "SampleAfterValue": "200000",
@@ -433,7 +379,6 @@
     },
     {
         "BriefDescription": "L2 RFO transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.RFO",
         "SampleAfterValue": "200000",
@@ -441,7 +386,6 @@
     },
     {
         "BriefDescription": "L2 writeback to LLC transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.WB",
         "SampleAfterValue": "200000",
@@ -449,7 +393,6 @@
     },
     {
         "BriefDescription": "L2 demand lock RFOs in E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.E_STATE",
         "SampleAfterValue": "100000",
@@ -457,7 +400,6 @@
     },
     {
         "BriefDescription": "All demand L2 lock RFOs that hit the cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.HIT",
         "SampleAfterValue": "100000",
@@ -465,7 +407,6 @@
     },
     {
         "BriefDescription": "L2 demand lock RFOs in I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.I_STATE",
         "SampleAfterValue": "100000",
@@ -473,7 +414,6 @@
     },
     {
         "BriefDescription": "All demand L2 lock RFOs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.MESI",
         "SampleAfterValue": "100000",
@@ -481,7 +421,6 @@
     },
     {
         "BriefDescription": "L2 demand lock RFOs in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.M_STATE",
         "SampleAfterValue": "100000",
@@ -489,7 +428,6 @@
     },
     {
         "BriefDescription": "L2 demand lock RFOs in S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.S_STATE",
         "SampleAfterValue": "100000",
@@ -497,7 +435,6 @@
     },
     {
         "BriefDescription": "All L2 demand store RFOs that hit the cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.HIT",
         "SampleAfterValue": "100000",
@@ -505,7 +442,6 @@
     },
     {
         "BriefDescription": "L2 demand store RFOs in I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.I_STATE",
         "SampleAfterValue": "100000",
@@ -513,7 +449,6 @@
     },
     {
         "BriefDescription": "All L2 demand store RFOs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.MESI",
         "SampleAfterValue": "100000",
@@ -521,7 +456,6 @@
     },
     {
         "BriefDescription": "L2 demand store RFOs in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.M_STATE",
         "SampleAfterValue": "100000",
@@ -529,7 +463,6 @@
     },
     {
         "BriefDescription": "L2 demand store RFOs in S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.S_STATE",
         "SampleAfterValue": "100000",
@@ -537,7 +470,6 @@
     },
     {
         "BriefDescription": "Longest latency cache miss",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.MISS",
         "SampleAfterValue": "100000",
@@ -545,7 +477,6 @@
     },
     {
         "BriefDescription": "Longest latency cache reference",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
         "SampleAfterValue": "200000",
@@ -553,18 +484,15 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
         "MSRIndex": "0x3F6",
-        "MSRValue": "0x0",
         "PEBS": "2",
         "SampleAfterValue": "2000000",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
         "MSRIndex": "0x3F6",
@@ -575,7 +503,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
         "MSRIndex": "0x3F6",
@@ -586,7 +513,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
         "MSRIndex": "0x3F6",
@@ -597,7 +523,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
         "MSRIndex": "0x3F6",
@@ -608,7 +533,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
         "MSRIndex": "0x3F6",
@@ -619,7 +543,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
         "MSRIndex": "0x3F6",
@@ -630,7 +553,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
         "MSRIndex": "0x3F6",
@@ -641,7 +563,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
         "MSRIndex": "0x3F6",
@@ -652,7 +573,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
         "MSRIndex": "0x3F6",
@@ -663,7 +583,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
         "MSRIndex": "0x3F6",
@@ -674,7 +593,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
         "MSRIndex": "0x3F6",
@@ -685,7 +603,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
         "MSRIndex": "0x3F6",
@@ -696,7 +613,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
         "MSRIndex": "0x3F6",
@@ -707,7 +623,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
         "MSRIndex": "0x3F6",
@@ -718,7 +633,6 @@
     },
     {
         "BriefDescription": "Instructions retired which contains a load (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LOADS",
         "PEBS": "1",
@@ -727,7 +641,6 @@
     },
     {
         "BriefDescription": "Instructions retired which contains a store (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.STORES",
         "PEBS": "1",
@@ -736,7 +649,6 @@
     },
     {
         "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.HIT_LFB",
         "PEBS": "1",
@@ -745,7 +657,6 @@
     },
     {
         "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.L1D_HIT",
         "PEBS": "1",
@@ -754,7 +665,6 @@
     },
     {
         "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.L2_HIT",
         "PEBS": "1",
@@ -763,7 +673,6 @@
     },
     {
         "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.LLC_MISS",
         "PEBS": "1",
@@ -772,7 +681,6 @@
     },
     {
         "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
         "PEBS": "1",
@@ -781,7 +689,6 @@
     },
     {
         "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
         "PEBS": "1",
@@ -790,7 +697,6 @@
     },
     {
         "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM",
         "PEBS": "1",
@@ -799,7 +705,6 @@
     },
     {
         "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM",
         "PEBS": "1",
@@ -808,7 +713,6 @@
     },
     {
         "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT",
         "PEBS": "1",
@@ -817,7 +721,6 @@
     },
     {
         "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM",
         "PEBS": "1",
@@ -826,7 +729,6 @@
     },
     {
         "BriefDescription": "Load instructions retired IO (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE",
         "PEBS": "1",
@@ -835,7 +737,6 @@
     },
     {
         "BriefDescription": "All offcore requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ANY",
         "SampleAfterValue": "100000",
@@ -843,7 +744,6 @@
     },
     {
         "BriefDescription": "Offcore read requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ANY.READ",
         "SampleAfterValue": "100000",
@@ -851,7 +751,6 @@
     },
     {
         "BriefDescription": "Offcore RFO requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ANY.RFO",
         "SampleAfterValue": "100000",
@@ -859,7 +758,6 @@
     },
     {
         "BriefDescription": "Offcore demand code read requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE",
         "SampleAfterValue": "100000",
@@ -867,7 +765,6 @@
     },
     {
         "BriefDescription": "Offcore demand data read requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA",
         "SampleAfterValue": "100000",
@@ -875,7 +772,6 @@
     },
     {
         "BriefDescription": "Offcore demand RFO requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND.RFO",
         "SampleAfterValue": "100000",
@@ -883,7 +779,6 @@
     },
     {
         "BriefDescription": "Offcore L1 data cache writebacks",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
         "SampleAfterValue": "100000",
@@ -891,7 +786,6 @@
     },
     {
         "BriefDescription": "Offcore uncached memory accesses",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.UNCACHED_MEM",
         "SampleAfterValue": "100000",
@@ -959,7 +853,6 @@
     },
     {
         "BriefDescription": "Offcore requests blocked due to Super Queue full",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "OFFCORE_REQUESTS_SQ_FULL",
         "SampleAfterValue": "100000",
@@ -967,2240 +860,1833 @@
     },
     {
         "BriefDescription": "Offcore data reads satisfied by any cache or DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7F11",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore data reads",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xFF11",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x111",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x211",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x411",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x711",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2711",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1811",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5811",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads that HIT in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads that HITM in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x811",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by any cache or DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7F44",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore code reads",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xFF44",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x144",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x244",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x444",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x744",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2744",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1844",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5844",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads that HIT in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads that HITM in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x844",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by any cache or DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7FFF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xFFFF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x80FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x27FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x18FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x58FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests that HIT in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x10FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests that HITM in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7F22",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore RFO requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xFF22",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x122",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x222",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x422",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x722",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2722",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1822",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5822",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests that HIT in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests that HITM in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x822",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to any cache or DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7F08",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore writebacks",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xFF08",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x108",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the LLC  and HITM in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x408",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x708",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the LLC or local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2708",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1808",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5808",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks that HIT in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks that HITM in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x808",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7F77",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore code or data read requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xFF77",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x177",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x277",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x477",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x777",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2777",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1877",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5877",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests that HIT in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests that HITM in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x877",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = any cache_dram",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7F33",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = any location",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xFF33",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x133",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x233",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x433",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = local cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x733",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = local cache or dram",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2733",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1833",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = remote cache or dram",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5833",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x833",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7F03",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore demand data requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xFF03",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x103",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x203",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x403",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x703",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2703",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1803",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5803",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests that HIT in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests that HITM in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x803",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7F01",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore demand data reads",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xFF01",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x101",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x201",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x401",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x701",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2701",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1801",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5801",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads that HIT in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads that HITM in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x801",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7F04",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore demand code reads",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xFF04",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x104",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x204",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x404",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x704",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2704",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1804",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5804",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads that HIT in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads that HITM in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x804",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7F02",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore demand RFO requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xFF02",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x102",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x202",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x402",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x702",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2702",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1802",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5802",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x802",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7F80",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore other requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xFF80",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8080",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x180",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x280",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x480",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x780",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2780",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1880",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5880",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests that HIT in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1080",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests that HITM in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x880",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7F50",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore prefetch data requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xFF50",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8050",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x150",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x250",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x450",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x750",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2750",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1850",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5850",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1050",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x850",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7F10",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore prefetch data reads",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xFF10",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x110",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x210",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x410",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x710",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2710",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1810",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5810",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x810",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7F40",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore prefetch code reads",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xFF40",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x140",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x240",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x440",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x740",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2740",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1840",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5840",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x840",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7F20",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore prefetch RFO requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xFF20",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x120",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x220",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x420",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x720",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2720",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1820",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5820",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x820",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x7F70",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore prefetch requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xFF70",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x8070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x170",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x270",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x470",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x770",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2770",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1870",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x5870",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests that HIT in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x1070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests that HITM in a remote cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x870",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Super Queue LRU hints sent to LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF4",
         "EventName": "SQ_MISC.LRU_HINTS",
         "SampleAfterValue": "2000000",
@@ -3208,7 +2694,6 @@
     },
     {
         "BriefDescription": "Super Queue lock splits across a cache line",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF4",
         "EventName": "SQ_MISC.SPLIT_LOCK",
         "SampleAfterValue": "2000000",
@@ -3216,7 +2701,6 @@
     },
     {
         "BriefDescription": "Loads delayed with at-Retirement block code",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "STORE_BLOCKS.AT_RET",
         "SampleAfterValue": "200000",
@@ -3224,7 +2708,6 @@
     },
     {
         "BriefDescription": "Cacheable loads delayed with L1D block code",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "STORE_BLOCKS.L1D_BLOCK",
         "SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json
index 666e466d351c4..c03f8990fa82a 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "X87 Floating point assists (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF7",
         "EventName": "FP_ASSIST.ALL",
         "PEBS": "1",
@@ -10,7 +9,6 @@
     },
     {
         "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF7",
         "EventName": "FP_ASSIST.INPUT",
         "PEBS": "1",
@@ -19,7 +17,6 @@
     },
     {
         "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF7",
         "EventName": "FP_ASSIST.OUTPUT",
         "PEBS": "1",
@@ -28,7 +25,6 @@
     },
     {
         "BriefDescription": "MMX Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.MMX",
         "SampleAfterValue": "2000000",
@@ -36,7 +32,6 @@
     },
     {
         "BriefDescription": "SSE2 integer Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
         "SampleAfterValue": "2000000",
@@ -44,7 +39,6 @@
     },
     {
         "BriefDescription": "SSE* FP double precision Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
         "SampleAfterValue": "2000000",
@@ -52,7 +46,6 @@
     },
     {
         "BriefDescription": "SSE and SSE2 FP Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_FP",
         "SampleAfterValue": "2000000",
@@ -60,7 +53,6 @@
     },
     {
         "BriefDescription": "SSE FP packed Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
         "SampleAfterValue": "2000000",
@@ -68,7 +60,6 @@
     },
     {
         "BriefDescription": "SSE FP scalar Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
         "SampleAfterValue": "2000000",
@@ -76,7 +67,6 @@
     },
     {
         "BriefDescription": "SSE* FP single precision Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
         "SampleAfterValue": "2000000",
@@ -84,7 +74,6 @@
     },
     {
         "BriefDescription": "Computational floating-point operations executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.X87",
         "SampleAfterValue": "2000000",
@@ -92,7 +81,6 @@
     },
     {
         "BriefDescription": "All Floating Point to and from MMX transitions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCC",
         "EventName": "FP_MMX_TRANS.ANY",
         "SampleAfterValue": "2000000",
@@ -100,7 +88,6 @@
     },
     {
         "BriefDescription": "Transitions from MMX to Floating Point instructions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCC",
         "EventName": "FP_MMX_TRANS.TO_FP",
         "SampleAfterValue": "2000000",
@@ -108,7 +95,6 @@
     },
     {
         "BriefDescription": "Transitions from Floating Point to MMX instructions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCC",
         "EventName": "FP_MMX_TRANS.TO_MMX",
         "SampleAfterValue": "2000000",
@@ -116,7 +102,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer pack operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACK",
         "SampleAfterValue": "200000",
@@ -124,7 +109,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer arithmetic operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_ARITH",
         "SampleAfterValue": "200000",
@@ -132,7 +116,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer logical operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_LOGICAL",
         "SampleAfterValue": "200000",
@@ -140,7 +123,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer multiply operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_MPY",
         "SampleAfterValue": "200000",
@@ -148,7 +130,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer shift operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_SHIFT",
         "SampleAfterValue": "200000",
@@ -156,7 +137,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer shuffle/move operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.SHUFFLE_MOVE",
         "SampleAfterValue": "200000",
@@ -164,7 +144,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer unpack operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.UNPACK",
         "SampleAfterValue": "200000",
@@ -172,7 +151,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit pack operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACK",
         "SampleAfterValue": "200000",
@@ -180,7 +158,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit arithmetic operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_ARITH",
         "SampleAfterValue": "200000",
@@ -188,7 +165,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit logical operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_LOGICAL",
         "SampleAfterValue": "200000",
@@ -196,7 +172,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit packed multiply operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_MPY",
         "SampleAfterValue": "200000",
@@ -204,7 +179,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit shift operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_SHIFT",
         "SampleAfterValue": "200000",
@@ -212,7 +186,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit shuffle/move operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.SHUFFLE_MOVE",
         "SampleAfterValue": "200000",
@@ -220,7 +193,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit unpack operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.UNPACK",
         "SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json
index c561ac24d91d1..f7f28510e3ae9 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MACRO_INSTS.DECODED",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Macro-fused instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA6",
         "EventName": "MACRO_INSTS.FUSIONS_DECODED",
         "SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "Two Uop instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "TWO_UOP_INSTS_DECODED",
         "SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json
index f14e760a9ddc4..b65c5294bcf1d 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json
@@ -1,738 +1,604 @@
 [
     {
         "BriefDescription": "Offcore data reads satisfied by any DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x6011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads that missed the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xF811",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by a remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by any DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x6044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads that missed the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xF844",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by a remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by any DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x60FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests that missed the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xF8FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x20FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by a remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x40FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by any DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x6022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests that missed the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xF822",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to any DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x6008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks that missed the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xF808",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to a remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by any DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x6077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests that missed the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xF877",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = any DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x6033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = any LLC miss",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xF833",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the local DRAM.",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by any DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x6003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests that missed the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xF803",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by any DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x6001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads that missed the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xF801",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by any DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x6004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads that missed the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xF804",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x6002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests that missed the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xF802",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by any DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x6080",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests that missed the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xF880",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by a remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4080",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x6050",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests that missed the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xF850",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2050",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4050",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x6010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads that missed the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xF810",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x6040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads that missed the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xF840",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x6020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests that missed the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xF820",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by any DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x6070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests that missed the LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0xF870",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x2070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB7, 0xBB",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1a6,0x1a7",
         "MSRValue": "0x4070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     }
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json
index 67bc34984fa80..4882749805646 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "ES segment renames",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD5",
         "EventName": "ES_REG_RENAMES",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "I/O transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6C",
         "EventName": "IO_TRANSACTIONS",
         "SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "L1I instruction fetch stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.CYCLES_STALLED",
         "SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "L1I instruction fetch hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.HITS",
         "SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "L1I instruction fetch misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.MISSES",
         "SampleAfterValue": "2000000",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "L1I Instruction fetches",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.READS",
         "SampleAfterValue": "2000000",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "Large ITLB hit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x82",
         "EventName": "LARGE_ITLB.HIT",
         "SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
     },
     {
         "BriefDescription": "Loads that partially overlap an earlier store",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "LOAD_BLOCK.OVERLAP_STORE",
         "SampleAfterValue": "200000",
@@ -65,7 +57,6 @@
     },
     {
         "BriefDescription": "All loads dispatched",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.ANY",
         "SampleAfterValue": "2000000",
@@ -73,7 +64,6 @@
     },
     {
         "BriefDescription": "Loads dispatched from the MOB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.MOB",
         "SampleAfterValue": "2000000",
@@ -81,7 +71,6 @@
     },
     {
         "BriefDescription": "Loads dispatched that bypass the MOB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.RS",
         "SampleAfterValue": "2000000",
@@ -89,7 +78,6 @@
     },
     {
         "BriefDescription": "Loads dispatched from stage 305",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.RS_DELAYED",
         "SampleAfterValue": "2000000",
@@ -97,7 +85,6 @@
     },
     {
         "BriefDescription": "False dependencies due to partial address aliasing",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "PARTIAL_ADDRESS_ALIAS",
         "SampleAfterValue": "200000",
@@ -105,7 +92,6 @@
     },
     {
         "BriefDescription": "All Store buffer stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "SB_DRAIN.ANY",
         "SampleAfterValue": "200000",
@@ -113,7 +99,6 @@
     },
     {
         "BriefDescription": "Segment rename stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD4",
         "EventName": "SEG_RENAME_STALLS",
         "SampleAfterValue": "2000000",
@@ -121,7 +106,6 @@
     },
     {
         "BriefDescription": "Snoop code requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "SNOOPQ_REQUESTS.CODE",
         "SampleAfterValue": "100000",
@@ -129,7 +113,6 @@
     },
     {
         "BriefDescription": "Snoop data requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "SNOOPQ_REQUESTS.DATA",
         "SampleAfterValue": "100000",
@@ -137,7 +120,6 @@
     },
     {
         "BriefDescription": "Snoop invalidate requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "SNOOPQ_REQUESTS.INVALIDATE",
         "SampleAfterValue": "100000",
@@ -190,7 +172,6 @@
     },
     {
         "BriefDescription": "Thread responded HIT to snoop",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "SNOOP_RESPONSE.HIT",
         "SampleAfterValue": "100000",
@@ -198,7 +179,6 @@
     },
     {
         "BriefDescription": "Thread responded HITE to snoop",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "SNOOP_RESPONSE.HITE",
         "SampleAfterValue": "100000",
@@ -206,7 +186,6 @@
     },
     {
         "BriefDescription": "Thread responded HITM to snoop",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "SNOOP_RESPONSE.HITM",
         "SampleAfterValue": "100000",
@@ -214,7 +193,6 @@
     },
     {
         "BriefDescription": "Super Queue full stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF6",
         "EventName": "SQ_FULL_STALL_CYCLES",
         "SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json
index 403fb2b87fc4d..a29ed35227794 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Cycles the divider is busy",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "ARITH.CYCLES_DIV_BUSY",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Divide Operations executed",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x14",
@@ -20,7 +18,6 @@
     },
     {
         "BriefDescription": "Multiply operations executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "ARITH.MUL",
         "SampleAfterValue": "2000000",
@@ -28,7 +25,6 @@
     },
     {
         "BriefDescription": "BACLEAR asserted with bad target address",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE6",
         "EventName": "BACLEAR.BAD_TARGET",
         "SampleAfterValue": "2000000",
@@ -36,7 +32,6 @@
     },
     {
         "BriefDescription": "BACLEAR asserted, regardless of cause",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE6",
         "EventName": "BACLEAR.CLEAR",
         "SampleAfterValue": "2000000",
@@ -44,7 +39,6 @@
     },
     {
         "BriefDescription": "Instruction queue forced BACLEAR",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA7",
         "EventName": "BACLEAR_FORCE_IQ",
         "SampleAfterValue": "2000000",
@@ -52,7 +46,6 @@
     },
     {
         "BriefDescription": "Early Branch Prediciton Unit clears",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE8",
         "EventName": "BPU_CLEARS.EARLY",
         "SampleAfterValue": "2000000",
@@ -60,7 +53,6 @@
     },
     {
         "BriefDescription": "Late Branch Prediction Unit clears",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE8",
         "EventName": "BPU_CLEARS.LATE",
         "SampleAfterValue": "2000000",
@@ -68,7 +60,6 @@
     },
     {
         "BriefDescription": "Branch prediction unit missed call or return",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE5",
         "EventName": "BPU_MISSED_CALL_RET",
         "SampleAfterValue": "2000000",
@@ -76,7 +67,6 @@
     },
     {
         "BriefDescription": "Branch instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE0",
         "EventName": "BR_INST_DECODED",
         "SampleAfterValue": "2000000",
@@ -84,7 +74,6 @@
     },
     {
         "BriefDescription": "Branch instructions executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ANY",
         "SampleAfterValue": "200000",
@@ -92,7 +81,6 @@
     },
     {
         "BriefDescription": "Conditional branch instructions executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.COND",
         "SampleAfterValue": "200000",
@@ -100,7 +88,6 @@
     },
     {
         "BriefDescription": "Unconditional branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.DIRECT",
         "SampleAfterValue": "200000",
@@ -108,7 +95,6 @@
     },
     {
         "BriefDescription": "Unconditional call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
         "SampleAfterValue": "20000",
@@ -116,7 +102,6 @@
     },
     {
         "BriefDescription": "Indirect call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
         "SampleAfterValue": "20000",
@@ -124,7 +109,6 @@
     },
     {
         "BriefDescription": "Indirect non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
         "SampleAfterValue": "20000",
@@ -132,7 +116,6 @@
     },
     {
         "BriefDescription": "Call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.NEAR_CALLS",
         "SampleAfterValue": "20000",
@@ -140,7 +123,6 @@
     },
     {
         "BriefDescription": "All non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.NON_CALLS",
         "SampleAfterValue": "200000",
@@ -148,7 +130,6 @@
     },
     {
         "BriefDescription": "Indirect return branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.RETURN_NEAR",
         "SampleAfterValue": "20000",
@@ -156,7 +137,6 @@
     },
     {
         "BriefDescription": "Taken branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN",
         "SampleAfterValue": "200000",
@@ -164,7 +144,6 @@
     },
     {
         "BriefDescription": "Retired branch instructions (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
@@ -173,7 +152,6 @@
     },
     {
         "BriefDescription": "Retired conditional branch instructions (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -182,7 +160,6 @@
     },
     {
         "BriefDescription": "Retired near call instructions (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -191,7 +168,6 @@
     },
     {
         "BriefDescription": "Mispredicted branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ANY",
         "SampleAfterValue": "20000",
@@ -199,7 +175,6 @@
     },
     {
         "BriefDescription": "Mispredicted conditional branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.COND",
         "SampleAfterValue": "20000",
@@ -207,7 +182,6 @@
     },
     {
         "BriefDescription": "Mispredicted unconditional branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.DIRECT",
         "SampleAfterValue": "20000",
@@ -215,7 +189,6 @@
     },
     {
         "BriefDescription": "Mispredicted non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
         "SampleAfterValue": "2000",
@@ -223,7 +196,6 @@
     },
     {
         "BriefDescription": "Mispredicted indirect call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
         "SampleAfterValue": "2000",
@@ -231,7 +203,6 @@
     },
     {
         "BriefDescription": "Mispredicted indirect non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
         "SampleAfterValue": "2000",
@@ -239,7 +210,6 @@
     },
     {
         "BriefDescription": "Mispredicted call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.NEAR_CALLS",
         "SampleAfterValue": "2000",
@@ -247,7 +217,6 @@
     },
     {
         "BriefDescription": "Mispredicted non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.NON_CALLS",
         "SampleAfterValue": "20000",
@@ -255,7 +224,6 @@
     },
     {
         "BriefDescription": "Mispredicted return branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.RETURN_NEAR",
         "SampleAfterValue": "2000",
@@ -263,7 +231,6 @@
     },
     {
         "BriefDescription": "Mispredicted taken branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN",
         "SampleAfterValue": "20000",
@@ -271,7 +238,6 @@
     },
     {
         "BriefDescription": "Mispredicted retired branch instructions (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
@@ -280,7 +246,6 @@
     },
     {
         "BriefDescription": "Mispredicted conditional retired branches (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -289,7 +254,6 @@
     },
     {
         "BriefDescription": "Mispredicted near retired calls (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -298,15 +262,11 @@
     },
     {
         "BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
-        "Counter": "Fixed counter 3",
-        "EventCode": "0x0",
         "EventName": "CPU_CLK_UNHALTED.REF",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_P",
         "SampleAfterValue": "100000",
@@ -314,33 +274,25 @@
     },
     {
         "BriefDescription": "Cycles when thread is not halted (fixed counter)",
-        "Counter": "Fixed counter 2",
-        "EventCode": "0x0",
         "EventName": "CPU_CLK_UNHALTED.THREAD",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Cycles when thread is not halted (programmable counter)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Total CPU cycles",
-        "Counter": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
         "Invert": "1",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Any Instruction Length Decoder stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.ANY",
         "SampleAfterValue": "2000000",
@@ -348,7 +300,6 @@
     },
     {
         "BriefDescription": "Instruction Queue full stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.IQ_FULL",
         "SampleAfterValue": "2000000",
@@ -356,7 +307,6 @@
     },
     {
         "BriefDescription": "Length Change Prefix stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.LCP",
         "SampleAfterValue": "2000000",
@@ -364,7 +314,6 @@
     },
     {
         "BriefDescription": "Stall cycles due to BPU MRU bypass",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.MRU",
         "SampleAfterValue": "2000000",
@@ -372,7 +321,6 @@
     },
     {
         "BriefDescription": "Regen stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.REGEN",
         "SampleAfterValue": "2000000",
@@ -380,7 +328,6 @@
     },
     {
         "BriefDescription": "Instructions that must be decoded by decoder 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "INST_DECODED.DEC0",
         "SampleAfterValue": "2000000",
@@ -388,7 +335,6 @@
     },
     {
         "BriefDescription": "Instructions written to instruction queue.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x17",
         "EventName": "INST_QUEUE_WRITES",
         "SampleAfterValue": "2000000",
@@ -396,7 +342,6 @@
     },
     {
         "BriefDescription": "Cycles instructions are written to the instruction queue",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
         "EventName": "INST_QUEUE_WRITE_CYCLES",
         "SampleAfterValue": "2000000",
@@ -404,15 +349,11 @@
     },
     {
         "BriefDescription": "Instructions retired (fixed counter)",
-        "Counter": "Fixed counter 1",
-        "EventCode": "0x0",
         "EventName": "INST_RETIRED.ANY",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.ANY_P",
         "PEBS": "1",
@@ -421,7 +362,6 @@
     },
     {
         "BriefDescription": "Retired MMX instructions (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.MMX",
         "PEBS": "1",
@@ -430,7 +370,6 @@
     },
     {
         "BriefDescription": "Total cycles (Precise Event)",
-        "Counter": "0,1,2,3",
         "CounterMask": "16",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.TOTAL_CYCLES",
@@ -441,7 +380,6 @@
     },
     {
         "BriefDescription": "Total cycles (Precise Event)",
-        "Counter": "0,1,2,3",
         "CounterMask": "16",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
@@ -452,7 +390,6 @@
     },
     {
         "BriefDescription": "Retired floating-point operations (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.X87",
         "PEBS": "1",
@@ -461,7 +398,6 @@
     },
     {
         "BriefDescription": "Load operations conflicting with software prefetches",
-        "Counter": "0,1",
         "EventCode": "0x4C",
         "EventName": "LOAD_HIT_PRE",
         "SampleAfterValue": "200000",
@@ -469,7 +405,6 @@
     },
     {
         "BriefDescription": "Cycles when uops were delivered by the LSD",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.ACTIVE",
@@ -478,7 +413,6 @@
     },
     {
         "BriefDescription": "Cycles no uops were delivered by the LSD",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.INACTIVE",
@@ -488,7 +422,6 @@
     },
     {
         "BriefDescription": "Loops that can't stream from the instruction queue",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "LSD_OVERFLOW",
         "SampleAfterValue": "2000000",
@@ -496,7 +429,6 @@
     },
     {
         "BriefDescription": "Cycles machine clear asserted",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.CYCLES",
         "SampleAfterValue": "20000",
@@ -504,7 +436,6 @@
     },
     {
         "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MEM_ORDER",
         "SampleAfterValue": "20000",
@@ -512,7 +443,6 @@
     },
     {
         "BriefDescription": "Self-Modifying Code detected",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.SMC",
         "SampleAfterValue": "20000",
@@ -520,7 +450,6 @@
     },
     {
         "BriefDescription": "All RAT stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.ANY",
         "SampleAfterValue": "2000000",
@@ -528,7 +457,6 @@
     },
     {
         "BriefDescription": "Flag stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.FLAGS",
         "SampleAfterValue": "2000000",
@@ -536,7 +464,6 @@
     },
     {
         "BriefDescription": "Partial register stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.REGISTERS",
         "SampleAfterValue": "2000000",
@@ -544,7 +471,6 @@
     },
     {
         "BriefDescription": "ROB read port stalls cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.ROB_READ_PORT",
         "SampleAfterValue": "2000000",
@@ -552,7 +478,6 @@
     },
     {
         "BriefDescription": "Scoreboard stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.SCOREBOARD",
         "SampleAfterValue": "2000000",
@@ -560,7 +485,6 @@
     },
     {
         "BriefDescription": "Resource related stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ANY",
         "SampleAfterValue": "2000000",
@@ -568,7 +492,6 @@
     },
     {
         "BriefDescription": "FPU control word write stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.FPCW",
         "SampleAfterValue": "2000000",
@@ -576,7 +499,6 @@
     },
     {
         "BriefDescription": "Load buffer stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.LOAD",
         "SampleAfterValue": "2000000",
@@ -584,7 +506,6 @@
     },
     {
         "BriefDescription": "MXCSR rename stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.MXCSR",
         "SampleAfterValue": "2000000",
@@ -592,7 +513,6 @@
     },
     {
         "BriefDescription": "Other Resource related stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.OTHER",
         "SampleAfterValue": "2000000",
@@ -600,7 +520,6 @@
     },
     {
         "BriefDescription": "ROB full stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ROB_FULL",
         "SampleAfterValue": "2000000",
@@ -608,7 +527,6 @@
     },
     {
         "BriefDescription": "Reservation Station full stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.RS_FULL",
         "SampleAfterValue": "2000000",
@@ -616,7 +534,6 @@
     },
     {
         "BriefDescription": "Store buffer stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.STORE",
         "SampleAfterValue": "2000000",
@@ -624,7 +541,6 @@
     },
     {
         "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
         "PEBS": "1",
@@ -633,7 +549,6 @@
     },
     {
         "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
         "PEBS": "1",
@@ -642,7 +557,6 @@
     },
     {
         "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
         "PEBS": "1",
@@ -651,7 +565,6 @@
     },
     {
         "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
         "PEBS": "1",
@@ -660,7 +573,6 @@
     },
     {
         "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
         "PEBS": "1",
@@ -669,7 +581,6 @@
     },
     {
         "BriefDescription": "Stack pointer instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "UOPS_DECODED.ESP_FOLDING",
         "SampleAfterValue": "2000000",
@@ -677,7 +588,6 @@
     },
     {
         "BriefDescription": "Stack pointer sync operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "UOPS_DECODED.ESP_SYNC",
         "SampleAfterValue": "2000000",
@@ -685,7 +595,6 @@
     },
     {
         "BriefDescription": "Uops decoded by Microcode Sequencer",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xD1",
         "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
@@ -694,7 +603,6 @@
     },
     {
         "BriefDescription": "Cycles no Uops are decoded",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xD1",
         "EventName": "UOPS_DECODED.STALL_CYCLES",
@@ -705,7 +613,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles Uops executed on any port (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
@@ -715,7 +622,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
@@ -725,7 +631,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops executed on any port (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xB1",
@@ -737,7 +642,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops executed on ports 0-4 (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xB1",
@@ -749,7 +653,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles no Uops issued on any port (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
@@ -760,7 +663,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
@@ -770,7 +672,6 @@
     },
     {
         "BriefDescription": "Uops executed on port 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT0",
         "SampleAfterValue": "2000000",
@@ -778,7 +679,6 @@
     },
     {
         "BriefDescription": "Uops issued on ports 0, 1 or 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT015",
         "SampleAfterValue": "2000000",
@@ -786,7 +686,6 @@
     },
     {
         "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
@@ -796,7 +695,6 @@
     },
     {
         "BriefDescription": "Uops executed on port 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT1",
         "SampleAfterValue": "2000000",
@@ -805,7 +703,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops issued on ports 2, 3 or 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT234_CORE",
         "SampleAfterValue": "2000000",
@@ -814,7 +711,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops executed on port 2 (core count)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT2_CORE",
         "SampleAfterValue": "2000000",
@@ -823,7 +719,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops executed on port 3 (core count)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT3_CORE",
         "SampleAfterValue": "2000000",
@@ -832,7 +727,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops executed on port 4 (core count)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT4_CORE",
         "SampleAfterValue": "2000000",
@@ -840,7 +734,6 @@
     },
     {
         "BriefDescription": "Uops executed on port 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT5",
         "SampleAfterValue": "2000000",
@@ -848,7 +741,6 @@
     },
     {
         "BriefDescription": "Uops issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.ANY",
         "SampleAfterValue": "2000000",
@@ -857,7 +749,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles no Uops were issued on any thread",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -868,7 +759,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles Uops were issued on either thread",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
@@ -877,7 +767,6 @@
     },
     {
         "BriefDescription": "Fused Uops issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.FUSED",
         "SampleAfterValue": "2000000",
@@ -885,7 +774,6 @@
     },
     {
         "BriefDescription": "Cycles no Uops were issued",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -895,7 +783,6 @@
     },
     {
         "BriefDescription": "Cycles Uops are being retired",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
@@ -905,7 +792,6 @@
     },
     {
         "BriefDescription": "Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ANY",
         "PEBS": "1",
@@ -914,7 +800,6 @@
     },
     {
         "BriefDescription": "Macro-fused Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.MACRO_FUSED",
         "PEBS": "1",
@@ -923,7 +808,6 @@
     },
     {
         "BriefDescription": "Retirement slots used (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
         "PEBS": "1",
@@ -932,7 +816,6 @@
     },
     {
         "BriefDescription": "Cycles Uops are not retiring (Precise Event)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -943,7 +826,6 @@
     },
     {
         "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
-        "Counter": "0,1,2,3",
         "CounterMask": "16",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
@@ -954,7 +836,6 @@
     },
     {
         "BriefDescription": "Uop unfusions due to FP exceptions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xDB",
         "EventName": "UOP_UNFUSION",
         "SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json
index e7affdf7f41b7..80efcfd482392 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "DTLB load misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.ANY",
         "SampleAfterValue": "200000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "DTLB load miss caused by low part of address",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.PDE_MISS",
         "SampleAfterValue": "200000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "DTLB second level hit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
         "SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "DTLB load miss page walks complete",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "DTLB load miss page walk cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",
         "SampleAfterValue": "200000",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "DTLB misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.ANY",
         "SampleAfterValue": "200000",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "DTLB miss large page walks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
     },
     {
         "BriefDescription": "DTLB first level misses but second level hit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.STLB_HIT",
         "SampleAfterValue": "200000",
@@ -65,7 +57,6 @@
     },
     {
         "BriefDescription": "DTLB miss page walks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -73,7 +64,6 @@
     },
     {
         "BriefDescription": "DTLB miss page walk cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.WALK_CYCLES",
         "SampleAfterValue": "2000000",
@@ -81,7 +71,6 @@
     },
     {
         "BriefDescription": "Extended Page Table walk cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4F",
         "EventName": "EPT.WALK_CYCLES",
         "SampleAfterValue": "2000000",
@@ -89,7 +78,6 @@
     },
     {
         "BriefDescription": "ITLB flushes",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAE",
         "EventName": "ITLB_FLUSH",
         "SampleAfterValue": "2000000",
@@ -97,7 +85,6 @@
     },
     {
         "BriefDescription": "ITLB miss",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.ANY",
         "SampleAfterValue": "200000",
@@ -105,7 +92,6 @@
     },
     {
         "BriefDescription": "ITLB miss page walks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -113,7 +99,6 @@
     },
     {
         "BriefDescription": "ITLB miss page walk cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_CYCLES",
         "SampleAfterValue": "2000000",
@@ -121,7 +106,6 @@
     },
     {
         "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC8",
         "EventName": "ITLB_MISS_RETIRED",
         "PEBS": "1",
@@ -130,7 +114,6 @@
     },
     {
         "BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
         "PEBS": "1",
@@ -139,7 +122,6 @@
     },
     {
         "BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC",
         "EventName": "MEM_STORE_RETIRED.DTLB_MISS",
         "PEBS": "1",
-- 
GitLab


From 6abaa0204c34dc185783a23b0dbc35cdf9cc1399 Mon Sep 17 00:00:00 2001
From: Ian Rogers <irogers@google.com>
Date: Wed, 14 Dec 2022 22:55:10 -0800
Subject: [PATCH 594/875] perf vendor events intel: Refresh westmereex events

Update the westmereex events using the new tooling from:

  https://github.com/intel/perfmon

The events are unchanged but unused json values are removed. This
increases consistency across the json files.

Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-24-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../pmu-events/arch/x86/westmereex/cache.json | 516 ------------------
 .../arch/x86/westmereex/floating-point.json   |  28 -
 .../arch/x86/westmereex/frontend.json         |   3 -
 .../arch/x86/westmereex/memory.json           | 135 -----
 .../pmu-events/arch/x86/westmereex/other.json |  22 -
 .../arch/x86/westmereex/pipeline.json         | 129 +----
 .../arch/x86/westmereex/virtual-memory.json   |  21 -
 7 files changed, 5 insertions(+), 849 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/westmereex/cache.json b/tools/perf/pmu-events/arch/x86/westmereex/cache.json
index d6243d008bfe3..6c7c52733ddae 100644
--- a/tools/perf/pmu-events/arch/x86/westmereex/cache.json
+++ b/tools/perf/pmu-events/arch/x86/westmereex/cache.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Cycles L1D locked",
-        "Counter": "0,1",
         "EventCode": "0x63",
         "EventName": "CACHE_LOCK_CYCLES.L1D",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Cycles L1D and L2 locked",
-        "Counter": "0,1",
         "EventCode": "0x63",
         "EventName": "CACHE_LOCK_CYCLES.L1D_L2",
         "SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "L1D cache lines replaced in M state",
-        "Counter": "0,1",
         "EventCode": "0x51",
         "EventName": "L1D.M_EVICT",
         "SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "L1D cache lines allocated in the M state",
-        "Counter": "0,1",
         "EventCode": "0x51",
         "EventName": "L1D.M_REPL",
         "SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "L1D snoop eviction of cache lines in M state",
-        "Counter": "0,1",
         "EventCode": "0x51",
         "EventName": "L1D.M_SNOOP_EVICT",
         "SampleAfterValue": "2000000",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "L1 data cache lines allocated",
-        "Counter": "0,1",
         "EventCode": "0x51",
         "EventName": "L1D.REPL",
         "SampleAfterValue": "2000000",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "L1D prefetch load lock accepted in fill buffer",
-        "Counter": "0,1",
         "EventCode": "0x52",
         "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
         "SampleAfterValue": "2000000",
@@ -57,7 +50,6 @@
     },
     {
         "BriefDescription": "L1D hardware prefetch misses",
-        "Counter": "0,1",
         "EventCode": "0x4E",
         "EventName": "L1D_PREFETCH.MISS",
         "SampleAfterValue": "200000",
@@ -65,7 +57,6 @@
     },
     {
         "BriefDescription": "L1D hardware prefetch requests",
-        "Counter": "0,1",
         "EventCode": "0x4E",
         "EventName": "L1D_PREFETCH.REQUESTS",
         "SampleAfterValue": "200000",
@@ -73,7 +64,6 @@
     },
     {
         "BriefDescription": "L1D hardware prefetch requests triggered",
-        "Counter": "0,1",
         "EventCode": "0x4E",
         "EventName": "L1D_PREFETCH.TRIGGERS",
         "SampleAfterValue": "200000",
@@ -81,7 +71,6 @@
     },
     {
         "BriefDescription": "L1 writebacks to L2 in E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.E_STATE",
         "SampleAfterValue": "100000",
@@ -89,7 +78,6 @@
     },
     {
         "BriefDescription": "L1 writebacks to L2 in I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.I_STATE",
         "SampleAfterValue": "100000",
@@ -97,7 +85,6 @@
     },
     {
         "BriefDescription": "All L1 writebacks to L2",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.MESI",
         "SampleAfterValue": "100000",
@@ -105,7 +92,6 @@
     },
     {
         "BriefDescription": "L1 writebacks to L2 in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.M_STATE",
         "SampleAfterValue": "100000",
@@ -113,7 +99,6 @@
     },
     {
         "BriefDescription": "L1 writebacks to L2 in S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x28",
         "EventName": "L1D_WB_L2.S_STATE",
         "SampleAfterValue": "100000",
@@ -121,7 +106,6 @@
     },
     {
         "BriefDescription": "All L2 data requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.ANY",
         "SampleAfterValue": "200000",
@@ -129,7 +113,6 @@
     },
     {
         "BriefDescription": "L2 data demand loads in E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
         "SampleAfterValue": "200000",
@@ -137,7 +120,6 @@
     },
     {
         "BriefDescription": "L2 data demand loads in I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
         "SampleAfterValue": "200000",
@@ -145,7 +127,6 @@
     },
     {
         "BriefDescription": "L2 data demand requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.MESI",
         "SampleAfterValue": "200000",
@@ -153,7 +134,6 @@
     },
     {
         "BriefDescription": "L2 data demand loads in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
         "SampleAfterValue": "200000",
@@ -161,7 +141,6 @@
     },
     {
         "BriefDescription": "L2 data demand loads in S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
         "SampleAfterValue": "200000",
@@ -169,7 +148,6 @@
     },
     {
         "BriefDescription": "L2 data prefetches in E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
         "SampleAfterValue": "200000",
@@ -177,7 +155,6 @@
     },
     {
         "BriefDescription": "L2 data prefetches in the I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
         "SampleAfterValue": "200000",
@@ -185,7 +162,6 @@
     },
     {
         "BriefDescription": "All L2 data prefetches",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
         "SampleAfterValue": "200000",
@@ -193,7 +169,6 @@
     },
     {
         "BriefDescription": "L2 data prefetches in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
         "SampleAfterValue": "200000",
@@ -201,7 +176,6 @@
     },
     {
         "BriefDescription": "L2 data prefetches in the S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x26",
         "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
         "SampleAfterValue": "200000",
@@ -209,7 +183,6 @@
     },
     {
         "BriefDescription": "L2 lines alloacated",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.ANY",
         "SampleAfterValue": "100000",
@@ -217,7 +190,6 @@
     },
     {
         "BriefDescription": "L2 lines allocated in the E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.E_STATE",
         "SampleAfterValue": "100000",
@@ -225,7 +197,6 @@
     },
     {
         "BriefDescription": "L2 lines allocated in the S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF1",
         "EventName": "L2_LINES_IN.S_STATE",
         "SampleAfterValue": "100000",
@@ -233,7 +204,6 @@
     },
     {
         "BriefDescription": "L2 lines evicted",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.ANY",
         "SampleAfterValue": "100000",
@@ -241,7 +211,6 @@
     },
     {
         "BriefDescription": "L2 lines evicted by a demand request",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
         "SampleAfterValue": "100000",
@@ -249,7 +218,6 @@
     },
     {
         "BriefDescription": "L2 modified lines evicted by a demand request",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
         "SampleAfterValue": "100000",
@@ -257,7 +225,6 @@
     },
     {
         "BriefDescription": "L2 lines evicted by a prefetch request",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
         "SampleAfterValue": "100000",
@@ -265,7 +232,6 @@
     },
     {
         "BriefDescription": "L2 modified lines evicted by a prefetch request",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF2",
         "EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
         "SampleAfterValue": "100000",
@@ -273,7 +239,6 @@
     },
     {
         "BriefDescription": "L2 instruction fetches",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.IFETCHES",
         "SampleAfterValue": "200000",
@@ -281,7 +246,6 @@
     },
     {
         "BriefDescription": "L2 instruction fetch hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.IFETCH_HIT",
         "SampleAfterValue": "200000",
@@ -289,7 +253,6 @@
     },
     {
         "BriefDescription": "L2 instruction fetch misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.IFETCH_MISS",
         "SampleAfterValue": "200000",
@@ -297,7 +260,6 @@
     },
     {
         "BriefDescription": "L2 load hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.LD_HIT",
         "SampleAfterValue": "200000",
@@ -305,7 +267,6 @@
     },
     {
         "BriefDescription": "L2 load misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.LD_MISS",
         "SampleAfterValue": "200000",
@@ -313,7 +274,6 @@
     },
     {
         "BriefDescription": "L2 requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.LOADS",
         "SampleAfterValue": "200000",
@@ -321,7 +281,6 @@
     },
     {
         "BriefDescription": "All L2 misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.MISS",
         "SampleAfterValue": "200000",
@@ -329,7 +288,6 @@
     },
     {
         "BriefDescription": "All L2 prefetches",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PREFETCHES",
         "SampleAfterValue": "200000",
@@ -337,7 +295,6 @@
     },
     {
         "BriefDescription": "L2 prefetch hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PREFETCH_HIT",
         "SampleAfterValue": "200000",
@@ -345,7 +302,6 @@
     },
     {
         "BriefDescription": "L2 prefetch misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.PREFETCH_MISS",
         "SampleAfterValue": "200000",
@@ -353,7 +309,6 @@
     },
     {
         "BriefDescription": "All L2 requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.REFERENCES",
         "SampleAfterValue": "200000",
@@ -361,7 +316,6 @@
     },
     {
         "BriefDescription": "L2 RFO requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFOS",
         "SampleAfterValue": "200000",
@@ -369,7 +323,6 @@
     },
     {
         "BriefDescription": "L2 RFO hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_HIT",
         "SampleAfterValue": "200000",
@@ -377,7 +330,6 @@
     },
     {
         "BriefDescription": "L2 RFO misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x24",
         "EventName": "L2_RQSTS.RFO_MISS",
         "SampleAfterValue": "200000",
@@ -385,7 +337,6 @@
     },
     {
         "BriefDescription": "All L2 transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.ANY",
         "SampleAfterValue": "200000",
@@ -393,7 +344,6 @@
     },
     {
         "BriefDescription": "L2 fill transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.FILL",
         "SampleAfterValue": "200000",
@@ -401,7 +351,6 @@
     },
     {
         "BriefDescription": "L2 instruction fetch transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.IFETCH",
         "SampleAfterValue": "200000",
@@ -409,7 +358,6 @@
     },
     {
         "BriefDescription": "L1D writeback to L2 transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.L1D_WB",
         "SampleAfterValue": "200000",
@@ -417,7 +365,6 @@
     },
     {
         "BriefDescription": "L2 Load transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.LOAD",
         "SampleAfterValue": "200000",
@@ -425,7 +372,6 @@
     },
     {
         "BriefDescription": "L2 prefetch transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.PREFETCH",
         "SampleAfterValue": "200000",
@@ -433,7 +379,6 @@
     },
     {
         "BriefDescription": "L2 RFO transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.RFO",
         "SampleAfterValue": "200000",
@@ -441,7 +386,6 @@
     },
     {
         "BriefDescription": "L2 writeback to LLC transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF0",
         "EventName": "L2_TRANSACTIONS.WB",
         "SampleAfterValue": "200000",
@@ -449,7 +393,6 @@
     },
     {
         "BriefDescription": "L2 demand lock RFOs in E state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.E_STATE",
         "SampleAfterValue": "100000",
@@ -457,7 +400,6 @@
     },
     {
         "BriefDescription": "All demand L2 lock RFOs that hit the cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.HIT",
         "SampleAfterValue": "100000",
@@ -465,7 +407,6 @@
     },
     {
         "BriefDescription": "L2 demand lock RFOs in I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.I_STATE",
         "SampleAfterValue": "100000",
@@ -473,7 +414,6 @@
     },
     {
         "BriefDescription": "All demand L2 lock RFOs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.MESI",
         "SampleAfterValue": "100000",
@@ -481,7 +421,6 @@
     },
     {
         "BriefDescription": "L2 demand lock RFOs in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.M_STATE",
         "SampleAfterValue": "100000",
@@ -489,7 +428,6 @@
     },
     {
         "BriefDescription": "L2 demand lock RFOs in S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.LOCK.S_STATE",
         "SampleAfterValue": "100000",
@@ -497,7 +435,6 @@
     },
     {
         "BriefDescription": "All L2 demand store RFOs that hit the cache",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.HIT",
         "SampleAfterValue": "100000",
@@ -505,7 +442,6 @@
     },
     {
         "BriefDescription": "L2 demand store RFOs in I state (misses)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.I_STATE",
         "SampleAfterValue": "100000",
@@ -513,7 +449,6 @@
     },
     {
         "BriefDescription": "All L2 demand store RFOs",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.MESI",
         "SampleAfterValue": "100000",
@@ -521,7 +456,6 @@
     },
     {
         "BriefDescription": "L2 demand store RFOs in M state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.M_STATE",
         "SampleAfterValue": "100000",
@@ -529,7 +463,6 @@
     },
     {
         "BriefDescription": "L2 demand store RFOs in S state",
-        "Counter": "0,1,2,3",
         "EventCode": "0x27",
         "EventName": "L2_WRITE.RFO.S_STATE",
         "SampleAfterValue": "100000",
@@ -537,7 +470,6 @@
     },
     {
         "BriefDescription": "Longest latency cache miss",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.MISS",
         "SampleAfterValue": "100000",
@@ -545,7 +477,6 @@
     },
     {
         "BriefDescription": "Longest latency cache reference",
-        "Counter": "0,1,2,3",
         "EventCode": "0x2E",
         "EventName": "LONGEST_LAT_CACHE.REFERENCE",
         "SampleAfterValue": "200000",
@@ -553,18 +484,15 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
         "MSRIndex": "0x3F6",
-        "MSRValue": "0x0",
         "PEBS": "2",
         "SampleAfterValue": "2000000",
         "UMask": "0x10"
     },
     {
         "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
         "MSRIndex": "0x3F6",
@@ -575,7 +503,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
         "MSRIndex": "0x3F6",
@@ -586,7 +513,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
         "MSRIndex": "0x3F6",
@@ -597,7 +523,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
         "MSRIndex": "0x3F6",
@@ -608,7 +533,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
         "MSRIndex": "0x3F6",
@@ -619,7 +543,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
         "MSRIndex": "0x3F6",
@@ -630,7 +553,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
         "MSRIndex": "0x3F6",
@@ -641,7 +563,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
         "MSRIndex": "0x3F6",
@@ -652,7 +573,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
         "MSRIndex": "0x3F6",
@@ -663,7 +583,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
         "MSRIndex": "0x3F6",
@@ -674,7 +593,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
         "MSRIndex": "0x3F6",
@@ -685,7 +603,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
         "MSRIndex": "0x3F6",
@@ -696,7 +613,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
         "MSRIndex": "0x3F6",
@@ -707,7 +623,6 @@
     },
     {
         "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
-        "Counter": "3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
         "MSRIndex": "0x3F6",
@@ -718,7 +633,6 @@
     },
     {
         "BriefDescription": "Instructions retired which contains a load (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.LOADS",
         "PEBS": "1",
@@ -727,7 +641,6 @@
     },
     {
         "BriefDescription": "Instructions retired which contains a store (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB",
         "EventName": "MEM_INST_RETIRED.STORES",
         "PEBS": "1",
@@ -736,7 +649,6 @@
     },
     {
         "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.HIT_LFB",
         "PEBS": "1",
@@ -745,7 +657,6 @@
     },
     {
         "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.L1D_HIT",
         "PEBS": "1",
@@ -754,7 +665,6 @@
     },
     {
         "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.L2_HIT",
         "PEBS": "1",
@@ -763,7 +673,6 @@
     },
     {
         "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.LLC_MISS",
         "PEBS": "1",
@@ -772,7 +681,6 @@
     },
     {
         "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
         "PEBS": "1",
@@ -781,7 +689,6 @@
     },
     {
         "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
         "PEBS": "1",
@@ -790,7 +697,6 @@
     },
     {
         "BriefDescription": "Load instructions retired local dram and remote cache HIT data sources (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
         "PEBS": "1",
@@ -799,7 +705,6 @@
     },
     {
         "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "MEM_UNCORE_RETIRED.LOCAL_HITM",
         "PEBS": "1",
@@ -808,7 +713,6 @@
     },
     {
         "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM",
         "PEBS": "1",
@@ -817,7 +721,6 @@
     },
     {
         "BriefDescription": "Retired loads that hit remote socket in modified state (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "MEM_UNCORE_RETIRED.REMOTE_HITM",
         "PEBS": "1",
@@ -826,7 +729,6 @@
     },
     {
         "BriefDescription": "Load instructions retired IO (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF",
         "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE",
         "PEBS": "1",
@@ -835,7 +737,6 @@
     },
     {
         "BriefDescription": "All offcore requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ANY",
         "SampleAfterValue": "100000",
@@ -843,7 +744,6 @@
     },
     {
         "BriefDescription": "Offcore read requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ANY.READ",
         "SampleAfterValue": "100000",
@@ -851,7 +751,6 @@
     },
     {
         "BriefDescription": "Offcore RFO requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.ANY.RFO",
         "SampleAfterValue": "100000",
@@ -859,7 +758,6 @@
     },
     {
         "BriefDescription": "Offcore demand code read requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE",
         "SampleAfterValue": "100000",
@@ -867,7 +765,6 @@
     },
     {
         "BriefDescription": "Offcore demand data read requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA",
         "SampleAfterValue": "100000",
@@ -875,7 +772,6 @@
     },
     {
         "BriefDescription": "Offcore demand RFO requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.DEMAND.RFO",
         "SampleAfterValue": "100000",
@@ -883,7 +779,6 @@
     },
     {
         "BriefDescription": "Offcore L1 data cache writebacks",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB0",
         "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
         "SampleAfterValue": "100000",
@@ -951,7 +846,6 @@
     },
     {
         "BriefDescription": "Offcore requests blocked due to Super Queue full",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB2",
         "EventName": "OFFCORE_REQUESTS_SQ_FULL",
         "SampleAfterValue": "100000",
@@ -959,2240 +853,1833 @@
     },
     {
         "BriefDescription": "Offcore data reads satisfied by any cache or DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F11",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore data reads",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF11",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x111",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x211",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x411",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x711",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4711",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1811",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3811",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x811",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by any cache or DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F44",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore code reads",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF44",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x144",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x244",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x444",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x744",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4744",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1844",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3844",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x844",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by any cache or DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7FFF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFFFF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x80FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x47FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x18FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x38FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x10FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F22",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore RFO requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF22",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x122",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x222",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x422",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x722",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4722",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1822",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3822",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x822",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F08",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore writebacks",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF08",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x108",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x408",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x708",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4708",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1808",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3808",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x808",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F77",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore code or data read requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF77",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x177",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x277",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x477",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x777",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4777",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1877",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3877",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x877",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = any cache_dram",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F33",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = any location",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF33",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x133",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x233",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x433",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = local cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x733",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = local cache or dram",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4733",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1833",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = remote cache or dram",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3833",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x833",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F03",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore demand data requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF03",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x103",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x203",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x403",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x703",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4703",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1803",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3803",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x803",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F01",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore demand data reads",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF01",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x101",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x201",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x401",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x701",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4701",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1801",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3801",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x801",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F04",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore demand code reads",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF04",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x104",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x204",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x404",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x704",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4704",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1804",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3804",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x804",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F02",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore demand RFO requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF02",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x102",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x202",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x402",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x702",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4702",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1802",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3802",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x802",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F80",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore other requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF80",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8080",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x180",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x280",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x480",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x780",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4780",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1880",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3880",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1080",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x880",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F30",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore prefetch data requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF30",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8030",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x130",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x230",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x430",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x730",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4730",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1830",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3830",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1030",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x830",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F10",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore prefetch data reads",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF10",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x110",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x210",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x410",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x710",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4710",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1810",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3810",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x810",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F40",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore prefetch code reads",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF40",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x140",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x240",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x440",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x740",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4740",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1840",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3840",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x840",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F20",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore prefetch RFO requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF20",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x120",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x220",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x420",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x720",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4720",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1820",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3820",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x820",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x7F70",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "All offcore prefetch requests",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xFF70",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x8070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x170",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x270",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the LLC  and HITM in a sibling core",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x470",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x770",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4770",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1870",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x3870",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests that HIT in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x1070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests that HITM in a remote cache",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x870",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Super Queue LRU hints sent to LLC",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF4",
         "EventName": "SQ_MISC.LRU_HINTS",
         "SampleAfterValue": "2000000",
@@ -3200,7 +2687,6 @@
     },
     {
         "BriefDescription": "Super Queue lock splits across a cache line",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF4",
         "EventName": "SQ_MISC.SPLIT_LOCK",
         "SampleAfterValue": "2000000",
@@ -3208,7 +2694,6 @@
     },
     {
         "BriefDescription": "Loads delayed with at-Retirement block code",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "STORE_BLOCKS.AT_RET",
         "SampleAfterValue": "200000",
@@ -3216,7 +2701,6 @@
     },
     {
         "BriefDescription": "Cacheable loads delayed with L1D block code",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6",
         "EventName": "STORE_BLOCKS.L1D_BLOCK",
         "SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json b/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json
index 666e466d351c4..c03f8990fa82a 100644
--- a/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "X87 Floating point assists (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF7",
         "EventName": "FP_ASSIST.ALL",
         "PEBS": "1",
@@ -10,7 +9,6 @@
     },
     {
         "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF7",
         "EventName": "FP_ASSIST.INPUT",
         "PEBS": "1",
@@ -19,7 +17,6 @@
     },
     {
         "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF7",
         "EventName": "FP_ASSIST.OUTPUT",
         "PEBS": "1",
@@ -28,7 +25,6 @@
     },
     {
         "BriefDescription": "MMX Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.MMX",
         "SampleAfterValue": "2000000",
@@ -36,7 +32,6 @@
     },
     {
         "BriefDescription": "SSE2 integer Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
         "SampleAfterValue": "2000000",
@@ -44,7 +39,6 @@
     },
     {
         "BriefDescription": "SSE* FP double precision Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
         "SampleAfterValue": "2000000",
@@ -52,7 +46,6 @@
     },
     {
         "BriefDescription": "SSE and SSE2 FP Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_FP",
         "SampleAfterValue": "2000000",
@@ -60,7 +53,6 @@
     },
     {
         "BriefDescription": "SSE FP packed Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
         "SampleAfterValue": "2000000",
@@ -68,7 +60,6 @@
     },
     {
         "BriefDescription": "SSE FP scalar Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
         "SampleAfterValue": "2000000",
@@ -76,7 +67,6 @@
     },
     {
         "BriefDescription": "SSE* FP single precision Uops",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
         "SampleAfterValue": "2000000",
@@ -84,7 +74,6 @@
     },
     {
         "BriefDescription": "Computational floating-point operations executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x10",
         "EventName": "FP_COMP_OPS_EXE.X87",
         "SampleAfterValue": "2000000",
@@ -92,7 +81,6 @@
     },
     {
         "BriefDescription": "All Floating Point to and from MMX transitions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCC",
         "EventName": "FP_MMX_TRANS.ANY",
         "SampleAfterValue": "2000000",
@@ -100,7 +88,6 @@
     },
     {
         "BriefDescription": "Transitions from MMX to Floating Point instructions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCC",
         "EventName": "FP_MMX_TRANS.TO_FP",
         "SampleAfterValue": "2000000",
@@ -108,7 +95,6 @@
     },
     {
         "BriefDescription": "Transitions from Floating Point to MMX instructions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCC",
         "EventName": "FP_MMX_TRANS.TO_MMX",
         "SampleAfterValue": "2000000",
@@ -116,7 +102,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer pack operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACK",
         "SampleAfterValue": "200000",
@@ -124,7 +109,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer arithmetic operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_ARITH",
         "SampleAfterValue": "200000",
@@ -132,7 +116,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer logical operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_LOGICAL",
         "SampleAfterValue": "200000",
@@ -140,7 +123,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer multiply operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_MPY",
         "SampleAfterValue": "200000",
@@ -148,7 +130,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer shift operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.PACKED_SHIFT",
         "SampleAfterValue": "200000",
@@ -156,7 +137,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer shuffle/move operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.SHUFFLE_MOVE",
         "SampleAfterValue": "200000",
@@ -164,7 +144,6 @@
     },
     {
         "BriefDescription": "128 bit SIMD integer unpack operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0x12",
         "EventName": "SIMD_INT_128.UNPACK",
         "SampleAfterValue": "200000",
@@ -172,7 +151,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit pack operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACK",
         "SampleAfterValue": "200000",
@@ -180,7 +158,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit arithmetic operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_ARITH",
         "SampleAfterValue": "200000",
@@ -188,7 +165,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit logical operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_LOGICAL",
         "SampleAfterValue": "200000",
@@ -196,7 +172,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit packed multiply operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_MPY",
         "SampleAfterValue": "200000",
@@ -204,7 +179,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit shift operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.PACKED_SHIFT",
         "SampleAfterValue": "200000",
@@ -212,7 +186,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit shuffle/move operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.SHUFFLE_MOVE",
         "SampleAfterValue": "200000",
@@ -220,7 +193,6 @@
     },
     {
         "BriefDescription": "SIMD integer 64 bit unpack operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xFD",
         "EventName": "SIMD_INT_64.UNPACK",
         "SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/frontend.json b/tools/perf/pmu-events/arch/x86/westmereex/frontend.json
index c561ac24d91d1..f7f28510e3ae9 100644
--- a/tools/perf/pmu-events/arch/x86/westmereex/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/westmereex/frontend.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD0",
         "EventName": "MACRO_INSTS.DECODED",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Macro-fused instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA6",
         "EventName": "MACRO_INSTS.FUSIONS_DECODED",
         "SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "Two Uop instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0x19",
         "EventName": "TWO_UOP_INSTS_DECODED",
         "SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/memory.json b/tools/perf/pmu-events/arch/x86/westmereex/memory.json
index 1f8cfabe08c0a..f3c0d2d4bc6aa 100644
--- a/tools/perf/pmu-events/arch/x86/westmereex/memory.json
+++ b/tools/perf/pmu-events/arch/x86/westmereex/memory.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Misaligned store references",
-        "Counter": "0,1,2,3",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.STORE",
         "SampleAfterValue": "200000",
@@ -9,738 +8,604 @@
     },
     {
         "BriefDescription": "Offcore data reads satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF811",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2011",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF844",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code reads satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2044",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x60FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF8FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x40FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x20FF",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF822",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2022",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF808",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore writebacks to a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2008",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF877",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2077",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore request = all data, response = any LLC miss",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF833",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the local DRAM.",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2033",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF803",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2003",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF801",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2001",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF804",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2004",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF802",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2002",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6080",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF880",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore other requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2080",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6030",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF830",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4030",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2030",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF810",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2010",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF840",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2040",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF820",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2020",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by any DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x6070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests that missed the LLC",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS",
         "MSRIndex": "0x1A6",
         "MSRValue": "0xF870",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x4070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     },
     {
         "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM",
-        "Counter": "2",
         "EventCode": "0xB7",
         "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM",
         "MSRIndex": "0x1A6",
         "MSRValue": "0x2070",
-        "Offcore": "1",
         "SampleAfterValue": "100000",
         "UMask": "0x1"
     }
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/other.json b/tools/perf/pmu-events/arch/x86/westmereex/other.json
index 67bc34984fa80..4882749805646 100644
--- a/tools/perf/pmu-events/arch/x86/westmereex/other.json
+++ b/tools/perf/pmu-events/arch/x86/westmereex/other.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "ES segment renames",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD5",
         "EventName": "ES_REG_RENAMES",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "I/O transactions",
-        "Counter": "0,1,2,3",
         "EventCode": "0x6C",
         "EventName": "IO_TRANSACTIONS",
         "SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "L1I instruction fetch stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.CYCLES_STALLED",
         "SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "L1I instruction fetch hits",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.HITS",
         "SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "L1I instruction fetch misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.MISSES",
         "SampleAfterValue": "2000000",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "L1I Instruction fetches",
-        "Counter": "0,1,2,3",
         "EventCode": "0x80",
         "EventName": "L1I.READS",
         "SampleAfterValue": "2000000",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "Large ITLB hit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x82",
         "EventName": "LARGE_ITLB.HIT",
         "SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
     },
     {
         "BriefDescription": "Loads that partially overlap an earlier store",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3",
         "EventName": "LOAD_BLOCK.OVERLAP_STORE",
         "SampleAfterValue": "200000",
@@ -65,7 +57,6 @@
     },
     {
         "BriefDescription": "All loads dispatched",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.ANY",
         "SampleAfterValue": "2000000",
@@ -73,7 +64,6 @@
     },
     {
         "BriefDescription": "Loads dispatched from the MOB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.MOB",
         "SampleAfterValue": "2000000",
@@ -81,7 +71,6 @@
     },
     {
         "BriefDescription": "Loads dispatched that bypass the MOB",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.RS",
         "SampleAfterValue": "2000000",
@@ -89,7 +78,6 @@
     },
     {
         "BriefDescription": "Loads dispatched from stage 305",
-        "Counter": "0,1,2,3",
         "EventCode": "0x13",
         "EventName": "LOAD_DISPATCH.RS_DELAYED",
         "SampleAfterValue": "2000000",
@@ -97,7 +85,6 @@
     },
     {
         "BriefDescription": "False dependencies due to partial address aliasing",
-        "Counter": "0,1,2,3",
         "EventCode": "0x7",
         "EventName": "PARTIAL_ADDRESS_ALIAS",
         "SampleAfterValue": "200000",
@@ -105,7 +92,6 @@
     },
     {
         "BriefDescription": "All Store buffer stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4",
         "EventName": "SB_DRAIN.ANY",
         "SampleAfterValue": "200000",
@@ -113,7 +99,6 @@
     },
     {
         "BriefDescription": "Segment rename stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD4",
         "EventName": "SEG_RENAME_STALLS",
         "SampleAfterValue": "2000000",
@@ -121,7 +106,6 @@
     },
     {
         "BriefDescription": "Snoop code requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "SNOOPQ_REQUESTS.CODE",
         "SampleAfterValue": "100000",
@@ -129,7 +113,6 @@
     },
     {
         "BriefDescription": "Snoop data requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "SNOOPQ_REQUESTS.DATA",
         "SampleAfterValue": "100000",
@@ -137,7 +120,6 @@
     },
     {
         "BriefDescription": "Snoop invalidate requests",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB4",
         "EventName": "SNOOPQ_REQUESTS.INVALIDATE",
         "SampleAfterValue": "100000",
@@ -190,7 +172,6 @@
     },
     {
         "BriefDescription": "Thread responded HIT to snoop",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "SNOOP_RESPONSE.HIT",
         "SampleAfterValue": "100000",
@@ -198,7 +179,6 @@
     },
     {
         "BriefDescription": "Thread responded HITE to snoop",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "SNOOP_RESPONSE.HITE",
         "SampleAfterValue": "100000",
@@ -206,7 +186,6 @@
     },
     {
         "BriefDescription": "Thread responded HITM to snoop",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB8",
         "EventName": "SNOOP_RESPONSE.HITM",
         "SampleAfterValue": "100000",
@@ -214,7 +193,6 @@
     },
     {
         "BriefDescription": "Super Queue full stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xF6",
         "EventName": "SQ_FULL_STALL_CYCLES",
         "SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json b/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json
index 7d6c2c1e0db00..1c61d18a4b5fc 100644
--- a/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Cycles the divider is busy",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "ARITH.CYCLES_DIV_BUSY",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Divide Operations executed",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0x14",
@@ -20,7 +18,6 @@
     },
     {
         "BriefDescription": "Multiply operations executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x14",
         "EventName": "ARITH.MUL",
         "SampleAfterValue": "2000000",
@@ -28,7 +25,6 @@
     },
     {
         "BriefDescription": "BACLEAR asserted with bad target address",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE6",
         "EventName": "BACLEAR.BAD_TARGET",
         "SampleAfterValue": "2000000",
@@ -36,7 +32,6 @@
     },
     {
         "BriefDescription": "BACLEAR asserted, regardless of cause",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE6",
         "EventName": "BACLEAR.CLEAR",
         "SampleAfterValue": "2000000",
@@ -44,7 +39,6 @@
     },
     {
         "BriefDescription": "Instruction queue forced BACLEAR",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA7",
         "EventName": "BACLEAR_FORCE_IQ",
         "SampleAfterValue": "2000000",
@@ -52,7 +46,6 @@
     },
     {
         "BriefDescription": "Early Branch Prediciton Unit clears",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE8",
         "EventName": "BPU_CLEARS.EARLY",
         "SampleAfterValue": "2000000",
@@ -60,7 +53,6 @@
     },
     {
         "BriefDescription": "Late Branch Prediction Unit clears",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE8",
         "EventName": "BPU_CLEARS.LATE",
         "SampleAfterValue": "2000000",
@@ -68,7 +60,6 @@
     },
     {
         "BriefDescription": "Branch prediction unit missed call or return",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE5",
         "EventName": "BPU_MISSED_CALL_RET",
         "SampleAfterValue": "2000000",
@@ -76,7 +67,6 @@
     },
     {
         "BriefDescription": "Branch instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE0",
         "EventName": "BR_INST_DECODED",
         "SampleAfterValue": "2000000",
@@ -84,7 +74,6 @@
     },
     {
         "BriefDescription": "Branch instructions executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.ANY",
         "SampleAfterValue": "200000",
@@ -92,7 +81,6 @@
     },
     {
         "BriefDescription": "Conditional branch instructions executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.COND",
         "SampleAfterValue": "200000",
@@ -100,7 +88,6 @@
     },
     {
         "BriefDescription": "Unconditional branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.DIRECT",
         "SampleAfterValue": "200000",
@@ -108,7 +95,6 @@
     },
     {
         "BriefDescription": "Unconditional call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
         "SampleAfterValue": "20000",
@@ -116,7 +102,6 @@
     },
     {
         "BriefDescription": "Indirect call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
         "SampleAfterValue": "20000",
@@ -124,7 +109,6 @@
     },
     {
         "BriefDescription": "Indirect non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
         "SampleAfterValue": "20000",
@@ -132,7 +116,6 @@
     },
     {
         "BriefDescription": "Call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.NEAR_CALLS",
         "SampleAfterValue": "20000",
@@ -140,7 +123,6 @@
     },
     {
         "BriefDescription": "All non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.NON_CALLS",
         "SampleAfterValue": "200000",
@@ -148,7 +130,6 @@
     },
     {
         "BriefDescription": "Indirect return branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.RETURN_NEAR",
         "SampleAfterValue": "20000",
@@ -156,7 +137,6 @@
     },
     {
         "BriefDescription": "Taken branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x88",
         "EventName": "BR_INST_EXEC.TAKEN",
         "SampleAfterValue": "200000",
@@ -164,7 +144,6 @@
     },
     {
         "BriefDescription": "Retired branch instructions (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
@@ -173,7 +152,6 @@
     },
     {
         "BriefDescription": "Retired conditional branch instructions (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -182,7 +160,6 @@
     },
     {
         "BriefDescription": "Retired near call instructions (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -191,7 +168,6 @@
     },
     {
         "BriefDescription": "Mispredicted branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.ANY",
         "SampleAfterValue": "20000",
@@ -199,7 +175,6 @@
     },
     {
         "BriefDescription": "Mispredicted conditional branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.COND",
         "SampleAfterValue": "20000",
@@ -207,7 +182,6 @@
     },
     {
         "BriefDescription": "Mispredicted unconditional branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.DIRECT",
         "SampleAfterValue": "20000",
@@ -215,7 +189,6 @@
     },
     {
         "BriefDescription": "Mispredicted non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
         "SampleAfterValue": "2000",
@@ -223,7 +196,6 @@
     },
     {
         "BriefDescription": "Mispredicted indirect call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
         "SampleAfterValue": "2000",
@@ -231,7 +203,6 @@
     },
     {
         "BriefDescription": "Mispredicted indirect non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
         "SampleAfterValue": "2000",
@@ -239,7 +210,6 @@
     },
     {
         "BriefDescription": "Mispredicted call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.NEAR_CALLS",
         "SampleAfterValue": "2000",
@@ -247,7 +217,6 @@
     },
     {
         "BriefDescription": "Mispredicted non call branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.NON_CALLS",
         "SampleAfterValue": "20000",
@@ -255,7 +224,6 @@
     },
     {
         "BriefDescription": "Mispredicted return branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.RETURN_NEAR",
         "SampleAfterValue": "2000",
@@ -263,7 +231,6 @@
     },
     {
         "BriefDescription": "Mispredicted taken branches executed",
-        "Counter": "0,1,2,3",
         "EventCode": "0x89",
         "EventName": "BR_MISP_EXEC.TAKEN",
         "SampleAfterValue": "20000",
@@ -271,7 +238,6 @@
     },
     {
         "BriefDescription": "Mispredicted retired branch instructions (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
         "PEBS": "1",
@@ -280,7 +246,6 @@
     },
     {
         "BriefDescription": "Mispredicted conditional retired branches (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.CONDITIONAL",
         "PEBS": "1",
@@ -289,7 +254,6 @@
     },
     {
         "BriefDescription": "Mispredicted near retired calls (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC5",
         "EventName": "BR_MISP_RETIRED.NEAR_CALL",
         "PEBS": "1",
@@ -298,15 +262,11 @@
     },
     {
         "BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
-        "Counter": "Fixed counter 3",
-        "EventCode": "0x0",
         "EventName": "CPU_CLK_UNHALTED.REF",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.REF_P",
         "SampleAfterValue": "100000",
@@ -314,33 +274,25 @@
     },
     {
         "BriefDescription": "Cycles when thread is not halted (fixed counter)",
-        "Counter": "Fixed counter 2",
-        "EventCode": "0x0",
         "EventName": "CPU_CLK_UNHALTED.THREAD",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Cycles when thread is not halted (programmable counter)",
-        "Counter": "0,1,2,3",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Total CPU cycles",
-        "Counter": "0,1,2,3",
         "CounterMask": "2",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
         "Invert": "1",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Any Instruction Length Decoder stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.ANY",
         "SampleAfterValue": "2000000",
@@ -348,7 +300,6 @@
     },
     {
         "BriefDescription": "Instruction Queue full stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.IQ_FULL",
         "SampleAfterValue": "2000000",
@@ -356,7 +307,6 @@
     },
     {
         "BriefDescription": "Length Change Prefix stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.LCP",
         "SampleAfterValue": "2000000",
@@ -364,7 +314,6 @@
     },
     {
         "BriefDescription": "Stall cycles due to BPU MRU bypass",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.MRU",
         "SampleAfterValue": "2000000",
@@ -372,7 +321,6 @@
     },
     {
         "BriefDescription": "Regen stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x87",
         "EventName": "ILD_STALL.REGEN",
         "SampleAfterValue": "2000000",
@@ -380,7 +328,6 @@
     },
     {
         "BriefDescription": "Instructions that must be decoded by decoder 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0x18",
         "EventName": "INST_DECODED.DEC0",
         "SampleAfterValue": "2000000",
@@ -388,7 +335,6 @@
     },
     {
         "BriefDescription": "Instructions written to instruction queue.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x17",
         "EventName": "INST_QUEUE_WRITES",
         "SampleAfterValue": "2000000",
@@ -396,7 +342,6 @@
     },
     {
         "BriefDescription": "Cycles instructions are written to the instruction queue",
-        "Counter": "0,1,2,3",
         "EventCode": "0x1E",
         "EventName": "INST_QUEUE_WRITE_CYCLES",
         "SampleAfterValue": "2000000",
@@ -404,15 +349,11 @@
     },
     {
         "BriefDescription": "Instructions retired (fixed counter)",
-        "Counter": "Fixed counter 1",
-        "EventCode": "0x0",
         "EventName": "INST_RETIRED.ANY",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.ANY_P",
         "PEBS": "1",
@@ -421,7 +362,6 @@
     },
     {
         "BriefDescription": "Retired MMX instructions (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.MMX",
         "PEBS": "1",
@@ -430,7 +370,6 @@
     },
     {
         "BriefDescription": "Total cycles (Precise Event)",
-        "Counter": "0,1,2,3",
         "CounterMask": "16",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.TOTAL_CYCLES",
@@ -441,7 +380,6 @@
     },
     {
         "BriefDescription": "Total cycles (Precise Event)",
-        "Counter": "0,1,2,3",
         "CounterMask": "16",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
@@ -452,7 +390,6 @@
     },
     {
         "BriefDescription": "Retired floating-point operations (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.X87",
         "PEBS": "1",
@@ -461,7 +398,6 @@
     },
     {
         "BriefDescription": "Load operations conflicting with software prefetches",
-        "Counter": "0,1",
         "EventCode": "0x4C",
         "EventName": "LOAD_HIT_PRE",
         "SampleAfterValue": "200000",
@@ -469,7 +405,6 @@
     },
     {
         "BriefDescription": "Cycles when uops were delivered by the LSD",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.ACTIVE",
@@ -478,7 +413,6 @@
     },
     {
         "BriefDescription": "Cycles no uops were delivered by the LSD",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xA8",
         "EventName": "LSD.INACTIVE",
@@ -488,7 +422,6 @@
     },
     {
         "BriefDescription": "Loops that can't stream from the instruction queue",
-        "Counter": "0,1,2,3",
         "EventCode": "0x20",
         "EventName": "LSD_OVERFLOW",
         "SampleAfterValue": "2000000",
@@ -496,7 +429,6 @@
     },
     {
         "BriefDescription": "Cycles machine clear asserted",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.CYCLES",
         "SampleAfterValue": "20000",
@@ -504,7 +436,6 @@
     },
     {
         "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.MEM_ORDER",
         "SampleAfterValue": "20000",
@@ -512,7 +443,6 @@
     },
     {
         "BriefDescription": "Self-Modifying Code detected",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.SMC",
         "SampleAfterValue": "20000",
@@ -520,7 +450,6 @@
     },
     {
         "BriefDescription": "All RAT stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.ANY",
         "SampleAfterValue": "2000000",
@@ -528,7 +457,6 @@
     },
     {
         "BriefDescription": "Flag stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.FLAGS",
         "SampleAfterValue": "2000000",
@@ -536,7 +464,6 @@
     },
     {
         "BriefDescription": "Partial register stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.REGISTERS",
         "SampleAfterValue": "2000000",
@@ -544,7 +471,6 @@
     },
     {
         "BriefDescription": "ROB read port stalls cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.ROB_READ_PORT",
         "SampleAfterValue": "2000000",
@@ -552,7 +478,6 @@
     },
     {
         "BriefDescription": "Scoreboard stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD2",
         "EventName": "RAT_STALLS.SCOREBOARD",
         "SampleAfterValue": "2000000",
@@ -560,7 +485,6 @@
     },
     {
         "BriefDescription": "Resource related stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ANY",
         "SampleAfterValue": "2000000",
@@ -568,7 +492,6 @@
     },
     {
         "BriefDescription": "FPU control word write stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.FPCW",
         "SampleAfterValue": "2000000",
@@ -576,7 +499,6 @@
     },
     {
         "BriefDescription": "Load buffer stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.LOAD",
         "SampleAfterValue": "2000000",
@@ -584,7 +506,6 @@
     },
     {
         "BriefDescription": "MXCSR rename stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.MXCSR",
         "SampleAfterValue": "2000000",
@@ -592,7 +513,6 @@
     },
     {
         "BriefDescription": "Other Resource related stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.OTHER",
         "SampleAfterValue": "2000000",
@@ -600,7 +520,6 @@
     },
     {
         "BriefDescription": "ROB full stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.ROB_FULL",
         "SampleAfterValue": "2000000",
@@ -608,7 +527,6 @@
     },
     {
         "BriefDescription": "Reservation Station full stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.RS_FULL",
         "SampleAfterValue": "2000000",
@@ -616,7 +534,6 @@
     },
     {
         "BriefDescription": "Store buffer stall cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0xA2",
         "EventName": "RESOURCE_STALLS.STORE",
         "SampleAfterValue": "2000000",
@@ -624,7 +541,6 @@
     },
     {
         "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
         "PEBS": "1",
@@ -633,7 +549,6 @@
     },
     {
         "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
         "PEBS": "1",
@@ -642,7 +557,6 @@
     },
     {
         "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
         "PEBS": "1",
@@ -651,7 +565,6 @@
     },
     {
         "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
         "PEBS": "1",
@@ -660,7 +573,6 @@
     },
     {
         "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC7",
         "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
         "PEBS": "1",
@@ -669,7 +581,6 @@
     },
     {
         "BriefDescription": "Stack pointer instructions decoded",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "UOPS_DECODED.ESP_FOLDING",
         "SampleAfterValue": "2000000",
@@ -677,7 +588,6 @@
     },
     {
         "BriefDescription": "Stack pointer sync operations",
-        "Counter": "0,1,2,3",
         "EventCode": "0xD1",
         "EventName": "UOPS_DECODED.ESP_SYNC",
         "SampleAfterValue": "2000000",
@@ -685,7 +595,6 @@
     },
     {
         "BriefDescription": "Uops decoded by Microcode Sequencer",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xD1",
         "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
@@ -694,7 +603,6 @@
     },
     {
         "BriefDescription": "Cycles no Uops are decoded",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xD1",
         "EventName": "UOPS_DECODED.STALL_CYCLES",
@@ -705,7 +613,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles Uops executed on any port (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
@@ -715,7 +622,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
@@ -724,7 +630,6 @@
     },
     {
         "BriefDescription": "Uops executed on any port (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xB1",
@@ -735,7 +640,6 @@
     },
     {
         "BriefDescription": "Uops executed on ports 0-4 (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EdgeDetect": "1",
         "EventCode": "0xB1",
@@ -747,7 +651,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles no Uops issued on any port (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
@@ -758,7 +661,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
@@ -768,7 +670,6 @@
     },
     {
         "BriefDescription": "Uops executed on port 0",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT0",
         "SampleAfterValue": "2000000",
@@ -776,7 +677,6 @@
     },
     {
         "BriefDescription": "Uops issued on ports 0, 1 or 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT015",
         "SampleAfterValue": "2000000",
@@ -784,7 +684,6 @@
     },
     {
         "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
@@ -794,7 +693,6 @@
     },
     {
         "BriefDescription": "Uops executed on port 1",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT1",
         "SampleAfterValue": "2000000",
@@ -803,7 +701,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops issued on ports 2, 3 or 4",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT234_CORE",
         "SampleAfterValue": "2000000",
@@ -812,7 +709,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops executed on port 2 (core count)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT2_CORE",
         "SampleAfterValue": "2000000",
@@ -821,7 +717,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops executed on port 3 (core count)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT3_CORE",
         "SampleAfterValue": "2000000",
@@ -830,7 +725,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Uops executed on port 4 (core count)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT4_CORE",
         "SampleAfterValue": "2000000",
@@ -838,7 +732,6 @@
     },
     {
         "BriefDescription": "Uops executed on port 5",
-        "Counter": "0,1,2,3",
         "EventCode": "0xB1",
         "EventName": "UOPS_EXECUTED.PORT5",
         "SampleAfterValue": "2000000",
@@ -846,7 +739,6 @@
     },
     {
         "BriefDescription": "Uops issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.ANY",
         "SampleAfterValue": "2000000",
@@ -855,7 +747,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles no Uops were issued on any thread",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
@@ -866,7 +757,6 @@
     {
         "AnyThread": "1",
         "BriefDescription": "Cycles Uops were issued on either thread",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
@@ -875,7 +765,6 @@
     },
     {
         "BriefDescription": "Fused Uops issued",
-        "Counter": "0,1,2,3",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.FUSED",
         "SampleAfterValue": "2000000",
@@ -883,7 +772,6 @@
     },
     {
         "BriefDescription": "Cycles no Uops were issued",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xE",
         "EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -893,7 +781,6 @@
     },
     {
         "BriefDescription": "Cycles Uops are being retired",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
@@ -903,7 +790,6 @@
     },
     {
         "BriefDescription": "Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ANY",
         "PEBS": "1",
@@ -912,7 +798,6 @@
     },
     {
         "BriefDescription": "Macro-fused Uops retired (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.MACRO_FUSED",
         "PEBS": "1",
@@ -921,7 +806,6 @@
     },
     {
         "BriefDescription": "Retirement slots used (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
         "PEBS": "1",
@@ -930,7 +814,6 @@
     },
     {
         "BriefDescription": "Cycles Uops are not retiring (Precise Event)",
-        "Counter": "0,1,2,3",
         "CounterMask": "1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -941,7 +824,6 @@
     },
     {
         "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
-        "Counter": "0,1,2,3",
         "CounterMask": "16",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
@@ -952,7 +834,6 @@
     },
     {
         "BriefDescription": "Uop unfusions due to FP exceptions",
-        "Counter": "0,1,2,3",
         "EventCode": "0xDB",
         "EventName": "UOP_UNFUSION",
         "SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json b/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json
index 0c3501e6e5a32..6c92b2be2d06b 100644
--- a/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "DTLB load misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.ANY",
         "SampleAfterValue": "200000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "DTLB load miss large page walks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "DTLB load miss caused by low part of address",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.PDE_MISS",
         "SampleAfterValue": "200000",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "DTLB second level hit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
         "SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "DTLB load miss page walks complete",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "DTLB load miss page walk cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x8",
         "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",
         "SampleAfterValue": "200000",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "DTLB misses",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.ANY",
         "SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
     },
     {
         "BriefDescription": "DTLB miss large page walks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -65,7 +57,6 @@
     },
     {
         "BriefDescription": "DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE.",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.PDE_MISS",
         "SampleAfterValue": "200000",
@@ -73,7 +64,6 @@
     },
     {
         "BriefDescription": "DTLB first level misses but second level hit",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.STLB_HIT",
         "SampleAfterValue": "200000",
@@ -81,7 +71,6 @@
     },
     {
         "BriefDescription": "DTLB miss page walks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -89,7 +78,6 @@
     },
     {
         "BriefDescription": "DTLB miss page walk cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x49",
         "EventName": "DTLB_MISSES.WALK_CYCLES",
         "SampleAfterValue": "2000000",
@@ -97,7 +85,6 @@
     },
     {
         "BriefDescription": "Extended Page Table walk cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x4F",
         "EventName": "EPT.WALK_CYCLES",
         "SampleAfterValue": "2000000",
@@ -105,7 +92,6 @@
     },
     {
         "BriefDescription": "ITLB flushes",
-        "Counter": "0,1,2,3",
         "EventCode": "0xAE",
         "EventName": "ITLB_FLUSH",
         "SampleAfterValue": "2000000",
@@ -113,7 +99,6 @@
     },
     {
         "BriefDescription": "ITLB miss",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.ANY",
         "SampleAfterValue": "200000",
@@ -121,7 +106,6 @@
     },
     {
         "BriefDescription": "ITLB miss large page walks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -129,7 +113,6 @@
     },
     {
         "BriefDescription": "ITLB miss page walks",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_COMPLETED",
         "SampleAfterValue": "200000",
@@ -137,7 +120,6 @@
     },
     {
         "BriefDescription": "ITLB miss page walk cycles",
-        "Counter": "0,1,2,3",
         "EventCode": "0x85",
         "EventName": "ITLB_MISSES.WALK_CYCLES",
         "SampleAfterValue": "2000000",
@@ -145,7 +127,6 @@
     },
     {
         "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC8",
         "EventName": "ITLB_MISS_RETIRED",
         "PEBS": "1",
@@ -154,7 +135,6 @@
     },
     {
         "BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
         "PEBS": "1",
@@ -163,7 +143,6 @@
     },
     {
         "BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
-        "Counter": "0,1,2,3",
         "EventCode": "0xC",
         "EventName": "MEM_STORE_RETIRED.DTLB_MISS",
         "PEBS": "1",
-- 
GitLab


From 658448281d190c1467295914b2e9c1a4490e41b8 Mon Sep 17 00:00:00 2001
From: Sandipan Das <sandipan.das@amd.com>
Date: Wed, 14 Dec 2022 13:56:49 +0530
Subject: [PATCH 595/875] perf vendor events amd: Add Zen 4 core events

Add core events taken from Section 2.1.15.4 "Core Performance Monitor
Counters" in the Processor Programming Reference (PPR) for AMD Family
19h Model 11h Revision B1 processors. This constitutes events which
capture op dispatch, execution and retirement, branch prediction, L1
and L2 cache activity, TLB activity, etc.

Signed-off-by: Sandipan Das <sandipan.das@amd.com>
Acked-by: Ian Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ananth Narayan <ananth.narayan@amd.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Jirka Hladky <jhladky@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@amd.com>
Cc: Stephane Eranian <eranian@google.com>
Link: https://lore.kernel.org/r/20221214082652.419965-2-sandipan.das@amd.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../pmu-events/arch/x86/amdzen4/branch.json   |  82 ++
 .../pmu-events/arch/x86/amdzen4/cache.json    | 653 ++++++++++++++
 .../pmu-events/arch/x86/amdzen4/core.json     | 122 +++
 .../arch/x86/amdzen4/floating-point.json      | 818 ++++++++++++++++++
 .../pmu-events/arch/x86/amdzen4/memory.json   | 174 ++++
 .../pmu-events/arch/x86/amdzen4/other.json    | 138 +++
 6 files changed, 1987 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/x86/amdzen4/branch.json
 create mode 100644 tools/perf/pmu-events/arch/x86/amdzen4/cache.json
 create mode 100644 tools/perf/pmu-events/arch/x86/amdzen4/core.json
 create mode 100644 tools/perf/pmu-events/arch/x86/amdzen4/floating-point.json
 create mode 100644 tools/perf/pmu-events/arch/x86/amdzen4/memory.json
 create mode 100644 tools/perf/pmu-events/arch/x86/amdzen4/other.json

diff --git a/tools/perf/pmu-events/arch/x86/amdzen4/branch.json b/tools/perf/pmu-events/arch/x86/amdzen4/branch.json
new file mode 100644
index 0000000000000..208c646c59ca4
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/amdzen4/branch.json
@@ -0,0 +1,82 @@
+[
+  {
+    "EventName": "bp_l2_btb_correct",
+    "EventCode": "0x8b",
+    "BriefDescription": "L2 branch prediction overrides existing prediction (speculative)."
+  },
+  {
+    "EventName": "bp_dyn_ind_pred",
+    "EventCode": "0x8e",
+    "BriefDescription": "Dynamic indirect predictions (branch used the indirect predictor to make a prediction)."
+  },
+  {
+    "EventName": "bp_de_redirect",
+    "EventCode": "0x91",
+    "BriefDescription": "Instruction decoder corrects the predicted target and resteers the branch predictor."
+  },
+  {
+    "EventName": "ex_ret_brn",
+    "EventCode": "0xc2",
+    "BriefDescription": "Retired branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."
+  },
+  {
+    "EventName": "ex_ret_brn_misp",
+    "EventCode": "0xc3",
+    "BriefDescription": "Retired branch instructions mispredicted."
+  },
+  {
+    "EventName": "ex_ret_brn_tkn",
+    "EventCode": "0xc4",
+    "BriefDescription": "Retired taken branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."
+  },
+  {
+    "EventName": "ex_ret_brn_tkn_misp",
+    "EventCode": "0xc5",
+    "BriefDescription": "Retired taken branch instructions mispredicted."
+  },
+  {
+    "EventName": "ex_ret_brn_far",
+    "EventCode": "0xc6",
+    "BriefDescription": "Retired far control transfers (far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts). Far control transfers are not subject to branch prediction."
+  },
+  {
+    "EventName": "ex_ret_near_ret",
+    "EventCode": "0xc8",
+    "BriefDescription": "Retired near returns (RET or RET Iw)."
+  },
+  {
+    "EventName": "ex_ret_near_ret_mispred",
+    "EventCode": "0xc9",
+    "BriefDescription": "Retired near returns mispredicted. Each misprediction incurs the same penalty as a mispredicted conditional branch instruction."
+  },
+  {
+    "EventName": "ex_ret_brn_ind_misp",
+    "EventCode": "0xca",
+    "BriefDescription": "Retired indirect branch instructions mispredicted (only EX mispredicts). Each misprediction incurs the same penalty as a mispredicted conditional branch instruction."
+  },
+  {
+    "EventName": "ex_ret_ind_brch_instr",
+    "EventCode": "0xcc",
+    "BriefDescription": "Retired indirect branch instructions."
+  },
+  {
+    "EventName": "ex_ret_cond",
+    "EventCode": "0xd1",
+    "BriefDescription": "Retired conditional branch instructions."
+  },
+  {
+    "EventName": "ex_ret_msprd_brnch_instr_dir_msmtch",
+    "EventCode": "0x1c7",
+    "BriefDescription": "Retired branch instructions mispredicted due to direction mismatch."
+  },
+  {
+    "EventName": "ex_ret_uncond_brnch_instr_mispred",
+    "EventCode": "0x1c8",
+    "BriefDescription": "Retired unconditional indirect branch instructions mispredicted."
+  },
+  {
+    "EventName": "ex_ret_uncond_brnch_instr",
+    "EventCode": "0x1c9",
+    "BriefDescription": "Retired unconditional branch instructions."
+  }
+]
diff --git a/tools/perf/pmu-events/arch/x86/amdzen4/cache.json b/tools/perf/pmu-events/arch/x86/amdzen4/cache.json
new file mode 100644
index 0000000000000..323ffd4b1423a
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/amdzen4/cache.json
@@ -0,0 +1,653 @@
+[
+  {
+    "EventName": "ls_mab_alloc.load_store_allocations",
+    "EventCode": "0x41",
+    "BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store allocations.",
+    "UMask": "0x3f"
+  },
+  {
+    "EventName": "ls_mab_alloc.hardware_prefetcher_allocations",
+    "EventCode": "0x41",
+    "BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for hardware prefetcher allocations.",
+    "UMask": "0x40"
+  },
+  {
+    "EventName": "ls_mab_alloc.all_allocations",
+    "EventCode": "0x41",
+    "BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all types of allocations.",
+    "UMask": "0x7f"
+  },
+  {
+    "EventName": "ls_dmnd_fills_from_sys.local_l2",
+    "EventCode": "0x43",
+    "BriefDescription": "Demand data cache fills from local L2 cache.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "ls_dmnd_fills_from_sys.local_ccx",
+    "EventCode": "0x43",
+    "BriefDescription": "Demand data cache fills from L3 cache or different L2 cache in the same CCX.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "ls_dmnd_fills_from_sys.near_cache",
+    "EventCode": "0x43",
+    "BriefDescription": "Demand data cache fills from cache of another CCX when the address was in the same NUMA node.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "ls_dmnd_fills_from_sys.dram_io_near",
+    "EventCode": "0x43",
+    "BriefDescription": "Demand data cache fills from either DRAM or MMIO in the same NUMA node.",
+    "UMask": "0x08"
+  },
+  {
+    "EventName": "ls_dmnd_fills_from_sys.far_cache",
+    "EventCode": "0x43",
+    "BriefDescription": "Demand data cache fills from cache of another CCX when the address was in a different NUMA node.",
+    "UMask": "0x10"
+  },
+  {
+    "EventName": "ls_dmnd_fills_from_sys.dram_io_far",
+    "EventCode": "0x43",
+    "BriefDescription": "Demand data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket).",
+    "UMask": "0x40"
+  },
+  {
+    "EventName": "ls_dmnd_fills_from_sys.alternate_memories",
+    "EventCode": "0x43",
+    "BriefDescription": "Demand data cache fills from extension memory.",
+    "UMask": "0x80"
+  },
+  {
+    "EventName": "ls_dmnd_fills_from_sys.all",
+    "EventCode": "0x43",
+    "BriefDescription": "Demand data cache fills from all types of data sources.",
+    "UMask": "0xff"
+  },
+  {
+    "EventName": "ls_any_fills_from_sys.local_l2",
+    "EventCode": "0x44",
+    "BriefDescription": "Any data cache fills from local L2 cache.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "ls_any_fills_from_sys.local_ccx",
+    "EventCode": "0x44",
+    "BriefDescription": "Any data cache fills from L3 cache or different L2 cache in the same CCX.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "ls_any_fills_from_sys.local_all",
+    "EventCode": "0x44",
+    "BriefDescription": "Any data cache fills from local L2 cache or L3 cache or different L2 cache in the same CCX.",
+    "UMask": "0x03"
+  },
+  {
+    "EventName": "ls_any_fills_from_sys.near_cache",
+    "EventCode": "0x44",
+    "BriefDescription": "Any data cache fills from cache of another CCX when the address was in the same NUMA node.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "ls_any_fills_from_sys.dram_io_near",
+    "EventCode": "0x44",
+    "BriefDescription": "Any data cache fills from either DRAM or MMIO in the same NUMA node.",
+    "UMask": "0x08"
+  },
+  {
+    "EventName": "ls_any_fills_from_sys.far_cache",
+    "EventCode": "0x44",
+    "BriefDescription": "Any data cache fills from cache of another CCX when the address was in a different NUMA node.",
+    "UMask": "0x10"
+  },
+  {
+    "EventName": "ls_any_fills_from_sys.remote_cache",
+    "EventCode": "0x44",
+    "BriefDescription": "Any data cache fills from cache of another CCX when the address was in the same or a different NUMA node.",
+    "UMask": "0x14"
+  },
+  {
+    "EventName": "ls_any_fills_from_sys.dram_io_far",
+    "EventCode": "0x44",
+    "BriefDescription": "Any data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket).",
+    "UMask": "0x40"
+  },
+  {
+    "EventName": "ls_any_fills_from_sys.dram_io_all",
+    "EventCode": "0x44",
+    "BriefDescription": "Any data cache fills from either DRAM or MMIO in any NUMA node (same or different socket).",
+    "UMask": "0x48"
+  },
+  {
+    "EventName": "ls_any_fills_from_sys.far_all",
+    "EventCode": "0x44",
+    "BriefDescription": "Any data cache fills from either cache of another CCX, DRAM or MMIO when the address was in a different NUMA node (same or different socket).",
+    "UMask": "0x50"
+  },
+  {
+    "EventName": "ls_any_fills_from_sys.all_dram_io",
+    "EventCode": "0x44",
+    "BriefDescription": "Any data cache fills from either DRAM or MMIO in any NUMA node (same or different socket).",
+    "UMask": "0x48"
+  },
+  {
+    "EventName": "ls_any_fills_from_sys.alternate_memories",
+    "EventCode": "0x44",
+    "BriefDescription": "Any data cache fills from extension memory.",
+    "UMask": "0x80"
+  },
+  {
+    "EventName": "ls_any_fills_from_sys.all",
+    "EventCode": "0x44",
+    "BriefDescription": "Any data cache fills from all types of data sources.",
+    "UMask": "0xff"
+  },
+  {
+    "EventName": "ls_pref_instr_disp.prefetch",
+    "EventCode": "0x4b",
+    "BriefDescription": "Software prefetch instructions dispatched (speculative) of type PrefetchT0 (move data to all cache levels), T1 (move data to all cache levels except L1) and T2 (move data to all cache levels except L1 and L2).",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "ls_pref_instr_disp.prefetch_w",
+    "EventCode": "0x4b",
+    "BriefDescription": "Software prefetch instructions dispatched (speculative) of type PrefetchW (move data to L1 cache and mark it modifiable).",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "ls_pref_instr_disp.prefetch_nta",
+    "EventCode": "0x4b",
+    "BriefDescription": "Software prefetch instructions dispatched (speculative) of type PrefetchNTA (move data with minimum cache pollution i.e. non-temporal access).",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "ls_pref_instr_disp.all",
+    "EventCode": "0x4b",
+    "BriefDescription": "Software prefetch instructions dispatched (speculative) of all types.",
+    "UMask": "0x07"
+  },
+  {
+    "EventName": "ls_inef_sw_pref.data_pipe_sw_pf_dc_hit",
+    "EventCode": "0x52",
+    "BriefDescription": "Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a data cache hit.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "ls_inef_sw_pref.mab_mch_cnt",
+    "EventCode": "0x52",
+    "BriefDescription": "Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a match on an already allocated Miss Address Buffer (MAB).",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "ls_inef_sw_pref.all",
+    "EventCode": "0x52",
+    "BriefDescript6ion": "Software prefetches that did not fetch data outside of the processor core for any reason.",
+    "UMask": "0x03"
+  },
+  {
+    "EventName": "ls_sw_pf_dc_fills.local_l2",
+    "EventCode": "0x59",
+    "BriefDescription": "Software prefetch data cache fills from local L2 cache.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "ls_sw_pf_dc_fills.local_ccx",
+    "EventCode": "0x59",
+    "BriefDescription": "Software prefetch data cache fills from L3 cache or different L2 cache in the same CCX.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "ls_sw_pf_dc_fills.near_cache",
+    "EventCode": "0x59",
+    "BriefDescription": "Software prefetch data cache fills from cache of another CCX in the same NUMA node.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "ls_sw_pf_dc_fills.dram_io_near",
+    "EventCode": "0x59",
+    "BriefDescription": "Software prefetch data cache fills from either DRAM or MMIO in the same NUMA node.",
+    "UMask": "0x08"
+  },
+  {
+    "EventName": "ls_sw_pf_dc_fills.far_cache",
+    "EventCode": "0x59",
+    "BriefDescription": "Software prefetch data cache fills from cache of another CCX in a different NUMA node.",
+    "UMask": "0x10"
+  },
+  {
+    "EventName": "ls_sw_pf_dc_fills.dram_io_far",
+    "EventCode": "0x59",
+    "BriefDescription": "Software prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket).",
+    "UMask": "0x40"
+  },
+  {
+    "EventName": "ls_sw_pf_dc_fills.alternate_memories",
+    "EventCode": "0x59",
+    "BriefDescription": "Software prefetch data cache fills from extension memory.",
+    "UMask": "0x80"
+  },
+  {
+    "EventName": "ls_sw_pf_dc_fills.all",
+    "EventCode": "0x59",
+    "BriefDescription": "Software prefetch data cache fills from all types of data sources.",
+    "UMask": "0xdf"
+  },
+  {
+    "EventName": "ls_hw_pf_dc_fills.local_l2",
+    "EventCode": "0x5a",
+    "BriefDescription": "Hardware prefetch data cache fills from local L2 cache.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "ls_hw_pf_dc_fills.local_ccx",
+    "EventCode": "0x5a",
+    "BriefDescription": "Hardware prefetch data cache fills from L3 cache or different L2 cache in the same CCX.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "ls_hw_pf_dc_fills.near_cache",
+    "EventCode": "0x5a",
+    "BriefDescription": "Hardware prefetch data cache fills from cache of another CCX when the address was in the same NUMA node.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "ls_hw_pf_dc_fills.dram_io_near",
+    "EventCode": "0x5a",
+    "BriefDescription": "Hardware prefetch data cache fills from either DRAM or MMIO in the same NUMA node.",
+    "UMask": "0x08"
+  },
+  {
+    "EventName": "ls_hw_pf_dc_fills.far_cache",
+    "EventCode": "0x5a",
+    "BriefDescription": "Hardware prefetch data cache fills from cache of another CCX when the address was in a different NUMA node.",
+    "UMask": "0x10"
+  },
+  {
+    "EventName": "ls_hw_pf_dc_fills.dram_io_far",
+    "EventCode": "0x5a",
+    "BriefDescription": "Hardware prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket).",
+    "UMask": "0x40"
+  },
+  {
+    "EventName": "ls_hw_pf_dc_fills.alternate_memories",
+    "EventCode": "0x5a",
+    "BriefDescription": "Hardware prefetch data cache fills from extension memory.",
+    "UMask": "0x80"
+  },
+  {
+    "EventName": "ls_hw_pf_dc_fills.all",
+    "EventCode": "0x5a",
+    "BriefDescription": "Hardware prefetch data cache fills from all types of data sources.",
+    "UMask": "0xdf"
+  },
+  {
+    "EventName": "ls_alloc_mab_count",
+    "EventCode": "0x5f",
+    "BriefDescription": "In-flight L1 data cache misses i.e. Miss Address Buffer (MAB) allocations each cycle."
+  },
+  {
+    "EventName": "l2_request_g1.group2",
+    "EventCode": "0x60",
+    "BriefDescription": "L2 cache requests of non-cacheable type (non-cached data and instructions reads, self-modifying code checks).",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "l2_request_g1.l2_hw_pf",
+    "EventCode": "0x60",
+    "BriefDescription": "L2 cache requests: from hardware prefetchers to prefetch directly into L2 (hit or miss).",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "l2_request_g1.prefetch_l2_cmd",
+    "EventCode": "0x60",
+    "BriefDescription": "L2 cache requests: prefetch directly into L2.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "l2_request_g1.change_to_x",
+    "EventCode": "0x60",
+    "BriefDescription": "L2 cache requests: data cache state change to writable, check L2 for current state.",
+    "UMask": "0x08"
+  },
+  {
+    "EventName": "l2_request_g1.cacheable_ic_read",
+    "EventCode": "0x60",
+    "BriefDescription": "L2 cache requests: instruction cache reads.",
+    "UMask": "0x10"
+  },
+  {
+    "EventName": "l2_request_g1.ls_rd_blk_c_s",
+    "EventCode": "0x60",
+    "BriefDescription": "L2 cache requests: data cache shared reads.",
+    "UMask": "0x20"
+  },
+  {
+    "EventName": "l2_request_g1.rd_blk_x",
+    "EventCode": "0x60",
+    "BriefDescription": "L2 cache requests: data cache stores.",
+    "UMask": "0x40"
+  },
+  {
+    "EventName": "l2_request_g1.rd_blk_l",
+    "EventCode": "0x60",
+    "BriefDescription": "L2 cache requests: data cache reads including hardware and software prefetch.",
+    "UMask": "0x80"
+  },
+  {
+    "EventName": "l2_request_g1.all_dc",
+    "EventCode": "0x60",
+    "BriefDescription": "L2 cache requests of common types from L1 data cache (including prefetches).",
+    "UMask": "0xe8"
+  },
+  {
+    "EventName": "l2_request_g1.all_no_prefetch",
+    "EventCode": "0x60",
+    "BriefDescription": "L2 cache requests of common types not including prefetches.",
+    "UMask": "0xf9"
+  },
+  {
+    "EventName": "l2_request_g1.all",
+    "EventCode": "0x60",
+    "BriefDescription": "L2 cache requests of all types.",
+    "UMask": "0xff"
+  },
+  {
+    "EventName": "l2_cache_req_stat.ic_fill_miss",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cache request miss in L2.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "l2_cache_req_stat.ic_fill_hit_s",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit non-modifiable line in L2.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "l2_cache_req_stat.ic_fill_hit_x",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit modifiable line in L2.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "l2_cache_req_stat.ic_hit_in_l2",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for instruction cache hits.",
+    "UMask": "0x06"
+  },
+  {
+    "EventName": "l2_cache_req_stat.ic_access_in_l2",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for instruction cache access.",
+    "UMask": "0x07"
+  },
+  {
+    "EventName": "l2_cache_req_stat.ls_rd_blk_c",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache request miss in L2.",
+    "UMask": "0x08"
+  },
+  {
+    "EventName": "l2_cache_req_stat.ic_dc_miss_in_l2",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instruction cache misses.",
+    "UMask": "0x09"
+  },
+  {
+    "EventName": "l2_cache_req_stat.ls_rd_blk_x",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache store or state change hit in L2.",
+    "UMask": "0x10"
+  },
+  {
+    "EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_s",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit non-modifiable line in L2.",
+    "UMask": "0x20"
+  },
+  {
+    "EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_x",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit modifiable line in L2.",
+    "UMask": "0x40"
+  },
+  {
+    "EventName": "l2_cache_req_stat.ls_rd_blk_cs",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache shared read hit in L2.",
+    "UMask": "0x80"
+  },
+  {
+    "EventName": "l2_cache_req_stat.dc_hit_in_l2",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data cache hits.",
+    "UMask": "0xf0"
+  },
+  {
+    "EventName": "l2_cache_req_stat.ic_dc_hit_in_l2",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instruction cache hits.",
+    "UMask": "0xf6"
+  },
+  {
+    "EventName": "l2_cache_req_stat.dc_access_in_l2",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data cache access.",
+    "UMask": "0xf8"
+  },
+  {
+    "EventName": "l2_cache_req_stat.all",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instruction cache access.",
+    "UMask": "0xff"
+  },
+  {
+    "EventName": "l2_pf_hit_l2.l2_stream",
+    "EventCode": "0x70",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Stream (fetch additional sequential lines into L2 cache).",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "l2_pf_hit_l2.l2_next_line",
+    "EventCode": "0x70",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2NextLine (fetch the next line into L2 cache).",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "l2_pf_hit_l2.l2_up_down",
+    "EventCode": "0x70",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses).",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "l2_pf_hit_l2.l2_burst",
+    "EventCode": "0x70",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Burst (aggressively fetch additional sequential lines into L2 cache).",
+    "UMask": "0x08"
+  },
+  {
+    "EventName": "l2_pf_hit_l2.l2_stride",
+    "EventCode": "0x70",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Stride (fetch additional lines into L2 cache when each access is at a constant distance from the previous).",
+    "UMask": "0x10"
+  },
+  {
+    "EventName": "l2_pf_hit_l2.l1_stream",
+    "EventCode": "0x70",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Stream (fetch additional sequential lines into L1 cache).",
+    "UMask": "0x20"
+  },
+  {
+    "EventName": "l2_pf_hit_l2.l1_stride",
+    "EventCode": "0x70",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous).",
+    "UMask": "0x40"
+  },
+  {
+    "EventName": "l2_pf_hit_l2.l1_region",
+    "EventCode": "0x70",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region).",
+    "UMask": "0x80"
+  },
+  {
+    "EventName": "l2_pf_hit_l2.all",
+    "EventCode": "0x70",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of all types.",
+    "UMask": "0xff"
+  },
+  {
+    "EventName": "l2_pf_miss_l2_hit_l3.l2_stream",
+    "EventCode": "0x71",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Stream (fetch additional sequential lines into L2 cache).",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "l2_pf_miss_l2_hit_l3.l2_next_line",
+    "EventCode": "0x71",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2NextLine (fetch the next line into L2 cache).",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "l2_pf_miss_l2_hit_l3.l2_up_down",
+    "EventCode": "0x71",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses).",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "l2_pf_miss_l2_hit_l3.l2_burst",
+    "EventCode": "0x71",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Burst (aggressively fetch additional sequential lines into L2 cache).",
+    "UMask": "0x08"
+  },
+  {
+    "EventName": "l2_pf_miss_l2_hit_l3.l2_stride",
+    "EventCode": "0x71",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Stride (fetch additional lines into L2 cache when each access is a constant distance from the previous).",
+    "UMask": "0x10"
+  },
+  {
+    "EventName": "l2_pf_miss_l2_hit_l3.l1_stream",
+    "EventCode": "0x71",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Stream (fetch additional sequential lines into L1 cache).",
+    "UMask": "0x20"
+  },
+  {
+    "EventName": "l2_pf_miss_l2_hit_l3.l1_stride",
+    "EventCode": "0x71",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous).",
+    "UMask": "0x40"
+  },
+  {
+    "EventName": "l2_pf_miss_l2_hit_l3.l1_region",
+    "EventCode": "0x71",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region).",
+    "UMask": "0x80"
+  },
+  {
+    "EventName": "l2_pf_miss_l2_hit_l3.all",
+    "EventCode": "0x71",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache cache of all types.",
+    "UMask": "0xff"
+  },
+  {
+    "EventName": "l2_pf_miss_l2_l3.l2_stream",
+    "EventCode": "0x72",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Stream (fetch additional sequential lines into L2 cache).",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "l2_pf_miss_l2_l3.l2_next_line",
+    "EventCode": "0x72",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2NextLine (fetch the next line into L2 cache).",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "l2_pf_miss_l2_l3.l2_up_down",
+    "EventCode": "0x72",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses).",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "l2_pf_miss_l2_l3.l2_burst",
+    "EventCode": "0x72",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Burst (aggressively fetch additional sequential lines into L2 cache).",
+    "UMask": "0x08"
+  },
+  {
+    "EventName": "l2_pf_miss_l2_l3.l2_stride",
+    "EventCode": "0x72",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Stride (fetch additional lines into L2 cache when each access is a constant distance from the previous).",
+    "UMask": "0x10"
+  },
+  {
+    "EventName": "l2_pf_miss_l2_l3.l1_stream",
+    "EventCode": "0x72",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Stream (fetch additional sequential lines into L1 cache).",
+    "UMask": "0x20"
+  },
+  {
+    "EventName": "l2_pf_miss_l2_l3.l1_stride",
+    "EventCode": "0x72",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous).",
+    "UMask": "0x40"
+  },
+  {
+    "EventName": "l2_pf_miss_l2_l3.l1_region",
+    "EventCode": "0x72",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region).",
+    "UMask": "0x80"
+  },
+  {
+    "EventName": "l2_pf_miss_l2_l3.all",
+    "EventCode": "0x72",
+    "BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of all types.",
+    "UMask": "0xff"
+  },
+  {
+    "EventName": "ic_cache_fill_l2",
+    "EventCode": "0x82",
+    "BriefDescription": "Instruction cache lines (64 bytes) fulfilled from the L2 cache."
+  },
+  {
+    "EventName": "ic_cache_fill_sys",
+    "EventCode": "0x83",
+    "BriefDescription": "Instruction cache lines (64 bytes) fulfilled from system memory or another cache."
+  },
+  {
+    "EventName": "ic_tag_hit_miss.instruction_cache_hit",
+    "EventCode": "0x18e",
+    "BriefDescription": "Instruction cache hits.",
+    "UMask": "0x07"
+  },
+  {
+    "EventName": "ic_tag_hit_miss.instruction_cache_miss",
+    "EventCode": "0x18e",
+    "BriefDescription": "Instruction cache misses.",
+    "UMask": "0x18"
+  },
+  {
+    "EventName": "ic_tag_hit_miss.all_instruction_cache_accesses",
+    "EventCode": "0x18e",
+    "BriefDescription": "Instruction cache accesses of all types.",
+    "UMask": "0x1f"
+  },
+  {
+    "EventName": "op_cache_hit_miss.op_cache_hit",
+    "EventCode": "0x28f",
+    "BriefDescription": "Op cache hits.",
+    "UMask": "0x03"
+  },
+  {
+    "EventName": "op_cache_hit_miss.op_cache_miss",
+    "EventCode": "0x28f",
+    "BriefDescription": "Op cache misses.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "op_cache_hit_miss.all_op_cache_accesses",
+    "EventCode": "0x28f",
+    "BriefDescription": "Op cache accesses of all types.",
+    "UMask": "0x07"
+  }
+]
diff --git a/tools/perf/pmu-events/arch/x86/amdzen4/core.json b/tools/perf/pmu-events/arch/x86/amdzen4/core.json
new file mode 100644
index 0000000000000..a56a41828bd43
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/amdzen4/core.json
@@ -0,0 +1,122 @@
+[
+  {
+    "EventName": "ls_locks.bus_lock",
+    "EventCode": "0x25",
+    "BriefDescription": "Retired Lock instructions which caused a bus lock.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "ls_ret_cl_flush",
+    "EventCode": "0x26",
+    "BriefDescription": "Retired CLFLUSH instructions."
+  },
+  {
+    "EventName": "ls_ret_cpuid",
+    "EventCode": "0x27",
+    "BriefDescription": "Retired CPUID instructions."
+  },
+  {
+    "EventName": "ls_smi_rx",
+    "EventCode": "0x2b",
+    "BriefDescription": "SMIs received."
+  },
+  {
+    "EventName": "ls_int_taken",
+    "EventCode": "0x2c",
+    "BriefDescription": "Interrupts taken."
+  },
+  {
+    "EventName": "ls_not_halted_cyc",
+    "EventCode": "0x76",
+    "BriefDescription": "Core cycles not in halt."
+  },
+  {
+    "EventName": "ex_ret_instr",
+    "EventCode": "0xc0",
+    "BriefDescription": "Retired instructions."
+  },
+  {
+    "EventName": "ex_ret_ops",
+    "EventCode": "0xc1",
+    "BriefDescription": "Retired macro-ops."
+  },
+  {
+    "EventName": "ex_div_busy",
+    "EventCode": "0xd3",
+    "BriefDescription": "Number of cycles the divider is busy."
+  },
+  {
+    "EventName": "ex_div_count",
+    "EventCode": "0xd4",
+    "BriefDescription": "Divide ops executed."
+  },
+  {
+    "EventName": "ex_no_retire.empty",
+    "EventCode": "0xd6",
+    "BriefDescription": "Cycles with no retire due  to the lack of valid ops in the retire queue (may be caused by front-end bottlenecks or pipeline redirects).",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "ex_no_retire.not_complete",
+    "EventCode": "0xd6",
+    "BriefDescription": "Cycles with no retire while the oldest op is waiting to be executed.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "ex_no_retire.other",
+    "EventCode": "0xd6",
+    "BriefDescription": "Cycles with no retire caused by other reasons (retire breaks, traps, faults, etc.).",
+    "UMask": "0x08"
+  },
+  {
+    "EventName": "ex_no_retire.thread_not_selected",
+    "EventCode": "0xd6",
+    "BriefDescription": "Cycles with no retire because thread arbitration did not select the thread.",
+    "UMask": "0x10"
+  },
+  {
+    "EventName": "ex_no_retire.load_not_complete",
+    "EventCode": "0xd6",
+    "BriefDescription": "Cycles with no retire while the oldest op is waiting for load data.",
+    "UMask": "0xa2"
+  },
+  {
+    "EventName": "ex_no_retire.all",
+    "EventCode": "0xd6",
+    "BriefDescription": "Cycles with no retire for any reason.",
+    "UMask": "0x1b"
+  },
+  {
+    "EventName": "ls_not_halted_p0_cyc.p0_freq_cyc",
+    "EventCode": "0x120",
+    "BriefDescription": "Reference cycles (P0 frequency) not in halt .",
+    "UMask": "0x1"
+  },
+  {
+    "EventName": "ex_ret_ucode_instr",
+    "EventCode": "0x1c1",
+    "BriefDescription": "Retired microcoded instructions."
+  },
+  {
+    "EventName": "ex_ret_ucode_ops",
+    "EventCode": "0x1c2",
+    "BriefDescription": "Retired microcode ops."
+  },
+  {
+    "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops",
+    "EventCode": "0x1cf",
+    "BriefDescription": "Ops tagged by IBS.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops_ret",
+    "EventCode": "0x1cf",
+    "BriefDescription": "Ops tagged by IBS that retired.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "ex_ret_fused_instr",
+    "EventCode": "0x1d0",
+    "BriefDescription": "Retired fused instructions."
+  }
+]
diff --git a/tools/perf/pmu-events/arch/x86/amdzen4/floating-point.json b/tools/perf/pmu-events/arch/x86/amdzen4/floating-point.json
new file mode 100644
index 0000000000000..cd7328fb79981
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/amdzen4/floating-point.json
@@ -0,0 +1,818 @@
+[
+  {
+    "EventName": "fp_ret_x87_fp_ops.add_sub_ops",
+    "EventCode": "0x02",
+    "BriefDescription": "Retired x87 floating-point add and subtract ops.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "fp_ret_x87_fp_ops.mul_ops",
+    "EventCode": "0x02",
+    "BriefDescription": "Retired x87 floating-point multiply ops.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "fp_ret_x87_fp_ops.div_sqrt_ops",
+    "EventCode": "0x02",
+    "BriefDescription": "Retired x87 floating-point divide and square root ops.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "fp_ret_x87_fp_ops.all",
+    "EventCode": "0x02",
+    "BriefDescription": "Retired x87 floating-point ops of all types.",
+    "UMask": "0x07"
+  },
+  {
+    "EventName": "fp_ret_sse_avx_ops.add_sub_flops",
+    "EventCode": "0x03",
+    "BriefDescription": "Retired SSE and AVX floating-point add and subtract ops.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "fp_ret_sse_avx_ops.mult_flops",
+    "EventCode": "0x03",
+    "BriefDescription": "Retired SSE and AVX floating-point multiply ops.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "fp_ret_sse_avx_ops.div_flops",
+    "EventCode": "0x03",
+    "BriefDescription": "Retired SSE and AVX floating-point divide and square root ops.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "fp_ret_sse_avx_ops.mac_flops",
+    "EventCode": "0x03",
+    "BriefDescription": "Retired SSE and AVX floating-point multiply-accumulate ops (each operation is counted as 2 ops).",
+    "UMask": "0x08"
+  },
+  {
+    "EventName": "fp_ret_sse_avx_ops.bfloat_mac_flops",
+    "EventCode": "0x03",
+    "BriefDescription": "Retired SSE and AVX floating-point bfloat multiply-accumulate ops (each operation is counted as 2 ops).",
+    "UMask": "0x10"
+  },
+  {
+    "EventName": "fp_ret_sse_avx_ops.all",
+    "EventCode": "0x03",
+    "BriefDescription": "Retired SSE and AVX floating-point ops of all types.",
+    "UMask": "0x1f"
+  },
+  {
+    "EventName": "fp_retired_ser_ops.x87_ctrl_ret",
+    "EventCode": "0x05",
+    "BriefDescription": "Retired x87 control word mispredict traps due to mispredictions in RC or PC, or changes in exception mask bits.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "fp_retired_ser_ops.x87_bot_ret",
+    "EventCode": "0x05",
+    "BriefDescription": "Retired x87 bottom-executing ops. Bottom-executing ops wait for all older ops to retire before executing.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "fp_retired_ser_ops.sse_ctrl_ret",
+    "EventCode": "0x05",
+    "BriefDescription": "Retired SSE and AVX control word mispredict traps.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "fp_retired_ser_ops.sse_bot_ret",
+    "EventCode": "0x05",
+    "BriefDescription": "Retired SSE and AVX bottom-executing ops. Bottom-executing ops wait for all older ops to retire before executing.",
+    "UMask": "0x08"
+  },
+  {
+    "EventName": "fp_retired_ser_ops.all",
+    "EventCode": "0x05",
+    "BriefDescription": "Retired SSE and AVX serializing ops of all types.",
+    "UMask": "0x0f"
+  },
+  {
+    "EventName": "fp_ops_retired_by_width.x87_uops_retired",
+    "EventCode": "0x08",
+    "BriefDescription": "Retired x87 floating-point ops.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "fp_ops_retired_by_width.mmx_uops_retired",
+    "EventCode": "0x08",
+    "BriefDescription": "Retired MMX floating-point ops.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "fp_ops_retired_by_width.scalar_uops_retired",
+    "EventCode": "0x08",
+    "BriefDescription": "Retired scalar floating-point ops.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "fp_ops_retired_by_width.pack_128_uops_retired",
+    "EventCode": "0x08",
+    "BriefDescription": "Retired packed 128-bit floating-point ops.",
+    "UMask": "0x08"
+  },
+  {
+    "EventName": "fp_ops_retired_by_width.pack_256_uops_retired",
+    "EventCode": "0x08",
+    "BriefDescription": "Retired packed 256-bit floating-point ops.",
+    "UMask": "0x10"
+  },
+  {
+    "EventName": "fp_ops_retired_by_width.pack_512_uops_retired",
+    "EventCode": "0x08",
+    "BriefDescription": "Retired packed 512-bit floating-point ops.",
+    "UMask": "0x20"
+  },
+  {
+    "EventName": "fp_ops_retired_by_width.all",
+    "EventCode": "0x08",
+    "BriefDescription": "Retired floating-point ops of all widths.",
+    "UMask": "0x3f"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.scalar_add",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired scalar floating-point add ops.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.scalar_sub",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired scalar floating-point subtract ops.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.scalar_mul",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired scalar floating-point multiply ops.",
+    "UMask": "0x03"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.scalar_mac",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired scalar floating-point multiply-accumulate ops.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.scalar_div",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired scalar floating-point divide ops.",
+    "UMask": "0x05"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.scalar_sqrt",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired scalar floating-point square root ops.",
+    "UMask": "0x06"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.scalar_cmp",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired scalar floating-point compare ops.",
+    "UMask": "0x07"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.scalar_cvt",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired scalar floating-point convert ops.",
+    "UMask": "0x08"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.scalar_blend",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired scalar floating-point blend ops.",
+    "UMask": "0x09"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.scalar_other",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired scalar floating-point ops of other types.",
+    "UMask": "0x0e"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.scalar_all",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired scalar floating-point ops of all types.",
+    "UMask": "0x0f"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.vector_add",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired vector floating-point add ops.",
+    "UMask": "0x10"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.vector_sub",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired vector floating-point subtract ops.",
+    "UMask": "0x20"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.vector_mul",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired vector floating-point multiply ops.",
+    "UMask": "0x30"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.vector_mac",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired vector floating-point multiply-accumulate ops.",
+    "UMask": "0x40"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.vector_div",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired vector floating-point divide ops.",
+    "UMask": "0x50"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.vector_sqrt",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired vector floating-point square root ops.",
+    "UMask": "0x60"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.vector_cmp",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired vector floating-point compare ops.",
+    "UMask": "0x70"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.vector_cvt",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired vector floating-point convert ops.",
+    "UMask": "0x80"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.vector_blend",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired vector floating-point blend ops.",
+    "UMask": "0x90"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.vector_shuffle",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired vector floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
+    "UMask": "0xb0"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.vector_logical",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired vector floating-point logical ops.",
+    "UMask": "0xd0"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.vector_other",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired vector floating-point ops of other types.",
+    "UMask": "0xe0"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.vector_all",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired vector floating-point ops of all types.",
+    "UMask": "0xf0"
+  },
+  {
+    "EventName": "fp_ops_retired_by_type.all",
+    "EventCode": "0x0a",
+    "BriefDescription": "Retired floating-point ops of all types.",
+    "UMask": "0xff"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.mmx_add",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired MMX integer add.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.mmx_sub",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired MMX integer subtract ops.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.mmx_mul",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired MMX integer multiply ops.",
+    "UMask": "0x03"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.mmx_mac",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired MMX integer multiply-accumulate ops.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.mmx_cmp",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired MMX integer compare ops.",
+    "UMask": "0x07"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.mmx_shift",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired MMX integer shift ops.",
+    "UMask": "0x09"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.mmx_mov",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired MMX integer MOV ops.",
+    "UMask": "0x0a"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.mmx_shuffle",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired MMX integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
+    "UMask": "0x0b"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.mmx_pack",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired MMX integer pack ops.",
+    "UMask": "0x0c"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.mmx_logical",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired MMX integer logical ops.",
+    "UMask": "0x0d"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.mmx_other",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired MMX integer multiply ops of other types.",
+    "UMask": "0x0e"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.mmx_all",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired MMX integer ops of all types.",
+    "UMask": "0x0f"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.sse_avx_add",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired SSE and AVX integer add ops.",
+    "UMask": "0x10"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.sse_avx_sub",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired SSE and AVX integer subtract ops.",
+    "UMask": "0x20"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.sse_avx_mul",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired SSE and AVX integer multiply ops.",
+    "UMask": "0x30"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.sse_avx_mac",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired SSE and AVX integer multiply-accumulate ops.",
+    "UMask": "0x40"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.sse_avx_aes",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired SSE and AVX integer AES ops.",
+    "UMask": "0x50"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.sse_avx_sha",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired SSE and AVX integer SHA ops.",
+    "UMask": "0x60"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.sse_avx_cmp",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired SSE and AVX integer compare ops.",
+    "UMask": "0x70"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.sse_avx_clm",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired SSE and AVX integer CLM ops.",
+    "UMask": "0x80"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.sse_avx_shift",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired SSE and AVX integer shift ops.",
+    "UMask": "0x90"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.sse_avx_mov",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired SSE and AVX integer MOV ops.",
+    "UMask": "0xa0"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.sse_avx_shuffle",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired SSE and AVX integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
+    "UMask": "0xb0"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.sse_avx_pack",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired SSE and AVX integer pack ops.",
+    "UMask": "0xc0"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.sse_avx_logical",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired SSE and AVX integer logical ops.",
+    "UMask": "0xd0"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.sse_avx_other",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired SSE and AVX integer ops of other types.",
+    "UMask": "0xe0"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.sse_avx_all",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired SSE and AVX integer ops of all types.",
+    "UMask": "0xf0"
+  },
+  {
+    "EventName": "sse_avx_ops_retired.all",
+    "EventCode": "0x0b",
+    "BriefDescription": "Retired SSE, AVX and MMX integer ops of all types.",
+    "UMask": "0xff"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp128_add",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 128-bit packed floating-point add ops.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp128_sub",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 128-bit packed floating-point subtract ops.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp128_mul",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 128-bit packed floating-point multiply ops.",
+    "UMask": "0x03"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp128_mac",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 128-bit packed floating-point multiply-accumulate ops.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp128_div",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 128-bit packed floating-point divide ops.",
+    "UMask": "0x05"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp128_sqrt",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 128-bit packed floating-point square root ops.",
+    "UMask": "0x06"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp128_cmp",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 128-bit packed floating-point compare ops.",
+    "UMask": "0x07"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp128_cvt",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 128-bit packed floating-point convert ops.",
+    "UMask": "0x08"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp128_blend",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 128-bit packed floating-point blend ops.",
+    "UMask": "0x09"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp128_shuffle",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 128-bit packed floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
+    "UMask": "0x0b"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp128_logical",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 128-bit packed floating-point logical ops.",
+    "UMask": "0x0d"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp128_other",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 128-bit packed floating-point ops of other types.",
+    "UMask": "0x0e"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp128_all",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 128-bit packed floating-point ops of all types.",
+    "UMask": "0x0f"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp256_add",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 256-bit packed floating-point add ops.",
+    "UMask": "0x10"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp256_sub",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 256-bit packed floating-point subtract ops.",
+    "UMask": "0x20"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp256_mul",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 256-bit packed floating-point multiply ops.",
+    "UMask": "0x30"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp256_mac",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 256-bit packed floating-point multiply-accumulate ops.",
+    "UMask": "0x40"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp256_div",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 256-bit packed floating-point divide ops.",
+    "UMask": "0x50"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp256_sqrt",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 256-bit packed floating-point square root ops.",
+    "UMask": "0x60"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp256_cmp",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 256-bit packed floating-point compare ops.",
+    "UMask": "0x70"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp256_cvt",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 256-bit packed floating-point convert ops.",
+    "UMask": "0x80"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp256_blend",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 256-bit packed floating-point blend ops.",
+    "UMask": "0x90"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp256_shuffle",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 256-bit packed floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
+    "UMask": "0xb0"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp256_logical",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 256-bit packed floating-point logical ops.",
+    "UMask": "0xd0"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp256_other",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 256-bit packed floating-point ops of other types.",
+    "UMask": "0xe0"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.fp256_all",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired 256-bit packed floating-point ops of all types.",
+    "UMask": "0xf0"
+  },
+  {
+    "EventName": "fp_pack_ops_retired.all",
+    "EventCode": "0x0c",
+    "BriefDescription": "Retired packed floating-point ops of all types.",
+    "UMask": "0xff"
+  },
+  {
+    "EventName": "packed_int_op_type.int128_add",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 128-bit packed integer add ops.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "packed_int_op_type.int128_sub",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 128-bit packed integer subtract ops.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "packed_int_op_type.int128_mul",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 128-bit packed integer multiply ops.",
+    "UMask": "0x03"
+  },
+  {
+    "EventName": "packed_int_op_type.int128_mac",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 128-bit packed integer multiply-accumulate ops.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "packed_int_op_type.int128_aes",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 128-bit packed integer AES ops.",
+    "UMask": "0x05"
+  },
+  {
+    "EventName": "packed_int_op_type.int128_sha",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 128-bit packed integer SHA ops.",
+    "UMask": "0x06"
+  },
+  {
+    "EventName": "packed_int_op_type.int128_cmp",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 128-bit packed integer compare ops.",
+    "UMask": "0x07"
+  },
+  {
+    "EventName": "packed_int_op_type.int128_clm",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 128-bit packed integer CLM ops.",
+    "UMask": "0x08"
+  },
+  {
+    "EventName": "packed_int_op_type.int128_shift",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 128-bit packed integer shift ops.",
+    "UMask": "0x09"
+  },
+  {
+    "EventName": "packed_int_op_type.int128_mov",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 128-bit packed integer MOV ops.",
+    "UMask": "0x0a"
+  },
+  {
+    "EventName": "packed_int_op_type.int128_shuffle",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 128-bit packed integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
+    "UMask": "0x0b"
+  },
+  {
+    "EventName": "packed_int_op_type.int128_pack",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 128-bit packed integer pack ops.",
+    "UMask": "0x0c"
+  },
+  {
+    "EventName": "packed_int_op_type.int128_logical",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 128-bit packed integer logical ops.",
+    "UMask": "0x0d"
+  },
+  {
+    "EventName": "packed_int_op_type.int128_other",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 128-bit packed integer ops of other types.",
+    "UMask": "0x0e"
+  },
+  {
+    "EventName": "packed_int_op_type.int128_all",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 128-bit packed integer ops of all types.",
+    "UMask": "0x0f"
+  },
+  {
+    "EventName": "packed_int_op_type.int256_add",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 256-bit packed integer add ops.",
+    "UMask": "0x10"
+  },
+  {
+    "EventName": "packed_int_op_type.int256_sub",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 256-bit packed integer subtract ops.",
+    "UMask": "0x20"
+  },
+  {
+    "EventName": "packed_int_op_type.int256_mul",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 256-bit packed integer multiply ops.",
+    "UMask": "0x30"
+  },
+  {
+    "EventName": "packed_int_op_type.int256_mac",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 256-bit packed integer multiply-accumulate ops.",
+    "UMask": "0x40"
+  },
+  {
+    "EventName": "packed_int_op_type.int256_cmp",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 256-bit packed integer compare ops.",
+    "UMask": "0x70"
+  },
+  {
+    "EventName": "packed_int_op_type.int256_shift",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 256-bit packed integer shift ops.",
+    "UMask": "0x90"
+  },
+  {
+    "EventName": "packed_int_op_type.int256_mov",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 256-bit packed integer MOV ops.",
+    "UMask": "0xa0"
+  },
+  {
+    "EventName": "packed_int_op_type.int256_shuffle",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 256-bit packed integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
+    "UMask": "0xb0"
+  },
+  {
+    "EventName": "packed_int_op_type.int256_pack",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 256-bit packed integer pack ops.",
+    "UMask": "0xc0"
+  },
+  {
+    "EventName": "packed_int_op_type.int256_logical",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 256-bit packed integer logical ops.",
+    "UMask": "0xd0"
+  },
+  {
+    "EventName": "packed_int_op_type.int256_other",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 256-bit packed integer ops of other types.",
+    "UMask": "0xe0"
+  },
+  {
+    "EventName": "packed_int_op_type.int256_all",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired 256-bit packed integer ops of all types.",
+    "UMask": "0xf0"
+  },
+  {
+    "EventName": "packed_int_op_type.all",
+    "EventCode": "0x0d",
+    "BriefDescription": "Retired packed integer ops of all types.",
+    "UMask": "0xff"
+  },
+  {
+    "EventName": "fp_disp_faults.x87_fill_fault",
+    "EventCode": "0x0e",
+    "BriefDescription": "Floating-point dispatch faults for x87 fills.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "fp_disp_faults.xmm_fill_fault",
+    "EventCode": "0x0e",
+    "BriefDescription": "Floating-point dispatch faults for XMM fills.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "fp_disp_faults.ymm_fill_fault",
+    "EventCode": "0x0e",
+    "BriefDescription": "Floating-point dispatch faults for YMM fills.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "fp_disp_faults.ymm_spill_fault",
+    "EventCode": "0x0e",
+    "BriefDescription": "Floating-point dispatch faults for YMM spills.",
+    "UMask": "0x08"
+  },
+  {
+    "EventName": "fp_disp_faults.sse_avx_all",
+    "EventCode": "0x0e",
+    "BriefDescription": "Floating-point dispatch faults of all types for SSE and AVX ops.",
+    "UMask": "0x0e"
+  },
+  {
+    "EventName": "fp_disp_faults.all",
+    "EventCode": "0x0e",
+    "BriefDescription": "Floating-point dispatch faults of all types.",
+    "UMask": "0x0f"
+  }
+]
diff --git a/tools/perf/pmu-events/arch/x86/amdzen4/memory.json b/tools/perf/pmu-events/arch/x86/amdzen4/memory.json
new file mode 100644
index 0000000000000..cb1517f8f399d
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/amdzen4/memory.json
@@ -0,0 +1,174 @@
+[
+  {
+    "EventName": "ls_bad_status2.stli_other",
+    "EventCode": "0x24",
+    "BriefDescription": "Store-to-load conflicts (load unable to complete due to a non-forwardable conflict with an older store).",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "ls_dispatch.ld_dispatch",
+    "EventCode": "0x29",
+    "BriefDescription": "Number of memory load operations dispatched to the load-store unit.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "ls_dispatch.store_dispatch",
+    "EventCode": "0x29",
+    "BriefDescription": "Number of memory store operations dispatched to the load-store unit.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "ls_dispatch.ld_st_dispatch",
+    "EventCode": "0x29",
+    "BriefDescription": "Number of memory load-store operations dispatched to the load-store unit.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "ls_stlf",
+    "EventCode": "0x35",
+    "BriefDescription": "Store-to-load-forward (STLF) hits."
+  },
+  {
+    "EventName": "ls_st_commit_cancel2.st_commit_cancel_wcb_full",
+    "EventCode": "0x37",
+    "BriefDescription": "Non-cacheable store commits cancelled due to the non-cacheable commit buffer being full.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",
+    "EventCode": "0x45",
+    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 4k pages.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit",
+    "EventCode": "0x45",
+    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",
+    "EventCode": "0x45",
+    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 2M pages.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",
+    "EventCode": "0x45",
+    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 1G pages.",
+    "UMask": "0x08"
+  },
+  {
+    "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss",
+    "EventCode": "0x45",
+    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pages.",
+    "UMask": "0x10"
+  },
+  {
+    "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss",
+    "EventCode": "0x45",
+    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
+    "UMask": "0x20"
+  },
+  {
+    "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss",
+    "EventCode": "0x45",
+    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 2M pages.",
+    "UMask": "0x40"
+  },
+  {
+    "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss",
+    "EventCode": "0x45",
+    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 1G pages.",
+    "UMask": "0x80"
+  },
+  {
+    "EventName": "ls_l1_d_tlb_miss.all_l2_miss",
+    "EventCode": "0x45",
+    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for all page sizes.",
+    "UMask": "0xf0"
+  },
+  {
+    "EventName": "ls_l1_d_tlb_miss.all",
+    "EventCode": "0x45",
+    "BriefDescription": "L1 DTLB misses for all page sizes.",
+    "UMask": "0xff"
+  },
+  {
+    "EventName": "ls_misal_loads.ma64",
+    "EventCode": "0x47",
+    "BriefDescription": "64B misaligned (cacheline crossing) loads.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "ls_misal_loads.ma4k",
+    "EventCode": "0x47",
+    "BriefDescription": "4kB misaligned (page crossing) loads.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "ls_tlb_flush.all",
+    "EventCode": "0x78",
+    "BriefDescription": "All TLB Flushes.",
+    "UMask": "0xff"
+  },
+  {
+    "EventName": "bp_l1_tlb_miss_l2_tlb_hit",
+    "EventCode": "0x84",
+    "BriefDescription": "Instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
+  },
+  {
+    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if4k",
+    "EventCode": "0x85",
+    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 4k pages.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if2m",
+    "EventCode": "0x85",
+    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 2M pages.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if1g",
+    "EventCode": "0x85",
+    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 1G pages.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k",
+    "EventCode": "0x85",
+    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
+    "UMask": "0x08"
+  },
+  {
+    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.all",
+    "EventCode": "0x85",
+    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for all page sizes.",
+    "UMask": "0x0f"
+  },
+  {
+    "EventName": "bp_l1_tlb_fetch_hit.if4k",
+    "EventCode": "0x94",
+    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "bp_l1_tlb_fetch_hit.if2m",
+    "EventCode": "0x94",
+    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 2M pages.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "bp_l1_tlb_fetch_hit.if1g",
+    "EventCode": "0x94",
+    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 1G pages.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "bp_l1_tlb_fetch_hit.all",
+    "EventCode": "0x94",
+    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for all page sizes.",
+    "UMask": "0x07"
+  }
+]
diff --git a/tools/perf/pmu-events/arch/x86/amdzen4/other.json b/tools/perf/pmu-events/arch/x86/amdzen4/other.json
new file mode 100644
index 0000000000000..a02a9c807289d
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/amdzen4/other.json
@@ -0,0 +1,138 @@
+[
+  {
+    "EventName": "resyncs_or_nc_redirects",
+    "EventCode": "0x96",
+    "BriefDescription": "Pipeline restarts not caused by branch mispredicts."
+  },
+  {
+    "EventName": "de_op_queue_empty",
+    "EventCode": "0xa9",
+    "BriefDescription": "Cycles when the op queue is empty. Such cycles indicate that the front-end is not delivering instructions fast enough."
+  },
+  {
+    "EventName": "de_src_op_disp.decoder",
+    "EventCode": "0xaa",
+    "BriefDescription": "Ops fetched from instruction cache and dispatched.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "de_src_op_disp.op_cache",
+    "EventCode": "0xaa",
+    "BriefDescription": "Ops fetched from op cache and dispatched.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "de_src_op_disp.loop_buffer",
+    "EventCode": "0xaa",
+    "BriefDescription": "Ops dispatched from loop buffer.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "de_src_op_disp.all",
+    "EventCode": "0xaa",
+    "BriefDescription": "Ops dispatched from any source.",
+    "UMask": "0x07"
+  },
+  {
+    "EventName": "de_dis_ops_from_decoder.any_fp_dispatch",
+    "EventCode": "0xab",
+    "BriefDescription": "Number of ops dispatched to the floating-point unit.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "de_dis_ops_from_decoder.disp_op_type.any_integer_dispatch",
+    "EventCode": "0xab",
+    "BriefDescription": "Number of ops dispatched to the integer execution unit.",
+    "UMask": "0x08"
+  },
+  {
+    "EventName": "de_dis_dispatch_token_stalls1.int_phy_reg_file_rsrc_stall",
+    "EventCode": "0xae",
+    "BriefDescription": "Number of cycles dispatch is stalled for integer physical register file tokens.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "de_dis_dispatch_token_stalls1.load_queue_rsrc_stall",
+    "EventCode": "0xae",
+    "BriefDescription": "Number of cycles dispatch is stalled for Load queue token.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "de_dis_dispatch_token_stalls1.store_queue_rsrc_stall",
+    "EventCode": "0xae",
+    "BriefDescription": "Number of cycles dispatch is stalled for store queue tokens.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "de_dis_dispatch_token_stalls1.taken_brnch_buffer_rsrc",
+    "EventCode": "0xae",
+    "BriefDescription": "Number of cycles dispatch is stalled for taken branch buffer tokens.",
+    "UMask": "0x10"
+  },
+  {
+    "EventName": "de_dis_dispatch_token_stalls1.fp_reg_file_rsrc_stall",
+    "EventCode": "0xae",
+    "BriefDescription": "Number of cycles dispatch is stalled for floating-point register file tokens.",
+    "UMask": "0x20"
+  },
+  {
+    "EventName": "de_dis_dispatch_token_stalls1.fp_sch_rsrc_stall",
+    "EventCode": "0xae",
+    "BriefDescription": "Number of cycles dispatch is stalled for floating-point scheduler tokens.",
+    "UMask": "0x40"
+  },
+  {
+    "EventName": "de_dis_dispatch_token_stalls1.fp_flush_recovery_stall",
+    "EventCode": "0xae",
+    "BriefDescription": "Number of cycles dispatch is stalled for floating-point flush recovery.",
+    "UMask": "0x80"
+  },
+  {
+    "EventName": "de_dis_dispatch_token_stalls2.int_sch0_token_stall",
+    "EventCode": "0xaf",
+    "BriefDescription": "Number of cycles dispatch is stalled for integer scheduler queue 0 tokens.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "de_dis_dispatch_token_stalls2.int_sch1_token_stall",
+    "EventCode": "0xaf",
+    "BriefDescription": "Number of cycles dispatch is stalled for integer scheduler queue 1 tokens.",
+    "UMask": "0x02"
+  },
+  {
+    "EventName": "de_dis_dispatch_token_stalls2.int_sch2_token_stall",
+    "EventCode": "0xaf",
+    "BriefDescription": "Number of cycles dispatch is stalled for integer scheduler queue 2 tokens.",
+    "UMask": "0x04"
+  },
+  {
+    "EventName": "de_dis_dispatch_token_stalls2.int_sch3_token_stall",
+    "EventCode": "0xaf",
+    "BriefDescription": "Number of cycles dispatch is stalled for integer scheduler queue 3 tokens.",
+    "UMask": "0x08"
+  },
+  {
+    "EventName": "de_dis_dispatch_token_stalls2.retire_token_stall",
+    "EventCode": "0xaf",
+    "BriefDescription": "Number of cycles dispatch is stalled for retire queue tokens.",
+    "UMask": "0x20"
+  },
+  {
+    "EventName": "de_no_dispatch_per_slot.no_ops_from_frontend",
+    "EventCode": "0x1a0",
+    "BriefDescription": "In each cycle counts dispatch slots left empty because the front-end did not supply ops.",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "de_no_dispatch_per_slot.backend_stalls",
+    "EventCode": "0x1a0",
+    "BriefDescription": "In each cycle counts ops unable to dispatch because of back-end stalls.",
+    "UMask": "0x1e"
+  },
+  {
+    "EventName": "de_no_dispatch_per_slot.smt_contention",
+    "EventCode": "0x1a0",
+    "BriefDescription": "In each cycle counts ops unable to dispatch because the dispatch cycle was granted to the other SMT thread.",
+    "UMask": "0x60"
+  }
+]
-- 
GitLab


From 5b2ca349c313a0e03162e353d898c4f7046c7898 Mon Sep 17 00:00:00 2001
From: Sandipan Das <sandipan.das@amd.com>
Date: Wed, 14 Dec 2022 13:56:50 +0530
Subject: [PATCH 596/875] perf vendor events amd: Add Zen 4 uncore events

Add uncore events taken from Section 2.1.15.5 "L3 Cache Performance
Monitor Counter"s and Section 7.1 "Fabric Performance Monitor Counter
(PMC) Events" in the Processor Programming Reference (PPR) for AMD
Family 19h Model 11h Revision B1 processors. This constitutes events
which capture L3 cache activity and data bandwidth for various links
and interfaces in the Data Fabric.

Signed-off-by: Sandipan Das <sandipan.das@amd.com>
Acked-by: Ian Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ananth Narayan <ananth.narayan@amd.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Jirka Hladky <jhladky@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@amd.com>
Cc: Stephane Eranian <eranian@google.com>
Link: https://lore.kernel.org/r/20221214082652.419965-3-sandipan.das@amd.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../pmu-events/arch/x86/amdzen4/cache.json    |  119 ++
 .../arch/x86/amdzen4/data-fabric.json         | 1090 +++++++++++++++++
 2 files changed, 1209 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/x86/amdzen4/data-fabric.json

diff --git a/tools/perf/pmu-events/arch/x86/amdzen4/cache.json b/tools/perf/pmu-events/arch/x86/amdzen4/cache.json
index 323ffd4b1423a..ecbe9660b2b31 100644
--- a/tools/perf/pmu-events/arch/x86/amdzen4/cache.json
+++ b/tools/perf/pmu-events/arch/x86/amdzen4/cache.json
@@ -649,5 +649,124 @@
     "EventCode": "0x28f",
     "BriefDescription": "Op cache accesses of all types.",
     "UMask": "0x07"
+  },
+  {
+    "EventName": "l3_lookup_state.l3_miss",
+    "EventCode": "0x04",
+    "BriefDescription": "L3 cache misses.",
+    "UMask": "0x01",
+    "Unit": "L3PMC"
+  },
+  {
+    "EventName": "l3_lookup_state.l3_hit",
+    "EventCode": "0x04",
+    "BriefDescription": "L3 cache hits.",
+    "UMask": "0xfe",
+    "Unit": "L3PMC"
+  },
+  {
+    "EventName": "l3_lookup_state.all_coherent_accesses_to_l3",
+    "EventCode": "0x04",
+    "BriefDescription": "L3 cache requests for all coherent accesses.",
+    "UMask": "0xff",
+    "Unit": "L3PMC"
+  },
+  {
+    "EventName": "l3_xi_sampled_latency.dram_near",
+    "EventCode": "0xac",
+    "BriefDescription": "Average sampled latency when data is sourced from DRAM in the same NUMA node.",
+    "UMask": "0x01",
+    "Unit": "L3PMC"
+  },
+  {
+    "EventName": "l3_xi_sampled_latency.dram_far",
+    "EventCode": "0xac",
+    "BriefDescription": "Average sampled latency when data is sourced from DRAM in a different NUMA node.",
+    "UMask": "0x02",
+    "Unit": "L3PMC"
+  },
+  {
+    "EventName": "l3_xi_sampled_latency.near_cache",
+    "EventCode": "0xac",
+    "BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in the same NUMA node.",
+    "UMask": "0x04",
+    "Unit": "L3PMC"
+  },
+  {
+    "EventName": "l3_xi_sampled_latency.far_cache",
+    "EventCode": "0xac",
+    "BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in a different NUMA node.",
+    "UMask": "0x08",
+    "Unit": "L3PMC"
+  },
+  {
+    "EventName": "l3_xi_sampled_latency.ext_near",
+    "EventCode": "0xac",
+    "BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in the same NUMA node.",
+    "UMask": "0x10",
+    "Unit": "L3PMC"
+  },
+  {
+    "EventName": "l3_xi_sampled_latency.ext_far",
+    "EventCode": "0xac",
+    "BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in a different NUMA node.",
+    "UMask": "0x20",
+    "Unit": "L3PMC"
+  },
+  {
+    "EventName": "l3_xi_sampled_latency.all",
+    "EventCode": "0xac",
+    "BriefDescription": "Average sampled latency from all data sources.",
+    "UMask": "0x3f",
+    "Unit": "L3PMC"
+  },
+  {
+    "EventName": "l3_xi_sampled_latency_requests.dram_near",
+    "EventCode": "0xad",
+    "BriefDescription": "L3 cache fill requests sourced from DRAM in the same NUMA node.",
+    "UMask": "0x01",
+    "Unit": "L3PMC"
+  },
+  {
+    "EventName": "l3_xi_sampled_latency_requests.dram_far",
+    "EventCode": "0xad",
+    "BriefDescription": "L3 cache fill requests sourced from DRAM in a different NUMA node.",
+    "UMask": "0x02",
+    "Unit": "L3PMC"
+  },
+  {
+    "EventName": "l3_xi_sampled_latency_requests.near_cache",
+    "EventCode": "0xad",
+    "BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in the same NUMA node.",
+    "UMask": "0x04",
+    "Unit": "L3PMC"
+  },
+  {
+    "EventName": "l3_xi_sampled_latency_requests.far_cache",
+    "EventCode": "0xad",
+    "BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in a different NUMA node.",
+    "UMask": "0x08",
+    "Unit": "L3PMC"
+  },
+  {
+    "EventName": "l3_xi_sampled_latency_requests.ext_near",
+    "EventCode": "0xad",
+    "BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in the same NUMA node.",
+    "UMask": "0x10",
+    "Unit": "L3PMC"
+  },
+  {
+    "EventName": "l3_xi_sampled_latency_requests.ext_far",
+    "EventCode": "0xad",
+    "BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in a different NUMA node.",
+    "UMask": "0x20",
+    "Unit": "L3PMC"
+  },
+  {
+    "EventName": "l3_xi_sampled_latency_requests.all",
+    "EventCode": "0xad",
+    "BriefDescription": "L3 cache fill requests sourced from all data sources.",
+    "UMask": "0x3f",
+    "Unit": "L3PMC"
   }
 ]
diff --git a/tools/perf/pmu-events/arch/x86/amdzen4/data-fabric.json b/tools/perf/pmu-events/arch/x86/amdzen4/data-fabric.json
new file mode 100644
index 0000000000000..cf8f13075e622
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/amdzen4/data-fabric.json
@@ -0,0 +1,1090 @@
+[
+  {
+    "EventName": "local_processor_read_data_beats_cs0",
+    "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 0.",
+    "EventCode": "0x1f",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_processor_read_data_beats_cs1",
+    "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 1.",
+    "EventCode": "0x5f",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_processor_read_data_beats_cs2",
+    "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 2.",
+    "EventCode": "0x9f",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_processor_read_data_beats_cs3",
+    "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 3.",
+    "EventCode": "0xdf",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_processor_read_data_beats_cs4",
+    "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 4.",
+    "EventCode": "0x11f",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_processor_read_data_beats_cs5",
+    "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 5.",
+    "EventCode": "0x15f",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_processor_read_data_beats_cs6",
+    "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 6.",
+    "EventCode": "0x19f",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_processor_read_data_beats_cs7",
+    "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 7.",
+    "EventCode": "0x1df",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_processor_read_data_beats_cs8",
+    "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 8.",
+    "EventCode": "0x21f",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_processor_read_data_beats_cs9",
+    "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 9.",
+    "EventCode": "0x25f",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_processor_read_data_beats_cs10",
+    "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 10.",
+    "EventCode": "0x29f",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_processor_read_data_beats_cs11",
+    "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 11.",
+    "EventCode": "0x2df",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_processor_write_data_beats_cs0",
+    "PublicDescription": "Write data beats (64 bytes) for local processor at Coherent Station (CS) 0.",
+    "EventCode": "0x1f",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_processor_write_data_beats_cs1",
+    "PublicDescription": "Write data beats (64 bytes) for local processor at Coherent Station (CS) 1.",
+    "EventCode": "0x5f",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_processor_write_data_beats_cs2",
+    "PublicDescription": "Write data beats (64 bytes) for local processor at Coherent Station (CS) 2.",
+    "EventCode": "0x9f",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_processor_write_data_beats_cs3",
+    "PublicDescription": "Write data beats (64 bytes) for local processor at Coherent Station (CS) 3.",
+    "EventCode": "0xdf",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_processor_write_data_beats_cs4",
+    "PublicDescription": "Write data beats (64 bytes) for local processor at Coherent Station (CS) 4.",
+    "EventCode": "0x11f",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_processor_write_data_beats_cs5",
+    "PublicDescription": "Write data beats (64 bytes) for local processor at Coherent Station (CS) 5.",
+    "EventCode": "0x15f",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_processor_write_data_beats_cs6",
+    "PublicDescription": "Write data beats (64 bytes) for local processor at Coherent Station (CS) 6.",
+    "EventCode": "0x19f",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_processor_write_data_beats_cs7",
+    "PublicDescription": "Write data beats (64 bytes) for local processor at Coherent Station (CS) 7.",
+    "EventCode": "0x1df",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_processor_write_data_beats_cs8",
+    "PublicDescription": "Write data beats (64 bytes) for local processor at Coherent Station (CS) 8.",
+    "EventCode": "0x21f",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_processor_write_data_beats_cs9",
+    "PublicDescription": "Write data beats (64 bytes) for local processor at Coherent Station (CS) 9.",
+    "EventCode": "0x25f",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_processor_write_data_beats_cs10",
+    "PublicDescription": "Write data beats (64 bytes) for local processor at Coherent Station (CS) 10.",
+    "EventCode": "0x29f",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_processor_write_data_beats_cs11",
+    "PublicDescription": "Write data beats (64 bytes) for local processor at Coherent Station (CS) 11.",
+    "EventCode": "0x2df",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_read_data_beats_cs0",
+    "PublicDescription": "Read data beats (64 bytes) for remote processor at Coherent Station (CS) 0.",
+    "EventCode": "0x1f",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_read_data_beats_cs1",
+    "PublicDescription": "Read data beats (64 bytes) for remote processor at Coherent Station (CS) 1.",
+    "EventCode": "0x5f",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_read_data_beats_cs2",
+    "PublicDescription": "Read data beats (64 bytes) for remote processor at Coherent Station (CS) 2.",
+    "EventCode": "0x9f",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_read_data_beats_cs3",
+    "PublicDescription": "Read data beats (64 bytes) for remote processor at Coherent Station (CS) 3.",
+    "EventCode": "0xdf",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_read_data_beats_cs4",
+    "PublicDescription": "Read data beats (64 bytes) for remote processor at Coherent Station (CS) 4.",
+    "EventCode": "0x11f",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_read_data_beats_cs5",
+    "PublicDescription": "Read data beats (64 bytes) for remote processor at Coherent Station (CS) 5.",
+    "EventCode": "0x15f",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_read_data_beats_cs6",
+    "PublicDescription": "Read data beats (64 bytes) for remote processor at Coherent Station (CS) 6.",
+    "EventCode": "0x19f",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_read_data_beats_cs7",
+    "PublicDescription": "Read data beats (64 bytes) for remote processor at Coherent Station (CS) 7.",
+    "EventCode": "0x1df",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_read_data_beats_cs8",
+    "PublicDescription": "Read data beats (64 bytes) for remote processor at Coherent Station (CS) 8.",
+    "EventCode": "0x21f",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_read_data_beats_cs9",
+    "PublicDescription": "Read data beats (64 bytes) for remote processor at Coherent Station (CS) 9.",
+    "EventCode": "0x25f",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_read_data_beats_cs10",
+    "PublicDescription": "Read data beats (64 bytes) for remote processor at Coherent Station (CS) 10.",
+    "EventCode": "0x29f",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_read_data_beats_cs11",
+    "PublicDescription": "Read data beats (64 bytes) for remote processor at Coherent Station (CS) 11.",
+    "EventCode": "0x2df",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_write_data_beats_cs0",
+    "PublicDescription": "Write data beats (64 bytes) for remote processor at Coherent Station (CS) 0.",
+    "EventCode": "0x1f",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_write_data_beats_cs1",
+    "PublicDescription": "Write data beats (64 bytes) for remote processor at Coherent Station (CS) 1.",
+    "EventCode": "0x5f",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_write_data_beats_cs2",
+    "PublicDescription": "Write data beats (64 bytes) for remote processor at Coherent Station (CS) 2.",
+    "EventCode": "0x9f",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_write_data_beats_cs3",
+    "PublicDescription": "Write data beats (64 bytes) for remote processor at Coherent Station (CS) 3.",
+    "EventCode": "0xdf",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_write_data_beats_cs4",
+    "PublicDescription": "Write data beats (64 bytes) for remote processor at Coherent Station (CS) 4.",
+    "EventCode": "0x11f",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_write_data_beats_cs5",
+    "PublicDescription": "Write data beats (64 bytes) for remote processor at Coherent Station (CS) 5.",
+    "EventCode": "0x15f",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_write_data_beats_cs6",
+    "PublicDescription": "Write data beats (64 bytes) for remote processor at Coherent Station (CS) 6.",
+    "EventCode": "0x19f",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_write_data_beats_cs7",
+    "PublicDescription": "Write data beats (64 bytes) for remote processor at Coherent Station (CS) 7.",
+    "EventCode": "0x1df",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_write_data_beats_cs8",
+    "PublicDescription": "Write data beats (64 bytes) for remote processor at Coherent Station (CS) 8.",
+    "EventCode": "0x21f",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_write_data_beats_cs9",
+    "PublicDescription": "Write data beats (64 bytes) for remote processor at Coherent Station (CS) 9.",
+    "EventCode": "0x25f",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_write_data_beats_cs10",
+    "PublicDescription": "Write data beats (64 bytes) for remote processor at Coherent Station (CS) 10.",
+    "EventCode": "0x29f",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_processor_write_data_beats_cs11",
+    "PublicDescription": "Write data beats (64 bytes) for remote processor at Coherent Station (CS) 11.",
+    "EventCode": "0x2df",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_upstream_read_beats_iom0",
+    "PublicDescription": "Read data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 0.",
+    "EventCode": "0x81f",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_upstream_read_beats_iom1",
+    "PublicDescription": "Read data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 1.",
+    "EventCode": "0x85f",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_upstream_read_beats_iom2",
+    "PublicDescription": "Read data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 2.",
+    "EventCode": "0x89f",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_upstream_read_beats_iom3",
+    "PublicDescription": "Read data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 3.",
+    "EventCode": "0x8df",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_upstream_write_beats_iom0",
+    "PublicDescription": "Write data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 0.",
+    "EventCode": "0x81f",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_upstream_write_beats_iom1",
+    "PublicDescription": "Write data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 1.",
+    "EventCode": "0x85f",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_upstream_write_beats_iom2",
+    "PublicDescription": "Write data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 2.",
+    "EventCode": "0x89f",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_upstream_write_beats_iom3",
+    "PublicDescription": "Write data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 3.",
+    "EventCode": "0x8df",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_upstream_read_beats_iom0",
+    "PublicDescription": "Read data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 0.",
+    "EventCode": "0x81f",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_upstream_read_beats_iom1",
+    "PublicDescription": "Read data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 1.",
+    "EventCode": "0x85f",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_upstream_read_beats_iom2",
+    "PublicDescription": "Read data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 2.",
+    "EventCode": "0x89f",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_upstream_read_beats_iom3",
+    "PublicDescription": "Read data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 3.",
+    "EventCode": "0x8df",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_upstream_write_beats_iom0",
+    "PublicDescription": "Write data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 0.",
+    "EventCode": "0x81f",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_upstream_write_beats_iom1",
+    "PublicDescription": "Write data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 1.",
+    "EventCode": "0x85f",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_upstream_write_beats_iom2",
+    "PublicDescription": "Write data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 2.",
+    "EventCode": "0x89f",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_upstream_write_beats_iom3",
+    "PublicDescription": "Write data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 3.",
+    "EventCode": "0x8df",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf0_inbound_data_beats_ccm0",
+    "PublicDescription": "Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 0.",
+    "EventCode": "0x41e",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf0_inbound_data_beats_ccm1",
+    "PublicDescription": "Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 1.",
+    "EventCode": "0x45e",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf0_inbound_data_beats_ccm2",
+    "PublicDescription": "Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 2.",
+    "EventCode": "0x49e",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf0_inbound_data_beats_ccm3",
+    "PublicDescription": "Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 3.",
+    "EventCode": "0x4de",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf0_inbound_data_beats_ccm4",
+    "PublicDescription": "Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 4.",
+    "EventCode": "0x51e",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf0_inbound_data_beats_ccm5",
+    "PublicDescription": "Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 5.",
+    "EventCode": "0x55e",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf0_inbound_data_beats_ccm6",
+    "PublicDescription": "Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 6.",
+    "EventCode": "0x59e",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf0_inbound_data_beats_ccm7",
+    "PublicDescription": "Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 7.",
+    "EventCode": "0x5de",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf1_inbound_data_beats_ccm0",
+    "PublicDescription": "Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 0.",
+    "EventCode": "0x41f",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf1_inbound_data_beats_ccm1",
+    "PublicDescription": "Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 1.",
+    "EventCode": "0x45f",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf1_inbound_data_beats_ccm2",
+    "PublicDescription": "Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 2.",
+    "EventCode": "0x49f",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf1_inbound_data_beats_ccm3",
+    "PublicDescription": "Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 3.",
+    "EventCode": "0x4df",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf1_inbound_data_beats_ccm4",
+    "PublicDescription": "Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 4.",
+    "EventCode": "0x51f",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf1_inbound_data_beats_ccm5",
+    "PublicDescription": "Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 5.",
+    "EventCode": "0x55f",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf1_inbound_data_beats_ccm6",
+    "PublicDescription": "Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 6.",
+    "EventCode": "0x59f",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf1_inbound_data_beats_ccm7",
+    "PublicDescription": "Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 7.",
+    "EventCode": "0x5df",
+    "UMask": "0x7fe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf0_outbound_data_beats_ccm0",
+    "PublicDescription": "Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 0.",
+    "EventCode": "0x41e",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf0_outbound_data_beats_ccm1",
+    "PublicDescription": "Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 1.",
+    "EventCode": "0x45e",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf0_outbound_data_beats_ccm2",
+    "PublicDescription": "Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 2.",
+    "EventCode": "0x49e",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf0_outbound_data_beats_ccm3",
+    "PublicDescription": "Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 3.",
+    "EventCode": "0x4de",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf0_outbound_data_beats_ccm4",
+    "PublicDescription": "Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 4.",
+    "EventCode": "0x51e",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf0_outbound_data_beats_ccm5",
+    "PublicDescription": "Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 5.",
+    "EventCode": "0x55e",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf0_outbound_data_beats_ccm6",
+    "PublicDescription": "Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 6.",
+    "EventCode": "0x59e",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf0_outbound_data_beats_ccm7",
+    "PublicDescription": "Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 7.",
+    "EventCode": "0x5de",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf1_outbound_data_beats_ccm0",
+    "PublicDescription": "Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 0.",
+    "EventCode": "0x41f",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf1_outbound_data_beats_ccm1",
+    "PublicDescription": "Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 1.",
+    "EventCode": "0x45f",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf1_outbound_data_beats_ccm2",
+    "PublicDescription": "Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 2.",
+    "EventCode": "0x49f",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf1_outbound_data_beats_ccm3",
+    "PublicDescription": "Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 3.",
+    "EventCode": "0x4df",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf1_outbound_data_beats_ccm4",
+    "PublicDescription": "Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 4.",
+    "EventCode": "0x51f",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf1_outbound_data_beats_ccm5",
+    "PublicDescription": "Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 5.",
+    "EventCode": "0x55f",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf1_outbound_data_beats_ccm6",
+    "PublicDescription": "Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 6.",
+    "EventCode": "0x59f",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_inf1_outbound_data_beats_ccm7",
+    "PublicDescription": "Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 7.",
+    "EventCode": "0x5df",
+    "UMask": "0x7ff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf0_inbound_data_beats_ccm0",
+    "PublicDescription": "Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 0.",
+    "EventCode": "0x41e",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf0_inbound_data_beats_ccm1",
+    "PublicDescription": "Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 1.",
+    "EventCode": "0x45e",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf0_inbound_data_beats_ccm2",
+    "PublicDescription": "Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 2.",
+    "EventCode": "0x49e",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf0_inbound_data_beats_ccm3",
+    "PublicDescription": "Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 3.",
+    "EventCode": "0x4de",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf0_inbound_data_beats_ccm4",
+    "PublicDescription": "Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 4.",
+    "EventCode": "0x51e",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf0_inbound_data_beats_ccm5",
+    "PublicDescription": "Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 5.",
+    "EventCode": "0x55e",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf0_inbound_data_beats_ccm6",
+    "PublicDescription": "Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 6.",
+    "EventCode": "0x59e",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf0_inbound_data_beats_ccm7",
+    "PublicDescription": "Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 7.",
+    "EventCode": "0x5de",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf1_inbound_data_beats_ccm0",
+    "PublicDescription": "Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 0.",
+    "EventCode": "0x41f",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf1_inbound_data_beats_ccm1",
+    "PublicDescription": "Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 1.",
+    "EventCode": "0x45f",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf1_inbound_data_beats_ccm2",
+    "PublicDescription": "Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 2.",
+    "EventCode": "0x49f",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf1_inbound_data_beats_ccm3",
+    "PublicDescription": "Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 3.",
+    "EventCode": "0x4df",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf1_inbound_data_beats_ccm4",
+    "PublicDescription": "Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 4.",
+    "EventCode": "0x51f",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf1_inbound_data_beats_ccm5",
+    "PublicDescription": "Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 5.",
+    "EventCode": "0x55f",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf1_inbound_data_beats_ccm6",
+    "PublicDescription": "Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 6.",
+    "EventCode": "0x59f",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf1_inbound_data_beats_ccm7",
+    "PublicDescription": "Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 7.",
+    "EventCode": "0x5df",
+    "UMask": "0xbfe",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf0_outbound_data_beats_ccm0",
+    "PublicDescription": "Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 0.",
+    "EventCode": "0x41e",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf0_outbound_data_beats_ccm1",
+    "PublicDescription": "Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 1.",
+    "EventCode": "0x45e",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf0_outbound_data_beats_ccm2",
+    "PublicDescription": "Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 2.",
+    "EventCode": "0x49e",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf0_outbound_data_beats_ccm3",
+    "PublicDescription": "Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 3.",
+    "EventCode": "0x4de",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf0_outbound_data_beats_ccm4",
+    "PublicDescription": "Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 4.",
+    "EventCode": "0x51e",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf0_outbound_data_beats_ccm5",
+    "PublicDescription": "Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 5.",
+    "EventCode": "0x55e",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf0_outbound_data_beats_ccm6",
+    "PublicDescription": "Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 6.",
+    "EventCode": "0x59e",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf0_outbound_data_beats_ccm7",
+    "PublicDescription": "Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 7.",
+    "EventCode": "0x5de",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf1_outbound_data_beats_ccm0",
+    "PublicDescription": "Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 0.",
+    "EventCode": "0x41f",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf1_outbound_data_beats_ccm1",
+    "PublicDescription": "Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 1.",
+    "EventCode": "0x45f",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf1_outbound_data_beats_ccm2",
+    "PublicDescription": "Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 2.",
+    "EventCode": "0x49f",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf1_outbound_data_beats_ccm3",
+    "PublicDescription": "Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 3.",
+    "EventCode": "0x4df",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf1_outbound_data_beats_ccm4",
+    "PublicDescription": "Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 4.",
+    "EventCode": "0x51f",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf1_outbound_data_beats_ccm5",
+    "PublicDescription": "Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 5.",
+    "EventCode": "0x55f",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf1_outbound_data_beats_ccm6",
+    "PublicDescription": "Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 6.",
+    "EventCode": "0x59f",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_socket_inf1_outbound_data_beats_ccm7",
+    "PublicDescription": "Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 7.",
+    "EventCode": "0x5df",
+    "UMask": "0xbff",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_outbound_data_beats_link0",
+    "PublicDescription": "Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 0.",
+    "EventCode": "0xb5f",
+    "UMask": "0xf3e",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_outbound_data_beats_link1",
+    "PublicDescription": "Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 1.",
+    "EventCode": "0xb9f",
+    "UMask": "0xf3e",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_outbound_data_beats_link2",
+    "PublicDescription": "Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 2.",
+    "EventCode": "0xbdf",
+    "UMask": "0xf3e",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_outbound_data_beats_link3",
+    "PublicDescription": "Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 3.",
+    "EventCode": "0xc1f",
+    "UMask": "0xf3e",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_outbound_data_beats_link4",
+    "PublicDescription": "Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 4.",
+    "EventCode": "0xc5f",
+    "UMask": "0xf3e",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_outbound_data_beats_link5",
+    "PublicDescription": "Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 5.",
+    "EventCode": "0xc9f",
+    "UMask": "0xf3e",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_outbound_data_beats_link6",
+    "PublicDescription": "Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 6.",
+    "EventCode": "0xcdf",
+    "UMask": "0xf3e",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "local_socket_outbound_data_beats_link7",
+    "PublicDescription": "Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 7.",
+    "EventCode": "0xd1f",
+    "UMask": "0xf3e",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  }
+]
-- 
GitLab


From aba4cb3eb5b8a7ad70a566a25f530c809993e556 Mon Sep 17 00:00:00 2001
From: Sandipan Das <sandipan.das@amd.com>
Date: Wed, 14 Dec 2022 13:56:51 +0530
Subject: [PATCH 597/875] perf vendor events amd: Add Zen 4 metrics

Add metrics taken from Section 2.1.15.2 "Performance Measurement" in
the Processor Programming Reference (PPR) for AMD Family 19h Model 11h
Revision B1 processors.

The recommended metrics are sourced from Table 27 "Guidance for Common
Performance Statistics with Complex Event Selects".

The pipeline utilization metrics are sourced from Table 28 "Guidance
for Pipeline Utilization Analysis Statistics". These are new to Zen 4
processors and useful for finding performance bottlenecks by analyzing
activity at different stages of the pipeline. Metric groups have been
added for Level 1 and Level 2 analysis.

Signed-off-by: Sandipan Das <sandipan.das@amd.com>
Acked-by: Ian Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ananth Narayan <ananth.narayan@amd.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Jirka Hladky <jhladky@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@amd.com>
Cc: Stephane Eranian <eranian@google.com>
Link: https://lore.kernel.org/r/20221214082652.419965-4-sandipan.das@amd.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../pmu-events/arch/x86/amdzen4/pipeline.json |  98 +++++
 .../arch/x86/amdzen4/recommended.json         | 334 ++++++++++++++++++
 2 files changed, 432 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/x86/amdzen4/pipeline.json
 create mode 100644 tools/perf/pmu-events/arch/x86/amdzen4/recommended.json

diff --git a/tools/perf/pmu-events/arch/x86/amdzen4/pipeline.json b/tools/perf/pmu-events/arch/x86/amdzen4/pipeline.json
new file mode 100644
index 0000000000000..4ae8316c75070
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/amdzen4/pipeline.json
@@ -0,0 +1,98 @@
+[
+  {
+    "MetricName": "total_dispatch_slots",
+    "BriefDescription": "Total dispatch slots (upto 6 instructions can be dispatched in each cycle).",
+    "MetricExpr": "6 * ls_not_halted_cyc"
+  },
+  {
+    "MetricName": "frontend_bound",
+    "BriefDescription": "Fraction of dispatch slots that remained unused because the frontend did not supply enough instructions/ops.",
+    "MetricExpr": "d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend, total_dispatch_slots)",
+    "MetricGroup": "PipelineL1",
+    "ScaleUnit": "100%"
+  },
+  {
+    "MetricName": "bad_speculation",
+    "BriefDescription": "Fraction of dispatched ops that did not retire.",
+    "MetricExpr": "d_ratio(de_src_op_disp.all - ex_ret_ops, total_dispatch_slots)",
+    "MetricGroup": "PipelineL1",
+    "ScaleUnit": "100%"
+  },
+  {
+    "MetricName": "backend_bound",
+    "BriefDescription": "Fraction of dispatch slots that remained unused because of backend stalls.",
+    "MetricExpr": "d_ratio(de_no_dispatch_per_slot.backend_stalls, total_dispatch_slots)",
+    "MetricGroup": "PipelineL1",
+    "ScaleUnit": "100%"
+  },
+  {
+    "MetricName": "smt_contention",
+    "BriefDescription": "Fraction of dispatch slots that remained unused because the other thread was selected.",
+    "MetricExpr": "d_ratio(de_no_dispatch_per_slot.smt_contention, total_dispatch_slots)",
+    "MetricGroup": "PipelineL1",
+    "ScaleUnit": "100%"
+  },
+  {
+    "MetricName": "retiring",
+    "BriefDescription": "Fraction of dispatch slots used by ops that retired.",
+    "MetricExpr": "d_ratio(ex_ret_ops, total_dispatch_slots)",
+    "MetricGroup": "PipelineL1",
+    "ScaleUnit": "100%"
+  },
+  {
+    "MetricName": "frontend_bound_latency",
+    "BriefDescription": "Fraction of dispatch slots that remained unused because of a latency bottleneck in the frontend (such as instruction cache or TLB misses).",
+    "MetricExpr": "d_ratio((6 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\\,cmask\\=0x6@), total_dispatch_slots)",
+    "MetricGroup": "PipelineL2;frontend_bound_group",
+    "ScaleUnit": "100%"
+  },
+  {
+    "MetricName": "frontend_bound_bandwidth",
+    "BriefDescription": "Fraction of dispatch slots that remained unused because of a bandwidth bottleneck in the frontend (such as decode or op cache fetch bandwidth).",
+    "MetricExpr": "d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend - (6 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\\,cmask\\=0x6@), total_dispatch_slots)",
+    "MetricGroup": "PipelineL2;frontend_bound_group",
+    "ScaleUnit": "100%"
+  },
+  {
+    "MetricName": "bad_speculation_mispredicts",
+    "BriefDescription": "Fraction of dispatched ops that were flushed due to branch mispredicts.",
+    "MetricExpr": "d_ratio(bad_speculation * ex_ret_brn_misp, ex_ret_brn_misp + resyncs_or_nc_redirects)",
+    "MetricGroup": "PipelineL2;bad_speculation_group",
+    "ScaleUnit": "100%"
+  },
+  {
+    "MetricName": "bad_speculation_pipeline_restarts",
+    "BriefDescription": "Fraction of dispatched ops that were flushed due to pipeline restarts (resyncs).",
+    "MetricExpr": "d_ratio(bad_speculation * resyncs_or_nc_redirects, ex_ret_brn_misp + resyncs_or_nc_redirects)",
+    "MetricGroup": "PipelineL2;bad_speculation_group",
+    "ScaleUnit": "100%"
+  },
+  {
+    "MetricName": "backend_bound_memory",
+    "BriefDescription": "Fraction of dispatch slots that remained unused because of stalls due to the memory subsystem.",
+    "MetricExpr": "backend_bound * d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete)",
+    "MetricGroup": "PipelineL2;backend_bound_group",
+    "ScaleUnit": "100%"
+  },
+  {
+    "MetricName": "backend_bound_cpu",
+    "BriefDescription": "Fraction of dispatch slots that remained unused because of stalls not related to the memory subsystem.",
+    "MetricExpr": "backend_bound * (1 - d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete))",
+    "MetricGroup": "PipelineL2;backend_bound_group",
+    "ScaleUnit": "100%"
+  },
+  {
+    "MetricName": "retiring_fastpath",
+    "BriefDescription": "Fraction of dispatch slots used by fastpath ops that retired.",
+    "MetricExpr": "retiring * (1 - d_ratio(ex_ret_ucode_ops, ex_ret_ops))",
+    "MetricGroup": "PipelineL2;retiring_group",
+    "ScaleUnit": "100%"
+  },
+  {
+    "MetricName": "retiring_microcode",
+    "BriefDescription": "Fraction of dispatch slots used by microcode ops that retired.",
+    "MetricExpr": "retiring * d_ratio(ex_ret_ucode_ops, ex_ret_ops)",
+    "MetricGroup": "PipelineL2;retiring_group",
+    "ScaleUnit": "100%"
+  }
+]
diff --git a/tools/perf/pmu-events/arch/x86/amdzen4/recommended.json b/tools/perf/pmu-events/arch/x86/amdzen4/recommended.json
new file mode 100644
index 0000000000000..5e6a793acf7b2
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/amdzen4/recommended.json
@@ -0,0 +1,334 @@
+[
+  {
+    "MetricName": "branch_misprediction_ratio",
+    "BriefDescription": "Execution-time branch misprediction ratio (non-speculative).",
+    "MetricExpr": "d_ratio(ex_ret_brn_misp, ex_ret_brn)",
+    "MetricGroup": "branch_prediction",
+    "ScaleUnit": "100%"
+  },
+  {
+    "EventName": "all_data_cache_accesses",
+    "EventCode": "0x29",
+    "BriefDescription": "All data cache accesses.",
+    "UMask": "0x07"
+  },
+  {
+    "MetricName": "all_l2_cache_accesses",
+    "BriefDescription": "All L2 cache accesses.",
+    "MetricExpr": "l2_request_g1.all_no_prefetch + l2_pf_hit_l2.all + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all",
+    "MetricGroup": "l2_cache"
+  },
+  {
+    "MetricName": "l2_cache_accesses_from_l1_ic_misses",
+    "BriefDescription": "L2 cache accesses from L1 instruction cache misses (including prefetch).",
+    "MetricExpr": "l2_request_g1.cacheable_ic_read",
+    "MetricGroup": "l2_cache"
+  },
+  {
+    "MetricName": "l2_cache_accesses_from_l1_dc_misses",
+    "BriefDescription": "L2 cache accesses from L1 data cache misses (including prefetch).",
+    "MetricExpr": "l2_request_g1.all_dc",
+    "MetricGroup": "l2_cache"
+  },
+  {
+    "MetricName": "l2_cache_accesses_from_l2_hwpf",
+    "BriefDescription": "L2 cache accesses from L2 cache hardware prefetcher.",
+    "MetricExpr": "l2_pf_hit_l2.all + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all",
+    "MetricGroup": "l2_cache"
+  },
+  {
+    "MetricName": "all_l2_cache_misses",
+    "BriefDescription": "All L2 cache misses.",
+    "MetricExpr": "l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all",
+    "MetricGroup": "l2_cache"
+  },
+  {
+    "MetricName": "l2_cache_misses_from_l1_ic_miss",
+    "BriefDescription": "L2 cache misses from L1 instruction cache misses.",
+    "MetricExpr": "l2_cache_req_stat.ic_fill_miss",
+    "MetricGroup": "l2_cache"
+  },
+  {
+    "MetricName": "l2_cache_misses_from_l1_dc_miss",
+    "BriefDescription": "L2 cache misses from L1 data cache misses.",
+    "MetricExpr": "l2_cache_req_stat.ls_rd_blk_c",
+    "MetricGroup": "l2_cache"
+  },
+  {
+    "MetricName": "l2_cache_misses_from_l2_hwpf",
+    "BriefDescription": "L2 cache misses from L2 cache hardware prefetcher.",
+    "MetricExpr": "l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all",
+    "MetricGroup": "l2_cache"
+  },
+  {
+    "MetricName": "all_l2_cache_hits",
+    "BriefDescription": "All L2 cache hits.",
+    "MetricExpr": "l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2.all",
+    "MetricGroup": "l2_cache"
+  },
+  {
+    "MetricName": "l2_cache_hits_from_l1_ic_miss",
+    "BriefDescription": "L2 cache hits from L1 instruction cache misses.",
+    "MetricExpr": "l2_cache_req_stat.ic_hit_in_l2",
+    "MetricGroup": "l2_cache"
+  },
+  {
+    "MetricName": "l2_cache_hits_from_l1_dc_miss",
+    "BriefDescription": "L2 cache hits from L1 data cache misses.",
+    "MetricExpr": "l2_cache_req_stat.dc_hit_in_l2",
+    "MetricGroup": "l2_cache"
+  },
+  {
+    "MetricName": "l2_cache_hits_from_l2_hwpf",
+    "BriefDescription": "L2 cache hits from L2 cache hardware prefetcher.",
+    "MetricExpr": "l2_pf_hit_l2.all",
+    "MetricGroup": "l2_cache"
+  },
+  {
+    "MetricName": "l3_cache_accesses",
+    "BriefDescription": "L3 cache accesses.",
+    "MetricExpr": "l3_lookup_state.all_coherent_accesses_to_l3",
+    "MetricGroup": "l3_cache"
+  },
+  {
+    "MetricName": "l3_misses",
+    "BriefDescription": "L3 misses (including cacheline state change requests).",
+    "MetricExpr": "l3_lookup_state.l3_miss",
+    "MetricGroup": "l3_cache"
+  },
+  {
+    "MetricName": "l3_read_miss_latency",
+    "BriefDescription": "Average L3 read miss latency (in core clocks).",
+    "MetricExpr": "(l3_xi_sampled_latency.all * 10) / l3_xi_sampled_latency_requests.all",
+    "MetricGroup": "l3_cache",
+    "ScaleUnit": "1core clocks"
+  },
+  {
+    "MetricName": "op_cache_fetch_miss_ratio",
+    "BriefDescription": "Op cache miss ratio for all fetches.",
+    "MetricExpr": "d_ratio(op_cache_hit_miss.op_cache_miss, op_cache_hit_miss.all_op_cache_accesses)",
+    "ScaleUnit": "100%"
+  },
+  {
+    "MetricName": "ic_fetch_miss_ratio",
+    "BriefDescription": "Instruction cache miss ratio for all fetches. An instruction cache miss will not be counted by this metric if it is an OC hit.",
+    "MetricExpr": "d_ratio(ic_tag_hit_miss.instruction_cache_miss, ic_tag_hit_miss.all_instruction_cache_accesses)",
+    "ScaleUnit": "100%"
+  },
+  {
+    "MetricName": "l1_data_cache_fills_from_memory",
+    "BriefDescription": "L1 data cache fills from DRAM or MMIO in any NUMA node.",
+    "MetricExpr": "ls_any_fills_from_sys.dram_io_all",
+    "MetricGroup": "l1_dcache"
+  },
+  {
+    "MetricName": "l1_data_cache_fills_from_remote_node",
+    "BriefDescription": "L1 data cache fills from a different NUMA node.",
+    "MetricExpr": "ls_any_fills_from_sys.far_all",
+    "MetricGroup": "l1_dcache"
+  },
+  {
+    "MetricName": "l1_data_cache_fills_from_same_ccx",
+    "BriefDescription": "L1 data cache fills from within the same CCX.",
+    "MetricExpr": "ls_any_fills_from_sys.local_all",
+    "MetricGroup": "l1_dcache"
+  },
+  {
+    "MetricName": "l1_data_cache_fills_from_different_ccx",
+    "BriefDescription": "L1 data cache fills from another CCX cache in any NUMA node.",
+    "MetricExpr": "ls_any_fills_from_sys.remote_cache",
+    "MetricGroup": "l1_dcache"
+  },
+  {
+    "MetricName": "all_l1_data_cache_fills",
+    "BriefDescription": "All L1 data cache fills.",
+    "MetricExpr": "ls_any_fills_from_sys.all",
+    "MetricGroup": "l1_dcache"
+  },
+  {
+    "MetricName": "l1_demand_data_cache_fills_from_local_l2",
+    "BriefDescription": "L1 demand data cache fills from local L2 cache.",
+    "MetricExpr": "ls_dmnd_fills_from_sys.local_l2",
+    "MetricGroup": "l1_dcache"
+  },
+  {
+    "MetricName": "l1_demand_data_cache_fills_from_same_ccx",
+    "BriefDescription": "L1 demand data cache fills from within the same CCX.",
+    "MetricExpr": "ls_dmnd_fills_from_sys.local_ccx",
+    "MetricGroup": "l1_dcache"
+  },
+  {
+    "MetricName": "l1_demand_data_cache_fills_from_near_cache",
+    "BriefDescription": "L1 demand data cache fills from another CCX cache in the same NUMA node.",
+    "MetricExpr": "ls_dmnd_fills_from_sys.near_cache",
+    "MetricGroup": "l1_dcache"
+  },
+  {
+    "MetricName": "l1_demand_data_cache_fills_from_near_memory",
+    "BriefDescription": "L1 demand data cache fills from DRAM or MMIO in the same NUMA node.",
+    "MetricExpr": "ls_dmnd_fills_from_sys.dram_io_near",
+    "MetricGroup": "l1_dcache"
+  },
+  {
+    "MetricName": "l1_demand_data_cache_fills_from_far_cache",
+    "BriefDescription": "L1 demand data cache fills from another CCX cache in a different NUMA node.",
+    "MetricExpr": "ls_dmnd_fills_from_sys.far_cache",
+    "MetricGroup": "l1_dcache"
+  },
+  {
+    "MetricName": "l1_demand_data_cache_fills_from_far_memory",
+    "BriefDescription": "L1 demand data cache fills from DRAM or MMIO in a different NUMA node.",
+    "MetricExpr": "ls_dmnd_fills_from_sys.dram_io_far",
+    "MetricGroup": "l1_dcache"
+  },
+  {
+    "MetricName": "l1_itlb_misses",
+    "BriefDescription": "L1 instruction TLB misses.",
+    "MetricExpr": "bp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_miss.all",
+    "MetricGroup": "tlb"
+  },
+  {
+    "MetricName": "l2_itlb_misses",
+    "BriefDescription": "L2 instruction TLB misses and instruction page walks.",
+    "MetricExpr": "bp_l1_tlb_miss_l2_tlb_miss.all",
+    "MetricGroup": "tlb"
+  },
+  {
+    "MetricName": "l1_dtlb_misses",
+    "BriefDescription": "L1 data TLB misses.",
+    "MetricExpr": "ls_l1_d_tlb_miss.all",
+    "MetricGroup": "tlb"
+  },
+  {
+    "MetricName": "l2_dtlb_misses",
+    "BriefDescription": "L2 data TLB misses and data page walks.",
+    "MetricExpr": "ls_l1_d_tlb_miss.all_l2_miss",
+    "MetricGroup": "tlb"
+  },
+  {
+    "MetricName": "all_tlbs_flushed",
+    "BriefDescription": "All TLBs flushed.",
+    "MetricExpr": "ls_tlb_flush.all",
+    "MetricGroup": "tlb"
+  },
+  {
+    "MetricName": "macro_ops_dispatched",
+    "BriefDescription": "Macro-ops dispatched.",
+    "MetricExpr": "de_src_op_disp.all",
+    "MetricGroup": "decoder"
+  },
+  {
+    "MetricName": "sse_avx_stalls",
+    "BriefDescription": "Mixed SSE/AVX stalls.",
+    "MetricExpr": "fp_disp_faults.sse_avx_all"
+  },
+  {
+    "MetricName": "macro_ops_retired",
+    "BriefDescription": "Macro-ops retired.",
+    "MetricExpr": "ex_ret_ops"
+  },
+  {
+    "MetricName": "dram_read_data_for_local_processor",
+    "BriefDescription": "DRAM read data for local processor.",
+    "MetricExpr": "local_processor_read_data_beats_cs0 + local_processor_read_data_beats_cs1 + local_processor_read_data_beats_cs2 + local_processor_read_data_beats_cs3 + local_processor_read_data_beats_cs4 + local_processor_read_data_beats_cs5 + local_processor_read_data_beats_cs6 + local_processor_read_data_beats_cs7 + local_processor_read_data_beats_cs8 + local_processor_read_data_beats_cs9 + local_processor_read_data_beats_cs10 + local_processor_read_data_beats_cs11",
+    "MetricGroup": "data_fabric",
+    "PerPkg": "1",
+    "ScaleUnit": "6.103515625e-5MiB"
+  },
+  {
+    "MetricName": "dram_write_data_for_local_processor",
+    "BriefDescription": "DRAM write data for local processor.",
+    "MetricExpr": "local_processor_write_data_beats_cs0 + local_processor_write_data_beats_cs1 + local_processor_write_data_beats_cs2 + local_processor_write_data_beats_cs3 + local_processor_write_data_beats_cs4 + local_processor_write_data_beats_cs5 + local_processor_write_data_beats_cs6 + local_processor_write_data_beats_cs7 + local_processor_write_data_beats_cs8 + local_processor_write_data_beats_cs9 + local_processor_write_data_beats_cs10 + local_processor_write_data_beats_cs11",
+    "MetricGroup": "data_fabric",
+    "PerPkg": "1",
+    "ScaleUnit": "6.103515625e-5MiB"
+  },
+  {
+    "MetricName": "dram_read_data_for_remote_processor",
+    "BriefDescription": "DRAM read data for remote processor.",
+    "MetricExpr": "remote_processor_read_data_beats_cs0 + remote_processor_read_data_beats_cs1 + remote_processor_read_data_beats_cs2 + remote_processor_read_data_beats_cs3 + remote_processor_read_data_beats_cs4 + remote_processor_read_data_beats_cs5 + remote_processor_read_data_beats_cs6 + remote_processor_read_data_beats_cs7 + remote_processor_read_data_beats_cs8 + remote_processor_read_data_beats_cs9 + remote_processor_read_data_beats_cs10 + remote_processor_read_data_beats_cs11",
+    "MetricGroup": "data_fabric",
+    "PerPkg": "1",
+    "ScaleUnit": "6.103515625e-5MiB"
+  },
+  {
+    "MetricName": "dram_write_data_for_remote_processor",
+    "BriefDescription": "DRAM write data for remote processor.",
+    "MetricExpr": "remote_processor_write_data_beats_cs0 + remote_processor_write_data_beats_cs1 + remote_processor_write_data_beats_cs2 + remote_processor_write_data_beats_cs3 + remote_processor_write_data_beats_cs4 + remote_processor_write_data_beats_cs5 + remote_processor_write_data_beats_cs6 + remote_processor_write_data_beats_cs7 + remote_processor_write_data_beats_cs8 + remote_processor_write_data_beats_cs9 + remote_processor_write_data_beats_cs10 + remote_processor_write_data_beats_cs11",
+    "MetricGroup": "data_fabric",
+    "PerPkg": "1",
+    "ScaleUnit": "6.103515625e-5MiB"
+  },
+  {
+    "MetricName": "local_socket_upstream_dma_read_data",
+    "BriefDescription": "Local socket upstream DMA read data.",
+    "MetricExpr": "local_socket_upstream_read_beats_iom0 + local_socket_upstream_read_beats_iom1 + local_socket_upstream_read_beats_iom2 + local_socket_upstream_read_beats_iom3",
+    "MetricGroup": "data_fabric",
+    "PerPkg": "1",
+    "ScaleUnit": "6.103515625e-5MiB"
+  },
+  {
+    "MetricName": "local_socket_upstream_dma_write_data",
+    "BriefDescription": "Local socket upstream DMA write data.",
+    "MetricExpr": "local_socket_upstream_write_beats_iom0 + local_socket_upstream_write_beats_iom1 + local_socket_upstream_write_beats_iom2 + local_socket_upstream_write_beats_iom3",
+    "MetricGroup": "data_fabric",
+    "PerPkg": "1",
+    "ScaleUnit": "6.103515625e-5MiB"
+  },
+  {
+    "MetricName": "remote_socket_upstream_dma_read_data",
+    "BriefDescription": "Remote socket upstream DMA read data.",
+    "MetricExpr": "remote_socket_upstream_read_beats_iom0 + remote_socket_upstream_read_beats_iom1 + remote_socket_upstream_read_beats_iom2 + remote_socket_upstream_read_beats_iom3",
+    "MetricGroup": "data_fabric",
+    "PerPkg": "1",
+    "ScaleUnit": "6.103515625e-5MiB"
+  },
+  {
+    "MetricName": "remote_socket_upstream_dma_write_data",
+    "BriefDescription": "Remote socket upstream DMA write data.",
+    "MetricExpr": "remote_socket_upstream_write_beats_iom0 + remote_socket_upstream_write_beats_iom1 + remote_socket_upstream_write_beats_iom2 + remote_socket_upstream_write_beats_iom3",
+    "MetricGroup": "data_fabric",
+    "PerPkg": "1",
+    "ScaleUnit": "6.103515625e-5MiB"
+  },
+  {
+    "MetricName": "local_socket_inbound_data_to_cpu",
+    "BriefDescription": "Local socket inbound data to the CPU (e.g. read data).",
+    "MetricExpr": "local_socket_inf0_inbound_data_beats_ccm0 + local_socket_inf1_inbound_data_beats_ccm0 + local_socket_inf0_inbound_data_beats_ccm1 + local_socket_inf1_inbound_data_beats_ccm1 + local_socket_inf0_inbound_data_beats_ccm2 + local_socket_inf1_inbound_data_beats_ccm2 + local_socket_inf0_inbound_data_beats_ccm3 + local_socket_inf1_inbound_data_beats_ccm3 + local_socket_inf0_inbound_data_beats_ccm4 + local_socket_inf1_inbound_data_beats_ccm4 + local_socket_inf0_inbound_data_beats_ccm5 + local_socket_inf1_inbound_data_beats_ccm5 + local_socket_inf0_inbound_data_beats_ccm6 + local_socket_inf1_inbound_data_beats_ccm6 + local_socket_inf0_inbound_data_beats_ccm7 + local_socket_inf1_inbound_data_beats_ccm7",
+    "MetricGroup": "data_fabric",
+    "PerPkg": "1",
+    "ScaleUnit": "3.0517578125e-5MiB"
+  },
+  {
+    "MetricName": "local_socket_outbound_data_from_cpu",
+    "BriefDescription": "Local socket outbound data from the CPU (e.g. write data).",
+    "MetricExpr": "local_socket_inf0_outbound_data_beats_ccm0 + local_socket_inf1_outbound_data_beats_ccm0 + local_socket_inf0_outbound_data_beats_ccm1 + local_socket_inf1_outbound_data_beats_ccm1 + local_socket_inf0_outbound_data_beats_ccm2 + local_socket_inf1_outbound_data_beats_ccm2 + local_socket_inf0_outbound_data_beats_ccm3 + local_socket_inf1_outbound_data_beats_ccm3 + local_socket_inf0_outbound_data_beats_ccm4 + local_socket_inf1_outbound_data_beats_ccm4 + local_socket_inf0_outbound_data_beats_ccm5 + local_socket_inf1_outbound_data_beats_ccm5 + local_socket_inf0_outbound_data_beats_ccm6 + local_socket_inf1_outbound_data_beats_ccm6 + local_socket_inf0_outbound_data_beats_ccm7 + local_socket_inf1_outbound_data_beats_ccm7",
+    "MetricGroup": "data_fabric",
+    "PerPkg": "1",
+    "ScaleUnit": "6.103515625e-5MiB"
+  },
+  {
+    "MetricName": "remote_socket_inbound_data_to_cpu",
+    "BriefDescription": "Remote socket inbound data to the CPU (e.g. read data).",
+    "MetricExpr": "remote_socket_inf0_inbound_data_beats_ccm0 + remote_socket_inf1_inbound_data_beats_ccm0 + remote_socket_inf0_inbound_data_beats_ccm1 + remote_socket_inf1_inbound_data_beats_ccm1 + remote_socket_inf0_inbound_data_beats_ccm2 + remote_socket_inf1_inbound_data_beats_ccm2 + remote_socket_inf0_inbound_data_beats_ccm3 + remote_socket_inf1_inbound_data_beats_ccm3 + remote_socket_inf0_inbound_data_beats_ccm4 + remote_socket_inf1_inbound_data_beats_ccm4 + remote_socket_inf0_inbound_data_beats_ccm5 + remote_socket_inf1_inbound_data_beats_ccm5 + remote_socket_inf0_inbound_data_beats_ccm6 + remote_socket_inf1_inbound_data_beats_ccm6 + remote_socket_inf0_inbound_data_beats_ccm7 + remote_socket_inf1_inbound_data_beats_ccm7",
+    "MetricGroup": "data_fabric",
+    "PerPkg": "1",
+    "ScaleUnit": "3.0517578125e-5MiB"
+  },
+  {
+    "MetricName": "remote_socket_outbound_data_from_cpu",
+    "BriefDescription": "Remote socket outbound data from the CPU (e.g. write data).",
+    "MetricExpr": "remote_socket_inf0_outbound_data_beats_ccm0 + remote_socket_inf1_outbound_data_beats_ccm0 + remote_socket_inf0_outbound_data_beats_ccm1 + remote_socket_inf1_outbound_data_beats_ccm1 + remote_socket_inf0_outbound_data_beats_ccm2 + remote_socket_inf1_outbound_data_beats_ccm2 + remote_socket_inf0_outbound_data_beats_ccm3 + remote_socket_inf1_outbound_data_beats_ccm3 + remote_socket_inf0_outbound_data_beats_ccm4 + remote_socket_inf1_outbound_data_beats_ccm4 + remote_socket_inf0_outbound_data_beats_ccm5 + remote_socket_inf1_outbound_data_beats_ccm5 + remote_socket_inf0_outbound_data_beats_ccm6 + remote_socket_inf1_outbound_data_beats_ccm6 + remote_socket_inf0_outbound_data_beats_ccm7 + remote_socket_inf1_outbound_data_beats_ccm7",
+    "MetricGroup": "data_fabric",
+    "PerPkg": "1",
+    "ScaleUnit": "6.103515625e-5MiB"
+  },
+  {
+    "MetricName": "local_socket_outbound_data_from_all_links",
+    "BriefDescription": "Outbound data from all links (local socket).",
+    "MetricExpr": "local_socket_outbound_data_beats_link0 + local_socket_outbound_data_beats_link1 + local_socket_outbound_data_beats_link2 + local_socket_outbound_data_beats_link3 + local_socket_outbound_data_beats_link4 + local_socket_outbound_data_beats_link5 + local_socket_outbound_data_beats_link6 + local_socket_outbound_data_beats_link7",
+    "MetricGroup": "data_fabric",
+    "PerPkg": "1",
+    "ScaleUnit": "6.103515625e-5MiB"
+  }
+]
-- 
GitLab


From 5fe089d3a3eb4c1cd416993cd4bc7e3c0c30297a Mon Sep 17 00:00:00 2001
From: Sandipan Das <sandipan.das@amd.com>
Date: Wed, 14 Dec 2022 13:56:52 +0530
Subject: [PATCH 598/875] perf vendor events amd: Add Zen 4 mapping

Add a regular expression in the map file so that appropriate JSON event
files are used for AMD Zen 4 processors. Restrict the regular expression
for AMD Zen 3 processors to known model ranges since they also belong to
Family 19h.

Signed-off-by: Sandipan Das <sandipan.das@amd.com>
Acked-by: Ian Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ananth Narayan <ananth.narayan@amd.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Jirka Hladky <jhladky@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@amd.com>
Cc: Stephane Eranian <eranian@google.com>
Link: https://lore.kernel.org/r/20221214082652.419965-5-sandipan.das@amd.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/pmu-events/arch/x86/mapfile.csv | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index a515d9594ced2..711a4ef05fdf9 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -32,4 +32,5 @@ GenuineIntel-6-25,v3,westmereep-sp,core
 GenuineIntel-6-2F,v3,westmereex,core
 AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core
 AuthenticAMD-23-[[:xdigit:]]+,v1,amdzen2,core
-AuthenticAMD-25-[[:xdigit:]]+,v1,amdzen3,core
+AuthenticAMD-25-([245][[:xdigit:]]|[[:xdigit:]]),v1,amdzen3,core
+AuthenticAMD-25-[[:xdigit:]]+,v1,amdzen4,core
-- 
GitLab


From c3c2e8ebe365ae028ec82ceab039b2035875b6d5 Mon Sep 17 00:00:00 2001
From: Arnaldo Carvalho de Melo <acme@redhat.com>
Date: Wed, 21 Dec 2022 14:08:20 -0300
Subject: [PATCH 599/875] perf build: Remove explicit reference to python 2.x
 devel files

If the libpython feature test (tools/build/feature/test-libpython.c)
fails, then the python-devel is missing, it doesn't mattere if it is for
python2 or 3, remove that explicit 2.x reference.

Reported-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/Makefile.config | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config
index c21bd6010be13..c2504c39bdcb8 100644
--- a/tools/perf/Makefile.config
+++ b/tools/perf/Makefile.config
@@ -886,7 +886,7 @@ else
     else
 
       ifneq ($(feature-libpython), 1)
-        $(call disable-python,No 'Python.h' (for Python 2.x support) was found: disables Python support - please install python-devel/python-dev)
+        $(call disable-python,No 'Python.h' was found: disables Python support - please install python-devel/python-dev)
       else
          LDFLAGS += $(PYTHON_EMBED_LDFLAGS)
          EXTLIBS += $(PYTHON_EMBED_LIBADD)
-- 
GitLab


From 9854e7ad35fecf3007d44e58484e05cf39a62bd6 Mon Sep 17 00:00:00 2001
From: Hans-Peter Nilsson <hp@axis.com>
Date: Mon, 28 Dec 2020 03:41:59 +0100
Subject: [PATCH 600/875] perf arm64: Simplify mksyscalltbl

This patch isn't intended to have any effect on the compiled code.  It
just removes one level of indirection: calling the *host* compiler to
build and then run a program that just printf:s the numerical entries of
the syscall-table.  In other words, the generated syscalls.c changes
from:

	[46] = "ftruncate",
to:
	[__NR3264_ftruncate] = "ftruncate",

The latter is as good as the former to the user of perf, and this can be
done directly by the shell-script.  The syscalls defined as non-literal
values (like "#define __NR_ftruncate __NR3264_ftruncate") are trivially
resolved at compile-time without namespace-leaking and/or collision for
its sole user, perf/util/syscalltbl.c, that just #includes the generated
file.  A future "-mabi=32" support would probably have to handle this
differently, but that is a pre-existing problem not affected by this
simplification.

Calling the *host* compiler only complicates things and accidentally can
get a completely wrong set of files and syscall numbers, see earlier
commits.  Note that the script parameter hostcc is now unused.

At the time of this patch, powerpc (the origin, see comments), and also
e.g. x86 has moved on, from filtering "gcc -dM -E" output to reading
separate specific text-file, a table of syscall numbers.  IMHO should
arm64 consider adopting this.

Signed-off-by: Hans-Peter Nilsson <hp@axis.com>

Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Reviewed-by: Leo Yan <leo.yan@linaro.org>
Tested-by: Leo Yan <leo.yan@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Kim Phillips <kim.phillips@arm.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20201228024159.2BB66203B5@pchp3.se.axis.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../arch/arm64/entry/syscalls/mksyscalltbl    | 23 +++----------------
 1 file changed, 3 insertions(+), 20 deletions(-)

diff --git a/tools/perf/arch/arm64/entry/syscalls/mksyscalltbl b/tools/perf/arch/arm64/entry/syscalls/mksyscalltbl
index a7ca48d1e37bc..22cdf911dd9aa 100755
--- a/tools/perf/arch/arm64/entry/syscalls/mksyscalltbl
+++ b/tools/perf/arch/arm64/entry/syscalls/mksyscalltbl
@@ -23,34 +23,17 @@ create_table_from_c()
 {
 	local sc nr last_sc
 
-	create_table_exe=`mktemp ${TMPDIR:-/tmp}/create-table-XXXXXX`
-
-	{
-
-	cat <<-_EoHEADER
-		#include <stdio.h>
-		#include "$input"
-		int main(int argc, char *argv[])
-		{
-	_EoHEADER
-
 	while read sc nr; do
-		printf "%s\n" "	printf(\"\\t[%d] = \\\"$sc\\\",\\n\", __NR_$sc);"
+		printf "%s\n" "	[$nr] = \"$sc\","
 		last_sc=$sc
 	done
 
-	printf "%s\n" "	printf(\"#define SYSCALLTBL_ARM64_MAX_ID %d\\n\", __NR_$last_sc);"
-	printf "}\n"
-
-	} | $hostcc -I $incpath/include/uapi -o $create_table_exe -x c -
-
-	$create_table_exe
-
-	rm -f $create_table_exe
+	printf "%s\n" "#define SYSCALLTBL_ARM64_MAX_ID __NR_$last_sc"
 }
 
 create_table()
 {
+	echo "#include \"$input\""
 	echo "static const char *syscalltbl_arm64[] = {"
 	create_table_from_c
 	echo "};"
-- 
GitLab


From e1d900df63adcb748905131dd6258e570e11aed1 Mon Sep 17 00:00:00 2001
From: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Date: Tue, 20 Dec 2022 13:21:44 +0530
Subject: [PATCH 601/875] drm/amdgpu: enable VCN DPG for GC IP v11.0.4

Enable VCN Dynamic Power Gating control for GC IP v11.0.4.

Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Reviewed-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.0, 6.1
---
 drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 7d5fdf450d0cc..5562670b7b521 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -666,6 +666,7 @@ static int soc21_common_early_init(void *handle)
 			AMD_CG_SUPPORT_VCN_MGCG |
 			AMD_CG_SUPPORT_JPEG_MGCG;
 		adev->pg_flags = AMD_PG_SUPPORT_VCN |
+			AMD_PG_SUPPORT_VCN_DPG |
 			AMD_PG_SUPPORT_GFX_PG |
 			AMD_PG_SUPPORT_JPEG;
 		adev->external_rev_id = adev->rev_id + 0x1;
-- 
GitLab


From f257ba9c160f4cb13e88b9be83e39a0e94d45c70 Mon Sep 17 00:00:00 2001
From: Arnaldo Carvalho de Melo <acme@redhat.com>
Date: Wed, 21 Dec 2022 17:30:38 -0300
Subject: [PATCH 602/875] perf scripting python: Don't be strict at handling
 libtraceevent enumerations
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The build was failing on archlinux because it has a newer libtraceevent
that added a new entry to the tep_print_arg_type enum:

    19.72 archlinux:base                : FAIL gcc version 12.2.0 (GCC)
    util/scripting-engines/trace-event-python.c: In function ‘define_event_symbols’:
    util/scripting-engines/trace-event-python.c:281:9: error: enumeration value ‘TEP_PRINT_CPUMASK’ not handled in switch [-Werror=switch-enum]
      281 |         switch (args->type) {
          |         ^~~~~~
    cc1: all warnings being treated as errors

Since we build with distros that have different versions of
libtraceevent and there is no way to easily test if these enum entries
are available, just disable -Werror=switch-enum for that specific
object.

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/scripting-engines/Build | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/perf/util/scripting-engines/Build b/tools/perf/util/scripting-engines/Build
index d47820c0b4d47..2c96aa3cc1ec8 100644
--- a/tools/perf/util/scripting-engines/Build
+++ b/tools/perf/util/scripting-engines/Build
@@ -5,4 +5,4 @@ endif
 
 CFLAGS_trace-event-perl.o += $(PERL_EMBED_CCOPTS) -Wno-redundant-decls -Wno-strict-prototypes -Wno-unused-parameter -Wno-shadow -Wno-nested-externs -Wno-undef -Wno-switch-default -Wno-bad-function-cast -Wno-declaration-after-statement -Wno-switch-enum
 
-CFLAGS_trace-event-python.o += $(PYTHON_EMBED_CCOPTS) -Wno-redundant-decls -Wno-strict-prototypes -Wno-unused-parameter -Wno-shadow -Wno-deprecated-declarations
+CFLAGS_trace-event-python.o += $(PYTHON_EMBED_CCOPTS) -Wno-redundant-decls -Wno-strict-prototypes -Wno-unused-parameter -Wno-shadow -Wno-deprecated-declarations -Wno-switch-enum
-- 
GitLab


From 23fffb2f09ce1145cbd751801d45ba74acaa6542 Mon Sep 17 00:00:00 2001
From: Jens Axboe <axboe@kernel.dk>
Date: Wed, 21 Dec 2022 07:11:33 -0700
Subject: [PATCH 603/875] io_uring/cancel: re-grab ctx mutex after finishing
 wait

If we have a signal pending during cancelations, it'll cause the
task_work run to return an error. Since we didn't run task_work, the
current task is left in TASK_INTERRUPTIBLE state when we need to
re-grab the ctx mutex, and the kernel will rightfully complain about
that.

Move the lock grabbing for the error cases outside the loop to avoid
that issue.

Reported-by: syzbot+7df055631cd1be4586fd@syzkaller.appspotmail.com
Link: https://lore.kernel.org/io-uring/0000000000003a14a905f05050b0@google.com/
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 io_uring/cancel.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/io_uring/cancel.c b/io_uring/cancel.c
index 2291a53cdabd1..b4f5dfacc0c31 100644
--- a/io_uring/cancel.c
+++ b/io_uring/cancel.c
@@ -288,24 +288,23 @@ int io_sync_cancel(struct io_ring_ctx *ctx, void __user *arg)
 
 		ret = __io_sync_cancel(current->io_uring, &cd, sc.fd);
 
+		mutex_unlock(&ctx->uring_lock);
 		if (ret != -EALREADY)
 			break;
 
-		mutex_unlock(&ctx->uring_lock);
 		ret = io_run_task_work_sig(ctx);
-		if (ret < 0) {
-			mutex_lock(&ctx->uring_lock);
+		if (ret < 0)
 			break;
-		}
 		ret = schedule_hrtimeout(&timeout, HRTIMER_MODE_ABS);
-		mutex_lock(&ctx->uring_lock);
 		if (!ret) {
 			ret = -ETIME;
 			break;
 		}
+		mutex_lock(&ctx->uring_lock);
 	} while (1);
 
 	finish_wait(&ctx->cq_wait, &wait);
+	mutex_lock(&ctx->uring_lock);
 
 	if (ret == -ENOENT || ret > 0)
 		ret = 0;
-- 
GitLab


From c1c4a8b217213c1924eabf4f28385bbee9cc50c1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Christian=20K=C3=B6nig?= <ckoenig.leichtzumerken@gmail.com>
Date: Mon, 19 Dec 2022 11:47:18 +0100
Subject: [PATCH 604/875] drm/amdgpu: grab extra fence reference for
 drm_sched_job_add_dependency
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

That function consumes the reference.

Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Reported-by: Borislav Petkov (AMD) <bp@alien8.de>
Tested-by: Borislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: Christian König <christian.koenig@amd.com>
Fixes: aab9cf7b6954 ("drm/amdgpu: use scheduler dependencies for VM updates")
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
index 59cf64216fbb6..535cd6569bccf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
@@ -238,8 +238,10 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p,
 	/* Wait for PD/PT moves to be completed */
 	dma_resv_iter_begin(&cursor, bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL);
 	dma_resv_for_each_fence_unlocked(&cursor, fence) {
+		dma_fence_get(fence);
 		r = drm_sched_job_add_dependency(&p->job->base, fence);
 		if (r) {
+			dma_fence_put(fence);
 			dma_resv_iter_end(&cursor);
 			return r;
 		}
-- 
GitLab


From 6f12be792fde994ed934168f93c2a0d2a0cf0bc5 Mon Sep 17 00:00:00 2001
From: Vlastimil Babka <vbabka@suse.cz>
Date: Fri, 16 Dec 2022 17:32:27 +0100
Subject: [PATCH 605/875] mm, mremap: fix mremap() expanding vma with addr
 inside vma
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Since 6.1 we have noticed random rpm install failures that were tracked to
mremap() returning -ENOMEM and to commit ca3d76b0aa80 ("mm: add merging
after mremap resize").

The problem occurs when mremap() expands a VMA in place, but using an
starting address that's not vma->vm_start, but somewhere in the middle.
The extension_pgoff calculation introduced by the commit is wrong in that
case, so vma_merge() fails due to pgoffs not being compatible.  Fix the
calculation.

By the way it seems that the situations, where rpm now expands a vma from
the middle, were made possible also due to that commit, thanks to the
improved vma merging.  Yet it should work just fine, except for the buggy
calculation.

Link: https://lkml.kernel.org/r/20221216163227.24648-1-vbabka@suse.cz
Reported-by: Jiri Slaby <jirislaby@kernel.org>
  Link: https://bugzilla.suse.com/show_bug.cgi?id=1206359
Fixes: ca3d76b0aa80 ("mm: add merging after mremap resize")
Signed-off-by: Vlastimil Babka <vbabka@suse.cz>
Cc: Jakub Matěna <matenajakub@gmail.com>
Cc: "Kirill A . Shutemov" <kirill@shutemov.name>
Cc: Liam Howlett <liam.howlett@oracle.com>
Cc: Matthew Wilcox <willy@infradead.org>
Cc: Mel Gorman <mgorman@techsingularity.net>
Cc: Michal Hocko <mhocko@kernel.org>
Cc: <stable@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 mm/mremap.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/mm/mremap.c b/mm/mremap.c
index e465ffe279bb0..fe587c5d65913 100644
--- a/mm/mremap.c
+++ b/mm/mremap.c
@@ -1016,7 +1016,8 @@ SYSCALL_DEFINE5(mremap, unsigned long, addr, unsigned long, old_len,
 			long pages = (new_len - old_len) >> PAGE_SHIFT;
 			unsigned long extension_start = addr + old_len;
 			unsigned long extension_end = addr + new_len;
-			pgoff_t extension_pgoff = vma->vm_pgoff + (old_len >> PAGE_SHIFT);
+			pgoff_t extension_pgoff = vma->vm_pgoff +
+				((extension_start - vma->vm_start) >> PAGE_SHIFT);
 
 			if (vma->vm_flags & VM_ACCOUNT) {
 				if (security_vm_enough_memory_mm(mm, pages)) {
-- 
GitLab


From 38ce7c9bdfc228c14d7621ba36d3eebedd9d4f76 Mon Sep 17 00:00:00 2001
From: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Date: Thu, 15 Dec 2022 14:46:21 -0500
Subject: [PATCH 606/875] mm/mempolicy: fix memory leak in
 set_mempolicy_home_node system call

When encountering any vma in the range with policy other than MPOL_BIND or
MPOL_PREFERRED_MANY, an error is returned without issuing a mpol_put on
the policy just allocated with mpol_dup().

This allows arbitrary users to leak kernel memory.

Link: https://lkml.kernel.org/r/20221215194621.202816-1-mathieu.desnoyers@efficios.com
Fixes: c6018b4b2549 ("mm/mempolicy: add set_mempolicy_home_node syscall")
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
Reviewed-by: "Huang, Ying" <ying.huang@intel.com>
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Acked-by: Michal Hocko <mhocko@suse.com>
Cc: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Feng Tang <feng.tang@intel.com>
Cc: Michal Hocko <mhocko@kernel.org>
Cc: Andrea Arcangeli <aarcange@redhat.com>
Cc: Mel Gorman <mgorman@techsingularity.net>
Cc: Mike Kravetz <mike.kravetz@oracle.com>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: Vlastimil Babka <vbabka@suse.cz>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Huang Ying <ying.huang@intel.com>
Cc: <stable@vger.kernel.org>	[5.17+]
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 mm/mempolicy.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/mm/mempolicy.c b/mm/mempolicy.c
index 61aa9aedb7289..02c8a712282f1 100644
--- a/mm/mempolicy.c
+++ b/mm/mempolicy.c
@@ -1540,6 +1540,7 @@ SYSCALL_DEFINE4(set_mempolicy_home_node, unsigned long, start, unsigned long, le
 		 * the home node for vmas we already updated before.
 		 */
 		if (new->mode != MPOL_BIND && new->mode != MPOL_PREFERRED_MANY) {
+			mpol_put(new);
 			err = -EOPNOTSUPP;
 			break;
 		}
-- 
GitLab


From aaa746ad8b30f38ef89a301faf339ef1c19cf33a Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Thu, 15 Dec 2022 17:30:17 +0100
Subject: [PATCH 607/875] kmsan: include linux/vmalloc.h

This is needed for the vmap/vunmap declarations:

mm/kmsan/kmsan_test.c:316:9: error: implicit declaration of function 'vmap' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
        vbuf = vmap(pages, npages, VM_MAP, PAGE_KERNEL);
               ^
mm/kmsan/kmsan_test.c:316:29: error: use of undeclared identifier 'VM_MAP'
        vbuf = vmap(pages, npages, VM_MAP, PAGE_KERNEL);
                                   ^
mm/kmsan/kmsan_test.c:322:3: error: implicit declaration of function 'vunmap' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
                vunmap(vbuf);
                ^

Link: https://lkml.kernel.org/r/20221215163046.4079767-1-arnd@kernel.org
Fixes: 8ed691b02ade ("kmsan: add tests for KMSAN")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Alexander Potapenko <glider@google.com>
Cc: Dmitry Vyukov <dvyukov@google.com>
Cc: Marco Elver <elver@google.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 mm/kmsan/kmsan_test.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/mm/kmsan/kmsan_test.c b/mm/kmsan/kmsan_test.c
index eb44ef3c5f290..088e21a48dc4b 100644
--- a/mm/kmsan/kmsan_test.c
+++ b/mm/kmsan/kmsan_test.c
@@ -22,6 +22,7 @@
 #include <linux/spinlock.h>
 #include <linux/string.h>
 #include <linux/tracepoint.h>
+#include <linux/vmalloc.h>
 #include <trace/events/printk.h>
 
 static DEFINE_PER_CPU(int, per_cpu_var);
-- 
GitLab


From 7ba594d700998bafa96a75360d2e060aa39156d2 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Thu, 15 Dec 2022 17:26:57 +0100
Subject: [PATCH 608/875] kmsan: export kmsan_handle_urb

USB support can be in a loadable module, and this causes a link failure
with KMSAN:

ERROR: modpost: "kmsan_handle_urb" [drivers/usb/core/usbcore.ko] undefined!

Export the symbol so it can be used by this module.

Link: https://lkml.kernel.org/r/20221215162710.3802378-1-arnd@kernel.org
Fixes: 553a80188a5d ("kmsan: handle memory sent to/from USB")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Alexander Potapenko <glider@google.com>
Cc: Dmitry Vyukov <dvyukov@google.com>
Cc: Marco Elver <elver@google.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 mm/kmsan/hooks.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/mm/kmsan/hooks.c b/mm/kmsan/hooks.c
index 35f6b6e6a908c..3807502766a3e 100644
--- a/mm/kmsan/hooks.c
+++ b/mm/kmsan/hooks.c
@@ -260,6 +260,7 @@ void kmsan_handle_urb(const struct urb *urb, bool is_out)
 					       urb->transfer_buffer_length,
 					       /*checked*/ false);
 }
+EXPORT_SYMBOL_GPL(kmsan_handle_urb);
 
 static void kmsan_handle_dma_page(const void *addr, size_t size,
 				  enum dma_data_direction dir)
-- 
GitLab


From e700898fa075c69b3ae02b702ab57fb75e1a82ec Mon Sep 17 00:00:00 2001
From: Mike Kravetz <mike.kravetz@oracle.com>
Date: Mon, 12 Dec 2022 15:50:41 -0800
Subject: [PATCH 609/875] hugetlb: really allocate vma lock for all sharable
 vmas

Commit bbff39cc6cbc ("hugetlb: allocate vma lock for all sharable vmas")
removed the pmd sharable checks in the vma lock helper routines.  However,
it left the functional version of helper routines behind #ifdef
CONFIG_ARCH_WANT_HUGE_PMD_SHARE.  Therefore, the vma lock is not being
used for sharable vmas on architectures that do not support pmd sharing.
On these architectures, a potential fault/truncation race is exposed that
could leave pages in a hugetlb file past i_size until the file is removed.

Move the functional vma lock helpers outside the ifdef, and remove the
non-functional stubs.  Since the vma lock is not just for pmd sharing,
rename the routine __vma_shareable_flags_pmd.

Link: https://lkml.kernel.org/r/20221212235042.178355-1-mike.kravetz@oracle.com
Fixes: bbff39cc6cbc ("hugetlb: allocate vma lock for all sharable vmas")
Signed-off-by: Mike Kravetz <mike.kravetz@oracle.com>
Reviewed-by: Miaohe Lin <linmiaohe@huawei.com>
Cc: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Cc: David Hildenbrand <david@redhat.com>
Cc: James Houghton <jthoughton@google.com>
Cc: Mina Almasry <almasrymina@google.com>
Cc: Muchun Song <songmuchun@bytedance.com>
Cc: Naoya Horiguchi <naoya.horiguchi@linux.dev>
Cc: Peter Xu <peterx@redhat.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 mm/hugetlb.c | 333 +++++++++++++++++++++++----------------------------
 1 file changed, 148 insertions(+), 185 deletions(-)

diff --git a/mm/hugetlb.c b/mm/hugetlb.c
index 77f36e3681e39..db895230ee7e4 100644
--- a/mm/hugetlb.c
+++ b/mm/hugetlb.c
@@ -255,6 +255,152 @@ static inline struct hugepage_subpool *subpool_vma(struct vm_area_struct *vma)
 	return subpool_inode(file_inode(vma->vm_file));
 }
 
+/*
+ * hugetlb vma_lock helper routines
+ */
+static bool __vma_shareable_lock(struct vm_area_struct *vma)
+{
+	return vma->vm_flags & (VM_MAYSHARE | VM_SHARED) &&
+		vma->vm_private_data;
+}
+
+void hugetlb_vma_lock_read(struct vm_area_struct *vma)
+{
+	if (__vma_shareable_lock(vma)) {
+		struct hugetlb_vma_lock *vma_lock = vma->vm_private_data;
+
+		down_read(&vma_lock->rw_sema);
+	}
+}
+
+void hugetlb_vma_unlock_read(struct vm_area_struct *vma)
+{
+	if (__vma_shareable_lock(vma)) {
+		struct hugetlb_vma_lock *vma_lock = vma->vm_private_data;
+
+		up_read(&vma_lock->rw_sema);
+	}
+}
+
+void hugetlb_vma_lock_write(struct vm_area_struct *vma)
+{
+	if (__vma_shareable_lock(vma)) {
+		struct hugetlb_vma_lock *vma_lock = vma->vm_private_data;
+
+		down_write(&vma_lock->rw_sema);
+	}
+}
+
+void hugetlb_vma_unlock_write(struct vm_area_struct *vma)
+{
+	if (__vma_shareable_lock(vma)) {
+		struct hugetlb_vma_lock *vma_lock = vma->vm_private_data;
+
+		up_write(&vma_lock->rw_sema);
+	}
+}
+
+int hugetlb_vma_trylock_write(struct vm_area_struct *vma)
+{
+	struct hugetlb_vma_lock *vma_lock = vma->vm_private_data;
+
+	if (!__vma_shareable_lock(vma))
+		return 1;
+
+	return down_write_trylock(&vma_lock->rw_sema);
+}
+
+void hugetlb_vma_assert_locked(struct vm_area_struct *vma)
+{
+	if (__vma_shareable_lock(vma)) {
+		struct hugetlb_vma_lock *vma_lock = vma->vm_private_data;
+
+		lockdep_assert_held(&vma_lock->rw_sema);
+	}
+}
+
+void hugetlb_vma_lock_release(struct kref *kref)
+{
+	struct hugetlb_vma_lock *vma_lock = container_of(kref,
+			struct hugetlb_vma_lock, refs);
+
+	kfree(vma_lock);
+}
+
+static void __hugetlb_vma_unlock_write_put(struct hugetlb_vma_lock *vma_lock)
+{
+	struct vm_area_struct *vma = vma_lock->vma;
+
+	/*
+	 * vma_lock structure may or not be released as a result of put,
+	 * it certainly will no longer be attached to vma so clear pointer.
+	 * Semaphore synchronizes access to vma_lock->vma field.
+	 */
+	vma_lock->vma = NULL;
+	vma->vm_private_data = NULL;
+	up_write(&vma_lock->rw_sema);
+	kref_put(&vma_lock->refs, hugetlb_vma_lock_release);
+}
+
+static void __hugetlb_vma_unlock_write_free(struct vm_area_struct *vma)
+{
+	if (__vma_shareable_lock(vma)) {
+		struct hugetlb_vma_lock *vma_lock = vma->vm_private_data;
+
+		__hugetlb_vma_unlock_write_put(vma_lock);
+	}
+}
+
+static void hugetlb_vma_lock_free(struct vm_area_struct *vma)
+{
+	/*
+	 * Only present in sharable vmas.
+	 */
+	if (!vma || !__vma_shareable_lock(vma))
+		return;
+
+	if (vma->vm_private_data) {
+		struct hugetlb_vma_lock *vma_lock = vma->vm_private_data;
+
+		down_write(&vma_lock->rw_sema);
+		__hugetlb_vma_unlock_write_put(vma_lock);
+	}
+}
+
+static void hugetlb_vma_lock_alloc(struct vm_area_struct *vma)
+{
+	struct hugetlb_vma_lock *vma_lock;
+
+	/* Only establish in (flags) sharable vmas */
+	if (!vma || !(vma->vm_flags & VM_MAYSHARE))
+		return;
+
+	/* Should never get here with non-NULL vm_private_data */
+	if (vma->vm_private_data)
+		return;
+
+	vma_lock = kmalloc(sizeof(*vma_lock), GFP_KERNEL);
+	if (!vma_lock) {
+		/*
+		 * If we can not allocate structure, then vma can not
+		 * participate in pmd sharing.  This is only a possible
+		 * performance enhancement and memory saving issue.
+		 * However, the lock is also used to synchronize page
+		 * faults with truncation.  If the lock is not present,
+		 * unlikely races could leave pages in a file past i_size
+		 * until the file is removed.  Warn in the unlikely case of
+		 * allocation failure.
+		 */
+		pr_warn_once("HugeTLB: unable to allocate vma specific lock\n");
+		return;
+	}
+
+	kref_init(&vma_lock->refs);
+	init_rwsem(&vma_lock->rw_sema);
+	vma_lock->vma = vma;
+	vma->vm_private_data = vma_lock;
+}
+
 /* Helper that removes a struct file_region from the resv_map cache and returns
  * it for use.
  */
@@ -6613,7 +6759,8 @@ bool hugetlb_reserve_pages(struct inode *inode,
 	}
 
 	/*
-	 * vma specific semaphore used for pmd sharing synchronization
+	 * vma specific semaphore used for pmd sharing and fault/truncation
+	 * synchronization
 	 */
 	hugetlb_vma_lock_alloc(vma);
 
@@ -6869,149 +7016,6 @@ void adjust_range_if_pmd_sharing_possible(struct vm_area_struct *vma,
 		*end = ALIGN(*end, PUD_SIZE);
 }
 
-static bool __vma_shareable_flags_pmd(struct vm_area_struct *vma)
-{
-	return vma->vm_flags & (VM_MAYSHARE | VM_SHARED) &&
-		vma->vm_private_data;
-}
-
-void hugetlb_vma_lock_read(struct vm_area_struct *vma)
-{
-	if (__vma_shareable_flags_pmd(vma)) {
-		struct hugetlb_vma_lock *vma_lock = vma->vm_private_data;
-
-		down_read(&vma_lock->rw_sema);
-	}
-}
-
-void hugetlb_vma_unlock_read(struct vm_area_struct *vma)
-{
-	if (__vma_shareable_flags_pmd(vma)) {
-		struct hugetlb_vma_lock *vma_lock = vma->vm_private_data;
-
-		up_read(&vma_lock->rw_sema);
-	}
-}
-
-void hugetlb_vma_lock_write(struct vm_area_struct *vma)
-{
-	if (__vma_shareable_flags_pmd(vma)) {
-		struct hugetlb_vma_lock *vma_lock = vma->vm_private_data;
-
-		down_write(&vma_lock->rw_sema);
-	}
-}
-
-void hugetlb_vma_unlock_write(struct vm_area_struct *vma)
-{
-	if (__vma_shareable_flags_pmd(vma)) {
-		struct hugetlb_vma_lock *vma_lock = vma->vm_private_data;
-
-		up_write(&vma_lock->rw_sema);
-	}
-}
-
-int hugetlb_vma_trylock_write(struct vm_area_struct *vma)
-{
-	struct hugetlb_vma_lock *vma_lock = vma->vm_private_data;
-
-	if (!__vma_shareable_flags_pmd(vma))
-		return 1;
-
-	return down_write_trylock(&vma_lock->rw_sema);
-}
-
-void hugetlb_vma_assert_locked(struct vm_area_struct *vma)
-{
-	if (__vma_shareable_flags_pmd(vma)) {
-		struct hugetlb_vma_lock *vma_lock = vma->vm_private_data;
-
-		lockdep_assert_held(&vma_lock->rw_sema);
-	}
-}
-
-void hugetlb_vma_lock_release(struct kref *kref)
-{
-	struct hugetlb_vma_lock *vma_lock = container_of(kref,
-			struct hugetlb_vma_lock, refs);
-
-	kfree(vma_lock);
-}
-
-static void __hugetlb_vma_unlock_write_put(struct hugetlb_vma_lock *vma_lock)
-{
-	struct vm_area_struct *vma = vma_lock->vma;
-
-	/*
-	 * vma_lock structure may or not be released as a result of put,
-	 * it certainly will no longer be attached to vma so clear pointer.
-	 * Semaphore synchronizes access to vma_lock->vma field.
-	 */
-	vma_lock->vma = NULL;
-	vma->vm_private_data = NULL;
-	up_write(&vma_lock->rw_sema);
-	kref_put(&vma_lock->refs, hugetlb_vma_lock_release);
-}
-
-static void __hugetlb_vma_unlock_write_free(struct vm_area_struct *vma)
-{
-	if (__vma_shareable_flags_pmd(vma)) {
-		struct hugetlb_vma_lock *vma_lock = vma->vm_private_data;
-
-		__hugetlb_vma_unlock_write_put(vma_lock);
-	}
-}
-
-static void hugetlb_vma_lock_free(struct vm_area_struct *vma)
-{
-	/*
-	 * Only present in sharable vmas.
-	 */
-	if (!vma || !__vma_shareable_flags_pmd(vma))
-		return;
-
-	if (vma->vm_private_data) {
-		struct hugetlb_vma_lock *vma_lock = vma->vm_private_data;
-
-		down_write(&vma_lock->rw_sema);
-		__hugetlb_vma_unlock_write_put(vma_lock);
-	}
-}
-
-static void hugetlb_vma_lock_alloc(struct vm_area_struct *vma)
-{
-	struct hugetlb_vma_lock *vma_lock;
-
-	/* Only establish in (flags) sharable vmas */
-	if (!vma || !(vma->vm_flags & VM_MAYSHARE))
-		return;
-
-	/* Should never get here with non-NULL vm_private_data */
-	if (vma->vm_private_data)
-		return;
-
-	vma_lock = kmalloc(sizeof(*vma_lock), GFP_KERNEL);
-	if (!vma_lock) {
-		/*
-		 * If we can not allocate structure, then vma can not
-		 * participate in pmd sharing.  This is only a possible
-		 * performance enhancement and memory saving issue.
-		 * However, the lock is also used to synchronize page
-		 * faults with truncation.  If the lock is not present,
-		 * unlikely races could leave pages in a file past i_size
-		 * until the file is removed.  Warn in the unlikely case of
-		 * allocation failure.
-		 */
-		pr_warn_once("HugeTLB: unable to allocate vma specific lock\n");
-		return;
-	}
-
-	kref_init(&vma_lock->refs);
-	init_rwsem(&vma_lock->rw_sema);
-	vma_lock->vma = vma;
-	vma->vm_private_data = vma_lock;
-}
-
 /*
  * Search for a shareable pmd page for hugetlb. In any case calls pmd_alloc()
  * and returns the corresponding pte. While this is not necessary for the
@@ -7100,47 +7104,6 @@ int huge_pmd_unshare(struct mm_struct *mm, struct vm_area_struct *vma,
 
 #else /* !CONFIG_ARCH_WANT_HUGE_PMD_SHARE */
 
-void hugetlb_vma_lock_read(struct vm_area_struct *vma)
-{
-}
-
-void hugetlb_vma_unlock_read(struct vm_area_struct *vma)
-{
-}
-
-void hugetlb_vma_lock_write(struct vm_area_struct *vma)
-{
-}
-
-void hugetlb_vma_unlock_write(struct vm_area_struct *vma)
-{
-}
-
-int hugetlb_vma_trylock_write(struct vm_area_struct *vma)
-{
-	return 1;
-}
-
-void hugetlb_vma_assert_locked(struct vm_area_struct *vma)
-{
-}
-
-void hugetlb_vma_lock_release(struct kref *kref)
-{
-}
-
-static void __hugetlb_vma_unlock_write_free(struct vm_area_struct *vma)
-{
-}
-
-static void hugetlb_vma_lock_free(struct vm_area_struct *vma)
-{
-}
-
-static void hugetlb_vma_lock_alloc(struct vm_area_struct *vma)
-{
-}
-
 pte_t *huge_pmd_share(struct mm_struct *mm, struct vm_area_struct *vma,
 		      unsigned long addr, pud_t *pud)
 {
-- 
GitLab


From 0abb964aae3da746ea2fd4301599a6fa26da58db Mon Sep 17 00:00:00 2001
From: Liam Howlett <liam.howlett@oracle.com>
Date: Mon, 19 Dec 2022 16:20:15 +0000
Subject: [PATCH 610/875] maple_tree: fix mas_spanning_rebalance() on
 insufficient data

Mike Rapoport contacted me off-list with a regression in running criu.
Periodic tests fail with an RCU stall during execution.  Although rare, it
is possible to hit this with other uses so this patch should be backported
to fix the regression.

This patchset adds the fix and a test case to the maple tree test
suite.


This patch (of 2):

An insufficient node was causing an out-of-bounds access on the node in
mas_leaf_max_gap().  The cause was the faulty detection of the new node
being a root node when overwriting many entries at the end of the tree.

Fix the detection of a new root and ensure there is sufficient data prior
to entering the spanning rebalance loop.

Link: https://lkml.kernel.org/r/20221219161922.2708732-1-Liam.Howlett@oracle.com
Link: https://lkml.kernel.org/r/20221219161922.2708732-2-Liam.Howlett@oracle.com
Fixes: 54a611b60590 ("Maple Tree: add new data structure")
Signed-off-by: Liam R. Howlett <Liam.Howlett@oracle.com>
Reported-by: Mike Rapoport <rppt@kernel.org>
Tested-by: Mike Rapoport <rppt@kernel.org>
Cc: Andrei Vagin <avagin@gmail.com>
Cc: Mike Rapoport <rppt@kernel.org>
Cc: Muhammad Usama Anjum <usama.anjum@collabora.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 lib/maple_tree.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/lib/maple_tree.c b/lib/maple_tree.c
index fe3947b800690..26e2045d3cda9 100644
--- a/lib/maple_tree.c
+++ b/lib/maple_tree.c
@@ -2994,7 +2994,9 @@ static int mas_spanning_rebalance(struct ma_state *mas,
 	mast->free = &free;
 	mast->destroy = &destroy;
 	l_mas.node = r_mas.node = m_mas.node = MAS_NONE;
-	if (!(mast->orig_l->min && mast->orig_r->max == ULONG_MAX) &&
+
+	/* Check if this is not root and has sufficient data.  */
+	if (((mast->orig_l->min != 0) || (mast->orig_r->max != ULONG_MAX)) &&
 	    unlikely(mast->bn->b_end <= mt_min_slots[mast->bn->type]))
 		mast_spanning_rebalance(mast);
 
-- 
GitLab


From c5651b31f51584bd1199b3a552c8211a8523d6e1 Mon Sep 17 00:00:00 2001
From: Liam Howlett <liam.howlett@oracle.com>
Date: Mon, 19 Dec 2022 16:20:15 +0000
Subject: [PATCH 611/875] test_maple_tree: add test for
 mas_spanning_rebalance() on insufficient data

Add a test to the maple tree test suite for the spanning rebalance
insufficient node issue does not go undetected again.

Link: https://lkml.kernel.org/r/20221219161922.2708732-3-Liam.Howlett@oracle.com
Fixes: 54a611b60590 ("Maple Tree: add new data structure")
Signed-off-by: Liam R. Howlett <Liam.Howlett@oracle.com>
Cc: Andrei Vagin <avagin@gmail.com>
Cc: Mike Rapoport <rppt@kernel.org>
Cc: Muhammad Usama Anjum <usama.anjum@collabora.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 lib/test_maple_tree.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/lib/test_maple_tree.c b/lib/test_maple_tree.c
index f425f169ef089..497fc93ccf9ec 100644
--- a/lib/test_maple_tree.c
+++ b/lib/test_maple_tree.c
@@ -2498,6 +2498,25 @@ static noinline void check_dup(struct maple_tree *mt)
 	}
 }
 
+static noinline void check_bnode_min_spanning(struct maple_tree *mt)
+{
+	int i = 50;
+	MA_STATE(mas, mt, 0, 0);
+
+	mt_set_non_kernel(9999);
+	mas_lock(&mas);
+	do {
+		mas_set_range(&mas, i*10, i*10+9);
+		mas_store(&mas, check_bnode_min_spanning);
+	} while (i--);
+
+	mas_set_range(&mas, 240, 509);
+	mas_store(&mas, NULL);
+	mas_unlock(&mas);
+	mas_destroy(&mas);
+	mt_set_non_kernel(0);
+}
+
 static DEFINE_MTREE(tree);
 static int maple_tree_seed(void)
 {
@@ -2742,6 +2761,10 @@ static int maple_tree_seed(void)
 	check_dup(&tree);
 	mtree_destroy(&tree);
 
+	mt_init_flags(&tree, MT_FLAGS_ALLOC_RANGE);
+	check_bnode_min_spanning(&tree);
+	mtree_destroy(&tree);
+
 #if defined(BENCH)
 skip:
 #endif
-- 
GitLab


From e96b95c2b7a63a454b6498e2df67aac14d046d13 Mon Sep 17 00:00:00 2001
From: Rickard x Andersson <rickaran@axis.com>
Date: Tue, 20 Dec 2022 11:23:18 +0100
Subject: [PATCH 612/875] gcov: add support for checksum field

In GCC version 12.1 a checksum field was added.

This patch fixes a kernel crash occurring during boot when using
gcov-kernel with GCC version 12.2.  The crash occurred on a system running
on i.MX6SX.

Link: https://lkml.kernel.org/r/20221220102318.3418501-1-rickaran@axis.com
Fixes: 977ef30a7d88 ("gcov: support GCC 12.1 and newer compilers")
Signed-off-by: Rickard x Andersson <rickaran@axis.com>
Reviewed-by: Peter Oberparleiter <oberpar@linux.ibm.com>
Tested-by: Peter Oberparleiter <oberpar@linux.ibm.com>
Reviewed-by: Martin Liska <mliska@suse.cz>
Cc: <stable@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 kernel/gcov/gcc_4_7.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/kernel/gcov/gcc_4_7.c b/kernel/gcov/gcc_4_7.c
index 7971e989e425b..74a4ef1da9ad7 100644
--- a/kernel/gcov/gcc_4_7.c
+++ b/kernel/gcov/gcc_4_7.c
@@ -82,6 +82,7 @@ struct gcov_fn_info {
  * @version: gcov version magic indicating the gcc version used for compilation
  * @next: list head for a singly-linked list
  * @stamp: uniquifying time stamp
+ * @checksum: unique object checksum
  * @filename: name of the associated gcov data file
  * @merge: merge functions (null for unused counter type)
  * @n_functions: number of instrumented functions
@@ -94,6 +95,10 @@ struct gcov_info {
 	unsigned int version;
 	struct gcov_info *next;
 	unsigned int stamp;
+ /* Since GCC 12.1 a checksum field is added. */
+#if (__GNUC__ >= 12)
+	unsigned int checksum;
+#endif
 	const char *filename;
 	void (*merge[GCOV_COUNTERS])(gcov_type *, unsigned int);
 	unsigned int n_functions;
-- 
GitLab


From 70a00e2f1dbae11dc3444444c6bd7555763d8421 Mon Sep 17 00:00:00 2001
From: Martin KaFai Lau <martin.lau@kernel.org>
Date: Wed, 21 Dec 2022 10:56:53 -0800
Subject: [PATCH 613/875] selftests/bpf: Test bpf_skb_adjust_room on
 CHECKSUM_PARTIAL

When the bpf_skb_adjust_room() shrinks the skb such that its csum_start
is invalid, the skb->ip_summed should be reset from CHECKSUM_PARTIAL to
CHECKSUM_NONE.

The commit 54c3f1a81421 ("bpf: pull before calling skb_postpull_rcsum()")
fixed it.

This patch adds a test to ensure the skb->ip_summed changed from
CHECKSUM_PARTIAL to CHECKSUM_NONE after bpf_skb_adjust_room().

Signed-off-by: Martin KaFai Lau <martin.lau@kernel.org>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Acked-by: Stanislav Fomichev <sdf@google.com>
Link: https://lore.kernel.org/bpf/20221221185653.1589961-1-martin.lau@linux.dev
---
 tools/testing/selftests/bpf/DENYLIST.s390x    |  1 +
 .../selftests/bpf/prog_tests/decap_sanity.c   | 85 +++++++++++++++++++
 .../selftests/bpf/progs/bpf_tracing_net.h     |  6 ++
 .../selftests/bpf/progs/decap_sanity.c        | 68 +++++++++++++++
 4 files changed, 160 insertions(+)
 create mode 100644 tools/testing/selftests/bpf/prog_tests/decap_sanity.c
 create mode 100644 tools/testing/selftests/bpf/progs/decap_sanity.c

diff --git a/tools/testing/selftests/bpf/DENYLIST.s390x b/tools/testing/selftests/bpf/DENYLIST.s390x
index 585fcf73c7314..3fc3e54b19aad 100644
--- a/tools/testing/selftests/bpf/DENYLIST.s390x
+++ b/tools/testing/selftests/bpf/DENYLIST.s390x
@@ -14,6 +14,7 @@ cgrp_kfunc                               # JIT does not support calling kernel f
 cgrp_local_storage                       # prog_attach unexpected error: -524                                          (trampoline)
 core_read_macros                         # unknown func bpf_probe_read#4                                               (overlapping)
 d_path                                   # failed to auto-attach program 'prog_stat': -524                             (trampoline)
+decap_sanity                             # JIT does not support calling kernel function                                (kfunc)
 deny_namespace                           # failed to attach: ERROR: strerror_r(-524)=22                                (trampoline)
 dummy_st_ops                             # test_run unexpected error: -524 (errno 524)                                 (trampoline)
 fentry_fexit                             # fentry attach failed: -524                                                  (trampoline)
diff --git a/tools/testing/selftests/bpf/prog_tests/decap_sanity.c b/tools/testing/selftests/bpf/prog_tests/decap_sanity.c
new file mode 100644
index 0000000000000..0b2f73b88c53d
--- /dev/null
+++ b/tools/testing/selftests/bpf/prog_tests/decap_sanity.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (c) 2022 Meta Platforms, Inc. and affiliates. */
+
+#include <sys/types.h>
+#include <sys/socket.h>
+#include <net/if.h>
+#include <linux/in6.h>
+
+#include "test_progs.h"
+#include "network_helpers.h"
+#include "decap_sanity.skel.h"
+
+#define SYS(fmt, ...)						\
+	({							\
+		char cmd[1024];					\
+		snprintf(cmd, sizeof(cmd), fmt, ##__VA_ARGS__);	\
+		if (!ASSERT_OK(system(cmd), cmd))		\
+			goto fail;				\
+	})
+
+#define NS_TEST "decap_sanity_ns"
+#define IPV6_IFACE_ADDR "face::1"
+#define UDP_TEST_PORT 7777
+
+void test_decap_sanity(void)
+{
+	LIBBPF_OPTS(bpf_tc_hook, qdisc_hook, .attach_point = BPF_TC_EGRESS);
+	LIBBPF_OPTS(bpf_tc_opts, tc_attach);
+	struct nstoken *nstoken = NULL;
+	struct decap_sanity *skel;
+	struct sockaddr_in6 addr;
+	socklen_t addrlen;
+	char buf[128] = {};
+	int sockfd, err;
+
+	skel = decap_sanity__open_and_load();
+	if (!ASSERT_OK_PTR(skel, "skel open_and_load"))
+		return;
+
+	SYS("ip netns add %s", NS_TEST);
+	SYS("ip -net %s -6 addr add %s/128 dev lo nodad", NS_TEST, IPV6_IFACE_ADDR);
+	SYS("ip -net %s link set dev lo up", NS_TEST);
+
+	nstoken = open_netns(NS_TEST);
+	if (!ASSERT_OK_PTR(nstoken, "open_netns"))
+		goto fail;
+
+	qdisc_hook.ifindex = if_nametoindex("lo");
+	if (!ASSERT_GT(qdisc_hook.ifindex, 0, "if_nametoindex lo"))
+		goto fail;
+
+	err = bpf_tc_hook_create(&qdisc_hook);
+	if (!ASSERT_OK(err, "create qdisc hook"))
+		goto fail;
+
+	tc_attach.prog_fd = bpf_program__fd(skel->progs.decap_sanity);
+	err = bpf_tc_attach(&qdisc_hook, &tc_attach);
+	if (!ASSERT_OK(err, "attach filter"))
+		goto fail;
+
+	addrlen = sizeof(addr);
+	err = make_sockaddr(AF_INET6, IPV6_IFACE_ADDR, UDP_TEST_PORT,
+			    (void *)&addr, &addrlen);
+	if (!ASSERT_OK(err, "make_sockaddr"))
+		goto fail;
+	sockfd = socket(AF_INET6, SOCK_DGRAM, 0);
+	if (!ASSERT_NEQ(sockfd, -1, "socket"))
+		goto fail;
+	err = sendto(sockfd, buf, sizeof(buf), 0, (void *)&addr, addrlen);
+	close(sockfd);
+	if (!ASSERT_EQ(err, sizeof(buf), "send"))
+		goto fail;
+
+	ASSERT_TRUE(skel->bss->init_csum_partial, "init_csum_partial");
+	ASSERT_TRUE(skel->bss->final_csum_none, "final_csum_none");
+	ASSERT_FALSE(skel->bss->broken_csum_start, "broken_csum_start");
+
+fail:
+	if (nstoken) {
+		bpf_tc_hook_destroy(&qdisc_hook);
+		close_netns(nstoken);
+	}
+	system("ip netns del " NS_TEST " >& /dev/null");
+	decap_sanity__destroy(skel);
+}
diff --git a/tools/testing/selftests/bpf/progs/bpf_tracing_net.h b/tools/testing/selftests/bpf/progs/bpf_tracing_net.h
index b394817126cf9..cfed4df490f35 100644
--- a/tools/testing/selftests/bpf/progs/bpf_tracing_net.h
+++ b/tools/testing/selftests/bpf/progs/bpf_tracing_net.h
@@ -50,6 +50,12 @@
 #define ICSK_TIME_LOSS_PROBE	5
 #define ICSK_TIME_REO_TIMEOUT	6
 
+#define ETH_HLEN		14
+#define ETH_P_IPV6		0x86DD
+
+#define CHECKSUM_NONE		0
+#define CHECKSUM_PARTIAL	3
+
 #define IFNAMSIZ		16
 
 #define RTF_GATEWAY		0x0002
diff --git a/tools/testing/selftests/bpf/progs/decap_sanity.c b/tools/testing/selftests/bpf/progs/decap_sanity.c
new file mode 100644
index 0000000000000..bd3c657c58a79
--- /dev/null
+++ b/tools/testing/selftests/bpf/progs/decap_sanity.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (c) 2022 Meta Platforms, Inc. and affiliates. */
+
+#include "vmlinux.h"
+#include "bpf_tracing_net.h"
+#include <bpf/bpf_helpers.h>
+#include <bpf/bpf_endian.h>
+
+#define UDP_TEST_PORT 7777
+
+void *bpf_cast_to_kern_ctx(void *) __ksym;
+bool init_csum_partial = false;
+bool final_csum_none = false;
+bool broken_csum_start = false;
+
+static unsigned int skb_headlen(const struct sk_buff *skb)
+{
+	return skb->len - skb->data_len;
+}
+
+static unsigned int skb_headroom(const struct sk_buff *skb)
+{
+	return skb->data - skb->head;
+}
+
+static int skb_checksum_start_offset(const struct sk_buff *skb)
+{
+	return skb->csum_start - skb_headroom(skb);
+}
+
+SEC("tc")
+int decap_sanity(struct __sk_buff *skb)
+{
+	struct sk_buff *kskb;
+	struct ipv6hdr ip6h;
+	struct udphdr udph;
+	int err;
+
+	if (skb->protocol != __bpf_constant_htons(ETH_P_IPV6))
+		return TC_ACT_SHOT;
+
+	if (bpf_skb_load_bytes(skb, ETH_HLEN, &ip6h, sizeof(ip6h)))
+		return TC_ACT_SHOT;
+
+	if (ip6h.nexthdr != IPPROTO_UDP)
+		return TC_ACT_SHOT;
+
+	if (bpf_skb_load_bytes(skb, ETH_HLEN + sizeof(ip6h), &udph, sizeof(udph)))
+		return TC_ACT_SHOT;
+
+	if (udph.dest != __bpf_constant_htons(UDP_TEST_PORT))
+		return TC_ACT_SHOT;
+
+	kskb = bpf_cast_to_kern_ctx(skb);
+	init_csum_partial = (kskb->ip_summed == CHECKSUM_PARTIAL);
+	err = bpf_skb_adjust_room(skb, -(s32)(ETH_HLEN + sizeof(ip6h) + sizeof(udph)),
+				  1, BPF_F_ADJ_ROOM_FIXED_GSO);
+	if (err)
+		return TC_ACT_SHOT;
+	final_csum_none = (kskb->ip_summed == CHECKSUM_NONE);
+	if (kskb->ip_summed == CHECKSUM_PARTIAL &&
+	    (unsigned int)skb_checksum_start_offset(kskb) >= skb_headlen(kskb))
+		broken_csum_start = true;
+
+	return TC_ACT_SHOT;
+}
+
+char __license[] SEC("license") = "GPL";
-- 
GitLab


From 53fc61be273a1e76dd5e356f91805dce00ff2d2c Mon Sep 17 00:00:00 2001
From: Maciej Fijalkowski <maciej.fijalkowski@intel.com>
Date: Tue, 20 Dec 2022 09:54:48 -0800
Subject: [PATCH 614/875] ice: xsk: do not use xdp_return_frame() on
 tx_buf->raw_buf

Previously ice XDP xmit routine was changed in a way that it avoids
xdp_buff->xdp_frame conversion as it is simply not needed for handling
XDP_TX action and what is more it saves us CPU cycles. This routine is
re-used on ZC driver to handle XDP_TX action.

Although for XDP_TX on Rx ZC xdp_buff that comes from xsk_buff_pool is
converted to xdp_frame, xdp_frame itself is not stored inside
ice_tx_buf, we only store raw data pointer. Casting this pointer to
xdp_frame and calling against it xdp_return_frame in
ice_clean_xdp_tx_buf() results in undefined behavior.

To fix this, simply call page_frag_free() on tx_buf->raw_buf.
Later intention is to remove the buff->frame conversion in order to
simplify the codebase and improve XDP_TX performance on ZC.

Fixes: 126cdfe1007a ("ice: xsk: Improve AF_XDP ZC Tx and use batching API")
Reported-and-tested-by: Robin Cowley <robin.cowley@thehutgroup.com>
Signed-off-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com>
Tested-by: Chandan Kumar Rout <chandanx.rout@intel.com> (A Contingent Worker at Intel)
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Reviewed-by: Piotr Raczynski <piotr.raczynski@.intel.com>
Link: https://lore.kernel.org/r/20221220175448.693999-1-anthony.l.nguyen@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/ethernet/intel/ice/ice_xsk.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/intel/ice/ice_xsk.c b/drivers/net/ethernet/intel/ice/ice_xsk.c
index 907055b77af0e..7105de6fb3444 100644
--- a/drivers/net/ethernet/intel/ice/ice_xsk.c
+++ b/drivers/net/ethernet/intel/ice/ice_xsk.c
@@ -783,7 +783,7 @@ construct_skb:
 static void
 ice_clean_xdp_tx_buf(struct ice_tx_ring *xdp_ring, struct ice_tx_buf *tx_buf)
 {
-	xdp_return_frame((struct xdp_frame *)tx_buf->raw_buf);
+	page_frag_free(tx_buf->raw_buf);
 	xdp_ring->xdp_tx_active--;
 	dma_unmap_single(xdp_ring->dev, dma_unmap_addr(tx_buf, dma),
 			 dma_unmap_len(tx_buf, len), DMA_TO_DEVICE);
-- 
GitLab


From f2575c8f404911da83f25b688e12afcf4273e640 Mon Sep 17 00:00:00 2001
From: Antoine Tenart <atenart@kernel.org>
Date: Tue, 20 Dec 2022 18:18:25 +0100
Subject: [PATCH 615/875] net: vrf: determine the dst using the original
 ifindex for multicast

Multicast packets received on an interface bound to a VRF are marked as
belonging to the VRF and the skb device is updated to point to the VRF
device itself. This was fine even when a route was associated to a
device as when performing a fib table lookup 'oif' in fib6_table_lookup
(coming from 'skb->dev->ifindex' in ip6_route_input) was set to 0 when
FLOWI_FLAG_SKIP_NH_OIF was set.

With commit 40867d74c374 ("net: Add l3mdev index to flow struct and
avoid oif reset for port devices") this is not longer true and multicast
traffic is not received on the original interface.

Instead of adding back a similar check in fib6_table_lookup determine
the dst using the original ifindex for multicast VRF traffic. To make
things consistent across the function do the above for all strict
packets, which was the logic before commit 6f12fa775530 ("vrf: mark skb
for multicast or link-local as enslaved to VRF"). Note that reverting to
this behavior should be fine as the change was about marking packets
belonging to the VRF, not about their dst.

Fixes: 40867d74c374 ("net: Add l3mdev index to flow struct and avoid oif reset for port devices")
Reported-by: Jianlin Shi <jishi@redhat.com>
Signed-off-by: Antoine Tenart <atenart@kernel.org>
Reviewed-by: David Ahern <dsahern@kernel.org>
Link: https://lore.kernel.org/r/20221220171825.1172237-1-atenart@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/vrf.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/vrf.c b/drivers/net/vrf.c
index 6b5a4d036d153..bdb3a76a352e4 100644
--- a/drivers/net/vrf.c
+++ b/drivers/net/vrf.c
@@ -1385,8 +1385,8 @@ static struct sk_buff *vrf_ip6_rcv(struct net_device *vrf_dev,
 
 	/* loopback, multicast & non-ND link-local traffic; do not push through
 	 * packet taps again. Reset pkt_type for upper layers to process skb.
-	 * For strict packets with a source LLA, determine the dst using the
-	 * original ifindex.
+	 * For non-loopback strict packets, determine the dst using the original
+	 * ifindex.
 	 */
 	if (skb->pkt_type == PACKET_LOOPBACK || (need_strict && !is_ndisc)) {
 		skb->dev = vrf_dev;
@@ -1395,7 +1395,7 @@ static struct sk_buff *vrf_ip6_rcv(struct net_device *vrf_dev,
 
 		if (skb->pkt_type == PACKET_LOOPBACK)
 			skb->pkt_type = PACKET_HOST;
-		else if (ipv6_addr_type(&ipv6_hdr(skb)->saddr) & IPV6_ADDR_LINKLOCAL)
+		else
 			vrf_ip6_input_dst(skb, vrf_dev, orig_iif);
 
 		goto out;
-- 
GitLab


From 95637d91fefdb94d6e7389222ba9ddab0e9f5abe Mon Sep 17 00:00:00 2001
From: Aaron Conole <aconole@redhat.com>
Date: Tue, 20 Dec 2022 16:27:17 -0500
Subject: [PATCH 616/875] net: openvswitch: release vport resources on failure

A recent commit introducing upcall packet accounting failed to properly
release the vport object when the per-cpu stats struct couldn't be
allocated.  This can cause dangling pointers to dp objects long after
they've been released.

Cc: wangchuanlei <wangchuanlei@inspur.com>
Fixes: 1933ea365aa7 ("net: openvswitch: Add support to count upcall packets")
Reported-by: syzbot+8f4e2dcfcb3209ac35f9@syzkaller.appspotmail.com
Signed-off-by: Aaron Conole <aconole@redhat.com>
Acked-by: Eelco Chaudron <echaudro@redhat.com>
Reviewed-by: Michal Swiatkowski <michal.swiatkowski@linux.intel.com>
Link: https://lore.kernel.org/r/20221220212717.526780-1-aconole@redhat.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 net/openvswitch/datapath.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/net/openvswitch/datapath.c b/net/openvswitch/datapath.c
index 9ca721c9fa718..a71795355aecf 100644
--- a/net/openvswitch/datapath.c
+++ b/net/openvswitch/datapath.c
@@ -1861,7 +1861,7 @@ static int ovs_dp_cmd_new(struct sk_buff *skb, struct genl_info *info)
 	vport->upcall_stats = netdev_alloc_pcpu_stats(struct vport_upcall_stats_percpu);
 	if (!vport->upcall_stats) {
 		err = -ENOMEM;
-		goto err_destroy_portids;
+		goto err_destroy_vport;
 	}
 
 	err = ovs_dp_cmd_fill_info(dp, reply, info->snd_portid,
@@ -1876,6 +1876,8 @@ static int ovs_dp_cmd_new(struct sk_buff *skb, struct genl_info *info)
 	ovs_notify(&dp_datapath_genl_family, reply, info);
 	return 0;
 
+err_destroy_vport:
+	ovs_dp_detach_port(vport);
 err_destroy_portids:
 	kfree(rcu_dereference_raw(dp->upcall_portids));
 err_unlock_and_destroy_meters:
@@ -2323,7 +2325,7 @@ restart:
 	vport->upcall_stats = netdev_alloc_pcpu_stats(struct vport_upcall_stats_percpu);
 	if (!vport->upcall_stats) {
 		err = -ENOMEM;
-		goto exit_unlock_free;
+		goto exit_unlock_free_vport;
 	}
 
 	err = ovs_vport_cmd_fill_info(vport, reply, genl_info_net(info),
@@ -2343,6 +2345,8 @@ restart:
 	ovs_notify(&dp_vport_genl_family, reply, info);
 	return 0;
 
+exit_unlock_free_vport:
+	ovs_dp_detach_port(vport);
 exit_unlock_free:
 	ovs_unlock();
 	kfree_skb(reply);
-- 
GitLab


From 3d8f2c4269d08f8793e946279dbdf5e972cc4911 Mon Sep 17 00:00:00 2001
From: Ronak Doshi <doshir@vmware.com>
Date: Tue, 20 Dec 2022 12:25:55 -0800
Subject: [PATCH 617/875] vmxnet3: correctly report csum_level for encapsulated
 packet

Commit dacce2be3312 ("vmxnet3: add geneve and vxlan tunnel offload
support") added support for encapsulation offload. However, the
pathc did not report correctly the csum_level for encapsulated packet.

This patch fixes this issue by reporting correct csum level for the
encapsulated packet.

Fixes: dacce2be3312 ("vmxnet3: add geneve and vxlan tunnel offload support")
Signed-off-by: Ronak Doshi <doshir@vmware.com>
Acked-by: Peng Li <lpeng@vmware.com>
Link: https://lore.kernel.org/r/20221220202556.24421-1-doshir@vmware.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/vmxnet3/vmxnet3_drv.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/net/vmxnet3/vmxnet3_drv.c b/drivers/net/vmxnet3/vmxnet3_drv.c
index 6f1e560fb15c4..56267c327f0b7 100644
--- a/drivers/net/vmxnet3/vmxnet3_drv.c
+++ b/drivers/net/vmxnet3/vmxnet3_drv.c
@@ -1288,6 +1288,10 @@ vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
 		    (le32_to_cpu(gdesc->dword[3]) &
 		     VMXNET3_RCD_CSUM_OK) == VMXNET3_RCD_CSUM_OK) {
 			skb->ip_summed = CHECKSUM_UNNECESSARY;
+			if ((le32_to_cpu(gdesc->dword[0]) &
+				     (1UL << VMXNET3_RCD_HDR_INNER_SHIFT))) {
+				skb->csum_level = 1;
+			}
 			WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) &&
 				     !(le32_to_cpu(gdesc->dword[0]) &
 				     (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
@@ -1297,6 +1301,10 @@ vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
 		} else if (gdesc->rcd.v6 && (le32_to_cpu(gdesc->dword[3]) &
 					     (1 << VMXNET3_RCD_TUC_SHIFT))) {
 			skb->ip_summed = CHECKSUM_UNNECESSARY;
+			if ((le32_to_cpu(gdesc->dword[0]) &
+				     (1UL << VMXNET3_RCD_HDR_INNER_SHIFT))) {
+				skb->csum_level = 1;
+			}
 			WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) &&
 				     !(le32_to_cpu(gdesc->dword[0]) &
 				     (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
-- 
GitLab


From e20aa071cd955aabc15be0ec1e914283592ddef4 Mon Sep 17 00:00:00 2001
From: Yinjun Zhang <yinjun.zhang@corigine.com>
Date: Tue, 20 Dec 2022 16:21:00 +0100
Subject: [PATCH 618/875] nfp: fix schedule in atomic context when sync mc
 address

The callback `.ndo_set_rx_mode` is called in atomic context, sleep
is not allowed in the implementation. Now use workqueue mechanism
to avoid this issue.

Fixes: de6248644966 ("nfp: add support for multicast filter")
Signed-off-by: Yinjun Zhang <yinjun.zhang@corigine.com>
Reviewed-by: Louis Peens <louis.peens@corigine.com>
Signed-off-by: Simon Horman <simon.horman@corigine.com>
Link: https://lore.kernel.org/r/20221220152100.1042774-1-simon.horman@corigine.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/ethernet/netronome/nfp/nfp_net.h  |  7 +++
 .../ethernet/netronome/nfp/nfp_net_common.c   | 61 +++++++++++++++++--
 2 files changed, 64 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/netronome/nfp/nfp_net.h b/drivers/net/ethernet/netronome/nfp/nfp_net.h
index da33f09facb91..432d79d691c29 100644
--- a/drivers/net/ethernet/netronome/nfp/nfp_net.h
+++ b/drivers/net/ethernet/netronome/nfp/nfp_net.h
@@ -617,6 +617,9 @@ struct nfp_net_dp {
  * @vnic_no_name:	For non-port PF vNIC make ndo_get_phys_port_name return
  *			-EOPNOTSUPP to keep backwards compatibility (set by app)
  * @port:		Pointer to nfp_port structure if vNIC is a port
+ * @mc_lock:		Protect mc_addrs list
+ * @mc_addrs:		List of mc addrs to add/del to HW
+ * @mc_work:		Work to update mc addrs
  * @app_priv:		APP private data for this vNIC
  */
 struct nfp_net {
@@ -718,6 +721,10 @@ struct nfp_net {
 
 	struct nfp_port *port;
 
+	spinlock_t mc_lock;
+	struct list_head mc_addrs;
+	struct work_struct mc_work;
+
 	void *app_priv;
 };
 
diff --git a/drivers/net/ethernet/netronome/nfp/nfp_net_common.c b/drivers/net/ethernet/netronome/nfp/nfp_net_common.c
index 09053373288fe..18fc9971f1c8f 100644
--- a/drivers/net/ethernet/netronome/nfp/nfp_net_common.c
+++ b/drivers/net/ethernet/netronome/nfp/nfp_net_common.c
@@ -1334,9 +1334,14 @@ err_unlock:
 	return err;
 }
 
-static int nfp_net_mc_cfg(struct net_device *netdev, const unsigned char *addr, const u32 cmd)
+struct nfp_mc_addr_entry {
+	u8 addr[ETH_ALEN];
+	u32 cmd;
+	struct list_head list;
+};
+
+static int nfp_net_mc_cfg(struct nfp_net *nn, const unsigned char *addr, const u32 cmd)
 {
-	struct nfp_net *nn = netdev_priv(netdev);
 	int ret;
 
 	ret = nfp_net_mbox_lock(nn, NFP_NET_CFG_MULTICAST_SZ);
@@ -1351,6 +1356,25 @@ static int nfp_net_mc_cfg(struct net_device *netdev, const unsigned char *addr,
 	return nfp_net_mbox_reconfig_and_unlock(nn, cmd);
 }
 
+static int nfp_net_mc_prep(struct nfp_net *nn, const unsigned char *addr, const u32 cmd)
+{
+	struct nfp_mc_addr_entry *entry;
+
+	entry = kmalloc(sizeof(*entry), GFP_ATOMIC);
+	if (!entry)
+		return -ENOMEM;
+
+	ether_addr_copy(entry->addr, addr);
+	entry->cmd = cmd;
+	spin_lock_bh(&nn->mc_lock);
+	list_add_tail(&entry->list, &nn->mc_addrs);
+	spin_unlock_bh(&nn->mc_lock);
+
+	schedule_work(&nn->mc_work);
+
+	return 0;
+}
+
 static int nfp_net_mc_sync(struct net_device *netdev, const unsigned char *addr)
 {
 	struct nfp_net *nn = netdev_priv(netdev);
@@ -1361,12 +1385,35 @@ static int nfp_net_mc_sync(struct net_device *netdev, const unsigned char *addr)
 		return -EINVAL;
 	}
 
-	return nfp_net_mc_cfg(netdev, addr, NFP_NET_CFG_MBOX_CMD_MULTICAST_ADD);
+	return nfp_net_mc_prep(nn, addr, NFP_NET_CFG_MBOX_CMD_MULTICAST_ADD);
 }
 
 static int nfp_net_mc_unsync(struct net_device *netdev, const unsigned char *addr)
 {
-	return nfp_net_mc_cfg(netdev, addr, NFP_NET_CFG_MBOX_CMD_MULTICAST_DEL);
+	struct nfp_net *nn = netdev_priv(netdev);
+
+	return nfp_net_mc_prep(nn, addr, NFP_NET_CFG_MBOX_CMD_MULTICAST_DEL);
+}
+
+static void nfp_net_mc_addr_config(struct work_struct *work)
+{
+	struct nfp_net *nn = container_of(work, struct nfp_net, mc_work);
+	struct nfp_mc_addr_entry *entry, *tmp;
+	struct list_head tmp_list;
+
+	INIT_LIST_HEAD(&tmp_list);
+
+	spin_lock_bh(&nn->mc_lock);
+	list_splice_init(&nn->mc_addrs, &tmp_list);
+	spin_unlock_bh(&nn->mc_lock);
+
+	list_for_each_entry_safe(entry, tmp, &tmp_list, list) {
+		if (nfp_net_mc_cfg(nn, entry->addr, entry->cmd))
+			nn_err(nn, "Config mc address to HW failed.\n");
+
+		list_del(&entry->list);
+		kfree(entry);
+	}
 }
 
 static void nfp_net_set_rx_mode(struct net_device *netdev)
@@ -2633,6 +2680,11 @@ int nfp_net_init(struct nfp_net *nn)
 
 	if (!nn->dp.netdev)
 		return 0;
+
+	spin_lock_init(&nn->mc_lock);
+	INIT_LIST_HEAD(&nn->mc_addrs);
+	INIT_WORK(&nn->mc_work, nfp_net_mc_addr_config);
+
 	return register_netdev(nn->dp.netdev);
 
 err_clean_mbox:
@@ -2652,5 +2704,6 @@ void nfp_net_clean(struct nfp_net *nn)
 	unregister_netdev(nn->dp.netdev);
 	nfp_net_ipsec_clean(nn);
 	nfp_ccm_mbox_clean(nn);
+	flush_work(&nn->mc_work);
 	nfp_net_reconfig_wait_posted(nn);
 }
-- 
GitLab


From 7d803344fdc3e38079fabcf38b1e4cb6f8faa655 Mon Sep 17 00:00:00 2001
From: Paolo Abeni <pabeni@redhat.com>
Date: Tue, 20 Dec 2022 11:52:14 -0800
Subject: [PATCH 619/875] mptcp: fix deadlock in fastopen error path

MatM reported a deadlock at fastopening time:

INFO: task syz-executor.0:11454 blocked for more than 143 seconds.
      Tainted: G S                 6.1.0-rc5-03226-gdb0157db5153 #1
"echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
task:syz-executor.0  state:D stack:25104 pid:11454 ppid:424    flags:0x00004006
Call Trace:
 <TASK>
 context_switch kernel/sched/core.c:5191 [inline]
 __schedule+0x5c2/0x1550 kernel/sched/core.c:6503
 schedule+0xe8/0x1c0 kernel/sched/core.c:6579
 __lock_sock+0x142/0x260 net/core/sock.c:2896
 lock_sock_nested+0xdb/0x100 net/core/sock.c:3466
 __mptcp_close_ssk+0x1a3/0x790 net/mptcp/protocol.c:2328
 mptcp_destroy_common+0x16a/0x650 net/mptcp/protocol.c:3171
 mptcp_disconnect+0xb8/0x450 net/mptcp/protocol.c:3019
 __inet_stream_connect+0x897/0xa40 net/ipv4/af_inet.c:720
 tcp_sendmsg_fastopen+0x3dd/0x740 net/ipv4/tcp.c:1200
 mptcp_sendmsg_fastopen net/mptcp/protocol.c:1682 [inline]
 mptcp_sendmsg+0x128a/0x1a50 net/mptcp/protocol.c:1721
 inet6_sendmsg+0x11f/0x150 net/ipv6/af_inet6.c:663
 sock_sendmsg_nosec net/socket.c:714 [inline]
 sock_sendmsg+0xf7/0x190 net/socket.c:734
 ____sys_sendmsg+0x336/0x970 net/socket.c:2476
 ___sys_sendmsg+0x122/0x1c0 net/socket.c:2530
 __sys_sendmmsg+0x18d/0x460 net/socket.c:2616
 __do_sys_sendmmsg net/socket.c:2645 [inline]
 __se_sys_sendmmsg net/socket.c:2642 [inline]
 __x64_sys_sendmmsg+0x9d/0x110 net/socket.c:2642
 do_syscall_x64 arch/x86/entry/common.c:50 [inline]
 do_syscall_64+0x38/0x90 arch/x86/entry/common.c:80
 entry_SYSCALL_64_after_hwframe+0x63/0xcd
RIP: 0033:0x7f5920a75e7d
RSP: 002b:00007f59201e8028 EFLAGS: 00000246 ORIG_RAX: 0000000000000133
RAX: ffffffffffffffda RBX: 00007f5920bb4f80 RCX: 00007f5920a75e7d
RDX: 0000000000000001 RSI: 0000000020002940 RDI: 0000000000000005
RBP: 00007f5920ae7593 R08: 0000000000000000 R09: 0000000000000000
R10: 0000000020004050 R11: 0000000000000246 R12: 0000000000000000
R13: 000000000000000b R14: 00007f5920bb4f80 R15: 00007f59201c8000
 </TASK>

In the error path, tcp_sendmsg_fastopen() ends-up calling
mptcp_disconnect(), and the latter tries to close each
subflow, acquiring the socket lock on each of them.

At fastopen time, we have a single subflow, and such subflow
socket lock is already held by the called, causing the deadlock.

We already track the 'fastopen in progress' status inside the msk
socket. Use it to address the issue, making mptcp_disconnect() a
no op when invoked from the fastopen (error) path and doing the
relevant cleanup after releasing the subflow socket lock.

While at the above, rename the fastopen status bit to something
more meaningful.

Closes: https://github.com/multipath-tcp/mptcp_net-next/issues/321
Fixes: fa9e57468aa1 ("mptcp: fix abba deadlock on fastopen")
Reported-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
Reviewed-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 net/mptcp/protocol.c | 18 +++++++++++++++---
 net/mptcp/protocol.h |  2 +-
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/net/mptcp/protocol.c b/net/mptcp/protocol.c
index f6f93957275b8..907b435e29842 100644
--- a/net/mptcp/protocol.c
+++ b/net/mptcp/protocol.c
@@ -1662,6 +1662,8 @@ static void mptcp_set_nospace(struct sock *sk)
 	set_bit(MPTCP_NOSPACE, &mptcp_sk(sk)->flags);
 }
 
+static int mptcp_disconnect(struct sock *sk, int flags);
+
 static int mptcp_sendmsg_fastopen(struct sock *sk, struct sock *ssk, struct msghdr *msg,
 				  size_t len, int *copied_syn)
 {
@@ -1672,9 +1674,9 @@ static int mptcp_sendmsg_fastopen(struct sock *sk, struct sock *ssk, struct msgh
 	lock_sock(ssk);
 	msg->msg_flags |= MSG_DONTWAIT;
 	msk->connect_flags = O_NONBLOCK;
-	msk->is_sendmsg = 1;
+	msk->fastopening = 1;
 	ret = tcp_sendmsg_fastopen(ssk, msg, copied_syn, len, NULL);
-	msk->is_sendmsg = 0;
+	msk->fastopening = 0;
 	msg->msg_flags = saved_flags;
 	release_sock(ssk);
 
@@ -1688,6 +1690,8 @@ static int mptcp_sendmsg_fastopen(struct sock *sk, struct sock *ssk, struct msgh
 		 */
 		if (ret && ret != -EINPROGRESS && ret != -ERESTARTSYS && ret != -EINTR)
 			*copied_syn = 0;
+	} else if (ret && ret != -EINPROGRESS) {
+		mptcp_disconnect(sk, 0);
 	}
 
 	return ret;
@@ -2989,6 +2993,14 @@ static int mptcp_disconnect(struct sock *sk, int flags)
 {
 	struct mptcp_sock *msk = mptcp_sk(sk);
 
+	/* We are on the fastopen error path. We can't call straight into the
+	 * subflows cleanup code due to lock nesting (we are already under
+	 * msk->firstsocket lock). Do nothing and leave the cleanup to the
+	 * caller.
+	 */
+	if (msk->fastopening)
+		return 0;
+
 	inet_sk_state_store(sk, TCP_CLOSE);
 
 	mptcp_stop_timer(sk);
@@ -3532,7 +3544,7 @@ static int mptcp_connect(struct sock *sk, struct sockaddr *uaddr, int addr_len)
 	/* if reaching here via the fastopen/sendmsg path, the caller already
 	 * acquired the subflow socket lock, too.
 	 */
-	if (msk->is_sendmsg)
+	if (msk->fastopening)
 		err = __inet_stream_connect(ssock, uaddr, addr_len, msk->connect_flags, 1);
 	else
 		err = inet_stream_connect(ssock, uaddr, addr_len, msk->connect_flags);
diff --git a/net/mptcp/protocol.h b/net/mptcp/protocol.h
index 955fb3d88eb3a..f47d3e4018b51 100644
--- a/net/mptcp/protocol.h
+++ b/net/mptcp/protocol.h
@@ -295,7 +295,7 @@ struct mptcp_sock {
 	u8		recvmsg_inq:1,
 			cork:1,
 			nodelay:1,
-			is_sendmsg:1;
+			fastopening:1;
 	int		connect_flags;
 	struct work_struct work;
 	struct sk_buff  *ooo_last_skb;
-- 
GitLab


From fec3adfd754ccc99a7230e8ab9f105b65fb07bcc Mon Sep 17 00:00:00 2001
From: Paolo Abeni <pabeni@redhat.com>
Date: Tue, 20 Dec 2022 11:52:15 -0800
Subject: [PATCH 620/875] mptcp: fix lockdep false positive

MattB reported a lockdep splat in the mptcp listener code cleanup:

 WARNING: possible circular locking dependency detected
 packetdrill/14278 is trying to acquire lock:
 ffff888017d868f0 ((work_completion)(&msk->work)){+.+.}-{0:0}, at: __flush_work (kernel/workqueue.c:3069)

 but task is already holding lock:
 ffff888017d84130 (sk_lock-AF_INET){+.+.}-{0:0}, at: mptcp_close (net/mptcp/protocol.c:2973)

 which lock already depends on the new lock.

 the existing dependency chain (in reverse order) is:

 -> #1 (sk_lock-AF_INET){+.+.}-{0:0}:
        __lock_acquire (kernel/locking/lockdep.c:5055)
        lock_acquire (kernel/locking/lockdep.c:466)
        lock_sock_nested (net/core/sock.c:3463)
        mptcp_worker (net/mptcp/protocol.c:2614)
        process_one_work (kernel/workqueue.c:2294)
        worker_thread (include/linux/list.h:292)
        kthread (kernel/kthread.c:376)
        ret_from_fork (arch/x86/entry/entry_64.S:312)

 -> #0 ((work_completion)(&msk->work)){+.+.}-{0:0}:
        check_prev_add (kernel/locking/lockdep.c:3098)
        validate_chain (kernel/locking/lockdep.c:3217)
        __lock_acquire (kernel/locking/lockdep.c:5055)
        lock_acquire (kernel/locking/lockdep.c:466)
        __flush_work (kernel/workqueue.c:3070)
        __cancel_work_timer (kernel/workqueue.c:3160)
        mptcp_cancel_work (net/mptcp/protocol.c:2758)
        mptcp_subflow_queue_clean (net/mptcp/subflow.c:1817)
        __mptcp_close_ssk (net/mptcp/protocol.c:2363)
        mptcp_destroy_common (net/mptcp/protocol.c:3170)
        mptcp_destroy (include/net/sock.h:1495)
        __mptcp_destroy_sock (net/mptcp/protocol.c:2886)
        __mptcp_close (net/mptcp/protocol.c:2959)
        mptcp_close (net/mptcp/protocol.c:2974)
        inet_release (net/ipv4/af_inet.c:432)
        __sock_release (net/socket.c:651)
        sock_close (net/socket.c:1367)
        __fput (fs/file_table.c:320)
        task_work_run (kernel/task_work.c:181 (discriminator 1))
        exit_to_user_mode_prepare (include/linux/resume_user_mode.h:49)
        syscall_exit_to_user_mode (kernel/entry/common.c:130)
        do_syscall_64 (arch/x86/entry/common.c:87)
        entry_SYSCALL_64_after_hwframe (arch/x86/entry/entry_64.S:120)

 other info that might help us debug this:

  Possible unsafe locking scenario:

        CPU0                    CPU1
        ----                    ----
   lock(sk_lock-AF_INET);
                                lock((work_completion)(&msk->work));
                                lock(sk_lock-AF_INET);
   lock((work_completion)(&msk->work));

  *** DEADLOCK ***

The report is actually a false positive, since the only existing lock
nesting is the msk socket lock acquired by the mptcp work.
cancel_work_sync() is invoked without the relevant socket lock being
held, but under a different (the msk listener) socket lock.

We could silence the splat adding a per workqueue dynamic lockdep key,
but that looks overkill. Instead just tell lockdep the msk socket lock
is not held around cancel_work_sync().

Closes: https://github.com/multipath-tcp/mptcp_net-next/issues/322
Fixes: 30e51b923e43 ("mptcp: fix unreleased socket in accept queue")
Reported-by: Matthieu Baerts <matthieu.baerts@tessares.net>
Reviewed-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 net/mptcp/protocol.c |  2 +-
 net/mptcp/protocol.h |  2 +-
 net/mptcp/subflow.c  | 19 +++++++++++++++++--
 3 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/net/mptcp/protocol.c b/net/mptcp/protocol.c
index 907b435e29842..b7ad030dfe891 100644
--- a/net/mptcp/protocol.c
+++ b/net/mptcp/protocol.c
@@ -2357,7 +2357,7 @@ static void __mptcp_close_ssk(struct sock *sk, struct sock *ssk,
 		/* otherwise tcp will dispose of the ssk and subflow ctx */
 		if (ssk->sk_state == TCP_LISTEN) {
 			tcp_set_state(ssk, TCP_CLOSE);
-			mptcp_subflow_queue_clean(ssk);
+			mptcp_subflow_queue_clean(sk, ssk);
 			inet_csk_listen_stop(ssk);
 			mptcp_event_pm_listener(ssk, MPTCP_EVENT_LISTENER_CLOSED);
 		}
diff --git a/net/mptcp/protocol.h b/net/mptcp/protocol.h
index f47d3e4018b51..a0d1658ce59ee 100644
--- a/net/mptcp/protocol.h
+++ b/net/mptcp/protocol.h
@@ -628,7 +628,7 @@ void mptcp_close_ssk(struct sock *sk, struct sock *ssk,
 		     struct mptcp_subflow_context *subflow);
 void __mptcp_subflow_send_ack(struct sock *ssk);
 void mptcp_subflow_reset(struct sock *ssk);
-void mptcp_subflow_queue_clean(struct sock *ssk);
+void mptcp_subflow_queue_clean(struct sock *sk, struct sock *ssk);
 void mptcp_sock_graft(struct sock *sk, struct socket *parent);
 struct socket *__mptcp_nmpc_socket(const struct mptcp_sock *msk);
 bool __mptcp_close(struct sock *sk, long timeout);
diff --git a/net/mptcp/subflow.c b/net/mptcp/subflow.c
index d1d32a66ae3f7..bd387d4b5a38f 100644
--- a/net/mptcp/subflow.c
+++ b/net/mptcp/subflow.c
@@ -1791,7 +1791,7 @@ static void subflow_state_change(struct sock *sk)
 	}
 }
 
-void mptcp_subflow_queue_clean(struct sock *listener_ssk)
+void mptcp_subflow_queue_clean(struct sock *listener_sk, struct sock *listener_ssk)
 {
 	struct request_sock_queue *queue = &inet_csk(listener_ssk)->icsk_accept_queue;
 	struct mptcp_sock *msk, *next, *head = NULL;
@@ -1840,8 +1840,23 @@ void mptcp_subflow_queue_clean(struct sock *listener_ssk)
 
 		do_cancel_work = __mptcp_close(sk, 0);
 		release_sock(sk);
-		if (do_cancel_work)
+		if (do_cancel_work) {
+			/* lockdep will report a false positive ABBA deadlock
+			 * between cancel_work_sync and the listener socket.
+			 * The involved locks belong to different sockets WRT
+			 * the existing AB chain.
+			 * Using a per socket key is problematic as key
+			 * deregistration requires process context and must be
+			 * performed at socket disposal time, in atomic
+			 * context.
+			 * Just tell lockdep to consider the listener socket
+			 * released here.
+			 */
+			mutex_release(&listener_sk->sk_lock.dep_map, _RET_IP_);
 			mptcp_cancel_work(sk);
+			mutex_acquire(&listener_sk->sk_lock.dep_map,
+				      SINGLE_DEPTH_NESTING, 0, _RET_IP_);
+		}
 		sock_put(sk);
 	}
 
-- 
GitLab


From a95e163a4bfa7780f64e589bbedc6bdeb7cf3839 Mon Sep 17 00:00:00 2001
From: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
Date: Tue, 13 Dec 2022 14:13:55 +0800
Subject: [PATCH 621/875] ALSA: azt3328: Remove the unused function
 snd_azf3328_codec_outl()

The function snd_azf3328_codec_outl is defined in the azt3328.c file, but
not called elsewhere, so remove this unused function.

sound/pci/azt3328.c:367:1: warning: unused function 'snd_azf3328_codec_outl'.

Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=3432
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
Link: https://lore.kernel.org/r/20221213061355.62856-1-jiapeng.chong@linux.alibaba.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/pci/azt3328.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/sound/pci/azt3328.c b/sound/pci/azt3328.c
index 7f329dfc5404a..0c6754bf94554 100644
--- a/sound/pci/azt3328.c
+++ b/sound/pci/azt3328.c
@@ -363,15 +363,6 @@ snd_azf3328_codec_inw(const struct snd_azf3328_codec_data *codec, unsigned reg)
 	return inw(codec->io_base + reg);
 }
 
-static inline void
-snd_azf3328_codec_outl(const struct snd_azf3328_codec_data *codec,
-		       unsigned reg,
-		       u32 value
-)
-{
-	outl(value, codec->io_base + reg);
-}
-
 static inline void
 snd_azf3328_codec_outl_multi(const struct snd_azf3328_codec_data *codec,
 			     unsigned reg, const void *buffer, int count
-- 
GitLab


From fd28941cff1cd9d8ffa59fe11eb64148e09b6ed6 Mon Sep 17 00:00:00 2001
From: Jaroslav Kysela <perex@perex.cz>
Date: Thu, 15 Dec 2022 16:30:37 +0100
Subject: [PATCH 622/875] ALSA: usb-audio: Add new quirk FIXED_RATE for JBL
 Quantum810 Wireless

It seems that the firmware is broken and does not accept
the UAC_EP_CS_ATTR_SAMPLE_RATE URB. There is only one rate (48000Hz)
available in the descriptors for the output endpoint.

Create a new quirk QUIRK_FLAG_FIXED_RATE to skip the rate setup
when only one rate is available (fixed).

BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=216798
Signed-off-by: Jaroslav Kysela <perex@perex.cz>
Link: https://lore.kernel.org/r/20221215153037.1163786-1-perex@perex.cz
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/usb/card.h     |  1 +
 sound/usb/endpoint.c | 16 ++++++++++------
 sound/usb/endpoint.h |  3 ++-
 sound/usb/implicit.c |  6 +++++-
 sound/usb/implicit.h |  2 +-
 sound/usb/pcm.c      | 36 +++++++++++++++++++++++++++++++++---
 sound/usb/pcm.h      |  2 ++
 sound/usb/quirks.c   |  2 ++
 sound/usb/usbaudio.h |  4 ++++
 9 files changed, 60 insertions(+), 12 deletions(-)

diff --git a/sound/usb/card.h b/sound/usb/card.h
index 40061550105ac..6ec95b2edf863 100644
--- a/sound/usb/card.h
+++ b/sound/usb/card.h
@@ -131,6 +131,7 @@ struct snd_usb_endpoint {
 	bool lowlatency_playback;	/* low-latency playback mode */
 	bool need_setup;		/* (re-)need for hw_params? */
 	bool need_prepare;		/* (re-)need for prepare? */
+	bool fixed_rate;		/* skip rate setup */
 
 	/* for hw constraints */
 	const struct audioformat *cur_audiofmt;
diff --git a/sound/usb/endpoint.c b/sound/usb/endpoint.c
index 4aaf0784940b5..419302e2057e8 100644
--- a/sound/usb/endpoint.c
+++ b/sound/usb/endpoint.c
@@ -769,7 +769,8 @@ struct snd_usb_endpoint *
 snd_usb_endpoint_open(struct snd_usb_audio *chip,
 		      const struct audioformat *fp,
 		      const struct snd_pcm_hw_params *params,
-		      bool is_sync_ep)
+		      bool is_sync_ep,
+		      bool fixed_rate)
 {
 	struct snd_usb_endpoint *ep;
 	int ep_num = is_sync_ep ? fp->sync_ep : fp->endpoint;
@@ -825,6 +826,7 @@ snd_usb_endpoint_open(struct snd_usb_audio *chip,
 		ep->implicit_fb_sync = fp->implicit_fb;
 		ep->need_setup = true;
 		ep->need_prepare = true;
+		ep->fixed_rate = fixed_rate;
 
 		usb_audio_dbg(chip, "  channels=%d, rate=%d, format=%s, period_bytes=%d, periods=%d, implicit_fb=%d\n",
 			      ep->cur_channels, ep->cur_rate,
@@ -1413,11 +1415,13 @@ static int init_sample_rate(struct snd_usb_audio *chip,
 	if (clock && !clock->need_setup)
 		return 0;
 
-	err = snd_usb_init_sample_rate(chip, ep->cur_audiofmt, rate);
-	if (err < 0) {
-		if (clock)
-			clock->rate = 0; /* reset rate */
-		return err;
+	if (!ep->fixed_rate) {
+		err = snd_usb_init_sample_rate(chip, ep->cur_audiofmt, rate);
+		if (err < 0) {
+			if (clock)
+				clock->rate = 0; /* reset rate */
+			return err;
+		}
 	}
 
 	if (clock)
diff --git a/sound/usb/endpoint.h b/sound/usb/endpoint.h
index e67ea28faa54f..924f4351588ce 100644
--- a/sound/usb/endpoint.h
+++ b/sound/usb/endpoint.h
@@ -14,7 +14,8 @@ struct snd_usb_endpoint *
 snd_usb_endpoint_open(struct snd_usb_audio *chip,
 		      const struct audioformat *fp,
 		      const struct snd_pcm_hw_params *params,
-		      bool is_sync_ep);
+		      bool is_sync_ep,
+		      bool fixed_rate);
 void snd_usb_endpoint_close(struct snd_usb_audio *chip,
 			    struct snd_usb_endpoint *ep);
 int snd_usb_endpoint_set_params(struct snd_usb_audio *chip,
diff --git a/sound/usb/implicit.c b/sound/usb/implicit.c
index f3e8484b3d9cb..41ac7185b42b6 100644
--- a/sound/usb/implicit.c
+++ b/sound/usb/implicit.c
@@ -15,6 +15,7 @@
 #include "usbaudio.h"
 #include "card.h"
 #include "helper.h"
+#include "pcm.h"
 #include "implicit.h"
 
 enum {
@@ -455,7 +456,8 @@ const struct audioformat *
 snd_usb_find_implicit_fb_sync_format(struct snd_usb_audio *chip,
 				     const struct audioformat *target,
 				     const struct snd_pcm_hw_params *params,
-				     int stream)
+				     int stream,
+				     bool *fixed_rate)
 {
 	struct snd_usb_substream *subs;
 	const struct audioformat *fp, *sync_fmt = NULL;
@@ -483,6 +485,8 @@ snd_usb_find_implicit_fb_sync_format(struct snd_usb_audio *chip,
 		}
 	}
 
+	if (fixed_rate)
+		*fixed_rate = snd_usb_pcm_has_fixed_rate(subs);
 	return sync_fmt;
 }
 
diff --git a/sound/usb/implicit.h b/sound/usb/implicit.h
index ccb415a0ea860..7f1577b6c4d38 100644
--- a/sound/usb/implicit.h
+++ b/sound/usb/implicit.h
@@ -9,6 +9,6 @@ const struct audioformat *
 snd_usb_find_implicit_fb_sync_format(struct snd_usb_audio *chip,
 				     const struct audioformat *target,
 				     const struct snd_pcm_hw_params *params,
-				     int stream);
+				     int stream, bool *fixed_rate);
 
 #endif /* __USBAUDIO_IMPLICIT_H */
diff --git a/sound/usb/pcm.c b/sound/usb/pcm.c
index 9557bd4d1bbca..99a66d0ef5b26 100644
--- a/sound/usb/pcm.c
+++ b/sound/usb/pcm.c
@@ -157,6 +157,31 @@ find_substream_format(struct snd_usb_substream *subs,
 			   true, subs);
 }
 
+bool snd_usb_pcm_has_fixed_rate(struct snd_usb_substream *subs)
+{
+	const struct audioformat *fp;
+	struct snd_usb_audio *chip = subs->stream->chip;
+	int rate = -1;
+
+	if (!(chip->quirk_flags & QUIRK_FLAG_FIXED_RATE))
+		return false;
+	list_for_each_entry(fp, &subs->fmt_list, list) {
+		if (fp->rates & SNDRV_PCM_RATE_CONTINUOUS)
+			return false;
+		if (fp->nr_rates < 1)
+			continue;
+		if (fp->nr_rates > 1)
+			return false;
+		if (rate < 0) {
+			rate = fp->rate_table[0];
+			continue;
+		}
+		if (rate != fp->rate_table[0])
+			return false;
+	}
+	return true;
+}
+
 static int init_pitch_v1(struct snd_usb_audio *chip, int ep)
 {
 	struct usb_device *dev = chip->dev;
@@ -450,12 +475,14 @@ static int snd_usb_hw_params(struct snd_pcm_substream *substream,
 	struct snd_usb_audio *chip = subs->stream->chip;
 	const struct audioformat *fmt;
 	const struct audioformat *sync_fmt;
+	bool fixed_rate, sync_fixed_rate;
 	int ret;
 
 	ret = snd_media_start_pipeline(subs);
 	if (ret)
 		return ret;
 
+	fixed_rate = snd_usb_pcm_has_fixed_rate(subs);
 	fmt = find_substream_format(subs, hw_params);
 	if (!fmt) {
 		usb_audio_dbg(chip,
@@ -469,7 +496,8 @@ static int snd_usb_hw_params(struct snd_pcm_substream *substream,
 	if (fmt->implicit_fb) {
 		sync_fmt = snd_usb_find_implicit_fb_sync_format(chip, fmt,
 								hw_params,
-								!substream->stream);
+								!substream->stream,
+								&sync_fixed_rate);
 		if (!sync_fmt) {
 			usb_audio_dbg(chip,
 				      "cannot find sync format: ep=0x%x, iface=%d:%d, format=%s, rate=%d, channels=%d\n",
@@ -482,6 +510,7 @@ static int snd_usb_hw_params(struct snd_pcm_substream *substream,
 		}
 	} else {
 		sync_fmt = fmt;
+		sync_fixed_rate = fixed_rate;
 	}
 
 	ret = snd_usb_lock_shutdown(chip);
@@ -499,7 +528,7 @@ static int snd_usb_hw_params(struct snd_pcm_substream *substream,
 		close_endpoints(chip, subs);
 	}
 
-	subs->data_endpoint = snd_usb_endpoint_open(chip, fmt, hw_params, false);
+	subs->data_endpoint = snd_usb_endpoint_open(chip, fmt, hw_params, false, fixed_rate);
 	if (!subs->data_endpoint) {
 		ret = -EINVAL;
 		goto unlock;
@@ -508,7 +537,8 @@ static int snd_usb_hw_params(struct snd_pcm_substream *substream,
 	if (fmt->sync_ep) {
 		subs->sync_endpoint = snd_usb_endpoint_open(chip, sync_fmt,
 							    hw_params,
-							    fmt == sync_fmt);
+							    fmt == sync_fmt,
+							    sync_fixed_rate);
 		if (!subs->sync_endpoint) {
 			ret = -EINVAL;
 			goto unlock;
diff --git a/sound/usb/pcm.h b/sound/usb/pcm.h
index 493a4e34d78dc..388fe2ba346d6 100644
--- a/sound/usb/pcm.h
+++ b/sound/usb/pcm.h
@@ -6,6 +6,8 @@ void snd_usb_set_pcm_ops(struct snd_pcm *pcm, int stream);
 int snd_usb_pcm_suspend(struct snd_usb_stream *as);
 int snd_usb_pcm_resume(struct snd_usb_stream *as);
 
+bool snd_usb_pcm_has_fixed_rate(struct snd_usb_substream *as);
+
 int snd_usb_init_pitch(struct snd_usb_audio *chip,
 		       const struct audioformat *fmt);
 void snd_usb_preallocate_buffer(struct snd_usb_substream *subs);
diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c
index 58b37bfc885cb..3d13fdf7590cd 100644
--- a/sound/usb/quirks.c
+++ b/sound/usb/quirks.c
@@ -2152,6 +2152,8 @@ static const struct usb_audio_quirk_flags_table quirk_flags_table[] = {
 		   QUIRK_FLAG_GENERIC_IMPLICIT_FB),
 	DEVICE_FLG(0x0525, 0xa4ad, /* Hamedal C20 usb camero */
 		   QUIRK_FLAG_IFACE_SKIP_CLOSE),
+	DEVICE_FLG(0x0ecb, 0x2069, /* JBL Quantum810 Wireless */
+		   QUIRK_FLAG_FIXED_RATE),
 
 	/* Vendor matches */
 	VENDOR_FLG(0x045e, /* MS Lifecam */
diff --git a/sound/usb/usbaudio.h b/sound/usb/usbaudio.h
index 2aba508a48312..f5a8dca66457f 100644
--- a/sound/usb/usbaudio.h
+++ b/sound/usb/usbaudio.h
@@ -175,6 +175,9 @@ extern bool snd_usb_skip_validation;
  * QUIRK_FLAG_FORCE_IFACE_RESET
  *  Force an interface reset whenever stopping & restarting a stream
  *  (e.g. after xrun)
+ * QUIRK_FLAG_FIXED_RATE
+ *  Do not set PCM rate (frequency) when only one rate is available
+ *  for the given endpoint.
  */
 
 #define QUIRK_FLAG_GET_SAMPLE_RATE	(1U << 0)
@@ -198,5 +201,6 @@ extern bool snd_usb_skip_validation;
 #define QUIRK_FLAG_SKIP_IMPLICIT_FB	(1U << 18)
 #define QUIRK_FLAG_IFACE_SKIP_CLOSE	(1U << 19)
 #define QUIRK_FLAG_FORCE_IFACE_RESET	(1U << 20)
+#define QUIRK_FLAG_FIXED_RATE		(1U << 21)
 
 #endif /* __USBAUDIO_H */
-- 
GitLab


From 3659fb5ac29a5e6102bebe494ac789fd47fb78f4 Mon Sep 17 00:00:00 2001
From: Yanjun Zhang <zhangyanjun@cestc.cn>
Date: Thu, 22 Dec 2022 09:57:21 +0800
Subject: [PATCH 623/875] nvme: fix multipath crash caused by flush request
 when blktrace is enabled

The flush request initialized by blk_kick_flush has NULL bio,
and it may be dealt with nvme_end_req during io completion.
When blktrace is enabled, nvme_trace_bio_complete with multipath
activated trying to access NULL pointer bio from flush request
results in the following crash:

[ 2517.831677] BUG: kernel NULL pointer dereference, address: 000000000000001a
[ 2517.835213] #PF: supervisor read access in kernel mode
[ 2517.838724] #PF: error_code(0x0000) - not-present page
[ 2517.842222] PGD 7b2d51067 P4D 0
[ 2517.845684] Oops: 0000 [#1] SMP NOPTI
[ 2517.849125] CPU: 2 PID: 732 Comm: kworker/2:1H Kdump: loaded Tainted: G S                5.15.67-0.cl9.x86_64 #1
[ 2517.852723] Hardware name: XFUSION 2288H V6/BC13MBSBC, BIOS 1.13 07/27/2022
[ 2517.856358] Workqueue: nvme_tcp_wq nvme_tcp_io_work [nvme_tcp]
[ 2517.859993] RIP: 0010:blk_add_trace_bio_complete+0x6/0x30
[ 2517.863628] Code: 1f 44 00 00 48 8b 46 08 31 c9 ba 04 00 10 00 48 8b 80 50 03 00 00 48 8b 78 50 e9 e5 fe ff ff 0f 1f 44 00 00 41 54 49 89 f4 55 <0f> b6 7a 1a 48 89 d5 e8 3e 1c 2b 00 48 89 ee 4c 89 e7 5d 89 c1 ba
[ 2517.871269] RSP: 0018:ff7f6a008d9dbcd0 EFLAGS: 00010286
[ 2517.875081] RAX: ff3d5b4be00b1d50 RBX: 0000000002040002 RCX: ff3d5b0a270f2000
[ 2517.878966] RDX: 0000000000000000 RSI: ff3d5b0b021fb9f8 RDI: 0000000000000000
[ 2517.882849] RBP: ff3d5b0b96a6fa00 R08: 0000000000000001 R09: 0000000000000000
[ 2517.886718] R10: 000000000000000c R11: 000000000000000c R12: ff3d5b0b021fb9f8
[ 2517.890575] R13: 0000000002000000 R14: ff3d5b0b021fb1b0 R15: 0000000000000018
[ 2517.894434] FS:  0000000000000000(0000) GS:ff3d5b42bfc80000(0000) knlGS:0000000000000000
[ 2517.898299] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 2517.902157] CR2: 000000000000001a CR3: 00000004f023e005 CR4: 0000000000771ee0
[ 2517.906053] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[ 2517.909930] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
[ 2517.913761] PKRU: 55555554
[ 2517.917558] Call Trace:
[ 2517.921294]  <TASK>
[ 2517.924982]  nvme_complete_rq+0x1c3/0x1e0 [nvme_core]
[ 2517.928715]  nvme_tcp_recv_pdu+0x4d7/0x540 [nvme_tcp]
[ 2517.932442]  nvme_tcp_recv_skb+0x4f/0x240 [nvme_tcp]
[ 2517.936137]  ? nvme_tcp_recv_pdu+0x540/0x540 [nvme_tcp]
[ 2517.939830]  tcp_read_sock+0x9c/0x260
[ 2517.943486]  nvme_tcp_try_recv+0x65/0xa0 [nvme_tcp]
[ 2517.947173]  nvme_tcp_io_work+0x64/0x90 [nvme_tcp]
[ 2517.950834]  process_one_work+0x1e8/0x390
[ 2517.954473]  worker_thread+0x53/0x3c0
[ 2517.958069]  ? process_one_work+0x390/0x390
[ 2517.961655]  kthread+0x10c/0x130
[ 2517.965211]  ? set_kthread_struct+0x40/0x40
[ 2517.968760]  ret_from_fork+0x1f/0x30
[ 2517.972285]  </TASK>

To avoid this situation, add a NULL check for req->bio before
calling trace_block_bio_complete.

Signed-off-by: Yanjun Zhang <zhangyanjun@cestc.cn>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/nvme/host/nvme.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/nvme/host/nvme.h b/drivers/nvme/host/nvme.h
index 6bbb73ef8b254..424c8a467a0c2 100644
--- a/drivers/nvme/host/nvme.h
+++ b/drivers/nvme/host/nvme.h
@@ -893,7 +893,7 @@ static inline void nvme_trace_bio_complete(struct request *req)
 {
 	struct nvme_ns *ns = req->q->queuedata;
 
-	if (req->cmd_flags & REQ_NVME_MPATH)
+	if ((req->cmd_flags & REQ_NVME_MPATH) && req->bio)
 		trace_block_bio_complete(ns->head->disk->queue, req->bio);
 }
 
-- 
GitLab


From 123b99619cca94bdca0bf7bde9abe28f0a0dfe06 Mon Sep 17 00:00:00 2001
From: Pablo Neira Ayuso <pablo@netfilter.org>
Date: Mon, 19 Dec 2022 20:10:12 +0100
Subject: [PATCH 624/875] netfilter: nf_tables: honor set timeout and garbage
 collection updates

Set timeout and garbage collection interval updates are ignored on
updates. Add transaction to update global set element timeout and
garbage collection interval.

Fixes: 96518518cc41 ("netfilter: add nftables")
Suggested-by: Florian Westphal <fw@strlen.de>
Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
---
 include/net/netfilter/nf_tables.h | 13 ++++++-
 net/netfilter/nf_tables_api.c     | 63 ++++++++++++++++++++++---------
 2 files changed, 57 insertions(+), 19 deletions(-)

diff --git a/include/net/netfilter/nf_tables.h b/include/net/netfilter/nf_tables.h
index 4957b4775757b..9430128aae991 100644
--- a/include/net/netfilter/nf_tables.h
+++ b/include/net/netfilter/nf_tables.h
@@ -597,7 +597,9 @@ void *nft_set_catchall_gc(const struct nft_set *set);
 
 static inline unsigned long nft_set_gc_interval(const struct nft_set *set)
 {
-	return set->gc_int ? msecs_to_jiffies(set->gc_int) : HZ;
+	u32 gc_int = READ_ONCE(set->gc_int);
+
+	return gc_int ? msecs_to_jiffies(gc_int) : HZ;
 }
 
 /**
@@ -1570,6 +1572,9 @@ struct nft_trans_rule {
 struct nft_trans_set {
 	struct nft_set			*set;
 	u32				set_id;
+	u32				gc_int;
+	u64				timeout;
+	bool				update;
 	bool				bound;
 };
 
@@ -1579,6 +1584,12 @@ struct nft_trans_set {
 	(((struct nft_trans_set *)trans->data)->set_id)
 #define nft_trans_set_bound(trans)	\
 	(((struct nft_trans_set *)trans->data)->bound)
+#define nft_trans_set_update(trans)	\
+	(((struct nft_trans_set *)trans->data)->update)
+#define nft_trans_set_timeout(trans)	\
+	(((struct nft_trans_set *)trans->data)->timeout)
+#define nft_trans_set_gc_int(trans)	\
+	(((struct nft_trans_set *)trans->data)->gc_int)
 
 struct nft_trans_chain {
 	bool				update;
diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c
index 319887f4d3ef7..8c09e4d12ac1e 100644
--- a/net/netfilter/nf_tables_api.c
+++ b/net/netfilter/nf_tables_api.c
@@ -465,8 +465,9 @@ static int nft_delrule_by_chain(struct nft_ctx *ctx)
 	return 0;
 }
 
-static int nft_trans_set_add(const struct nft_ctx *ctx, int msg_type,
-			     struct nft_set *set)
+static int __nft_trans_set_add(const struct nft_ctx *ctx, int msg_type,
+			       struct nft_set *set,
+			       const struct nft_set_desc *desc)
 {
 	struct nft_trans *trans;
 
@@ -474,17 +475,28 @@ static int nft_trans_set_add(const struct nft_ctx *ctx, int msg_type,
 	if (trans == NULL)
 		return -ENOMEM;
 
-	if (msg_type == NFT_MSG_NEWSET && ctx->nla[NFTA_SET_ID] != NULL) {
+	if (msg_type == NFT_MSG_NEWSET && ctx->nla[NFTA_SET_ID] && !desc) {
 		nft_trans_set_id(trans) =
 			ntohl(nla_get_be32(ctx->nla[NFTA_SET_ID]));
 		nft_activate_next(ctx->net, set);
 	}
 	nft_trans_set(trans) = set;
+	if (desc) {
+		nft_trans_set_update(trans) = true;
+		nft_trans_set_gc_int(trans) = desc->gc_int;
+		nft_trans_set_timeout(trans) = desc->timeout;
+	}
 	nft_trans_commit_list_add_tail(ctx->net, trans);
 
 	return 0;
 }
 
+static int nft_trans_set_add(const struct nft_ctx *ctx, int msg_type,
+			     struct nft_set *set)
+{
+	return __nft_trans_set_add(ctx, msg_type, set, NULL);
+}
+
 static int nft_delset(const struct nft_ctx *ctx, struct nft_set *set)
 {
 	int err;
@@ -4044,8 +4056,10 @@ static int nf_tables_fill_set_concat(struct sk_buff *skb,
 static int nf_tables_fill_set(struct sk_buff *skb, const struct nft_ctx *ctx,
 			      const struct nft_set *set, u16 event, u16 flags)
 {
-	struct nlmsghdr *nlh;
+	u64 timeout = READ_ONCE(set->timeout);
+	u32 gc_int = READ_ONCE(set->gc_int);
 	u32 portid = ctx->portid;
+	struct nlmsghdr *nlh;
 	struct nlattr *nest;
 	u32 seq = ctx->seq;
 	int i;
@@ -4081,13 +4095,13 @@ static int nf_tables_fill_set(struct sk_buff *skb, const struct nft_ctx *ctx,
 	    nla_put_be32(skb, NFTA_SET_OBJ_TYPE, htonl(set->objtype)))
 		goto nla_put_failure;
 
-	if (set->timeout &&
+	if (timeout &&
 	    nla_put_be64(skb, NFTA_SET_TIMEOUT,
-			 nf_jiffies64_to_msecs(set->timeout),
+			 nf_jiffies64_to_msecs(timeout),
 			 NFTA_SET_PAD))
 		goto nla_put_failure;
-	if (set->gc_int &&
-	    nla_put_be32(skb, NFTA_SET_GC_INTERVAL, htonl(set->gc_int)))
+	if (gc_int &&
+	    nla_put_be32(skb, NFTA_SET_GC_INTERVAL, htonl(gc_int)))
 		goto nla_put_failure;
 
 	if (set->policy != NFT_SET_POL_PERFORMANCE) {
@@ -4632,7 +4646,10 @@ static int nf_tables_newset(struct sk_buff *skb, const struct nfnl_info *info,
 		for (i = 0; i < num_exprs; i++)
 			nft_expr_destroy(&ctx, exprs[i]);
 
-		return err;
+		if (err < 0)
+			return err;
+
+		return __nft_trans_set_add(&ctx, NFT_MSG_NEWSET, set, &desc);
 	}
 
 	if (!(info->nlh->nlmsg_flags & NLM_F_CREATE))
@@ -6070,7 +6087,7 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set,
 			return err;
 	} else if (set->flags & NFT_SET_TIMEOUT &&
 		   !(flags & NFT_SET_ELEM_INTERVAL_END)) {
-		timeout = set->timeout;
+		timeout = READ_ONCE(set->timeout);
 	}
 
 	expiration = 0;
@@ -6171,7 +6188,7 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set,
 		if (err < 0)
 			goto err_parse_key_end;
 
-		if (timeout != set->timeout) {
+		if (timeout != READ_ONCE(set->timeout)) {
 			err = nft_set_ext_add(&tmpl, NFT_SET_EXT_TIMEOUT);
 			if (err < 0)
 				goto err_parse_key_end;
@@ -9093,14 +9110,20 @@ static int nf_tables_commit(struct net *net, struct sk_buff *skb)
 				nft_flow_rule_destroy(nft_trans_flow_rule(trans));
 			break;
 		case NFT_MSG_NEWSET:
-			nft_clear(net, nft_trans_set(trans));
-			/* This avoids hitting -EBUSY when deleting the table
-			 * from the transaction.
-			 */
-			if (nft_set_is_anonymous(nft_trans_set(trans)) &&
-			    !list_empty(&nft_trans_set(trans)->bindings))
-				trans->ctx.table->use--;
+			if (nft_trans_set_update(trans)) {
+				struct nft_set *set = nft_trans_set(trans);
 
+				WRITE_ONCE(set->timeout, nft_trans_set_timeout(trans));
+				WRITE_ONCE(set->gc_int, nft_trans_set_gc_int(trans));
+			} else {
+				nft_clear(net, nft_trans_set(trans));
+				/* This avoids hitting -EBUSY when deleting the table
+				 * from the transaction.
+				 */
+				if (nft_set_is_anonymous(nft_trans_set(trans)) &&
+				    !list_empty(&nft_trans_set(trans)->bindings))
+					trans->ctx.table->use--;
+			}
 			nf_tables_set_notify(&trans->ctx, nft_trans_set(trans),
 					     NFT_MSG_NEWSET, GFP_KERNEL);
 			nft_trans_destroy(trans);
@@ -9322,6 +9345,10 @@ static int __nf_tables_abort(struct net *net, enum nfnl_abort_action action)
 			nft_trans_destroy(trans);
 			break;
 		case NFT_MSG_NEWSET:
+			if (nft_trans_set_update(trans)) {
+				nft_trans_destroy(trans);
+				break;
+			}
 			trans->ctx.table->use--;
 			if (nft_trans_set_bound(trans)) {
 				nft_trans_destroy(trans);
-- 
GitLab


From 42c7ded0eeacd2ba5db599205c71c279dc715de7 Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Tue, 20 Dec 2022 13:08:31 +0000
Subject: [PATCH 625/875] bonding: fix lockdep splat in bond_miimon_commit()

bond_miimon_commit() is run while RTNL is held, not RCU.

WARNING: suspicious RCU usage
6.1.0-syzkaller-09671-g89529367293c #0 Not tainted
-----------------------------
drivers/net/bonding/bond_main.c:2704 suspicious rcu_dereference_check() usage!

Fixes: e95cc44763a4 ("bonding: do failover when high prio link up")
Signed-off-by: Eric Dumazet <edumazet@google.com>
Reported-by: syzbot <syzkaller@googlegroups.com>
Cc: Hangbin Liu <liuhangbin@gmail.com>
Cc: Jay Vosburgh <j.vosburgh@gmail.com>
Cc: Veaceslav Falico <vfalico@gmail.com>
Cc: Andy Gospodarek <andy@greyhouse.net>
Link: https://lore.kernel.org/r/20221220130831.1480888-1-edumazet@google.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
---
 drivers/net/bonding/bond_main.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c
index b4c65783960a5..0363ce5976614 100644
--- a/drivers/net/bonding/bond_main.c
+++ b/drivers/net/bonding/bond_main.c
@@ -2654,10 +2654,12 @@ static void bond_miimon_link_change(struct bonding *bond,
 
 static void bond_miimon_commit(struct bonding *bond)
 {
-	struct slave *slave, *primary;
+	struct slave *slave, *primary, *active;
 	bool do_failover = false;
 	struct list_head *iter;
 
+	ASSERT_RTNL();
+
 	bond_for_each_slave(bond, slave, iter) {
 		switch (slave->link_new_state) {
 		case BOND_LINK_NOCHANGE:
@@ -2700,8 +2702,8 @@ static void bond_miimon_commit(struct bonding *bond)
 
 			bond_miimon_link_change(bond, slave, BOND_LINK_UP);
 
-			if (!rcu_access_pointer(bond->curr_active_slave) || slave == primary ||
-			    slave->prio > rcu_dereference(bond->curr_active_slave)->prio)
+			active = rtnl_dereference(bond->curr_active_slave);
+			if (!active || slave == primary || slave->prio > active->prio)
 				do_failover = true;
 
 			continue;
-- 
GitLab


From d717f9474e3fb7e6bd3e43ca16e131f04320ed6f Mon Sep 17 00:00:00 2001
From: Horatiu Vultur <horatiu.vultur@microchip.com>
Date: Wed, 21 Dec 2022 10:33:15 +0100
Subject: [PATCH 626/875] net: lan966x: Fix configuration of the PCS

When the PCS was taken out of reset, we were changing by mistake also
the speed to 100 Mbit. But in case the link was going down, the link
up routine was setting correctly the link speed. If the link was not
getting down then the speed was forced to run at 100 even if the
speed was something else.
On lan966x, to set the speed link to 1G or 2.5G a value of 1 needs to be
written in DEV_CLOCK_CFG_LINK_SPEED. This is similar to the procedure in
lan966x_port_init.

The issue was reproduced using 1000base-x sfp module using the commands:
ip link set dev eth2 up
ip link addr add 10.97.10.2/24 dev eth2
ethtool -s eth2 speed 1000 autoneg off

Fixes: d28d6d2e37d1 ("net: lan966x: add port module support")
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Piotr Raczynski <piotr.raczynski@intel.com>
Link: https://lore.kernel.org/r/20221221093315.939133-1-horatiu.vultur@microchip.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
---
 drivers/net/ethernet/microchip/lan966x/lan966x_port.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_port.c b/drivers/net/ethernet/microchip/lan966x/lan966x_port.c
index 1a61c6cdb0779..0050fcb988b75 100644
--- a/drivers/net/ethernet/microchip/lan966x/lan966x_port.c
+++ b/drivers/net/ethernet/microchip/lan966x/lan966x_port.c
@@ -381,7 +381,7 @@ int lan966x_port_pcs_set(struct lan966x_port *port,
 	}
 
 	/* Take PCS out of reset */
-	lan_rmw(DEV_CLOCK_CFG_LINK_SPEED_SET(2) |
+	lan_rmw(DEV_CLOCK_CFG_LINK_SPEED_SET(LAN966X_SPEED_1000) |
 		DEV_CLOCK_CFG_PCS_RX_RST_SET(0) |
 		DEV_CLOCK_CFG_PCS_TX_RST_SET(0),
 		DEV_CLOCK_CFG_LINK_SPEED |
-- 
GitLab


From 36f82c93ee0bd88f1c95a52537906b8178b537f1 Mon Sep 17 00:00:00 2001
From: David Howells <dhowells@redhat.com>
Date: Wed, 21 Dec 2022 14:30:48 +0000
Subject: [PATCH 627/875] afs: Fix lost servers_outstanding count

The afs_fs_probe_dispatcher() work function is passed a count on
net->servers_outstanding when it is scheduled (which may come via its
timer).  This is passed back to the work_item, passed to the timer or
dropped at the end of the dispatcher function.

But, at the top of the dispatcher function, there are two checks which
skip the rest of the function: if the network namespace is being destroyed
or if there are no fileservers to probe.  These two return paths, however,
do not drop the count passed to the dispatcher, and so, sometimes, the
destruction of a network namespace, such as induced by rmmod of the kafs
module, may get stuck in afs_purge_servers(), waiting for
net->servers_outstanding to become zero.

Fix this by adding the missing decrements in afs_fs_probe_dispatcher().

Fixes: f6cbb368bcb0 ("afs: Actively poll fileservers to maintain NAT or firewall openings")
Reported-by: Marc Dionne <marc.dionne@auristor.com>
Signed-off-by: David Howells <dhowells@redhat.com>
Tested-by: Marc Dionne <marc.dionne@auristor.com>
cc: linux-afs@lists.infradead.org
Link: https://lore.kernel.org/r/167164544917.2072364.3759519569649459359.stgit@warthog.procyon.org.uk/
---
 fs/afs/fs_probe.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/fs/afs/fs_probe.c b/fs/afs/fs_probe.c
index 3ac5fcf98d0d6..daaf3810cc925 100644
--- a/fs/afs/fs_probe.c
+++ b/fs/afs/fs_probe.c
@@ -366,12 +366,15 @@ void afs_fs_probe_dispatcher(struct work_struct *work)
 	unsigned long nowj, timer_at, poll_at;
 	bool first_pass = true, set_timer = false;
 
-	if (!net->live)
+	if (!net->live) {
+		afs_dec_servers_outstanding(net);
 		return;
+	}
 
 	_enter("");
 
 	if (list_empty(&net->fs_probe_fast) && list_empty(&net->fs_probe_slow)) {
+		afs_dec_servers_outstanding(net);
 		_leave(" [none]");
 		return;
 	}
-- 
GitLab


From 318b83b71242998814a570c3420c042ee6165fca Mon Sep 17 00:00:00 2001
From: Colin Ian King <colin.i.king@gmail.com>
Date: Thu, 20 Oct 2022 18:39:23 +0100
Subject: [PATCH 628/875] afs: remove variable nr_servers

Variable nr_servers is no longer being used, the last reference
to it was removed in commit 45df8462730d ("afs: Fix server list handling")
so clean up the code by removing it.

Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Signed-off-by: David Howells <dhowells@redhat.com>
cc: Marc Dionne <marc.dionne@auristor.com>
cc: linux-afs@lists.infradead.org
Link: https://lore.kernel.org/r/20221020173923.21342-1-colin.i.king@gmail.com/
---
 fs/afs/volume.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/fs/afs/volume.c b/fs/afs/volume.c
index f4937029dcd72..29d483c802813 100644
--- a/fs/afs/volume.c
+++ b/fs/afs/volume.c
@@ -70,11 +70,7 @@ static struct afs_volume *afs_alloc_volume(struct afs_fs_context *params,
 {
 	struct afs_server_list *slist;
 	struct afs_volume *volume;
-	int ret = -ENOMEM, nr_servers = 0, i;
-
-	for (i = 0; i < vldb->nr_servers; i++)
-		if (vldb->fs_mask[i] & type_mask)
-			nr_servers++;
+	int ret = -ENOMEM;
 
 	volume = kzalloc(sizeof(struct afs_volume), GFP_KERNEL);
 	if (!volume)
-- 
GitLab


From b3d3ca556757577c95a6bc786a5b6a48c23f00fa Mon Sep 17 00:00:00 2001
From: Gaosheng Cui <cuigaosheng1@huawei.com>
Date: Fri, 9 Sep 2022 15:03:53 +0800
Subject: [PATCH 629/875] afs: remove afs_cache_netfs and afs_zap_permits()
 declarations

afs_zap_permits() has been removed since
commit be080a6f43c4 ("afs: Overhaul permit caching").

afs_cache_netfs has been removed since
commit 523d27cda149 ("afs: Convert afs to use the new fscache API").

so remove the declare for them from header file.

Signed-off-by: Gaosheng Cui <cuigaosheng1@huawei.com>
Signed-off-by: David Howells <dhowells@redhat.com>
cc: Marc Dionne <marc.dionne@auristor.com>
cc: linux-afs@lists.infradead.org
Link: https://lore.kernel.org/r/20220909070353.1160228-1-cuigaosheng1@huawei.com/
---
 fs/afs/internal.h | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/fs/afs/internal.h b/fs/afs/internal.h
index 9ba7b68375c9f..fd8567b98e2bb 100644
--- a/fs/afs/internal.h
+++ b/fs/afs/internal.h
@@ -971,13 +971,6 @@ extern int afs_end_cursor(struct afs_addr_cursor *);
 extern void afs_merge_fs_addr4(struct afs_addr_list *, __be32, u16);
 extern void afs_merge_fs_addr6(struct afs_addr_list *, __be32 *, u16);
 
-/*
- * cache.c
- */
-#ifdef CONFIG_AFS_FSCACHE
-extern struct fscache_netfs afs_cache_netfs;
-#endif
-
 /*
  * callback.c
  */
@@ -1391,7 +1384,6 @@ extern void afs_put_permits(struct afs_permits *);
 extern void afs_clear_permits(struct afs_vnode *);
 extern void afs_cache_permit(struct afs_vnode *, struct key *, unsigned int,
 			     struct afs_status_cb *);
-extern void afs_zap_permits(struct rcu_head *);
 extern struct key *afs_request_key(struct afs_cell *);
 extern struct key *afs_request_key_rcu(struct afs_cell *);
 extern int afs_check_permit(struct afs_vnode *, struct key *, afs_access_t *);
-- 
GitLab


From a9eb558a5bea66cc43950632f5fffec6b5795233 Mon Sep 17 00:00:00 2001
From: David Howells <dhowells@redhat.com>
Date: Fri, 18 Nov 2022 07:57:27 +0000
Subject: [PATCH 630/875] afs: Stop implementing ->writepage()

We're trying to get rid of the ->writepage() hook[1].  Stop afs from using
it by unlocking the page and calling afs_writepages_region() rather than
folio_write_one().

A flag is passed to afs_writepages_region() to indicate that it should only
write a single region so that we don't flush the entire file in
->write_begin(), but do add other dirty data to the region being written to
try and reduce the number of RPC ops.

This requires ->migrate_folio() to be implemented, so point that at
filemap_migrate_folio() for files and also for symlinks and directories.

This can be tested by turning on the afs_folio_dirty tracepoint and then
doing something like:

   xfs_io -c "w 2223 7000" -c "w 15000 22222" -c "w 23 7" /afs/my/test/foo

and then looking in the trace to see if the write at position 15000 gets
stored before page 0 gets dirtied for the write at position 23.

Signed-off-by: David Howells <dhowells@redhat.com>
cc: Marc Dionne <marc.dionne@auristor.com>
cc: Christoph Hellwig <hch@lst.de>
cc: Matthew Wilcox <willy@infradead.org>
cc: linux-afs@lists.infradead.org
Link: https://lore.kernel.org/r/20221113162902.883850-1-hch@lst.de/ [1]
Link: https://lore.kernel.org/r/166876785552.222254.4403222906022558715.stgit@warthog.procyon.org.uk/ # v1
---
 fs/afs/dir.c   |  1 +
 fs/afs/file.c  |  3 +-
 fs/afs/write.c | 83 ++++++++++++++++++++++++++++----------------------
 3 files changed, 50 insertions(+), 37 deletions(-)

diff --git a/fs/afs/dir.c b/fs/afs/dir.c
index 104df2964225c..b7c1f8c84b38a 100644
--- a/fs/afs/dir.c
+++ b/fs/afs/dir.c
@@ -77,6 +77,7 @@ const struct address_space_operations afs_dir_aops = {
 	.dirty_folio	= afs_dir_dirty_folio,
 	.release_folio	= afs_dir_release_folio,
 	.invalidate_folio = afs_dir_invalidate_folio,
+	.migrate_folio	= filemap_migrate_folio,
 };
 
 const struct dentry_operations afs_fs_dentry_operations = {
diff --git a/fs/afs/file.c b/fs/afs/file.c
index 2eeab57df133a..68d6d5dc608d5 100644
--- a/fs/afs/file.c
+++ b/fs/afs/file.c
@@ -58,14 +58,15 @@ const struct address_space_operations afs_file_aops = {
 	.invalidate_folio = afs_invalidate_folio,
 	.write_begin	= afs_write_begin,
 	.write_end	= afs_write_end,
-	.writepage	= afs_writepage,
 	.writepages	= afs_writepages,
+	.migrate_folio	= filemap_migrate_folio,
 };
 
 const struct address_space_operations afs_symlink_aops = {
 	.read_folio	= afs_symlink_read_folio,
 	.release_folio	= afs_release_folio,
 	.invalidate_folio = afs_invalidate_folio,
+	.migrate_folio	= filemap_migrate_folio,
 };
 
 static const struct vm_operations_struct afs_vm_ops = {
diff --git a/fs/afs/write.c b/fs/afs/write.c
index 08fd456dde67c..19df10d63323d 100644
--- a/fs/afs/write.c
+++ b/fs/afs/write.c
@@ -14,6 +14,11 @@
 #include <linux/netfs.h>
 #include "internal.h"
 
+static int afs_writepages_region(struct address_space *mapping,
+				 struct writeback_control *wbc,
+				 loff_t start, loff_t end, loff_t *_next,
+				 bool max_one_loop);
+
 static void afs_write_to_cache(struct afs_vnode *vnode, loff_t start, size_t len,
 			       loff_t i_size, bool caching);
 
@@ -38,6 +43,25 @@ static void afs_folio_start_fscache(bool caching, struct folio *folio)
 }
 #endif
 
+/*
+ * Flush out a conflicting write.  This may extend the write to the surrounding
+ * pages if also dirty and contiguous to the conflicting region..
+ */
+static int afs_flush_conflicting_write(struct address_space *mapping,
+				       struct folio *folio)
+{
+	struct writeback_control wbc = {
+		.sync_mode	= WB_SYNC_ALL,
+		.nr_to_write	= LONG_MAX,
+		.range_start	= folio_pos(folio),
+		.range_end	= LLONG_MAX,
+	};
+	loff_t next;
+
+	return afs_writepages_region(mapping, &wbc, folio_pos(folio), LLONG_MAX,
+				     &next, true);
+}
+
 /*
  * prepare to perform part of a write to a page
  */
@@ -80,7 +104,8 @@ try_again:
 
 		if (folio_test_writeback(folio)) {
 			trace_afs_folio_dirty(vnode, tracepoint_string("alrdy"), folio);
-			goto flush_conflicting_write;
+			folio_unlock(folio);
+			goto wait_for_writeback;
 		}
 		/* If the file is being filled locally, allow inter-write
 		 * spaces to be merged into writes.  If it's not, only write
@@ -99,8 +124,15 @@ try_again:
 	 * flush the page out.
 	 */
 flush_conflicting_write:
-	_debug("flush conflict");
-	ret = folio_write_one(folio);
+	trace_afs_folio_dirty(vnode, tracepoint_string("confl"), folio);
+	folio_unlock(folio);
+
+	ret = afs_flush_conflicting_write(mapping, folio);
+	if (ret < 0)
+		goto error;
+
+wait_for_writeback:
+	ret = folio_wait_writeback_killable(folio);
 	if (ret < 0)
 		goto error;
 
@@ -663,40 +695,13 @@ static ssize_t afs_write_back_from_locked_folio(struct address_space *mapping,
 	return ret;
 }
 
-/*
- * write a page back to the server
- * - the caller locked the page for us
- */
-int afs_writepage(struct page *subpage, struct writeback_control *wbc)
-{
-	struct folio *folio = page_folio(subpage);
-	ssize_t ret;
-	loff_t start;
-
-	_enter("{%lx},", folio_index(folio));
-
-#ifdef CONFIG_AFS_FSCACHE
-	folio_wait_fscache(folio);
-#endif
-
-	start = folio_index(folio) * PAGE_SIZE;
-	ret = afs_write_back_from_locked_folio(folio_mapping(folio), wbc,
-					       folio, start, LLONG_MAX - start);
-	if (ret < 0) {
-		_leave(" = %zd", ret);
-		return ret;
-	}
-
-	_leave(" = 0");
-	return 0;
-}
-
 /*
  * write a region of pages back to the server
  */
 static int afs_writepages_region(struct address_space *mapping,
 				 struct writeback_control *wbc,
-				 loff_t start, loff_t end, loff_t *_next)
+				 loff_t start, loff_t end, loff_t *_next,
+				 bool max_one_loop)
 {
 	struct folio *folio;
 	struct page *head_page;
@@ -775,6 +780,9 @@ static int afs_writepages_region(struct address_space *mapping,
 
 		start += ret;
 
+		if (max_one_loop)
+			break;
+
 		cond_resched();
 	} while (wbc->nr_to_write > 0);
 
@@ -806,24 +814,27 @@ int afs_writepages(struct address_space *mapping,
 
 	if (wbc->range_cyclic) {
 		start = mapping->writeback_index * PAGE_SIZE;
-		ret = afs_writepages_region(mapping, wbc, start, LLONG_MAX, &next);
+		ret = afs_writepages_region(mapping, wbc, start, LLONG_MAX,
+					    &next, false);
 		if (ret == 0) {
 			mapping->writeback_index = next / PAGE_SIZE;
 			if (start > 0 && wbc->nr_to_write > 0) {
 				ret = afs_writepages_region(mapping, wbc, 0,
-							    start, &next);
+							    start, &next, false);
 				if (ret == 0)
 					mapping->writeback_index =
 						next / PAGE_SIZE;
 			}
 		}
 	} else if (wbc->range_start == 0 && wbc->range_end == LLONG_MAX) {
-		ret = afs_writepages_region(mapping, wbc, 0, LLONG_MAX, &next);
+		ret = afs_writepages_region(mapping, wbc, 0, LLONG_MAX,
+					    &next, false);
 		if (wbc->nr_to_write > 0 && ret == 0)
 			mapping->writeback_index = next / PAGE_SIZE;
 	} else {
 		ret = afs_writepages_region(mapping, wbc,
-					    wbc->range_start, wbc->range_end, &next);
+					    wbc->range_start, wbc->range_end,
+					    &next, false);
 	}
 
 	up_read(&vnode->validate_lock);
-- 
GitLab


From fa349e396e4886d742fd6501c599ec627ef1353b Mon Sep 17 00:00:00 2001
From: Shawn Bohrer <sbohrer@cloudflare.com>
Date: Tue, 20 Dec 2022 12:59:03 -0600
Subject: [PATCH 631/875] veth: Fix race with AF_XDP exposing old or
 uninitialized descriptors

When AF_XDP is used on on a veth interface the RX ring is updated in two
steps.  veth_xdp_rcv() removes packet descriptors from the FILL ring
fills them and places them in the RX ring updating the cached_prod
pointer.  Later xdp_do_flush() syncs the RX ring prod pointer with the
cached_prod pointer allowing user-space to see the recently filled in
descriptors.  The rings are intended to be SPSC, however the existing
order in veth_poll allows the xdp_do_flush() to run concurrently with
another CPU creating a race condition that allows user-space to see old
or uninitialized descriptors in the RX ring.  This bug has been observed
in production systems.

To summarize, we are expecting this ordering:

CPU 0 __xsk_rcv_zc()
CPU 0 __xsk_map_flush()
CPU 2 __xsk_rcv_zc()
CPU 2 __xsk_map_flush()

But we are seeing this order:

CPU 0 __xsk_rcv_zc()
CPU 2 __xsk_rcv_zc()
CPU 0 __xsk_map_flush()
CPU 2 __xsk_map_flush()

This occurs because we rely on NAPI to ensure that only one napi_poll
handler is running at a time for the given veth receive queue.
napi_schedule_prep() will prevent multiple instances from getting
scheduled. However calling napi_complete_done() signals that this
napi_poll is complete and allows subsequent calls to
napi_schedule_prep() and __napi_schedule() to succeed in scheduling a
concurrent napi_poll before the xdp_do_flush() has been called.  For the
veth driver a concurrent call to napi_schedule_prep() and
__napi_schedule() can occur on a different CPU because the veth xmit
path can additionally schedule a napi_poll creating the race.

The fix as suggested by Magnus Karlsson, is to simply move the
xdp_do_flush() call before napi_complete_done().  This syncs the
producer ring pointers before another instance of napi_poll can be
scheduled on another CPU.  It will also slightly improve performance by
moving the flush closer to when the descriptors were placed in the
RX ring.

Fixes: d1396004dd86 ("veth: Add XDP TX and REDIRECT")
Suggested-by: Magnus Karlsson <magnus.karlsson@gmail.com>
Signed-off-by: Shawn Bohrer <sbohrer@cloudflare.com>
Link: https://lore.kernel.org/r/20221220185903.1105011-1-sbohrer@cloudflare.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
---
 drivers/net/veth.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/net/veth.c b/drivers/net/veth.c
index ac7c0653695f0..dfc7d87fad59f 100644
--- a/drivers/net/veth.c
+++ b/drivers/net/veth.c
@@ -974,6 +974,9 @@ static int veth_poll(struct napi_struct *napi, int budget)
 	xdp_set_return_frame_no_direct();
 	done = veth_xdp_rcv(rq, budget, &bq, &stats);
 
+	if (stats.xdp_redirect > 0)
+		xdp_do_flush();
+
 	if (done < budget && napi_complete_done(napi, done)) {
 		/* Write rx_notify_masked before reading ptr_ring */
 		smp_store_mb(rq->rx_notify_masked, false);
@@ -987,8 +990,6 @@ static int veth_poll(struct napi_struct *napi, int budget)
 
 	if (stats.xdp_tx > 0)
 		veth_xdp_flush(rq, &bq);
-	if (stats.xdp_redirect > 0)
-		xdp_do_flush();
 	xdp_clear_return_frame_no_direct();
 
 	return done;
-- 
GitLab


From 09e6f9f98370be9a9f8978139e0eb1be87d1125f Mon Sep 17 00:00:00 2001
From: Arnaldo Carvalho de Melo <acme@redhat.com>
Date: Thu, 22 Dec 2022 10:56:25 -0300
Subject: [PATCH 632/875] perf python: Fix splitting CC into compiler and
 options

Noticed this build failure on archlinux:base when building with clang:

  clang-14: error: optimization flag '-ffat-lto-objects' is not supported [-Werror,-Wignored-optimization-argument]

In tools/perf/util/setup.py we check if clang supports that option, but
since commit 3cad53a6f9cdbafa ("perf python: Account for multiple words
in CC") this got broken as in the common case where CC="clang":

  >>> cc="clang"
  >>> print(cc.split()[0])
  clang
  >>> option="-ffat-lto-objects"
  >>> print(str(cc.split()[1:]) + option)
  []-ffat-lto-objects
  >>>

And then the Popen will call clang with that bogus option name that in
turn will not produce the b"unknown argument" or b"is not supported"
that this function uses to detect if the option is not available and
thus later on clang will be called with an unknown/unsupported option.

Fix it by looking if really there are options in the provided CC
variable, and if so override 'cc' with the first token and append the
options to the 'option' variable.

Fixes: 3cad53a6f9cdbafa ("perf python: Account for multiple words in CC")
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Fangrui Song <maskray@google.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Keeping <john@metanate.com>
Cc: Khem Raj <raj.khem@gmail.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Michael Petlan <mpetlan@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Nathan Chancellor <nathan@kernel.org>
Cc: Nick Desaulniers <ndesaulniers@google.com>
Cc: Sedat Dilek <sedat.dilek@gmail.com>
Link: http://lore.kernel.org/lkml/Y6Rq5F5NI0v1QQHM@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/setup.py | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/tools/perf/util/setup.py b/tools/perf/util/setup.py
index 4f265d0222c45..c294db713677c 100644
--- a/tools/perf/util/setup.py
+++ b/tools/perf/util/setup.py
@@ -3,11 +3,20 @@ from subprocess import Popen, PIPE
 from re import sub
 
 cc = getenv("CC")
-cc_is_clang = b"clang version" in Popen([cc.split()[0], "-v"], stderr=PIPE).stderr.readline()
+
+# Check if CC has options, as is the case in yocto, where it uses CC="cc --sysroot..."
+cc_tokens = cc.split()
+if len(cc_tokens) > 1:
+    cc = cc_tokens[0]
+    cc_options = " ".join([str(e) for e in cc_tokens[1:]]) + " "
+else:
+    cc_options = ""
+
+cc_is_clang = b"clang version" in Popen([cc, "-v"], stderr=PIPE).stderr.readline()
 src_feature_tests  = getenv('srctree') + '/tools/build/feature'
 
 def clang_has_option(option):
-    cc_output = Popen([cc.split()[0], str(cc.split()[1:]) + option, path.join(src_feature_tests, "test-hello.c") ], stderr=PIPE).stderr.readlines()
+    cc_output = Popen([cc, cc_options + option, path.join(src_feature_tests, "test-hello.c") ], stderr=PIPE).stderr.readlines()
     return [o for o in cc_output if ((b"unknown argument" in o) or (b"is not supported" in o))] == [ ]
 
 if cc_is_clang:
-- 
GitLab


From 789e1e10f214c00ca18fc6610824c5b9876ba5f2 Mon Sep 17 00:00:00 2001
From: Jeff Layton <jlayton@kernel.org>
Date: Thu, 22 Dec 2022 09:51:30 -0500
Subject: [PATCH 633/875] nfsd: shut down the NFSv4 state objects before the
 filecache

Currently, we shut down the filecache before trying to clean up the
stateids that depend on it. This leads to the kernel trying to free an
nfsd_file twice, and a refcount overput on the nf_mark.

Change the shutdown procedure to tear down all of the stateids prior
to shutting down the filecache.

Reported-and-tested-by: Wang Yugui <wangyugui@e16-tech.com>
Signed-off-by: Jeff Layton <jlayton@kernel.org>
Fixes: 5e113224c17e ("nfsd: nfsd_file cache entries should be per net namespace")
Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
---
 fs/nfsd/nfssvc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/nfsd/nfssvc.c b/fs/nfsd/nfssvc.c
index 56fba1cba3af7..325d3d3f12110 100644
--- a/fs/nfsd/nfssvc.c
+++ b/fs/nfsd/nfssvc.c
@@ -453,8 +453,8 @@ static void nfsd_shutdown_net(struct net *net)
 {
 	struct nfsd_net *nn = net_generic(net, nfsd_net_id);
 
-	nfsd_file_cache_shutdown_net(net);
 	nfs4_state_shutdown_net(net);
+	nfsd_file_cache_shutdown_net(net);
 	if (nn->lockd_up) {
 		lockd_down(net);
 		nn->lockd_up = false;
-- 
GitLab


From 00a734104af7d878f1252d49eff9298785c6cbdc Mon Sep 17 00:00:00 2001
From: Mario Limonciello <mario.limonciello@amd.com>
Date: Thu, 8 Dec 2022 10:42:05 -0600
Subject: [PATCH 634/875] ACPI: video: Allow GPU drivers to report no panels

The current logic for the ACPI backlight detection will create
a backlight device if no native or vendor drivers have created
8 seconds after the system has booted if the ACPI tables
included backlight control methods.

If the GPU drivers have loaded, they may be able to report whether
any LCD panels were found.  Allow using this information to factor
in whether to enable the fallback logic for making an acpi_video0
backlight device.

Suggested-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 drivers/acpi/acpi_video.c | 11 +++++++++++
 include/acpi/video.h      |  2 ++
 2 files changed, 13 insertions(+)

diff --git a/drivers/acpi/acpi_video.c b/drivers/acpi/acpi_video.c
index 30d8fd03fec7c..75dc37affff25 100644
--- a/drivers/acpi/acpi_video.c
+++ b/drivers/acpi/acpi_video.c
@@ -2176,6 +2176,17 @@ static bool should_check_lcd_flag(void)
 	return false;
 }
 
+/*
+ * At least one graphics driver has reported that no LCD is connected
+ * via the native interface. cancel the registration for fallback acpi_video0.
+ * If another driver still deems this necessary, it can explicitly register it.
+ */
+void acpi_video_report_nolcd(void)
+{
+	cancel_delayed_work(&video_bus_register_backlight_work);
+}
+EXPORT_SYMBOL(acpi_video_report_nolcd);
+
 int acpi_video_register(void)
 {
 	int ret = 0;
diff --git a/include/acpi/video.h b/include/acpi/video.h
index a275c35e5249d..8ed9bec03e534 100644
--- a/include/acpi/video.h
+++ b/include/acpi/video.h
@@ -53,6 +53,7 @@ enum acpi_backlight_type {
 };
 
 #if IS_ENABLED(CONFIG_ACPI_VIDEO)
+extern void acpi_video_report_nolcd(void);
 extern int acpi_video_register(void);
 extern void acpi_video_unregister(void);
 extern void acpi_video_register_backlight(void);
@@ -69,6 +70,7 @@ extern int acpi_video_get_levels(struct acpi_device *device,
 				 struct acpi_video_device_brightness **dev_br,
 				 int *pmax_level);
 #else
+static inline void acpi_video_report_nolcd(void) { return; };
 static inline int acpi_video_register(void) { return -ENODEV; }
 static inline void acpi_video_unregister(void) { return; }
 static inline void acpi_video_register_backlight(void) { return; }
-- 
GitLab


From c573e240609ff781a0246c0c8c8351abd0475287 Mon Sep 17 00:00:00 2001
From: Mario Limonciello <mario.limonciello@amd.com>
Date: Thu, 8 Dec 2022 10:42:06 -0600
Subject: [PATCH 635/875] drm/amd/display: Report to ACPI video if no panels
 were found

On desktop APUs amdgpu doesn't create a native backlight device
as no eDP panels are found.  However if the BIOS has reported
backlight control methods in the ACPI tables then an acpi_video0
backlight device will be made 8 seconds after boot.

This has manifested in a power slider on a number of desktop APUs
ranging from Ryzen 5000 through Ryzen 7000 on various motherboard
manufacturers. To avoid this, report to the acpi video detection
that the system does not have any panel connected in the native
driver.

Link: https://bugzilla.redhat.com/show_bug.cgi?id=1783786
Reported-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 77277d90b6e2f..a7eb13902af89 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4360,6 +4360,10 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 		amdgpu_set_panel_orientation(&aconnector->base);
 	}
 
+	/* If we didn't find a panel, notify the acpi video detection */
+	if (dm->adev->flags & AMD_IS_APU && dm->num_of_edps == 0)
+		acpi_video_report_nolcd();
+
 	/* Software is initialized. Now we can register interrupt handlers. */
 	switch (adev->asic_type) {
 #if defined(CONFIG_DRM_AMD_DC_SI)
-- 
GitLab


From 5aa9d943e9b6bf6e6023645cbe7ce7d5ed84baf4 Mon Sep 17 00:00:00 2001
From: Mario Limonciello <mario.limonciello@amd.com>
Date: Thu, 8 Dec 2022 10:42:07 -0600
Subject: [PATCH 636/875] ACPI: video: Don't enable fallback path for creating
 ACPI backlight by default

The ACPI video detection code has a module parameter
`register_backlight_delay` which is currently configured to 8 seconds.
This means that if after 8 seconds of booting no native driver has created
a backlight device then the code will attempt to make an ACPI video
backlight device.

This was intended as a safety mechanism with the backlight overhaul that
occurred in kernel 6.1, but as it doesn't appear necesssary set it to be
disabled by default.

Suggested-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 drivers/acpi/acpi_video.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/acpi/acpi_video.c b/drivers/acpi/acpi_video.c
index 75dc37affff25..97b711e57bff4 100644
--- a/drivers/acpi/acpi_video.c
+++ b/drivers/acpi/acpi_video.c
@@ -70,11 +70,7 @@ module_param(device_id_scheme, bool, 0444);
 static int only_lcd = -1;
 module_param(only_lcd, int, 0444);
 
-/*
- * Display probing is known to take up to 5 seconds, so delay the fallback
- * backlight registration by 5 seconds + 3 seconds for some extra margin.
- */
-static int register_backlight_delay = 8;
+static int register_backlight_delay;
 module_param(register_backlight_delay, int, 0444);
 MODULE_PARM_DESC(register_backlight_delay,
 	"Delay in seconds before doing fallback (non GPU driver triggered) "
-- 
GitLab


From 7592b79ba4a91350b38469e05238308bcfe1019b Mon Sep 17 00:00:00 2001
From: Erik Schumacher <ofenfisch@googlemail.com>
Date: Sun, 11 Dec 2022 14:33:22 +0100
Subject: [PATCH 637/875] ACPI: resource: do IRQ override on XMG Core 15

The Schenker XMG CORE 15 (M22) is Ryzen-6 based and needs IRQ overriding
for the keyboard to work. Adding an entry for this laptop to the
override_table makes the internal keyboard functional again.

Signed-off-by: Erik Schumacher <ofenfisch@googlemail.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 drivers/acpi/resource.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/acpi/resource.c b/drivers/acpi/resource.c
index f27914aedbd5a..037d1aa103570 100644
--- a/drivers/acpi/resource.c
+++ b/drivers/acpi/resource.c
@@ -446,6 +446,17 @@ static const struct dmi_system_id lenovo_82ra[] = {
 	{ }
 };
 
+static const struct dmi_system_id schenker_gm_rg[] = {
+	{
+		.ident = "XMG CORE 15 (M22)",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "SchenkerTechnologiesGmbH"),
+			DMI_MATCH(DMI_BOARD_NAME, "GMxRGxx"),
+		},
+	},
+	{ }
+};
+
 struct irq_override_cmp {
 	const struct dmi_system_id *system;
 	unsigned char irq;
@@ -460,6 +471,7 @@ static const struct irq_override_cmp override_table[] = {
 	{ asus_laptop, 1, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_LOW, 0, false },
 	{ lenovo_82ra, 6, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_LOW, 0, true },
 	{ lenovo_82ra, 10, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_LOW, 0, true },
+	{ schenker_gm_rg, 1, ACPI_EDGE_SENSITIVE, ACPI_ACTIVE_LOW, 1, true },
 };
 
 static bool acpi_dev_irq_override(u32 gsi, u8 triggering, u8 polarity,
-- 
GitLab


From f3cb9b740869712d448edf3b9ef5952b847caf8b Mon Sep 17 00:00:00 2001
From: Adrian Freund <adrian@freund.io>
Date: Tue, 13 Dec 2022 21:13:11 +0100
Subject: [PATCH 638/875] ACPI: resource: do IRQ override on Lenovo 14ALC7

Commit bfcdf58380b1 ("ACPI: resource: do IRQ override on LENOVO IdeaPad")
added an override for Lenovo IdeaPad 5 16ALC7. The 14ALC7 variant also
suffers from a broken touchscreen and trackpad.

Fixes: 9946e39fe8d0 ("ACPI: resource: skip IRQ override on AMD Zen platforms")
Link: https://bugzilla.kernel.org/show_bug.cgi?id=216804
Signed-off-by: Adrian Freund <adrian@freund.io>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 drivers/acpi/resource.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/acpi/resource.c b/drivers/acpi/resource.c
index 037d1aa103570..d0c92422e2069 100644
--- a/drivers/acpi/resource.c
+++ b/drivers/acpi/resource.c
@@ -435,7 +435,14 @@ static const struct dmi_system_id asus_laptop[] = {
 	{ }
 };
 
-static const struct dmi_system_id lenovo_82ra[] = {
+static const struct dmi_system_id lenovo_laptop[] = {
+	{
+		.ident = "LENOVO IdeaPad Flex 5 14ALC7",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "82R9"),
+		},
+	},
 	{
 		.ident = "LENOVO IdeaPad Flex 5 16ALC7",
 		.matches = {
@@ -469,8 +476,8 @@ struct irq_override_cmp {
 static const struct irq_override_cmp override_table[] = {
 	{ medion_laptop, 1, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_LOW, 0, false },
 	{ asus_laptop, 1, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_LOW, 0, false },
-	{ lenovo_82ra, 6, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_LOW, 0, true },
-	{ lenovo_82ra, 10, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_LOW, 0, true },
+	{ lenovo_laptop, 6, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_LOW, 0, true },
+	{ lenovo_laptop, 10, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_LOW, 0, true },
 	{ schenker_gm_rg, 1, ACPI_EDGE_SENSITIVE, ACPI_ACTIVE_LOW, 1, true },
 };
 
-- 
GitLab


From 7203481fd12b1257938519efb2460ea02b9236ee Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Thu, 15 Dec 2022 10:44:43 +0100
Subject: [PATCH 639/875] ACPI: resource: Add Asus ExpertBook B2502 to Asus
 quirks

The Asus ExpertBook B2502 has the same keyboard issue as Asus Vivobook
K3402ZA/K3502ZA. The kernel overrides IRQ 1 to Edge_High when it
should be Active_Low.

This patch adds the ExpertBook B2502 model to the existing
quirk list of Asus laptops with this issue.

Fixes: b5f9223a105d ("ACPI: resource: Skip IRQ override on Asus Vivobook S5602ZA")
Link: https://bugzilla.redhat.com/show_bug.cgi?id=2142574
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 drivers/acpi/resource.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/acpi/resource.c b/drivers/acpi/resource.c
index d0c92422e2069..16dcd31d124fe 100644
--- a/drivers/acpi/resource.c
+++ b/drivers/acpi/resource.c
@@ -432,6 +432,13 @@ static const struct dmi_system_id asus_laptop[] = {
 			DMI_MATCH(DMI_BOARD_NAME, "S5602ZA"),
 		},
 	},
+	{
+		.ident = "Asus ExpertBook B2502",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+			DMI_MATCH(DMI_BOARD_NAME, "B2502CBA"),
+		},
+	},
 	{ }
 };
 
-- 
GitLab


From 3cf3b7f012f3ea8bdc56196e367cf07c10424855 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Thu, 15 Dec 2022 10:41:38 +0100
Subject: [PATCH 640/875] ACPI: video: Fix Apple GMUX backlight detection

The apple-gmux driver only binds to old GMUX devices which have an
IORESOURCE_IO resource (using inb()/outb()) rather then memory-mapped
IO (IORESOURCE_MEM).

T2 MacBooks use the new style GMUX devices (with IORESOURCE_MEM access),
so these are not supported by the apple-gmux driver. This is not a problem
since they have working ACPI video backlight support.

But the apple_gmux_present() helper only checks if an ACPI device with
the "APP000B" HID is present, causing acpi_video_get_backlight_type()
to return acpi_backlight_apple_gmux disabling the acpi_video backlight
device.

Add a new apple_gmux_backlight_present() helper which checks that
the "APP000B" device actually is an old GMUX device with an IORESOURCE_IO
resource.

This fixes the acpi_video0 backlight no longer registering on T2 MacBooks.

Note people are working to add support for the new style GMUX to Linux:
https://github.com/kekrby/linux-t2/commits/wip/hybrid-graphics

Once this lands this patch should be reverted so that
acpi_video_get_backlight_type() also prefers the gmux on new style GMUX
MacBooks, but for now this is necessary to avoid regressing backlight
control on T2 Macs.

Fixes: 21245df307cb ("ACPI: video: Add Apple GMUX brightness control detection")
Reported-and-tested-by: Aditya Garg <gargaditya08@live.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 drivers/acpi/video_detect.c | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/acpi/video_detect.c b/drivers/acpi/video_detect.c
index a934bbc9dd37c..1b78c74344928 100644
--- a/drivers/acpi/video_detect.c
+++ b/drivers/acpi/video_detect.c
@@ -34,6 +34,7 @@
 #include <linux/module.h>
 #include <linux/pci.h>
 #include <linux/platform_data/x86/nvidia-wmi-ec-backlight.h>
+#include <linux/pnp.h>
 #include <linux/types.h>
 #include <linux/workqueue.h>
 #include <acpi/video.h>
@@ -105,6 +106,26 @@ static bool nvidia_wmi_ec_supported(void)
 }
 #endif
 
+static bool apple_gmux_backlight_present(void)
+{
+	struct acpi_device *adev;
+	struct device *dev;
+
+	adev = acpi_dev_get_first_match_dev(GMUX_ACPI_HID, NULL, -1);
+	if (!adev)
+		return false;
+
+	dev = acpi_get_first_physical_node(adev);
+	if (!dev)
+		return false;
+
+	/*
+	 * drivers/platform/x86/apple-gmux.c only supports old style
+	 * Apple GMUX with an IO-resource.
+	 */
+	return pnp_get_resource(to_pnp_dev(dev), IORESOURCE_IO, 0) != NULL;
+}
+
 /* Force to use vendor driver when the ACPI device is known to be
  * buggy */
 static int video_detect_force_vendor(const struct dmi_system_id *d)
@@ -767,7 +788,7 @@ static enum acpi_backlight_type __acpi_video_get_backlight_type(bool native)
 	if (nvidia_wmi_ec_present)
 		return acpi_backlight_nvidia_wmi_ec;
 
-	if (apple_gmux_present())
+	if (apple_gmux_backlight_present())
 		return acpi_backlight_apple_gmux;
 
 	/* Use ACPI video if available, except when native should be preferred. */
-- 
GitLab


From 3ea45390e9c0d35805ef8357ace55594fd4233d0 Mon Sep 17 00:00:00 2001
From: Mario Limonciello <mario.limonciello@amd.com>
Date: Thu, 15 Dec 2022 13:16:15 -0600
Subject: [PATCH 641/875] ACPI: x86: s2idle: Force AMD GUID/_REV 2 on HP
 Elitebook 865

HP Elitebook 865 supports both the AMD GUID w/ _REV 2 and Microsoft
GUID with _REV 0. Both have very similar code but the AMD GUID
has a special workaround that is specific to a problem with
spurious wakeups on systems with Qualcomm WLAN.

This is believed to be a bug in the Qualcomm WLAN F/W (it doesn't
affect any other WLAN H/W). If this WLAN firmware is fixed this
quirk can be dropped.

Cc: stable@vger.kernel.org # 6.1
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 drivers/acpi/x86/s2idle.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/acpi/x86/s2idle.c b/drivers/acpi/x86/s2idle.c
index 5350c73564b60..422415cb14f46 100644
--- a/drivers/acpi/x86/s2idle.c
+++ b/drivers/acpi/x86/s2idle.c
@@ -401,6 +401,13 @@ static const struct acpi_device_id amd_hid_ids[] = {
 	{}
 };
 
+static int lps0_prefer_amd(const struct dmi_system_id *id)
+{
+	pr_debug("Using AMD GUID w/ _REV 2.\n");
+	rev_id = 2;
+	return 0;
+}
+
 static int lps0_prefer_microsoft(const struct dmi_system_id *id)
 {
 	pr_debug("Preferring Microsoft GUID.\n");
@@ -462,6 +469,19 @@ static const struct dmi_system_id s2idle_dmi_table[] __initconst = {
 			DMI_MATCH(DMI_PRODUCT_NAME, "ROG Flow X16 GV601"),
 		},
 	},
+	{
+		/*
+		 * AMD Rembrandt based HP EliteBook 835/845/865 G9
+		 * Contains specialized AML in AMD/_REV 2 path to avoid
+		 * triggering a bug in Qualcomm WLAN firmware. This may be
+		 * removed in the future if that firmware is fixed.
+		 */
+		.callback = lps0_prefer_amd,
+		.matches = {
+			DMI_MATCH(DMI_BOARD_VENDOR, "HP"),
+			DMI_MATCH(DMI_BOARD_NAME, "8990"),
+		},
+	},
 	{}
 };
 
-- 
GitLab


From e555c85792bd5f9828a2fd2ca9761f70efb1c77b Mon Sep 17 00:00:00 2001
From: Mario Limonciello <mario.limonciello@amd.com>
Date: Thu, 15 Dec 2022 13:16:16 -0600
Subject: [PATCH 642/875] ACPI: x86: s2idle: Stop using AMD specific codepath
 for Rembrandt+

After we introduced a module parameter and quirk infrastructure for
picking the Microsoft GUID over the SOC vendor GUID we discovered
that lots and lots of systems are getting this wrong.

The table continues to grow, and is becoming unwieldy.

We don't really have any benefit to forcing vendors to populate the
AMD GUID. This is just extra work, and more and more vendors seem
to mess it up.  As the Microsoft GUID is used by Windows as well,
it's very likely that it won't be messed up like this.

So drop all the quirks forcing it and the Rembrandt behavior. This
means that Cezanne or later effectively only run the Microsoft GUID
codepath with the exception of HP Elitebook 8*5 G9.

Fixes: fd894f05cf30 ("ACPI: x86: s2idle: If a new AMD _HID is missing assume Rembrandt")
Cc: stable@vger.kernel.org # 6.1
Reported-by: Benjamin Cheng <ben@bcheng.me>
Reported-by: bilkow@tutanota.com
Reported-by: Paul <paul@zogpog.com>
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2292
Link: https://bugzilla.kernel.org/show_bug.cgi?id=216768
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Philipp Zabel <philipp.zabel@gmail.com>
Tested-by: Philipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 drivers/acpi/x86/s2idle.c | 87 ++-------------------------------------
 1 file changed, 3 insertions(+), 84 deletions(-)

diff --git a/drivers/acpi/x86/s2idle.c b/drivers/acpi/x86/s2idle.c
index 422415cb14f46..c7afce465a071 100644
--- a/drivers/acpi/x86/s2idle.c
+++ b/drivers/acpi/x86/s2idle.c
@@ -28,10 +28,6 @@ static bool sleep_no_lps0 __read_mostly;
 module_param(sleep_no_lps0, bool, 0644);
 MODULE_PARM_DESC(sleep_no_lps0, "Do not use the special LPS0 device interface");
 
-static bool prefer_microsoft_dsm_guid __read_mostly;
-module_param(prefer_microsoft_dsm_guid, bool, 0644);
-MODULE_PARM_DESC(prefer_microsoft_dsm_guid, "Prefer using Microsoft GUID in LPS0 device _DSM evaluation");
-
 static const struct acpi_device_id lps0_device_ids[] = {
 	{"PNP0D80", },
 	{"", },
@@ -369,27 +365,15 @@ out:
 }
 
 struct amd_lps0_hid_device_data {
-	const unsigned int rev_id;
 	const bool check_off_by_one;
-	const bool prefer_amd_guid;
 };
 
 static const struct amd_lps0_hid_device_data amd_picasso = {
-	.rev_id = 0,
 	.check_off_by_one = true,
-	.prefer_amd_guid = false,
 };
 
 static const struct amd_lps0_hid_device_data amd_cezanne = {
-	.rev_id = 0,
 	.check_off_by_one = false,
-	.prefer_amd_guid = false,
-};
-
-static const struct amd_lps0_hid_device_data amd_rembrandt = {
-	.rev_id = 2,
-	.check_off_by_one = false,
-	.prefer_amd_guid = true,
 };
 
 static const struct acpi_device_id amd_hid_ids[] = {
@@ -397,7 +381,6 @@ static const struct acpi_device_id amd_hid_ids[] = {
 	{"AMD0005",	(kernel_ulong_t)&amd_picasso,	},
 	{"AMDI0005",	(kernel_ulong_t)&amd_picasso,	},
 	{"AMDI0006",	(kernel_ulong_t)&amd_cezanne,	},
-	{"AMDI0007",	(kernel_ulong_t)&amd_rembrandt,	},
 	{}
 };
 
@@ -407,68 +390,7 @@ static int lps0_prefer_amd(const struct dmi_system_id *id)
 	rev_id = 2;
 	return 0;
 }
-
-static int lps0_prefer_microsoft(const struct dmi_system_id *id)
-{
-	pr_debug("Preferring Microsoft GUID.\n");
-	prefer_microsoft_dsm_guid = true;
-	return 0;
-}
-
 static const struct dmi_system_id s2idle_dmi_table[] __initconst = {
-	{
-		/*
-		 * ASUS TUF Gaming A17 FA707RE
-		 * https://bugzilla.kernel.org/show_bug.cgi?id=216101
-		 */
-		.callback = lps0_prefer_microsoft,
-		.matches = {
-			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
-			DMI_MATCH(DMI_PRODUCT_NAME, "ASUS TUF Gaming A17"),
-		},
-	},
-	{
-		/* ASUS ROG Zephyrus G14 (2022) */
-		.callback = lps0_prefer_microsoft,
-		.matches = {
-			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
-			DMI_MATCH(DMI_PRODUCT_NAME, "ROG Zephyrus G14 GA402"),
-		},
-	},
-	{
-		/*
-		 * Lenovo Yoga Slim 7 Pro X 14ARH7
-		 * https://bugzilla.kernel.org/show_bug.cgi?id=216473 : 82V2
-		 * https://bugzilla.kernel.org/show_bug.cgi?id=216438 : 82TL
-		 */
-		.callback = lps0_prefer_microsoft,
-		.matches = {
-			DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
-			DMI_MATCH(DMI_PRODUCT_NAME, "82"),
-		},
-	},
-	{
-		/*
-		 * ASUSTeK COMPUTER INC. ROG Flow X13 GV301RE_GV301RE
-		 * https://gitlab.freedesktop.org/drm/amd/-/issues/2148
-		 */
-		.callback = lps0_prefer_microsoft,
-		.matches = {
-			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
-			DMI_MATCH(DMI_PRODUCT_NAME, "ROG Flow X13 GV301"),
-		},
-	},
-	{
-		/*
-		 * ASUSTeK COMPUTER INC. ROG Flow X16 GV601RW_GV601RW
-		 * https://gitlab.freedesktop.org/drm/amd/-/issues/2148
-		 */
-		.callback = lps0_prefer_microsoft,
-		.matches = {
-			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
-			DMI_MATCH(DMI_PRODUCT_NAME, "ROG Flow X16 GV601"),
-		},
-	},
 	{
 		/*
 		 * AMD Rembrandt based HP EliteBook 835/845/865 G9
@@ -504,16 +426,14 @@ static int lps0_device_attach(struct acpi_device *adev,
 		if (dev_id->id[0])
 			data = (const struct amd_lps0_hid_device_data *) dev_id->driver_data;
 		else
-			data = &amd_rembrandt;
-		rev_id = data->rev_id;
+			data = &amd_cezanne;
 		lps0_dsm_func_mask = validate_dsm(adev->handle,
 					ACPI_LPS0_DSM_UUID_AMD, rev_id, &lps0_dsm_guid);
 		if (lps0_dsm_func_mask > 0x3 && data->check_off_by_one) {
 			lps0_dsm_func_mask = (lps0_dsm_func_mask << 1) | 0x1;
 			acpi_handle_debug(adev->handle, "_DSM UUID %s: Adjusted function mask: 0x%x\n",
 					  ACPI_LPS0_DSM_UUID_AMD, lps0_dsm_func_mask);
-		} else if (lps0_dsm_func_mask_microsoft > 0 && data->prefer_amd_guid &&
-				!prefer_microsoft_dsm_guid) {
+		} else if (lps0_dsm_func_mask_microsoft > 0 && rev_id) {
 			lps0_dsm_func_mask_microsoft = -EINVAL;
 			acpi_handle_debug(adev->handle, "_DSM Using AMD method\n");
 		}
@@ -521,8 +441,7 @@ static int lps0_device_attach(struct acpi_device *adev,
 		rev_id = 1;
 		lps0_dsm_func_mask = validate_dsm(adev->handle,
 					ACPI_LPS0_DSM_UUID, rev_id, &lps0_dsm_guid);
-		if (!prefer_microsoft_dsm_guid)
-			lps0_dsm_func_mask_microsoft = -EINVAL;
+		lps0_dsm_func_mask_microsoft = -EINVAL;
 	}
 
 	if (lps0_dsm_func_mask < 0 && lps0_dsm_func_mask_microsoft < 0)
-- 
GitLab


From 55171f2930be98c8a49991435cdf3a8b574353b6 Mon Sep 17 00:00:00 2001
From: Anton Protopopov <aspsk@isovalent.com>
Date: Thu, 22 Dec 2022 10:26:27 +0000
Subject: [PATCH 643/875] bpftool: Fix linkage with statically built libllvm

Since the commit eb9d1acf634b ("bpftool: Add LLVM as default library for
disassembling JIT-ed programs") we might link the bpftool program with the
libllvm library. This works fine when a shared libllvm library is available,
but fails if we want to link bpftool with a statically built LLVM:

  [...]
  /usr/bin/ld: /usr/local/lib/libLLVMSupport.a(CrashRecoveryContext.cpp.o): in function `llvm::CrashRecoveryContextCleanup::~CrashRecoveryContextCleanup()':
  CrashRecoveryContext.cpp:(.text._ZN4llvm27CrashRecoveryContextCleanupD0Ev+0x17): undefined reference to `operator delete(void*, unsigned long)'
  /usr/bin/ld: /usr/local/lib/libLLVMSupport.a(CrashRecoveryContext.cpp.o): in function `llvm::CrashRecoveryContext::~CrashRecoveryContext()':
  CrashRecoveryContext.cpp:(.text._ZN4llvm20CrashRecoveryContextD2Ev+0xc8): undefined reference to `operator delete(void*, unsigned long)'
  [...]

So in the case of static libllvm we need to explicitly link bpftool with
required libraries, namely, libstdc++ and those provided by the `llvm-config
--system-libs` command. We can distinguish between the shared and static cases
by using the `llvm-config --shared-mode` command.

Fixes: eb9d1acf634b ("bpftool: Add LLVM as default library for disassembling JIT-ed programs")
Signed-off-by: Anton Protopopov <aspsk@isovalent.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Acked-by: Stanislav Fomichev <sdf@google.com>
Link: https://lore.kernel.org/bpf/20221222102627.1643709-1-aspsk@isovalent.com
---
 tools/bpf/bpftool/Makefile | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/tools/bpf/bpftool/Makefile b/tools/bpf/bpftool/Makefile
index 787b857d3fb5f..f610e184ce02a 100644
--- a/tools/bpf/bpftool/Makefile
+++ b/tools/bpf/bpftool/Makefile
@@ -145,6 +145,10 @@ ifeq ($(feature-llvm),1)
   LLVM_CONFIG_LIB_COMPONENTS := mcdisassembler all-targets
   CFLAGS  += $(shell $(LLVM_CONFIG) --cflags --libs $(LLVM_CONFIG_LIB_COMPONENTS))
   LIBS    += $(shell $(LLVM_CONFIG) --libs $(LLVM_CONFIG_LIB_COMPONENTS))
+  ifeq ($(shell $(LLVM_CONFIG) --shared-mode),static)
+    LIBS += $(shell $(LLVM_CONFIG) --system-libs $(LLVM_CONFIG_LIB_COMPONENTS))
+    LIBS += -lstdc++
+  endif
   LDFLAGS += $(shell $(LLVM_CONFIG) --ldflags)
 else
   # Fall back on libbfd
-- 
GitLab


From 8374bfd5a3c90a5b250f7c087c4d2b8ac467b12e Mon Sep 17 00:00:00 2001
From: Hao Sun <sunhao.th@gmail.com>
Date: Thu, 22 Dec 2022 10:44:13 +0800
Subject: [PATCH 644/875] bpf: fix nullness propagation for reg to reg
 comparisons

After befae75856ab, the verifier would propagate null information after
JEQ/JNE, e.g., if two pointers, one is maybe_null and the other is not,
the former would be marked as non-null in eq path. However, as comment
"PTR_TO_BTF_ID points to a kernel struct that does not need to be null
checked by the BPF program ... The verifier must keep this in mind and
can make no assumptions about null or non-null when doing branch ...".
If one pointer is maybe_null and the other is PTR_TO_BTF, the former is
incorrectly marked non-null. The following BPF prog can trigger a
null-ptr-deref, also see this report for more details[1]:

	0: (18) r1 = map_fd	        ; R1_w=map_ptr(ks=4, vs=4)
	2: (79) r6 = *(u64 *)(r1 +8)    ; R6_w=bpf_map->inner_map_data
					; R6 is PTR_TO_BTF_ID
					; equals to null at runtime
	3: (bf) r2 = r10
	4: (07) r2 += -4
	5: (62) *(u32 *)(r2 +0) = 0
	6: (85) call bpf_map_lookup_elem#1    ; R0_w=map_value_or_null
	7: (1d) if r6 == r0 goto pc+1
	8: (95) exit
	; from 7 to 9: R0=map_value R6=ptr_bpf_map
	9: (61) r0 = *(u32 *)(r0 +0)          ; null-ptr-deref
	10: (95) exit

So, make the verifier propagate nullness information for reg to reg
comparisons only if neither reg is PTR_TO_BTF_ID.

[1] https://lore.kernel.org/bpf/CACkBjsaFJwjC5oiw-1KXvcazywodwXo4zGYsRHwbr2gSG9WcSw@mail.gmail.com/T/#u

Fixes: befae75856ab ("bpf: propagate nullness information for reg to reg comparisons")
Signed-off-by: Hao Sun <sunhao.th@gmail.com>
Acked-by: Yonghong Song <yhs@fb.com>
Link: https://lore.kernel.org/r/20221222024414.29539-1-sunhao.th@gmail.com
Signed-off-by: Martin KaFai Lau <martin.lau@kernel.org>
---
 kernel/bpf/verifier.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c
index a5255a0dcbb68..243d06ce68426 100644
--- a/kernel/bpf/verifier.c
+++ b/kernel/bpf/verifier.c
@@ -11822,10 +11822,17 @@ static int check_cond_jmp_op(struct bpf_verifier_env *env,
 	 *      register B - not null
 	 * for JNE A, B, ... - A is not null in the false branch;
 	 * for JEQ A, B, ... - A is not null in the true branch.
+	 *
+	 * Since PTR_TO_BTF_ID points to a kernel struct that does
+	 * not need to be null checked by the BPF program, i.e.,
+	 * could be null even without PTR_MAYBE_NULL marking, so
+	 * only propagate nullness when neither reg is that type.
 	 */
 	if (!is_jmp32 && BPF_SRC(insn->code) == BPF_X &&
 	    __is_pointer_value(false, src_reg) && __is_pointer_value(false, dst_reg) &&
-	    type_may_be_null(src_reg->type) != type_may_be_null(dst_reg->type)) {
+	    type_may_be_null(src_reg->type) != type_may_be_null(dst_reg->type) &&
+	    base_type(src_reg->type) != PTR_TO_BTF_ID &&
+	    base_type(dst_reg->type) != PTR_TO_BTF_ID) {
 		eq_branch_regs = NULL;
 		switch (opcode) {
 		case BPF_JEQ:
-- 
GitLab


From cedebd74cf3883f0384af9ec26b4e6f8f1964dd4 Mon Sep 17 00:00:00 2001
From: Hao Sun <sunhao.th@gmail.com>
Date: Thu, 22 Dec 2022 10:44:14 +0800
Subject: [PATCH 645/875] selftests/bpf: check null propagation only neither
 reg is PTR_TO_BTF_ID

Verify that nullness information is not porpagated in the branches
of register to register JEQ and JNE operations if one of them is
PTR_TO_BTF_ID. Implement this in C level so we can use CO-RE.

Signed-off-by: Hao Sun <sunhao.th@gmail.com>
Suggested-by: Martin KaFai Lau <martin.lau@kernel.org>
Link: https://lore.kernel.org/r/20221222024414.29539-2-sunhao.th@gmail.com
Signed-off-by: Martin KaFai Lau <martin.lau@kernel.org>
---
 .../bpf/prog_tests/jeq_infer_not_null.c       |  9 ++++
 .../bpf/progs/jeq_infer_not_null_fail.c       | 42 +++++++++++++++++++
 2 files changed, 51 insertions(+)
 create mode 100644 tools/testing/selftests/bpf/prog_tests/jeq_infer_not_null.c
 create mode 100644 tools/testing/selftests/bpf/progs/jeq_infer_not_null_fail.c

diff --git a/tools/testing/selftests/bpf/prog_tests/jeq_infer_not_null.c b/tools/testing/selftests/bpf/prog_tests/jeq_infer_not_null.c
new file mode 100644
index 0000000000000..3add34df57678
--- /dev/null
+++ b/tools/testing/selftests/bpf/prog_tests/jeq_infer_not_null.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <test_progs.h>
+#include "jeq_infer_not_null_fail.skel.h"
+
+void test_jeq_infer_not_null(void)
+{
+	RUN_TESTS(jeq_infer_not_null_fail);
+}
diff --git a/tools/testing/selftests/bpf/progs/jeq_infer_not_null_fail.c b/tools/testing/selftests/bpf/progs/jeq_infer_not_null_fail.c
new file mode 100644
index 0000000000000..f46965053acb2
--- /dev/null
+++ b/tools/testing/selftests/bpf/progs/jeq_infer_not_null_fail.c
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "vmlinux.h"
+#include <bpf/bpf_helpers.h>
+#include "bpf_misc.h"
+
+char _license[] SEC("license") = "GPL";
+
+struct {
+	__uint(type, BPF_MAP_TYPE_HASH);
+	__uint(max_entries, 1);
+	__type(key, u64);
+	__type(value, u64);
+} m_hash SEC(".maps");
+
+SEC("?raw_tp")
+__failure __msg("R8 invalid mem access 'map_value_or_null")
+int jeq_infer_not_null_ptr_to_btfid(void *ctx)
+{
+	struct bpf_map *map = (struct bpf_map *)&m_hash;
+	struct bpf_map *inner_map = map->inner_map_meta;
+	u64 key = 0, ret = 0, *val;
+
+	val = bpf_map_lookup_elem(map, &key);
+	/* Do not mark ptr as non-null if one of them is
+	 * PTR_TO_BTF_ID (R9), reject because of invalid
+	 * access to map value (R8).
+	 *
+	 * Here, we need to inline those insns to access
+	 * R8 directly, since compiler may use other reg
+	 * once it figures out val==inner_map.
+	 */
+	asm volatile("r8 = %[val];\n"
+		     "r9 = %[inner_map];\n"
+		     "if r8 != r9 goto +1;\n"
+		     "%[ret] = *(u64 *)(r8 +0);\n"
+		     : [ret] "+r"(ret)
+		     : [inner_map] "r"(inner_map), [val] "r"(val)
+		     : "r8", "r9");
+
+	return ret;
+}
-- 
GitLab


From 8d8bee13ae9e316443c6666286360126a19c8d94 Mon Sep 17 00:00:00 2001
From: Sean Anderson <sean.anderson@seco.com>
Date: Fri, 16 Dec 2022 12:29:37 -0500
Subject: [PATCH 646/875] powerpc: dts: t208x: Disable 10G on MAC1 and MAC2

There aren't enough resources to run these ports at 10G speeds. Disable
10G for these ports, reverting to the previous speed.

Fixes: 36926a7d70c2 ("powerpc: dts: t208x: Mark MAC1 and MAC2 as 10G")
Reported-by: Camelia Alexandra Groza <camelia.groza@nxp.com>
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Camelia Groza <camelia.groza@nxp.com>
Tested-by: Camelia Groza <camelia.groza@nxp.com>
Link: https://lore.kernel.org/r/20221216172937.2960054-1-sean.anderson@seco.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
index 74e17e134387d..27714dc2f04a5 100644
--- a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
@@ -659,3 +659,19 @@
 		interrupts = <16 2 1 9>;
 	};
 };
+
+&fman0_rx_0x08 {
+	/delete-property/ fsl,fman-10g-port;
+};
+
+&fman0_tx_0x28 {
+	/delete-property/ fsl,fman-10g-port;
+};
+
+&fman0_rx_0x09 {
+	/delete-property/ fsl,fman-10g-port;
+};
+
+&fman0_tx_0x29 {
+	/delete-property/ fsl,fman-10g-port;
+};
-- 
GitLab


From 7fac54b93ad13e5e7ac237af33eb2a0940eaeea0 Mon Sep 17 00:00:00 2001
From: Rong Tao <rongtao@cestc.cn>
Date: Wed, 21 Dec 2022 20:36:27 +0800
Subject: [PATCH 647/875] atm: uapi: fix spelling typos in comments

Fix the typo of 'Unsuported' in atmbr2684.h

Signed-off-by: Rong Tao <rongtao@cestc.cn>
Link: https://lore.kernel.org/r/tencent_F1354BEC925C65EA357E741E91DF2044E805@qq.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 include/uapi/linux/atmbr2684.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/uapi/linux/atmbr2684.h b/include/uapi/linux/atmbr2684.h
index a9e2250cd7205..d47c47d06f110 100644
--- a/include/uapi/linux/atmbr2684.h
+++ b/include/uapi/linux/atmbr2684.h
@@ -38,7 +38,7 @@
  */
 #define BR2684_ENCAPS_VC	(0)	/* VC-mux */
 #define BR2684_ENCAPS_LLC	(1)
-#define BR2684_ENCAPS_AUTODETECT (2)	/* Unsuported */
+#define BR2684_ENCAPS_AUTODETECT (2)	/* Unsupported */
 
 /*
  * Is this VC bridged or routed?
-- 
GitLab


From 343190841a1f22b96996d9f8cfab902a4d1bfd0e Mon Sep 17 00:00:00 2001
From: Jens Axboe <axboe@kernel.dk>
Date: Fri, 23 Dec 2022 06:37:08 -0700
Subject: [PATCH 648/875] io_uring: check for valid register opcode earlier

We only check the register opcode value inside the restricted ring
section, move it into the main io_uring_register() function instead
and check it up front.

Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 io_uring/io_uring.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/io_uring/io_uring.c b/io_uring/io_uring.c
index ac5d39eeb3d1e..58ac13b69dc8d 100644
--- a/io_uring/io_uring.c
+++ b/io_uring/io_uring.c
@@ -4020,8 +4020,6 @@ static int __io_uring_register(struct io_ring_ctx *ctx, unsigned opcode,
 		return -EEXIST;
 
 	if (ctx->restricted) {
-		if (opcode >= IORING_REGISTER_LAST)
-			return -EINVAL;
 		opcode = array_index_nospec(opcode, IORING_REGISTER_LAST);
 		if (!test_bit(opcode, ctx->restrictions.register_op))
 			return -EACCES;
@@ -4177,6 +4175,9 @@ SYSCALL_DEFINE4(io_uring_register, unsigned int, fd, unsigned int, opcode,
 	long ret = -EBADF;
 	struct fd f;
 
+	if (opcode >= IORING_REGISTER_LAST)
+		return -EINVAL;
+
 	f = fdget(fd);
 	if (!f.file)
 		return -EBADF;
-- 
GitLab


From 55c590adfe18b5380f7c4ae3696468bc5c916ee5 Mon Sep 17 00:00:00 2001
From: Like Xu <likexu@tencent.com>
Date: Wed, 7 Dec 2022 15:15:05 +0800
Subject: [PATCH 649/875] KVM: x86/pmu: Prevent zero period event from being
 repeatedly released

The current vPMU can reuse the same pmc->perf_event for the same
hardware event via pmc_pause/resume_counter(), but this optimization
does not apply to a portion of the TSX events (e.g., "event=0x3c,in_tx=1,
in_tx_cp=1"), where event->attr.sample_period is legally zero at creation,
thus making the perf call to perf_event_period() meaningless (no need to
adjust sample period in this case), and instead causing such reusable
perf_events to be repeatedly released and created.

Avoid releasing zero sample_period events by checking is_sampling_event()
to follow the previously enable/disable optimization.

Signed-off-by: Like Xu <likexu@tencent.com>
Message-Id: <20221207071506.15733-2-likexu@tencent.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/pmu.c | 3 ++-
 arch/x86/kvm/pmu.h | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c
index 684393c221052..eb594620dd75a 100644
--- a/arch/x86/kvm/pmu.c
+++ b/arch/x86/kvm/pmu.c
@@ -238,7 +238,8 @@ static bool pmc_resume_counter(struct kvm_pmc *pmc)
 		return false;
 
 	/* recalibrate sample period and check if it's accepted by perf core */
-	if (perf_event_period(pmc->perf_event,
+	if (is_sampling_event(pmc->perf_event) &&
+	    perf_event_period(pmc->perf_event,
 			      get_sample_period(pmc, pmc->counter)))
 		return false;
 
diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h
index 85ff3c0588bac..cdb91009701dd 100644
--- a/arch/x86/kvm/pmu.h
+++ b/arch/x86/kvm/pmu.h
@@ -140,7 +140,8 @@ static inline u64 get_sample_period(struct kvm_pmc *pmc, u64 counter_value)
 
 static inline void pmc_update_sample_period(struct kvm_pmc *pmc)
 {
-	if (!pmc->perf_event || pmc->is_paused)
+	if (!pmc->perf_event || pmc->is_paused ||
+	    !is_sampling_event(pmc->perf_event))
 		return;
 
 	perf_event_period(pmc->perf_event,
-- 
GitLab


From fceb3a36c29a957515d5156e5e7844ea040dc43d Mon Sep 17 00:00:00 2001
From: Adamos Ttofari <attofari@amazon.de>
Date: Thu, 8 Dec 2022 09:44:14 +0000
Subject: [PATCH 650/875] KVM: x86: ioapic: Fix level-triggered EOI and
 userspace I/OAPIC reconfigure race

When scanning userspace I/OAPIC entries, intercept EOI for level-triggered
IRQs if the current vCPU has a pending and/or in-service IRQ for the
vector in its local API, even if the vCPU doesn't match the new entry's
destination.  This fixes a race between userspace I/OAPIC reconfiguration
and IRQ delivery that results in the vector's bit being left set in the
remote IRR due to the eventual EOI not being forwarded to the userspace
I/OAPIC.

Commit 0fc5a36dd6b3 ("KVM: x86: ioapic: Fix level-triggered EOI and IOAPIC
reconfigure race") fixed the in-kernel IOAPIC, but not the userspace
IOAPIC configuration, which has a similar race.

Fixes: 0fc5a36dd6b3 ("KVM: x86: ioapic: Fix level-triggered EOI and IOAPIC reconfigure race")

Signed-off-by: Adamos Ttofari <attofari@amazon.de>
Reviewed-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20221208094415.12723-1-attofari@amazon.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/irq_comm.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kvm/irq_comm.c b/arch/x86/kvm/irq_comm.c
index 0687162c4f227..3742d9adacfc1 100644
--- a/arch/x86/kvm/irq_comm.c
+++ b/arch/x86/kvm/irq_comm.c
@@ -426,8 +426,9 @@ void kvm_scan_ioapic_routes(struct kvm_vcpu *vcpu,
 			kvm_set_msi_irq(vcpu->kvm, entry, &irq);
 
 			if (irq.trig_mode &&
-			    kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT,
-						irq.dest_id, irq.dest_mode))
+			    (kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT,
+						 irq.dest_id, irq.dest_mode) ||
+			     kvm_apic_pending_eoi(vcpu, irq.vector)))
 				__set_bit(irq.vector, ioapic_handled_vectors);
 		}
 	}
-- 
GitLab


From 8b9e13d2de73b5513c2ceffe0f62eab40206a126 Mon Sep 17 00:00:00 2001
From: Vitaly Kuznetsov <vkuznets@redhat.com>
Date: Thu, 8 Dec 2022 11:27:00 +0100
Subject: [PATCH 651/875] KVM: x86: hyper-v: Fix 'using uninitialized value'
 Coverity warning

In kvm_hv_flush_tlb(), 'data_offset' and 'consumed_xmm_halves' variables
are used in a mutually exclusive way: in 'hc->fast' we count in 'XMM
halves' and increase 'data_offset' otherwise. Coverity discovered, that in
one case both variables are incremented unconditionally. This doesn't seem
to cause any issues as the only user of 'data_offset'/'consumed_xmm_halves'
data is kvm_hv_get_tlb_flush_entries() -> kvm_hv_get_hc_data() which also
takes into account 'hc->fast' but is still worth fixing.

To make things explicit, put 'data_offset' and 'consumed_xmm_halves' to
'struct kvm_hv_hcall' as a union and use at call sites. This allows to
remove explicit 'data_offset'/'consumed_xmm_halves' parameters from
kvm_hv_get_hc_data()/kvm_get_sparse_vp_set()/kvm_hv_get_tlb_flush_entries()
helpers.

Note: 'struct kvm_hv_hcall' is allocated on stack in kvm_hv_hypercall() and
is not zeroed, consumers are supposed to initialize the appropriate field
if needed.

Reported-by: coverity-bot <keescook+coverity-bot@chromium.org>
Addresses-Coverity-ID: 1527764 ("Uninitialized variables")
Fixes: 260970862c88 ("KVM: x86: hyper-v: Handle HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST{,EX} calls gently")
Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Reviewed-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20221208102700.959630-1-vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/hyperv.c | 63 ++++++++++++++++++++++++-------------------
 1 file changed, 36 insertions(+), 27 deletions(-)

diff --git a/arch/x86/kvm/hyperv.c b/arch/x86/kvm/hyperv.c
index 2c7f2a26421e8..e8296942a8682 100644
--- a/arch/x86/kvm/hyperv.c
+++ b/arch/x86/kvm/hyperv.c
@@ -1769,6 +1769,7 @@ static bool hv_is_vp_in_sparse_set(u32 vp_id, u64 valid_bank_mask, u64 sparse_ba
 }
 
 struct kvm_hv_hcall {
+	/* Hypercall input data */
 	u64 param;
 	u64 ingpa;
 	u64 outgpa;
@@ -1779,12 +1780,21 @@ struct kvm_hv_hcall {
 	bool fast;
 	bool rep;
 	sse128_t xmm[HV_HYPERCALL_MAX_XMM_REGISTERS];
+
+	/*
+	 * Current read offset when KVM reads hypercall input data gradually,
+	 * either offset in bytes from 'ingpa' for regular hypercalls or the
+	 * number of already consumed 'XMM halves' for 'fast' hypercalls.
+	 */
+	union {
+		gpa_t data_offset;
+		int consumed_xmm_halves;
+	};
 };
 
 
 static int kvm_hv_get_hc_data(struct kvm *kvm, struct kvm_hv_hcall *hc,
-			      u16 orig_cnt, u16 cnt_cap, u64 *data,
-			      int consumed_xmm_halves, gpa_t offset)
+			      u16 orig_cnt, u16 cnt_cap, u64 *data)
 {
 	/*
 	 * Preserve the original count when ignoring entries via a "cap", KVM
@@ -1799,11 +1809,11 @@ static int kvm_hv_get_hc_data(struct kvm *kvm, struct kvm_hv_hcall *hc,
 		 * Each XMM holds two sparse banks, but do not count halves that
 		 * have already been consumed for hypercall parameters.
 		 */
-		if (orig_cnt > 2 * HV_HYPERCALL_MAX_XMM_REGISTERS - consumed_xmm_halves)
+		if (orig_cnt > 2 * HV_HYPERCALL_MAX_XMM_REGISTERS - hc->consumed_xmm_halves)
 			return HV_STATUS_INVALID_HYPERCALL_INPUT;
 
 		for (i = 0; i < cnt; i++) {
-			j = i + consumed_xmm_halves;
+			j = i + hc->consumed_xmm_halves;
 			if (j % 2)
 				data[i] = sse128_hi(hc->xmm[j / 2]);
 			else
@@ -1812,27 +1822,24 @@ static int kvm_hv_get_hc_data(struct kvm *kvm, struct kvm_hv_hcall *hc,
 		return 0;
 	}
 
-	return kvm_read_guest(kvm, hc->ingpa + offset, data,
+	return kvm_read_guest(kvm, hc->ingpa + hc->data_offset, data,
 			      cnt * sizeof(*data));
 }
 
 static u64 kvm_get_sparse_vp_set(struct kvm *kvm, struct kvm_hv_hcall *hc,
-				 u64 *sparse_banks, int consumed_xmm_halves,
-				 gpa_t offset)
+				 u64 *sparse_banks)
 {
 	if (hc->var_cnt > HV_MAX_SPARSE_VCPU_BANKS)
 		return -EINVAL;
 
 	/* Cap var_cnt to ignore banks that cannot contain a legal VP index. */
 	return kvm_hv_get_hc_data(kvm, hc, hc->var_cnt, KVM_HV_MAX_SPARSE_VCPU_SET_BITS,
-				  sparse_banks, consumed_xmm_halves, offset);
+				  sparse_banks);
 }
 
-static int kvm_hv_get_tlb_flush_entries(struct kvm *kvm, struct kvm_hv_hcall *hc, u64 entries[],
-					int consumed_xmm_halves, gpa_t offset)
+static int kvm_hv_get_tlb_flush_entries(struct kvm *kvm, struct kvm_hv_hcall *hc, u64 entries[])
 {
-	return kvm_hv_get_hc_data(kvm, hc, hc->rep_cnt, hc->rep_cnt,
-				  entries, consumed_xmm_halves, offset);
+	return kvm_hv_get_hc_data(kvm, hc, hc->rep_cnt, hc->rep_cnt, entries);
 }
 
 static void hv_tlb_flush_enqueue(struct kvm_vcpu *vcpu,
@@ -1926,8 +1933,6 @@ static u64 kvm_hv_flush_tlb(struct kvm_vcpu *vcpu, struct kvm_hv_hcall *hc)
 	struct kvm_vcpu *v;
 	unsigned long i;
 	bool all_cpus;
-	int consumed_xmm_halves = 0;
-	gpa_t data_offset;
 
 	/*
 	 * The Hyper-V TLFS doesn't allow more than HV_MAX_SPARSE_VCPU_BANKS
@@ -1955,12 +1960,12 @@ static u64 kvm_hv_flush_tlb(struct kvm_vcpu *vcpu, struct kvm_hv_hcall *hc)
 			flush.address_space = hc->ingpa;
 			flush.flags = hc->outgpa;
 			flush.processor_mask = sse128_lo(hc->xmm[0]);
-			consumed_xmm_halves = 1;
+			hc->consumed_xmm_halves = 1;
 		} else {
 			if (unlikely(kvm_read_guest(kvm, hc->ingpa,
 						    &flush, sizeof(flush))))
 				return HV_STATUS_INVALID_HYPERCALL_INPUT;
-			data_offset = sizeof(flush);
+			hc->data_offset = sizeof(flush);
 		}
 
 		trace_kvm_hv_flush_tlb(flush.processor_mask,
@@ -1985,12 +1990,12 @@ static u64 kvm_hv_flush_tlb(struct kvm_vcpu *vcpu, struct kvm_hv_hcall *hc)
 			flush_ex.flags = hc->outgpa;
 			memcpy(&flush_ex.hv_vp_set,
 			       &hc->xmm[0], sizeof(hc->xmm[0]));
-			consumed_xmm_halves = 2;
+			hc->consumed_xmm_halves = 2;
 		} else {
 			if (unlikely(kvm_read_guest(kvm, hc->ingpa, &flush_ex,
 						    sizeof(flush_ex))))
 				return HV_STATUS_INVALID_HYPERCALL_INPUT;
-			data_offset = sizeof(flush_ex);
+			hc->data_offset = sizeof(flush_ex);
 		}
 
 		trace_kvm_hv_flush_tlb_ex(flush_ex.hv_vp_set.valid_bank_mask,
@@ -2009,8 +2014,7 @@ static u64 kvm_hv_flush_tlb(struct kvm_vcpu *vcpu, struct kvm_hv_hcall *hc)
 			if (!hc->var_cnt)
 				goto ret_success;
 
-			if (kvm_get_sparse_vp_set(kvm, hc, sparse_banks,
-						  consumed_xmm_halves, data_offset))
+			if (kvm_get_sparse_vp_set(kvm, hc, sparse_banks))
 				return HV_STATUS_INVALID_HYPERCALL_INPUT;
 		}
 
@@ -2021,8 +2025,10 @@ static u64 kvm_hv_flush_tlb(struct kvm_vcpu *vcpu, struct kvm_hv_hcall *hc)
 		 * consumed_xmm_halves to make sure TLB flush entries are read
 		 * from the correct offset.
 		 */
-		data_offset += hc->var_cnt * sizeof(sparse_banks[0]);
-		consumed_xmm_halves += hc->var_cnt;
+		if (hc->fast)
+			hc->consumed_xmm_halves += hc->var_cnt;
+		else
+			hc->data_offset += hc->var_cnt * sizeof(sparse_banks[0]);
 	}
 
 	if (hc->code == HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE ||
@@ -2030,8 +2036,7 @@ static u64 kvm_hv_flush_tlb(struct kvm_vcpu *vcpu, struct kvm_hv_hcall *hc)
 	    hc->rep_cnt > ARRAY_SIZE(__tlb_flush_entries)) {
 		tlb_flush_entries = NULL;
 	} else {
-		if (kvm_hv_get_tlb_flush_entries(kvm, hc, __tlb_flush_entries,
-						consumed_xmm_halves, data_offset))
+		if (kvm_hv_get_tlb_flush_entries(kvm, hc, __tlb_flush_entries))
 			return HV_STATUS_INVALID_HYPERCALL_INPUT;
 		tlb_flush_entries = __tlb_flush_entries;
 	}
@@ -2180,9 +2185,13 @@ static u64 kvm_hv_send_ipi(struct kvm_vcpu *vcpu, struct kvm_hv_hcall *hc)
 		if (!hc->var_cnt)
 			goto ret_success;
 
-		if (kvm_get_sparse_vp_set(kvm, hc, sparse_banks, 1,
-					  offsetof(struct hv_send_ipi_ex,
-						   vp_set.bank_contents)))
+		if (!hc->fast)
+			hc->data_offset = offsetof(struct hv_send_ipi_ex,
+						   vp_set.bank_contents);
+		else
+			hc->consumed_xmm_halves = 1;
+
+		if (kvm_get_sparse_vp_set(kvm, hc, sparse_banks))
 			return HV_STATUS_INVALID_HYPERCALL_INPUT;
 	}
 
-- 
GitLab


From 3c649918b764c0aaef22ea65d514bac5e2324ec0 Mon Sep 17 00:00:00 2001
From: Peng Hao <flyingpeng@tencent.com>
Date: Tue, 6 Dec 2022 17:20:15 +0800
Subject: [PATCH 652/875] KVM: x86: Simplify kvm_apic_hw_enabled

kvm_apic_hw_enabled() only needs to return bool, there is no place
to use the return value of MSR_IA32_APICBASE_ENABLE.

Signed-off-by: Peng Hao <flyingpeng@tencent.com>
Message-Id: <CAPm50aJ=BLXNWT11+j36Dd6d7nz2JmOBk4u7o_NPQ0N61ODu1g@mail.gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/lapic.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
index 28e3769066e21..58c3242fcc7ad 100644
--- a/arch/x86/kvm/lapic.h
+++ b/arch/x86/kvm/lapic.h
@@ -188,11 +188,11 @@ static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
 
 extern struct static_key_false_deferred apic_hw_disabled;
 
-static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic)
+static inline bool kvm_apic_hw_enabled(struct kvm_lapic *apic)
 {
 	if (static_branch_unlikely(&apic_hw_disabled.key))
 		return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
-	return MSR_IA32_APICBASE_ENABLE;
+	return true;
 }
 
 extern struct static_key_false_deferred apic_sw_disabled;
-- 
GitLab


From 77b1908e10eccf34310ffd95b0b455c01aa76286 Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@google.com>
Date: Tue, 20 Dec 2022 15:34:27 +0000
Subject: [PATCH 653/875] KVM: x86: Sanity check inputs to
 kvm_handle_memory_failure()

Add a sanity check in kvm_handle_memory_failure() to assert that a valid
x86_exception structure is provided if the memory "failure" wants to
propagate a fault into the guest.  If a memory failure happens during a
direct guest physical memory access, e.g. for nested VMX, KVM hardcodes
the failure to X86EMUL_IO_NEEDED and doesn't provide an exception pointer
(because the exception struct would just be filled with garbage).

Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20221220153427.514032-1-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/x86.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index fd6c01a393128..5c3ce39cdccbf 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -13132,6 +13132,9 @@ int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
 			      struct x86_exception *e)
 {
 	if (r == X86EMUL_PROPAGATE_FAULT) {
+		if (KVM_BUG_ON(!e, vcpu->kvm))
+			return -EIO;
+
 		kvm_inject_emulated_page_fault(vcpu, e);
 		return 1;
 	}
-- 
GitLab


From 53800f88d414525d3fdc5c84629faa0b6bc35b3b Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@google.com>
Date: Mon, 19 Dec 2022 22:04:16 +0000
Subject: [PATCH 654/875] KVM: selftests: Zero out valid_bank_mask for "all"
 case in Hyper-V IPI test

Zero out the valid_bank_mask when using the fast variant of
HVCALL_SEND_IPI_EX to send IPIs to all vCPUs.  KVM requires the "var_cnt"
and "valid_bank_mask" inputs to be consistent even when targeting all
vCPUs.  See commit bd1ba5732bb9 ("KVM: x86: Get the number of Hyper-V
sparse banks from the VARHEAD field").

Fixes: 998489245d84 ("KVM: selftests: Hyper-V PV IPI selftest")
Cc: Vitaly Kuznetsov <vkuznets@redhat.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20221219220416.395329-1-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/x86_64/hyperv_ipi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/tools/testing/selftests/kvm/x86_64/hyperv_ipi.c b/tools/testing/selftests/kvm/x86_64/hyperv_ipi.c
index 8b791eac7d5a3..0cbb0e646ef8d 100644
--- a/tools/testing/selftests/kvm/x86_64/hyperv_ipi.c
+++ b/tools/testing/selftests/kvm/x86_64/hyperv_ipi.c
@@ -193,8 +193,9 @@ static void sender_guest_code(void *hcall_page, vm_vaddr_t pgs_gpa)
 	GUEST_SYNC(stage++);
 	/*
 	 * 'XMM Fast' HvCallSendSyntheticClusterIpiEx to HV_GENERIC_SET_ALL.
-	 * Nothing to write anything to XMM regs.
 	 */
+	ipi_ex->vp_set.valid_bank_mask = 0;
+	hyperv_write_xmm_input(&ipi_ex->vp_set.valid_bank_mask, 2);
 	hyperv_hypercall(HVCALL_SEND_IPI_EX | HV_HYPERCALL_FAST_BIT,
 			 IPI_VECTOR, HV_GENERIC_SET_ALL);
 	nop_loop();
-- 
GitLab


From 057b18756b464729bc787ed4e6b44abb9f5c3a38 Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@google.com>
Date: Tue, 20 Dec 2022 15:42:24 +0000
Subject: [PATCH 655/875] KVM: nVMX: Document that ignoring memory failures for
 VMCLEAR is deliberate

Explicitly drop the result of kvm_vcpu_write_guest() when writing the
"launch state" as part of VMCLEAR emulation, and add a comment to call
out that KVM's behavior is architecturally valid.  Intel's pseudocode
effectively says that VMCLEAR is a nop if the target VMCS address isn't
in memory, e.g. if the address points at MMIO.

Add a FIXME to call out that suppressing failures on __copy_to_user() is
wrong, as memory (a memslot) does exist in that case.  Punt the issue to
the future as open coding kvm_vcpu_write_guest() just to make sure the
guest dies with -EFAULT isn't worth the extra complexity.  The flaw will
need to be addressed if KVM ever does something intelligent on uaccess
failures, e.g. to support post-copy demand paging, but in that case KVM
will need a more thorough overhaul, i.e. VMCLEAR shouldn't need to open
code a core KVM helper.

No functional change intended.

Reported-by: coverity-bot <keescook+coverity-bot@chromium.org>
Addresses-Coverity-ID: 1527765 ("Error handling issues")
Fixes: 587d7e72aedc ("kvm: nVMX: VMCLEAR should not cause the vCPU to shut down")
Cc: Jim Mattson <jmattson@google.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20221220154224.526568-1-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/vmx/nested.c | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index b6f4411b613e9..f18f3a9f09435 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -5296,10 +5296,19 @@ static int handle_vmclear(struct kvm_vcpu *vcpu)
 		if (vmptr == vmx->nested.current_vmptr)
 			nested_release_vmcs12(vcpu);
 
-		kvm_vcpu_write_guest(vcpu,
-				     vmptr + offsetof(struct vmcs12,
-						      launch_state),
-				     &zero, sizeof(zero));
+		/*
+		 * Silently ignore memory errors on VMCLEAR, Intel's pseudocode
+		 * for VMCLEAR includes a "ensure that data for VMCS referenced
+		 * by the operand is in memory" clause that guards writes to
+		 * memory, i.e. doing nothing for I/O is architecturally valid.
+		 *
+		 * FIXME: Suppress failures if and only if no memslot is found,
+		 * i.e. exit to userspace if __copy_to_user() fails.
+		 */
+		(void)kvm_vcpu_write_guest(vcpu,
+					   vmptr + offsetof(struct vmcs12,
+							    launch_state),
+					   &zero, sizeof(zero));
 	} else if (vmx->nested.hv_evmcs && vmptr == vmx->nested.hv_evmcs_vmptr) {
 		nested_release_evmcs(vcpu);
 	}
-- 
GitLab


From 31de69f4eea77b28a9724b3fa55aae104fc91fc7 Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@google.com>
Date: Tue, 13 Dec 2022 06:23:03 +0000
Subject: [PATCH 656/875] KVM: nVMX: Properly expose ENABLE_USR_WAIT_PAUSE
 control to L1

Set ENABLE_USR_WAIT_PAUSE in KVM's supported VMX MSR configuration if the
feature is supported in hardware and enabled in KVM's base, non-nested
configuration, i.e. expose ENABLE_USR_WAIT_PAUSE to L1 if it's supported.
This fixes a bug where saving/restoring, i.e. migrating, a vCPU will fail
if WAITPKG (the associated CPUID feature) is enabled for the vCPU, and
obviously allows L1 to enable the feature for L2.

KVM already effectively exposes ENABLE_USR_WAIT_PAUSE to L1 by stuffing
the allowed-1 control ina vCPU's virtual MSR_IA32_VMX_PROCBASED_CTLS2 when
updating secondary controls in response to KVM_SET_CPUID(2), but (a) that
depends on flawed code (KVM shouldn't touch VMX MSRs in response to CPUID
updates) and (b) runs afoul of vmx_restore_control_msr()'s restriction
that the guest value must be a strict subset of the supported host value.

Although no past commit explicitly enabled nested support for WAITPKG,
doing so is safe and functionally correct from an architectural
perspective as no additional KVM support is needed to virtualize TPAUSE,
UMONITOR, and UMWAIT for L2 relative to L1, and KVM already forwards
VM-Exits to L1 as necessary (commit bf653b78f960, "KVM: vmx: Introduce
handle_unexpected_vmexit and handle WAITPKG vmexit").

Note, KVM always keeps the hosts MSR_IA32_UMWAIT_CONTROL resident in
hardware, i.e. always runs both L1 and L2 with the host's power management
settings for TPAUSE and UMWAIT.  See commit bf09fb6cba4f ("KVM: VMX: Stop
context switching MSR_IA32_UMWAIT_CONTROL") for more details.

Fixes: e69e72faa3a0 ("KVM: x86: Add support for user wait instructions")
Cc: stable@vger.kernel.org
Reported-by: Aaron Lewis <aaronlewis@google.com>
Reported-by: Yu Zhang <yu.c.zhang@linux.intel.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Reviewed-by: Jim Mattson <jmattson@google.com>
Message-Id: <20221213062306.667649-2-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/vmx/nested.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index f18f3a9f09435..d93c715cda6ab 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -6882,7 +6882,8 @@ void nested_vmx_setup_ctls_msrs(struct vmcs_config *vmcs_conf, u32 ept_caps)
 		SECONDARY_EXEC_ENABLE_INVPCID |
 		SECONDARY_EXEC_RDSEED_EXITING |
 		SECONDARY_EXEC_XSAVES |
-		SECONDARY_EXEC_TSC_SCALING;
+		SECONDARY_EXEC_TSC_SCALING |
+		SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
 
 	/*
 	 * We can emulate "VMCS shadowing," even if the hardware
-- 
GitLab


From a0860d68a25dee4e51e7d3e067a66ca765776fe8 Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@google.com>
Date: Tue, 13 Dec 2022 06:23:04 +0000
Subject: [PATCH 657/875] KVM: nVMX: Don't stuff secondary execution control if
 it's not supported

When stuffing the allowed secondary execution controls for nested VMX in
response to CPUID updates, don't set the allowed-1 bit for a feature that
isn't supported by KVM, i.e. isn't allowed by the canonical vmcs_config.

WARN if KVM attempts to manipulate a feature that isn't supported.  All
features that are currently stuffed are always advertised to L1 for
nested VMX if they are supported in KVM's base configuration, and no
additional features should ever be added to the CPUID-induced stuffing
(updating VMX MSRs in response to CPUID updates is a long-standing KVM
flaw that is slowly being fixed).

Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20221213062306.667649-3-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/vmx/vmx.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index fe5615fd8295c..fc9008dbed334 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -4459,6 +4459,13 @@ vmx_adjust_secondary_exec_control(struct vcpu_vmx *vmx, u32 *exec_control,
 	 * controls for features that are/aren't exposed to the guest.
 	 */
 	if (nested) {
+		/*
+		 * All features that can be added or removed to VMX MSRs must
+		 * be supported in the first place for nested virtualization.
+		 */
+		if (WARN_ON_ONCE(!(vmcs_config.nested.secondary_ctls_high & control)))
+			enabled = false;
+
 		if (enabled)
 			vmx->nested.msrs.secondary_ctls_high |= control;
 		else
-- 
GitLab


From f5d16bb9be68b20c78fc3d93fa243eb1f0b9fa53 Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@google.com>
Date: Tue, 13 Dec 2022 03:30:26 +0000
Subject: [PATCH 658/875] KVM: x86/mmu: Don't attempt to map leaf if target TDP
 MMU SPTE is frozen

Hoist the is_removed_spte() check above the "level == goal_level" check
when walking SPTEs during a TDP MMU page fault to avoid attempting to map
a leaf entry if said entry is frozen by a different task/vCPU.

  ------------[ cut here ]------------
  WARNING: CPU: 3 PID: 939 at arch/x86/kvm/mmu/tdp_mmu.c:653 kvm_tdp_mmu_map+0x269/0x4b0
  Modules linked in: kvm_intel
  CPU: 3 PID: 939 Comm: nx_huge_pages_t Not tainted 6.1.0-rc4+ #67
  Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS 0.0.0 02/06/2015
  RIP: 0010:kvm_tdp_mmu_map+0x269/0x4b0
  RSP: 0018:ffffc9000068fba8 EFLAGS: 00010246
  RAX: 00000000000005a0 RBX: ffffc9000068fcc0 RCX: 0000000000000005
  RDX: ffff88810741f000 RSI: ffff888107f04600 RDI: ffffc900006a3000
  RBP: 060000010b000bf3 R08: 0000000000000000 R09: 0000000000000000
  R10: 0000000000000000 R11: 000ffffffffff000 R12: 0000000000000005
  R13: ffff888113670000 R14: ffff888107464958 R15: 0000000000000000
  FS:  00007f01c942c740(0000) GS:ffff888277cc0000(0000) knlGS:0000000000000000
  CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
  CR2: 0000000000000000 CR3: 0000000117013006 CR4: 0000000000172ea0
  Call Trace:
   <TASK>
   kvm_tdp_page_fault+0x10c/0x130
   kvm_mmu_page_fault+0x103/0x680
   vmx_handle_exit+0x132/0x5a0 [kvm_intel]
   vcpu_enter_guest+0x60c/0x16f0
   kvm_arch_vcpu_ioctl_run+0x1e2/0x9d0
   kvm_vcpu_ioctl+0x271/0x660
   __x64_sys_ioctl+0x80/0xb0
   do_syscall_64+0x2b/0x50
   entry_SYSCALL_64_after_hwframe+0x46/0xb0
   </TASK>
  ---[ end trace 0000000000000000 ]---

Fixes: 63d28a25e04c ("KVM: x86/mmu: simplify kvm_tdp_mmu_map flow when guest has to retry")
Cc: Robert Hoo <robert.hu@linux.intel.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Reviewed-by: Robert Hoo <robert.hu@linux.intel.com>
Message-Id: <20221213033030.83345-2-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/mmu/tdp_mmu.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kvm/mmu/tdp_mmu.c b/arch/x86/kvm/mmu/tdp_mmu.c
index 771210ce51811..84b0b225fe5f5 100644
--- a/arch/x86/kvm/mmu/tdp_mmu.c
+++ b/arch/x86/kvm/mmu/tdp_mmu.c
@@ -1173,9 +1173,6 @@ int kvm_tdp_mmu_map(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault)
 		if (fault->nx_huge_page_workaround_enabled)
 			disallowed_hugepage_adjust(fault, iter.old_spte, iter.level);
 
-		if (iter.level == fault->goal_level)
-			break;
-
 		/*
 		 * If SPTE has been frozen by another thread, just give up and
 		 * retry, avoiding unnecessary page table allocation and free.
@@ -1183,6 +1180,9 @@ int kvm_tdp_mmu_map(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault)
 		if (is_removed_spte(iter.old_spte))
 			goto retry;
 
+		if (iter.level == fault->goal_level)
+			break;
+
 		/* Step down into the lower level page table if it exists. */
 		if (is_shadow_present_pte(iter.old_spte) &&
 		    !is_large_pte(iter.old_spte))
-- 
GitLab


From 80a3e4ae962de33ff6a94e798c80e56e1fed4d10 Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@google.com>
Date: Tue, 13 Dec 2022 03:30:27 +0000
Subject: [PATCH 659/875] KVM: x86/mmu: Map TDP MMU leaf SPTE iff target level
 is reached

Map the leaf SPTE when handling a TDP MMU page fault if and only if the
target level is reached.  A recent commit reworked the retry logic and
incorrectly assumed that walking SPTEs would never "fail", as the loop
either bails (retries) or installs parent SPs.  However, the iterator
itself will bail early if it detects a frozen (REMOVED) SPTE when
stepping down.   The TDP iterator also rereads the current SPTE before
stepping down specifically to avoid walking into a part of the tree that
is being removed, which means it's possible to terminate the loop without
the guts of the loop observing the frozen SPTE, e.g. if a different task
zaps a parent SPTE between the initial read and try_step_down()'s refresh.

Mapping a leaf SPTE at the wrong level results in all kinds of badness as
page table walkers interpret the SPTE as a page table, not a leaf, and
walk into the weeds.

  ------------[ cut here ]------------
  WARNING: CPU: 1 PID: 1025 at arch/x86/kvm/mmu/tdp_mmu.c:1070 kvm_tdp_mmu_map+0x481/0x510
  Modules linked in: kvm_intel
  CPU: 1 PID: 1025 Comm: nx_huge_pages_t Tainted: G        W          6.1.0-rc4+ #64
  Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS 0.0.0 02/06/2015
  RIP: 0010:kvm_tdp_mmu_map+0x481/0x510
  RSP: 0018:ffffc9000072fba8 EFLAGS: 00010286
  RAX: 0000000000000000 RBX: ffffc9000072fcc0 RCX: 0000000000000027
  RDX: 0000000000000027 RSI: 00000000ffffdfff RDI: ffff888277c5b4c8
  RBP: ffff888107d45a10 R08: ffff888277c5b4c0 R09: ffffc9000072fa48
  R10: 0000000000000001 R11: 0000000000000001 R12: ffffc9000073a0e0
  R13: ffff88810fc54800 R14: ffff888107d1ae60 R15: ffff88810fc54f90
  FS:  00007fba9f853740(0000) GS:ffff888277c40000(0000) knlGS:0000000000000000
  CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
  CR2: 0000000000000000 CR3: 000000010aa7a003 CR4: 0000000000172ea0
  Call Trace:
   <TASK>
   kvm_tdp_page_fault+0x10c/0x130
   kvm_mmu_page_fault+0x103/0x680
   vmx_handle_exit+0x132/0x5a0 [kvm_intel]
   vcpu_enter_guest+0x60c/0x16f0
   kvm_arch_vcpu_ioctl_run+0x1e2/0x9d0
   kvm_vcpu_ioctl+0x271/0x660
   __x64_sys_ioctl+0x80/0xb0
   do_syscall_64+0x2b/0x50
   entry_SYSCALL_64_after_hwframe+0x46/0xb0
   </TASK>
  ---[ end trace 0000000000000000 ]---
  Invalid SPTE change: cannot replace a present leaf
  SPTE with another present leaf SPTE mapping a
  different PFN!
  as_id: 0 gfn: 100200 old_spte: 600000112400bf3 new_spte: 6000001126009f3 level: 2
  ------------[ cut here ]------------
  kernel BUG at arch/x86/kvm/mmu/tdp_mmu.c:559!
  invalid opcode: 0000 [#1] SMP
  CPU: 1 PID: 1025 Comm: nx_huge_pages_t Tainted: G        W          6.1.0-rc4+ #64
  Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS 0.0.0 02/06/2015
  RIP: 0010:__handle_changed_spte.cold+0x95/0x9c
  RSP: 0018:ffffc9000072faf8 EFLAGS: 00010246
  RAX: 00000000000000c1 RBX: ffffc90000731000 RCX: 0000000000000027
  RDX: 0000000000000000 RSI: 00000000ffffdfff RDI: ffff888277c5b4c8
  RBP: 0600000112400bf3 R08: ffff888277c5b4c0 R09: ffffc9000072f9a0
  R10: 0000000000000001 R11: 0000000000000001 R12: 06000001126009f3
  R13: 0000000000000002 R14: 0000000012600901 R15: 0000000012400b01
  FS:  00007fba9f853740(0000) GS:ffff888277c40000(0000) knlGS:0000000000000000
  CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
  CR2: 0000000000000000 CR3: 000000010aa7a003 CR4: 0000000000172ea0
  Call Trace:
   <TASK>
   kvm_tdp_mmu_map+0x3b0/0x510
   kvm_tdp_page_fault+0x10c/0x130
   kvm_mmu_page_fault+0x103/0x680
   vmx_handle_exit+0x132/0x5a0 [kvm_intel]
   vcpu_enter_guest+0x60c/0x16f0
   kvm_arch_vcpu_ioctl_run+0x1e2/0x9d0
   kvm_vcpu_ioctl+0x271/0x660
   __x64_sys_ioctl+0x80/0xb0
   do_syscall_64+0x2b/0x50
   entry_SYSCALL_64_after_hwframe+0x46/0xb0
   </TASK>
  Modules linked in: kvm_intel
  ---[ end trace 0000000000000000 ]---

Fixes: 63d28a25e04c ("KVM: x86/mmu: simplify kvm_tdp_mmu_map flow when guest has to retry")
Cc: Robert Hoo <robert.hu@linux.intel.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20221213033030.83345-3-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/mmu/tdp_mmu.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kvm/mmu/tdp_mmu.c b/arch/x86/kvm/mmu/tdp_mmu.c
index 84b0b225fe5f5..fbdef59374fed 100644
--- a/arch/x86/kvm/mmu/tdp_mmu.c
+++ b/arch/x86/kvm/mmu/tdp_mmu.c
@@ -1181,7 +1181,7 @@ int kvm_tdp_mmu_map(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault)
 			goto retry;
 
 		if (iter.level == fault->goal_level)
-			break;
+			goto map_target_level;
 
 		/* Step down into the lower level page table if it exists. */
 		if (is_shadow_present_pte(iter.old_spte) &&
@@ -1203,8 +1203,8 @@ int kvm_tdp_mmu_map(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault)
 			r = tdp_mmu_link_sp(kvm, &iter, sp, true);
 
 		/*
-		 * Also force the guest to retry the access if the upper level SPTEs
-		 * aren't in place.
+		 * Force the guest to retry if installing an upper level SPTE
+		 * failed, e.g. because a different task modified the SPTE.
 		 */
 		if (r) {
 			tdp_mmu_free_sp(sp);
@@ -1219,6 +1219,14 @@ int kvm_tdp_mmu_map(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault)
 		}
 	}
 
+	/*
+	 * The walk aborted before reaching the target level, e.g. because the
+	 * iterator detected an upper level SPTE was frozen during traversal.
+	 */
+	WARN_ON_ONCE(iter.level == fault->goal_level);
+	goto retry;
+
+map_target_level:
 	ret = tdp_mmu_map_handle_target_level(vcpu, fault, &iter);
 
 retry:
-- 
GitLab


From 21a36ac6b6c7059965bac0cc73ef3cbb8ef576dd Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@google.com>
Date: Tue, 13 Dec 2022 03:30:28 +0000
Subject: [PATCH 660/875] KVM: x86/mmu: Re-check under lock that TDP MMU SP
 hugepage is disallowed

Re-check sp->nx_huge_page_disallowed under the tdp_mmu_pages_lock spinlock
when adding a new shadow page in the TDP MMU.  To ensure the NX reclaim
kthread can't see a not-yet-linked shadow page, the page fault path links
the new page table prior to adding the page to possible_nx_huge_pages.

If the page is zapped by different task, e.g. because dirty logging is
disabled, between linking the page and adding it to the list, KVM can end
up triggering use-after-free by adding the zapped SP to the aforementioned
list, as the zapped SP's memory is scheduled for removal via RCU callback.
The bug is detected by the sanity checks guarded by CONFIG_DEBUG_LIST=y,
i.e. the below splat is just one possible signature.

  ------------[ cut here ]------------
  list_add corruption. prev->next should be next (ffffc9000071fa70), but was ffff88811125ee38. (prev=ffff88811125ee38).
  WARNING: CPU: 1 PID: 953 at lib/list_debug.c:30 __list_add_valid+0x79/0xa0
  Modules linked in: kvm_intel
  CPU: 1 PID: 953 Comm: nx_huge_pages_t Tainted: G        W          6.1.0-rc4+ #71
  Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS 0.0.0 02/06/2015
  RIP: 0010:__list_add_valid+0x79/0xa0
  RSP: 0018:ffffc900006efb68 EFLAGS: 00010286
  RAX: 0000000000000000 RBX: ffff888116cae8a0 RCX: 0000000000000027
  RDX: 0000000000000027 RSI: 0000000100001872 RDI: ffff888277c5b4c8
  RBP: ffffc90000717000 R08: ffff888277c5b4c0 R09: ffffc900006efa08
  R10: 0000000000199998 R11: 0000000000199a20 R12: ffff888116cae930
  R13: ffff88811125ee38 R14: ffffc9000071fa70 R15: ffff88810b794f90
  FS:  00007fc0415d2740(0000) GS:ffff888277c40000(0000) knlGS:0000000000000000
  CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
  CR2: 0000000000000000 CR3: 0000000115201006 CR4: 0000000000172ea0
  Call Trace:
   <TASK>
   track_possible_nx_huge_page+0x53/0x80
   kvm_tdp_mmu_map+0x242/0x2c0
   kvm_tdp_page_fault+0x10c/0x130
   kvm_mmu_page_fault+0x103/0x680
   vmx_handle_exit+0x132/0x5a0 [kvm_intel]
   vcpu_enter_guest+0x60c/0x16f0
   kvm_arch_vcpu_ioctl_run+0x1e2/0x9d0
   kvm_vcpu_ioctl+0x271/0x660
   __x64_sys_ioctl+0x80/0xb0
   do_syscall_64+0x2b/0x50
   entry_SYSCALL_64_after_hwframe+0x46/0xb0
   </TASK>
  ---[ end trace 0000000000000000 ]---

Fixes: 61f94478547b ("KVM: x86/mmu: Set disallowed_nx_huge_page in TDP MMU before setting SPTE")
Reported-by: Greg Thelen <gthelen@google.com>
Analyzed-by: David Matlack <dmatlack@google.com>
Cc: David Matlack <dmatlack@google.com>
Cc: Ben Gardon <bgardon@google.com>
Cc: Mingwei Zhang <mizhang@google.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20221213033030.83345-4-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/mmu/tdp_mmu.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kvm/mmu/tdp_mmu.c b/arch/x86/kvm/mmu/tdp_mmu.c
index fbdef59374fed..62a687d094bba 100644
--- a/arch/x86/kvm/mmu/tdp_mmu.c
+++ b/arch/x86/kvm/mmu/tdp_mmu.c
@@ -1214,7 +1214,8 @@ int kvm_tdp_mmu_map(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault)
 		if (fault->huge_page_disallowed &&
 		    fault->req_level >= iter.level) {
 			spin_lock(&kvm->arch.tdp_mmu_pages_lock);
-			track_possible_nx_huge_page(kvm, sp);
+			if (sp->nx_huge_page_disallowed)
+				track_possible_nx_huge_page(kvm, sp);
 			spin_unlock(&kvm->arch.tdp_mmu_pages_lock);
 		}
 	}
-- 
GitLab


From 50a9ac25985c037d45ee6d7e3a7ae198a63b9266 Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@google.com>
Date: Tue, 13 Dec 2022 03:30:29 +0000
Subject: [PATCH 661/875] KVM: x86/mmu: Don't install TDP MMU SPTE if SP has
 unexpected level

Don't install a leaf TDP MMU SPTE if the parent page's level doesn't
match the target level of the fault, and instead have the vCPU retry the
faulting instruction after warning.  Continuing on is completely
unnecessary as the absolute worst case scenario of retrying is DoSing
the vCPU, whereas continuing on all but guarantees bigger explosions, e.g.

  ------------[ cut here ]------------
  kernel BUG at arch/x86/kvm/mmu/tdp_mmu.c:559!
  invalid opcode: 0000 [#1] SMP
  CPU: 1 PID: 1025 Comm: nx_huge_pages_t Tainted: G        W          6.1.0-rc4+ #64
  Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS 0.0.0 02/06/2015
  RIP: 0010:__handle_changed_spte.cold+0x95/0x9c
  RSP: 0018:ffffc9000072faf8 EFLAGS: 00010246
  RAX: 00000000000000c1 RBX: ffffc90000731000 RCX: 0000000000000027
  RDX: 0000000000000000 RSI: 00000000ffffdfff RDI: ffff888277c5b4c8
  RBP: 0600000112400bf3 R08: ffff888277c5b4c0 R09: ffffc9000072f9a0
  R10: 0000000000000001 R11: 0000000000000001 R12: 06000001126009f3
  R13: 0000000000000002 R14: 0000000012600901 R15: 0000000012400b01
  FS:  00007fba9f853740(0000) GS:ffff888277c40000(0000) knlGS:0000000000000000
  CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
  CR2: 0000000000000000 CR3: 000000010aa7a003 CR4: 0000000000172ea0
  Call Trace:
   <TASK>
   kvm_tdp_mmu_map+0x3b0/0x510
   kvm_tdp_page_fault+0x10c/0x130
   kvm_mmu_page_fault+0x103/0x680
   vmx_handle_exit+0x132/0x5a0 [kvm_intel]
   vcpu_enter_guest+0x60c/0x16f0
   kvm_arch_vcpu_ioctl_run+0x1e2/0x9d0
   kvm_vcpu_ioctl+0x271/0x660
   __x64_sys_ioctl+0x80/0xb0
   do_syscall_64+0x2b/0x50
   entry_SYSCALL_64_after_hwframe+0x46/0xb0
   </TASK>
  Modules linked in: kvm_intel
  ---[ end trace 0000000000000000 ]---

Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20221213033030.83345-5-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/mmu/tdp_mmu.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kvm/mmu/tdp_mmu.c b/arch/x86/kvm/mmu/tdp_mmu.c
index 62a687d094bba..d6df38d371a00 100644
--- a/arch/x86/kvm/mmu/tdp_mmu.c
+++ b/arch/x86/kvm/mmu/tdp_mmu.c
@@ -1074,7 +1074,9 @@ static int tdp_mmu_map_handle_target_level(struct kvm_vcpu *vcpu,
 	int ret = RET_PF_FIXED;
 	bool wrprot = false;
 
-	WARN_ON(sp->role.level != fault->goal_level);
+	if (WARN_ON_ONCE(sp->role.level != fault->goal_level))
+		return RET_PF_RETRY;
+
 	if (unlikely(!fault->slot))
 		new_spte = make_mmio_spte(vcpu, iter->gfn, ACC_ALL);
 	else
-- 
GitLab


From cf8016408d880afe9c5dc495af40dc2932874e77 Mon Sep 17 00:00:00 2001
From: Sami Tolvanen <samitolvanen@google.com>
Date: Thu, 22 Dec 2022 22:57:47 +0000
Subject: [PATCH 662/875] cfi: Fix CFI failure with KASAN

When CFI_CLANG and KASAN are both enabled, LLVM doesn't generate a
CFI type hash for asan.module_ctor functions in translation units
where CFI is disabled, which leads to a CFI failure during boot when
do_ctors calls the affected constructors:

  CFI failure at do_basic_setup+0x64/0x90 (target:
  asan.module_ctor+0x0/0x28; expected type: 0xa540670c)

Specifically, this happens because CFI is disabled for
kernel/cfi.c. There's no reason to keep CFI disabled here anymore, so
fix the failure by not filtering out CC_FLAGS_CFI for the file.

Note that https://reviews.llvm.org/rG3b14862f0a96 fixed the issue
where LLVM didn't emit CFI type hashes for any sanitizer constructors,
but now type hashes are emitted correctly for TUs that use CFI.

Link: https://github.com/ClangBuiltLinux/linux/issues/1742
Fixes: 89245600941e ("cfi: Switch to -fsanitize=kcfi")
Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
Signed-off-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/r/20221222225747.3538676-1-samitolvanen@google.com
---
 kernel/Makefile | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/kernel/Makefile b/kernel/Makefile
index d754e0be1176d..ebc692242b68b 100644
--- a/kernel/Makefile
+++ b/kernel/Makefile
@@ -41,9 +41,6 @@ UBSAN_SANITIZE_kcov.o := n
 KMSAN_SANITIZE_kcov.o := n
 CFLAGS_kcov.o := $(call cc-option, -fno-conserve-stack) -fno-stack-protector
 
-# Don't instrument error handlers
-CFLAGS_REMOVE_cfi.o := $(CC_FLAGS_CFI)
-
 obj-y += sched/
 obj-y += locking/
 obj-y += power/
-- 
GitLab


From 2f4fec5943407318b9523f01ce1f5d668c028332 Mon Sep 17 00:00:00 2001
From: John Stultz <jstultz@google.com>
Date: Wed, 21 Dec 2022 05:18:55 +0000
Subject: [PATCH 663/875] pstore: Make sure CONFIG_PSTORE_PMSG selects
 CONFIG_RT_MUTEXES

In commit 76d62f24db07 ("pstore: Switch pmsg_lock to an rt_mutex
to avoid priority inversion") I changed a lock to an rt_mutex.

However, its possible that CONFIG_RT_MUTEXES is not enabled,
which then results in a build failure, as the 0day bot detected:
  https://lore.kernel.org/linux-mm/202212211244.TwzWZD3H-lkp@intel.com/

Thus this patch changes CONFIG_PSTORE_PMSG to select
CONFIG_RT_MUTEXES, which ensures the build will not fail.

Cc: Wei Wang <wvw@google.com>
Cc: Midas Chien<midaschieh@google.com>
Cc: Connor O'Brien <connoro@google.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Anton Vorontsov <anton@enomsg.org>
Cc: Colin Cross <ccross@android.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: kernel test robot <lkp@intel.com>
Cc: kernel-team@android.com
Fixes: 76d62f24db07 ("pstore: Switch pmsg_lock to an rt_mutex to avoid priority inversion")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: John Stultz <jstultz@google.com>
Signed-off-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/r/20221221051855.15761-1-jstultz@google.com
---
 fs/pstore/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/fs/pstore/Kconfig b/fs/pstore/Kconfig
index 8adabde685f13..c49d554cc9ae9 100644
--- a/fs/pstore/Kconfig
+++ b/fs/pstore/Kconfig
@@ -126,6 +126,7 @@ config PSTORE_CONSOLE
 config PSTORE_PMSG
 	bool "Log user space messages"
 	depends on PSTORE
+	select RT_MUTEXES
 	help
 	  When the option is enabled, pstore will export a character
 	  interface /dev/pmsg0 to log user space messages. On reboot
-- 
GitLab


From beca3e311a49cd3c55a056096531737d7afa4361 Mon Sep 17 00:00:00 2001
From: Luca Stefani <luca@osomprivacy.com>
Date: Thu, 22 Dec 2022 14:10:49 +0100
Subject: [PATCH 664/875] pstore: Properly assign mem_type property

If mem-type is specified in the device tree
it would end up overriding the record_size
field instead of populating mem_type.

As record_size is currently parsed after the
improper assignment with default size 0 it
continued to work as expected regardless of the
value found in the device tree.

Simply changing the target field of the struct
is enough to get mem-type working as expected.

Fixes: 9d843e8fafc7 ("pstore: Add mem_type property DT parsing support")
Cc: stable@vger.kernel.org
Signed-off-by: Luca Stefani <luca@osomprivacy.com>
Signed-off-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/r/20221222131049.286288-1-luca@osomprivacy.com
---
 fs/pstore/ram.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/pstore/ram.c b/fs/pstore/ram.c
index 9a5052431fd36..ade66dbe5f396 100644
--- a/fs/pstore/ram.c
+++ b/fs/pstore/ram.c
@@ -680,7 +680,7 @@ static int ramoops_parse_dt(struct platform_device *pdev,
 		field = value;						\
 	}
 
-	parse_u32("mem-type", pdata->record_size, pdata->mem_type);
+	parse_u32("mem-type", pdata->mem_type, pdata->mem_type);
 	parse_u32("record-size", pdata->record_size, 0);
 	parse_u32("console-size", pdata->console_size, 0);
 	parse_u32("ftrace-size", pdata->ftrace_size, 0);
-- 
GitLab


From 09e6b30eeb254f1818a008cace3547159e908dfd Mon Sep 17 00:00:00 2001
From: Jie Wang <wangjie125@huawei.com>
Date: Thu, 22 Dec 2022 14:43:41 +0800
Subject: [PATCH 665/875] net: hns3: add interrupts re-initialization while
 doing VF FLR

Currently keep alive message between PF and VF may be lost and the VF is
unalive in PF. So the VF will not do reset during PF FLR reset process.
This would make the allocated interrupt resources of VF invalid and VF
would't receive or respond to PF any more.

So this patch adds VF interrupts re-initialization during VF FLR for VF
recovery in above cases.

Fixes: 862d969a3a4d ("net: hns3: do VF's pci re-initialization while PF doing FLR")
Signed-off-by: Jie Wang <wangjie125@huawei.com>
Signed-off-by: Hao Lan <lanhao@huawei.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
index db6f7cdba9587..081bd2c3f2891 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
@@ -2767,7 +2767,8 @@ static int hclgevf_pci_reset(struct hclgevf_dev *hdev)
 	struct pci_dev *pdev = hdev->pdev;
 	int ret = 0;
 
-	if (hdev->reset_type == HNAE3_VF_FULL_RESET &&
+	if ((hdev->reset_type == HNAE3_VF_FULL_RESET ||
+	     hdev->reset_type == HNAE3_FLR_RESET) &&
 	    test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
 		hclgevf_misc_irq_uninit(hdev);
 		hclgevf_uninit_msi(hdev);
-- 
GitLab


From 7d89b53cea1a702f97117fb4361523519bb1e52c Mon Sep 17 00:00:00 2001
From: Jian Shen <shenjian15@huawei.com>
Date: Thu, 22 Dec 2022 14:43:42 +0800
Subject: [PATCH 666/875] net: hns3: fix miss L3E checking for rx packet

For device supports RXD advanced layout, the driver will
return directly if the hardware finish the checksum
calculate. It cause missing L3E checking for ip packets.
Fixes it.

Fixes: 1ddc028ac849 ("net: hns3: refactor out RX completion checksum")
Signed-off-by: Jian Shen <shenjian15@huawei.com>
Signed-off-by: Hao Lan <lanhao@huawei.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
index 0ec5730b17886..b4c4fb873568c 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
@@ -3855,18 +3855,16 @@ static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
 	return 0;
 }
 
-static bool hns3_checksum_complete(struct hns3_enet_ring *ring,
+static void hns3_checksum_complete(struct hns3_enet_ring *ring,
 				   struct sk_buff *skb, u32 ptype, u16 csum)
 {
 	if (ptype == HNS3_INVALID_PTYPE ||
 	    hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE)
-		return false;
+		return;
 
 	hns3_ring_stats_update(ring, csum_complete);
 	skb->ip_summed = CHECKSUM_COMPLETE;
 	skb->csum = csum_unfold((__force __sum16)csum);
-
-	return true;
 }
 
 static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info,
@@ -3926,8 +3924,7 @@ static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
 		ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
 					HNS3_RXD_PTYPE_S);
 
-	if (hns3_checksum_complete(ring, skb, ptype, csum))
-		return;
+	hns3_checksum_complete(ring, skb, ptype, csum);
 
 	/* check if hardware has done checksum */
 	if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
@@ -3936,6 +3933,7 @@ static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
 	if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
 				 BIT(HNS3_RXD_OL3E_B) |
 				 BIT(HNS3_RXD_OL4E_B)))) {
+		skb->ip_summed = CHECKSUM_NONE;
 		hns3_ring_stats_update(ring, l3l4_csum_err);
 
 		return;
-- 
GitLab


From 8ee57c7b8406c7aa8ca31e014440c87c6383f429 Mon Sep 17 00:00:00 2001
From: Jian Shen <shenjian15@huawei.com>
Date: Thu, 22 Dec 2022 14:43:43 +0800
Subject: [PATCH 667/875] net: hns3: fix VF promisc mode not update when mac
 table full

Currently, it missed set HCLGE_VPORT_STATE_PROMISC_CHANGE
flag for VF when vport->overflow_promisc_flags changed.
So the VF won't check whether to update promisc mode in
this case. So add it.

Fixes: 1e6e76101fd9 ("net: hns3: configure promisc mode for VF asynchronously")
Signed-off-by: Jian Shen <shenjian15@huawei.com>
Signed-off-by: Hao Lan <lanhao@huawei.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 .../hisilicon/hns3/hns3pf/hclge_main.c        | 75 +++++++++++--------
 1 file changed, 43 insertions(+), 32 deletions(-)

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index 4e54f91f7a6c1..6c2742f59c777 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -12754,60 +12754,71 @@ static int hclge_gro_en(struct hnae3_handle *handle, bool enable)
 	return ret;
 }
 
-static void hclge_sync_promisc_mode(struct hclge_dev *hdev)
+static int hclge_sync_vport_promisc_mode(struct hclge_vport *vport)
 {
-	struct hclge_vport *vport = &hdev->vport[0];
 	struct hnae3_handle *handle = &vport->nic;
+	struct hclge_dev *hdev = vport->back;
+	bool uc_en = false;
+	bool mc_en = false;
 	u8 tmp_flags;
+	bool bc_en;
 	int ret;
-	u16 i;
 
 	if (vport->last_promisc_flags != vport->overflow_promisc_flags) {
 		set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
 		vport->last_promisc_flags = vport->overflow_promisc_flags;
 	}
 
-	if (test_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state)) {
+	if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE,
+				&vport->state))
+		return 0;
+
+	/* for PF */
+	if (!vport->vport_id) {
 		tmp_flags = handle->netdev_flags | vport->last_promisc_flags;
 		ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE,
 					     tmp_flags & HNAE3_MPE);
-		if (!ret) {
-			clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE,
-				  &vport->state);
+		if (!ret)
 			set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
 				&vport->state);
-		}
+		else
+			set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE,
+				&vport->state);
+		return ret;
 	}
 
-	for (i = 1; i < hdev->num_alloc_vport; i++) {
-		bool uc_en = false;
-		bool mc_en = false;
-		bool bc_en;
+	/* for VF */
+	if (vport->vf_info.trusted) {
+		uc_en = vport->vf_info.request_uc_en > 0 ||
+			vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE;
+		mc_en = vport->vf_info.request_mc_en > 0 ||
+			vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE;
+	}
+	bc_en = vport->vf_info.request_bc_en > 0;
 
-		vport = &hdev->vport[i];
+	ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en,
+					 mc_en, bc_en);
+	if (ret) {
+		set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
+		return ret;
+	}
+	hclge_set_vport_vlan_fltr_change(vport);
 
-		if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE,
-					&vport->state))
-			continue;
+	return 0;
+}
 
-		if (vport->vf_info.trusted) {
-			uc_en = vport->vf_info.request_uc_en > 0 ||
-				vport->overflow_promisc_flags &
-				HNAE3_OVERFLOW_UPE;
-			mc_en = vport->vf_info.request_mc_en > 0 ||
-				vport->overflow_promisc_flags &
-				HNAE3_OVERFLOW_MPE;
-		}
-		bc_en = vport->vf_info.request_bc_en > 0;
+static void hclge_sync_promisc_mode(struct hclge_dev *hdev)
+{
+	struct hclge_vport *vport;
+	int ret;
+	u16 i;
 
-		ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en,
-						 mc_en, bc_en);
-		if (ret) {
-			set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE,
-				&vport->state);
+	for (i = 0; i < hdev->num_alloc_vport; i++) {
+		vport = &hdev->vport[i];
+
+		ret = hclge_sync_vport_promisc_mode(vport);
+		if (ret)
 			return;
-		}
-		hclge_set_vport_vlan_fltr_change(vport);
 	}
 }
 
-- 
GitLab


From fcbb408a1aaf426f88d8fb3b4c14e3625745b02f Mon Sep 17 00:00:00 2001
From: Stanislav Fomichev <sdf@google.com>
Date: Thu, 22 Dec 2022 13:39:58 -0800
Subject: [PATCH 668/875] selftests/bpf: Add host-tools to gitignore

Shows up when cross-compiling:

HOST_SCRATCH_DIR        := $(OUTPUT)/host-tools

vs

SCRATCH_DIR := $(OUTPUT)/tools
HOST_SCRATCH_DIR        := $(SCRATCH_DIR)

Reported-by: John Sperbeck <jsperbeck@google.com>
Signed-off-by: Stanislav Fomichev <sdf@google.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Link: https://lore.kernel.org/bpf/20221222213958.2302320-1-sdf@google.com
---
 tools/testing/selftests/bpf/.gitignore | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tools/testing/selftests/bpf/.gitignore b/tools/testing/selftests/bpf/.gitignore
index 07d2d0a8c5cb4..401a75844cc0e 100644
--- a/tools/testing/selftests/bpf/.gitignore
+++ b/tools/testing/selftests/bpf/.gitignore
@@ -36,6 +36,7 @@ test_cpp
 *.lskel.h
 /no_alu32
 /bpf_gcc
+/host-tools
 /tools
 /runqslower
 /bench
-- 
GitLab


From 292a089d78d3e2f7944e60bb897c977785a321e3 Mon Sep 17 00:00:00 2001
From: "Steven Rostedt (Google)" <rostedt@goodmis.org>
Date: Tue, 20 Dec 2022 13:45:19 -0500
Subject: [PATCH 669/875] treewide: Convert del_timer*() to timer_shutdown*()

Due to several bugs caused by timers being re-armed after they are
shutdown and just before they are freed, a new state of timers was added
called "shutdown".  After a timer is set to this state, then it can no
longer be re-armed.

The following script was run to find all the trivial locations where
del_timer() or del_timer_sync() is called in the same function that the
object holding the timer is freed.  It also ignores any locations where
the timer->function is modified between the del_timer*() and the free(),
as that is not considered a "trivial" case.

This was created by using a coccinelle script and the following
commands:

    $ cat timer.cocci
    @@
    expression ptr, slab;
    identifier timer, rfield;
    @@
    (
    -       del_timer(&ptr->timer);
    +       timer_shutdown(&ptr->timer);
    |
    -       del_timer_sync(&ptr->timer);
    +       timer_shutdown_sync(&ptr->timer);
    )
      ... when strict
          when != ptr->timer
    (
            kfree_rcu(ptr, rfield);
    |
            kmem_cache_free(slab, ptr);
    |
            kfree(ptr);
    )

    $ spatch timer.cocci . > /tmp/t.patch
    $ patch -p1 < /tmp/t.patch

Link: https://lore.kernel.org/lkml/20221123201306.823305113@linutronix.de/
Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>
Acked-by: Pavel Machek <pavel@ucw.cz> [ LED ]
Acked-by: Kalle Valo <kvalo@kernel.org> [ wireless ]
Acked-by: Paolo Abeni <pabeni@redhat.com> [ networking ]
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
---
 arch/sh/drivers/push-switch.c                    |  2 +-
 block/blk-iocost.c                               |  2 +-
 block/blk-iolatency.c                            |  2 +-
 block/kyber-iosched.c                            |  2 +-
 drivers/acpi/apei/ghes.c                         |  2 +-
 drivers/atm/idt77252.c                           |  6 +++---
 drivers/block/drbd/drbd_main.c                   |  2 +-
 drivers/block/loop.c                             |  2 +-
 drivers/bluetooth/hci_bcsp.c                     |  2 +-
 drivers/gpu/drm/i915/i915_sw_fence.c             |  2 +-
 drivers/hid/hid-wiimote-core.c                   |  2 +-
 drivers/input/keyboard/locomokbd.c               |  2 +-
 drivers/input/keyboard/omap-keypad.c             |  2 +-
 drivers/input/mouse/alps.c                       |  2 +-
 drivers/isdn/mISDN/l1oip_core.c                  |  4 ++--
 drivers/isdn/mISDN/timerdev.c                    |  4 ++--
 drivers/leds/trigger/ledtrig-activity.c          |  2 +-
 drivers/leds/trigger/ledtrig-heartbeat.c         |  2 +-
 drivers/leds/trigger/ledtrig-pattern.c           |  2 +-
 drivers/leds/trigger/ledtrig-transient.c         |  2 +-
 drivers/media/pci/ivtv/ivtv-driver.c             |  2 +-
 drivers/media/usb/pvrusb2/pvrusb2-hdw.c          | 16 ++++++++--------
 drivers/media/usb/s2255/s2255drv.c               |  4 ++--
 drivers/net/ethernet/intel/i40e/i40e_main.c      |  6 +++---
 drivers/net/ethernet/marvell/sky2.c              |  2 +-
 drivers/net/ethernet/sun/sunvnet.c               |  2 +-
 drivers/net/usb/sierra_net.c                     |  2 +-
 .../broadcom/brcm80211/brcmfmac/btcoex.c         |  2 +-
 drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c |  2 +-
 drivers/net/wireless/intel/iwlwifi/mvm/sta.c     |  2 +-
 drivers/net/wireless/intersil/hostap/hostap_ap.c |  2 +-
 drivers/net/wireless/marvell/mwifiex/main.c      |  2 +-
 drivers/net/wireless/microchip/wilc1000/hif.c    |  6 +++---
 drivers/nfc/pn533/pn533.c                        |  2 +-
 drivers/nfc/pn533/uart.c                         |  2 +-
 drivers/pcmcia/bcm63xx_pcmcia.c                  |  2 +-
 drivers/pcmcia/electra_cf.c                      |  2 +-
 drivers/pcmcia/omap_cf.c                         |  2 +-
 drivers/pcmcia/pd6729.c                          |  4 ++--
 drivers/pcmcia/yenta_socket.c                    |  4 ++--
 drivers/scsi/qla2xxx/qla_edif.c                  |  4 ++--
 .../staging/media/atomisp/i2c/atomisp-lm3554.c   |  2 +-
 drivers/staging/wlan-ng/prism2usb.c              |  6 +++---
 drivers/tty/n_gsm.c                              |  2 +-
 drivers/tty/sysrq.c                              |  2 +-
 drivers/usb/gadget/udc/m66592-udc.c              |  2 +-
 drivers/usb/serial/garmin_gps.c                  |  2 +-
 drivers/usb/serial/mos7840.c                     |  4 ++--
 fs/ext4/super.c                                  |  2 +-
 fs/nilfs2/segment.c                              |  2 +-
 net/802/garp.c                                   |  2 +-
 net/802/mrp.c                                    |  4 ++--
 net/bridge/br_multicast.c                        |  8 ++++----
 net/bridge/br_multicast_eht.c                    |  4 ++--
 net/core/gen_estimator.c                         |  2 +-
 net/ipv4/ipmr.c                                  |  2 +-
 net/ipv6/ip6mr.c                                 |  2 +-
 net/mac80211/mesh_pathtbl.c                      |  2 +-
 net/netfilter/ipset/ip_set_list_set.c            |  2 +-
 net/netfilter/ipvs/ip_vs_lblc.c                  |  2 +-
 net/netfilter/ipvs/ip_vs_lblcr.c                 |  2 +-
 net/netfilter/xt_IDLETIMER.c                     |  4 ++--
 net/netfilter/xt_LED.c                           |  2 +-
 net/sched/cls_flow.c                             |  2 +-
 net/sunrpc/svc.c                                 |  2 +-
 net/tipc/discover.c                              |  2 +-
 net/tipc/monitor.c                               |  2 +-
 sound/i2c/other/ak4117.c                         |  2 +-
 sound/synth/emux/emux.c                          |  2 +-
 69 files changed, 97 insertions(+), 97 deletions(-)

diff --git a/arch/sh/drivers/push-switch.c b/arch/sh/drivers/push-switch.c
index 2813140fd92bb..c95f48ff3f6fb 100644
--- a/arch/sh/drivers/push-switch.c
+++ b/arch/sh/drivers/push-switch.c
@@ -102,7 +102,7 @@ static int switch_drv_remove(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, NULL);
 	flush_work(&psw->work);
-	del_timer_sync(&psw->debounce);
+	timer_shutdown_sync(&psw->debounce);
 	free_irq(irq, pdev);
 
 	kfree(psw);
diff --git a/block/blk-iocost.c b/block/blk-iocost.c
index 549ddc9e0c6f4..6955605629e4f 100644
--- a/block/blk-iocost.c
+++ b/block/blk-iocost.c
@@ -2820,7 +2820,7 @@ static void ioc_rqos_exit(struct rq_qos *rqos)
 	ioc->running = IOC_STOP;
 	spin_unlock_irq(&ioc->lock);
 
-	del_timer_sync(&ioc->timer);
+	timer_shutdown_sync(&ioc->timer);
 	free_percpu(ioc->pcpu_stat);
 	kfree(ioc);
 }
diff --git a/block/blk-iolatency.c b/block/blk-iolatency.c
index 778a0057193ef..ecdc107418362 100644
--- a/block/blk-iolatency.c
+++ b/block/blk-iolatency.c
@@ -644,7 +644,7 @@ static void blkcg_iolatency_exit(struct rq_qos *rqos)
 {
 	struct blk_iolatency *blkiolat = BLKIOLATENCY(rqos);
 
-	del_timer_sync(&blkiolat->timer);
+	timer_shutdown_sync(&blkiolat->timer);
 	flush_work(&blkiolat->enable_work);
 	blkcg_deactivate_policy(rqos->q, &blkcg_policy_iolatency);
 	kfree(blkiolat);
diff --git a/block/kyber-iosched.c b/block/kyber-iosched.c
index b05357bced990..2146969237bfe 100644
--- a/block/kyber-iosched.c
+++ b/block/kyber-iosched.c
@@ -434,7 +434,7 @@ static void kyber_exit_sched(struct elevator_queue *e)
 	struct kyber_queue_data *kqd = e->elevator_data;
 	int i;
 
-	del_timer_sync(&kqd->timer);
+	timer_shutdown_sync(&kqd->timer);
 	blk_stat_disable_accounting(kqd->q);
 
 	for (i = 0; i < KYBER_NUM_DOMAINS; i++)
diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
index 066dc1f5c235e..34ad071a64e96 100644
--- a/drivers/acpi/apei/ghes.c
+++ b/drivers/acpi/apei/ghes.c
@@ -1431,7 +1431,7 @@ static int ghes_remove(struct platform_device *ghes_dev)
 	ghes->flags |= GHES_EXITING;
 	switch (generic->notify.type) {
 	case ACPI_HEST_NOTIFY_POLLED:
-		del_timer_sync(&ghes->timer);
+		timer_shutdown_sync(&ghes->timer);
 		break;
 	case ACPI_HEST_NOTIFY_EXTERNAL:
 		free_irq(ghes->irq, ghes);
diff --git a/drivers/atm/idt77252.c b/drivers/atm/idt77252.c
index 681cb3786794d..eec0cc2144e02 100644
--- a/drivers/atm/idt77252.c
+++ b/drivers/atm/idt77252.c
@@ -2213,7 +2213,7 @@ idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc,
 	}
 	spin_unlock_irqrestore(&vc->lock, flags);
 	if (est) {
-		del_timer_sync(&est->timer);
+		timer_shutdown_sync(&est->timer);
 		kfree(est);
 	}
 
@@ -2530,7 +2530,7 @@ done:
 		vc->tx_vcc = NULL;
 
 		if (vc->estimator) {
-			del_timer(&vc->estimator->timer);
+			timer_shutdown(&vc->estimator->timer);
 			kfree(vc->estimator);
 			vc->estimator = NULL;
 		}
@@ -3752,7 +3752,7 @@ static void __exit idt77252_exit(void)
 		card = idt77252_chain;
 		dev = card->atmdev;
 		idt77252_chain = card->next;
-		del_timer_sync(&card->tst_timer);
+		timer_shutdown_sync(&card->tst_timer);
 
 		if (dev->phy->stop)
 			dev->phy->stop(dev);
diff --git a/drivers/block/drbd/drbd_main.c b/drivers/block/drbd/drbd_main.c
index 2f16e1bfb6e71..e43dfb9eb6ad3 100644
--- a/drivers/block/drbd/drbd_main.c
+++ b/drivers/block/drbd/drbd_main.c
@@ -2184,7 +2184,7 @@ void drbd_destroy_device(struct kref *kref)
 	struct drbd_resource *resource = device->resource;
 	struct drbd_peer_device *peer_device, *tmp_peer_device;
 
-	del_timer_sync(&device->request_timer);
+	timer_shutdown_sync(&device->request_timer);
 
 	/* paranoia asserts */
 	D_ASSERT(device, device->open_cnt == 0);
diff --git a/drivers/block/loop.c b/drivers/block/loop.c
index df628e30bca41..1518a6423279b 100644
--- a/drivers/block/loop.c
+++ b/drivers/block/loop.c
@@ -1755,7 +1755,7 @@ static void lo_free_disk(struct gendisk *disk)
 	if (lo->workqueue)
 		destroy_workqueue(lo->workqueue);
 	loop_free_idle_workers(lo, true);
-	del_timer_sync(&lo->timer);
+	timer_shutdown_sync(&lo->timer);
 	mutex_destroy(&lo->lo_mutex);
 	kfree(lo);
 }
diff --git a/drivers/bluetooth/hci_bcsp.c b/drivers/bluetooth/hci_bcsp.c
index 8055f63603f45..2a5a27d713f8a 100644
--- a/drivers/bluetooth/hci_bcsp.c
+++ b/drivers/bluetooth/hci_bcsp.c
@@ -737,7 +737,7 @@ static int bcsp_close(struct hci_uart *hu)
 {
 	struct bcsp_struct *bcsp = hu->priv;
 
-	del_timer_sync(&bcsp->tbcsp);
+	timer_shutdown_sync(&bcsp->tbcsp);
 
 	hu->priv = NULL;
 
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c b/drivers/gpu/drm/i915/i915_sw_fence.c
index cc2a8821d22a3..8a9aad523eec2 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence.c
@@ -465,7 +465,7 @@ static void irq_i915_sw_fence_work(struct irq_work *wrk)
 	struct i915_sw_dma_fence_cb_timer *cb =
 		container_of(wrk, typeof(*cb), work);
 
-	del_timer_sync(&cb->timer);
+	timer_shutdown_sync(&cb->timer);
 	dma_fence_put(cb->dma);
 
 	kfree_rcu(cb, rcu);
diff --git a/drivers/hid/hid-wiimote-core.c b/drivers/hid/hid-wiimote-core.c
index 09db8111dc262..26167cfb696f8 100644
--- a/drivers/hid/hid-wiimote-core.c
+++ b/drivers/hid/hid-wiimote-core.c
@@ -1771,7 +1771,7 @@ static void wiimote_destroy(struct wiimote_data *wdata)
 	spin_unlock_irqrestore(&wdata->state.lock, flags);
 
 	cancel_work_sync(&wdata->init_worker);
-	del_timer_sync(&wdata->timer);
+	timer_shutdown_sync(&wdata->timer);
 
 	device_remove_file(&wdata->hdev->dev, &dev_attr_devtype);
 	device_remove_file(&wdata->hdev->dev, &dev_attr_extension);
diff --git a/drivers/input/keyboard/locomokbd.c b/drivers/input/keyboard/locomokbd.c
index dae0535965722..f866c03b9d0ef 100644
--- a/drivers/input/keyboard/locomokbd.c
+++ b/drivers/input/keyboard/locomokbd.c
@@ -310,7 +310,7 @@ static void locomokbd_remove(struct locomo_dev *dev)
 
 	free_irq(dev->irq[0], locomokbd);
 
-	del_timer_sync(&locomokbd->timer);
+	timer_shutdown_sync(&locomokbd->timer);
 
 	input_unregister_device(locomokbd->input);
 	locomo_set_drvdata(dev, NULL);
diff --git a/drivers/input/keyboard/omap-keypad.c b/drivers/input/keyboard/omap-keypad.c
index 57447d6c90078..24440b4986457 100644
--- a/drivers/input/keyboard/omap-keypad.c
+++ b/drivers/input/keyboard/omap-keypad.c
@@ -296,7 +296,7 @@ static int omap_kp_remove(struct platform_device *pdev)
 	omap_writew(1, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
 	free_irq(omap_kp->irq, omap_kp);
 
-	del_timer_sync(&omap_kp->timer);
+	timer_shutdown_sync(&omap_kp->timer);
 	tasklet_kill(&kp_tasklet);
 
 	/* unregister everything */
diff --git a/drivers/input/mouse/alps.c b/drivers/input/mouse/alps.c
index 4a6b33bbe7eaf..989228b5a0a44 100644
--- a/drivers/input/mouse/alps.c
+++ b/drivers/input/mouse/alps.c
@@ -2970,7 +2970,7 @@ static void alps_disconnect(struct psmouse *psmouse)
 	struct alps_data *priv = psmouse->private;
 
 	psmouse_reset(psmouse);
-	del_timer_sync(&priv->timer);
+	timer_shutdown_sync(&priv->timer);
 	if (priv->dev2)
 		input_unregister_device(priv->dev2);
 	if (!IS_ERR_OR_NULL(priv->dev3))
diff --git a/drivers/isdn/mISDN/l1oip_core.c b/drivers/isdn/mISDN/l1oip_core.c
index c24771336f611..f010b35a05313 100644
--- a/drivers/isdn/mISDN/l1oip_core.c
+++ b/drivers/isdn/mISDN/l1oip_core.c
@@ -1236,8 +1236,8 @@ release_card(struct l1oip *hc)
 
 	hc->shutdown = true;
 
-	del_timer_sync(&hc->keep_tl);
-	del_timer_sync(&hc->timeout_tl);
+	timer_shutdown_sync(&hc->keep_tl);
+	timer_shutdown_sync(&hc->timeout_tl);
 
 	cancel_work_sync(&hc->workq);
 
diff --git a/drivers/isdn/mISDN/timerdev.c b/drivers/isdn/mISDN/timerdev.c
index abdf36ac3bee5..83d6b484d3c6c 100644
--- a/drivers/isdn/mISDN/timerdev.c
+++ b/drivers/isdn/mISDN/timerdev.c
@@ -74,7 +74,7 @@ mISDN_close(struct inode *ino, struct file *filep)
 	while (!list_empty(list)) {
 		timer = list_first_entry(list, struct mISDNtimer, list);
 		spin_unlock_irq(&dev->lock);
-		del_timer_sync(&timer->tl);
+		timer_shutdown_sync(&timer->tl);
 		spin_lock_irq(&dev->lock);
 		/* it might have been moved to ->expired */
 		list_del(&timer->list);
@@ -204,7 +204,7 @@ misdn_del_timer(struct mISDNtimerdev *dev, int id)
 			list_del_init(&timer->list);
 			timer->id = -1;
 			spin_unlock_irq(&dev->lock);
-			del_timer_sync(&timer->tl);
+			timer_shutdown_sync(&timer->tl);
 			kfree(timer);
 			return id;
 		}
diff --git a/drivers/leds/trigger/ledtrig-activity.c b/drivers/leds/trigger/ledtrig-activity.c
index 30bc9df036360..33cbf84136585 100644
--- a/drivers/leds/trigger/ledtrig-activity.c
+++ b/drivers/leds/trigger/ledtrig-activity.c
@@ -208,7 +208,7 @@ static void activity_deactivate(struct led_classdev *led_cdev)
 {
 	struct activity_data *activity_data = led_get_trigger_data(led_cdev);
 
-	del_timer_sync(&activity_data->timer);
+	timer_shutdown_sync(&activity_data->timer);
 	kfree(activity_data);
 	clear_bit(LED_BLINK_SW, &led_cdev->work_flags);
 }
diff --git a/drivers/leds/trigger/ledtrig-heartbeat.c b/drivers/leds/trigger/ledtrig-heartbeat.c
index 7fe0a05574d2a..393b3ae832f49 100644
--- a/drivers/leds/trigger/ledtrig-heartbeat.c
+++ b/drivers/leds/trigger/ledtrig-heartbeat.c
@@ -151,7 +151,7 @@ static void heartbeat_trig_deactivate(struct led_classdev *led_cdev)
 	struct heartbeat_trig_data *heartbeat_data =
 		led_get_trigger_data(led_cdev);
 
-	del_timer_sync(&heartbeat_data->timer);
+	timer_shutdown_sync(&heartbeat_data->timer);
 	kfree(heartbeat_data);
 	clear_bit(LED_BLINK_SW, &led_cdev->work_flags);
 }
diff --git a/drivers/leds/trigger/ledtrig-pattern.c b/drivers/leds/trigger/ledtrig-pattern.c
index 885ca63f383fb..fadd87dbe9930 100644
--- a/drivers/leds/trigger/ledtrig-pattern.c
+++ b/drivers/leds/trigger/ledtrig-pattern.c
@@ -430,7 +430,7 @@ static void pattern_trig_deactivate(struct led_classdev *led_cdev)
 	if (led_cdev->pattern_clear)
 		led_cdev->pattern_clear(led_cdev);
 
-	del_timer_sync(&data->timer);
+	timer_shutdown_sync(&data->timer);
 
 	led_set_brightness(led_cdev, LED_OFF);
 	kfree(data);
diff --git a/drivers/leds/trigger/ledtrig-transient.c b/drivers/leds/trigger/ledtrig-transient.c
index 80635183fac87..f111fa7635e5f 100644
--- a/drivers/leds/trigger/ledtrig-transient.c
+++ b/drivers/leds/trigger/ledtrig-transient.c
@@ -180,7 +180,7 @@ static void transient_trig_deactivate(struct led_classdev *led_cdev)
 {
 	struct transient_trig_data *transient_data = led_get_trigger_data(led_cdev);
 
-	del_timer_sync(&transient_data->timer);
+	timer_shutdown_sync(&transient_data->timer);
 	led_set_brightness_nosleep(led_cdev, transient_data->restore_state);
 	kfree(transient_data);
 }
diff --git a/drivers/media/pci/ivtv/ivtv-driver.c b/drivers/media/pci/ivtv/ivtv-driver.c
index f5846c22c799a..ba503d820e48e 100644
--- a/drivers/media/pci/ivtv/ivtv-driver.c
+++ b/drivers/media/pci/ivtv/ivtv-driver.c
@@ -1425,7 +1425,7 @@ static void ivtv_remove(struct pci_dev *pdev)
 
 	/* Interrupts */
 	ivtv_set_irq_mask(itv, 0xffffffff);
-	del_timer_sync(&itv->dma_timer);
+	timer_shutdown_sync(&itv->dma_timer);
 
 	/* Kill irq worker */
 	kthread_flush_worker(&itv->irq_worker);
diff --git a/drivers/media/usb/pvrusb2/pvrusb2-hdw.c b/drivers/media/usb/pvrusb2/pvrusb2-hdw.c
index 62ff1fa1c7539..75c89b07e86a0 100644
--- a/drivers/media/usb/pvrusb2/pvrusb2-hdw.c
+++ b/drivers/media/usb/pvrusb2/pvrusb2-hdw.c
@@ -2605,10 +2605,10 @@ struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
 	return hdw;
  fail:
 	if (hdw) {
-		del_timer_sync(&hdw->quiescent_timer);
-		del_timer_sync(&hdw->decoder_stabilization_timer);
-		del_timer_sync(&hdw->encoder_run_timer);
-		del_timer_sync(&hdw->encoder_wait_timer);
+		timer_shutdown_sync(&hdw->quiescent_timer);
+		timer_shutdown_sync(&hdw->decoder_stabilization_timer);
+		timer_shutdown_sync(&hdw->encoder_run_timer);
+		timer_shutdown_sync(&hdw->encoder_wait_timer);
 		flush_work(&hdw->workpoll);
 		v4l2_device_unregister(&hdw->v4l2_dev);
 		usb_free_urb(hdw->ctl_read_urb);
@@ -2668,10 +2668,10 @@ void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
 	if (!hdw) return;
 	pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
 	flush_work(&hdw->workpoll);
-	del_timer_sync(&hdw->quiescent_timer);
-	del_timer_sync(&hdw->decoder_stabilization_timer);
-	del_timer_sync(&hdw->encoder_run_timer);
-	del_timer_sync(&hdw->encoder_wait_timer);
+	timer_shutdown_sync(&hdw->quiescent_timer);
+	timer_shutdown_sync(&hdw->decoder_stabilization_timer);
+	timer_shutdown_sync(&hdw->encoder_run_timer);
+	timer_shutdown_sync(&hdw->encoder_wait_timer);
 	if (hdw->fw_buffer) {
 		kfree(hdw->fw_buffer);
 		hdw->fw_buffer = NULL;
diff --git a/drivers/media/usb/s2255/s2255drv.c b/drivers/media/usb/s2255/s2255drv.c
index acf18e2251a52..3c2627712fe9d 100644
--- a/drivers/media/usb/s2255/s2255drv.c
+++ b/drivers/media/usb/s2255/s2255drv.c
@@ -1487,7 +1487,7 @@ static void s2255_destroy(struct s2255_dev *dev)
 	/* board shutdown stops the read pipe if it is running */
 	s2255_board_shutdown(dev);
 	/* make sure firmware still not trying to load */
-	del_timer_sync(&dev->timer);  /* only started in .probe and .open */
+	timer_shutdown_sync(&dev->timer);  /* only started in .probe and .open */
 	if (dev->fw_data->fw_urb) {
 		usb_kill_urb(dev->fw_data->fw_urb);
 		usb_free_urb(dev->fw_data->fw_urb);
@@ -2322,7 +2322,7 @@ errorREQFW:
 errorFWDATA2:
 	usb_free_urb(dev->fw_data->fw_urb);
 errorFWURB:
-	del_timer_sync(&dev->timer);
+	timer_shutdown_sync(&dev->timer);
 errorEP:
 	usb_put_dev(dev->udev);
 errorUDEV:
diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c
index 94feea3b25998..53d0083e35daf 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_main.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_main.c
@@ -15586,7 +15586,7 @@ static int i40e_init_recovery_mode(struct i40e_pf *pf, struct i40e_hw *hw)
 
 err_switch_setup:
 	i40e_reset_interrupt_capability(pf);
-	del_timer_sync(&pf->service_timer);
+	timer_shutdown_sync(&pf->service_timer);
 	i40e_shutdown_adminq(hw);
 	iounmap(hw->hw_addr);
 	pci_disable_pcie_error_reporting(pf->pdev);
@@ -16205,7 +16205,7 @@ err_vsis:
 	kfree(pf->vsi);
 err_switch_setup:
 	i40e_reset_interrupt_capability(pf);
-	del_timer_sync(&pf->service_timer);
+	timer_shutdown_sync(&pf->service_timer);
 err_mac_addr:
 err_configure_lan_hmc:
 	(void)i40e_shutdown_lan_hmc(hw);
@@ -16267,7 +16267,7 @@ static void i40e_remove(struct pci_dev *pdev)
 	set_bit(__I40E_SUSPENDED, pf->state);
 	set_bit(__I40E_DOWN, pf->state);
 	if (pf->service_timer.function)
-		del_timer_sync(&pf->service_timer);
+		timer_shutdown_sync(&pf->service_timer);
 	if (pf->service_task.func)
 		cancel_work_sync(&pf->service_task);
 
diff --git a/drivers/net/ethernet/marvell/sky2.c b/drivers/net/ethernet/marvell/sky2.c
index ff97b140886ae..7c487f9b36ec6 100644
--- a/drivers/net/ethernet/marvell/sky2.c
+++ b/drivers/net/ethernet/marvell/sky2.c
@@ -5013,7 +5013,7 @@ static void sky2_remove(struct pci_dev *pdev)
 	if (!hw)
 		return;
 
-	del_timer_sync(&hw->watchdog_timer);
+	timer_shutdown_sync(&hw->watchdog_timer);
 	cancel_work_sync(&hw->restart_work);
 
 	for (i = hw->ports-1; i >= 0; --i)
diff --git a/drivers/net/ethernet/sun/sunvnet.c b/drivers/net/ethernet/sun/sunvnet.c
index acda6cbd0238d..fe86fbd585861 100644
--- a/drivers/net/ethernet/sun/sunvnet.c
+++ b/drivers/net/ethernet/sun/sunvnet.c
@@ -524,7 +524,7 @@ static void vnet_port_remove(struct vio_dev *vdev)
 		hlist_del_rcu(&port->hash);
 
 		synchronize_rcu();
-		del_timer_sync(&port->clean_timer);
+		timer_shutdown_sync(&port->clean_timer);
 		sunvnet_port_rm_txq_common(port);
 		netif_napi_del(&port->napi);
 		sunvnet_port_free_tx_bufs_common(port);
diff --git a/drivers/net/usb/sierra_net.c b/drivers/net/usb/sierra_net.c
index b3ae949e6f1c5..673d3aa837926 100644
--- a/drivers/net/usb/sierra_net.c
+++ b/drivers/net/usb/sierra_net.c
@@ -759,7 +759,7 @@ static void sierra_net_unbind(struct usbnet *dev, struct usb_interface *intf)
 	dev_dbg(&dev->udev->dev, "%s", __func__);
 
 	/* kill the timer and work */
-	del_timer_sync(&priv->sync_timer);
+	timer_shutdown_sync(&priv->sync_timer);
 	cancel_work_sync(&priv->sierra_net_kevent);
 
 	/* tell modem we are going away */
diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/btcoex.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/btcoex.c
index f9f18ff451ea7..7ea2631b80692 100644
--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/btcoex.c
+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/btcoex.c
@@ -394,7 +394,7 @@ void brcmf_btcoex_detach(struct brcmf_cfg80211_info *cfg)
 
 	if (cfg->btcoex->timer_on) {
 		cfg->btcoex->timer_on = false;
-		del_timer_sync(&cfg->btcoex->timer);
+		timer_shutdown_sync(&cfg->btcoex->timer);
 	}
 
 	cancel_work_sync(&cfg->btcoex->work);
diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c b/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c
index 6d6c129996454..48e7376a5fea7 100644
--- a/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c
+++ b/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c
@@ -371,7 +371,7 @@ void iwl_dbg_tlv_del_timers(struct iwl_trans *trans)
 	struct iwl_dbg_tlv_timer_node *node, *tmp;
 
 	list_for_each_entry_safe(node, tmp, timer_list, list) {
-		del_timer_sync(&node->timer);
+		timer_shutdown_sync(&node->timer);
 		list_del(&node->list);
 		kfree(node);
 	}
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/sta.c b/drivers/net/wireless/intel/iwlwifi/mvm/sta.c
index 6c9c5d6e77830..69634fb82a9bf 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/sta.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/sta.c
@@ -2835,7 +2835,7 @@ int iwl_mvm_sta_rx_agg(struct iwl_mvm *mvm, struct ieee80211_sta *sta,
 
 		/* synchronize all rx queues so we can safely delete */
 		iwl_mvm_free_reorder(mvm, baid_data);
-		del_timer_sync(&baid_data->session_timer);
+		timer_shutdown_sync(&baid_data->session_timer);
 		RCU_INIT_POINTER(mvm->baid_map[baid], NULL);
 		kfree_rcu(baid_data, rcu_head);
 		IWL_DEBUG_HT(mvm, "BAID %d is free\n", baid);
diff --git a/drivers/net/wireless/intersil/hostap/hostap_ap.c b/drivers/net/wireless/intersil/hostap/hostap_ap.c
index 462ccc7d7d1ac..9b546a71e7a2e 100644
--- a/drivers/net/wireless/intersil/hostap/hostap_ap.c
+++ b/drivers/net/wireless/intersil/hostap/hostap_ap.c
@@ -135,7 +135,7 @@ static void ap_free_sta(struct ap_data *ap, struct sta_info *sta)
 
 	if (!sta->ap)
 		kfree(sta->u.sta.challenge);
-	del_timer_sync(&sta->timer);
+	timer_shutdown_sync(&sta->timer);
 #endif /* PRISM2_NO_KERNEL_IEEE80211_MGMT */
 
 	kfree(sta);
diff --git a/drivers/net/wireless/marvell/mwifiex/main.c b/drivers/net/wireless/marvell/mwifiex/main.c
index da2e6557e6841..ea22a08e6c083 100644
--- a/drivers/net/wireless/marvell/mwifiex/main.c
+++ b/drivers/net/wireless/marvell/mwifiex/main.c
@@ -123,7 +123,7 @@ static int mwifiex_unregister(struct mwifiex_adapter *adapter)
 	if (adapter->if_ops.cleanup_if)
 		adapter->if_ops.cleanup_if(adapter);
 
-	del_timer_sync(&adapter->cmd_timer);
+	timer_shutdown_sync(&adapter->cmd_timer);
 
 	/* Free private structures */
 	for (i = 0; i < adapter->priv_num; i++) {
diff --git a/drivers/net/wireless/microchip/wilc1000/hif.c b/drivers/net/wireless/microchip/wilc1000/hif.c
index 67df8221b5aeb..5adc69d5bcae3 100644
--- a/drivers/net/wireless/microchip/wilc1000/hif.c
+++ b/drivers/net/wireless/microchip/wilc1000/hif.c
@@ -1531,10 +1531,10 @@ int wilc_deinit(struct wilc_vif *vif)
 
 	mutex_lock(&vif->wilc->deinit_lock);
 
-	del_timer_sync(&hif_drv->scan_timer);
-	del_timer_sync(&hif_drv->connect_timer);
+	timer_shutdown_sync(&hif_drv->scan_timer);
+	timer_shutdown_sync(&hif_drv->connect_timer);
 	del_timer_sync(&vif->periodic_rssi);
-	del_timer_sync(&hif_drv->remain_on_ch_timer);
+	timer_shutdown_sync(&hif_drv->remain_on_ch_timer);
 
 	if (hif_drv->usr_scan_req.scan_result) {
 		hif_drv->usr_scan_req.scan_result(SCAN_EVENT_ABORTED, NULL,
diff --git a/drivers/nfc/pn533/pn533.c b/drivers/nfc/pn533/pn533.c
index f0cac19005527..b19c39dcfbd93 100644
--- a/drivers/nfc/pn533/pn533.c
+++ b/drivers/nfc/pn533/pn533.c
@@ -2792,7 +2792,7 @@ void pn53x_common_clean(struct pn533 *priv)
 	struct pn533_cmd *cmd, *n;
 
 	/* delete the timer before cleanup the worker */
-	del_timer_sync(&priv->listen_timer);
+	timer_shutdown_sync(&priv->listen_timer);
 
 	flush_delayed_work(&priv->poll_work);
 	destroy_workqueue(priv->wq);
diff --git a/drivers/nfc/pn533/uart.c b/drivers/nfc/pn533/uart.c
index 07596bf5f7d6d..a556acdb947bb 100644
--- a/drivers/nfc/pn533/uart.c
+++ b/drivers/nfc/pn533/uart.c
@@ -310,7 +310,7 @@ static void pn532_uart_remove(struct serdev_device *serdev)
 	pn53x_unregister_nfc(pn532->priv);
 	serdev_device_close(serdev);
 	pn53x_common_clean(pn532->priv);
-	del_timer_sync(&pn532->cmd_timeout);
+	timer_shutdown_sync(&pn532->cmd_timeout);
 	kfree_skb(pn532->recv_skb);
 	kfree(pn532);
 }
diff --git a/drivers/pcmcia/bcm63xx_pcmcia.c b/drivers/pcmcia/bcm63xx_pcmcia.c
index bb06311d0b5f5..dd3c260990487 100644
--- a/drivers/pcmcia/bcm63xx_pcmcia.c
+++ b/drivers/pcmcia/bcm63xx_pcmcia.c
@@ -443,7 +443,7 @@ static int bcm63xx_drv_pcmcia_remove(struct platform_device *pdev)
 	struct resource *res;
 
 	skt = platform_get_drvdata(pdev);
-	del_timer_sync(&skt->timer);
+	timer_shutdown_sync(&skt->timer);
 	iounmap(skt->base);
 	iounmap(skt->io_base);
 	res = skt->reg_res;
diff --git a/drivers/pcmcia/electra_cf.c b/drivers/pcmcia/electra_cf.c
index 40a5cffe24a4c..efc27bc15152e 100644
--- a/drivers/pcmcia/electra_cf.c
+++ b/drivers/pcmcia/electra_cf.c
@@ -317,7 +317,7 @@ static int electra_cf_remove(struct platform_device *ofdev)
 	cf->active = 0;
 	pcmcia_unregister_socket(&cf->socket);
 	free_irq(cf->irq, cf);
-	del_timer_sync(&cf->timer);
+	timer_shutdown_sync(&cf->timer);
 
 	iounmap(cf->io_virt);
 	iounmap(cf->mem_base);
diff --git a/drivers/pcmcia/omap_cf.c b/drivers/pcmcia/omap_cf.c
index d3f827d4224a3..e613818dc0bc9 100644
--- a/drivers/pcmcia/omap_cf.c
+++ b/drivers/pcmcia/omap_cf.c
@@ -296,7 +296,7 @@ static int __exit omap_cf_remove(struct platform_device *pdev)
 
 	cf->active = 0;
 	pcmcia_unregister_socket(&cf->socket);
-	del_timer_sync(&cf->timer);
+	timer_shutdown_sync(&cf->timer);
 	release_mem_region(cf->phys_cf, SZ_8K);
 	free_irq(cf->irq, cf);
 	kfree(cf);
diff --git a/drivers/pcmcia/pd6729.c b/drivers/pcmcia/pd6729.c
index f0af9985ca092..a0a2e7f18356c 100644
--- a/drivers/pcmcia/pd6729.c
+++ b/drivers/pcmcia/pd6729.c
@@ -727,7 +727,7 @@ err_out_free_res2:
 	if (irq_mode == 1)
 		free_irq(dev->irq, socket);
 	else
-		del_timer_sync(&socket->poll_timer);
+		timer_shutdown_sync(&socket->poll_timer);
 err_out_free_res:
 	pci_release_regions(dev);
 err_out_disable:
@@ -754,7 +754,7 @@ static void pd6729_pci_remove(struct pci_dev *dev)
 	if (irq_mode == 1)
 		free_irq(dev->irq, socket);
 	else
-		del_timer_sync(&socket->poll_timer);
+		timer_shutdown_sync(&socket->poll_timer);
 	pci_release_regions(dev);
 	pci_disable_device(dev);
 
diff --git a/drivers/pcmcia/yenta_socket.c b/drivers/pcmcia/yenta_socket.c
index 3966a6ceb1ac7..1365eaa20ff49 100644
--- a/drivers/pcmcia/yenta_socket.c
+++ b/drivers/pcmcia/yenta_socket.c
@@ -814,7 +814,7 @@ static void yenta_close(struct pci_dev *dev)
 	if (sock->cb_irq)
 		free_irq(sock->cb_irq, sock);
 	else
-		del_timer_sync(&sock->poll_timer);
+		timer_shutdown_sync(&sock->poll_timer);
 
 	iounmap(sock->base);
 	yenta_free_resources(sock);
@@ -1285,7 +1285,7 @@ static int yenta_probe(struct pci_dev *dev, const struct pci_device_id *id)
 	if (socket->cb_irq)
 		free_irq(socket->cb_irq, socket);
 	else
-		del_timer_sync(&socket->poll_timer);
+		timer_shutdown_sync(&socket->poll_timer);
  unmap:
 	iounmap(socket->base);
 	yenta_free_resources(socket);
diff --git a/drivers/scsi/qla2xxx/qla_edif.c b/drivers/scsi/qla2xxx/qla_edif.c
index 00ccc41cef147..e4240aae5f9e3 100644
--- a/drivers/scsi/qla2xxx/qla_edif.c
+++ b/drivers/scsi/qla2xxx/qla_edif.c
@@ -416,7 +416,7 @@ static void __qla2x00_release_all_sadb(struct scsi_qla_host *vha,
 				 */
 				if (edif_entry->delete_sa_index !=
 						INVALID_EDIF_SA_INDEX) {
-					del_timer(&edif_entry->timer);
+					timer_shutdown(&edif_entry->timer);
 
 					/* build and send the aen */
 					fcport->edif.rx_sa_set = 1;
@@ -2799,7 +2799,7 @@ qla28xx_sa_update_iocb_entry(scsi_qla_host_t *v, struct req_que *req,
 			    "%s: removing edif_entry %p, new sa_index: 0x%x\n",
 			    __func__, edif_entry, pkt->sa_index);
 			qla_edif_list_delete_sa_index(sp->fcport, edif_entry);
-			del_timer(&edif_entry->timer);
+			timer_shutdown(&edif_entry->timer);
 
 			ql_dbg(ql_dbg_edif, vha, 0x5033,
 			    "%s: releasing edif_entry %p, new sa_index: 0x%x\n",
diff --git a/drivers/staging/media/atomisp/i2c/atomisp-lm3554.c b/drivers/staging/media/atomisp/i2c/atomisp-lm3554.c
index 75d16b525294f..c4ce4cd445d77 100644
--- a/drivers/staging/media/atomisp/i2c/atomisp-lm3554.c
+++ b/drivers/staging/media/atomisp/i2c/atomisp-lm3554.c
@@ -921,7 +921,7 @@ static void lm3554_remove(struct i2c_client *client)
 
 	atomisp_gmin_remove_subdev(sd);
 
-	del_timer_sync(&flash->flash_off_delay);
+	timer_shutdown_sync(&flash->flash_off_delay);
 
 	lm3554_gpio_uninit(client);
 
diff --git a/drivers/staging/wlan-ng/prism2usb.c b/drivers/staging/wlan-ng/prism2usb.c
index c13f1699e5a2f..80e36d03c4e25 100644
--- a/drivers/staging/wlan-ng/prism2usb.c
+++ b/drivers/staging/wlan-ng/prism2usb.c
@@ -170,9 +170,9 @@ static void prism2sta_disconnect_usb(struct usb_interface *interface)
 		 */
 		prism2sta_ifstate(wlandev, P80211ENUM_ifstate_disable);
 
-		del_timer_sync(&hw->throttle);
-		del_timer_sync(&hw->reqtimer);
-		del_timer_sync(&hw->resptimer);
+		timer_shutdown_sync(&hw->throttle);
+		timer_shutdown_sync(&hw->reqtimer);
+		timer_shutdown_sync(&hw->resptimer);
 
 		/* Unlink all the URBs. This "removes the wheels"
 		 * from the entire CTLX handling mechanism.
diff --git a/drivers/tty/n_gsm.c b/drivers/tty/n_gsm.c
index daf12132deb17..348d85c13f918 100644
--- a/drivers/tty/n_gsm.c
+++ b/drivers/tty/n_gsm.c
@@ -2444,7 +2444,7 @@ static void gsm_dlci_free(struct tty_port *port)
 {
 	struct gsm_dlci *dlci = container_of(port, struct gsm_dlci, port);
 
-	del_timer_sync(&dlci->t1);
+	timer_shutdown_sync(&dlci->t1);
 	dlci->gsm->dlci[dlci->addr] = NULL;
 	kfifo_free(&dlci->fifo);
 	while ((dlci->skb = skb_dequeue(&dlci->skb_list)))
diff --git a/drivers/tty/sysrq.c b/drivers/tty/sysrq.c
index d2b2720db6ca7..b6e70c5cfa174 100644
--- a/drivers/tty/sysrq.c
+++ b/drivers/tty/sysrq.c
@@ -1003,7 +1003,7 @@ static void sysrq_disconnect(struct input_handle *handle)
 
 	input_close_device(handle);
 	cancel_work_sync(&sysrq->reinject_work);
-	del_timer_sync(&sysrq->keyreset_timer);
+	timer_shutdown_sync(&sysrq->keyreset_timer);
 	input_unregister_handle(handle);
 	kfree(sysrq);
 }
diff --git a/drivers/usb/gadget/udc/m66592-udc.c b/drivers/usb/gadget/udc/m66592-udc.c
index 931e6362a13da..c7e421b449f36 100644
--- a/drivers/usb/gadget/udc/m66592-udc.c
+++ b/drivers/usb/gadget/udc/m66592-udc.c
@@ -1519,7 +1519,7 @@ static int m66592_remove(struct platform_device *pdev)
 
 	usb_del_gadget_udc(&m66592->gadget);
 
-	del_timer_sync(&m66592->timer);
+	timer_shutdown_sync(&m66592->timer);
 	iounmap(m66592->reg);
 	free_irq(platform_get_irq(pdev, 0), m66592);
 	m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
diff --git a/drivers/usb/serial/garmin_gps.c b/drivers/usb/serial/garmin_gps.c
index f1a8d83436236..670e942fdaaa1 100644
--- a/drivers/usb/serial/garmin_gps.c
+++ b/drivers/usb/serial/garmin_gps.c
@@ -1405,7 +1405,7 @@ static void garmin_port_remove(struct usb_serial_port *port)
 
 	usb_kill_anchored_urbs(&garmin_data_p->write_urbs);
 	usb_kill_urb(port->interrupt_in_urb);
-	del_timer_sync(&garmin_data_p->timer);
+	timer_shutdown_sync(&garmin_data_p->timer);
 	kfree(garmin_data_p);
 }
 
diff --git a/drivers/usb/serial/mos7840.c b/drivers/usb/serial/mos7840.c
index 6b12bb4648b83..73370eaae0abc 100644
--- a/drivers/usb/serial/mos7840.c
+++ b/drivers/usb/serial/mos7840.c
@@ -1725,8 +1725,8 @@ static void mos7840_port_remove(struct usb_serial_port *port)
 		/* Turn off LED */
 		mos7840_set_led_sync(port, MODEM_CONTROL_REGISTER, 0x0300);
 
-		del_timer_sync(&mos7840_port->led_timer1);
-		del_timer_sync(&mos7840_port->led_timer2);
+		timer_shutdown_sync(&mos7840_port->led_timer1);
+		timer_shutdown_sync(&mos7840_port->led_timer2);
 
 		usb_kill_urb(mos7840_port->led_urb);
 		usb_free_urb(mos7840_port->led_urb);
diff --git a/fs/ext4/super.c b/fs/ext4/super.c
index 16a343e8047d4..260c1b3e3ef2c 100644
--- a/fs/ext4/super.c
+++ b/fs/ext4/super.c
@@ -1225,7 +1225,7 @@ static void ext4_put_super(struct super_block *sb)
 	}
 
 	ext4_es_unregister_shrinker(sbi);
-	del_timer_sync(&sbi->s_err_report);
+	timer_shutdown_sync(&sbi->s_err_report);
 	ext4_release_system_zone(sb);
 	ext4_mb_release(sb);
 	ext4_ext_release(sb);
diff --git a/fs/nilfs2/segment.c b/fs/nilfs2/segment.c
index 3335ef3529155..76c3bd88b8582 100644
--- a/fs/nilfs2/segment.c
+++ b/fs/nilfs2/segment.c
@@ -2752,7 +2752,7 @@ static void nilfs_segctor_destroy(struct nilfs_sc_info *sci)
 
 	down_write(&nilfs->ns_segctor_sem);
 
-	del_timer_sync(&sci->sc_timer);
+	timer_shutdown_sync(&sci->sc_timer);
 	kfree(sci);
 }
 
diff --git a/net/802/garp.c b/net/802/garp.c
index 77aac27638353..ab24b21fbb493 100644
--- a/net/802/garp.c
+++ b/net/802/garp.c
@@ -618,7 +618,7 @@ void garp_uninit_applicant(struct net_device *dev, struct garp_application *appl
 
 	/* Delete timer and generate a final TRANSMIT_PDU event to flush out
 	 * all pending messages before the applicant is gone. */
-	del_timer_sync(&app->join_timer);
+	timer_shutdown_sync(&app->join_timer);
 
 	spin_lock_bh(&app->lock);
 	garp_gid_event(app, GARP_EVENT_TRANSMIT_PDU);
diff --git a/net/802/mrp.c b/net/802/mrp.c
index 66fcbf23b4868..eafc21ecc287d 100644
--- a/net/802/mrp.c
+++ b/net/802/mrp.c
@@ -911,8 +911,8 @@ void mrp_uninit_applicant(struct net_device *dev, struct mrp_application *appl)
 	/* Delete timer and generate a final TX event to flush out
 	 * all pending messages before the applicant is gone.
 	 */
-	del_timer_sync(&app->join_timer);
-	del_timer_sync(&app->periodic_timer);
+	timer_shutdown_sync(&app->join_timer);
+	timer_shutdown_sync(&app->periodic_timer);
 
 	spin_lock_bh(&app->lock);
 	mrp_mad_event(app, MRP_EVENT_TX);
diff --git a/net/bridge/br_multicast.c b/net/bridge/br_multicast.c
index 48170bd3785e1..dea1ee1bd0959 100644
--- a/net/bridge/br_multicast.c
+++ b/net/bridge/br_multicast.c
@@ -606,7 +606,7 @@ static void br_multicast_destroy_mdb_entry(struct net_bridge_mcast_gc *gc)
 	WARN_ON(!hlist_unhashed(&mp->mdb_node));
 	WARN_ON(mp->ports);
 
-	del_timer_sync(&mp->timer);
+	timer_shutdown_sync(&mp->timer);
 	kfree_rcu(mp, rcu);
 }
 
@@ -647,7 +647,7 @@ static void br_multicast_destroy_group_src(struct net_bridge_mcast_gc *gc)
 	src = container_of(gc, struct net_bridge_group_src, mcast_gc);
 	WARN_ON(!hlist_unhashed(&src->node));
 
-	del_timer_sync(&src->timer);
+	timer_shutdown_sync(&src->timer);
 	kfree_rcu(src, rcu);
 }
 
@@ -676,8 +676,8 @@ static void br_multicast_destroy_port_group(struct net_bridge_mcast_gc *gc)
 	WARN_ON(!hlist_unhashed(&pg->mglist));
 	WARN_ON(!hlist_empty(&pg->src_list));
 
-	del_timer_sync(&pg->rexmit_timer);
-	del_timer_sync(&pg->timer);
+	timer_shutdown_sync(&pg->rexmit_timer);
+	timer_shutdown_sync(&pg->timer);
 	kfree_rcu(pg, rcu);
 }
 
diff --git a/net/bridge/br_multicast_eht.c b/net/bridge/br_multicast_eht.c
index f91c071d16089..c126aa4e75512 100644
--- a/net/bridge/br_multicast_eht.c
+++ b/net/bridge/br_multicast_eht.c
@@ -142,7 +142,7 @@ static void br_multicast_destroy_eht_set_entry(struct net_bridge_mcast_gc *gc)
 	set_h = container_of(gc, struct net_bridge_group_eht_set_entry, mcast_gc);
 	WARN_ON(!RB_EMPTY_NODE(&set_h->rb_node));
 
-	del_timer_sync(&set_h->timer);
+	timer_shutdown_sync(&set_h->timer);
 	kfree(set_h);
 }
 
@@ -154,7 +154,7 @@ static void br_multicast_destroy_eht_set(struct net_bridge_mcast_gc *gc)
 	WARN_ON(!RB_EMPTY_NODE(&eht_set->rb_node));
 	WARN_ON(!RB_EMPTY_ROOT(&eht_set->entry_tree));
 
-	del_timer_sync(&eht_set->timer);
+	timer_shutdown_sync(&eht_set->timer);
 	kfree(eht_set);
 }
 
diff --git a/net/core/gen_estimator.c b/net/core/gen_estimator.c
index 4fcbdd71c59fa..fae9c4694186e 100644
--- a/net/core/gen_estimator.c
+++ b/net/core/gen_estimator.c
@@ -208,7 +208,7 @@ void gen_kill_estimator(struct net_rate_estimator __rcu **rate_est)
 
 	est = xchg((__force struct net_rate_estimator **)rate_est, NULL);
 	if (est) {
-		del_timer_sync(&est->timer);
+		timer_shutdown_sync(&est->timer);
 		kfree_rcu(est, rcu);
 	}
 }
diff --git a/net/ipv4/ipmr.c b/net/ipv4/ipmr.c
index b58df3c1bf7dc..eec1f6df80d80 100644
--- a/net/ipv4/ipmr.c
+++ b/net/ipv4/ipmr.c
@@ -412,7 +412,7 @@ static struct mr_table *ipmr_new_table(struct net *net, u32 id)
 
 static void ipmr_free_table(struct mr_table *mrt)
 {
-	del_timer_sync(&mrt->ipmr_expire_timer);
+	timer_shutdown_sync(&mrt->ipmr_expire_timer);
 	mroute_clean_tables(mrt, MRT_FLUSH_VIFS | MRT_FLUSH_VIFS_STATIC |
 				 MRT_FLUSH_MFC | MRT_FLUSH_MFC_STATIC);
 	rhltable_destroy(&mrt->mfc_hash);
diff --git a/net/ipv6/ip6mr.c b/net/ipv6/ip6mr.c
index 23e766597f362..51cf37abd142d 100644
--- a/net/ipv6/ip6mr.c
+++ b/net/ipv6/ip6mr.c
@@ -392,7 +392,7 @@ static struct mr_table *ip6mr_new_table(struct net *net, u32 id)
 
 static void ip6mr_free_table(struct mr_table *mrt)
 {
-	del_timer_sync(&mrt->ipmr_expire_timer);
+	timer_shutdown_sync(&mrt->ipmr_expire_timer);
 	mroute_clean_tables(mrt, MRT6_FLUSH_MIFS | MRT6_FLUSH_MIFS_STATIC |
 				 MRT6_FLUSH_MFC | MRT6_FLUSH_MFC_STATIC);
 	rhltable_destroy(&mrt->mfc_hash);
diff --git a/net/mac80211/mesh_pathtbl.c b/net/mac80211/mesh_pathtbl.c
index 69d5e1ec6edef..3b81e6df3f344 100644
--- a/net/mac80211/mesh_pathtbl.c
+++ b/net/mac80211/mesh_pathtbl.c
@@ -512,7 +512,7 @@ static void mesh_path_free_rcu(struct mesh_table *tbl,
 	mpath->flags |= MESH_PATH_RESOLVING | MESH_PATH_DELETED;
 	mesh_gate_del(tbl, mpath);
 	spin_unlock_bh(&mpath->state_lock);
-	del_timer_sync(&mpath->timer);
+	timer_shutdown_sync(&mpath->timer);
 	atomic_dec(&sdata->u.mesh.mpaths);
 	atomic_dec(&tbl->entries);
 	mesh_path_flush_pending(mpath);
diff --git a/net/netfilter/ipset/ip_set_list_set.c b/net/netfilter/ipset/ip_set_list_set.c
index 5a67f79665742..e162636525cfb 100644
--- a/net/netfilter/ipset/ip_set_list_set.c
+++ b/net/netfilter/ipset/ip_set_list_set.c
@@ -427,7 +427,7 @@ list_set_destroy(struct ip_set *set)
 	struct set_elem *e, *n;
 
 	if (SET_WITH_TIMEOUT(set))
-		del_timer_sync(&map->gc);
+		timer_shutdown_sync(&map->gc);
 
 	list_for_each_entry_safe(e, n, &map->members, list) {
 		list_del(&e->list);
diff --git a/net/netfilter/ipvs/ip_vs_lblc.c b/net/netfilter/ipvs/ip_vs_lblc.c
index 7ac7473e3804c..1b87214d385eb 100644
--- a/net/netfilter/ipvs/ip_vs_lblc.c
+++ b/net/netfilter/ipvs/ip_vs_lblc.c
@@ -384,7 +384,7 @@ static void ip_vs_lblc_done_svc(struct ip_vs_service *svc)
 	struct ip_vs_lblc_table *tbl = svc->sched_data;
 
 	/* remove periodic timer */
-	del_timer_sync(&tbl->periodic_timer);
+	timer_shutdown_sync(&tbl->periodic_timer);
 
 	/* got to clean up table entries here */
 	ip_vs_lblc_flush(svc);
diff --git a/net/netfilter/ipvs/ip_vs_lblcr.c b/net/netfilter/ipvs/ip_vs_lblcr.c
index 77c323c36a889..ad8f5fea6d3a1 100644
--- a/net/netfilter/ipvs/ip_vs_lblcr.c
+++ b/net/netfilter/ipvs/ip_vs_lblcr.c
@@ -547,7 +547,7 @@ static void ip_vs_lblcr_done_svc(struct ip_vs_service *svc)
 	struct ip_vs_lblcr_table *tbl = svc->sched_data;
 
 	/* remove periodic timer */
-	del_timer_sync(&tbl->periodic_timer);
+	timer_shutdown_sync(&tbl->periodic_timer);
 
 	/* got to clean up table entries here */
 	ip_vs_lblcr_flush(svc);
diff --git a/net/netfilter/xt_IDLETIMER.c b/net/netfilter/xt_IDLETIMER.c
index 0f8bb0bf558f9..8d36303f39351 100644
--- a/net/netfilter/xt_IDLETIMER.c
+++ b/net/netfilter/xt_IDLETIMER.c
@@ -413,7 +413,7 @@ static void idletimer_tg_destroy(const struct xt_tgdtor_param *par)
 		pr_debug("deleting timer %s\n", info->label);
 
 		list_del(&info->timer->entry);
-		del_timer_sync(&info->timer->timer);
+		timer_shutdown_sync(&info->timer->timer);
 		cancel_work_sync(&info->timer->work);
 		sysfs_remove_file(idletimer_tg_kobj, &info->timer->attr.attr);
 		kfree(info->timer->attr.attr.name);
@@ -441,7 +441,7 @@ static void idletimer_tg_destroy_v1(const struct xt_tgdtor_param *par)
 		if (info->timer->timer_type & XT_IDLETIMER_ALARM) {
 			alarm_cancel(&info->timer->alarm);
 		} else {
-			del_timer_sync(&info->timer->timer);
+			timer_shutdown_sync(&info->timer->timer);
 		}
 		cancel_work_sync(&info->timer->work);
 		sysfs_remove_file(idletimer_tg_kobj, &info->timer->attr.attr);
diff --git a/net/netfilter/xt_LED.c b/net/netfilter/xt_LED.c
index 0371c387b0d1f..66b0f941d8fbb 100644
--- a/net/netfilter/xt_LED.c
+++ b/net/netfilter/xt_LED.c
@@ -166,7 +166,7 @@ static void led_tg_destroy(const struct xt_tgdtor_param *par)
 
 	list_del(&ledinternal->list);
 
-	del_timer_sync(&ledinternal->timer);
+	timer_shutdown_sync(&ledinternal->timer);
 
 	led_trigger_unregister(&ledinternal->netfilter_led_trigger);
 
diff --git a/net/sched/cls_flow.c b/net/sched/cls_flow.c
index 535668e1f748d..6ab317b48d6c3 100644
--- a/net/sched/cls_flow.c
+++ b/net/sched/cls_flow.c
@@ -369,7 +369,7 @@ static const struct nla_policy flow_policy[TCA_FLOW_MAX + 1] = {
 
 static void __flow_destroy_filter(struct flow_filter *f)
 {
-	del_timer_sync(&f->perturb_timer);
+	timer_shutdown_sync(&f->perturb_timer);
 	tcf_exts_destroy(&f->exts);
 	tcf_em_tree_destroy(&f->ematches);
 	tcf_exts_put_net(&f->exts);
diff --git a/net/sunrpc/svc.c b/net/sunrpc/svc.c
index 8f1b596db33fc..85f0c3cfc8774 100644
--- a/net/sunrpc/svc.c
+++ b/net/sunrpc/svc.c
@@ -567,7 +567,7 @@ svc_destroy(struct kref *ref)
 	struct svc_serv *serv = container_of(ref, struct svc_serv, sv_refcnt);
 
 	dprintk("svc: svc_destroy(%s)\n", serv->sv_program->pg_name);
-	del_timer_sync(&serv->sv_temptimer);
+	timer_shutdown_sync(&serv->sv_temptimer);
 
 	/*
 	 * The last user is gone and thus all sockets have to be destroyed to
diff --git a/net/tipc/discover.c b/net/tipc/discover.c
index e8dcdf267c0c3..685389d4b245e 100644
--- a/net/tipc/discover.c
+++ b/net/tipc/discover.c
@@ -388,7 +388,7 @@ int tipc_disc_create(struct net *net, struct tipc_bearer *b,
  */
 void tipc_disc_delete(struct tipc_discoverer *d)
 {
-	del_timer_sync(&d->timer);
+	timer_shutdown_sync(&d->timer);
 	kfree_skb(d->skb);
 	kfree(d);
 }
diff --git a/net/tipc/monitor.c b/net/tipc/monitor.c
index 9618e4429f0fe..77a3d016cadec 100644
--- a/net/tipc/monitor.c
+++ b/net/tipc/monitor.c
@@ -700,7 +700,7 @@ void tipc_mon_delete(struct net *net, int bearer_id)
 	}
 	mon->self = NULL;
 	write_unlock_bh(&mon->lock);
-	del_timer_sync(&mon->timer);
+	timer_shutdown_sync(&mon->timer);
 	kfree(self->domain);
 	kfree(self);
 	kfree(mon);
diff --git a/sound/i2c/other/ak4117.c b/sound/i2c/other/ak4117.c
index 1bc43e927d824..640501bb3ca63 100644
--- a/sound/i2c/other/ak4117.c
+++ b/sound/i2c/other/ak4117.c
@@ -47,7 +47,7 @@ static void reg_dump(struct ak4117 *ak4117)
 
 static void snd_ak4117_free(struct ak4117 *chip)
 {
-	del_timer_sync(&chip->timer);
+	timer_shutdown_sync(&chip->timer);
 	kfree(chip);
 }
 
diff --git a/sound/synth/emux/emux.c b/sound/synth/emux/emux.c
index a870759d179ed..0006c3ddb51d6 100644
--- a/sound/synth/emux/emux.c
+++ b/sound/synth/emux/emux.c
@@ -129,7 +129,7 @@ int snd_emux_free(struct snd_emux *emu)
 	if (! emu)
 		return -EINVAL;
 
-	del_timer_sync(&emu->tlist);
+	timer_shutdown_sync(&emu->tlist);
 
 	snd_emux_proc_free(emu);
 	snd_emux_delete_virmidi(emu);
-- 
GitLab


From 1b929c02afd37871d5afb9d498426f83432e71c2 Mon Sep 17 00:00:00 2001
From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sun, 25 Dec 2022 13:41:39 -0800
Subject: [PATCH 670/875] Linux 6.2-rc1

---
 Makefile | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index 25247f9318722..d4b6af8c09e9c 100644
--- a/Makefile
+++ b/Makefile
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0
 VERSION = 6
-PATCHLEVEL = 1
+PATCHLEVEL = 2
 SUBLEVEL = 0
-EXTRAVERSION =
+EXTRAVERSION = -rc1
 NAME = Hurr durr I'ma ninja sloth
 
 # *DOCUMENTATION*
-- 
GitLab


From 8508fa2e7472f673edbeedf1b1d2b7a6bb898ecc Mon Sep 17 00:00:00 2001
From: Artem Egorkine <arteme@gmail.com>
Date: Sun, 25 Dec 2022 12:57:27 +0200
Subject: [PATCH 671/875] ALSA: line6: correct midi status byte when receiving
 data from podxt

A PODxt device sends 0xb2, 0xc2 or 0xf2 as a status byte for MIDI
messages over USB that should otherwise have a 0xb0, 0xc0 or 0xf0
status byte. This is usually corrected by the driver on other OSes.

This fixes MIDI sysex messages sent by PODxt.

[ tiwai: fixed white spaces ]

Signed-off-by: Artem Egorkine <arteme@gmail.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20221225105728.1153989-1-arteme@gmail.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/usb/line6/driver.c  |  3 ++-
 sound/usb/line6/midi.c    |  3 ++-
 sound/usb/line6/midibuf.c | 25 +++++++++++++++++--------
 sound/usb/line6/midibuf.h |  5 ++++-
 sound/usb/line6/pod.c     |  3 ++-
 5 files changed, 27 insertions(+), 12 deletions(-)

diff --git a/sound/usb/line6/driver.c b/sound/usb/line6/driver.c
index 59faa5a9a7141..b67617b68e509 100644
--- a/sound/usb/line6/driver.c
+++ b/sound/usb/line6/driver.c
@@ -304,7 +304,8 @@ static void line6_data_received(struct urb *urb)
 		for (;;) {
 			done =
 				line6_midibuf_read(mb, line6->buffer_message,
-						LINE6_MIDI_MESSAGE_MAXLEN);
+						   LINE6_MIDI_MESSAGE_MAXLEN,
+						   LINE6_MIDIBUF_READ_RX);
 
 			if (done <= 0)
 				break;
diff --git a/sound/usb/line6/midi.c b/sound/usb/line6/midi.c
index ba0e2b7e8fe19..d52355de2bbc0 100644
--- a/sound/usb/line6/midi.c
+++ b/sound/usb/line6/midi.c
@@ -56,7 +56,8 @@ static void line6_midi_transmit(struct snd_rawmidi_substream *substream)
 
 	for (;;) {
 		done = line6_midibuf_read(mb, chunk,
-					  LINE6_FALLBACK_MAXPACKETSIZE);
+					  LINE6_FALLBACK_MAXPACKETSIZE,
+					  LINE6_MIDIBUF_READ_TX);
 
 		if (done == 0)
 			break;
diff --git a/sound/usb/line6/midibuf.c b/sound/usb/line6/midibuf.c
index 6a70463f82c4e..e7f830f7526c9 100644
--- a/sound/usb/line6/midibuf.c
+++ b/sound/usb/line6/midibuf.c
@@ -9,6 +9,7 @@
 
 #include "midibuf.h"
 
+
 static int midibuf_message_length(unsigned char code)
 {
 	int message_length;
@@ -20,12 +21,7 @@ static int midibuf_message_length(unsigned char code)
 
 		message_length = length[(code >> 4) - 8];
 	} else {
-		/*
-		   Note that according to the MIDI specification 0xf2 is
-		   the "Song Position Pointer", but this is used by Line 6
-		   to send sysex messages to the host.
-		 */
-		static const int length[] = { -1, 2, -1, 2, -1, -1, 1, 1, 1, 1,
+		static const int length[] = { -1, 2, 2, 2, -1, -1, 1, 1, 1, -1,
 			1, 1, 1, -1, 1, 1
 		};
 		message_length = length[code & 0x0f];
@@ -125,7 +121,7 @@ int line6_midibuf_write(struct midi_buffer *this, unsigned char *data,
 }
 
 int line6_midibuf_read(struct midi_buffer *this, unsigned char *data,
-		       int length)
+		       int length, int read_type)
 {
 	int bytes_used;
 	int length1, length2;
@@ -148,9 +144,22 @@ int line6_midibuf_read(struct midi_buffer *this, unsigned char *data,
 
 	length1 = this->size - this->pos_read;
 
-	/* check MIDI command length */
 	command = this->buf[this->pos_read];
+	/*
+	   PODxt always has status byte lower nibble set to 0010,
+	   when it means to send 0000, so we correct if here so
+	   that control/program changes come on channel 1 and
+	   sysex message status byte is correct
+	 */
+	if (read_type == LINE6_MIDIBUF_READ_RX) {
+		if (command == 0xb2 || command == 0xc2 || command == 0xf2) {
+			unsigned char fixed = command & 0xf0;
+			this->buf[this->pos_read] = fixed;
+			command = fixed;
+		}
+	}
 
+	/* check MIDI command length */
 	if (command & 0x80) {
 		midi_length = midibuf_message_length(command);
 		this->command_prev = command;
diff --git a/sound/usb/line6/midibuf.h b/sound/usb/line6/midibuf.h
index 124a8f9f7e96c..542e8d836f87d 100644
--- a/sound/usb/line6/midibuf.h
+++ b/sound/usb/line6/midibuf.h
@@ -8,6 +8,9 @@
 #ifndef MIDIBUF_H
 #define MIDIBUF_H
 
+#define LINE6_MIDIBUF_READ_TX 0
+#define LINE6_MIDIBUF_READ_RX 1
+
 struct midi_buffer {
 	unsigned char *buf;
 	int size;
@@ -23,7 +26,7 @@ extern void line6_midibuf_destroy(struct midi_buffer *mb);
 extern int line6_midibuf_ignore(struct midi_buffer *mb, int length);
 extern int line6_midibuf_init(struct midi_buffer *mb, int size, int split);
 extern int line6_midibuf_read(struct midi_buffer *mb, unsigned char *data,
-			      int length);
+			      int length, int read_type);
 extern void line6_midibuf_reset(struct midi_buffer *mb);
 extern int line6_midibuf_write(struct midi_buffer *mb, unsigned char *data,
 			       int length);
diff --git a/sound/usb/line6/pod.c b/sound/usb/line6/pod.c
index cd41aa7f03851..d173971e5f029 100644
--- a/sound/usb/line6/pod.c
+++ b/sound/usb/line6/pod.c
@@ -159,8 +159,9 @@ static struct line6_pcm_properties pod_pcm_properties = {
 	.bytes_per_channel = 3 /* SNDRV_PCM_FMTBIT_S24_3LE */
 };
 
+
 static const char pod_version_header[] = {
-	0xf2, 0x7e, 0x7f, 0x06, 0x02
+	0xf0, 0x7e, 0x7f, 0x06, 0x02
 };
 
 static char *pod_alloc_sysex_buffer(struct usb_line6_pod *pod, int code,
-- 
GitLab


From b8800d324abb50160560c636bfafe2c81001b66c Mon Sep 17 00:00:00 2001
From: Artem Egorkine <arteme@gmail.com>
Date: Sun, 25 Dec 2022 12:57:28 +0200
Subject: [PATCH 672/875] ALSA: line6: fix stack overflow in
 line6_midi_transmit

Correctly calculate available space including the size of the chunk
buffer. This fixes a buffer overflow when multiple MIDI sysex
messages are sent to a PODxt device.

Signed-off-by: Artem Egorkine <arteme@gmail.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20221225105728.1153989-2-arteme@gmail.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/usb/line6/midi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/sound/usb/line6/midi.c b/sound/usb/line6/midi.c
index d52355de2bbc0..0838632c788e4 100644
--- a/sound/usb/line6/midi.c
+++ b/sound/usb/line6/midi.c
@@ -44,7 +44,8 @@ static void line6_midi_transmit(struct snd_rawmidi_substream *substream)
 	int req, done;
 
 	for (;;) {
-		req = min(line6_midibuf_bytes_free(mb), line6->max_packet_size);
+		req = min3(line6_midibuf_bytes_free(mb), line6->max_packet_size,
+			   LINE6_FALLBACK_MAXPACKETSIZE);
 		done = snd_rawmidi_transmit_peek(substream, chunk, req);
 
 		if (done == 0)
-- 
GitLab


From 399ab7fe0fa0d846881685fd4e57e9a8ef7559f7 Mon Sep 17 00:00:00 2001
From: Hawkins Jiawei <yin31149@gmail.com>
Date: Thu, 22 Dec 2022 11:51:19 +0800
Subject: [PATCH 673/875] net: sched: fix memory leak in tcindex_set_parms

Syzkaller reports a memory leak as follows:
====================================
BUG: memory leak
unreferenced object 0xffff88810c287f00 (size 256):
  comm "syz-executor105", pid 3600, jiffies 4294943292 (age 12.990s)
  hex dump (first 32 bytes):
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
  backtrace:
    [<ffffffff814cf9f0>] kmalloc_trace+0x20/0x90 mm/slab_common.c:1046
    [<ffffffff839c9e07>] kmalloc include/linux/slab.h:576 [inline]
    [<ffffffff839c9e07>] kmalloc_array include/linux/slab.h:627 [inline]
    [<ffffffff839c9e07>] kcalloc include/linux/slab.h:659 [inline]
    [<ffffffff839c9e07>] tcf_exts_init include/net/pkt_cls.h:250 [inline]
    [<ffffffff839c9e07>] tcindex_set_parms+0xa7/0xbe0 net/sched/cls_tcindex.c:342
    [<ffffffff839caa1f>] tcindex_change+0xdf/0x120 net/sched/cls_tcindex.c:553
    [<ffffffff8394db62>] tc_new_tfilter+0x4f2/0x1100 net/sched/cls_api.c:2147
    [<ffffffff8389e91c>] rtnetlink_rcv_msg+0x4dc/0x5d0 net/core/rtnetlink.c:6082
    [<ffffffff839eba67>] netlink_rcv_skb+0x87/0x1d0 net/netlink/af_netlink.c:2540
    [<ffffffff839eab87>] netlink_unicast_kernel net/netlink/af_netlink.c:1319 [inline]
    [<ffffffff839eab87>] netlink_unicast+0x397/0x4c0 net/netlink/af_netlink.c:1345
    [<ffffffff839eb046>] netlink_sendmsg+0x396/0x710 net/netlink/af_netlink.c:1921
    [<ffffffff8383e796>] sock_sendmsg_nosec net/socket.c:714 [inline]
    [<ffffffff8383e796>] sock_sendmsg+0x56/0x80 net/socket.c:734
    [<ffffffff8383eb08>] ____sys_sendmsg+0x178/0x410 net/socket.c:2482
    [<ffffffff83843678>] ___sys_sendmsg+0xa8/0x110 net/socket.c:2536
    [<ffffffff838439c5>] __sys_sendmmsg+0x105/0x330 net/socket.c:2622
    [<ffffffff83843c14>] __do_sys_sendmmsg net/socket.c:2651 [inline]
    [<ffffffff83843c14>] __se_sys_sendmmsg net/socket.c:2648 [inline]
    [<ffffffff83843c14>] __x64_sys_sendmmsg+0x24/0x30 net/socket.c:2648
    [<ffffffff84605fd5>] do_syscall_x64 arch/x86/entry/common.c:50 [inline]
    [<ffffffff84605fd5>] do_syscall_64+0x35/0xb0 arch/x86/entry/common.c:80
    [<ffffffff84800087>] entry_SYSCALL_64_after_hwframe+0x63/0xcd
====================================

Kernel uses tcindex_change() to change an existing
filter properties.

Yet the problem is that, during the process of changing,
if `old_r` is retrieved from `p->perfect`, then
kernel uses tcindex_alloc_perfect_hash() to newly
allocate filter results, uses tcindex_filter_result_init()
to clear the old filter result, without destroying
its tcf_exts structure, which triggers the above memory leak.

To be more specific, there are only two source for the `old_r`,
according to the tcindex_lookup(). `old_r` is retrieved from
`p->perfect`, or `old_r` is retrieved from `p->h`.

  * If `old_r` is retrieved from `p->perfect`, kernel uses
tcindex_alloc_perfect_hash() to newly allocate the
filter results. Then `r` is assigned with `cp->perfect + handle`,
which is newly allocated. So condition `old_r && old_r != r` is
true in this situation, and kernel uses tcindex_filter_result_init()
to clear the old filter result, without destroying
its tcf_exts structure

  * If `old_r` is retrieved from `p->h`, then `p->perfect` is NULL
according to the tcindex_lookup(). Considering that `cp->h`
is directly copied from `p->h` and `p->perfect` is NULL,
`r` is assigned with `tcindex_lookup(cp, handle)`, whose value
should be the same as `old_r`, so condition `old_r && old_r != r`
is false in this situation, kernel ignores using
tcindex_filter_result_init() to clear the old filter result.

So only when `old_r` is retrieved from `p->perfect` does kernel use
tcindex_filter_result_init() to clear the old filter result, which
triggers the above memory leak.

Considering that there already exists a tc_filter_wq workqueue
to destroy the old tcindex_data by tcindex_partial_destroy_work()
at the end of tcindex_set_parms(), this patch solves
this memory leak bug by removing this old filter result
clearing part and delegating it to the tc_filter_wq workqueue.

Note that this patch doesn't introduce any other issues. If
`old_r` is retrieved from `p->perfect`, this patch just
delegates old filter result clearing part to the
tc_filter_wq workqueue; If `old_r` is retrieved from `p->h`,
kernel doesn't reach the old filter result clearing part, so
removing this part has no effect.

[Thanks to the suggestion from Jakub Kicinski, Cong Wang, Paolo Abeni
and Dmitry Vyukov]

Fixes: b9a24bb76bf6 ("net_sched: properly handle failure case of tcf_exts_init()")
Link: https://lore.kernel.org/all/0000000000001de5c505ebc9ec59@google.com/
Reported-by: syzbot+232ebdbd36706c965ebf@syzkaller.appspotmail.com
Tested-by: syzbot+232ebdbd36706c965ebf@syzkaller.appspotmail.com
Cc: Cong Wang <cong.wang@bytedance.com>
Cc: Jakub Kicinski <kuba@kernel.org>
Cc: Paolo Abeni <pabeni@redhat.com>
Cc: Dmitry Vyukov <dvyukov@google.com>
Acked-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/sched/cls_tcindex.c | 12 ++----------
 1 file changed, 2 insertions(+), 10 deletions(-)

diff --git a/net/sched/cls_tcindex.c b/net/sched/cls_tcindex.c
index eb0e9458e722e..ee2a050c887bf 100644
--- a/net/sched/cls_tcindex.c
+++ b/net/sched/cls_tcindex.c
@@ -333,7 +333,7 @@ tcindex_set_parms(struct net *net, struct tcf_proto *tp, unsigned long base,
 		  struct tcindex_filter_result *r, struct nlattr **tb,
 		  struct nlattr *est, u32 flags, struct netlink_ext_ack *extack)
 {
-	struct tcindex_filter_result new_filter_result, *old_r = r;
+	struct tcindex_filter_result new_filter_result;
 	struct tcindex_data *cp = NULL, *oldp;
 	struct tcindex_filter *f = NULL; /* make gcc behave */
 	struct tcf_result cr = {};
@@ -402,7 +402,7 @@ tcindex_set_parms(struct net *net, struct tcf_proto *tp, unsigned long base,
 	err = tcindex_filter_result_init(&new_filter_result, cp, net);
 	if (err < 0)
 		goto errout_alloc;
-	if (old_r)
+	if (r)
 		cr = r->res;
 
 	err = -EBUSY;
@@ -479,14 +479,6 @@ tcindex_set_parms(struct net *net, struct tcf_proto *tp, unsigned long base,
 		tcf_bind_filter(tp, &cr, base);
 	}
 
-	if (old_r && old_r != r) {
-		err = tcindex_filter_result_init(old_r, cp, net);
-		if (err < 0) {
-			kfree(f);
-			goto errout_alloc;
-		}
-	}
-
 	oldp = p;
 	r->res = cr;
 	tcf_exts_change(&r->exts, &e);
-- 
GitLab


From 13a7c8964afcd8ca43c0b6001ebb0127baa95362 Mon Sep 17 00:00:00 2001
From: Daniil Tatianin <d-tatianin@yandex-team.ru>
Date: Thu, 22 Dec 2022 14:52:28 +0300
Subject: [PATCH 674/875] qlcnic: prevent ->dcb use-after-free on
 qlcnic_dcb_enable() failure

adapter->dcb would get silently freed inside qlcnic_dcb_enable() in
case qlcnic_dcb_attach() would return an error, which always happens
under OOM conditions. This would lead to use-after-free because both
of the existing callers invoke qlcnic_dcb_get_info() on the obtained
pointer, which is potentially freed at that point.

Propagate errors from qlcnic_dcb_enable(), and instead free the dcb
pointer at callsite using qlcnic_dcb_free(). This also removes the now
unused qlcnic_clear_dcb_ops() helper, which was a simple wrapper around
kfree() also causing memory leaks for partially initialized dcb.

Found by Linux Verification Center (linuxtesting.org) with the SVACE
static analysis tool.

Fixes: 3c44bba1d270 ("qlcnic: Disable DCB operations from SR-IOV VFs")
Reviewed-by: Michal Swiatkowski <michal.swiatkowski@linux.intel.com>
Signed-off-by: Daniil Tatianin <d-tatianin@yandex-team.ru>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c |  8 +++++++-
 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.h       | 10 ++--------
 drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c      |  8 +++++++-
 3 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c
index dbb800769cb63..c95d56e56c59a 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c
@@ -2505,7 +2505,13 @@ int qlcnic_83xx_init(struct qlcnic_adapter *adapter)
 		goto disable_mbx_intr;
 
 	qlcnic_83xx_clear_function_resources(adapter);
-	qlcnic_dcb_enable(adapter->dcb);
+
+	err = qlcnic_dcb_enable(adapter->dcb);
+	if (err) {
+		qlcnic_dcb_free(adapter->dcb);
+		goto disable_mbx_intr;
+	}
+
 	qlcnic_83xx_initialize_nic(adapter, 1);
 	qlcnic_dcb_get_info(adapter->dcb);
 
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.h b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.h
index 7519773eaca6e..22afa2be85fdb 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.h
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.h
@@ -41,11 +41,6 @@ struct qlcnic_dcb {
 	unsigned long			state;
 };
 
-static inline void qlcnic_clear_dcb_ops(struct qlcnic_dcb *dcb)
-{
-	kfree(dcb);
-}
-
 static inline int qlcnic_dcb_get_hw_capability(struct qlcnic_dcb *dcb)
 {
 	if (dcb && dcb->ops->get_hw_capability)
@@ -112,9 +107,8 @@ static inline void qlcnic_dcb_init_dcbnl_ops(struct qlcnic_dcb *dcb)
 		dcb->ops->init_dcbnl_ops(dcb);
 }
 
-static inline void qlcnic_dcb_enable(struct qlcnic_dcb *dcb)
+static inline int qlcnic_dcb_enable(struct qlcnic_dcb *dcb)
 {
-	if (dcb && qlcnic_dcb_attach(dcb))
-		qlcnic_clear_dcb_ops(dcb);
+	return dcb ? qlcnic_dcb_attach(dcb) : 0;
 }
 #endif
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c
index 28476b982bab6..44dac3c0908eb 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c
@@ -2599,7 +2599,13 @@ qlcnic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 			 "Device does not support MSI interrupts\n");
 
 	if (qlcnic_82xx_check(adapter)) {
-		qlcnic_dcb_enable(adapter->dcb);
+		err = qlcnic_dcb_enable(adapter->dcb);
+		if (err) {
+			qlcnic_dcb_free(adapter->dcb);
+			dev_err(&pdev->dev, "Failed to enable DCB\n");
+			goto err_out_free_hw;
+		}
+
 		qlcnic_dcb_get_info(adapter->dcb);
 		err = qlcnic_setup_intr(adapter);
 
-- 
GitLab


From 30e725537546248bddc12eaac2fe0a258917f190 Mon Sep 17 00:00:00 2001
From: "Johnny S. Lee" <foss@jsl.io>
Date: Thu, 22 Dec 2022 22:34:05 +0800
Subject: [PATCH 675/875] net: dsa: mv88e6xxx: depend on PTP conditionally

PTP hardware timestamping related objects are not linked when PTP
support for MV88E6xxx (NET_DSA_MV88E6XXX_PTP) is disabled, therefore
NET_DSA_MV88E6XXX should not depend on PTP_1588_CLOCK_OPTIONAL
regardless of NET_DSA_MV88E6XXX_PTP.

Instead, condition more strictly on how NET_DSA_MV88E6XXX_PTP's
dependencies are met, making sure that it cannot be enabled when
NET_DSA_MV88E6XXX=y and PTP_1588_CLOCK=m.

In other words, this commit allows NET_DSA_MV88E6XXX to be built-in
while PTP_1588_CLOCK is a module, as long as NET_DSA_MV88E6XXX_PTP is
prevented from being enabled.

Fixes: e5f31552674e ("ethernet: fix PTP_1588_CLOCK dependencies")
Signed-off-by: Johnny S. Lee <foss@jsl.io>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/dsa/mv88e6xxx/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/dsa/mv88e6xxx/Kconfig b/drivers/net/dsa/mv88e6xxx/Kconfig
index 7a2445a34eb77..e3181d5471dfe 100644
--- a/drivers/net/dsa/mv88e6xxx/Kconfig
+++ b/drivers/net/dsa/mv88e6xxx/Kconfig
@@ -2,7 +2,6 @@
 config NET_DSA_MV88E6XXX
 	tristate "Marvell 88E6xxx Ethernet switch fabric support"
 	depends on NET_DSA
-	depends on PTP_1588_CLOCK_OPTIONAL
 	select IRQ_DOMAIN
 	select NET_DSA_TAG_EDSA
 	select NET_DSA_TAG_DSA
@@ -13,7 +12,8 @@ config NET_DSA_MV88E6XXX
 config NET_DSA_MV88E6XXX_PTP
 	bool "PTP support for Marvell 88E6xxx"
 	default n
-	depends on NET_DSA_MV88E6XXX && PTP_1588_CLOCK
+	depends on (NET_DSA_MV88E6XXX = y && PTP_1588_CLOCK = y) || \
+	           (NET_DSA_MV88E6XXX = m && PTP_1588_CLOCK)
 	help
 	  Say Y to enable PTP hardware timestamping on Marvell 88E6xxx switch
 	  chips that support it.
-- 
GitLab


From df49908f3c52d211aea5e2a14a93bbe67a2cb3af Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Fri, 23 Dec 2022 11:37:18 +0400
Subject: [PATCH 676/875] nfc: Fix potential resource leaks

nfc_get_device() take reference for the device, add missing
nfc_put_device() to release it when not need anymore.
Also fix the style warnning by use error EOPNOTSUPP instead of
ENOTSUPP.

Fixes: 5ce3f32b5264 ("NFC: netlink: SE API implementation")
Fixes: 29e76924cf08 ("nfc: netlink: Add capability to reply to vendor_cmd with data")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/nfc/netlink.c | 52 ++++++++++++++++++++++++++++++++++-------------
 1 file changed, 38 insertions(+), 14 deletions(-)

diff --git a/net/nfc/netlink.c b/net/nfc/netlink.c
index 9d91087b93992..1fc339084d897 100644
--- a/net/nfc/netlink.c
+++ b/net/nfc/netlink.c
@@ -1497,6 +1497,7 @@ static int nfc_genl_se_io(struct sk_buff *skb, struct genl_info *info)
 	u32 dev_idx, se_idx;
 	u8 *apdu;
 	size_t apdu_len;
+	int rc;
 
 	if (!info->attrs[NFC_ATTR_DEVICE_INDEX] ||
 	    !info->attrs[NFC_ATTR_SE_INDEX] ||
@@ -1510,25 +1511,37 @@ static int nfc_genl_se_io(struct sk_buff *skb, struct genl_info *info)
 	if (!dev)
 		return -ENODEV;
 
-	if (!dev->ops || !dev->ops->se_io)
-		return -ENOTSUPP;
+	if (!dev->ops || !dev->ops->se_io) {
+		rc = -EOPNOTSUPP;
+		goto put_dev;
+	}
 
 	apdu_len = nla_len(info->attrs[NFC_ATTR_SE_APDU]);
-	if (apdu_len == 0)
-		return -EINVAL;
+	if (apdu_len == 0) {
+		rc = -EINVAL;
+		goto put_dev;
+	}
 
 	apdu = nla_data(info->attrs[NFC_ATTR_SE_APDU]);
-	if (!apdu)
-		return -EINVAL;
+	if (!apdu) {
+		rc = -EINVAL;
+		goto put_dev;
+	}
 
 	ctx = kzalloc(sizeof(struct se_io_ctx), GFP_KERNEL);
-	if (!ctx)
-		return -ENOMEM;
+	if (!ctx) {
+		rc = -ENOMEM;
+		goto put_dev;
+	}
 
 	ctx->dev_idx = dev_idx;
 	ctx->se_idx = se_idx;
 
-	return nfc_se_io(dev, se_idx, apdu, apdu_len, se_io_cb, ctx);
+	rc = nfc_se_io(dev, se_idx, apdu, apdu_len, se_io_cb, ctx);
+
+put_dev:
+	nfc_put_device(dev);
+	return rc;
 }
 
 static int nfc_genl_vendor_cmd(struct sk_buff *skb,
@@ -1551,14 +1564,21 @@ static int nfc_genl_vendor_cmd(struct sk_buff *skb,
 	subcmd = nla_get_u32(info->attrs[NFC_ATTR_VENDOR_SUBCMD]);
 
 	dev = nfc_get_device(dev_idx);
-	if (!dev || !dev->vendor_cmds || !dev->n_vendor_cmds)
+	if (!dev)
 		return -ENODEV;
 
+	if (!dev->vendor_cmds || !dev->n_vendor_cmds) {
+		err = -ENODEV;
+		goto put_dev;
+	}
+
 	if (info->attrs[NFC_ATTR_VENDOR_DATA]) {
 		data = nla_data(info->attrs[NFC_ATTR_VENDOR_DATA]);
 		data_len = nla_len(info->attrs[NFC_ATTR_VENDOR_DATA]);
-		if (data_len == 0)
-			return -EINVAL;
+		if (data_len == 0) {
+			err = -EINVAL;
+			goto put_dev;
+		}
 	} else {
 		data = NULL;
 		data_len = 0;
@@ -1573,10 +1593,14 @@ static int nfc_genl_vendor_cmd(struct sk_buff *skb,
 		dev->cur_cmd_info = info;
 		err = cmd->doit(dev, data, data_len);
 		dev->cur_cmd_info = NULL;
-		return err;
+		goto put_dev;
 	}
 
-	return -EOPNOTSUPP;
+	err = -EOPNOTSUPP;
+
+put_dev:
+	nfc_put_device(dev);
+	return err;
 }
 
 /* message building helper */
-- 
GitLab


From d3805695fe1e7383517903715cefc9bbdcffdc90 Mon Sep 17 00:00:00 2001
From: Anuradha Weeraman <anuradha@debian.org>
Date: Sun, 25 Dec 2022 23:12:22 +0530
Subject: [PATCH 677/875] net: ethernet: marvell: octeontx2: Fix uninitialized
 variable warning

Fix for uninitialized variable warning.

Addresses-Coverity: ("Uninitialized scalar variable")
Signed-off-by: Anuradha Weeraman <anuradha@debian.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/marvell/octeontx2/af/mcs_rvu_if.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mcs_rvu_if.c b/drivers/net/ethernet/marvell/octeontx2/af/mcs_rvu_if.c
index fa8029a940689..eb25e458266ca 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mcs_rvu_if.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mcs_rvu_if.c
@@ -589,7 +589,7 @@ int rvu_mbox_handler_mcs_free_resources(struct rvu *rvu,
 	u16 pcifunc = req->hdr.pcifunc;
 	struct mcs_rsrc_map *map;
 	struct mcs *mcs;
-	int rc;
+	int rc = 0;
 
 	if (req->mcs_id >= rvu->mcs_blk_cnt)
 		return MCS_AF_ERR_INVALID_MCSID;
-- 
GitLab


From a4517c4f3423c7c448f2c359218f97c1173523a1 Mon Sep 17 00:00:00 2001
From: Chris Chiu <chris.chiu@canonical.com>
Date: Mon, 26 Dec 2022 19:43:03 +0800
Subject: [PATCH 678/875] ALSA: hda/realtek: Apply dual codec fixup for Dell
 Latitude laptops

The Dell Latiture 3340/3440/3540 laptops with Realtek ALC3204 have
dual codecs and need the ALC1220_FIXUP_GB_DUAL_CODECS to fix the
conflicts of Master controls. The existing headset mic fixup for
Dell is also required to enable the jack sense and the headset mic.

Introduce a new fixup to fix the dual codec and headset mic issues
for particular Dell laptops since other old Dell laptops with the
same codec configuration are already well handled by the fixup in
alc269_fallback_pin_fixup_tbl[].

Signed-off-by: Chris Chiu <chris.chiu@canonical.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20221226114303.4027500-1-chris.chiu@canonical.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/pci/hda/patch_realtek.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index e443d88f627f0..3794b522c2222 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -7175,6 +7175,7 @@ enum {
 	ALC287_FIXUP_YOGA9_14IAP7_BASS_SPK,
 	ALC287_FIXUP_YOGA9_14IAP7_BASS_SPK_PIN,
 	ALC295_FIXUP_DELL_INSPIRON_TOP_SPEAKERS,
+	ALC236_FIXUP_DELL_DUAL_CODECS,
 };
 
 /* A special fixup for Lenovo C940 and Yoga Duet 7;
@@ -9130,6 +9131,12 @@ static const struct hda_fixup alc269_fixups[] = {
 		.chained = true,
 		.chain_id = ALC269_FIXUP_DELL4_MIC_NO_PRESENCE,
 	},
+	[ALC236_FIXUP_DELL_DUAL_CODECS] = {
+		.type = HDA_FIXUP_PINS,
+		.v.func = alc1220_fixup_gb_dual_codecs,
+		.chained = true,
+		.chain_id = ALC255_FIXUP_DELL1_MIC_NO_PRESENCE,
+	},
 };
 
 static const struct snd_pci_quirk alc269_fixup_tbl[] = {
@@ -9232,6 +9239,12 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
 	SND_PCI_QUIRK(0x1028, 0x0b1a, "Dell Precision 5570", ALC289_FIXUP_DUAL_SPK),
 	SND_PCI_QUIRK(0x1028, 0x0b37, "Dell Inspiron 16 Plus 7620 2-in-1", ALC295_FIXUP_DELL_INSPIRON_TOP_SPEAKERS),
 	SND_PCI_QUIRK(0x1028, 0x0b71, "Dell Inspiron 16 Plus 7620", ALC295_FIXUP_DELL_INSPIRON_TOP_SPEAKERS),
+	SND_PCI_QUIRK(0x1028, 0x0c19, "Dell Precision 3340", ALC236_FIXUP_DELL_DUAL_CODECS),
+	SND_PCI_QUIRK(0x1028, 0x0c1a, "Dell Precision 3340", ALC236_FIXUP_DELL_DUAL_CODECS),
+	SND_PCI_QUIRK(0x1028, 0x0c1b, "Dell Precision 3440", ALC236_FIXUP_DELL_DUAL_CODECS),
+	SND_PCI_QUIRK(0x1028, 0x0c1c, "Dell Precision 3540", ALC236_FIXUP_DELL_DUAL_CODECS),
+	SND_PCI_QUIRK(0x1028, 0x0c1d, "Dell Precision 3440", ALC236_FIXUP_DELL_DUAL_CODECS),
+	SND_PCI_QUIRK(0x1028, 0x0c1e, "Dell Precision 3540", ALC236_FIXUP_DELL_DUAL_CODECS),
 	SND_PCI_QUIRK(0x1028, 0x164a, "Dell", ALC293_FIXUP_DELL1_MIC_NO_PRESENCE),
 	SND_PCI_QUIRK(0x1028, 0x164b, "Dell", ALC293_FIXUP_DELL1_MIC_NO_PRESENCE),
 	SND_PCI_QUIRK(0x103c, 0x1586, "HP", ALC269_FIXUP_HP_MUTE_LED_MIC2),
-- 
GitLab


From 246cf66e300b76099b5dbd3fdd39e9a5dbc53f02 Mon Sep 17 00:00:00 2001
From: Yu Kuai <yukuai3@huawei.com>
Date: Mon, 26 Dec 2022 11:06:05 +0800
Subject: [PATCH 679/875] block, bfq: fix uaf for bfqq in bfq_exit_icq_bfqq

Commit 64dc8c732f5c ("block, bfq: fix possible uaf for 'bfqq->bic'")
will access 'bic->bfqq' in bic_set_bfqq(), however, bfq_exit_icq_bfqq()
can free bfqq first, and then call bic_set_bfqq(), which will cause uaf.

Fix the problem by moving bfq_exit_bfqq() behind bic_set_bfqq().

Fixes: 64dc8c732f5c ("block, bfq: fix possible uaf for 'bfqq->bic'")
Reported-by: Yi Zhang <yi.zhang@redhat.com>
Signed-off-by: Yu Kuai <yukuai3@huawei.com>
Link: https://lore.kernel.org/r/20221226030605.1437081-1-yukuai1@huaweicloud.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 block/bfq-iosched.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/block/bfq-iosched.c b/block/bfq-iosched.c
index 16f43bbc575a0..ccf2204477a57 100644
--- a/block/bfq-iosched.c
+++ b/block/bfq-iosched.c
@@ -5317,8 +5317,8 @@ static void bfq_exit_icq_bfqq(struct bfq_io_cq *bic, bool is_sync)
 		unsigned long flags;
 
 		spin_lock_irqsave(&bfqd->lock, flags);
-		bfq_exit_bfqq(bfqd, bfqq);
 		bic_set_bfqq(bic, NULL, is_sync);
+		bfq_exit_bfqq(bfqd, bfqq);
 		spin_unlock_irqrestore(&bfqd->lock, flags);
 	}
 }
-- 
GitLab


From 33b93727ce90c8db916fb071ed13e90106339754 Mon Sep 17 00:00:00 2001
From: Christoph Hellwig <hch@lst.de>
Date: Sun, 25 Dec 2022 11:32:31 +0100
Subject: [PATCH 680/875] nvme: fix setting the queue depth in
 nvme_alloc_io_tag_set

While the CAP.MQES field in NVMe is a 0s based filed with a natural one
off, we also need to account for the queue wrap condition and fix undo
the one off again in nvme_alloc_io_tag_set.  This was never properly
done by the fabrics drivers, but they don't seem to care because there
is no actual physical queue that can wrap around, but it became a
problem when converting over the PCIe driver.  Also add back the
BLK_MQ_MAX_DEPTH check that was lost in the same commit.

Fixes: 0da7feaa5913 ("nvme-pci: use the tagset alloc/free helpers")
Reported-by: Hugh Dickins <hughd@google.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Tested-by: Hugh Dickins <hughd@google.com>
Link: https://lore.kernel.org/r/20221225103234.226794-2-hch@lst.de
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 drivers/nvme/host/core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c
index e26b085a007ae..cda1361e6d4fb 100644
--- a/drivers/nvme/host/core.c
+++ b/drivers/nvme/host/core.c
@@ -4897,7 +4897,7 @@ int nvme_alloc_io_tag_set(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set,
 
 	memset(set, 0, sizeof(*set));
 	set->ops = ops;
-	set->queue_depth = ctrl->sqsize + 1;
+	set->queue_depth = min_t(unsigned, ctrl->sqsize, BLK_MQ_MAX_DEPTH - 1);
 	/*
 	 * Some Apple controllers requires tags to be unique across admin and
 	 * the (only) I/O queue, so reserve the first 32 tags of the I/O queue.
-- 
GitLab


From 88d356ca41ba1c3effc2d4208dfbd4392f58cd6d Mon Sep 17 00:00:00 2001
From: Christoph Hellwig <hch@lst.de>
Date: Sun, 25 Dec 2022 11:32:32 +0100
Subject: [PATCH 681/875] nvme-pci: update sqsize when adjusting the queue
 depth

Update the core sqsize field in addition to the PCIe-specific
q_depth field as the core tagset allocation helpers rely on it.

Fixes: 0da7feaa5913 ("nvme-pci: use the tagset alloc/free helpers")
Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Hugh Dickins <hughd@google.com>
Link: https://lore.kernel.org/r/20221225103234.226794-3-hch@lst.de
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 drivers/nvme/host/pci.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index 804b6a6cb43a9..b13baccedb4a9 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -2333,10 +2333,12 @@ static int nvme_setup_io_queues(struct nvme_dev *dev)
 	if (dev->cmb_use_sqes) {
 		result = nvme_cmb_qdepth(dev, nr_io_queues,
 				sizeof(struct nvme_command));
-		if (result > 0)
+		if (result > 0) {
 			dev->q_depth = result;
-		else
+			dev->ctrl.sqsize = result - 1;
+		} else {
 			dev->cmb_use_sqes = false;
+		}
 	}
 
 	do {
@@ -2537,7 +2539,6 @@ static int nvme_pci_enable(struct nvme_dev *dev)
 
 	dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
 				io_queue_depth);
-	dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
 	dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
 	dev->dbs = dev->bar + 4096;
 
@@ -2578,7 +2579,7 @@ static int nvme_pci_enable(struct nvme_dev *dev)
 		dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
 			 dev->q_depth);
 	}
-
+	dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
 
 	nvme_map_cmb(dev);
 
-- 
GitLab


From 93ef83050e597634d2c7dc838a28caf5137b9404 Mon Sep 17 00:00:00 2001
From: "YoungJun.park" <her0gyugyu@gmail.com>
Date: Fri, 28 Oct 2022 07:42:41 -0700
Subject: [PATCH 682/875] kunit: alloc_string_stream_fragment error handling
 bug fix

When it fails to allocate fragment, it does not free and return error.
And check the pointer inappropriately.

Fixed merge conflicts with
commit 618887768bb7 ("kunit: update NULL vs IS_ERR() tests")
Shuah Khan <skhan@linuxfoundation.org>

Signed-off-by: YoungJun.park <her0gyugyu@gmail.com>
Reviewed-by: David Gow <davidgow@google.com>
Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
---
 lib/kunit/string-stream.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/lib/kunit/string-stream.c b/lib/kunit/string-stream.c
index f5f51166d8c20..cc32743c1171f 100644
--- a/lib/kunit/string-stream.c
+++ b/lib/kunit/string-stream.c
@@ -23,8 +23,10 @@ static struct string_stream_fragment *alloc_string_stream_fragment(
 		return ERR_PTR(-ENOMEM);
 
 	frag->fragment = kunit_kmalloc(test, len, gfp);
-	if (!frag->fragment)
+	if (!frag->fragment) {
+		kunit_kfree(test, frag);
 		return ERR_PTR(-ENOMEM);
+	}
 
 	return frag;
 }
-- 
GitLab


From 37e14e4f3715428b809e4df9a9958baa64c77d51 Mon Sep 17 00:00:00 2001
From: Adam Vodopjan <grozzly@protonmail.com>
Date: Fri, 9 Dec 2022 09:26:34 +0000
Subject: [PATCH 683/875] ata: ahci: Fix PCS quirk application for suspend

Since kernel 5.3.4 my laptop (ICH8M controller) does not see Kingston
SV300S37A60G SSD disk connected into a SATA connector on wake from
suspend.  The problem was introduced in c312ef176399 ("libata/ahci: Drop
PCS quirk for Denverton and beyond"): the quirk is not applied on wake
from suspend as it originally was.

It is worth to mention the commit contained another bug: the quirk is
not applied at all to controllers which require it. The fix commit
09d6ac8dc51a ("libata/ahci: Fix PCS quirk application") landed in 5.3.8.
So testing my patch anywhere between commits c312ef176399 and
09d6ac8dc51a is pointless.

Not all disks trigger the problem. For example nothing bad happens with
Western Digital WD5000LPCX HDD.

Test hardware:
- Acer 5920G with ICH8M SATA controller
- sda: some SATA HDD connnected into the DVD drive IDE port with a
  SATA-IDE caddy. It is a boot disk
- sdb: Kingston SV300S37A60G SSD connected into the only SATA port

Sample "dmesg --notime | grep -E '^(sd |ata)'" output on wake:

sd 0:0:0:0: [sda] Starting disk
sd 2:0:0:0: [sdb] Starting disk
ata4: SATA link down (SStatus 4 SControl 300)
ata3: SATA link down (SStatus 4 SControl 300)
ata1.00: ACPI cmd ef/03:0c:00:00:00:a0 (SET FEATURES) filtered out
ata1.00: ACPI cmd ef/03:42:00:00:00:a0 (SET FEATURES) filtered out
ata1: FORCE: cable set to 80c
ata5: SATA link down (SStatus 0 SControl 300)
ata3: SATA link down (SStatus 4 SControl 300)
ata3: SATA link down (SStatus 4 SControl 300)
ata3.00: disabled
sd 2:0:0:0: rejecting I/O to offline device
ata3.00: detaching (SCSI 2:0:0:0)
sd 2:0:0:0: [sdb] Start/Stop Unit failed: Result: hostbyte=DID_NO_CONNECT
	driverbyte=DRIVER_OK
sd 2:0:0:0: [sdb] Synchronizing SCSI cache
sd 2:0:0:0: [sdb] Synchronize Cache(10) failed: Result:
	hostbyte=DID_BAD_TARGET driverbyte=DRIVER_OK
sd 2:0:0:0: [sdb] Stopping disk
sd 2:0:0:0: [sdb] Start/Stop Unit failed: Result: hostbyte=DID_BAD_TARGET
	driverbyte=DRIVER_OK

Commit c312ef176399 dropped ahci_pci_reset_controller() which internally
calls ahci_reset_controller() and applies the PCS quirk if needed after
that. It was called each time a reset was required instead of just
ahci_reset_controller(). This patch puts the function back in place.

Fixes: c312ef176399 ("libata/ahci: Drop PCS quirk for Denverton and beyond")
Signed-off-by: Adam Vodopjan <grozzly@protonmail.com>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
---
 drivers/ata/ahci.c | 32 +++++++++++++++++++++++---------
 1 file changed, 23 insertions(+), 9 deletions(-)

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 0cfd0ec6229b3..14a1c0d14916f 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -83,6 +83,7 @@ enum board_ids {
 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
 static void ahci_remove_one(struct pci_dev *dev);
 static void ahci_shutdown_one(struct pci_dev *dev);
+static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv);
 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
 				 unsigned long deadline);
 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
@@ -676,6 +677,25 @@ static void ahci_pci_save_initial_config(struct pci_dev *pdev,
 	ahci_save_initial_config(&pdev->dev, hpriv);
 }
 
+static int ahci_pci_reset_controller(struct ata_host *host)
+{
+	struct pci_dev *pdev = to_pci_dev(host->dev);
+	struct ahci_host_priv *hpriv = host->private_data;
+	int rc;
+
+	rc = ahci_reset_controller(host);
+	if (rc)
+		return rc;
+
+	/*
+	 * If platform firmware failed to enable ports, try to enable
+	 * them here.
+	 */
+	ahci_intel_pcs_quirk(pdev, hpriv);
+
+	return 0;
+}
+
 static void ahci_pci_init_controller(struct ata_host *host)
 {
 	struct ahci_host_priv *hpriv = host->private_data;
@@ -870,7 +890,7 @@ static int ahci_pci_device_runtime_resume(struct device *dev)
 	struct ata_host *host = pci_get_drvdata(pdev);
 	int rc;
 
-	rc = ahci_reset_controller(host);
+	rc = ahci_pci_reset_controller(host);
 	if (rc)
 		return rc;
 	ahci_pci_init_controller(host);
@@ -906,7 +926,7 @@ static int ahci_pci_device_resume(struct device *dev)
 		ahci_mcp89_apple_enable(pdev);
 
 	if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
-		rc = ahci_reset_controller(host);
+		rc = ahci_pci_reset_controller(host);
 		if (rc)
 			return rc;
 
@@ -1784,12 +1804,6 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 	/* save initial config */
 	ahci_pci_save_initial_config(pdev, hpriv);
 
-	/*
-	 * If platform firmware failed to enable ports, try to enable
-	 * them here.
-	 */
-	ahci_intel_pcs_quirk(pdev, hpriv);
-
 	/* prepare host */
 	if (hpriv->cap & HOST_CAP_NCQ) {
 		pi.flags |= ATA_FLAG_NCQ;
@@ -1899,7 +1913,7 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 	if (rc)
 		return rc;
 
-	rc = ahci_reset_controller(host);
+	rc = ahci_pci_reset_controller(host);
 	if (rc)
 		return rc;
 
-- 
GitLab


From e779fd53b4aa0aa8704ae62eb56065b9877a540b Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@google.com>
Date: Tue, 13 Dec 2022 00:16:40 +0000
Subject: [PATCH 684/875] KVM: selftests: Define literal to asm constraint in
 aarch64 as unsigned long
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Define a literal '0' asm input constraint to aarch64/page_fault_test's
guest_cas() as an unsigned long to make clang happy.

  tools/testing/selftests/kvm/aarch64/page_fault_test.c:120:16: error:
    value size does not match register size specified by the constraint
    and modifier [-Werror,-Wasm-operand-widths]
                       :: "r" (0), "r" (TEST_DATA), "r" (guest_test_memory));
                               ^
  tools/testing/selftests/kvm/aarch64/page_fault_test.c:119:15: note:
    use constraint modifier "w"
                       "casal %0, %1, [%2]\n"
                              ^~
                              %w0

Fixes: 35c581015712 ("KVM: selftests: aarch64: Add aarch64/page_fault_test")
Cc: Ricardo Koller <ricarkol@google.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221213001653.3852042-2-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/aarch64/page_fault_test.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/testing/selftests/kvm/aarch64/page_fault_test.c b/tools/testing/selftests/kvm/aarch64/page_fault_test.c
index 95d22cfb7b41a..beb944fa6fd46 100644
--- a/tools/testing/selftests/kvm/aarch64/page_fault_test.c
+++ b/tools/testing/selftests/kvm/aarch64/page_fault_test.c
@@ -117,7 +117,7 @@ static void guest_cas(void)
 	GUEST_ASSERT(guest_check_lse());
 	asm volatile(".arch_extension lse\n"
 		     "casal %0, %1, [%2]\n"
-		     :: "r" (0), "r" (TEST_DATA), "r" (guest_test_memory));
+		     :: "r" (0ul), "r" (TEST_DATA), "r" (guest_test_memory));
 	val = READ_ONCE(*guest_test_memory);
 	GUEST_ASSERT_EQ(val, TEST_DATA);
 }
-- 
GitLab


From 73441efa36c253906057b8800bc9a3fdadbc2c41 Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@google.com>
Date: Tue, 13 Dec 2022 00:16:41 +0000
Subject: [PATCH 685/875] KVM: selftests: Delete dead code in
 x86_64/vmx_tsc_adjust_test.c

Delete an unused struct definition in x86_64/vmx_tsc_adjust_test.c.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20221213001653.3852042-3-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/x86_64/vmx_tsc_adjust_test.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/tools/testing/selftests/kvm/x86_64/vmx_tsc_adjust_test.c b/tools/testing/selftests/kvm/x86_64/vmx_tsc_adjust_test.c
index 5943187e85949..ff8ecdf32ae07 100644
--- a/tools/testing/selftests/kvm/x86_64/vmx_tsc_adjust_test.c
+++ b/tools/testing/selftests/kvm/x86_64/vmx_tsc_adjust_test.c
@@ -49,11 +49,6 @@ enum {
 	NUM_VMX_PAGES,
 };
 
-struct kvm_single_msr {
-	struct kvm_msrs header;
-	struct kvm_msr_entry entry;
-} __attribute__((packed));
-
 /* The virtual machine object. */
 static struct kvm_vm *vm;
 
-- 
GitLab


From d61a12cb9af5b355a38e0c0106e91224b49195ce Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@google.com>
Date: Tue, 13 Dec 2022 00:16:42 +0000
Subject: [PATCH 686/875] KVM: selftests: Fix divide-by-zero bug in
 memslot_perf_test
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Check that the number of pages per slot is non-zero in get_max_slots()
prior to computing the remaining number of pages.  clang generates code
that uses an actual DIV for calculating the remaining, which causes a #DE
if the total number of pages is less than the number of slots.

  traps: memslot_perf_te[97611] trap divide error ip:4030c4 sp:7ffd18ae58f0
         error:0 in memslot_perf_test[401000+cb000]

Fixes: a69170c65acd ("KVM: selftests: memslot_perf_test: Report optimal memory slots")
Signed-off-by: Sean Christopherson <seanjc@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221213001653.3852042-4-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/memslot_perf_test.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tools/testing/selftests/kvm/memslot_perf_test.c b/tools/testing/selftests/kvm/memslot_perf_test.c
index e698306bf49d1..e6587e1934905 100644
--- a/tools/testing/selftests/kvm/memslot_perf_test.c
+++ b/tools/testing/selftests/kvm/memslot_perf_test.c
@@ -265,6 +265,9 @@ static uint64_t get_max_slots(struct vm_data *data, uint32_t host_page_size)
 	slots = data->nslots;
 	while (--slots > 1) {
 		pages_per_slot = mempages / slots;
+		if (!pages_per_slot)
+			continue;
+
 		rempages = mempages % pages_per_slot;
 		if (check_slot_pages(host_page_size, guest_page_size,
 				     pages_per_slot, rempages))
-- 
GitLab


From 43e96957e8b87bad8e4ba666750ff0cda9e03ffb Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@google.com>
Date: Tue, 13 Dec 2022 00:16:43 +0000
Subject: [PATCH 687/875] KVM: selftests: Use pattern matching in .gitignore

Use pattern matching to exclude everything except .c, .h, .S, and .sh
files from Git.  Manually adding every test target has an absurd
maintenance cost, is comically error prone, and leads to bikeshedding
over whether or not the targets should be listed in alphabetical order.

Deliberately do not include the one-off assets, e.g. config, settings,
.gitignore itself, etc as Git doesn't ignore files that are already in
the repository.  Adding the one-off assets won't prevent mistakes where
developers forget to --force add files that don't match the "allowed".

Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20221213001653.3852042-5-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/.gitignore | 91 ++------------------------
 1 file changed, 6 insertions(+), 85 deletions(-)

diff --git a/tools/testing/selftests/kvm/.gitignore b/tools/testing/selftests/kvm/.gitignore
index 6ce8c488d62ea..6d9381d60172f 100644
--- a/tools/testing/selftests/kvm/.gitignore
+++ b/tools/testing/selftests/kvm/.gitignore
@@ -1,86 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
-/aarch64/aarch32_id_regs
-/aarch64/arch_timer
-/aarch64/debug-exceptions
-/aarch64/get-reg-list
-/aarch64/hypercalls
-/aarch64/page_fault_test
-/aarch64/psci_test
-/aarch64/vcpu_width_config
-/aarch64/vgic_init
-/aarch64/vgic_irq
-/s390x/memop
-/s390x/resets
-/s390x/sync_regs_test
-/s390x/tprot
-/x86_64/amx_test
-/x86_64/cpuid_test
-/x86_64/cr4_cpuid_sync_test
-/x86_64/debug_regs
-/x86_64/exit_on_emulation_failure_test
-/x86_64/fix_hypercall_test
-/x86_64/get_msr_index_features
-/x86_64/kvm_clock_test
-/x86_64/kvm_pv_test
-/x86_64/hyperv_clock
-/x86_64/hyperv_cpuid
-/x86_64/hyperv_evmcs
-/x86_64/hyperv_features
-/x86_64/hyperv_ipi
-/x86_64/hyperv_svm_test
-/x86_64/hyperv_tlb_flush
-/x86_64/max_vcpuid_cap_test
-/x86_64/mmio_warning_test
-/x86_64/monitor_mwait_test
-/x86_64/nested_exceptions_test
-/x86_64/nx_huge_pages_test
-/x86_64/platform_info_test
-/x86_64/pmu_event_filter_test
-/x86_64/set_boot_cpu_id
-/x86_64/set_sregs_test
-/x86_64/sev_migrate_tests
-/x86_64/smaller_maxphyaddr_emulation_test
-/x86_64/smm_test
-/x86_64/state_test
-/x86_64/svm_vmcall_test
-/x86_64/svm_int_ctl_test
-/x86_64/svm_nested_soft_inject_test
-/x86_64/svm_nested_shutdown_test
-/x86_64/sync_regs_test
-/x86_64/tsc_msrs_test
-/x86_64/tsc_scaling_sync
-/x86_64/ucna_injection_test
-/x86_64/userspace_io_test
-/x86_64/userspace_msr_exit_test
-/x86_64/vmx_apic_access_test
-/x86_64/vmx_close_while_nested_test
-/x86_64/vmx_dirty_log_test
-/x86_64/vmx_exception_with_invalid_guest_state
-/x86_64/vmx_invalid_nested_guest_state
-/x86_64/vmx_msrs_test
-/x86_64/vmx_preemption_timer_test
-/x86_64/vmx_set_nested_state_test
-/x86_64/vmx_tsc_adjust_test
-/x86_64/vmx_nested_tsc_scaling_test
-/x86_64/xapic_ipi_test
-/x86_64/xapic_state_test
-/x86_64/xen_shinfo_test
-/x86_64/xen_vmcall_test
-/x86_64/xss_msr_test
-/x86_64/vmx_pmu_caps_test
-/x86_64/triple_fault_event_test
-/access_tracking_perf_test
-/demand_paging_test
-/dirty_log_test
-/dirty_log_perf_test
-/hardware_disable_test
-/kvm_create_max_vcpus
-/kvm_page_table_test
-/max_guest_memory_test
-/memslot_modification_stress_test
-/memslot_perf_test
-/rseq_test
-/set_memory_region_test
-/steal_time
-/kvm_binary_stats_test
-/system_counter_offset_test
+*
+!/**/
+!*.c
+!*.h
+!*.S
+!*.sh
-- 
GitLab


From 1525429fe5cb8e23b74c6dd473bb477a35906704 Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@google.com>
Date: Tue, 13 Dec 2022 00:16:44 +0000
Subject: [PATCH 688/875] KVM: selftests: Fix a typo in x86-64's
 kvm_get_cpu_address_width()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Fix a == vs. = typo in kvm_get_cpu_address_width() that results in
@pa_bits being left unset if the CPU doesn't support enumerating its
MAX_PHY_ADDR.  Flagged by clang's unusued-value warning.

lib/x86_64/processor.c:1034:51: warning: expression result unused [-Wunused-value]
                *pa_bits == kvm_cpu_has(X86_FEATURE_PAE) ? 36 : 32;

Fixes: 3bd396353d18 ("KVM: selftests: Add X86_FEATURE_PAE and use it calc "fallback" MAXPHYADDR")
Signed-off-by: Sean Christopherson <seanjc@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221213001653.3852042-6-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/lib/x86_64/processor.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/testing/selftests/kvm/lib/x86_64/processor.c b/tools/testing/selftests/kvm/lib/x86_64/processor.c
index c4d368d56cfe2..acfa1d01e7df0 100644
--- a/tools/testing/selftests/kvm/lib/x86_64/processor.c
+++ b/tools/testing/selftests/kvm/lib/x86_64/processor.c
@@ -1031,7 +1031,7 @@ bool is_amd_cpu(void)
 void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits)
 {
 	if (!kvm_cpu_has_p(X86_PROPERTY_MAX_PHY_ADDR)) {
-		*pa_bits == kvm_cpu_has(X86_FEATURE_PAE) ? 36 : 32;
+		*pa_bits = kvm_cpu_has(X86_FEATURE_PAE) ? 36 : 32;
 		*va_bits = 32;
 	} else {
 		*pa_bits = kvm_cpu_property(X86_PROPERTY_MAX_PHY_ADDR);
-- 
GitLab


From 6a5db83adfd668b3c1092274ddf45903eb1fe435 Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@google.com>
Date: Tue, 13 Dec 2022 00:16:45 +0000
Subject: [PATCH 689/875] KVM: selftests: Rename UNAME_M to ARCH_DIR, fill
 explicitly for x86

Rename UNAME_M to ARCH_DIR and explicitly set it directly for x86.  At
this point, the name of the arch directory really doesn't have anything
to do with `uname -m`, and UNAME_M is unnecessarily confusing given that
its purpose is purely to identify the arch specific directory.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20221213001653.3852042-7-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/Makefile | 47 ++++++++--------------------
 1 file changed, 13 insertions(+), 34 deletions(-)

diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
index 947676983da1f..59f3eb53c932c 100644
--- a/tools/testing/selftests/kvm/Makefile
+++ b/tools/testing/selftests/kvm/Makefile
@@ -7,35 +7,14 @@ top_srcdir = ../../../..
 include $(top_srcdir)/scripts/subarch.include
 ARCH            ?= $(SUBARCH)
 
-# For cross-builds to work, UNAME_M has to map to ARCH and arch specific
-# directories and targets in this Makefile. "uname -m" doesn't map to
-# arch specific sub-directory names.
-#
-# UNAME_M variable to used to run the compiles pointing to the right arch
-# directories and build the right targets for these supported architectures.
-#
-# TEST_GEN_PROGS and LIBKVM are set using UNAME_M variable.
-# LINUX_TOOL_ARCH_INCLUDE is set using ARCH variable.
-#
-# x86_64 targets are named to include x86_64 as a suffix and directories
-# for includes are in x86_64 sub-directory. s390x and aarch64 follow the
-# same convention. "uname -m" doesn't result in the correct mapping for
-# s390x and aarch64.
-#
-# No change necessary for x86_64
-UNAME_M := $(shell uname -m)
-
-# Set UNAME_M for arm64 compile/install to work
-ifeq ($(ARCH),arm64)
-	UNAME_M := aarch64
-endif
-# Set UNAME_M s390x compile/install to work
-ifeq ($(ARCH),s390)
-	UNAME_M := s390x
-endif
-# Set UNAME_M riscv compile/install to work
-ifeq ($(ARCH),riscv)
-	UNAME_M := riscv
+ifeq ($(ARCH),x86)
+	ARCH_DIR := x86_64
+else ifeq ($(ARCH),arm64)
+	ARCH_DIR := aarch64
+else ifeq ($(ARCH),s390)
+	ARCH_DIR := s390x
+else
+	ARCH_DIR := $(ARCH)
 endif
 
 LIBKVM += lib/assert.c
@@ -196,10 +175,10 @@ TEST_GEN_PROGS_riscv += kvm_page_table_test
 TEST_GEN_PROGS_riscv += set_memory_region_test
 TEST_GEN_PROGS_riscv += kvm_binary_stats_test
 
-TEST_PROGS += $(TEST_PROGS_$(UNAME_M))
-TEST_GEN_PROGS += $(TEST_GEN_PROGS_$(UNAME_M))
-TEST_GEN_PROGS_EXTENDED += $(TEST_GEN_PROGS_EXTENDED_$(UNAME_M))
-LIBKVM += $(LIBKVM_$(UNAME_M))
+TEST_PROGS += $(TEST_PROGS_$(ARCH_DIR))
+TEST_GEN_PROGS += $(TEST_GEN_PROGS_$(ARCH_DIR))
+TEST_GEN_PROGS_EXTENDED += $(TEST_GEN_PROGS_EXTENDED_$(ARCH_DIR))
+LIBKVM += $(LIBKVM_$(ARCH_DIR))
 
 INSTALL_HDR_PATH = $(top_srcdir)/usr
 LINUX_HDR_PATH = $(INSTALL_HDR_PATH)/include/
@@ -212,7 +191,7 @@ endif
 CFLAGS += -Wall -Wstrict-prototypes -Wuninitialized -O2 -g -std=gnu99 \
 	-fno-stack-protector -fno-PIE -I$(LINUX_TOOL_INCLUDE) \
 	-I$(LINUX_TOOL_ARCH_INCLUDE) -I$(LINUX_HDR_PATH) -Iinclude \
-	-I$(<D) -Iinclude/$(UNAME_M) -I ../rseq -I.. $(EXTRA_CFLAGS) \
+	-I$(<D) -Iinclude/$(ARCH_DIR) -I ../rseq -I.. $(EXTRA_CFLAGS) \
 	$(KHDR_INCLUDES)
 
 no-pie-option := $(call try-run, echo 'int main() { return 0; }' | \
-- 
GitLab


From 5dc38777a7de15109a1d45b42cf2bb7f1bbe6010 Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@google.com>
Date: Tue, 13 Dec 2022 00:16:46 +0000
Subject: [PATCH 690/875] KVM: selftests: Use proper function prototypes in
 probing code
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Make the main() functions in the probing code proper prototypes so that
compiling the probing code with more strict flags won't generate false
negatives.

  <stdin>:1:5: error: function declaration isn’t a prototype [-Werror=strict-prototypes]

Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20221213001653.3852042-8-seanjc@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/Makefile | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
index 59f3eb53c932c..8eecda2be0d0f 100644
--- a/tools/testing/selftests/kvm/Makefile
+++ b/tools/testing/selftests/kvm/Makefile
@@ -194,11 +194,11 @@ CFLAGS += -Wall -Wstrict-prototypes -Wuninitialized -O2 -g -std=gnu99 \
 	-I$(<D) -Iinclude/$(ARCH_DIR) -I ../rseq -I.. $(EXTRA_CFLAGS) \
 	$(KHDR_INCLUDES)
 
-no-pie-option := $(call try-run, echo 'int main() { return 0; }' | \
+no-pie-option := $(call try-run, echo 'int main(void) { return 0; }' | \
         $(CC) -Werror -no-pie -x c - -o "$$TMP", -no-pie)
 
 # On s390, build the testcases KVM-enabled
-pgste-option = $(call try-run, echo 'int main() { return 0; }' | \
+pgste-option = $(call try-run, echo 'int main(void) { return 0; }' | \
 	$(CC) -Werror -Wl$(comma)--s390-pgste -x c - -o "$$TMP",-Wl$(comma)--s390-pgste)
 
 LDLIBS += -ldl
-- 
GitLab


From 2b2d8afc1acf6396bea14ef973d0029c4a5b33f4 Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@google.com>
Date: Tue, 13 Dec 2022 00:16:47 +0000
Subject: [PATCH 691/875] KVM: selftests: Probe -no-pie with actual CFLAGS used
 to compile

Probe -no-pie with the actual set of CFLAGS used to compile the tests,
clang whines about -no-pie being unused if the tests are compiled with
-static.

  clang: warning: argument unused during compilation: '-no-pie'
  [-Wunused-command-line-argument]

Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20221213001653.3852042-9-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
index 8eecda2be0d0f..2ffd872472793 100644
--- a/tools/testing/selftests/kvm/Makefile
+++ b/tools/testing/selftests/kvm/Makefile
@@ -195,7 +195,7 @@ CFLAGS += -Wall -Wstrict-prototypes -Wuninitialized -O2 -g -std=gnu99 \
 	$(KHDR_INCLUDES)
 
 no-pie-option := $(call try-run, echo 'int main(void) { return 0; }' | \
-        $(CC) -Werror -no-pie -x c - -o "$$TMP", -no-pie)
+        $(CC) -Werror $(CFLAGS) -no-pie -x c - -o "$$TMP", -no-pie)
 
 # On s390, build the testcases KVM-enabled
 pgste-option = $(call try-run, echo 'int main(void) { return 0; }' | \
-- 
GitLab


From 7cf2e7373ab145bf972c3cbcb495fd1a9770c3b0 Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@google.com>
Date: Tue, 13 Dec 2022 00:16:48 +0000
Subject: [PATCH 692/875] KVM: selftests: Explicitly disable builtins for
 mem*() overrides

Explicitly disable the compiler's builtin memcmp(), memcpy(), and
memset().  Because only lib/string_override.c is built with -ffreestanding,
the compiler reserves the right to do what it wants and can try to link the
non-freestanding code to its own crud.

  /usr/bin/x86_64-linux-gnu-ld: /lib/x86_64-linux-gnu/libc.a(memcmp.o): in function `memcmp_ifunc':
  (.text+0x0): multiple definition of `memcmp'; tools/testing/selftests/kvm/lib/string_override.o:
  tools/testing/selftests/kvm/lib/string_override.c:15: first defined here
  clang: error: linker command failed with exit code 1 (use -v to see invocation)

Fixes: 6b6f71484bf4 ("KVM: selftests: Implement memcmp(), memcpy(), and memset() for guest use")
Reported-by: Aaron Lewis <aaronlewis@google.com>
Reported-by: Raghavendra Rao Ananta <rananta@google.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20221213001653.3852042-10-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
index 2ffd872472793..ecd3c8126c3d7 100644
--- a/tools/testing/selftests/kvm/Makefile
+++ b/tools/testing/selftests/kvm/Makefile
@@ -189,6 +189,7 @@ else
 LINUX_TOOL_ARCH_INCLUDE = $(top_srcdir)/tools/arch/$(ARCH)/include
 endif
 CFLAGS += -Wall -Wstrict-prototypes -Wuninitialized -O2 -g -std=gnu99 \
+	-fno-builtin-memcmp -fno-builtin-memcpy -fno-builtin-memset \
 	-fno-stack-protector -fno-PIE -I$(LINUX_TOOL_INCLUDE) \
 	-I$(LINUX_TOOL_ARCH_INCLUDE) -I$(LINUX_HDR_PATH) -Iinclude \
 	-I$(<D) -Iinclude/$(ARCH_DIR) -I ../rseq -I.. $(EXTRA_CFLAGS) \
-- 
GitLab


From 5efb946b9569abdfb8a42702d40a5c244096e932 Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@google.com>
Date: Tue, 13 Dec 2022 00:16:49 +0000
Subject: [PATCH 693/875] KVM: selftests: Include lib.mk before consuming $(CC)

Include lib.mk before consuming $(CC) and document that lib.mk overwrites
$(CC) unless make was invoked with -e or $(CC) was specified after make
(which makes the environment override the Makefile).  Including lib.mk
after using it for probing, e.g. for -no-pie, can lead to weirdness.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20221213001653.3852042-11-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/Makefile | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
index ecd3c8126c3d7..2acba3c74ad6d 100644
--- a/tools/testing/selftests/kvm/Makefile
+++ b/tools/testing/selftests/kvm/Makefile
@@ -180,6 +180,11 @@ TEST_GEN_PROGS += $(TEST_GEN_PROGS_$(ARCH_DIR))
 TEST_GEN_PROGS_EXTENDED += $(TEST_GEN_PROGS_EXTENDED_$(ARCH_DIR))
 LIBKVM += $(LIBKVM_$(ARCH_DIR))
 
+# lib.mak defines $(OUTPUT), prepends $(OUTPUT)/ to $(TEST_GEN_PROGS), and most
+# importantly defines, i.e. overwrites, $(CC) (unless `make -e` or `make CC=`,
+# which causes the environment variable to override the makefile).
+include ../lib.mk
+
 INSTALL_HDR_PATH = $(top_srcdir)/usr
 LINUX_HDR_PATH = $(INSTALL_HDR_PATH)/include/
 LINUX_TOOL_INCLUDE = $(top_srcdir)/tools/include
@@ -205,10 +210,6 @@ pgste-option = $(call try-run, echo 'int main(void) { return 0; }' | \
 LDLIBS += -ldl
 LDFLAGS += -pthread $(no-pie-option) $(pgste-option)
 
-# After inclusion, $(OUTPUT) is defined and
-# $(TEST_GEN_PROGS) starts with $(OUTPUT)/
-include ../lib.mk
-
 LIBKVM_C := $(filter %.c,$(LIBKVM))
 LIBKVM_S := $(filter %.S,$(LIBKVM))
 LIBKVM_C_OBJ := $(patsubst %.c, $(OUTPUT)/%.o, $(LIBKVM_C))
-- 
GitLab


From db7b780dab6742a8358ae7ecb1d0e972ccea8737 Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@google.com>
Date: Tue, 13 Dec 2022 00:16:50 +0000
Subject: [PATCH 694/875] KVM: selftests: Disable
 "gnu-variable-sized-type-not-at-end" warning

Disable gnu-variable-sized-type-not-at-end so that tests and libraries
can create overlays of variable sized arrays at the end of structs when
using a fixed number of entries, e.g. to get/set a single MSR.

It's possible to fudge around the warning, e.g. by defining a custom
struct that hardcodes the number of entries, but that is a burden for
both developers and readers of the code.

lib/x86_64/processor.c:664:19: warning: field 'header' with variable sized type 'struct kvm_msrs'
not at the end of a struct or class is a GNU extension [-Wgnu-variable-sized-type-not-at-end]
                struct kvm_msrs header;
                                ^
lib/x86_64/processor.c:772:19: warning: field 'header' with variable sized type 'struct kvm_msrs'
not at the end of a struct or class is a GNU extension [-Wgnu-variable-sized-type-not-at-end]
                struct kvm_msrs header;
                                ^
lib/x86_64/processor.c:787:19: warning: field 'header' with variable sized type 'struct kvm_msrs'
not at the end of a struct or class is a GNU extension [-Wgnu-variable-sized-type-not-at-end]
                struct kvm_msrs header;
                                ^
3 warnings generated.

x86_64/hyperv_tlb_flush.c:54:18: warning: field 'hv_vp_set' with variable sized type 'struct hv_vpset'
not at the end of a struct or class is a GNU extension [-Wgnu-variable-sized-type-not-at-end]
        struct hv_vpset hv_vp_set;
                        ^
1 warning generated.

x86_64/xen_shinfo_test.c:137:25: warning: field 'info' with variable sized type 'struct kvm_irq_routing'
not at the end of a struct or class is a GNU extension [-Wgnu-variable-sized-type-not-at-end]
        struct kvm_irq_routing info;
                               ^
1 warning generated.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20221213001653.3852042-12-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
index 2acba3c74ad6d..1750f91dd9362 100644
--- a/tools/testing/selftests/kvm/Makefile
+++ b/tools/testing/selftests/kvm/Makefile
@@ -194,6 +194,7 @@ else
 LINUX_TOOL_ARCH_INCLUDE = $(top_srcdir)/tools/arch/$(ARCH)/include
 endif
 CFLAGS += -Wall -Wstrict-prototypes -Wuninitialized -O2 -g -std=gnu99 \
+	-Wno-gnu-variable-sized-type-not-at-end \
 	-fno-builtin-memcmp -fno-builtin-memcpy -fno-builtin-memset \
 	-fno-stack-protector -fno-PIE -I$(LINUX_TOOL_INCLUDE) \
 	-I$(LINUX_TOOL_ARCH_INCLUDE) -I$(LINUX_HDR_PATH) -Iinclude \
-- 
GitLab


From 2f5213b8fc311eaa8fc78de7ecbd27ead027993c Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@google.com>
Date: Fri, 9 Dec 2022 12:55:44 -0800
Subject: [PATCH 695/875] KVM: selftests: Use magic value to signal
 ucall_alloc() failure

Use a magic value to signal a ucall_alloc() failure instead of simply
doing GUEST_ASSERT().  GUEST_ASSERT() relies on ucall_alloc() and so a
failure puts the guest into an infinite loop.

Use -1 as the magic value, as a real ucall struct should never wrap.

Reported-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/lib/ucall_common.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/tools/testing/selftests/kvm/lib/ucall_common.c b/tools/testing/selftests/kvm/lib/ucall_common.c
index 0cc0971ce60e3..2f0e2ea941cc6 100644
--- a/tools/testing/selftests/kvm/lib/ucall_common.c
+++ b/tools/testing/selftests/kvm/lib/ucall_common.c
@@ -4,6 +4,8 @@
 #include "linux/bitmap.h"
 #include "linux/atomic.h"
 
+#define GUEST_UCALL_FAILED -1
+
 struct ucall_header {
 	DECLARE_BITMAP(in_use, KVM_MAX_VCPUS);
 	struct ucall ucalls[KVM_MAX_VCPUS];
@@ -41,7 +43,8 @@ static struct ucall *ucall_alloc(void)
 	struct ucall *uc;
 	int i;
 
-	GUEST_ASSERT(ucall_pool);
+	if (!ucall_pool)
+		goto ucall_failed;
 
 	for (i = 0; i < KVM_MAX_VCPUS; ++i) {
 		if (!test_and_set_bit(i, ucall_pool->in_use)) {
@@ -51,7 +54,13 @@ static struct ucall *ucall_alloc(void)
 		}
 	}
 
-	GUEST_ASSERT(0);
+ucall_failed:
+	/*
+	 * If the vCPU cannot grab a ucall structure, make a bare ucall with a
+	 * magic value to signal to get_ucall() that things went sideways.
+	 * GUEST_ASSERT() depends on ucall_alloc() and so cannot be used here.
+	 */
+	ucall_arch_do_ucall(GUEST_UCALL_FAILED);
 	return NULL;
 }
 
@@ -93,6 +102,9 @@ uint64_t get_ucall(struct kvm_vcpu *vcpu, struct ucall *uc)
 
 	addr = ucall_arch_get_ucall(vcpu);
 	if (addr) {
+		TEST_ASSERT(addr != (void *)GUEST_UCALL_FAILED,
+			    "Guest failed to allocate ucall struct");
+
 		memcpy(uc, addr, sizeof(*uc));
 		vcpu_run_complete_io(vcpu);
 	} else {
-- 
GitLab


From feb84f6daa7e7d51444d13fa65df7d5562fd0075 Mon Sep 17 00:00:00 2001
From: Paolo Bonzini <pbonzini@redhat.com>
Date: Mon, 12 Dec 2022 05:36:53 -0500
Subject: [PATCH 696/875] KVM: selftests: document the default implementation
 of vm_vaddr_populate_bitmap

Explain the meaning of the bit manipulations of vm_vaddr_populate_bitmap.
These correspond to the "canonical addresses" of x86 and other
architectures, but that is not obvious.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/lib/kvm_util.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/tools/testing/selftests/kvm/lib/kvm_util.c b/tools/testing/selftests/kvm/lib/kvm_util.c
index c88c3ace16d2f..bd892a8149518 100644
--- a/tools/testing/selftests/kvm/lib/kvm_util.c
+++ b/tools/testing/selftests/kvm/lib/kvm_util.c
@@ -186,6 +186,15 @@ const struct vm_guest_mode_params vm_guest_mode_params[] = {
 _Static_assert(sizeof(vm_guest_mode_params)/sizeof(struct vm_guest_mode_params) == NUM_VM_MODES,
 	       "Missing new mode params?");
 
+/*
+ * Initializes vm->vpages_valid to match the canonical VA space of the
+ * architecture.
+ *
+ * The default implementation is valid for architectures which split the
+ * range addressed by a single page table into a low and high region
+ * based on the MSB of the VA. On architectures with this behavior
+ * the VA region spans [0, 2^(va_bits - 1)), [-(2^(va_bits - 1), -1].
+ */
 __weak void vm_vaddr_populate_bitmap(struct kvm_vm *vm)
 {
 	sparsebit_set_num(vm->vpages_valid,
-- 
GitLab


From 7a16142505cbb9b80d5e998e32b1d882e0f45d64 Mon Sep 17 00:00:00 2001
From: Oliver Upton <oliver.upton@linux.dev>
Date: Fri, 9 Dec 2022 01:53:04 +0000
Subject: [PATCH 697/875] KVM: arm64: selftests: Don't identity map the ucall
 MMIO hole

Currently the ucall MMIO hole is placed immediately after slot0, which
is a relatively safe address in the PA space. However, it is possible
that the same address has already been used for something else (like the
guest program image) in the VA space. At least in my own testing,
building the vgic_irq test with clang leads to the MMIO hole appearing
underneath gicv3_ops.

Stop identity mapping the MMIO hole and instead find an unused VA to map
to it. Yet another subtle detail of the KVM selftests library is that
virt_pg_map() does not update vm->vpages_mapped. Switch over to
virt_map() instead to guarantee that the chosen VA isn't to something
else.

Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Message-Id: <20221209015307.1781352-6-oliver.upton@linux.dev>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/lib/aarch64/ucall.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/tools/testing/selftests/kvm/lib/aarch64/ucall.c b/tools/testing/selftests/kvm/lib/aarch64/ucall.c
index 562c16dfbb002..f212bd8ab93d8 100644
--- a/tools/testing/selftests/kvm/lib/aarch64/ucall.c
+++ b/tools/testing/selftests/kvm/lib/aarch64/ucall.c
@@ -14,11 +14,13 @@ static vm_vaddr_t *ucall_exit_mmio_addr;
 
 void ucall_arch_init(struct kvm_vm *vm, vm_paddr_t mmio_gpa)
 {
-	virt_pg_map(vm, mmio_gpa, mmio_gpa);
+	vm_vaddr_t mmio_gva = vm_vaddr_unused_gap(vm, vm->page_size, KVM_UTIL_MIN_VADDR);
+
+	virt_map(vm, mmio_gva, mmio_gpa, 1);
 
 	vm->ucall_mmio_addr = mmio_gpa;
 
-	write_guest_global(vm, ucall_exit_mmio_addr, (vm_vaddr_t *)mmio_gpa);
+	write_guest_global(vm, ucall_exit_mmio_addr, (vm_vaddr_t *)mmio_gva);
 }
 
 void ucall_arch_do_ucall(vm_vaddr_t uc)
-- 
GitLab


From 92c8191bb5d3f670ed806f91823381193288a4e1 Mon Sep 17 00:00:00 2001
From: Oliver Upton <oliver.upton@linux.dev>
Date: Fri, 9 Dec 2022 01:53:02 +0000
Subject: [PATCH 698/875] KVM: selftests: Mark correct page as mapped in
 virt_map()

The loop marks vaddr as mapped after incrementing it by page size,
thereby marking the *next* page as mapped. Set the bit in vpages_mapped
first instead.

Fixes: 56fc7732031d ("KVM: selftests: Fill in vm->vpages_mapped bitmap in virt_map() too")
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Message-Id: <20221209015307.1781352-4-oliver.upton@linux.dev>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 tools/testing/selftests/kvm/lib/kvm_util.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/testing/selftests/kvm/lib/kvm_util.c b/tools/testing/selftests/kvm/lib/kvm_util.c
index bd892a8149518..56d5ea949cbbe 100644
--- a/tools/testing/selftests/kvm/lib/kvm_util.c
+++ b/tools/testing/selftests/kvm/lib/kvm_util.c
@@ -1425,10 +1425,10 @@ void virt_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr,
 
 	while (npages--) {
 		virt_pg_map(vm, vaddr, paddr);
+		sparsebit_set(vm->vpages_mapped, vaddr >> vm->page_shift);
+
 		vaddr += page_size;
 		paddr += page_size;
-
-		sparsebit_set(vm->vpages_mapped, vaddr >> vm->page_shift);
 	}
 }
 
-- 
GitLab


From e0a78525f540f9d9a44a296f307b8b74cee4c288 Mon Sep 17 00:00:00 2001
From: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Date: Mon, 5 Dec 2022 09:20:44 +0100
Subject: [PATCH 699/875] MAINTAINERS: adjust entry after renaming the vmx
 hyperv files

Commit a789aeba4196 ("KVM: VMX: Rename "vmx/evmcs.{ch}" to
"vmx/hyperv.{ch}"") renames the VMX specific Hyper-V files, but does not
adjust the entry in MAINTAINERS.

Hence, ./scripts/get_maintainer.pl --self-test=patterns complains about a
broken reference.

Repair this file reference in KVM X86 HYPER-V (KVM/hyper-v).

Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Fixes: a789aeba4196 ("KVM: VMX: Rename "vmx/evmcs.{ch}" to "vmx/hyperv.{ch}"")
Reviewed-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20221205082044.10141-1-lukas.bulwahn@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 89672a59c0c3a..8d90da0cda5a4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11322,7 +11322,7 @@ F:	arch/x86/kvm/hyperv.*
 F:	arch/x86/kvm/kvm_onhyperv.*
 F:	arch/x86/kvm/svm/hyperv.*
 F:	arch/x86/kvm/svm/svm_onhyperv.*
-F:	arch/x86/kvm/vmx/evmcs.*
+F:	arch/x86/kvm/vmx/hyperv.*
 
 KVM X86 Xen (KVM/Xen)
 M:	David Woodhouse <dwmw2@infradead.org>
-- 
GitLab


From a303def0fc18f0f2393b5c5f8ae3d2657a9713dc Mon Sep 17 00:00:00 2001
From: Lai Jiangshan <jiangshan.ljs@antgroup.com>
Date: Wed, 7 Dec 2022 20:06:16 +0800
Subject: [PATCH 700/875] kvm: Remove the unused macro KVM_MMU_READ_{,UN}LOCK()

No code is using KVM_MMU_READ_LOCK() or KVM_MMU_READ_UNLOCK().  They
used to be in virt/kvm/pfncache.c:

                KVM_MMU_READ_LOCK(kvm);
                retry = mmu_notifier_retry_hva(kvm, mmu_seq, uhva);
                KVM_MMU_READ_UNLOCK(kvm);

However, since 58cd407ca4c6 ("KVM: Fix multiple races in gfn=>pfn cache
refresh", 2022-05-25) the code is only relying on the MMU notifier's
invalidation count and sequence number.

Signed-off-by: Lai Jiangshan <jiangshan.ljs@antgroup.com>
Message-Id: <20221207120617.9409-1-jiangshanlai@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 virt/kvm/kvm_mm.h | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/virt/kvm/kvm_mm.h b/virt/kvm/kvm_mm.h
index a1ab15006af34..180f1a09e6ba7 100644
--- a/virt/kvm/kvm_mm.h
+++ b/virt/kvm/kvm_mm.h
@@ -14,14 +14,10 @@
 #define KVM_MMU_LOCK_INIT(kvm)		rwlock_init(&(kvm)->mmu_lock)
 #define KVM_MMU_LOCK(kvm)		write_lock(&(kvm)->mmu_lock)
 #define KVM_MMU_UNLOCK(kvm)		write_unlock(&(kvm)->mmu_lock)
-#define KVM_MMU_READ_LOCK(kvm)		read_lock(&(kvm)->mmu_lock)
-#define KVM_MMU_READ_UNLOCK(kvm)	read_unlock(&(kvm)->mmu_lock)
 #else
 #define KVM_MMU_LOCK_INIT(kvm)		spin_lock_init(&(kvm)->mmu_lock)
 #define KVM_MMU_LOCK(kvm)		spin_lock(&(kvm)->mmu_lock)
 #define KVM_MMU_UNLOCK(kvm)		spin_unlock(&(kvm)->mmu_lock)
-#define KVM_MMU_READ_LOCK(kvm)		spin_lock(&(kvm)->mmu_lock)
-#define KVM_MMU_READ_UNLOCK(kvm)	spin_unlock(&(kvm)->mmu_lock)
 #endif /* KVM_HAVE_MMU_RWLOCK */
 
 kvm_pfn_t hva_to_pfn(unsigned long addr, bool atomic, bool interruptible,
-- 
GitLab


From 562f5bc48a8d99a8898c734ecacf061a79a88fbf Mon Sep 17 00:00:00 2001
From: Lai Jiangshan <jiangshan.ljs@antgroup.com>
Date: Wed, 7 Dec 2022 20:05:05 +0800
Subject: [PATCH 701/875] kvm: x86/mmu: Remove duplicated "be split" in spte.h

"be split be split" -> "be split"

Signed-off-by: Lai Jiangshan <jiangshan.ljs@antgroup.com>
Message-Id: <20221207120505.9175-1-jiangshanlai@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/mmu/spte.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kvm/mmu/spte.h b/arch/x86/kvm/mmu/spte.h
index 1f03701b943a1..6f54dc9409c94 100644
--- a/arch/x86/kvm/mmu/spte.h
+++ b/arch/x86/kvm/mmu/spte.h
@@ -363,7 +363,7 @@ static __always_inline bool is_rsvd_spte(struct rsvd_bits_validate *rsvd_check,
  * A shadow-present leaf SPTE may be non-writable for 4 possible reasons:
  *
  *  1. To intercept writes for dirty logging. KVM write-protects huge pages
- *     so that they can be split be split down into the dirty logging
+ *     so that they can be split down into the dirty logging
  *     granularity (4KiB) whenever the guest writes to them. KVM also
  *     write-protects 4KiB pages so that writes can be recorded in the dirty log
  *     (e.g. if not using PML). SPTEs are write-protected for dirty logging
-- 
GitLab


From 23e528d9bce2385967370ad95a7d52a3c7a0a016 Mon Sep 17 00:00:00 2001
From: Sean Christopherson <seanjc@google.com>
Date: Wed, 7 Dec 2022 00:36:37 +0000
Subject: [PATCH 702/875] KVM: Delete extra block of "};" in the KVM API
 documentation

Delete an extra block of code/documentation that snuck in when KVM's
documentation was converted to ReST format.

Fixes: 106ee47dc633 ("docs: kvm: Convert api.txt to ReST format")
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20221207003637.2041211-1-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 Documentation/virt/kvm/api.rst | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst
index 778c6460d1de6..d795d683601cc 100644
--- a/Documentation/virt/kvm/api.rst
+++ b/Documentation/virt/kvm/api.rst
@@ -6577,11 +6577,6 @@ Please note that the kernel is allowed to use the kvm_run structure as the
 primary storage for certain register types. Therefore, the kernel may use the
 values in kvm_run even if the corresponding bit in kvm_dirty_regs is not set.
 
-::
-
-  };
-
-
 
 6. Capabilities that can be enabled on vCPUs
 ============================================
-- 
GitLab


From 385407a69d5140825d4cdab814cbf128ba63a64a Mon Sep 17 00:00:00 2001
From: Michal Luczaj <mhal@rbox.co>
Date: Mon, 26 Dec 2022 12:03:15 +0000
Subject: [PATCH 703/875] KVM: x86/xen: Fix memory leak in
 kvm_xen_write_hypercall_page()

Release page irrespectively of kvm_vcpu_write_guest() return value.

Suggested-by: Paul Durrant <paul@xen.org>
Fixes: 23200b7a30de ("KVM: x86/xen: intercept xen hypercalls if enabled")
Signed-off-by: Michal Luczaj <mhal@rbox.co>
Message-Id: <20221220151454.712165-1-mhal@rbox.co>
Reviewed-by: Paul Durrant <paul@xen.org>
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Message-Id: <20221226120320.1125390-1-dwmw2@infradead.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/xen.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kvm/xen.c b/arch/x86/kvm/xen.c
index d7af402402484..d1a98d834d185 100644
--- a/arch/x86/kvm/xen.c
+++ b/arch/x86/kvm/xen.c
@@ -1069,6 +1069,7 @@ int kvm_xen_write_hypercall_page(struct kvm_vcpu *vcpu, u64 data)
 		u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
 				  : kvm->arch.xen_hvm_config.blob_size_32;
 		u8 *page;
+		int ret;
 
 		if (page_num >= blob_size)
 			return 1;
@@ -1079,10 +1080,10 @@ int kvm_xen_write_hypercall_page(struct kvm_vcpu *vcpu, u64 data)
 		if (IS_ERR(page))
 			return PTR_ERR(page);
 
-		if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) {
-			kfree(page);
+		ret = kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE);
+		kfree(page);
+		if (ret)
 			return 1;
-		}
 	}
 	return 0;
 }
-- 
GitLab


From 92c58965e9656dc6e682a8ffe520fac0fb256d13 Mon Sep 17 00:00:00 2001
From: David Woodhouse <dwmw@amazon.co.uk>
Date: Mon, 26 Dec 2022 12:03:16 +0000
Subject: [PATCH 704/875] KVM: x86/xen: Use kvm_read_guest_virt() instead of
 open-coding it badly

In particular, we shouldn't assume that being contiguous in guest virtual
address space means being contiguous in guest *physical* address space.

In dropping the manual calls to kvm_mmu_gva_to_gpa_system(), also drop
the srcu_read_lock() that was around them. All call sites are reached
from kvm_xen_hypercall() which is called from the handle_exit function
with the read lock already held.

       536395260 ("KVM: x86/xen: handle PV timers oneshot mode")
       1a65105a5 ("KVM: x86/xen: handle PV spinlocks slowpath")

Fixes: 2fd6df2f2 ("KVM: x86/xen: intercept EVTCHNOP_send from guests")
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Message-Id: <20221226120320.1125390-2-dwmw2@infradead.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/xen.c | 56 +++++++++++++++-------------------------------
 1 file changed, 18 insertions(+), 38 deletions(-)

diff --git a/arch/x86/kvm/xen.c b/arch/x86/kvm/xen.c
index d1a98d834d185..929b887eafd7b 100644
--- a/arch/x86/kvm/xen.c
+++ b/arch/x86/kvm/xen.c
@@ -1184,30 +1184,22 @@ static bool wait_pending_event(struct kvm_vcpu *vcpu, int nr_ports,
 static bool kvm_xen_schedop_poll(struct kvm_vcpu *vcpu, bool longmode,
 				 u64 param, u64 *r)
 {
-	int idx, i;
 	struct sched_poll sched_poll;
 	evtchn_port_t port, *ports;
-	gpa_t gpa;
+	struct x86_exception e;
+	int i;
 
 	if (!lapic_in_kernel(vcpu) ||
 	    !(vcpu->kvm->arch.xen_hvm_config.flags & KVM_XEN_HVM_CONFIG_EVTCHN_SEND))
 		return false;
 
-	idx = srcu_read_lock(&vcpu->kvm->srcu);
-	gpa = kvm_mmu_gva_to_gpa_system(vcpu, param, NULL);
-	srcu_read_unlock(&vcpu->kvm->srcu, idx);
-	if (!gpa) {
-		*r = -EFAULT;
-		return true;
-	}
-
 	if (IS_ENABLED(CONFIG_64BIT) && !longmode) {
 		struct compat_sched_poll sp32;
 
 		/* Sanity check that the compat struct definition is correct */
 		BUILD_BUG_ON(sizeof(sp32) != 16);
 
-		if (kvm_vcpu_read_guest(vcpu, gpa, &sp32, sizeof(sp32))) {
+		if (kvm_read_guest_virt(vcpu, param, &sp32, sizeof(sp32), &e)) {
 			*r = -EFAULT;
 			return true;
 		}
@@ -1221,8 +1213,8 @@ static bool kvm_xen_schedop_poll(struct kvm_vcpu *vcpu, bool longmode,
 		sched_poll.nr_ports = sp32.nr_ports;
 		sched_poll.timeout = sp32.timeout;
 	} else {
-		if (kvm_vcpu_read_guest(vcpu, gpa, &sched_poll,
-					sizeof(sched_poll))) {
+		if (kvm_read_guest_virt(vcpu, param, &sched_poll,
+					sizeof(sched_poll), &e)) {
 			*r = -EFAULT;
 			return true;
 		}
@@ -1244,18 +1236,13 @@ static bool kvm_xen_schedop_poll(struct kvm_vcpu *vcpu, bool longmode,
 	} else
 		ports = &port;
 
+	if (kvm_read_guest_virt(vcpu, (gva_t)sched_poll.ports, ports,
+				sched_poll.nr_ports * sizeof(*ports), &e)) {
+		*r = -EFAULT;
+		return true;
+	}
+
 	for (i = 0; i < sched_poll.nr_ports; i++) {
-		idx = srcu_read_lock(&vcpu->kvm->srcu);
-		gpa = kvm_mmu_gva_to_gpa_system(vcpu,
-						(gva_t)(sched_poll.ports + i),
-						NULL);
-		srcu_read_unlock(&vcpu->kvm->srcu, idx);
-
-		if (!gpa || kvm_vcpu_read_guest(vcpu, gpa,
-						&ports[i], sizeof(port))) {
-			*r = -EFAULT;
-			goto out;
-		}
 		if (ports[i] >= max_evtchn_port(vcpu->kvm)) {
 			*r = -EINVAL;
 			goto out;
@@ -1331,9 +1318,8 @@ static bool kvm_xen_hcall_vcpu_op(struct kvm_vcpu *vcpu, bool longmode, int cmd,
 				  int vcpu_id, u64 param, u64 *r)
 {
 	struct vcpu_set_singleshot_timer oneshot;
+	struct x86_exception e;
 	s64 delta;
-	gpa_t gpa;
-	int idx;
 
 	if (!kvm_xen_timer_enabled(vcpu))
 		return false;
@@ -1344,9 +1330,6 @@ static bool kvm_xen_hcall_vcpu_op(struct kvm_vcpu *vcpu, bool longmode, int cmd,
 			*r = -EINVAL;
 			return true;
 		}
-		idx = srcu_read_lock(&vcpu->kvm->srcu);
-		gpa = kvm_mmu_gva_to_gpa_system(vcpu, param, NULL);
-		srcu_read_unlock(&vcpu->kvm->srcu, idx);
 
 		/*
 		 * The only difference for 32-bit compat is the 4 bytes of
@@ -1364,9 +1347,8 @@ static bool kvm_xen_hcall_vcpu_op(struct kvm_vcpu *vcpu, bool longmode, int cmd,
 		BUILD_BUG_ON(sizeof_field(struct compat_vcpu_set_singleshot_timer, flags) !=
 			     sizeof_field(struct vcpu_set_singleshot_timer, flags));
 
-		if (!gpa ||
-		    kvm_vcpu_read_guest(vcpu, gpa, &oneshot, longmode ? sizeof(oneshot) :
-					sizeof(struct compat_vcpu_set_singleshot_timer))) {
+		if (kvm_read_guest_virt(vcpu, param, &oneshot, longmode ? sizeof(oneshot) :
+					sizeof(struct compat_vcpu_set_singleshot_timer), &e)) {
 			*r = -EFAULT;
 			return true;
 		}
@@ -2003,14 +1985,12 @@ static bool kvm_xen_hcall_evtchn_send(struct kvm_vcpu *vcpu, u64 param, u64 *r)
 {
 	struct evtchnfd *evtchnfd;
 	struct evtchn_send send;
-	gpa_t gpa;
-	int idx;
+	struct x86_exception e;
 
-	idx = srcu_read_lock(&vcpu->kvm->srcu);
-	gpa = kvm_mmu_gva_to_gpa_system(vcpu, param, NULL);
-	srcu_read_unlock(&vcpu->kvm->srcu, idx);
+	/* Sanity check: this structure is the same for 32-bit and 64-bit */
+	BUILD_BUG_ON(sizeof(send) != 4);
 
-	if (!gpa || kvm_vcpu_read_guest(vcpu, gpa, &send, sizeof(send))) {
+	if (kvm_read_guest_virt(vcpu, param, &send, sizeof(send), &e)) {
 		*r = -EFAULT;
 		return true;
 	}
-- 
GitLab


From 70eae03087a3101493d9a1cf60c86c5f65600822 Mon Sep 17 00:00:00 2001
From: Paolo Bonzini <pbonzini@redhat.com>
Date: Mon, 26 Dec 2022 12:03:17 +0000
Subject: [PATCH 705/875] KVM: x86/xen: Fix SRCU/RCU usage in readers of
 evtchn_ports

The evtchnfd structure itself must be protected by either kvm->lock or
SRCU. Use the former in kvm_xen_eventfd_update(), since the lock is
being taken anyway; kvm_xen_hcall_evtchn_send() instead is a reader and
does not need kvm->lock, and is called in SRCU critical section from the
kvm_x86_handle_exit function.

It is also important to use rcu_read_{lock,unlock}() in
kvm_xen_hcall_evtchn_send(), because idr_remove() will *not*
use synchronize_srcu() to wait for readers to complete.

Remove a superfluous if (kvm) check before calling synchronize_srcu()
in kvm_xen_eventfd_deassign() where kvm has been dereferenced already.

Co-developed-by: Michal Luczaj <mhal@rbox.co>
Signed-off-by: Michal Luczaj <mhal@rbox.co>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Message-Id: <20221226120320.1125390-3-dwmw2@infradead.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/xen.c | 29 ++++++++++++++++++-----------
 1 file changed, 18 insertions(+), 11 deletions(-)

diff --git a/arch/x86/kvm/xen.c b/arch/x86/kvm/xen.c
index 929b887eafd7b..9b75457120f7d 100644
--- a/arch/x86/kvm/xen.c
+++ b/arch/x86/kvm/xen.c
@@ -1808,20 +1808,23 @@ static int kvm_xen_eventfd_update(struct kvm *kvm,
 {
 	u32 port = data->u.evtchn.send_port;
 	struct evtchnfd *evtchnfd;
+	int ret;
 
 	if (!port || port >= max_evtchn_port(kvm))
 		return -EINVAL;
 
+	/* Protect writes to evtchnfd as well as the idr lookup.  */
 	mutex_lock(&kvm->lock);
 	evtchnfd = idr_find(&kvm->arch.xen.evtchn_ports, port);
-	mutex_unlock(&kvm->lock);
 
+	ret = -ENOENT;
 	if (!evtchnfd)
-		return -ENOENT;
+		goto out_unlock;
 
 	/* For an UPDATE, nothing may change except the priority/vcpu */
+	ret = -EINVAL;
 	if (evtchnfd->type != data->u.evtchn.type)
-		return -EINVAL;
+		goto out_unlock;
 
 	/*
 	 * Port cannot change, and if it's zero that was an eventfd
@@ -1829,20 +1832,21 @@ static int kvm_xen_eventfd_update(struct kvm *kvm,
 	 */
 	if (!evtchnfd->deliver.port.port ||
 	    evtchnfd->deliver.port.port != data->u.evtchn.deliver.port.port)
-		return -EINVAL;
+		goto out_unlock;
 
 	/* We only support 2 level event channels for now */
 	if (data->u.evtchn.deliver.port.priority != KVM_IRQ_ROUTING_XEN_EVTCHN_PRIO_2LEVEL)
-		return -EINVAL;
+		goto out_unlock;
 
-	mutex_lock(&kvm->lock);
 	evtchnfd->deliver.port.priority = data->u.evtchn.deliver.port.priority;
 	if (evtchnfd->deliver.port.vcpu_id != data->u.evtchn.deliver.port.vcpu) {
 		evtchnfd->deliver.port.vcpu_id = data->u.evtchn.deliver.port.vcpu;
 		evtchnfd->deliver.port.vcpu_idx = -1;
 	}
+	ret = 0;
+out_unlock:
 	mutex_unlock(&kvm->lock);
-	return 0;
+	return ret;
 }
 
 /*
@@ -1935,8 +1939,7 @@ static int kvm_xen_eventfd_deassign(struct kvm *kvm, u32 port)
 	if (!evtchnfd)
 		return -ENOENT;
 
-	if (kvm)
-		synchronize_srcu(&kvm->srcu);
+	synchronize_srcu(&kvm->srcu);
 	if (!evtchnfd->deliver.port.port)
 		eventfd_ctx_put(evtchnfd->deliver.eventfd.ctx);
 	kfree(evtchnfd);
@@ -1989,14 +1992,18 @@ static bool kvm_xen_hcall_evtchn_send(struct kvm_vcpu *vcpu, u64 param, u64 *r)
 
 	/* Sanity check: this structure is the same for 32-bit and 64-bit */
 	BUILD_BUG_ON(sizeof(send) != 4);
-
 	if (kvm_read_guest_virt(vcpu, param, &send, sizeof(send), &e)) {
 		*r = -EFAULT;
 		return true;
 	}
 
-	/* The evtchn_ports idr is protected by vcpu->kvm->srcu */
+	/*
+	 * evtchnfd is protected by kvm->srcu; the idr lookup instead
+	 * is protected by RCU.
+	 */
+	rcu_read_lock();
 	evtchnfd = idr_find(&vcpu->kvm->arch.xen.evtchn_ports, send.port);
+	rcu_read_unlock();
 	if (!evtchnfd)
 		return false;
 
-- 
GitLab


From 1c14faa5087db0a098c3ab1e183f2b5df4b0d3f2 Mon Sep 17 00:00:00 2001
From: Michal Luczaj <mhal@rbox.co>
Date: Mon, 26 Dec 2022 12:03:18 +0000
Subject: [PATCH 706/875] KVM: x86/xen: Simplify eventfd IOCTLs

Port number is validated in kvm_xen_setattr_evtchn().
Remove superfluous checks in kvm_xen_eventfd_assign() and
kvm_xen_eventfd_update().

Signed-off-by: Michal Luczaj <mhal@rbox.co>
Message-Id: <20221222203021.1944101-3-mhal@rbox.co>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Message-Id: <20221226120320.1125390-4-dwmw2@infradead.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/xen.c | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/arch/x86/kvm/xen.c b/arch/x86/kvm/xen.c
index 9b75457120f7d..bddbe5ac5cfa2 100644
--- a/arch/x86/kvm/xen.c
+++ b/arch/x86/kvm/xen.c
@@ -1810,9 +1810,6 @@ static int kvm_xen_eventfd_update(struct kvm *kvm,
 	struct evtchnfd *evtchnfd;
 	int ret;
 
-	if (!port || port >= max_evtchn_port(kvm))
-		return -EINVAL;
-
 	/* Protect writes to evtchnfd as well as the idr lookup.  */
 	mutex_lock(&kvm->lock);
 	evtchnfd = idr_find(&kvm->arch.xen.evtchn_ports, port);
@@ -1858,12 +1855,9 @@ static int kvm_xen_eventfd_assign(struct kvm *kvm,
 {
 	u32 port = data->u.evtchn.send_port;
 	struct eventfd_ctx *eventfd = NULL;
-	struct evtchnfd *evtchnfd = NULL;
+	struct evtchnfd *evtchnfd;
 	int ret = -EINVAL;
 
-	if (!port || port >= max_evtchn_port(kvm))
-		return -EINVAL;
-
 	evtchnfd = kzalloc(sizeof(struct evtchnfd), GFP_KERNEL);
 	if (!evtchnfd)
 		return -ENOMEM;
-- 
GitLab


From b0305c1e0e27ad91187bc6d5ac3d502799faf239 Mon Sep 17 00:00:00 2001
From: David Woodhouse <dwmw@amazon.co.uk>
Date: Mon, 26 Dec 2022 12:03:19 +0000
Subject: [PATCH 707/875] KVM: x86/xen: Add KVM_XEN_INVALID_GPA and
 KVM_XEN_INVALID_GFN to uapi

These are (uint64_t)-1 magic values are a userspace ABI, allowing the
shared info pages and other enlightenments to be disabled. This isn't
a Xen ABI because Xen doesn't let the guest turn these off except with
the full SHUTDOWN_soft_reset mechanism. Under KVM, the userspace VMM is
expected to handle soft reset, and tear down the kernel parts of the
enlightenments accordingly.

Suggested-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Message-Id: <20221226120320.1125390-5-dwmw2@infradead.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/xen.c       | 14 +++++++-------
 include/uapi/linux/kvm.h |  3 +++
 2 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/arch/x86/kvm/xen.c b/arch/x86/kvm/xen.c
index bddbe5ac5cfa2..b178f40bd863c 100644
--- a/arch/x86/kvm/xen.c
+++ b/arch/x86/kvm/xen.c
@@ -41,7 +41,7 @@ static int kvm_xen_shared_info_init(struct kvm *kvm, gfn_t gfn)
 	int ret = 0;
 	int idx = srcu_read_lock(&kvm->srcu);
 
-	if (gfn == GPA_INVALID) {
+	if (gfn == KVM_XEN_INVALID_GFN) {
 		kvm_gpc_deactivate(gpc);
 		goto out;
 	}
@@ -659,7 +659,7 @@ int kvm_xen_hvm_get_attr(struct kvm *kvm, struct kvm_xen_hvm_attr *data)
 		if (kvm->arch.xen.shinfo_cache.active)
 			data->u.shared_info.gfn = gpa_to_gfn(kvm->arch.xen.shinfo_cache.gpa);
 		else
-			data->u.shared_info.gfn = GPA_INVALID;
+			data->u.shared_info.gfn = KVM_XEN_INVALID_GFN;
 		r = 0;
 		break;
 
@@ -705,7 +705,7 @@ int kvm_xen_vcpu_set_attr(struct kvm_vcpu *vcpu, struct kvm_xen_vcpu_attr *data)
 		BUILD_BUG_ON(offsetof(struct vcpu_info, time) !=
 			     offsetof(struct compat_vcpu_info, time));
 
-		if (data->u.gpa == GPA_INVALID) {
+		if (data->u.gpa == KVM_XEN_INVALID_GPA) {
 			kvm_gpc_deactivate(&vcpu->arch.xen.vcpu_info_cache);
 			r = 0;
 			break;
@@ -719,7 +719,7 @@ int kvm_xen_vcpu_set_attr(struct kvm_vcpu *vcpu, struct kvm_xen_vcpu_attr *data)
 		break;
 
 	case KVM_XEN_VCPU_ATTR_TYPE_VCPU_TIME_INFO:
-		if (data->u.gpa == GPA_INVALID) {
+		if (data->u.gpa == KVM_XEN_INVALID_GPA) {
 			kvm_gpc_deactivate(&vcpu->arch.xen.vcpu_time_info_cache);
 			r = 0;
 			break;
@@ -739,7 +739,7 @@ int kvm_xen_vcpu_set_attr(struct kvm_vcpu *vcpu, struct kvm_xen_vcpu_attr *data)
 			r = -EOPNOTSUPP;
 			break;
 		}
-		if (data->u.gpa == GPA_INVALID) {
+		if (data->u.gpa == KVM_XEN_INVALID_GPA) {
 			r = 0;
 		deactivate_out:
 			kvm_gpc_deactivate(&vcpu->arch.xen.runstate_cache);
@@ -937,7 +937,7 @@ int kvm_xen_vcpu_get_attr(struct kvm_vcpu *vcpu, struct kvm_xen_vcpu_attr *data)
 		if (vcpu->arch.xen.vcpu_info_cache.active)
 			data->u.gpa = vcpu->arch.xen.vcpu_info_cache.gpa;
 		else
-			data->u.gpa = GPA_INVALID;
+			data->u.gpa = KVM_XEN_INVALID_GPA;
 		r = 0;
 		break;
 
@@ -945,7 +945,7 @@ int kvm_xen_vcpu_get_attr(struct kvm_vcpu *vcpu, struct kvm_xen_vcpu_attr *data)
 		if (vcpu->arch.xen.vcpu_time_info_cache.active)
 			data->u.gpa = vcpu->arch.xen.vcpu_time_info_cache.gpa;
 		else
-			data->u.gpa = GPA_INVALID;
+			data->u.gpa = KVM_XEN_INVALID_GPA;
 		r = 0;
 		break;
 
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index 20522d4ba1e0d..55155e262646e 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -1767,6 +1767,7 @@ struct kvm_xen_hvm_attr {
 		__u8 runstate_update_flag;
 		struct {
 			__u64 gfn;
+#define KVM_XEN_INVALID_GFN ((__u64)-1)
 		} shared_info;
 		struct {
 			__u32 send_port;
@@ -1798,6 +1799,7 @@ struct kvm_xen_hvm_attr {
 	} u;
 };
 
+
 /* Available with KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_SHARED_INFO */
 #define KVM_XEN_ATTR_TYPE_LONG_MODE		0x0
 #define KVM_XEN_ATTR_TYPE_SHARED_INFO		0x1
@@ -1823,6 +1825,7 @@ struct kvm_xen_vcpu_attr {
 	__u16 pad[3];
 	union {
 		__u64 gpa;
+#define KVM_XEN_INVALID_GPA ((__u64)-1)
 		__u64 pad[8];
 		struct {
 			__u64 state;
-- 
GitLab


From af2808906aab0bf5786021d45b3ebfca6f4ad72f Mon Sep 17 00:00:00 2001
From: David Woodhouse <dwmw@amazon.co.uk>
Date: Mon, 26 Dec 2022 12:03:20 +0000
Subject: [PATCH 708/875] KVM: x86/xen: Documentation updates and
 clarifications

Most notably, the KVM_XEN_EVTCHN_RESET feature had escaped documentation
entirely. Along with how to turn most stuff off on SHUTDOWN_soft_reset.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Message-Id: <20221226120320.1125390-6-dwmw2@infradead.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 Documentation/virt/kvm/api.rst | 41 +++++++++++++++++++++-------------
 1 file changed, 26 insertions(+), 15 deletions(-)

diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst
index d795d683601cc..af64716573952 100644
--- a/Documentation/virt/kvm/api.rst
+++ b/Documentation/virt/kvm/api.rst
@@ -5343,9 +5343,9 @@ KVM_XEN_ATTR_TYPE_SHARED_INFO
   32 vCPUs in the shared_info page, KVM does not automatically do so
   and instead requires that KVM_XEN_VCPU_ATTR_TYPE_VCPU_INFO be used
   explicitly even when the vcpu_info for a given vCPU resides at the
-  "default" location in the shared_info page. This is because KVM is
-  not aware of the Xen CPU id which is used as the index into the
-  vcpu_info[] array, so cannot know the correct default location.
+  "default" location in the shared_info page. This is because KVM may
+  not be aware of the Xen CPU id which is used as the index into the
+  vcpu_info[] array, so may know the correct default location.
 
   Note that the shared info page may be constantly written to by KVM;
   it contains the event channel bitmap used to deliver interrupts to
@@ -5356,23 +5356,29 @@ KVM_XEN_ATTR_TYPE_SHARED_INFO
   any vCPU has been running or any event channel interrupts can be
   routed to the guest.
 
+  Setting the gfn to KVM_XEN_INVALID_GFN will disable the shared info
+  page.
+
 KVM_XEN_ATTR_TYPE_UPCALL_VECTOR
   Sets the exception vector used to deliver Xen event channel upcalls.
   This is the HVM-wide vector injected directly by the hypervisor
   (not through the local APIC), typically configured by a guest via
-  HVM_PARAM_CALLBACK_IRQ.
+  HVM_PARAM_CALLBACK_IRQ. This can be disabled again (e.g. for guest
+  SHUTDOWN_soft_reset) by setting it to zero.
 
 KVM_XEN_ATTR_TYPE_EVTCHN
   This attribute is available when the KVM_CAP_XEN_HVM ioctl indicates
   support for KVM_XEN_HVM_CONFIG_EVTCHN_SEND features. It configures
   an outbound port number for interception of EVTCHNOP_send requests
-  from the guest. A given sending port number may be directed back
-  to a specified vCPU (by APIC ID) / port / priority on the guest,
-  or to trigger events on an eventfd. The vCPU and priority can be
-  changed by setting KVM_XEN_EVTCHN_UPDATE in a subsequent call,
-  but other fields cannot change for a given sending port. A port
-  mapping is removed by using KVM_XEN_EVTCHN_DEASSIGN in the flags
-  field.
+  from the guest. A given sending port number may be directed back to
+  a specified vCPU (by APIC ID) / port / priority on the guest, or to
+  trigger events on an eventfd. The vCPU and priority can be changed
+  by setting KVM_XEN_EVTCHN_UPDATE in a subsequent call, but but other
+  fields cannot change for a given sending port. A port mapping is
+  removed by using KVM_XEN_EVTCHN_DEASSIGN in the flags field. Passing
+  KVM_XEN_EVTCHN_RESET in the flags field removes all interception of
+  outbound event channels. The values of the flags field are mutually
+  exclusive and cannot be combined as a bitmask.
 
 KVM_XEN_ATTR_TYPE_XEN_VERSION
   This attribute is available when the KVM_CAP_XEN_HVM ioctl indicates
@@ -5388,7 +5394,7 @@ KVM_XEN_ATTR_TYPE_RUNSTATE_UPDATE_FLAG
   support for KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG. It enables the
   XEN_RUNSTATE_UPDATE flag which allows guest vCPUs to safely read
   other vCPUs' vcpu_runstate_info. Xen guests enable this feature via
-  the VM_ASST_TYPE_runstate_update_flag of the HYPERVISOR_vm_assist
+  the VMASST_TYPE_runstate_update_flag of the HYPERVISOR_vm_assist
   hypercall.
 
 4.127 KVM_XEN_HVM_GET_ATTR
@@ -5446,15 +5452,18 @@ KVM_XEN_VCPU_ATTR_TYPE_VCPU_INFO
   As with the shared_info page for the VM, the corresponding page may be
   dirtied at any time if event channel interrupt delivery is enabled, so
   userspace should always assume that the page is dirty without relying
-  on dirty logging.
+  on dirty logging. Setting the gpa to KVM_XEN_INVALID_GPA will disable
+  the vcpu_info.
 
 KVM_XEN_VCPU_ATTR_TYPE_VCPU_TIME_INFO
   Sets the guest physical address of an additional pvclock structure
   for a given vCPU. This is typically used for guest vsyscall support.
+  Setting the gpa to KVM_XEN_INVALID_GPA will disable the structure.
 
 KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_ADDR
   Sets the guest physical address of the vcpu_runstate_info for a given
   vCPU. This is how a Xen guest tracks CPU state such as steal time.
+  Setting the gpa to KVM_XEN_INVALID_GPA will disable the runstate area.
 
 KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_CURRENT
   Sets the runstate (RUNSTATE_running/_runnable/_blocked/_offline) of
@@ -5487,7 +5496,8 @@ KVM_XEN_VCPU_ATTR_TYPE_TIMER
   This attribute is available when the KVM_CAP_XEN_HVM ioctl indicates
   support for KVM_XEN_HVM_CONFIG_EVTCHN_SEND features. It sets the
   event channel port/priority for the VIRQ_TIMER of the vCPU, as well
-  as allowing a pending timer to be saved/restored.
+  as allowing a pending timer to be saved/restored. Setting the timer
+  port to zero disables kernel handling of the singleshot timer.
 
 KVM_XEN_VCPU_ATTR_TYPE_UPCALL_VECTOR
   This attribute is available when the KVM_CAP_XEN_HVM ioctl indicates
@@ -5495,7 +5505,8 @@ KVM_XEN_VCPU_ATTR_TYPE_UPCALL_VECTOR
   per-vCPU local APIC upcall vector, configured by a Xen guest with
   the HVMOP_set_evtchn_upcall_vector hypercall. This is typically
   used by Windows guests, and is distinct from the HVM-wide upcall
-  vector configured with HVM_PARAM_CALLBACK_IRQ.
+  vector configured with HVM_PARAM_CALLBACK_IRQ. It is disabled by
+  setting the vector to zero.
 
 
 4.129 KVM_XEN_VCPU_GET_ATTR
-- 
GitLab


From e2d371484653ac83b970d3ebcf343383f39f8b6b Mon Sep 17 00:00:00 2001
From: Ravi Bangoria <ravi.bangoria@amd.com>
Date: Fri, 18 Nov 2022 10:45:39 +0530
Subject: [PATCH 709/875] perf core: Return error pointer if inherit_event()
 fails to find pmu_ctx

inherit_event() returns NULL only when it finds orphaned events
otherwise it returns either valid child_event pointer or an error
pointer. Follow the same when it fails to find pmu_ctx.

Fixes: bd2756811766 ("perf: Rewrite core context handling")
Reported-by: Dan Carpenter <error27@gmail.com>
Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20221118051539.820-1-ravi.bangoria@amd.com
---
 kernel/events/core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/kernel/events/core.c b/kernel/events/core.c
index eacc3702654d5..4bd2434251f01 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -13231,7 +13231,7 @@ inherit_event(struct perf_event *parent_event,
 	pmu_ctx = find_get_pmu_context(child_event->pmu, child_ctx, child_event);
 	if (IS_ERR(pmu_ctx)) {
 		free_event(child_event);
-		return NULL;
+		return ERR_CAST(pmu_ctx);
 	}
 	child_event->pmu_ctx = pmu_ctx;
 
-- 
GitLab


From f841b682baef90ee144df8b12e2c76aa460717c1 Mon Sep 17 00:00:00 2001
From: Chengming Zhou <zhouchengming@bytedance.com>
Date: Wed, 7 Dec 2022 20:40:23 +0800
Subject: [PATCH 710/875] perf/core: Fix cgroup events tracking

We encounter perf warnings when using cgroup events like:

  cd /sys/fs/cgroup
  mkdir test
  perf stat -e cycles -a -G test

Which then triggers:

  WARNING: CPU: 0 PID: 690 at kernel/events/core.c:849 perf_cgroup_switch+0xb2/0xc0
  Call Trace:
   <TASK>
   __schedule+0x4ae/0x9f0
   ? _raw_spin_unlock_irqrestore+0x23/0x40
   ? __cond_resched+0x18/0x20
   preempt_schedule_common+0x2d/0x70
   __cond_resched+0x18/0x20
   wait_for_completion+0x2f/0x160
   ? cpu_stop_queue_work+0x9e/0x130
   affine_move_task+0x18a/0x4f0

  WARNING: CPU: 0 PID: 690 at kernel/events/core.c:829 ctx_sched_in+0x1cf/0x1e0
  Call Trace:
   <TASK>
   ? ctx_sched_out+0xb7/0x1b0
   perf_cgroup_switch+0x88/0xc0
   __schedule+0x4ae/0x9f0
   ? _raw_spin_unlock_irqrestore+0x23/0x40
   ? __cond_resched+0x18/0x20
   preempt_schedule_common+0x2d/0x70
   __cond_resched+0x18/0x20
   wait_for_completion+0x2f/0x160
   ? cpu_stop_queue_work+0x9e/0x130
   affine_move_task+0x18a/0x4f0

The above two warnings are not complete here since I remove other
unimportant information. The problem is caused by the perf cgroup
events tracking:

  CPU0					CPU1
  perf_event_open()
    perf_event_alloc()
      account_event()
	account_event_cpu()
	  atomic_inc(perf_cgroup_events)
					  __perf_event_task_sched_out()
					    if (atomic_read(perf_cgroup_events))
					      perf_cgroup_switch()
						// kernel/events/core.c:849
						WARN_ON_ONCE(cpuctx->ctx.nr_cgroups == 0)
						if (READ_ONCE(cpuctx->cgrp) == cgrp) // false
						  return
						perf_ctx_lock()
						ctx_sched_out()
						cpuctx->cgrp = cgrp
						ctx_sched_in()
						  perf_cgroup_set_timestamp()
						    // kernel/events/core.c:829
						    WARN_ON_ONCE(!ctx->nr_cgroups)
						perf_ctx_unlock()
    perf_install_in_context()
      cpu_function_call()
					  __perf_install_in_context()
					    add_event_to_ctx()
					      list_add_event()
						perf_cgroup_event_enable()
						  ctx->nr_cgroups++
						  cpuctx->cgrp = X

We can see from above that we wrongly use percpu atomic perf_cgroup_events
to check if we need to perf_cgroup_switch(), which should only be used
when we know this CPU has cgroup events enabled.

The commit bd2756811766 ("perf: Rewrite core context handling") change
to have only one context per-CPU, so we can just use cpuctx->cgrp to
check if this CPU has cgroup events enabled.

So percpu atomic perf_cgroup_events is not needed.

Fixes: bd2756811766 ("perf: Rewrite core context handling")
Signed-off-by: Chengming Zhou <zhouchengming@bytedance.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: Ravi Bangoria <ravi.bangoria@amd.com>
Link: https://lkml.kernel.org/r/20221207124023.66252-1-zhouchengming@bytedance.com
---
 kernel/events/core.c | 42 ++++++++++--------------------------------
 1 file changed, 10 insertions(+), 32 deletions(-)

diff --git a/kernel/events/core.c b/kernel/events/core.c
index 4bd2434251f01..37c0f04d7a005 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -380,7 +380,6 @@ enum event_type_t {
 
 /*
  * perf_sched_events : >0 events exist
- * perf_cgroup_events: >0 per-cpu cgroup events exist on this cpu
  */
 
 static void perf_sched_delayed(struct work_struct *work);
@@ -389,7 +388,6 @@ static DECLARE_DELAYED_WORK(perf_sched_work, perf_sched_delayed);
 static DEFINE_MUTEX(perf_sched_mutex);
 static atomic_t perf_sched_count;
 
-static DEFINE_PER_CPU(atomic_t, perf_cgroup_events);
 static DEFINE_PER_CPU(struct pmu_event_list, pmu_sb_events);
 
 static atomic_t nr_mmap_events __read_mostly;
@@ -844,9 +842,16 @@ static void perf_cgroup_switch(struct task_struct *task)
 	struct perf_cpu_context *cpuctx = this_cpu_ptr(&perf_cpu_context);
 	struct perf_cgroup *cgrp;
 
-	cgrp = perf_cgroup_from_task(task, NULL);
+	/*
+	 * cpuctx->cgrp is set when the first cgroup event enabled,
+	 * and is cleared when the last cgroup event disabled.
+	 */
+	if (READ_ONCE(cpuctx->cgrp) == NULL)
+		return;
 
 	WARN_ON_ONCE(cpuctx->ctx.nr_cgroups == 0);
+
+	cgrp = perf_cgroup_from_task(task, NULL);
 	if (READ_ONCE(cpuctx->cgrp) == cgrp)
 		return;
 
@@ -3631,8 +3636,7 @@ void __perf_event_task_sched_out(struct task_struct *task,
 	 * to check if we have to switch out PMU state.
 	 * cgroup event are system-wide mode only
 	 */
-	if (atomic_read(this_cpu_ptr(&perf_cgroup_events)))
-		perf_cgroup_switch(next);
+	perf_cgroup_switch(next);
 }
 
 static bool perf_less_group_idx(const void *l, const void *r)
@@ -4974,15 +4978,6 @@ static void unaccount_pmu_sb_event(struct perf_event *event)
 		detach_sb_event(event);
 }
 
-static void unaccount_event_cpu(struct perf_event *event, int cpu)
-{
-	if (event->parent)
-		return;
-
-	if (is_cgroup_event(event))
-		atomic_dec(&per_cpu(perf_cgroup_events, cpu));
-}
-
 #ifdef CONFIG_NO_HZ_FULL
 static DEFINE_SPINLOCK(nr_freq_lock);
 #endif
@@ -5048,8 +5043,6 @@ static void unaccount_event(struct perf_event *event)
 			schedule_delayed_work(&perf_sched_work, HZ);
 	}
 
-	unaccount_event_cpu(event, event->cpu);
-
 	unaccount_pmu_sb_event(event);
 }
 
@@ -11679,15 +11672,6 @@ static void account_pmu_sb_event(struct perf_event *event)
 		attach_sb_event(event);
 }
 
-static void account_event_cpu(struct perf_event *event, int cpu)
-{
-	if (event->parent)
-		return;
-
-	if (is_cgroup_event(event))
-		atomic_inc(&per_cpu(perf_cgroup_events, cpu));
-}
-
 /* Freq events need the tick to stay alive (see perf_event_task_tick). */
 static void account_freq_event_nohz(void)
 {
@@ -11775,8 +11759,6 @@ static void account_event(struct perf_event *event)
 	}
 enabled:
 
-	account_event_cpu(event, event->cpu);
-
 	account_pmu_sb_event(event);
 }
 
@@ -12822,13 +12804,11 @@ static void __perf_pmu_remove(struct perf_event_context *ctx,
 
 	perf_event_groups_for_cpu_pmu(event, groups, cpu, pmu) {
 		perf_remove_from_context(event, 0);
-		unaccount_event_cpu(event, cpu);
 		put_pmu_ctx(event->pmu_ctx);
 		list_add(&event->migrate_entry, events);
 
 		for_each_sibling_event(sibling, event) {
 			perf_remove_from_context(sibling, 0);
-			unaccount_event_cpu(sibling, cpu);
 			put_pmu_ctx(sibling->pmu_ctx);
 			list_add(&sibling->migrate_entry, events);
 		}
@@ -12847,7 +12827,6 @@ static void __perf_pmu_install_event(struct pmu *pmu,
 
 	if (event->state >= PERF_EVENT_STATE_OFF)
 		event->state = PERF_EVENT_STATE_INACTIVE;
-	account_event_cpu(event, cpu);
 	perf_install_in_context(ctx, event, cpu);
 }
 
@@ -13742,8 +13721,7 @@ static int __perf_cgroup_move(void *info)
 	struct task_struct *task = info;
 
 	preempt_disable();
-	if (atomic_read(this_cpu_ptr(&perf_cgroup_events)))
-		perf_cgroup_switch(task);
+	perf_cgroup_switch(task);
 	preempt_enable();
 
 	return 0;
-- 
GitLab


From 08245672cdc6505550d1a5020603b0a8d4a6dcc7 Mon Sep 17 00:00:00 2001
From: Colin Ian King <colin.i.king@gmail.com>
Date: Fri, 2 Dec 2022 13:51:49 +0000
Subject: [PATCH 711/875] perf/x86/amd: fix potential integer overflow on shift
 of a int

The left shift of int 32 bit integer constant 1 is evaluated using 32 bit
arithmetic and then passed as a 64 bit function argument. In the case where
i is 32 or more this can lead to an overflow.  Avoid this by shifting
using the BIT_ULL macro instead.

Fixes: 471af006a747 ("perf/x86/amd: Constrain Large Increment per Cycle events")
Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Ian Rogers <irogers@google.com>
Acked-by: Kim Phillips <kim.phillips@amd.com>
Link: https://lore.kernel.org/r/20221202135149.1797974-1-colin.i.king@gmail.com
---
 arch/x86/events/amd/core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index d6f3703e41194..4386b10682ce4 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -1387,7 +1387,7 @@ static int __init amd_core_pmu_init(void)
 		 * numbered counter following it.
 		 */
 		for (i = 0; i < x86_pmu.num_counters - 1; i += 2)
-			even_ctr_mask |= 1 << i;
+			even_ctr_mask |= BIT_ULL(i);
 
 		pair_constraint = (struct event_constraint)
 				    __EVENT_CONSTRAINT(0, even_ctr_mask, 0,
-- 
GitLab


From a551844e345ba2a1c533dee4b55cb0efddb1bcda Mon Sep 17 00:00:00 2001
From: Peter Zijlstra <peterz@infradead.org>
Date: Mon, 19 Dec 2022 15:40:04 +0100
Subject: [PATCH 712/875] perf: Fix use-after-free in error path

The syscall error path has a use-after-free; put_pmu_ctx() will
reference ctx, therefore we must ensure ctx is destroyed after pmu_ctx
is.

Fixes: bd2756811766 ("perf: Rewrite core context handling")
Reported-by: syzbot+b8e8c01c8ade4fe6e48f@syzkaller.appspotmail.com
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: Chengming Zhou <zhouchengming@bytedance.com>
Link: https://lkml.kernel.org/r/Y6B3xEgkbmFUCeni@hirez.programming.kicks-ass.net
---
 kernel/events/core.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/kernel/events/core.c b/kernel/events/core.c
index 37c0f04d7a005..63d674c9b70e8 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -12671,7 +12671,8 @@ SYSCALL_DEFINE5(perf_event_open,
 	return event_fd;
 
 err_context:
-	/* event->pmu_ctx freed by free_event() */
+	put_pmu_ctx(event->pmu_ctx);
+	event->pmu_ctx = NULL; /* _free_event() */
 err_locked:
 	mutex_unlock(&ctx->mutex);
 	perf_unpin_context(ctx);
@@ -12784,6 +12785,7 @@ perf_event_create_kernel_counter(struct perf_event_attr *attr, int cpu,
 
 err_pmu_ctx:
 	put_pmu_ctx(pmu_ctx);
+	event->pmu_ctx = NULL; /* _free_event() */
 err_unlock:
 	mutex_unlock(&ctx->mutex);
 	perf_unpin_context(ctx);
-- 
GitLab


From 0a041ebca4956292cadfb14a63ace3a9c1dcb0a3 Mon Sep 17 00:00:00 2001
From: Namhyung Kim <namhyung@kernel.org>
Date: Tue, 20 Dec 2022 14:31:40 -0800
Subject: [PATCH 713/875] perf/core: Call LSM hook after copying
 perf_event_attr

It passes the attr struct to the security_perf_event_open() but it's
not initialized yet.

Fixes: da97e18458fb ("perf_event: Add support for LSM and SELinux checks")
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Joel Fernandes (Google) <joel@joelfernandes.org>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20221220223140.4020470-1-namhyung@kernel.org
---
 kernel/events/core.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/kernel/events/core.c b/kernel/events/core.c
index 63d674c9b70e8..d56328e5080e9 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -12321,12 +12321,12 @@ SYSCALL_DEFINE5(perf_event_open,
 	if (flags & ~PERF_FLAG_ALL)
 		return -EINVAL;
 
-	/* Do we allow access to perf_event_open(2) ? */
-	err = security_perf_event_open(&attr, PERF_SECURITY_OPEN);
+	err = perf_copy_attr(attr_uptr, &attr);
 	if (err)
 		return err;
 
-	err = perf_copy_attr(attr_uptr, &attr);
+	/* Do we allow access to perf_event_open(2) ? */
+	err = security_perf_event_open(&attr, PERF_SECURITY_OPEN);
 	if (err)
 		return err;
 
-- 
GitLab


From ade8c20847fcc3f4de08b35f730ec04ef29ddbdc Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Thu, 15 Dec 2022 17:43:23 +0100
Subject: [PATCH 714/875] x86/calldepth: Fix incorrect init section references

The addition of callthunks_translate_call_dest means that
skip_addr() and patch_dest() can no longer be discarded
as part of the __init section freeing:

WARNING: modpost: vmlinux.o: section mismatch in reference: callthunks_translate_call_dest.cold (section: .text.unlikely) -> skip_addr (section: .init.text)
WARNING: modpost: vmlinux.o: section mismatch in reference: callthunks_translate_call_dest.cold (section: .text.unlikely) -> patch_dest (section: .init.text)
WARNING: modpost: vmlinux.o: section mismatch in reference: is_callthunk.cold (section: .text.unlikely) -> skip_addr (section: .init.text)
ERROR: modpost: Section mismatches detected.
Set CONFIG_SECTION_MISMATCH_WARN_ONLY=y to allow them.

Fixes: b2e9dfe54be4 ("x86/bpf: Emit call depth accounting if required")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20221215164334.968863-1-arnd@kernel.org
---
 arch/x86/kernel/callthunks.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/callthunks.c b/arch/x86/kernel/callthunks.c
index 7d2c75ec9a8cd..ffea98f9064be 100644
--- a/arch/x86/kernel/callthunks.c
+++ b/arch/x86/kernel/callthunks.c
@@ -119,7 +119,7 @@ static bool is_coretext(const struct core_text *ct, void *addr)
 	return within_module_coretext(addr);
 }
 
-static __init_or_module bool skip_addr(void *dest)
+static bool skip_addr(void *dest)
 {
 	if (dest == error_entry)
 		return true;
@@ -181,7 +181,7 @@ static const u8 nops[] = {
 	0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90,
 };
 
-static __init_or_module void *patch_dest(void *dest, bool direct)
+static void *patch_dest(void *dest, bool direct)
 {
 	unsigned int tsize = SKL_TMPL_SIZE;
 	u8 *pad = dest - tsize;
-- 
GitLab


From 1993bf97992df2d560287f3c4120eda57426843d Mon Sep 17 00:00:00 2001
From: "Masami Hiramatsu (Google)" <mhiramat@kernel.org>
Date: Mon, 19 Dec 2022 23:35:10 +0900
Subject: [PATCH 715/875] x86/kprobes: Fix kprobes instruction boudary check
 with CONFIG_RETHUNK

Since the CONFIG_RETHUNK and CONFIG_SLS will use INT3 for stopping
speculative execution after RET instruction, kprobes always failes to
check the probed instruction boundary by decoding the function body if
the probed address is after such sequence. (Note that some conditional
code blocks will be placed after function return, if compiler decides
it is not on the hot path.)

This is because kprobes expects kgdb puts the INT3 as a software
breakpoint and it will replace the original instruction.
But these INT3 are not such purpose, it doesn't need to recover the
original instruction.

To avoid this issue, kprobes checks whether the INT3 is owned by
kgdb or not, and if so, stop decoding and make it fail. The other
INT3 will come from CONFIG_RETHUNK/CONFIG_SLS and those can be
treated as a one-byte instruction.

Fixes: e463a09af2f0 ("x86: Add straight-line-speculation mitigation")
Suggested-by: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/167146051026.1374301.392728975473572291.stgit@devnote3
---
 arch/x86/kernel/kprobes/core.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/kprobes/core.c b/arch/x86/kernel/kprobes/core.c
index 66299682b6b7e..b36f3c367cb24 100644
--- a/arch/x86/kernel/kprobes/core.c
+++ b/arch/x86/kernel/kprobes/core.c
@@ -37,6 +37,7 @@
 #include <linux/extable.h>
 #include <linux/kdebug.h>
 #include <linux/kallsyms.h>
+#include <linux/kgdb.h>
 #include <linux/ftrace.h>
 #include <linux/kasan.h>
 #include <linux/moduleloader.h>
@@ -281,12 +282,15 @@ static int can_probe(unsigned long paddr)
 		if (ret < 0)
 			return 0;
 
+#ifdef CONFIG_KGDB
 		/*
-		 * Another debugging subsystem might insert this breakpoint.
-		 * In that case, we can't recover it.
+		 * If there is a dynamically installed kgdb sw breakpoint,
+		 * this function should not be probed.
 		 */
-		if (insn.opcode.bytes[0] == INT3_INSN_OPCODE)
+		if (insn.opcode.bytes[0] == INT3_INSN_OPCODE &&
+		    kgdb_has_hit_break(addr))
 			return 0;
+#endif
 		addr += insn.length;
 	}
 
-- 
GitLab


From 63dc6325ff41ee9e570bde705ac34a39c5dbeb44 Mon Sep 17 00:00:00 2001
From: "Masami Hiramatsu (Google)" <mhiramat@kernel.org>
Date: Mon, 19 Dec 2022 23:35:19 +0900
Subject: [PATCH 716/875] x86/kprobes: Fix optprobe optimization check with
 CONFIG_RETHUNK

Since the CONFIG_RETHUNK and CONFIG_SLS will use INT3 for stopping
speculative execution after function return, kprobe jump optimization
always fails on the functions with such INT3 inside the function body.
(It already checks the INT3 padding between functions, but not inside
 the function)

To avoid this issue, as same as kprobes, check whether the INT3 comes
from kgdb or not, and if so, stop decoding and make it fail. The other
INT3 will come from CONFIG_RETHUNK/CONFIG_SLS and those can be
treated as a one-byte instruction.

Fixes: e463a09af2f0 ("x86: Add straight-line-speculation mitigation")
Suggested-by: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/167146051929.1374301.7419382929328081706.stgit@devnote3
---
 arch/x86/kernel/kprobes/opt.c | 28 ++++++++--------------------
 1 file changed, 8 insertions(+), 20 deletions(-)

diff --git a/arch/x86/kernel/kprobes/opt.c b/arch/x86/kernel/kprobes/opt.c
index e6b8c5362b945..e57e07b0edb64 100644
--- a/arch/x86/kernel/kprobes/opt.c
+++ b/arch/x86/kernel/kprobes/opt.c
@@ -15,6 +15,7 @@
 #include <linux/extable.h>
 #include <linux/kdebug.h>
 #include <linux/kallsyms.h>
+#include <linux/kgdb.h>
 #include <linux/ftrace.h>
 #include <linux/objtool.h>
 #include <linux/pgtable.h>
@@ -279,19 +280,6 @@ static int insn_is_indirect_jump(struct insn *insn)
 	return ret;
 }
 
-static bool is_padding_int3(unsigned long addr, unsigned long eaddr)
-{
-	unsigned char ops;
-
-	for (; addr < eaddr; addr++) {
-		if (get_kernel_nofault(ops, (void *)addr) < 0 ||
-		    ops != INT3_INSN_OPCODE)
-			return false;
-	}
-
-	return true;
-}
-
 /* Decode whole function to ensure any instructions don't jump into target */
 static int can_optimize(unsigned long paddr)
 {
@@ -334,15 +322,15 @@ static int can_optimize(unsigned long paddr)
 		ret = insn_decode_kernel(&insn, (void *)recovered_insn);
 		if (ret < 0)
 			return 0;
-
+#ifdef CONFIG_KGDB
 		/*
-		 * In the case of detecting unknown breakpoint, this could be
-		 * a padding INT3 between functions. Let's check that all the
-		 * rest of the bytes are also INT3.
+		 * If there is a dynamically installed kgdb sw breakpoint,
+		 * this function should not be probed.
 		 */
-		if (insn.opcode.bytes[0] == INT3_INSN_OPCODE)
-			return is_padding_int3(addr, paddr - offset + size) ? 1 : 0;
-
+		if (insn.opcode.bytes[0] == INT3_INSN_OPCODE &&
+		    kgdb_has_hit_break(addr))
+			return 0;
+#endif
 		/* Recover address */
 		insn.kaddr = (void *)addr;
 		insn.next_byte = (void *)(addr + insn.length);
-- 
GitLab


From 94cd8fa09f5f1ebdd4e90964b08b7f2cc4b36c43 Mon Sep 17 00:00:00 2001
From: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Date: Wed, 14 Dec 2022 17:20:08 -0500
Subject: [PATCH 717/875] futex: Fix futex_waitv() hrtimer debug object leak on
 kcalloc error

In a scenario where kcalloc() fails to allocate memory, the futex_waitv
system call immediately returns -ENOMEM without invoking
destroy_hrtimer_on_stack(). When CONFIG_DEBUG_OBJECTS_TIMERS=y, this
results in leaking a timer debug object.

Fixes: bf69bad38cf6 ("futex: Implement sys_futex_waitv()")
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Cc: stable@vger.kernel.org
Cc: stable@vger.kernel.org # v5.16+
Link: https://lore.kernel.org/r/20221214222008.200393-1-mathieu.desnoyers@efficios.com
---
 kernel/futex/syscalls.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/kernel/futex/syscalls.c b/kernel/futex/syscalls.c
index 086a22d1adb78..a8074079b09e8 100644
--- a/kernel/futex/syscalls.c
+++ b/kernel/futex/syscalls.c
@@ -286,19 +286,22 @@ SYSCALL_DEFINE5(futex_waitv, struct futex_waitv __user *, waiters,
 	}
 
 	futexv = kcalloc(nr_futexes, sizeof(*futexv), GFP_KERNEL);
-	if (!futexv)
-		return -ENOMEM;
+	if (!futexv) {
+		ret = -ENOMEM;
+		goto destroy_timer;
+	}
 
 	ret = futex_parse_waitv(futexv, waiters, nr_futexes);
 	if (!ret)
 		ret = futex_wait_multiple(futexv, nr_futexes, timeout ? &to : NULL);
 
+	kfree(futexv);
+
+destroy_timer:
 	if (timeout) {
 		hrtimer_cancel(&to.timer);
 		destroy_hrtimer_on_stack(&to.timer);
 	}
-
-	kfree(futexv);
 	return ret;
 }
 
-- 
GitLab


From 9eb803402a2a83400c6c6afd900e3b7c87c06816 Mon Sep 17 00:00:00 2001
From: Stefan Metzmacher <metze@samba.org>
Date: Wed, 16 Nov 2022 21:25:24 +0100
Subject: [PATCH 718/875] uapi:io_uring.h: allow linux/time_types.h to be
 skipped

include/uapi/linux/io_uring.h is synced 1:1 into
liburing:src/include/liburing/io_uring.h.

liburing has a configure check to detect the need for
linux/time_types.h. It can opt-out by defining
UAPI_LINUX_IO_URING_H_SKIP_LINUX_TIME_TYPES_H

Fixes: 78a861b94959 ("io_uring: add sync cancelation API through io_uring_register()")
Link: https://github.com/axboe/liburing/issues/708
Link: https://github.com/axboe/liburing/pull/709
Link: https://lore.kernel.org/io-uring/20221115212614.1308132-1-ammar.faizi@intel.com/T/#m9f5dd571cd4f6a5dee84452dbbca3b92ba7a4091
CC: Jens Axboe <axboe@kernel.dk>
Cc: Ammar Faizi <ammarfaizi2@gnuweeb.org>
Signed-off-by: Stefan Metzmacher <metze@samba.org>
Reviewed-by: Ammar Faizi <ammarfaizi2@gnuweeb.org>
Link: https://lore.kernel.org/r/7071a0a1d751221538b20b63f9160094fc7e06f4.1668630247.git.metze@samba.org
Signed-off-by: Jens Axboe <axboe@kernel.dk>
---
 include/uapi/linux/io_uring.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/include/uapi/linux/io_uring.h b/include/uapi/linux/io_uring.h
index 9d4c4078e8d00..2780bce62fafe 100644
--- a/include/uapi/linux/io_uring.h
+++ b/include/uapi/linux/io_uring.h
@@ -10,7 +10,15 @@
 
 #include <linux/fs.h>
 #include <linux/types.h>
+/*
+ * this file is shared with liburing and that has to autodetect
+ * if linux/time_types.h is available or not, it can
+ * define UAPI_LINUX_IO_URING_H_SKIP_LINUX_TIME_TYPES_H
+ * if linux/time_types.h is not available
+ */
+#ifndef UAPI_LINUX_IO_URING_H_SKIP_LINUX_TIME_TYPES_H
 #include <linux/time_types.h>
+#endif
 
 #ifdef __cplusplus
 extern "C" {
-- 
GitLab


From 9d8b5376cc2848ca22314fdec9a7a45b1bf69189 Mon Sep 17 00:00:00 2001
From: Randy Dunlap <rdunlap@infradead.org>
Date: Fri, 25 Nov 2022 16:04:01 -0800
Subject: [PATCH 719/875] fbdev: make offb driver tristate
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Make the offb (Open Firmware frame buffer) driver tristate,
i.e., so that it can be built as a loadable module.

However, it still depends on the setting of DRM_OFDRM
so that both of these drivers cannot be builtin at the same time
nor can one be builtin and the other one a loadable module.

Build-tested successfully with all combination of DRM_OFDRM and FB_OF.

This fixes a build issue that Michal reported when FB_OF=y and
DRM_OFDRM=m:

powerpc64-linux-ld: drivers/video/fbdev/offb.o:(.data.rel.ro+0x58): undefined reference to `cfb_fillrect'
powerpc64-linux-ld: drivers/video/fbdev/offb.o:(.data.rel.ro+0x60): undefined reference to `cfb_copyarea'
powerpc64-linux-ld: drivers/video/fbdev/offb.o:(.data.rel.ro+0x68): undefined reference to `cfb_imageblit'

Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Cc: Masahiro Yamada <masahiroy@kernel.org>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: Michal Suchánek <msuchanek@suse.de>
Cc: linuxppc-dev@lists.ozlabs.org
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Helge Deller <deller@gmx.de>
Cc: linux-fbdev@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
Signed-off-by: Helge Deller <deller@gmx.de>
---
 drivers/video/fbdev/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig
index df6e09f7d2422..b2bed599e6c6e 100644
--- a/drivers/video/fbdev/Kconfig
+++ b/drivers/video/fbdev/Kconfig
@@ -456,8 +456,8 @@ config FB_ATARI
 	  chipset found in Ataris.
 
 config FB_OF
-	bool "Open Firmware frame buffer device support"
-	depends on (FB = y) && PPC && (!PPC_PSERIES || PCI)
+	tristate "Open Firmware frame buffer device support"
+	depends on FB && PPC && (!PPC_PSERIES || PCI)
 	depends on !DRM_OFDRM
 	select APERTURE_HELPERS
 	select FB_CFB_FILLRECT
-- 
GitLab


From 8d8cf163c8d8c93bccf0c70a133309693af9bf61 Mon Sep 17 00:00:00 2001
From: Xu Panda <xu.panda@zte.com.cn>
Date: Wed, 28 Dec 2022 09:40:01 +0800
Subject: [PATCH 720/875] fbdev: omapfb: use strscpy() to instead of strncpy()

The implementation of strscpy() is more robust and safer.
That's now the recommended way to copy NUL-terminated strings.

Signed-off-by: Xu Panda <xu.panda@zte.com.cn>
Signed-off-by: Yang Yang <yang.yang29@zte.com>
Signed-off-by: Helge Deller <deller@gmx.de>
---
 drivers/video/fbdev/omap/omapfb_main.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/video/fbdev/omap/omapfb_main.c b/drivers/video/fbdev/omap/omapfb_main.c
index 17cda57656838..1f3df2055ff0d 100644
--- a/drivers/video/fbdev/omap/omapfb_main.c
+++ b/drivers/video/fbdev/omap/omapfb_main.c
@@ -1447,7 +1447,7 @@ static int fbinfo_init(struct omapfb_device *fbdev, struct fb_info *info)
 	info->fbops = &omapfb_ops;
 	info->flags = FBINFO_FLAG_DEFAULT;
 
-	strncpy(fix->id, MODULE_NAME, sizeof(fix->id));
+	strscpy(fix->id, MODULE_NAME, sizeof(fix->id));
 
 	info->pseudo_palette = fbdev->pseudo_palette;
 
@@ -1573,8 +1573,7 @@ static int omapfb_find_ctrl(struct omapfb_device *fbdev)
 
 	fbdev->ctrl = NULL;
 
-	strncpy(name, conf->lcd.ctrl_name, sizeof(name) - 1);
-	name[sizeof(name) - 1] = '\0';
+	strscpy(name, conf->lcd.ctrl_name, sizeof(name));
 
 	if (strcmp(name, "internal") == 0) {
 		fbdev->ctrl = fbdev->int_ctrl;
-- 
GitLab


From 6b90032c73405cd4da29ab914df11fd1be960b99 Mon Sep 17 00:00:00 2001
From: Xu Panda <xu.panda@zte.com.cn>
Date: Wed, 28 Dec 2022 09:44:11 +0800
Subject: [PATCH 721/875] fbdev: atyfb: use strscpy() to instead of strncpy()

The implementation of strscpy() is more robust and safer.
That's now the recommended way to copy NUL-terminated strings.

Signed-off-by: Xu Panda <xu.panda@zte.com.cn>
Signed-off-by: Yang Yang <yang.yang29@zte.com>
Signed-off-by: Helge Deller <deller@gmx.de>
---
 drivers/video/fbdev/aty/atyfb_base.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/video/fbdev/aty/atyfb_base.c b/drivers/video/fbdev/aty/atyfb_base.c
index 0ccf5d401ecbc..d59215a4992e0 100644
--- a/drivers/video/fbdev/aty/atyfb_base.c
+++ b/drivers/video/fbdev/aty/atyfb_base.c
@@ -3192,8 +3192,7 @@ static void aty_init_lcd(struct atyfb_par *par, u32 bios_base)
 		 * which we print to the screen.
 		 */
 		id = *(u8 *)par->lcd_table;
-		strncpy(model, (char *)par->lcd_table+1, 24);
-		model[23] = 0;
+		strscpy(model, (char *)par->lcd_table+1, sizeof(model));
 
 		width = par->lcd_width = *(u16 *)(par->lcd_table+25);
 		height = par->lcd_height = *(u16 *)(par->lcd_table+27);
-- 
GitLab


From 0e50d999903c009b6a9cd2277c82d6798d982e31 Mon Sep 17 00:00:00 2001
From: David Howells <dhowells@redhat.com>
Date: Sat, 24 Dec 2022 14:49:00 +0000
Subject: [PATCH 722/875] rxrpc: Fix a couple of potential use-after-frees

At the end of rxrpc_recvmsg(), if a call is found, the call is put and then
a trace line is emitted referencing that call in a couple of places - but
the call may have been deallocated by the time those traces happen.

Fix this by stashing the call debug_id in a variable and passing that to
the tracepoint rather than the call pointer.

Fixes: 849979051cbc ("rxrpc: Add a tracepoint to follow what recvmsg does")
Signed-off-by: David Howells <dhowells@redhat.com>
cc: Marc Dionne <marc.dionne@auristor.com>
cc: linux-afs@lists.infradead.org
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 include/trace/events/rxrpc.h |  6 +++---
 net/rxrpc/recvmsg.c          | 14 ++++++++------
 2 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/include/trace/events/rxrpc.h b/include/trace/events/rxrpc.h
index c6cfed00d0c6c..5f9dd73895364 100644
--- a/include/trace/events/rxrpc.h
+++ b/include/trace/events/rxrpc.h
@@ -1062,10 +1062,10 @@ TRACE_EVENT(rxrpc_receive,
 	    );
 
 TRACE_EVENT(rxrpc_recvmsg,
-	    TP_PROTO(struct rxrpc_call *call, enum rxrpc_recvmsg_trace why,
+	    TP_PROTO(unsigned int call_debug_id, enum rxrpc_recvmsg_trace why,
 		     int ret),
 
-	    TP_ARGS(call, why, ret),
+	    TP_ARGS(call_debug_id, why, ret),
 
 	    TP_STRUCT__entry(
 		    __field(unsigned int,		call		)
@@ -1074,7 +1074,7 @@ TRACE_EVENT(rxrpc_recvmsg,
 			     ),
 
 	    TP_fast_assign(
-		    __entry->call = call ? call->debug_id : 0;
+		    __entry->call = call_debug_id;
 		    __entry->why = why;
 		    __entry->ret = ret;
 			   ),
diff --git a/net/rxrpc/recvmsg.c b/net/rxrpc/recvmsg.c
index 36b25d003cf00..6ebd6440a2b7c 100644
--- a/net/rxrpc/recvmsg.c
+++ b/net/rxrpc/recvmsg.c
@@ -388,13 +388,14 @@ int rxrpc_recvmsg(struct socket *sock, struct msghdr *msg, size_t len,
 	struct rxrpc_call *call;
 	struct rxrpc_sock *rx = rxrpc_sk(sock->sk);
 	struct list_head *l;
+	unsigned int call_debug_id = 0;
 	size_t copied = 0;
 	long timeo;
 	int ret;
 
 	DEFINE_WAIT(wait);
 
-	trace_rxrpc_recvmsg(NULL, rxrpc_recvmsg_enter, 0);
+	trace_rxrpc_recvmsg(0, rxrpc_recvmsg_enter, 0);
 
 	if (flags & (MSG_OOB | MSG_TRUNC))
 		return -EOPNOTSUPP;
@@ -431,7 +432,7 @@ try_again:
 		if (list_empty(&rx->recvmsg_q)) {
 			if (signal_pending(current))
 				goto wait_interrupted;
-			trace_rxrpc_recvmsg(NULL, rxrpc_recvmsg_wait, 0);
+			trace_rxrpc_recvmsg(0, rxrpc_recvmsg_wait, 0);
 			timeo = schedule_timeout(timeo);
 		}
 		finish_wait(sk_sleep(&rx->sk), &wait);
@@ -450,7 +451,8 @@ try_again:
 		rxrpc_get_call(call, rxrpc_call_get_recvmsg);
 	write_unlock(&rx->recvmsg_lock);
 
-	trace_rxrpc_recvmsg(call, rxrpc_recvmsg_dequeue, 0);
+	call_debug_id = call->debug_id;
+	trace_rxrpc_recvmsg(call_debug_id, rxrpc_recvmsg_dequeue, 0);
 
 	/* We're going to drop the socket lock, so we need to lock the call
 	 * against interference by sendmsg.
@@ -531,7 +533,7 @@ try_again:
 error_unlock_call:
 	mutex_unlock(&call->user_mutex);
 	rxrpc_put_call(call, rxrpc_call_put_recvmsg);
-	trace_rxrpc_recvmsg(call, rxrpc_recvmsg_return, ret);
+	trace_rxrpc_recvmsg(call_debug_id, rxrpc_recvmsg_return, ret);
 	return ret;
 
 error_requeue_call:
@@ -539,14 +541,14 @@ error_requeue_call:
 		write_lock(&rx->recvmsg_lock);
 		list_add(&call->recvmsg_link, &rx->recvmsg_q);
 		write_unlock(&rx->recvmsg_lock);
-		trace_rxrpc_recvmsg(call, rxrpc_recvmsg_requeue, 0);
+		trace_rxrpc_recvmsg(call_debug_id, rxrpc_recvmsg_requeue, 0);
 	} else {
 		rxrpc_put_call(call, rxrpc_call_put_recvmsg);
 	}
 error_no_call:
 	release_sock(&rx->sk);
 error_trace:
-	trace_rxrpc_recvmsg(call, rxrpc_recvmsg_return, ret);
+	trace_rxrpc_recvmsg(call_debug_id, rxrpc_recvmsg_return, ret);
 	return ret;
 
 wait_interrupted:
-- 
GitLab


From f4ef681115f822daf7f36f8b1892d9f1e1a26fbf Mon Sep 17 00:00:00 2001
From: Jakub Kicinski <kuba@kernel.org>
Date: Thu, 22 Dec 2022 11:22:47 -0800
Subject: [PATCH 723/875] docs: netdev: reshuffle sections in prep for
 de-FAQization

Subsequent changes will reformat the doc away from FAQ.
To make that more readable perform the pure section moves now.

Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 Documentation/process/maintainer-netdev.rst | 186 ++++++++++----------
 1 file changed, 93 insertions(+), 93 deletions(-)

diff --git a/Documentation/process/maintainer-netdev.rst b/Documentation/process/maintainer-netdev.rst
index 1fa5ab8754d35..8f22f8a3dcd10 100644
--- a/Documentation/process/maintainer-netdev.rst
+++ b/Documentation/process/maintainer-netdev.rst
@@ -44,17 +44,6 @@ for the future release.  You can find the trees here:
 - https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git
 - https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git
 
-How do I indicate which tree (net vs. net-next) my patch should be in?
-----------------------------------------------------------------------
-To help maintainers and CI bots you should explicitly mark which tree
-your patch is targeting. Assuming that you use git, use the prefix
-flag::
-
-  git format-patch --subject-prefix='PATCH net-next' start..finish
-
-Use ``net`` instead of ``net-next`` (always lower case) in the above for
-bug-fix ``net`` content.
-
 How often do changes from these trees make it to the mainline Linus tree?
 -------------------------------------------------------------------------
 To understand this, you need to know a bit of background information on
@@ -127,15 +116,6 @@ patch. Patches are indexed by the ``Message-ID`` header of the emails
 which carried them so if you have trouble finding your patch append
 the value of ``Message-ID`` to the URL above.
 
-How long before my patch is accepted?
--------------------------------------
-Generally speaking, the patches get triaged quickly (in less than
-48h). But be patient, if your patch is active in patchwork (i.e. it's
-listed on the project's patch list) the chances it was missed are close to zero.
-Asking the maintainer for status updates on your
-patch is a good way to ensure your patch is ignored or pushed to the
-bottom of the priority list.
-
 Should I directly update patchwork state of my own patches?
 -----------------------------------------------------------
 It may be tempting to help the maintainers and update the state of your
@@ -145,19 +125,14 @@ it to the maintainer to figure out what is the most recent and current
 version that should be applied. If there is any doubt, the maintainer
 will reply and ask what should be done.
 
-How do I divide my work into patches?
+How long before my patch is accepted?
 -------------------------------------
-
-Put yourself in the shoes of the reviewer. Each patch is read separately
-and therefore should constitute a comprehensible step towards your stated
-goal.
-
-Avoid sending series longer than 15 patches. Larger series takes longer
-to review as reviewers will defer looking at it until they find a large
-chunk of time. A small series can be reviewed in a short time, so Maintainers
-just do it. As a result, a sequence of smaller series gets merged quicker and
-with better review coverage. Re-posting large series also increases the mailing
-list traffic.
+Generally speaking, the patches get triaged quickly (in less than
+48h). But be patient, if your patch is active in patchwork (i.e. it's
+listed on the project's patch list) the chances it was missed are close to zero.
+Asking the maintainer for status updates on your
+patch is a good way to ensure your patch is ignored or pushed to the
+bottom of the priority list.
 
 I made changes to only a few patches in a patch series should I resend only those changed?
 ------------------------------------------------------------------------------------------
@@ -165,17 +140,6 @@ No, please resend the entire patch series and make sure you do number your
 patches such that it is clear this is the latest and greatest set of patches
 that can be applied.
 
-I have received review feedback, when should I post a revised version of the patches?
--------------------------------------------------------------------------------------
-Allow at least 24 hours to pass between postings. This will ensure reviewers
-from all geographical locations have a chance to chime in. Do not wait
-too long (weeks) between postings either as it will make it harder for reviewers
-to recall all the context.
-
-Make sure you address all the feedback in your new posting. Do not post a new
-version of the code if the discussion about the previous version is still
-ongoing, unless directly instructed by a reviewer.
-
 I submitted multiple versions of a patch series and it looks like a version other than the last one has been accepted, what should I do?
 ----------------------------------------------------------------------------------------------------------------------------------------
 There is no revert possible, once it is pushed out, it stays like that.
@@ -191,6 +155,82 @@ the case today. Please follow the standard stable rules in
 :ref:`Documentation/process/stable-kernel-rules.rst <stable_kernel_rules>`,
 and make sure you include appropriate Fixes tags!
 
+I found a bug that might have possible security implications or similar. Should I mail the main netdev maintainer off-list?
+---------------------------------------------------------------------------------------------------------------------------
+No. The current netdev maintainer has consistently requested that
+people use the mailing lists and not reach out directly.  If you aren't
+OK with that, then perhaps consider mailing security@kernel.org or
+reading about http://oss-security.openwall.org/wiki/mailing-lists/distros
+as possible alternative mechanisms.
+
+How do I post corresponding changes to user space components?
+-------------------------------------------------------------
+User space code exercising kernel features should be posted
+alongside kernel patches. This gives reviewers a chance to see
+how any new interface is used and how well it works.
+
+When user space tools reside in the kernel repo itself all changes
+should generally come as one series. If series becomes too large
+or the user space project is not reviewed on netdev include a link
+to a public repo where user space patches can be seen.
+
+In case user space tooling lives in a separate repository but is
+reviewed on netdev  (e.g. patches to ``iproute2`` tools) kernel and
+user space patches should form separate series (threads) when posted
+to the mailing list, e.g.::
+
+  [PATCH net-next 0/3] net: some feature cover letter
+   └─ [PATCH net-next 1/3] net: some feature prep
+   └─ [PATCH net-next 2/3] net: some feature do it
+   └─ [PATCH net-next 3/3] selftest: net: some feature
+
+  [PATCH iproute2-next] ip: add support for some feature
+
+Posting as one thread is discouraged because it confuses patchwork
+(as of patchwork 2.2.2).
+
+Any other tips to help ensure my net/net-next patch gets OK'd?
+--------------------------------------------------------------
+Attention to detail.  Re-read your own work as if you were the
+reviewer.  You can start with using ``checkpatch.pl``, perhaps even with
+the ``--strict`` flag.  But do not be mindlessly robotic in doing so.
+If your change is a bug fix, make sure your commit log indicates the
+end-user visible symptom, the underlying reason as to why it happens,
+and then if necessary, explain why the fix proposed is the best way to
+get things done.  Don't mangle whitespace, and as is common, don't
+mis-indent function arguments that span multiple lines.  If it is your
+first patch, mail it to yourself so you can test apply it to an
+unpatched tree to confirm infrastructure didn't mangle it.
+
+Finally, go back and read
+:ref:`Documentation/process/submitting-patches.rst <submittingpatches>`
+to be sure you are not repeating some common mistake documented there.
+
+How do I indicate which tree (net vs. net-next) my patch should be in?
+----------------------------------------------------------------------
+To help maintainers and CI bots you should explicitly mark which tree
+your patch is targeting. Assuming that you use git, use the prefix
+flag::
+
+  git format-patch --subject-prefix='PATCH net-next' start..finish
+
+Use ``net`` instead of ``net-next`` (always lower case) in the above for
+bug-fix ``net`` content.
+
+How do I divide my work into patches?
+-------------------------------------
+
+Put yourself in the shoes of the reviewer. Each patch is read separately
+and therefore should constitute a comprehensible step towards your stated
+goal.
+
+Avoid sending series longer than 15 patches. Larger series takes longer
+to review as reviewers will defer looking at it until they find a large
+chunk of time. A small series can be reviewed in a short time, so Maintainers
+just do it. As a result, a sequence of smaller series gets merged quicker and
+with better review coverage. Re-posting large series also increases the mailing
+list traffic.
+
 Is the comment style convention different for the networking content?
 ---------------------------------------------------------------------
 Yes, in a largely trivial way.  Instead of this::
@@ -224,13 +264,16 @@ I am working in existing code which uses non-standard formatting. Which formatti
 Make your code follow the most recent guidelines, so that eventually all code
 in the domain of netdev is in the preferred format.
 
-I found a bug that might have possible security implications or similar. Should I mail the main netdev maintainer off-list?
----------------------------------------------------------------------------------------------------------------------------
-No. The current netdev maintainer has consistently requested that
-people use the mailing lists and not reach out directly.  If you aren't
-OK with that, then perhaps consider mailing security@kernel.org or
-reading about http://oss-security.openwall.org/wiki/mailing-lists/distros
-as possible alternative mechanisms.
+I have received review feedback, when should I post a revised version of the patches?
+-------------------------------------------------------------------------------------
+Allow at least 24 hours to pass between postings. This will ensure reviewers
+from all geographical locations have a chance to chime in. Do not wait
+too long (weeks) between postings either as it will make it harder for reviewers
+to recall all the context.
+
+Make sure you address all the feedback in your new posting. Do not post a new
+version of the code if the discussion about the previous version is still
+ongoing, unless directly instructed by a reviewer.
 
 What level of testing is expected before I submit my change?
 ------------------------------------------------------------
@@ -244,32 +287,6 @@ and the patch series contains a set of kernel selftest for
 You are expected to test your changes on top of the relevant networking
 tree (``net`` or ``net-next``) and not e.g. a stable tree or ``linux-next``.
 
-How do I post corresponding changes to user space components?
--------------------------------------------------------------
-User space code exercising kernel features should be posted
-alongside kernel patches. This gives reviewers a chance to see
-how any new interface is used and how well it works.
-
-When user space tools reside in the kernel repo itself all changes
-should generally come as one series. If series becomes too large
-or the user space project is not reviewed on netdev include a link
-to a public repo where user space patches can be seen.
-
-In case user space tooling lives in a separate repository but is
-reviewed on netdev  (e.g. patches to ``iproute2`` tools) kernel and
-user space patches should form separate series (threads) when posted
-to the mailing list, e.g.::
-
-  [PATCH net-next 0/3] net: some feature cover letter
-   └─ [PATCH net-next 1/3] net: some feature prep
-   └─ [PATCH net-next 2/3] net: some feature do it
-   └─ [PATCH net-next 3/3] selftest: net: some feature
-
-  [PATCH iproute2-next] ip: add support for some feature
-
-Posting as one thread is discouraged because it confuses patchwork
-(as of patchwork 2.2.2).
-
 Can I reproduce the checks from patchwork on my local machine?
 --------------------------------------------------------------
 
@@ -303,23 +320,6 @@ it has a real, in-tree user. Mock-ups and tests based on ``netdevsim`` are
 strongly encouraged when adding new APIs, but ``netdevsim`` in itself
 is **not** considered a use case/user.
 
-Any other tips to help ensure my net/net-next patch gets OK'd?
---------------------------------------------------------------
-Attention to detail.  Re-read your own work as if you were the
-reviewer.  You can start with using ``checkpatch.pl``, perhaps even with
-the ``--strict`` flag.  But do not be mindlessly robotic in doing so.
-If your change is a bug fix, make sure your commit log indicates the
-end-user visible symptom, the underlying reason as to why it happens,
-and then if necessary, explain why the fix proposed is the best way to
-get things done.  Don't mangle whitespace, and as is common, don't
-mis-indent function arguments that span multiple lines.  If it is your
-first patch, mail it to yourself so you can test apply it to an
-unpatched tree to confirm infrastructure didn't mangle it.
-
-Finally, go back and read
-:ref:`Documentation/process/submitting-patches.rst <submittingpatches>`
-to be sure you are not repeating some common mistake documented there.
-
 My company uses peer feedback in employee performance reviews. Can I ask netdev maintainers for feedback?
 ---------------------------------------------------------------------------------------------------------
 
-- 
GitLab


From ff249be5cca9f982e58936847ba6c30104abbcad Mon Sep 17 00:00:00 2001
From: Jakub Kicinski <kuba@kernel.org>
Date: Thu, 22 Dec 2022 11:22:48 -0800
Subject: [PATCH 724/875] docs: netdev: convert to a non-FAQ document

The netdev-FAQ document has grown over the years to the point
where finding information in it is somewhat challenging.
The length of the questions prevents readers from locating
content that's relevant at a glance.

Convert to a more standard documentation format with sections
and sub-sections rather than questions and answers.

The content edits are limited to what's necessary to change
the format, and very minor clarifications.

Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 Documentation/process/maintainer-netdev.rst | 221 +++++++++++---------
 1 file changed, 125 insertions(+), 96 deletions(-)

diff --git a/Documentation/process/maintainer-netdev.rst b/Documentation/process/maintainer-netdev.rst
index 8f22f8a3dcd10..4a75686d35ab4 100644
--- a/Documentation/process/maintainer-netdev.rst
+++ b/Documentation/process/maintainer-netdev.rst
@@ -2,9 +2,9 @@
 
 .. _netdev-FAQ:
 
-==========
-netdev FAQ
-==========
+=============================
+Networking subsystem (netdev)
+=============================
 
 tl;dr
 -----
@@ -15,14 +15,15 @@ tl;dr
  - don't repost your patches within one 24h period
  - reverse xmas tree
 
-What is netdev?
----------------
-It is a mailing list for all network-related Linux stuff.  This
+netdev
+------
+
+netdev is a mailing list for all network-related Linux stuff.  This
 includes anything found under net/ (i.e. core code like IPv6) and
 drivers/net (i.e. hardware specific drivers) in the Linux source tree.
 
 Note that some subsystems (e.g. wireless drivers) which have a high
-volume of traffic have their own specific mailing lists.
+volume of traffic have their own specific mailing lists and trees.
 
 The netdev list is managed (like many other Linux mailing lists) through
 VGER (http://vger.kernel.org/) with archives available at
@@ -32,21 +33,10 @@ Aside from subsystems like those mentioned above, all network-related
 Linux development (i.e. RFC, review, comments, etc.) takes place on
 netdev.
 
-How do the changes posted to netdev make their way into Linux?
---------------------------------------------------------------
-There are always two trees (git repositories) in play.  Both are
-driven by David Miller, the main network maintainer.  There is the
-``net`` tree, and the ``net-next`` tree.  As you can probably guess from
-the names, the ``net`` tree is for fixes to existing code already in the
-mainline tree from Linus, and ``net-next`` is where the new code goes
-for the future release.  You can find the trees here:
-
-- https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git
-- https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git
+Development cycle
+-----------------
 
-How often do changes from these trees make it to the mainline Linus tree?
--------------------------------------------------------------------------
-To understand this, you need to know a bit of background information on
+Here is a bit of background information on
 the cadence of Linux development.  Each new release starts off with a
 two week "merge window" where the main maintainers feed their new stuff
 to Linus for merging into the mainline tree.  After the two weeks, the
@@ -58,9 +48,33 @@ rc2 is released.  This repeats on a roughly weekly basis until rc7
 state of churn), and a week after the last vX.Y-rcN was done, the
 official vX.Y is released.
 
-Relating that to netdev: At the beginning of the 2-week merge window,
-the ``net-next`` tree will be closed - no new changes/features.  The
-accumulated new content of the past ~10 weeks will be passed onto
+To find out where we are now in the cycle - load the mainline (Linus)
+page here:
+
+  https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
+
+and note the top of the "tags" section.  If it is rc1, it is early in
+the dev cycle.  If it was tagged rc7 a week ago, then a release is
+probably imminent. If the most recent tag is a final release tag
+(without an ``-rcN`` suffix) - we are most likely in a merge window
+and ``net-next`` is closed.
+
+git trees and patch flow
+------------------------
+
+There are two networking trees (git repositories) in play.  Both are
+driven by David Miller, the main network maintainer.  There is the
+``net`` tree, and the ``net-next`` tree.  As you can probably guess from
+the names, the ``net`` tree is for fixes to existing code already in the
+mainline tree from Linus, and ``net-next`` is where the new code goes
+for the future release.  You can find the trees here:
+
+- https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git
+- https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git
+
+Relating that to kernel development: At the beginning of the 2-week
+merge window, the ``net-next`` tree will be closed - no new changes/features.
+The accumulated new content of the past ~10 weeks will be passed onto
 mainline/Linus via a pull request for vX.Y -- at the same time, the
 ``net`` tree will start accumulating fixes for this pulled content
 relating to vX.Y
@@ -92,22 +106,14 @@ focus for ``net`` is on stabilization and bug fixes.
 
 Finally, the vX.Y gets released, and the whole cycle starts over.
 
-So where are we now in this cycle?
-----------------------------------
+netdev patch review
+-------------------
 
-Load the mainline (Linus) page here:
+Patch status
+~~~~~~~~~~~~
 
-  https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
-
-and note the top of the "tags" section.  If it is rc1, it is early in
-the dev cycle.  If it was tagged rc7 a week ago, then a release is
-probably imminent. If the most recent tag is a final release tag
-(without an ``-rcN`` suffix) - we are most likely in a merge window
-and ``net-next`` is closed.
-
-How can I tell the status of a patch I've sent?
------------------------------------------------
-Start by looking at the main patchworks queue for netdev:
+Status of a patch can be checked by looking at the main patchwork
+queue for netdev:
 
   https://patchwork.kernel.org/project/netdevbpf/list/
 
@@ -116,17 +122,20 @@ patch. Patches are indexed by the ``Message-ID`` header of the emails
 which carried them so if you have trouble finding your patch append
 the value of ``Message-ID`` to the URL above.
 
-Should I directly update patchwork state of my own patches?
------------------------------------------------------------
+Updating patch status
+~~~~~~~~~~~~~~~~~~~~~
+
 It may be tempting to help the maintainers and update the state of your
-own patches when you post a new version or spot a bug. Please do not do that.
+own patches when you post a new version or spot a bug. Please **do not**
+do that.
 Interfering with the patch status on patchwork will only cause confusion. Leave
 it to the maintainer to figure out what is the most recent and current
 version that should be applied. If there is any doubt, the maintainer
 will reply and ask what should be done.
 
-How long before my patch is accepted?
--------------------------------------
+Review timelines
+~~~~~~~~~~~~~~~~
+
 Generally speaking, the patches get triaged quickly (in less than
 48h). But be patient, if your patch is active in patchwork (i.e. it's
 listed on the project's patch list) the chances it was missed are close to zero.
@@ -134,37 +143,47 @@ Asking the maintainer for status updates on your
 patch is a good way to ensure your patch is ignored or pushed to the
 bottom of the priority list.
 
-I made changes to only a few patches in a patch series should I resend only those changed?
-------------------------------------------------------------------------------------------
-No, please resend the entire patch series and make sure you do number your
+Partial resends
+~~~~~~~~~~~~~~~
+
+Please always resend the entire patch series and make sure you do number your
 patches such that it is clear this is the latest and greatest set of patches
-that can be applied.
+that can be applied. Do not try to resend just the patches which changed.
+
+Handling misapplied patches
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-I submitted multiple versions of a patch series and it looks like a version other than the last one has been accepted, what should I do?
-----------------------------------------------------------------------------------------------------------------------------------------
+Occasionally a patch series gets applied before receiving critical feedback,
+or the wrong version of a series gets applied.
 There is no revert possible, once it is pushed out, it stays like that.
 Please send incremental versions on top of what has been merged in order to fix
 the patches the way they would look like if your latest patch series was to be
 merged.
 
-Are there special rules regarding stable submissions on netdev?
----------------------------------------------------------------
+Stable tree
+~~~~~~~~~~~
+
 While it used to be the case that netdev submissions were not supposed
 to carry explicit ``CC: stable@vger.kernel.org`` tags that is no longer
 the case today. Please follow the standard stable rules in
 :ref:`Documentation/process/stable-kernel-rules.rst <stable_kernel_rules>`,
 and make sure you include appropriate Fixes tags!
 
-I found a bug that might have possible security implications or similar. Should I mail the main netdev maintainer off-list?
----------------------------------------------------------------------------------------------------------------------------
-No. The current netdev maintainer has consistently requested that
+Security fixes
+~~~~~~~~~~~~~~
+
+Do not email netdev maintainers directly if you think you discovered
+a bug that might have possible security implications.
+The current netdev maintainer has consistently requested that
 people use the mailing lists and not reach out directly.  If you aren't
 OK with that, then perhaps consider mailing security@kernel.org or
 reading about http://oss-security.openwall.org/wiki/mailing-lists/distros
 as possible alternative mechanisms.
 
-How do I post corresponding changes to user space components?
--------------------------------------------------------------
+
+Co-posting changes to user space components
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
 User space code exercising kernel features should be posted
 alongside kernel patches. This gives reviewers a chance to see
 how any new interface is used and how well it works.
@@ -189,9 +208,10 @@ to the mailing list, e.g.::
 Posting as one thread is discouraged because it confuses patchwork
 (as of patchwork 2.2.2).
 
-Any other tips to help ensure my net/net-next patch gets OK'd?
---------------------------------------------------------------
-Attention to detail.  Re-read your own work as if you were the
+Preparing changes
+-----------------
+
+Attention to detail is important.  Re-read your own work as if you were the
 reviewer.  You can start with using ``checkpatch.pl``, perhaps even with
 the ``--strict`` flag.  But do not be mindlessly robotic in doing so.
 If your change is a bug fix, make sure your commit log indicates the
@@ -206,8 +226,9 @@ Finally, go back and read
 :ref:`Documentation/process/submitting-patches.rst <submittingpatches>`
 to be sure you are not repeating some common mistake documented there.
 
-How do I indicate which tree (net vs. net-next) my patch should be in?
-----------------------------------------------------------------------
+Indicating target tree
+~~~~~~~~~~~~~~~~~~~~~~
+
 To help maintainers and CI bots you should explicitly mark which tree
 your patch is targeting. Assuming that you use git, use the prefix
 flag::
@@ -217,8 +238,8 @@ flag::
 Use ``net`` instead of ``net-next`` (always lower case) in the above for
 bug-fix ``net`` content.
 
-How do I divide my work into patches?
--------------------------------------
+Dividing work into patches
+~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 Put yourself in the shoes of the reviewer. Each patch is read separately
 and therefore should constitute a comprehensible step towards your stated
@@ -231,9 +252,11 @@ just do it. As a result, a sequence of smaller series gets merged quicker and
 with better review coverage. Re-posting large series also increases the mailing
 list traffic.
 
-Is the comment style convention different for the networking content?
----------------------------------------------------------------------
-Yes, in a largely trivial way.  Instead of this::
+Multi-line comments
+~~~~~~~~~~~~~~~~~~~
+
+Comment style convention is slightly different for networking and most of
+the tree.  Instead of this::
 
   /*
    * foobar blah blah blah
@@ -246,8 +269,8 @@ it is requested that you make it look like this::
    * another line of text
    */
 
-What is "reverse xmas tree"?
-----------------------------
+Local variable ordering ("reverse xmas tree", "RCS")
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 Netdev has a convention for ordering local variables in functions.
 Order the variable declaration lines longest to shortest, e.g.::
@@ -259,13 +282,16 @@ Order the variable declaration lines longest to shortest, e.g.::
 If there are dependencies between the variables preventing the ordering
 move the initialization out of line.
 
-I am working in existing code which uses non-standard formatting. Which formatting should I use?
-------------------------------------------------------------------------------------------------
-Make your code follow the most recent guidelines, so that eventually all code
+Format precedence
+~~~~~~~~~~~~~~~~~
+
+When working in existing code which uses nonstandard formatting make
+your code follow the most recent guidelines, so that eventually all code
 in the domain of netdev is in the preferred format.
 
-I have received review feedback, when should I post a revised version of the patches?
--------------------------------------------------------------------------------------
+Resending after review
+~~~~~~~~~~~~~~~~~~~~~~
+
 Allow at least 24 hours to pass between postings. This will ensure reviewers
 from all geographical locations have a chance to chime in. Do not wait
 too long (weeks) between postings either as it will make it harder for reviewers
@@ -275,8 +301,12 @@ Make sure you address all the feedback in your new posting. Do not post a new
 version of the code if the discussion about the previous version is still
 ongoing, unless directly instructed by a reviewer.
 
-What level of testing is expected before I submit my change?
-------------------------------------------------------------
+Testing
+-------
+
+Expected level of testing
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
 At the very minimum your changes must survive an ``allyesconfig`` and an
 ``allmodconfig`` build with ``W=1`` set without new warnings or failures.
 
@@ -287,43 +317,42 @@ and the patch series contains a set of kernel selftest for
 You are expected to test your changes on top of the relevant networking
 tree (``net`` or ``net-next``) and not e.g. a stable tree or ``linux-next``.
 
-Can I reproduce the checks from patchwork on my local machine?
---------------------------------------------------------------
+patchwork checks
+~~~~~~~~~~~~~~~~
 
 Checks in patchwork are mostly simple wrappers around existing kernel
 scripts, the sources are available at:
 
 https://github.com/kuba-moo/nipa/tree/master/tests
 
-Running all the builds and checks locally is a pain, can I post my patches and have the patchwork bot validate them?
---------------------------------------------------------------------------------------------------------------------
-
-No, you must ensure that your patches are ready by testing them locally
+**Do not** post your patches just to run them through the checks.
+You must ensure that your patches are ready by testing them locally
 before posting to the mailing list. The patchwork build bot instance
 gets overloaded very easily and netdev@vger really doesn't need more
 traffic if we can help it.
 
-netdevsim is great, can I extend it for my out-of-tree tests?
--------------------------------------------------------------
+netdevsim
+~~~~~~~~~
 
-No, ``netdevsim`` is a test vehicle solely for upstream tests.
-(Please add your tests under ``tools/testing/selftests/``.)
+``netdevsim`` is a test driver which can be used to exercise driver
+configuration APIs without requiring capable hardware.
+Mock-ups and tests based on ``netdevsim`` are strongly encouraged when
+adding new APIs, but ``netdevsim`` in itself is **not** considered
+a use case/user. You must also implement the new APIs in a real driver.
 
-We also give no guarantees that ``netdevsim`` won't change in the future
+We give no guarantees that ``netdevsim`` won't change in the future
 in a way which would break what would normally be considered uAPI.
 
-Is netdevsim considered a "user" of an API?
--------------------------------------------
-
-Linux kernel has a long standing rule that no API should be added unless
-it has a real, in-tree user. Mock-ups and tests based on ``netdevsim`` are
-strongly encouraged when adding new APIs, but ``netdevsim`` in itself
-is **not** considered a use case/user.
+``netdevsim`` is reserved for use by upstream tests only, so any
+new ``netdevsim`` features must be accompanied by selftests under
+``tools/testing/selftests/``.
 
-My company uses peer feedback in employee performance reviews. Can I ask netdev maintainers for feedback?
----------------------------------------------------------------------------------------------------------
+Testimonials / feedback
+-----------------------
 
-Yes, especially if you spend significant amount of time reviewing code
+Some companies use peer feedback in employee performance reviews.
+Please feel free to request feedback from netdev maintainers,
+especially if you spend significant amount of time reviewing code
 and go out of your way to improve shared infrastructure.
 
 The feedback must be requested by you, the contributor, and will always
-- 
GitLab


From b9e05399d9273c8c066e73db1e6e85364003030c Mon Sep 17 00:00:00 2001
From: Si-Wei Liu <si-wei.liu@oracle.com>
Date: Mon, 10 Oct 2022 10:27:03 -0700
Subject: [PATCH 725/875] vdpa: merge functionally duplicated dev_features
 attributes

We can merge VDPA_ATTR_VDPA_DEV_SUPPORTED_FEATURES with
VDPA_ATTR_DEV_FEATURES which is functionally equivalent.
While at it, tweak the comment in header file to make
user provioned device features distinguished from those
supported by the parent mgmtdev device: the former of
which can be inherited as a whole from the latter, or
can be a subset of the latter if explicitly specified.

Signed-off-by: Si-Wei Liu <si-wei.liu@oracle.com>
Message-Id: <1665422823-18364-1-git-send-email-si-wei.liu@oracle.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
---
 drivers/vdpa/vdpa.c       | 2 +-
 include/uapi/linux/vdpa.h | 4 +---
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/vdpa/vdpa.c b/drivers/vdpa/vdpa.c
index febdc99b51a7b..41ed56362992b 100644
--- a/drivers/vdpa/vdpa.c
+++ b/drivers/vdpa/vdpa.c
@@ -855,7 +855,7 @@ static int vdpa_dev_net_config_fill(struct vdpa_device *vdev, struct sk_buff *ms
 
 	features_device = vdev->config->get_device_features(vdev);
 
-	if (nla_put_u64_64bit(msg, VDPA_ATTR_VDPA_DEV_SUPPORTED_FEATURES, features_device,
+	if (nla_put_u64_64bit(msg, VDPA_ATTR_DEV_FEATURES, features_device,
 			      VDPA_ATTR_PAD))
 		return -EMSGSIZE;
 
diff --git a/include/uapi/linux/vdpa.h b/include/uapi/linux/vdpa.h
index 9bd79235c875f..54b649ab0f22b 100644
--- a/include/uapi/linux/vdpa.h
+++ b/include/uapi/linux/vdpa.h
@@ -53,11 +53,9 @@ enum vdpa_attr {
 	VDPA_ATTR_DEV_VENDOR_ATTR_NAME,		/* string */
 	VDPA_ATTR_DEV_VENDOR_ATTR_VALUE,        /* u64 */
 
+	/* virtio features that are provisioned to the vDPA device */
 	VDPA_ATTR_DEV_FEATURES,                 /* u64 */
 
-	/* virtio features that are supported by the vDPA device */
-	VDPA_ATTR_VDPA_DEV_SUPPORTED_FEATURES,	/* u64 */
-
 	/* new attributes must be added above here */
 	VDPA_ATTR_MAX,
 };
-- 
GitLab


From c262f75cb6bb5a63828e72ce3b8fe808e5029479 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ricardo=20Ca=C3=B1uelo?= <ricardo.canuelo@collabora.com>
Date: Wed, 12 Oct 2022 08:29:49 +0200
Subject: [PATCH 726/875] tools/virtio: initialize spinlocks in vring_test.c
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The virtio_device vqs_list spinlocks must be initialized before use to
prevent functions that manipulate the device virtualqueues, such as
vring_new_virtqueue(), from blocking indefinitely.

Signed-off-by: Ricardo Cañuelo <ricardo.canuelo@collabora.com>
Message-Id: <20221012062949.1526176-1-ricardo.canuelo@collabora.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
---
 tools/virtio/vringh_test.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/tools/virtio/vringh_test.c b/tools/virtio/vringh_test.c
index fa87b58bd5fa5..98ff808d6f0c2 100644
--- a/tools/virtio/vringh_test.c
+++ b/tools/virtio/vringh_test.c
@@ -308,6 +308,7 @@ static int parallel_test(u64 features,
 
 		gvdev.vdev.features = features;
 		INIT_LIST_HEAD(&gvdev.vdev.vqs);
+		spin_lock_init(&gvdev.vdev.vqs_list_lock);
 		gvdev.to_host_fd = to_host[1];
 		gvdev.notifies = 0;
 
@@ -455,6 +456,7 @@ int main(int argc, char *argv[])
 	getrange = getrange_iov;
 	vdev.features = 0;
 	INIT_LIST_HEAD(&vdev.vqs);
+	spin_lock_init(&vdev.vqs_list_lock);
 
 	while (argv[1]) {
 		if (strcmp(argv[1], "--indirect") == 0)
-- 
GitLab


From 258896fcc786b4e7db238eba26f6dd080e0ff41e Mon Sep 17 00:00:00 2001
From: Dmitry Fomichev <dmitry.fomichev@wdc.com>
Date: Sat, 15 Oct 2022 23:41:26 -0400
Subject: [PATCH 727/875] virtio-blk: use a helper to handle request queuing
 errors

Define a new helper function, virtblk_fail_to_queue(), to
clean up the error handling code in virtio_queue_rq().

Signed-off-by: Dmitry Fomichev <dmitry.fomichev@wdc.com>
Message-Id: <20221016034127.330942-2-dmitry.fomichev@wdc.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 drivers/block/virtio_blk.c | 29 ++++++++++++++++-------------
 1 file changed, 16 insertions(+), 13 deletions(-)

diff --git a/drivers/block/virtio_blk.c b/drivers/block/virtio_blk.c
index 68bd2f7961b3f..271a9878fa8b3 100644
--- a/drivers/block/virtio_blk.c
+++ b/drivers/block/virtio_blk.c
@@ -315,6 +315,19 @@ static void virtio_commit_rqs(struct blk_mq_hw_ctx *hctx)
 		virtqueue_notify(vq->vq);
 }
 
+static blk_status_t virtblk_fail_to_queue(struct request *req, int rc)
+{
+	virtblk_cleanup_cmd(req);
+	switch (rc) {
+	case -ENOSPC:
+		return BLK_STS_DEV_RESOURCE;
+	case -ENOMEM:
+		return BLK_STS_RESOURCE;
+	default:
+		return BLK_STS_IOERR;
+	}
+}
+
 static blk_status_t virtblk_prep_rq(struct blk_mq_hw_ctx *hctx,
 					struct virtio_blk *vblk,
 					struct request *req,
@@ -327,10 +340,8 @@ static blk_status_t virtblk_prep_rq(struct blk_mq_hw_ctx *hctx,
 		return status;
 
 	vbr->sg_table.nents = virtblk_map_data(hctx, req, vbr);
-	if (unlikely(vbr->sg_table.nents < 0)) {
-		virtblk_cleanup_cmd(req);
-		return BLK_STS_RESOURCE;
-	}
+	if (unlikely(vbr->sg_table.nents < 0))
+		return virtblk_fail_to_queue(req, -ENOMEM);
 
 	blk_mq_start_request(req);
 
@@ -364,15 +375,7 @@ static blk_status_t virtio_queue_rq(struct blk_mq_hw_ctx *hctx,
 			blk_mq_stop_hw_queue(hctx);
 		spin_unlock_irqrestore(&vblk->vqs[qid].lock, flags);
 		virtblk_unmap_data(req, vbr);
-		virtblk_cleanup_cmd(req);
-		switch (err) {
-		case -ENOSPC:
-			return BLK_STS_DEV_RESOURCE;
-		case -ENOMEM:
-			return BLK_STS_RESOURCE;
-		default:
-			return BLK_STS_IOERR;
-		}
+		return virtblk_fail_to_queue(req, err);
 	}
 
 	if (bd->last && virtqueue_kick_prepare(vblk->vqs[qid].vq))
-- 
GitLab


From 8e6a8d7a3dd93e93645be061692cb4ee6702dff0 Mon Sep 17 00:00:00 2001
From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Date: Mon, 26 Dec 2022 16:13:27 +0900
Subject: [PATCH 728/875] net: ethernet: renesas: rswitch: Fix error path in
 renesas_eth_sw_probe()

If rswitch_init() returns non-zero and this driver is re-probed,
the following error happens:

    renesas_eth_sw e6880000.ethernet: Unbalanced pm_runtime_enable!

So, fix error path in renesas_eth_sw_probe().

Fixes: 3590918b5d07 ("net: ethernet: renesas: Add support for "Ethernet Switch"")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/renesas/rswitch.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/net/ethernet/renesas/rswitch.c b/drivers/net/ethernet/renesas/rswitch.c
index e42ceaa0099fd..473d86bdf97d6 100644
--- a/drivers/net/ethernet/renesas/rswitch.c
+++ b/drivers/net/ethernet/renesas/rswitch.c
@@ -1786,6 +1786,11 @@ static int renesas_eth_sw_probe(struct platform_device *pdev)
 	pm_runtime_get_sync(&pdev->dev);
 
 	ret = rswitch_init(priv);
+	if (ret < 0) {
+		pm_runtime_put(&pdev->dev);
+		pm_runtime_disable(&pdev->dev);
+		return ret;
+	}
 
 	device_set_wakeup_capable(&pdev->dev, 1);
 
-- 
GitLab


From bd2adfe3b3b863c883309bcc915f13c831ca88da Mon Sep 17 00:00:00 2001
From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Date: Mon, 26 Dec 2022 16:13:28 +0900
Subject: [PATCH 729/875] net: ethernet: renesas: rswitch: Fix getting mac
 address from device tree

To get mac address from device tree which is from each ethernet-port,
fix the first argument of of_get_ethdev_address().

Fixes: 3590918b5d07 ("net: ethernet: renesas: Add support for "Ethernet Switch"")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/renesas/rswitch.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/renesas/rswitch.c b/drivers/net/ethernet/renesas/rswitch.c
index 473d86bdf97d6..6441892636dba 100644
--- a/drivers/net/ethernet/renesas/rswitch.c
+++ b/drivers/net/ethernet/renesas/rswitch.c
@@ -1578,6 +1578,7 @@ static int rswitch_device_alloc(struct rswitch_private *priv, int index)
 {
 	struct platform_device *pdev = priv->pdev;
 	struct rswitch_device *rdev;
+	struct device_node *port;
 	struct net_device *ndev;
 	int err;
 
@@ -1606,7 +1607,9 @@ static int rswitch_device_alloc(struct rswitch_private *priv, int index)
 
 	netif_napi_add(ndev, &rdev->napi, rswitch_poll);
 
-	err = of_get_ethdev_address(pdev->dev.of_node, ndev);
+	port = rswitch_get_port_node(rdev);
+	err = of_get_ethdev_address(port, ndev);
+	of_node_put(port);
 	if (err) {
 		if (is_valid_ether_addr(rdev->etha->mac_addr))
 			eth_hw_addr_set(ndev, rdev->etha->mac_addr);
-- 
GitLab


From 0020ae2a4aa81becd182231bf48acd66c86c86dd Mon Sep 17 00:00:00 2001
From: Vikas Gupta <vikas.gupta@broadcom.com>
Date: Mon, 26 Dec 2022 22:19:36 -0500
Subject: [PATCH 730/875] bnxt_en: fix devlink port registration to netdev

We don't register a devlink port in case of a VF so
avoid setting the devlink pointer to netdev.
Also, SET_NETDEV_DEVLINK_PORT has to be moved
so that we determine whether the device is PF/VF first.

This fixes the NULL pointer dereference of devlink_port->devlink
when creating VFs:

BUG: kernel NULL pointer dereference, address: 0000000000000160
PGD 0
Oops: 0000 [#1] PREEMPT SMP NOPTI
CPU: 14 PID: 388 Comm: kworker/14:1 Kdump: loaded Not tainted 6.1.0-rc8 #5
Hardware name: Dell Inc. PowerEdge R750/06V45N, BIOS 1.3.8 08/31/2021
Workqueue: events work_for_cpu_fn
RIP: 0010:devlink_nl_port_handle_size+0xb/0x50
Code: 83 c4 10 5b 5d c3 cc cc cc cc b8 a6 ff ff ff eb de e8 c9 59 21 00 66 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 55 53 48 8b 47 20 <48> 8b a8 60 01 00 00 48 8b 45 60 48 8b 38 e8 92 90 1a 00 48 8b 7d
RSP: 0018:ff4fe5394846fcd8 EFLAGS: 00010286
RAX: 0000000000000000 RBX: 0000000000000794 RCX: 0000000000000000
RDX: ff1f129683a30a40 RSI: 0000000000000008 RDI: ff1f1296bb496188
RBP: 0000000000000334 R08: 0000000000000cc0 R09: 0000000000000000
R10: ff1f1296bb494298 R11: ffffffffffffffc0 R12: 0000000000000000
R13: 0000000000000000 R14: ff1f1296bb494000 R15: 0000000000000000
FS:  0000000000000000(0000) GS:ff1f129e5fa00000(0000) knlGS:0000000000000000
CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 0000000000000160 CR3: 000000131f610006 CR4: 0000000000771ee0
DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
PKRU: 55555554
Call Trace:
 <TASK>
 if_nlmsg_size+0x14a/0x220
 rtmsg_ifinfo_build_skb+0x3c/0x100
 rtmsg_ifinfo+0x9c/0xc0
 register_netdevice+0x59d/0x670
 register_netdev+0x1c/0x40
 bnxt_init_one+0x674/0xa60 [bnxt_en]
 local_pci_probe+0x42/0x80
 work_for_cpu_fn+0x13/0x20
 process_one_work+0x1e2/0x3b0
 ? rescuer_thread+0x390/0x390
 worker_thread+0x1c4/0x3a0
 ? rescuer_thread+0x390/0x390
 kthread+0xd6/0x100
 ? kthread_complete_and_exit+0x20/0x20

Fixes: ac73d4bf2cda ("net: make drivers to use SET_NETDEV_DEVLINK_PORT to set devlink_port")
Cc: Jiri Pirko <jiri@nvidia.com>
Signed-off-by: Vikas Gupta <vikas.gupta@broadcom.com>
Reviewed-by: Andy Gospodarek <andrew.gospodarek@broadcom.com>
Reviewed-by: Kalesh Anakkur Purayil <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Damodharam Ammepalli <damodharam.ammepalli@broadcom.com>
Signed-off-by: Michael Chan <michael.chan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/broadcom/bnxt/bnxt.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
index 4c7d07c684c49..93d32b333007f 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
@@ -13591,7 +13591,6 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 		return -ENOMEM;
 
 	bp = netdev_priv(dev);
-	SET_NETDEV_DEVLINK_PORT(dev, &bp->dl_port);
 	bp->board_idx = ent->driver_data;
 	bp->msg_enable = BNXT_DEF_MSG_ENABLE;
 	bnxt_set_max_func_irqs(bp, max_irqs);
@@ -13599,6 +13598,10 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 	if (bnxt_vf_pciid(bp->board_idx))
 		bp->flags |= BNXT_FLAG_VF;
 
+	/* No devlink port registration in case of a VF */
+	if (BNXT_PF(bp))
+		SET_NETDEV_DEVLINK_PORT(dev, &bp->dl_port);
+
 	if (pdev->msix_cap)
 		bp->flags |= BNXT_FLAG_MSIX_CAP;
 
-- 
GitLab


From bbfc17e50ba2ed18dfef46b1c433d50a58566bf1 Mon Sep 17 00:00:00 2001
From: Michael Chan <michael.chan@broadcom.com>
Date: Mon, 26 Dec 2022 22:19:37 -0500
Subject: [PATCH 731/875] bnxt_en: Simplify bnxt_xdp_buff_init()

bnxt_xdp_buff_init() does not modify the data_ptr or the len parameters,
so no need to pass in the addresses of these parameters.

Fixes: b231c3f3414c ("bnxt: refactor bnxt_rx_xdp to separate xdp_init_buff/xdp_prepare_buff")
Reviewed-by: Andy Gospodarek <andrew.gospodarek@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Pavan Chebbi <pavan.chebbi@broadcom.com>
Signed-off-by: Michael Chan <michael.chan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/broadcom/bnxt/bnxt.c     | 2 +-
 drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c | 6 +++---
 drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.h | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
index 93d32b333007f..b8639b7e6b2b3 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
@@ -1925,7 +1925,7 @@ static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 	dma_addr = rx_buf->mapping;
 
 	if (bnxt_xdp_attached(bp, rxr)) {
-		bnxt_xdp_buff_init(bp, rxr, cons, &data_ptr, &len, &xdp);
+		bnxt_xdp_buff_init(bp, rxr, cons, data_ptr, len, &xdp);
 		if (agg_bufs) {
 			u32 frag_len = bnxt_rx_agg_pages_xdp(bp, cpr, &xdp,
 							     cp_cons, agg_bufs,
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c b/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c
index c3065ec0a4798..1847f191577d1 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c
@@ -177,7 +177,7 @@ bool bnxt_xdp_attached(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
 }
 
 void bnxt_xdp_buff_init(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
-			u16 cons, u8 **data_ptr, unsigned int *len,
+			u16 cons, u8 *data_ptr, unsigned int len,
 			struct xdp_buff *xdp)
 {
 	struct bnxt_sw_rx_bd *rx_buf;
@@ -191,13 +191,13 @@ void bnxt_xdp_buff_init(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 	offset = bp->rx_offset;
 
 	mapping = rx_buf->mapping - bp->rx_dma_offset;
-	dma_sync_single_for_cpu(&pdev->dev, mapping + offset, *len, bp->rx_dir);
+	dma_sync_single_for_cpu(&pdev->dev, mapping + offset, len, bp->rx_dir);
 
 	if (bp->xdp_has_frags)
 		buflen = BNXT_PAGE_MODE_BUF_SIZE + offset;
 
 	xdp_init_buff(xdp, buflen, &rxr->xdp_rxq);
-	xdp_prepare_buff(xdp, *data_ptr - offset, offset, *len, false);
+	xdp_prepare_buff(xdp, data_ptr - offset, offset, len, false);
 }
 
 void bnxt_xdp_buff_frags_free(struct bnxt_rx_ring_info *rxr,
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.h b/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.h
index 505911ae095d3..2bbdb8e7c506b 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.h
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.h
@@ -27,7 +27,7 @@ int bnxt_xdp_xmit(struct net_device *dev, int num_frames,
 bool bnxt_xdp_attached(struct bnxt *bp, struct bnxt_rx_ring_info *rxr);
 
 void bnxt_xdp_buff_init(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
-			u16 cons, u8 **data_ptr, unsigned int *len,
+			u16 cons, u8 *data_ptr, unsigned int len,
 			struct xdp_buff *xdp);
 void bnxt_xdp_buff_frags_free(struct bnxt_rx_ring_info *rxr,
 			      struct xdp_buff *xdp);
-- 
GitLab


From 9b3e607871ea5ee90f10f5be3965fc07f2aa3ef7 Mon Sep 17 00:00:00 2001
From: Michael Chan <michael.chan@broadcom.com>
Date: Mon, 26 Dec 2022 22:19:38 -0500
Subject: [PATCH 732/875] bnxt_en: Fix XDP RX path

The XDP program can change the starting address of the RX data buffer and
this information needs to be passed back from bnxt_rx_xdp() to
bnxt_rx_pkt() for the XDP_PASS case so that the SKB can point correctly
to the modified buffer address.  Add back the data_ptr parameter to
bnxt_rx_xdp() to make this work.

Fixes: b231c3f3414c ("bnxt: refactor bnxt_rx_xdp to separate xdp_init_buff/xdp_prepare_buff")
Reviewed-by: Andy Gospodarek <andrew.gospodarek@broadcom.com>
Reviewed-by: Pavan Chebbi <pavan.chebbi@broadcom.com>
Signed-off-by: Michael Chan <michael.chan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/broadcom/bnxt/bnxt.c     | 2 +-
 drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c | 7 +++++--
 drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.h | 4 ++--
 3 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
index b8639b7e6b2b3..1acabfe26db18 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
@@ -1940,7 +1940,7 @@ static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 	}
 
 	if (xdp_active) {
-		if (bnxt_rx_xdp(bp, rxr, cons, xdp, data, &len, event)) {
+		if (bnxt_rx_xdp(bp, rxr, cons, xdp, data, &data_ptr, &len, event)) {
 			rc = 1;
 			goto next_rx;
 		}
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c b/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c
index 1847f191577d1..2ceeaa818c1c6 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c
@@ -222,7 +222,8 @@ void bnxt_xdp_buff_frags_free(struct bnxt_rx_ring_info *rxr,
  * false   - packet should be passed to the stack.
  */
 bool bnxt_rx_xdp(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, u16 cons,
-		 struct xdp_buff xdp, struct page *page, unsigned int *len, u8 *event)
+		 struct xdp_buff xdp, struct page *page, u8 **data_ptr,
+		 unsigned int *len, u8 *event)
 {
 	struct bpf_prog *xdp_prog = READ_ONCE(rxr->xdp_prog);
 	struct bnxt_tx_ring_info *txr;
@@ -255,8 +256,10 @@ bool bnxt_rx_xdp(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, u16 cons,
 		*event &= ~BNXT_RX_EVENT;
 
 	*len = xdp.data_end - xdp.data;
-	if (orig_data != xdp.data)
+	if (orig_data != xdp.data) {
 		offset = xdp.data - xdp.data_hard_start;
+		*data_ptr = xdp.data_hard_start + offset;
+	}
 
 	switch (act) {
 	case XDP_PASS:
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.h b/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.h
index 2bbdb8e7c506b..ea430d6961df3 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.h
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.h
@@ -18,8 +18,8 @@ struct bnxt_sw_tx_bd *bnxt_xmit_bd(struct bnxt *bp,
 				   struct xdp_buff *xdp);
 void bnxt_tx_int_xdp(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts);
 bool bnxt_rx_xdp(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, u16 cons,
-		 struct xdp_buff xdp, struct page *page, unsigned int *len,
-		 u8 *event);
+		 struct xdp_buff xdp, struct page *page, u8 **data_ptr,
+		 unsigned int *len, u8 *event);
 int bnxt_xdp(struct net_device *dev, struct netdev_bpf *xdp);
 int bnxt_xdp_xmit(struct net_device *dev, int num_frames,
 		  struct xdp_frame **frames, u32 flags);
-- 
GitLab


From 1abeacc1979fa4a756695f5030791d8f0fa934b9 Mon Sep 17 00:00:00 2001
From: Michael Chan <michael.chan@broadcom.com>
Date: Mon, 26 Dec 2022 22:19:39 -0500
Subject: [PATCH 733/875] bnxt_en: Fix first buffer size calculations for XDP
 multi-buffer

The size of the first buffer is always page size, and the useable
space is the page size minus the offset and the skb_shared_info size.
Make sure SKB and XDP buf sizes match so that the skb_shared_info
is at the same offset seen from the SKB and XDP_BUF.

build_skb() should be passed PAGE_SIZE.  xdp_init_buff() should
be passed PAGE_SIZE as well.  xdp_get_shared_info_from_buff() will
automatically deduct the skb_shared_info size if the XDP buffer
has frags.  There is no need to keep bp->xdp_has_frags.

Change BNXT_PAGE_MODE_BUF_SIZE to BNXT_MAX_PAGE_MODE_MTU_SBUF
since this constant is really the MTU with ethernet header size
subtracted.

Also fix the BNXT_MAX_PAGE_MODE_MTU macro with proper parentheses.

Fixes: 32861236190b ("bnxt: change receive ring space parameters")
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Andy Gospodarek <andrew.gospodarek@broadcom.com>
Signed-off-by: Michael Chan <michael.chan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/broadcom/bnxt/bnxt.c     |  9 +++++----
 drivers/net/ethernet/broadcom/bnxt/bnxt.h     | 15 +++++++++++----
 drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c |  7 +------
 3 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
index 1acabfe26db18..a21c6829e301e 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
@@ -991,8 +991,7 @@ static struct sk_buff *bnxt_rx_multi_page_skb(struct bnxt *bp,
 	dma_addr -= bp->rx_dma_offset;
 	dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
 			     DMA_ATTR_WEAK_ORDERING);
-	skb = build_skb(page_address(page), BNXT_PAGE_MODE_BUF_SIZE +
-					    bp->rx_dma_offset);
+	skb = build_skb(page_address(page), PAGE_SIZE);
 	if (!skb) {
 		__free_page(page);
 		return NULL;
@@ -3969,8 +3968,10 @@ void bnxt_set_ring_params(struct bnxt *bp)
 		bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
 
 		if (BNXT_RX_PAGE_MODE(bp)) {
-			rx_space = BNXT_PAGE_MODE_BUF_SIZE;
-			rx_size = BNXT_MAX_PAGE_MODE_MTU;
+			rx_space = PAGE_SIZE;
+			rx_size = PAGE_SIZE -
+				  ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8) -
+				  SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 		} else {
 			rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
 			rx_space = rx_size + NET_SKB_PAD +
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.h b/drivers/net/ethernet/broadcom/bnxt/bnxt.h
index 41c6dd0ae447e..5163ef4a49ea3 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt.h
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.h
@@ -591,12 +591,20 @@ struct nqe_cn {
 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
 
 #define BNXT_MAX_MTU		9500
-#define BNXT_PAGE_MODE_BUF_SIZE \
+
+/* First RX buffer page in XDP multi-buf mode
+ *
+ * +-------------------------------------------------------------------------+
+ * | XDP_PACKET_HEADROOM | bp->rx_buf_use_size              | skb_shared_info|
+ * | (bp->rx_dma_offset) |                                  |                |
+ * +-------------------------------------------------------------------------+
+ */
+#define BNXT_MAX_PAGE_MODE_MTU_SBUF \
 	((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN -	\
 	 XDP_PACKET_HEADROOM)
 #define BNXT_MAX_PAGE_MODE_MTU	\
-	BNXT_PAGE_MODE_BUF_SIZE - \
-	SKB_DATA_ALIGN((unsigned int)sizeof(struct skb_shared_info))
+	(BNXT_MAX_PAGE_MODE_MTU_SBUF - \
+	 SKB_DATA_ALIGN((unsigned int)sizeof(struct skb_shared_info)))
 
 #define BNXT_MIN_PKT_SIZE	52
 
@@ -2134,7 +2142,6 @@ struct bnxt {
 #define BNXT_DUMP_CRASH		1
 
 	struct bpf_prog		*xdp_prog;
-	u8			xdp_has_frags;
 
 	struct bnxt_ptp_cfg	*ptp_cfg;
 	u8			ptp_all_rx_tstamp;
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c b/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c
index 2ceeaa818c1c6..36d5202c0aeec 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c
@@ -193,9 +193,6 @@ void bnxt_xdp_buff_init(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 	mapping = rx_buf->mapping - bp->rx_dma_offset;
 	dma_sync_single_for_cpu(&pdev->dev, mapping + offset, len, bp->rx_dir);
 
-	if (bp->xdp_has_frags)
-		buflen = BNXT_PAGE_MODE_BUF_SIZE + offset;
-
 	xdp_init_buff(xdp, buflen, &rxr->xdp_rxq);
 	xdp_prepare_buff(xdp, data_ptr - offset, offset, len, false);
 }
@@ -404,10 +401,8 @@ static int bnxt_xdp_set(struct bnxt *bp, struct bpf_prog *prog)
 		netdev_warn(dev, "ethtool rx/tx channels must be combined to support XDP.\n");
 		return -EOPNOTSUPP;
 	}
-	if (prog) {
+	if (prog)
 		tx_xdp = bp->rx_nr_rings;
-		bp->xdp_has_frags = prog->aux->xdp_has_frags;
-	}
 
 	tc = netdev_get_num_tc(dev);
 	if (!tc)
-- 
GitLab


From a056ebcc30e2f78451d66f615d2f6bdada3e6438 Mon Sep 17 00:00:00 2001
From: Michael Chan <michael.chan@broadcom.com>
Date: Mon, 26 Dec 2022 22:19:40 -0500
Subject: [PATCH 734/875] bnxt_en: Fix HDS and jumbo thresholds for RX packets

The recent XDP multi-buffer feature has introduced regressions in the
setting of HDS and jumbo thresholds.  HDS was accidentally disabled in
the nornmal mode without XDP.  This patch restores jumbo HDS placement
when not in XDP mode.  In XDP multi-buffer mode, HDS should be disabled
and the jumbo threshold should be set to the usable page size in the
first page buffer.

Fixes: 32861236190b ("bnxt: change receive ring space parameters")
Reviewed-by: Mohammad Shuab Siddique <mohammad-shuab.siddique@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Andy Gospodarek <andrew.gospodarek@broadcom.com>
Signed-off-by: Michael Chan <michael.chan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/broadcom/bnxt/bnxt.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
index a21c6829e301e..16ce7a90610c5 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
@@ -5399,15 +5399,16 @@ static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
 	req->flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT);
 	req->enables = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID);
 
-	if (BNXT_RX_PAGE_MODE(bp) && !BNXT_RX_JUMBO_MODE(bp)) {
+	if (BNXT_RX_PAGE_MODE(bp)) {
+		req->jumbo_thresh = cpu_to_le16(bp->rx_buf_use_size);
+	} else {
 		req->flags |= cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
 					  VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
 		req->enables |=
 			cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
+		req->jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
+		req->hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
 	}
-	/* thresholds not implemented in firmware yet */
-	req->jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
-	req->hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
 	req->vnic_id = cpu_to_le32(vnic->fw_vnic_id);
 	return hwrm_req_send(bp, req);
 }
-- 
GitLab


From a6ce72c0fb6041f9871f880b2d02b294f7f49cb4 Mon Sep 17 00:00:00 2001
From: Eli Cohen <elic@nvidia.com>
Date: Mon, 14 Nov 2022 15:17:52 +0200
Subject: [PATCH 735/875] vdpa/mlx5: Fix rule forwarding VLAN to TIR

Set the VLAN id to the header values field instead of overwriting the
headers criteria field.

Before this fix, VLAN filtering would not really work and tagged packets
would be forwarded unfiltered to the TIR.

Fixes: baf2ad3f6a98 ("vdpa/mlx5: Add RX MAC VLAN filter support")
Acked-by: Jason Wang <jasowang@redhat.com>
Signed-off-by: Eli Cohen <elic@nvidia.com>
Message-Id: <20221114131759.57883-2-elic@nvidia.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 drivers/vdpa/mlx5/net/mlx5_vnet.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c
index 90913365def43..3fb06dcee9436 100644
--- a/drivers/vdpa/mlx5/net/mlx5_vnet.c
+++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c
@@ -1468,11 +1468,13 @@ static int mlx5_vdpa_add_mac_vlan_rules(struct mlx5_vdpa_net *ndev, u8 *mac,
 	dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v, outer_headers.dmac_47_16);
 	eth_broadcast_addr(dmac_c);
 	ether_addr_copy(dmac_v, mac);
-	MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
+	if (ndev->mvdev.actual_features & BIT_ULL(VIRTIO_NET_F_CTRL_VLAN)) {
+		MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
+		MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, first_vid);
+	}
 	if (tagged) {
 		MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
-		MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, first_vid);
-		MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, vid);
+		MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, vid);
 	}
 	flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
 	dest.type = MLX5_FLOW_DESTINATION_TYPE_TIR;
-- 
GitLab


From 5aec804936bbff182081f1cdc271fcb76af1a4ff Mon Sep 17 00:00:00 2001
From: Eli Cohen <elic@nvidia.com>
Date: Mon, 14 Nov 2022 15:17:53 +0200
Subject: [PATCH 736/875] vdpa/mlx5: Return error on vlan ctrl commands if not
 supported
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Check if VIRTIO_NET_F_CTRL_VLAN is negotiated and return error if
control VQ command is received.

Signed-off-by: Eli Cohen <elic@nvidia.com>
Message-Id: <20221114131759.57883-3-elic@nvidia.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
---
 drivers/vdpa/mlx5/net/mlx5_vnet.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c
index 3fb06dcee9436..01da229d22da3 100644
--- a/drivers/vdpa/mlx5/net/mlx5_vnet.c
+++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c
@@ -1823,6 +1823,9 @@ static virtio_net_ctrl_ack handle_ctrl_vlan(struct mlx5_vdpa_dev *mvdev, u8 cmd)
 	size_t read;
 	u16 id;
 
+	if (!(ndev->mvdev.actual_features & BIT_ULL(VIRTIO_NET_F_CTRL_VLAN)))
+		return status;
+
 	switch (cmd) {
 	case VIRTIO_NET_CTRL_VLAN_ADD:
 		read = vringh_iov_pull_iotlb(&cvq->vring, &cvq->riov, &vlan, sizeof(vlan));
-- 
GitLab


From 1ab53760d322c82fb4cb5e81b5817065801e3ec4 Mon Sep 17 00:00:00 2001
From: Eli Cohen <elic@nvidia.com>
Date: Mon, 14 Nov 2022 15:17:54 +0200
Subject: [PATCH 737/875] vdpa/mlx5: Fix wrong mac address deletion

Delete the old MAC from the table and not the new one which is not there
yet.

Fixes: baf2ad3f6a98 ("vdpa/mlx5: Add RX MAC VLAN filter support")
Acked-by: Jason Wang <jasowang@redhat.com>
Signed-off-by: Eli Cohen <elic@nvidia.com>
Message-Id: <20221114131759.57883-4-elic@nvidia.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 drivers/vdpa/mlx5/net/mlx5_vnet.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c
index 01da229d22da3..b06260a376800 100644
--- a/drivers/vdpa/mlx5/net/mlx5_vnet.c
+++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c
@@ -1686,7 +1686,7 @@ static virtio_net_ctrl_ack handle_ctrl_mac(struct mlx5_vdpa_dev *mvdev, u8 cmd)
 
 		/* Need recreate the flow table entry, so that the packet could forward back
 		 */
-		mac_vlan_del(ndev, ndev->config.mac, 0, false);
+		mac_vlan_del(ndev, mac_back, 0, false);
 
 		if (mac_vlan_add(ndev, ndev->config.mac, 0, false)) {
 			mlx5_vdpa_warn(mvdev, "failed to insert forward rules, try to restore\n");
-- 
GitLab


From 0dbc1b4ae07d003b2e88ba9d4142846320f8e349 Mon Sep 17 00:00:00 2001
From: Eli Cohen <elic@nvidia.com>
Date: Mon, 14 Nov 2022 15:17:55 +0200
Subject: [PATCH 738/875] vdpa/mlx5: Avoid using reslock in event_handler

event_handler runs under atomic context and may not acquire reslock. We
can still guarantee that the handler won't be called after suspend by
clearing nb_registered, unregistering the handler and flushing the
workqueue.

Signed-off-by: Eli Cohen <elic@nvidia.com>
Message-Id: <20221114131759.57883-5-elic@nvidia.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 drivers/vdpa/mlx5/net/mlx5_vnet.c | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c
index b06260a376800..98dd8ce8af265 100644
--- a/drivers/vdpa/mlx5/net/mlx5_vnet.c
+++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c
@@ -2845,8 +2845,8 @@ static int mlx5_vdpa_suspend(struct vdpa_device *vdev)
 	int i;
 
 	down_write(&ndev->reslock);
-	mlx5_notifier_unregister(mvdev->mdev, &ndev->nb);
 	ndev->nb_registered = false;
+	mlx5_notifier_unregister(mvdev->mdev, &ndev->nb);
 	flush_workqueue(ndev->mvdev.wq);
 	for (i = 0; i < ndev->cur_num_vqs; i++) {
 		mvq = &ndev->vqs[i];
@@ -3024,7 +3024,7 @@ static void update_carrier(struct work_struct *work)
 	else
 		ndev->config.status &= cpu_to_mlx5vdpa16(mvdev, ~VIRTIO_NET_S_LINK_UP);
 
-	if (ndev->config_cb.callback)
+	if (ndev->nb_registered && ndev->config_cb.callback)
 		ndev->config_cb.callback(ndev->config_cb.private);
 
 	kfree(wqent);
@@ -3041,21 +3041,13 @@ static int event_handler(struct notifier_block *nb, unsigned long event, void *p
 		switch (eqe->sub_type) {
 		case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 		case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
-			down_read(&ndev->reslock);
-			if (!ndev->nb_registered) {
-				up_read(&ndev->reslock);
-				return NOTIFY_DONE;
-			}
 			wqent = kzalloc(sizeof(*wqent), GFP_ATOMIC);
-			if (!wqent) {
-				up_read(&ndev->reslock);
+			if (!wqent)
 				return NOTIFY_DONE;
-			}
 
 			wqent->mvdev = &ndev->mvdev;
 			INIT_WORK(&wqent->work, update_carrier);
 			queue_work(ndev->mvdev.wq, &wqent->work);
-			up_read(&ndev->reslock);
 			ret = NOTIFY_OK;
 			break;
 		default:
@@ -3242,8 +3234,8 @@ static void mlx5_vdpa_dev_del(struct vdpa_mgmt_dev *v_mdev, struct vdpa_device *
 	struct workqueue_struct *wq;
 
 	if (ndev->nb_registered) {
-		mlx5_notifier_unregister(mvdev->mdev, &ndev->nb);
 		ndev->nb_registered = false;
+		mlx5_notifier_unregister(mvdev->mdev, &ndev->nb);
 	}
 	wq = mvdev->wq;
 	mvdev->wq = NULL;
-- 
GitLab


From 38fc462f57ef4e5dc722bab6824854b105de8aa2 Mon Sep 17 00:00:00 2001
From: Eli Cohen <elic@nvidia.com>
Date: Mon, 14 Nov 2022 15:17:56 +0200
Subject: [PATCH 739/875] vdpa/mlx5: Avoid overwriting CVQ iotlb
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When qemu uses different address spaces for data and control virtqueues,
the current code would overwrite the control virtqueue iotlb through the
dup_iotlb call. Fix this by referring to the address space identifier
and the group to asid mapping to determine which mapping needs to be
updated. We also move the address space logic from mlx5 net to core
directory.

Reported-by: Eugenio Pérez <eperezma@redhat.com>
Signed-off-by: Eli Cohen <elic@nvidia.com>
Message-Id: <20221114131759.57883-6-elic@nvidia.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
---
 drivers/vdpa/mlx5/core/mlx5_vdpa.h |  5 +--
 drivers/vdpa/mlx5/core/mr.c        | 44 ++++++++++++++++-----------
 drivers/vdpa/mlx5/net/mlx5_vnet.c  | 49 ++++++------------------------
 3 files changed, 39 insertions(+), 59 deletions(-)

diff --git a/drivers/vdpa/mlx5/core/mlx5_vdpa.h b/drivers/vdpa/mlx5/core/mlx5_vdpa.h
index 6af9fdbb86b7a..058fbe28107e9 100644
--- a/drivers/vdpa/mlx5/core/mlx5_vdpa.h
+++ b/drivers/vdpa/mlx5/core/mlx5_vdpa.h
@@ -116,8 +116,9 @@ int mlx5_vdpa_create_mkey(struct mlx5_vdpa_dev *mvdev, u32 *mkey, u32 *in,
 			  int inlen);
 int mlx5_vdpa_destroy_mkey(struct mlx5_vdpa_dev *mvdev, u32 mkey);
 int mlx5_vdpa_handle_set_map(struct mlx5_vdpa_dev *mvdev, struct vhost_iotlb *iotlb,
-			     bool *change_map);
-int mlx5_vdpa_create_mr(struct mlx5_vdpa_dev *mvdev, struct vhost_iotlb *iotlb);
+			     bool *change_map, unsigned int asid);
+int mlx5_vdpa_create_mr(struct mlx5_vdpa_dev *mvdev, struct vhost_iotlb *iotlb,
+			unsigned int asid);
 void mlx5_vdpa_destroy_mr(struct mlx5_vdpa_dev *mvdev);
 
 #define mlx5_vdpa_warn(__dev, format, ...)                                                         \
diff --git a/drivers/vdpa/mlx5/core/mr.c b/drivers/vdpa/mlx5/core/mr.c
index a639b9208d414..a4d7ee2339fa5 100644
--- a/drivers/vdpa/mlx5/core/mr.c
+++ b/drivers/vdpa/mlx5/core/mr.c
@@ -511,7 +511,8 @@ out:
 	mutex_unlock(&mr->mkey_mtx);
 }
 
-static int _mlx5_vdpa_create_mr(struct mlx5_vdpa_dev *mvdev, struct vhost_iotlb *iotlb)
+static int _mlx5_vdpa_create_mr(struct mlx5_vdpa_dev *mvdev,
+				struct vhost_iotlb *iotlb, unsigned int asid)
 {
 	struct mlx5_vdpa_mr *mr = &mvdev->mr;
 	int err;
@@ -519,42 +520,49 @@ static int _mlx5_vdpa_create_mr(struct mlx5_vdpa_dev *mvdev, struct vhost_iotlb
 	if (mr->initialized)
 		return 0;
 
-	if (iotlb)
-		err = create_user_mr(mvdev, iotlb);
-	else
-		err = create_dma_mr(mvdev, mr);
+	if (mvdev->group2asid[MLX5_VDPA_DATAVQ_GROUP] == asid) {
+		if (iotlb)
+			err = create_user_mr(mvdev, iotlb);
+		else
+			err = create_dma_mr(mvdev, mr);
 
-	if (err)
-		return err;
+		if (err)
+			return err;
+	}
 
-	err = dup_iotlb(mvdev, iotlb);
-	if (err)
-		goto out_err;
+	if (mvdev->group2asid[MLX5_VDPA_CVQ_GROUP] == asid) {
+		err = dup_iotlb(mvdev, iotlb);
+		if (err)
+			goto out_err;
+	}
 
 	mr->initialized = true;
 	return 0;
 
 out_err:
-	if (iotlb)
-		destroy_user_mr(mvdev, mr);
-	else
-		destroy_dma_mr(mvdev, mr);
+	if (mvdev->group2asid[MLX5_VDPA_DATAVQ_GROUP] == asid) {
+		if (iotlb)
+			destroy_user_mr(mvdev, mr);
+		else
+			destroy_dma_mr(mvdev, mr);
+	}
 
 	return err;
 }
 
-int mlx5_vdpa_create_mr(struct mlx5_vdpa_dev *mvdev, struct vhost_iotlb *iotlb)
+int mlx5_vdpa_create_mr(struct mlx5_vdpa_dev *mvdev, struct vhost_iotlb *iotlb,
+			unsigned int asid)
 {
 	int err;
 
 	mutex_lock(&mvdev->mr.mkey_mtx);
-	err = _mlx5_vdpa_create_mr(mvdev, iotlb);
+	err = _mlx5_vdpa_create_mr(mvdev, iotlb, asid);
 	mutex_unlock(&mvdev->mr.mkey_mtx);
 	return err;
 }
 
 int mlx5_vdpa_handle_set_map(struct mlx5_vdpa_dev *mvdev, struct vhost_iotlb *iotlb,
-			     bool *change_map)
+			     bool *change_map, unsigned int asid)
 {
 	struct mlx5_vdpa_mr *mr = &mvdev->mr;
 	int err = 0;
@@ -566,7 +574,7 @@ int mlx5_vdpa_handle_set_map(struct mlx5_vdpa_dev *mvdev, struct vhost_iotlb *io
 		*change_map = true;
 	}
 	if (!*change_map)
-		err = _mlx5_vdpa_create_mr(mvdev, iotlb);
+		err = _mlx5_vdpa_create_mr(mvdev, iotlb, asid);
 	mutex_unlock(&mr->mkey_mtx);
 
 	return err;
diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c
index 98dd8ce8af265..3a6dbbc6440d4 100644
--- a/drivers/vdpa/mlx5/net/mlx5_vnet.c
+++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c
@@ -2394,7 +2394,8 @@ static void restore_channels_info(struct mlx5_vdpa_net *ndev)
 	}
 }
 
-static int mlx5_vdpa_change_map(struct mlx5_vdpa_dev *mvdev, struct vhost_iotlb *iotlb)
+static int mlx5_vdpa_change_map(struct mlx5_vdpa_dev *mvdev,
+				struct vhost_iotlb *iotlb, unsigned int asid)
 {
 	struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev);
 	int err;
@@ -2406,7 +2407,7 @@ static int mlx5_vdpa_change_map(struct mlx5_vdpa_dev *mvdev, struct vhost_iotlb
 
 	teardown_driver(ndev);
 	mlx5_vdpa_destroy_mr(mvdev);
-	err = mlx5_vdpa_create_mr(mvdev, iotlb);
+	err = mlx5_vdpa_create_mr(mvdev, iotlb, asid);
 	if (err)
 		goto err_mr;
 
@@ -2587,7 +2588,7 @@ static int mlx5_vdpa_reset(struct vdpa_device *vdev)
 	++mvdev->generation;
 
 	if (MLX5_CAP_GEN(mvdev->mdev, umem_uid_0)) {
-		if (mlx5_vdpa_create_mr(mvdev, NULL))
+		if (mlx5_vdpa_create_mr(mvdev, NULL, 0))
 			mlx5_vdpa_warn(mvdev, "create MR failed\n");
 	}
 	up_write(&ndev->reslock);
@@ -2623,41 +2624,20 @@ static u32 mlx5_vdpa_get_generation(struct vdpa_device *vdev)
 	return mvdev->generation;
 }
 
-static int set_map_control(struct mlx5_vdpa_dev *mvdev, struct vhost_iotlb *iotlb)
-{
-	u64 start = 0ULL, last = 0ULL - 1;
-	struct vhost_iotlb_map *map;
-	int err = 0;
-
-	spin_lock(&mvdev->cvq.iommu_lock);
-	vhost_iotlb_reset(mvdev->cvq.iotlb);
-
-	for (map = vhost_iotlb_itree_first(iotlb, start, last); map;
-	     map = vhost_iotlb_itree_next(map, start, last)) {
-		err = vhost_iotlb_add_range(mvdev->cvq.iotlb, map->start,
-					    map->last, map->addr, map->perm);
-		if (err)
-			goto out;
-	}
-
-out:
-	spin_unlock(&mvdev->cvq.iommu_lock);
-	return err;
-}
-
-static int set_map_data(struct mlx5_vdpa_dev *mvdev, struct vhost_iotlb *iotlb)
+static int set_map_data(struct mlx5_vdpa_dev *mvdev, struct vhost_iotlb *iotlb,
+			unsigned int asid)
 {
 	bool change_map;
 	int err;
 
-	err = mlx5_vdpa_handle_set_map(mvdev, iotlb, &change_map);
+	err = mlx5_vdpa_handle_set_map(mvdev, iotlb, &change_map, asid);
 	if (err) {
 		mlx5_vdpa_warn(mvdev, "set map failed(%d)\n", err);
 		return err;
 	}
 
 	if (change_map)
-		err = mlx5_vdpa_change_map(mvdev, iotlb);
+		err = mlx5_vdpa_change_map(mvdev, iotlb, asid);
 
 	return err;
 }
@@ -2670,16 +2650,7 @@ static int mlx5_vdpa_set_map(struct vdpa_device *vdev, unsigned int asid,
 	int err = -EINVAL;
 
 	down_write(&ndev->reslock);
-	if (mvdev->group2asid[MLX5_VDPA_DATAVQ_GROUP] == asid) {
-		err = set_map_data(mvdev, iotlb);
-		if (err)
-			goto out;
-	}
-
-	if (mvdev->group2asid[MLX5_VDPA_CVQ_GROUP] == asid)
-		err = set_map_control(mvdev, iotlb);
-
-out:
+	err = set_map_data(mvdev, iotlb, asid);
 	up_write(&ndev->reslock);
 	return err;
 }
@@ -3182,7 +3153,7 @@ static int mlx5_vdpa_dev_add(struct vdpa_mgmt_dev *v_mdev, const char *name,
 		goto err_mpfs;
 
 	if (MLX5_CAP_GEN(mvdev->mdev, umem_uid_0)) {
-		err = mlx5_vdpa_create_mr(mvdev, NULL);
+		err = mlx5_vdpa_create_mr(mvdev, NULL, 0);
 		if (err)
 			goto err_res;
 	}
-- 
GitLab


From 344686136d73501a18a9621de690ff7824a3d129 Mon Sep 17 00:00:00 2001
From: Shaoqin Huang <shaoqin.huang@intel.com>
Date: Thu, 20 Oct 2022 23:27:33 -0700
Subject: [PATCH 740/875] virtio_pci: use helper function is_power_of_2()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Use helper function is_power_of_2() to check if num is power of two.
Minor readability improvement.

Signed-off-by: Shaoqin Huang <shaoqin.huang@intel.com>
Message-Id: <20221021062734.228881-2-shaoqin.huang@intel.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
---
 drivers/virtio/virtio_pci_modern.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/virtio/virtio_pci_modern.c b/drivers/virtio/virtio_pci_modern.c
index c3b9f27618497..207294bd7b9d6 100644
--- a/drivers/virtio/virtio_pci_modern.c
+++ b/drivers/virtio/virtio_pci_modern.c
@@ -310,7 +310,7 @@ static struct virtqueue *setup_vq(struct virtio_pci_device *vp_dev,
 	if (!num || vp_modern_get_queue_enable(mdev, index))
 		return ERR_PTR(-ENOENT);
 
-	if (num & (num - 1)) {
+	if (!is_power_of_2(num)) {
 		dev_warn(&vp_dev->pci_dev->dev, "bad queue size %u", num);
 		return ERR_PTR(-EINVAL);
 	}
-- 
GitLab


From b9d978a89296c57fbbbd8ea647c303ce4d37028f Mon Sep 17 00:00:00 2001
From: Shaoqin Huang <shaoqin.huang@intel.com>
Date: Thu, 20 Oct 2022 23:27:34 -0700
Subject: [PATCH 741/875] virtio_ring: use helper function is_power_of_2()

Use helper function is_power_of_2() to check if num is power of two.
Minor readability improvement.

Signed-off-by: Shaoqin Huang <shaoqin.huang@intel.com>
Message-Id: <20221021062734.228881-3-shaoqin.huang@intel.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
---
 drivers/virtio/virtio_ring.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c
index 2e7689bb933b8..723c4e29e1d3b 100644
--- a/drivers/virtio/virtio_ring.c
+++ b/drivers/virtio/virtio_ring.c
@@ -1052,7 +1052,7 @@ static int vring_alloc_queue_split(struct vring_virtqueue_split *vring_split,
 	dma_addr_t dma_addr;
 
 	/* We assume num is a power of 2. */
-	if (num & (num - 1)) {
+	if (!is_power_of_2(num)) {
 		dev_warn(&vdev->dev, "Bad virtqueue length %u\n", num);
 		return -EINVAL;
 	}
-- 
GitLab


From a9f0a19ff7700cc8a30db2496f40d18490dcb9df Mon Sep 17 00:00:00 2001
From: Colin Ian King <colin.i.king@gmail.com>
Date: Mon, 24 Oct 2022 14:37:56 +0100
Subject: [PATCH 742/875] RDMA/mlx5: remove variable i

Variable i is just being incremented and it's never used
anywhere else. The variable and the increment are redundant so
remove it.

Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Message-Id: <20221024133756.2158497-1-colin.i.king@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 drivers/vdpa/mlx5/core/mr.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/vdpa/mlx5/core/mr.c b/drivers/vdpa/mlx5/core/mr.c
index a4d7ee2339fa5..0a1e0b0dc37e3 100644
--- a/drivers/vdpa/mlx5/core/mr.c
+++ b/drivers/vdpa/mlx5/core/mr.c
@@ -311,7 +311,6 @@ static int add_direct_chain(struct mlx5_vdpa_dev *mvdev, u64 start, u64 size, u8
 	u64 st;
 	u64 sz;
 	int err;
-	int i = 0;
 
 	st = start;
 	while (size) {
@@ -336,7 +335,6 @@ static int add_direct_chain(struct mlx5_vdpa_dev *mvdev, u64 start, u64 size, u8
 		mr->num_directs++;
 		mr->num_klms++;
 		st += sz;
-		i++;
 	}
 	list_splice_tail(&tmp, &mr->head);
 	return 0;
-- 
GitLab


From b66ead2d0ecac00c3a06a6218af5411cb5fcb5d5 Mon Sep 17 00:00:00 2001
From: Angus Chen <angus.chen@jaguarmicro.com>
Date: Tue, 1 Nov 2022 19:16:54 +0800
Subject: [PATCH 743/875] virtio_pci: modify ENOENT to EINVAL

Virtio_crypto use max_data_queues+1 to setup vqs,
we use vp_modern_get_num_queues to protect the vq range in setup_vq.
We could enter index >= vp_modern_get_num_queues(mdev) in setup_vq
if common->num_queues is not set well,and it return -ENOENT.
It is better to use -EINVAL instead.

Signed-off-by: Angus Chen <angus.chen@jaguarmicro.com>
Message-Id: <20221101111655.1947-1-angus.chen@jaguarmicro.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 drivers/virtio/virtio_pci_modern.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/virtio/virtio_pci_modern.c b/drivers/virtio/virtio_pci_modern.c
index 207294bd7b9d6..9e496e288cfad 100644
--- a/drivers/virtio/virtio_pci_modern.c
+++ b/drivers/virtio/virtio_pci_modern.c
@@ -303,7 +303,7 @@ static struct virtqueue *setup_vq(struct virtio_pci_device *vp_dev,
 	int err;
 
 	if (index >= vp_modern_get_num_queues(mdev))
-		return ERR_PTR(-ENOENT);
+		return ERR_PTR(-EINVAL);
 
 	/* Check if queue is either not available or already active. */
 	num = vp_modern_get_queue_size(mdev, index);
-- 
GitLab


From 75e4ab9735a5a70612dd06461ca372b897bf371c Mon Sep 17 00:00:00 2001
From: Shaomin Deng <dengshaomin@cdjrlc.com>
Date: Sat, 5 Nov 2022 11:51:51 -0400
Subject: [PATCH 744/875] tools: Delete the unneeded semicolon after curly
 braces

Unneeded semicolon after curly braces, so delete it.

Signed-off-by: Shaomin Deng <dengshaomin@cdjrlc.com>
Message-Id: <20221105155151.12155-1-dengshaomin@cdjrlc.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 tools/virtio/virtio-trace/trace-agent-ctl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/virtio/virtio-trace/trace-agent-ctl.c b/tools/virtio/virtio-trace/trace-agent-ctl.c
index 73d253d4b559a..39860be6e2d86 100644
--- a/tools/virtio/virtio-trace/trace-agent-ctl.c
+++ b/tools/virtio/virtio-trace/trace-agent-ctl.c
@@ -75,7 +75,7 @@ static int wait_order(int ctl_fd)
 
 		if (ret)
 			break;
-	};
+	}
 
 	return ret;
 
-- 
GitLab


From aeca7ff254843d49a8739f07f7dab1341450111d Mon Sep 17 00:00:00 2001
From: ruanjinjie <ruanjinjie@huawei.com>
Date: Thu, 10 Nov 2022 16:23:48 +0800
Subject: [PATCH 745/875] vdpa_sim: fix possible memory leak in
 vdpasim_net_init() and vdpasim_blk_init()

Inject fault while probing module, if device_register() fails in
vdpasim_net_init() or vdpasim_blk_init(), but the refcount of kobject is
not decreased to 0, the name allocated in dev_set_name() is leaked.
Fix this by calling put_device(), so that name can be freed in
callback function kobject_cleanup().

(vdpa_sim_net)
unreferenced object 0xffff88807eebc370 (size 16):
  comm "modprobe", pid 3848, jiffies 4362982860 (age 18.153s)
  hex dump (first 16 bytes):
    76 64 70 61 73 69 6d 5f 6e 65 74 00 6b 6b 6b a5  vdpasim_net.kkk.
  backtrace:
    [<ffffffff8174f19e>] __kmalloc_node_track_caller+0x4e/0x150
    [<ffffffff81731d53>] kstrdup+0x33/0x60
    [<ffffffff83a5d421>] kobject_set_name_vargs+0x41/0x110
    [<ffffffff82d87aab>] dev_set_name+0xab/0xe0
    [<ffffffff82d91a23>] device_add+0xe3/0x1a80
    [<ffffffffa0270013>] 0xffffffffa0270013
    [<ffffffff81001c27>] do_one_initcall+0x87/0x2e0
    [<ffffffff813739cb>] do_init_module+0x1ab/0x640
    [<ffffffff81379d20>] load_module+0x5d00/0x77f0
    [<ffffffff8137bc40>] __do_sys_finit_module+0x110/0x1b0
    [<ffffffff83c4d505>] do_syscall_64+0x35/0x80
    [<ffffffff83e0006a>] entry_SYSCALL_64_after_hwframe+0x46/0xb0

(vdpa_sim_blk)
unreferenced object 0xffff8881070c1250 (size 16):
  comm "modprobe", pid 6844, jiffies 4364069319 (age 17.572s)
  hex dump (first 16 bytes):
    76 64 70 61 73 69 6d 5f 62 6c 6b 00 6b 6b 6b a5  vdpasim_blk.kkk.
  backtrace:
    [<ffffffff8174f19e>] __kmalloc_node_track_caller+0x4e/0x150
    [<ffffffff81731d53>] kstrdup+0x33/0x60
    [<ffffffff83a5d421>] kobject_set_name_vargs+0x41/0x110
    [<ffffffff82d87aab>] dev_set_name+0xab/0xe0
    [<ffffffff82d91a23>] device_add+0xe3/0x1a80
    [<ffffffffa0220013>] 0xffffffffa0220013
    [<ffffffff81001c27>] do_one_initcall+0x87/0x2e0
    [<ffffffff813739cb>] do_init_module+0x1ab/0x640
    [<ffffffff81379d20>] load_module+0x5d00/0x77f0
    [<ffffffff8137bc40>] __do_sys_finit_module+0x110/0x1b0
    [<ffffffff83c4d505>] do_syscall_64+0x35/0x80
    [<ffffffff83e0006a>] entry_SYSCALL_64_after_hwframe+0x46/0xb0

Fixes: 899c4d187f6a ("vdpa_sim_blk: add support for vdpa management tool")
Fixes: a3c06ae158dd ("vdpa_sim_net: Add support for user supported devices")

Signed-off-by: ruanjinjie <ruanjinjie@huawei.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Message-Id: <20221110082348.4105476-1-ruanjinjie@huawei.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
---
 drivers/vdpa/vdpa_sim/vdpa_sim_blk.c | 4 +++-
 drivers/vdpa/vdpa_sim/vdpa_sim_net.c | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c b/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c
index c6db1a1baf768..f745926237a88 100644
--- a/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c
+++ b/drivers/vdpa/vdpa_sim/vdpa_sim_blk.c
@@ -427,8 +427,10 @@ static int __init vdpasim_blk_init(void)
 	int ret;
 
 	ret = device_register(&vdpasim_blk_mgmtdev);
-	if (ret)
+	if (ret) {
+		put_device(&vdpasim_blk_mgmtdev);
 		return ret;
+	}
 
 	ret = vdpa_mgmtdev_register(&mgmt_dev);
 	if (ret)
diff --git a/drivers/vdpa/vdpa_sim/vdpa_sim_net.c b/drivers/vdpa/vdpa_sim/vdpa_sim_net.c
index c3cb225ea4693..11f5a121df243 100644
--- a/drivers/vdpa/vdpa_sim/vdpa_sim_net.c
+++ b/drivers/vdpa/vdpa_sim/vdpa_sim_net.c
@@ -305,8 +305,10 @@ static int __init vdpasim_net_init(void)
 	int ret;
 
 	ret = device_register(&vdpasim_net_mgmtdev);
-	if (ret)
+	if (ret) {
+		put_device(&vdpasim_net_mgmtdev);
 		return ret;
+	}
 
 	ret = vdpa_mgmtdev_register(&mgmt_dev);
 	if (ret)
-- 
GitLab


From 7a4efe182ca61fb3e5307e69b261c57cbf434cd4 Mon Sep 17 00:00:00 2001
From: Yuan Can <yuancan@huawei.com>
Date: Tue, 8 Nov 2022 10:17:05 +0000
Subject: [PATCH 746/875] vhost/vsock: Fix error handling in vhost_vsock_init()

A problem about modprobe vhost_vsock failed is triggered with the
following log given:

modprobe: ERROR: could not insert 'vhost_vsock': Device or resource busy

The reason is that vhost_vsock_init() returns misc_register() directly
without checking its return value, if misc_register() failed, it returns
without calling vsock_core_unregister() on vhost_transport, resulting the
vhost_vsock can never be installed later.
A simple call graph is shown as below:

 vhost_vsock_init()
   vsock_core_register() # register vhost_transport
   misc_register()
     device_create_with_groups()
       device_create_groups_vargs()
         dev = kzalloc(...) # OOM happened
   # return without unregister vhost_transport

Fix by calling vsock_core_unregister() when misc_register() returns error.

Fixes: 433fc58e6bf2 ("VSOCK: Introduce vhost_vsock.ko")
Signed-off-by: Yuan Can <yuancan@huawei.com>
Message-Id: <20221108101705.45981-1-yuancan@huawei.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
---
 drivers/vhost/vsock.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/vhost/vsock.c b/drivers/vhost/vsock.c
index cd6f7776013ac..a2b3743723639 100644
--- a/drivers/vhost/vsock.c
+++ b/drivers/vhost/vsock.c
@@ -959,7 +959,14 @@ static int __init vhost_vsock_init(void)
 				  VSOCK_TRANSPORT_F_H2G);
 	if (ret < 0)
 		return ret;
-	return misc_register(&vhost_vsock_misc);
+
+	ret = misc_register(&vhost_vsock_misc);
+	if (ret) {
+		vsock_core_unregister(&vhost_transport.transport);
+		return ret;
+	}
+
+	return 0;
 };
 
 static void __exit vhost_vsock_exit(void)
-- 
GitLab


From f85efa9b0f5381874f727bd98f56787840313f0b Mon Sep 17 00:00:00 2001
From: Stefano Garzarella <sgarzare@redhat.com>
Date: Wed, 9 Nov 2022 11:25:02 +0100
Subject: [PATCH 747/875] vringh: fix range used in iotlb_translate()

vhost_iotlb_itree_first() requires `start` and `last` parameters
to search for a mapping that overlaps the range.

In iotlb_translate() we cyclically call vhost_iotlb_itree_first(),
incrementing `addr` by the amount already translated, so rightly
we move the `start` parameter passed to vhost_iotlb_itree_first(),
but we should hold the `last` parameter constant.

Let's fix it by saving the `last` parameter value before incrementing
`addr` in the loop.

Fixes: 9ad9c49cfe97 ("vringh: IOTLB support")
Acked-by: Jason Wang <jasowang@redhat.com>
Signed-off-by: Stefano Garzarella <sgarzare@redhat.com>
Message-Id: <20221109102503.18816-2-sgarzare@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 drivers/vhost/vringh.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/vhost/vringh.c b/drivers/vhost/vringh.c
index c9f5c8ea3afbd..33eb941fcf154 100644
--- a/drivers/vhost/vringh.c
+++ b/drivers/vhost/vringh.c
@@ -1102,7 +1102,7 @@ static int iotlb_translate(const struct vringh *vrh,
 	struct vhost_iotlb_map *map;
 	struct vhost_iotlb *iotlb = vrh->iotlb;
 	int ret = 0;
-	u64 s = 0;
+	u64 s = 0, last = addr + len - 1;
 
 	spin_lock(vrh->iotlb_lock);
 
@@ -1114,8 +1114,7 @@ static int iotlb_translate(const struct vringh *vrh,
 			break;
 		}
 
-		map = vhost_iotlb_itree_first(iotlb, addr,
-					      addr + len - 1);
+		map = vhost_iotlb_itree_first(iotlb, addr, last);
 		if (!map || map->start > addr) {
 			ret = -EINVAL;
 			break;
-- 
GitLab


From 98047313cdb46828093894d0ac8b1183b8b317f9 Mon Sep 17 00:00:00 2001
From: Stefano Garzarella <sgarzare@redhat.com>
Date: Wed, 9 Nov 2022 11:25:03 +0100
Subject: [PATCH 748/875] vhost: fix range used in translate_desc()

vhost_iotlb_itree_first() requires `start` and `last` parameters
to search for a mapping that overlaps the range.

In translate_desc() we cyclically call vhost_iotlb_itree_first(),
incrementing `addr` by the amount already translated, so rightly
we move the `start` parameter passed to vhost_iotlb_itree_first(),
but we should hold the `last` parameter constant.

Let's fix it by saving the `last` parameter value before incrementing
`addr` in the loop.

Fixes: a9709d6874d5 ("vhost: convert pre sorted vhost memory array to interval tree")
Acked-by: Jason Wang <jasowang@redhat.com>
Signed-off-by: Stefano Garzarella <sgarzare@redhat.com>
Message-Id: <20221109102503.18816-3-sgarzare@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 drivers/vhost/vhost.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/vhost/vhost.c b/drivers/vhost/vhost.c
index 5c9fe3c9c3646..cbe72bfd2f1fa 100644
--- a/drivers/vhost/vhost.c
+++ b/drivers/vhost/vhost.c
@@ -2053,7 +2053,7 @@ static int translate_desc(struct vhost_virtqueue *vq, u64 addr, u32 len,
 	struct vhost_dev *dev = vq->dev;
 	struct vhost_iotlb *umem = dev->iotlb ? dev->iotlb : dev->umem;
 	struct iovec *_iov;
-	u64 s = 0;
+	u64 s = 0, last = addr + len - 1;
 	int ret = 0;
 
 	while ((u64)len > s) {
@@ -2063,7 +2063,7 @@ static int translate_desc(struct vhost_virtqueue *vq, u64 addr, u32 len,
 			break;
 		}
 
-		map = vhost_iotlb_itree_first(umem, addr, addr + len - 1);
+		map = vhost_iotlb_itree_first(umem, addr, last);
 		if (map == NULL || map->start > addr) {
 			if (umem != dev->iotlb) {
 				ret = -EFAULT;
-- 
GitLab


From c070c1912a83432530cbb4271d5b9b11fa36b67a Mon Sep 17 00:00:00 2001
From: Stefano Garzarella <sgarzare@redhat.com>
Date: Wed, 9 Nov 2022 16:42:13 +0100
Subject: [PATCH 749/875] vhost-vdpa: fix an iotlb memory leak

Before commit 3d5698793897 ("vhost-vdpa: introduce asid based IOTLB")
we called vhost_vdpa_iotlb_unmap(v, iotlb, 0ULL, 0ULL - 1) during
release to free all the resources allocated when processing user IOTLB
messages through vhost_vdpa_process_iotlb_update().
That commit changed the handling of IOTLB a bit, and we accidentally
removed some code called during the release.

We partially fixed this with commit 037d4305569a ("vhost-vdpa: call
vhost_vdpa_cleanup during the release") but a potential memory leak is
still there as showed by kmemleak if the application does not send
VHOST_IOTLB_INVALIDATE or crashes:

  unreferenced object 0xffff888007fbaa30 (size 16):
    comm "blkio-bench", pid 914, jiffies 4294993521 (age 885.500s)
    hex dump (first 16 bytes):
      40 73 41 07 80 88 ff ff 00 00 00 00 00 00 00 00  @sA.............
    backtrace:
      [<0000000087736d2a>] kmem_cache_alloc_trace+0x142/0x1c0
      [<0000000060740f50>] vhost_vdpa_process_iotlb_msg+0x68c/0x901 [vhost_vdpa]
      [<0000000083e8e205>] vhost_chr_write_iter+0xc0/0x4a0 [vhost]
      [<000000008f2f414a>] vhost_vdpa_chr_write_iter+0x18/0x20 [vhost_vdpa]
      [<00000000de1cd4a0>] vfs_write+0x216/0x4b0
      [<00000000a2850200>] ksys_write+0x71/0xf0
      [<00000000de8e720b>] __x64_sys_write+0x19/0x20
      [<0000000018b12cbb>] do_syscall_64+0x3f/0x90
      [<00000000986ec465>] entry_SYSCALL_64_after_hwframe+0x63/0xcd

Let's fix this calling vhost_vdpa_iotlb_unmap() on the whole range in
vhost_vdpa_remove_as(). We move that call before vhost_dev_cleanup()
since we need a valid v->vdev.mm in vhost_vdpa_pa_unmap().
vhost_iotlb_reset() call can be removed, since vhost_vdpa_iotlb_unmap()
on the whole range removes all the entries.

The kmemleak log reported was observed with a vDPA device that has `use_va`
set to true (e.g. VDUSE). This patch has been tested with both types of
devices.

Fixes: 037d4305569a ("vhost-vdpa: call vhost_vdpa_cleanup during the release")
Fixes: 3d5698793897 ("vhost-vdpa: introduce asid based IOTLB")
Signed-off-by: Stefano Garzarella <sgarzare@redhat.com>
Message-Id: <20221109154213.146789-1-sgarzare@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
---
 drivers/vhost/vdpa.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/vhost/vdpa.c b/drivers/vhost/vdpa.c
index 166044642fd5c..b08e07fc7d1ff 100644
--- a/drivers/vhost/vdpa.c
+++ b/drivers/vhost/vdpa.c
@@ -65,6 +65,10 @@ static DEFINE_IDA(vhost_vdpa_ida);
 
 static dev_t vhost_vdpa_major;
 
+static void vhost_vdpa_iotlb_unmap(struct vhost_vdpa *v,
+				   struct vhost_iotlb *iotlb,
+				   u64 start, u64 last);
+
 static inline u32 iotlb_to_asid(struct vhost_iotlb *iotlb)
 {
 	struct vhost_vdpa_as *as = container_of(iotlb, struct
@@ -135,7 +139,7 @@ static int vhost_vdpa_remove_as(struct vhost_vdpa *v, u32 asid)
 		return -EINVAL;
 
 	hlist_del(&as->hash_link);
-	vhost_iotlb_reset(&as->iotlb);
+	vhost_vdpa_iotlb_unmap(v, &as->iotlb, 0ULL, 0ULL - 1);
 	kfree(as);
 
 	return 0;
@@ -1162,14 +1166,14 @@ static void vhost_vdpa_cleanup(struct vhost_vdpa *v)
 	struct vhost_vdpa_as *as;
 	u32 asid;
 
-	vhost_dev_cleanup(&v->vdev);
-	kfree(v->vdev.vqs);
-
 	for (asid = 0; asid < v->vdpa->nas; asid++) {
 		as = asid_to_as(v, asid);
 		if (as)
 			vhost_vdpa_remove_as(v, asid);
 	}
+
+	vhost_dev_cleanup(&v->vdev);
+	kfree(v->vdev.vqs);
 }
 
 static int vhost_vdpa_open(struct inode *inode, struct file *filep)
-- 
GitLab


From f4e468f708386ce5fa6878a7ef43a9818ceeaecf Mon Sep 17 00:00:00 2001
From: Angus Chen <angus.chen@jaguarmicro.com>
Date: Thu, 10 Nov 2022 11:01:23 +0800
Subject: [PATCH 750/875] virtio_blk: use UINT_MAX instead of -1U

We use UINT_MAX to limit max_discard_sectors in virtblk_probe,
we can use UINT_MAX to limit max_hw_sectors for consistencies.

No functional change intended.

Signed-off-by: Angus Chen <angus.chen@jaguarmicro.com>
Message-Id: <20221110030124.1986-1-angus.chen@jaguarmicro.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
---
 drivers/block/virtio_blk.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/block/virtio_blk.c b/drivers/block/virtio_blk.c
index 271a9878fa8b3..dcbf86cd2155e 100644
--- a/drivers/block/virtio_blk.c
+++ b/drivers/block/virtio_blk.c
@@ -994,7 +994,7 @@ static int virtblk_probe(struct virtio_device *vdev)
 	blk_queue_max_segments(q, sg_elems);
 
 	/* No real sector limit. */
-	blk_queue_max_hw_sectors(q, -1U);
+	blk_queue_max_hw_sectors(q, UINT_MAX);
 
 	max_size = virtio_max_dma_size(vdev);
 
-- 
GitLab


From 794ec498c9fa79e6bfd71b931410d5897a9c00d4 Mon Sep 17 00:00:00 2001
From: Stefano Garzarella <sgarzare@redhat.com>
Date: Thu, 10 Nov 2022 15:13:35 +0100
Subject: [PATCH 751/875] vdpa_sim: fix vringh initialization in
 vdpasim_queue_ready()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When we initialize vringh, we should pass the features and the
number of elements in the virtqueue negotiated with the driver,
otherwise operations with vringh may fail.

This was discovered in a case where the driver sets a number of
elements in the virtqueue different from the value returned by
.get_vq_num_max().

In vdpasim_vq_reset() is safe to initialize the vringh with
default values, since the virtqueue will not be used until
vdpasim_queue_ready() is called again.

Fixes: 2c53d0f64c06 ("vdpasim: vDPA device simulator")
Signed-off-by: Stefano Garzarella <sgarzare@redhat.com>
Message-Id: <20221110141335.62171-1-sgarzare@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
---
 drivers/vdpa/vdpa_sim/vdpa_sim.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/vdpa/vdpa_sim/vdpa_sim.c b/drivers/vdpa/vdpa_sim/vdpa_sim.c
index b071f0d842fba..b20689f8fe89c 100644
--- a/drivers/vdpa/vdpa_sim/vdpa_sim.c
+++ b/drivers/vdpa/vdpa_sim/vdpa_sim.c
@@ -67,8 +67,7 @@ static void vdpasim_queue_ready(struct vdpasim *vdpasim, unsigned int idx)
 {
 	struct vdpasim_virtqueue *vq = &vdpasim->vqs[idx];
 
-	vringh_init_iotlb(&vq->vring, vdpasim->dev_attr.supported_features,
-			  VDPASIM_QUEUE_MAX, false,
+	vringh_init_iotlb(&vq->vring, vdpasim->features, vq->num, false,
 			  (struct vring_desc *)(uintptr_t)vq->desc_addr,
 			  (struct vring_avail *)
 			  (uintptr_t)vq->driver_addr,
-- 
GitLab


From a4722f64f924a9992efc08d141c21b2da02b70f3 Mon Sep 17 00:00:00 2001
From: wangjianli <wangjianli@cdjrlc.com>
Date: Sun, 13 Nov 2022 15:07:42 +0800
Subject: [PATCH 752/875] tools/virtio: Variable type completion

Replace "unsigned" with "unsigned int"

Signed-off-by: wangjianli <wangjianli@cdjrlc.com>
Message-Id: <20221113070742.48271-1-wangjianli@cdjrlc.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 tools/virtio/virtio_test.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/virtio/virtio_test.c b/tools/virtio/virtio_test.c
index 86a410ddcedde..120062f94590c 100644
--- a/tools/virtio/virtio_test.c
+++ b/tools/virtio/virtio_test.c
@@ -173,7 +173,7 @@ static void run_test(struct vdev_info *dev, struct vq_info *vq,
 	long started = 0, completed = 0, next_reset = reset_n;
 	long completed_before, started_before;
 	int r, test = 1;
-	unsigned len;
+	unsigned int len;
 	long long spurious = 0;
 	const bool random_batch = batch == RANDOM_BATCH;
 
-- 
GitLab


From b1d65f717cd6305a396a8738e022c6f7c65cfbe8 Mon Sep 17 00:00:00 2001
From: Wei Yongjun <weiyongjun1@huawei.com>
Date: Mon, 14 Nov 2022 11:07:40 +0000
Subject: [PATCH 753/875] virtio-crypto: fix memory leak in
 virtio_crypto_alg_skcipher_close_session()

'vc_ctrl_req' is alloced in virtio_crypto_alg_skcipher_close_session(),
and should be freed in the invalid ctrl_status->status error handling
case. Otherwise there is a memory leak.

Fixes: 0756ad15b1fe ("virtio-crypto: use private buffer for control request")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Message-Id: <20221114110740.537276-1-weiyongjun@huaweicloud.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Gonglei <arei.gonglei@huawei.com>
Acked-by: zhenwei pi<pizhenwei@bytedance.com>
Acked-by: Jason Wang <jasowang@redhat.com>
---
 drivers/crypto/virtio/virtio_crypto_skcipher_algs.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/virtio/virtio_crypto_skcipher_algs.c b/drivers/crypto/virtio/virtio_crypto_skcipher_algs.c
index e553ccadbcbc8..e5876286828b8 100644
--- a/drivers/crypto/virtio/virtio_crypto_skcipher_algs.c
+++ b/drivers/crypto/virtio/virtio_crypto_skcipher_algs.c
@@ -239,7 +239,8 @@ static int virtio_crypto_alg_skcipher_close_session(
 		pr_err("virtio_crypto: Close session failed status: %u, session_id: 0x%llx\n",
 			ctrl_status->status, destroy_session->session_id);
 
-		return -EINVAL;
+		err = -EINVAL;
+		goto out;
 	}
 
 	err = 0;
-- 
GitLab


From c8e82e3877028381969779a86972d9a4f57a9ea0 Mon Sep 17 00:00:00 2001
From: Dawei Li <set_pte_at@outlook.com>
Date: Fri, 25 Nov 2022 00:12:14 +0800
Subject: [PATCH 754/875] virtio: Implementing attribute show with sysfs_emit

Replace sprintf with sysfs_emit or its variants for their
built-in PAGE_SIZE awareness.

Signed-off-by: Dawei Li <set_pte_at@outlook.com>
Message-Id: <TYCP286MB23232A999FE7DBDF50BA0FAACA0F9@TYCP286MB2323.JPNP286.PROD.OUTLOOK.COM>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 drivers/virtio/virtio.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/virtio/virtio.c b/drivers/virtio/virtio.c
index 828ced0607423..b9a80aedee1b7 100644
--- a/drivers/virtio/virtio.c
+++ b/drivers/virtio/virtio.c
@@ -15,7 +15,7 @@ static ssize_t device_show(struct device *_d,
 			   struct device_attribute *attr, char *buf)
 {
 	struct virtio_device *dev = dev_to_virtio(_d);
-	return sprintf(buf, "0x%04x\n", dev->id.device);
+	return sysfs_emit(buf, "0x%04x\n", dev->id.device);
 }
 static DEVICE_ATTR_RO(device);
 
@@ -23,7 +23,7 @@ static ssize_t vendor_show(struct device *_d,
 			   struct device_attribute *attr, char *buf)
 {
 	struct virtio_device *dev = dev_to_virtio(_d);
-	return sprintf(buf, "0x%04x\n", dev->id.vendor);
+	return sysfs_emit(buf, "0x%04x\n", dev->id.vendor);
 }
 static DEVICE_ATTR_RO(vendor);
 
@@ -31,7 +31,7 @@ static ssize_t status_show(struct device *_d,
 			   struct device_attribute *attr, char *buf)
 {
 	struct virtio_device *dev = dev_to_virtio(_d);
-	return sprintf(buf, "0x%08x\n", dev->config->get_status(dev));
+	return sysfs_emit(buf, "0x%08x\n", dev->config->get_status(dev));
 }
 static DEVICE_ATTR_RO(status);
 
@@ -39,7 +39,7 @@ static ssize_t modalias_show(struct device *_d,
 			     struct device_attribute *attr, char *buf)
 {
 	struct virtio_device *dev = dev_to_virtio(_d);
-	return sprintf(buf, "virtio:d%08Xv%08X\n",
+	return sysfs_emit(buf, "virtio:d%08Xv%08X\n",
 		       dev->id.device, dev->id.vendor);
 }
 static DEVICE_ATTR_RO(modalias);
@@ -54,9 +54,9 @@ static ssize_t features_show(struct device *_d,
 	/* We actually represent this as a bitstring, as it could be
 	 * arbitrary length in future. */
 	for (i = 0; i < sizeof(dev->features)*8; i++)
-		len += sprintf(buf+len, "%c",
+		len += sysfs_emit_at(buf, len, "%c",
 			       __virtio_test_bit(dev, i) ? '1' : '0');
-	len += sprintf(buf+len, "\n");
+	len += sysfs_emit_at(buf, len, "\n");
 	return len;
 }
 static DEVICE_ATTR_RO(features);
-- 
GitLab


From e794070af224ade46db368271896b2685ff4f96b Mon Sep 17 00:00:00 2001
From: Cindy Lu <lulu@redhat.com>
Date: Mon, 19 Dec 2022 15:33:31 +0800
Subject: [PATCH 755/875] vhost_vdpa: fix the crash in unmap a large memory

While testing in vIOMMU, sometimes Guest will unmap very large memory,
which will cause the crash. To fix this, add a new function
vhost_vdpa_general_unmap(). This function will only unmap the memory
that saved in iotlb.

Call Trace:
[  647.820144] ------------[ cut here ]------------
[  647.820848] kernel BUG at drivers/iommu/intel/iommu.c:1174!
[  647.821486] invalid opcode: 0000 [#1] PREEMPT SMP PTI
[  647.822082] CPU: 10 PID: 1181 Comm: qemu-system-x86 Not tainted 6.0.0-rc1home_lulu_2452_lulu7_vhost+ #62
[  647.823139] Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS rel-1.15.0-29-g6a62e0cb0dfe-prebuilt.qem4
[  647.824365] RIP: 0010:domain_unmap+0x48/0x110
[  647.825424] Code: 48 89 fb 8d 4c f6 1e 39 c1 0f 4f c8 83 e9 0c 83 f9 3f 7f 18 48 89 e8 48 d3 e8 48 85 c0 75 59
[  647.828064] RSP: 0018:ffffae5340c0bbf0 EFLAGS: 00010202
[  647.828973] RAX: 0000000000000001 RBX: ffff921793d10540 RCX: 000000000000001b
[  647.830083] RDX: 00000000080000ff RSI: 0000000000000001 RDI: ffff921793d10540
[  647.831214] RBP: 0000000007fc0100 R08: ffffae5340c0bcd0 R09: 0000000000000003
[  647.832388] R10: 0000007fc0100000 R11: 0000000000100000 R12: 00000000080000ff
[  647.833668] R13: ffffae5340c0bcd0 R14: ffff921793d10590 R15: 0000008000100000
[  647.834782] FS:  00007f772ec90640(0000) GS:ffff921ce7a80000(0000) knlGS:0000000000000000
[  647.836004] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[  647.836990] CR2: 00007f02c27a3a20 CR3: 0000000101b0c006 CR4: 0000000000372ee0
[  647.838107] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[  647.839283] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
[  647.840666] Call Trace:
[  647.841437]  <TASK>
[  647.842107]  intel_iommu_unmap_pages+0x93/0x140
[  647.843112]  __iommu_unmap+0x91/0x1b0
[  647.844003]  iommu_unmap+0x6a/0x95
[  647.844885]  vhost_vdpa_unmap+0x1de/0x1f0 [vhost_vdpa]
[  647.845985]  vhost_vdpa_process_iotlb_msg+0xf0/0x90b [vhost_vdpa]
[  647.847235]  ? _raw_spin_unlock+0x15/0x30
[  647.848181]  ? _copy_from_iter+0x8c/0x580
[  647.849137]  vhost_chr_write_iter+0xb3/0x430 [vhost]
[  647.850126]  vfs_write+0x1e4/0x3a0
[  647.850897]  ksys_write+0x53/0xd0
[  647.851688]  do_syscall_64+0x3a/0x90
[  647.852508]  entry_SYSCALL_64_after_hwframe+0x63/0xcd
[  647.853457] RIP: 0033:0x7f7734ef9f4f
[  647.854408] Code: 89 54 24 18 48 89 74 24 10 89 7c 24 08 e8 29 76 f8 ff 48 8b 54 24 18 48 8b 74 24 10 41 89 c8
[  647.857217] RSP: 002b:00007f772ec8f040 EFLAGS: 00000293 ORIG_RAX: 0000000000000001
[  647.858486] RAX: ffffffffffffffda RBX: 00000000fef00000 RCX: 00007f7734ef9f4f
[  647.859713] RDX: 0000000000000048 RSI: 00007f772ec8f090 RDI: 0000000000000010
[  647.860942] RBP: 00007f772ec8f1a0 R08: 0000000000000000 R09: 0000000000000000
[  647.862206] R10: 0000000000000001 R11: 0000000000000293 R12: 0000000000000010
[  647.863446] R13: 0000000000000002 R14: 0000000000000000 R15: ffffffff01100000
[  647.864692]  </TASK>
[  647.865458] Modules linked in: rpcsec_gss_krb5 auth_rpcgss nfsv4 dns_resolver nfs lockd grace fscache netfs v]
[  647.874688] ---[ end trace 0000000000000000 ]---

Cc: stable@vger.kernel.org
Fixes: 4c8cf31885f6 ("vhost: introduce vDPA-based backend")
Signed-off-by: Cindy Lu <lulu@redhat.com>
Message-Id: <20221219073331.556140-1-lulu@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 drivers/vhost/vdpa.c | 46 +++++++++++++++++++++++++-------------------
 1 file changed, 26 insertions(+), 20 deletions(-)

diff --git a/drivers/vhost/vdpa.c b/drivers/vhost/vdpa.c
index b08e07fc7d1ff..ec32f785dfdec 100644
--- a/drivers/vhost/vdpa.c
+++ b/drivers/vhost/vdpa.c
@@ -66,8 +66,8 @@ static DEFINE_IDA(vhost_vdpa_ida);
 static dev_t vhost_vdpa_major;
 
 static void vhost_vdpa_iotlb_unmap(struct vhost_vdpa *v,
-				   struct vhost_iotlb *iotlb,
-				   u64 start, u64 last);
+				   struct vhost_iotlb *iotlb, u64 start,
+				   u64 last, u32 asid);
 
 static inline u32 iotlb_to_asid(struct vhost_iotlb *iotlb)
 {
@@ -139,7 +139,7 @@ static int vhost_vdpa_remove_as(struct vhost_vdpa *v, u32 asid)
 		return -EINVAL;
 
 	hlist_del(&as->hash_link);
-	vhost_vdpa_iotlb_unmap(v, &as->iotlb, 0ULL, 0ULL - 1);
+	vhost_vdpa_iotlb_unmap(v, &as->iotlb, 0ULL, 0ULL - 1, asid);
 	kfree(as);
 
 	return 0;
@@ -687,10 +687,20 @@ static long vhost_vdpa_unlocked_ioctl(struct file *filep,
 	mutex_unlock(&d->mutex);
 	return r;
 }
+static void vhost_vdpa_general_unmap(struct vhost_vdpa *v,
+				     struct vhost_iotlb_map *map, u32 asid)
+{
+	struct vdpa_device *vdpa = v->vdpa;
+	const struct vdpa_config_ops *ops = vdpa->config;
+	if (ops->dma_map) {
+		ops->dma_unmap(vdpa, asid, map->start, map->size);
+	} else if (ops->set_map == NULL) {
+		iommu_unmap(v->domain, map->start, map->size);
+	}
+}
 
-static void vhost_vdpa_pa_unmap(struct vhost_vdpa *v,
-				struct vhost_iotlb *iotlb,
-				u64 start, u64 last)
+static void vhost_vdpa_pa_unmap(struct vhost_vdpa *v, struct vhost_iotlb *iotlb,
+				u64 start, u64 last, u32 asid)
 {
 	struct vhost_dev *dev = &v->vdev;
 	struct vhost_iotlb_map *map;
@@ -707,13 +717,13 @@ static void vhost_vdpa_pa_unmap(struct vhost_vdpa *v,
 			unpin_user_page(page);
 		}
 		atomic64_sub(PFN_DOWN(map->size), &dev->mm->pinned_vm);
+		vhost_vdpa_general_unmap(v, map, asid);
 		vhost_iotlb_map_free(iotlb, map);
 	}
 }
 
-static void vhost_vdpa_va_unmap(struct vhost_vdpa *v,
-				struct vhost_iotlb *iotlb,
-				u64 start, u64 last)
+static void vhost_vdpa_va_unmap(struct vhost_vdpa *v, struct vhost_iotlb *iotlb,
+				u64 start, u64 last, u32 asid)
 {
 	struct vhost_iotlb_map *map;
 	struct vdpa_map_file *map_file;
@@ -722,20 +732,21 @@ static void vhost_vdpa_va_unmap(struct vhost_vdpa *v,
 		map_file = (struct vdpa_map_file *)map->opaque;
 		fput(map_file->file);
 		kfree(map_file);
+		vhost_vdpa_general_unmap(v, map, asid);
 		vhost_iotlb_map_free(iotlb, map);
 	}
 }
 
 static void vhost_vdpa_iotlb_unmap(struct vhost_vdpa *v,
-				   struct vhost_iotlb *iotlb,
-				   u64 start, u64 last)
+				   struct vhost_iotlb *iotlb, u64 start,
+				   u64 last, u32 asid)
 {
 	struct vdpa_device *vdpa = v->vdpa;
 
 	if (vdpa->use_va)
-		return vhost_vdpa_va_unmap(v, iotlb, start, last);
+		return vhost_vdpa_va_unmap(v, iotlb, start, last, asid);
 
-	return vhost_vdpa_pa_unmap(v, iotlb, start, last);
+	return vhost_vdpa_pa_unmap(v, iotlb, start, last, asid);
 }
 
 static int perm_to_iommu_flags(u32 perm)
@@ -802,17 +813,12 @@ static void vhost_vdpa_unmap(struct vhost_vdpa *v,
 	const struct vdpa_config_ops *ops = vdpa->config;
 	u32 asid = iotlb_to_asid(iotlb);
 
-	vhost_vdpa_iotlb_unmap(v, iotlb, iova, iova + size - 1);
+	vhost_vdpa_iotlb_unmap(v, iotlb, iova, iova + size - 1, asid);
 
-	if (ops->dma_map) {
-		ops->dma_unmap(vdpa, asid, iova, size);
-	} else if (ops->set_map) {
+	if (ops->set_map) {
 		if (!v->in_batch)
 			ops->set_map(vdpa, asid, iotlb);
-	} else {
-		iommu_unmap(v->domain, iova, size);
 	}
-
 	/* If we are in the middle of batch processing, delay the free
 	 * of AS until BATCH_END.
 	 */
-- 
GitLab


From 8aeac42d60936046a00e67cdf7d27b061df2962f Mon Sep 17 00:00:00 2001
From: Davidlohr Bueso <dave@stgolabs.net>
Date: Sun, 27 Nov 2022 19:43:46 -0800
Subject: [PATCH 756/875] tools/virtio: remove stray characters

__read_once_size() is not a macro, remove those '/'s.

Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Message-Id: <20221128034347.990-2-dave@stgolabs.net>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
---
 tools/virtio/ringtest/main.h | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/tools/virtio/ringtest/main.h b/tools/virtio/ringtest/main.h
index 6d1fccd3d86ce..9ed09caa659e7 100644
--- a/tools/virtio/ringtest/main.h
+++ b/tools/virtio/ringtest/main.h
@@ -149,16 +149,16 @@ static inline void busy_wait(void)
 static __always_inline
 void __read_once_size(const volatile void *p, void *res, int size)
 {
-        switch (size) {                                                 \
-        case 1: *(unsigned char *)res = *(volatile unsigned char *)p; break;              \
-        case 2: *(unsigned short *)res = *(volatile unsigned short *)p; break;            \
-        case 4: *(unsigned int *)res = *(volatile unsigned int *)p; break;            \
-        case 8: *(unsigned long long *)res = *(volatile unsigned long long *)p; break;            \
-        default:                                                        \
-                barrier();                                              \
-                __builtin_memcpy((void *)res, (const void *)p, size);   \
-                barrier();                                              \
-        }                                                               \
+	switch (size) {
+	case 1: *(unsigned char *)res = *(volatile unsigned char *)p; break;
+	case 2: *(unsigned short *)res = *(volatile unsigned short *)p; break;
+	case 4: *(unsigned int *)res = *(volatile unsigned int *)p; break;
+	case 8: *(unsigned long long *)res = *(volatile unsigned long long *)p; break;
+	default:
+		barrier();
+		__builtin_memcpy((void *)res, (const void *)p, size);
+		barrier();
+	}
 }
 
 static __always_inline void __write_once_size(volatile void *p, void *res, int size)
-- 
GitLab


From 81931012bd7dc52fadf2b720605fce8a7148d4a7 Mon Sep 17 00:00:00 2001
From: Davidlohr Bueso <dave@stgolabs.net>
Date: Sun, 27 Nov 2022 19:43:47 -0800
Subject: [PATCH 757/875] tools/virtio: remove smp_read_barrier_depends()

This gets rid of the last references to smp_read_barrier_depends()
 which for the kernel side was removed in v5.9. The serialization
required for Alpha is done inside READ_ONCE() instead of having
users deal with it. Simply use a full barrier, the architecture
does not have rmb in the first place.

Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Message-Id: <20221128034347.990-3-dave@stgolabs.net>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
---
 tools/virtio/ringtest/main.h | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/tools/virtio/ringtest/main.h b/tools/virtio/ringtest/main.h
index 9ed09caa659e7..b68920d527503 100644
--- a/tools/virtio/ringtest/main.h
+++ b/tools/virtio/ringtest/main.h
@@ -140,12 +140,6 @@ static inline void busy_wait(void)
 #define smp_wmb() smp_release()
 #endif
 
-#ifdef __alpha__
-#define smp_read_barrier_depends() smp_acquire()
-#else
-#define smp_read_barrier_depends() do {} while(0)
-#endif
-
 static __always_inline
 void __read_once_size(const volatile void *p, void *res, int size)
 {
@@ -175,13 +169,22 @@ static __always_inline void __write_once_size(volatile void *p, void *res, int s
 	}
 }
 
+#ifdef __alpha__
 #define READ_ONCE(x) \
 ({									\
 	union { typeof(x) __val; char __c[1]; } __u;			\
 	__read_once_size(&(x), __u.__c, sizeof(x));		\
-	smp_read_barrier_depends(); /* Enforce dependency ordering from x */ \
+	smp_mb(); /* Enforce dependency ordering from x */		\
 	__u.__val;							\
 })
+#else
+#define READ_ONCE(x)							\
+({									\
+	union { typeof(x) __val; char __c[1]; } __u;			\
+	__read_once_size(&(x), __u.__c, sizeof(x));			\
+	__u.__val;							\
+})
+#endif
 
 #define WRITE_ONCE(x, val) \
 ({							\
-- 
GitLab


From 937c783aa3d8d77963ec91918d3298edb45b9161 Mon Sep 17 00:00:00 2001
From: Harshit Mogalapalli <harshit.m.mogalapalli@oracle.com>
Date: Mon, 28 Nov 2022 07:57:15 -0800
Subject: [PATCH 758/875] vduse: Validate vq_num in vduse_validate_config()

Add a limit to 'config->vq_num' which is user controlled data which
comes from an vduse_ioctl to prevent large memory allocations.

Micheal says  - This limit is somewhat arbitrary.
However, currently virtio pci and ccw are limited to a 16 bit vq number.
While MMIO isn't it is also isn't used with lots of VQs due to
current lack of support for per-vq interrupts.
Thus, the 0xffff limit on number of VQs corresponding
to a 16-bit VQ number seems sufficient for now.

This is found using static analysis with smatch.

Suggested-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Harshit Mogalapalli <harshit.m.mogalapalli@oracle.com>
Message-Id: <20221128155717.2579992-1-harshit.m.mogalapalli@oracle.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
---
 drivers/vdpa/vdpa_user/vduse_dev.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/vdpa/vdpa_user/vduse_dev.c b/drivers/vdpa/vdpa_user/vduse_dev.c
index 0dd3c1f291da3..0c3b48616a9f3 100644
--- a/drivers/vdpa/vdpa_user/vduse_dev.c
+++ b/drivers/vdpa/vdpa_user/vduse_dev.c
@@ -1440,6 +1440,9 @@ static bool vduse_validate_config(struct vduse_dev_config *config)
 	if (config->config_size > PAGE_SIZE)
 		return false;
 
+	if (config->vq_num > 0xffff)
+		return false;
+
 	if (!device_is_allowed(config->device_id))
 		return false;
 
-- 
GitLab


From ed843d6ed7310a27cf7c8ee0a82a482eed0cb4a6 Mon Sep 17 00:00:00 2001
From: Rong Wang <wangrong68@huawei.com>
Date: Wed, 7 Dec 2022 20:08:13 +0800
Subject: [PATCH 759/875] vdpa/vp_vdpa: fix kfree a wrong pointer in
 vp_vdpa_remove

In vp_vdpa_remove(), the code kfree(&vp_vdpa_mgtdev->mgtdev.id_table) uses
a reference of pointer as the argument of kfree, which is the wrong pointer
and then may hit crash like this:

Unable to handle kernel paging request at virtual address 00ffff003363e30c
Internal error: Oops: 96000004 [#1] SMP
Call trace:
 rb_next+0x20/0x5c
 ext4_readdir+0x494/0x5c4 [ext4]
 iterate_dir+0x168/0x1b4
 __se_sys_getdents64+0x68/0x170
 __arm64_sys_getdents64+0x24/0x30
 el0_svc_common.constprop.0+0x7c/0x1bc
 do_el0_svc+0x2c/0x94
 el0_svc+0x20/0x30
 el0_sync_handler+0xb0/0xb4
 el0_sync+0x160/0x180
Code: 54000220 f9400441 b4000161 aa0103e0 (f9400821)
SMP: stopping secondary CPUs
Starting crashdump kernel...

Fixes: ffbda8e9df10 ("vdpa/vp_vdpa : add vdpa tool support in vp_vdpa")
Signed-off-by: Rong Wang <wangrong68@huawei.com>
Signed-off-by: Nanyong Sun <sunnanyong@huawei.com>
Message-Id: <20221207120813.2837529-1-sunnanyong@huawei.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Cindy Lu <lulu@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
---
 drivers/vdpa/virtio_pci/vp_vdpa.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/vdpa/virtio_pci/vp_vdpa.c b/drivers/vdpa/virtio_pci/vp_vdpa.c
index d448db0c4de3f..8fe267ca3e76f 100644
--- a/drivers/vdpa/virtio_pci/vp_vdpa.c
+++ b/drivers/vdpa/virtio_pci/vp_vdpa.c
@@ -647,7 +647,7 @@ static void vp_vdpa_remove(struct pci_dev *pdev)
 	mdev = vp_vdpa_mgtdev->mdev;
 	vp_modern_remove(mdev);
 	vdpa_mgmtdev_unregister(&vp_vdpa_mgtdev->mgtdev);
-	kfree(&vp_vdpa_mgtdev->mgtdev.id_table);
+	kfree(vp_vdpa_mgtdev->mgtdev.id_table);
 	kfree(mdev);
 	kfree(vp_vdpa_mgtdev);
 }
-- 
GitLab


From 1c96d5457f7251d1c62aacc04921557d56fc049a Mon Sep 17 00:00:00 2001
From: Jason Wang <jasowang@redhat.com>
Date: Wed, 7 Sep 2022 14:01:10 +0800
Subject: [PATCH 760/875] vdpa: conditionally fill max max queue pair for stats

For the device without multiqueue feature, we will read 0 as
max_virtqueue_pairs from the config. So if we fill
VDPA_ATTR_DEV_NET_CFG_MAX_VQP with the value we read from the config
we will confuse the user.

Fixing this by only filling the value when multiqueue is offered by
the device so userspace can assume 1 when the attr is not provided.

Fixes: 13b00b135665c("vdpa: Add support for querying vendor statistics")
Cc: Eli Cohen <elic@nvidia.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20220907060110.4511-1-jasowang@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Eli Cohen <elic@nvidia.com>
---
 drivers/vdpa/vdpa.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/vdpa/vdpa.c b/drivers/vdpa/vdpa.c
index 41ed56362992b..8ef7aa1365cc5 100644
--- a/drivers/vdpa/vdpa.c
+++ b/drivers/vdpa/vdpa.c
@@ -935,7 +935,6 @@ static int vdpa_fill_stats_rec(struct vdpa_device *vdev, struct sk_buff *msg,
 {
 	struct virtio_net_config config = {};
 	u64 features;
-	u16 max_vqp;
 	u8 status;
 	int err;
 
@@ -946,15 +945,15 @@ static int vdpa_fill_stats_rec(struct vdpa_device *vdev, struct sk_buff *msg,
 	}
 	vdpa_get_config_unlocked(vdev, 0, &config, sizeof(config));
 
-	max_vqp = __virtio16_to_cpu(true, config.max_virtqueue_pairs);
-	if (nla_put_u16(msg, VDPA_ATTR_DEV_NET_CFG_MAX_VQP, max_vqp))
-		return -EMSGSIZE;
-
 	features = vdev->config->get_driver_features(vdev);
 	if (nla_put_u64_64bit(msg, VDPA_ATTR_DEV_NEGOTIATED_FEATURES,
 			      features, VDPA_ATTR_PAD))
 		return -EMSGSIZE;
 
+	err = vdpa_dev_net_mq_config_fill(msg, features, &config);
+	if (err)
+		return err;
+
 	if (nla_put_u32(msg, VDPA_ATTR_DEV_QUEUE_INDEX, index))
 		return -EMSGSIZE;
 
-- 
GitLab


From 0b7a04a30eef20e6b24926a45c0ce7906ae85bd6 Mon Sep 17 00:00:00 2001
From: Jason Wang <jasowang@redhat.com>
Date: Tue, 13 Dec 2022 17:07:17 +0800
Subject: [PATCH 761/875] vdpasim: fix memory leak when freeing IOTLBs

After commit bda324fd037a ("vdpasim: control virtqueue support"),
vdpasim->iommu became an array of IOTLB, so we should clean the
mappings of each free one by one instead of just deleting the ranges
in the first IOTLB which may leak maps.

Fixes: bda324fd037a ("vdpasim: control virtqueue support")
Cc: Gautam Dawar <gautam.dawar@xilinx.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20221213090717.61529-1-jasowang@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Gautam Dawar <gautam.dawar@amd.com>
---
 drivers/vdpa/vdpa_sim/vdpa_sim.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/vdpa/vdpa_sim/vdpa_sim.c b/drivers/vdpa/vdpa_sim/vdpa_sim.c
index b20689f8fe89c..cb88891b44a8c 100644
--- a/drivers/vdpa/vdpa_sim/vdpa_sim.c
+++ b/drivers/vdpa/vdpa_sim/vdpa_sim.c
@@ -689,7 +689,9 @@ static void vdpasim_free(struct vdpa_device *vdpa)
 	}
 
 	kvfree(vdpasim->buffer);
-	vhost_iotlb_free(vdpasim->iommu);
+	for (i = 0; i < vdpasim->dev_attr.nas; i++)
+		vhost_iotlb_reset(&vdpasim->iommu[i]);
+	kfree(vdpasim->iommu);
 	kfree(vdpasim->vqs);
 	kfree(vdpasim->config);
 }
-- 
GitLab


From 72455a1142527e607e1d69439f3ffa2ef6d09e26 Mon Sep 17 00:00:00 2001
From: Cindy Lu <lulu@redhat.com>
Date: Wed, 14 Dec 2022 13:43:06 +0800
Subject: [PATCH 762/875] vdpa_sim_net: should not drop the multicast/broadcast
 packet

In the receive_filter(), should not drop the packet with the
broadcast/multicast address. Add the check for this

Signed-off-by: Cindy Lu <lulu@redhat.com>
Message-Id: <20221214054306.24145-1-lulu@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
---
 drivers/vdpa/vdpa_sim/vdpa_sim_net.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/vdpa/vdpa_sim/vdpa_sim_net.c b/drivers/vdpa/vdpa_sim/vdpa_sim_net.c
index 11f5a121df243..584b975a98a7e 100644
--- a/drivers/vdpa/vdpa_sim/vdpa_sim_net.c
+++ b/drivers/vdpa/vdpa_sim/vdpa_sim_net.c
@@ -62,6 +62,9 @@ static bool receive_filter(struct vdpasim *vdpasim, size_t len)
 	if (len < ETH_ALEN + hdr_len)
 		return false;
 
+	if (is_broadcast_ether_addr(vdpasim->buffer + hdr_len) ||
+	    is_multicast_ether_addr(vdpasim->buffer + hdr_len))
+		return true;
 	if (!strncmp(vdpasim->buffer + hdr_len, vio_config->mac, ETH_ALEN))
 		return true;
 
-- 
GitLab


From a26116c1e74028914f281851488546c91cbae57d Mon Sep 17 00:00:00 2001
From: Rafael Mendonca <rafaelmendsr@gmail.com>
Date: Fri, 21 Oct 2022 17:41:26 -0300
Subject: [PATCH 763/875] virtio_blk: Fix signedness bug in virtblk_prep_rq()

The virtblk_map_data() function returns negative error codes, however, the
'nents' field of vbr->sg_table is an unsigned int, which causes the error
handling not to work correctly.

Cc: stable@vger.kernel.org
Fixes: 0e9911fa768f ("virtio-blk: support mq_ops->queue_rqs()")
Signed-off-by: Rafael Mendonca <rafaelmendsr@gmail.com>
Message-Id: <20221021204126.927603-1-rafaelmendsr@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Reviewed-by: Suwan Kim <suwan.kim027@gmail.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
---
 drivers/block/virtio_blk.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/block/virtio_blk.c b/drivers/block/virtio_blk.c
index dcbf86cd2155e..6a77fa9174288 100644
--- a/drivers/block/virtio_blk.c
+++ b/drivers/block/virtio_blk.c
@@ -334,14 +334,16 @@ static blk_status_t virtblk_prep_rq(struct blk_mq_hw_ctx *hctx,
 					struct virtblk_req *vbr)
 {
 	blk_status_t status;
+	int num;
 
 	status = virtblk_setup_cmd(vblk->vdev, req, vbr);
 	if (unlikely(status))
 		return status;
 
-	vbr->sg_table.nents = virtblk_map_data(hctx, req, vbr);
-	if (unlikely(vbr->sg_table.nents < 0))
+	num = virtblk_map_data(hctx, req, vbr);
+	if (unlikely(num < 0))
 		return virtblk_fail_to_queue(req, -ENOMEM);
+	vbr->sg_table.nents = num;
 
 	blk_mq_start_request(req);
 
-- 
GitLab


From a79b53aaaab53de017517bf9579b6106397a523c Mon Sep 17 00:00:00 2001
From: Paolo Bonzini <pbonzini@redhat.com>
Date: Wed, 28 Dec 2022 05:33:41 -0500
Subject: [PATCH 764/875] KVM: x86: fix deadlock for KVM_XEN_EVTCHN_RESET

While KVM_XEN_EVTCHN_RESET is usually called with no vCPUs running,
if that happened it could cause a deadlock.  This is due to
kvm_xen_eventfd_reset() doing a synchronize_srcu() inside
a kvm->lock critical section.

To avoid this, first collect all the evtchnfd objects in an
array and free all of them once the kvm->lock critical section
is over and th SRCU grace period has expired.

Reported-by: Michal Luczaj <mhal@rbox.co>
Cc: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/xen.c                            | 30 +++++++++++++++++--
 .../selftests/kvm/x86_64/xen_shinfo_test.c    |  6 ++++
 2 files changed, 33 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kvm/xen.c b/arch/x86/kvm/xen.c
index b178f40bd863c..2e29bdc2949ca 100644
--- a/arch/x86/kvm/xen.c
+++ b/arch/x86/kvm/xen.c
@@ -1942,18 +1942,42 @@ static int kvm_xen_eventfd_deassign(struct kvm *kvm, u32 port)
 
 static int kvm_xen_eventfd_reset(struct kvm *kvm)
 {
-	struct evtchnfd *evtchnfd;
+	struct evtchnfd *evtchnfd, **all_evtchnfds;
 	int i;
+	int n = 0;
 
 	mutex_lock(&kvm->lock);
+
+	/*
+	 * Because synchronize_srcu() cannot be called inside the
+	 * critical section, first collect all the evtchnfd objects
+	 * in an array as they are removed from evtchn_ports.
+	 */
+	idr_for_each_entry(&kvm->arch.xen.evtchn_ports, evtchnfd, i)
+		n++;
+
+	all_evtchnfds = kmalloc_array(n, sizeof(struct evtchnfd *), GFP_KERNEL);
+	if (!all_evtchnfds) {
+		mutex_unlock(&kvm->lock);
+		return -ENOMEM;
+	}
+
+	n = 0;
 	idr_for_each_entry(&kvm->arch.xen.evtchn_ports, evtchnfd, i) {
+		all_evtchnfds[n++] = evtchnfd;
 		idr_remove(&kvm->arch.xen.evtchn_ports, evtchnfd->send_port);
-		synchronize_srcu(&kvm->srcu);
+	}
+	mutex_unlock(&kvm->lock);
+
+	synchronize_srcu(&kvm->srcu);
+
+	while (n--) {
+		evtchnfd = all_evtchnfds[n];
 		if (!evtchnfd->deliver.port.port)
 			eventfd_ctx_put(evtchnfd->deliver.eventfd.ctx);
 		kfree(evtchnfd);
 	}
-	mutex_unlock(&kvm->lock);
+	kfree(all_evtchnfds);
 
 	return 0;
 }
diff --git a/tools/testing/selftests/kvm/x86_64/xen_shinfo_test.c b/tools/testing/selftests/kvm/x86_64/xen_shinfo_test.c
index 721f6a693799b..dae510c263b45 100644
--- a/tools/testing/selftests/kvm/x86_64/xen_shinfo_test.c
+++ b/tools/testing/selftests/kvm/x86_64/xen_shinfo_test.c
@@ -962,6 +962,12 @@ int main(int argc, char *argv[])
 	}
 
  done:
+	struct kvm_xen_hvm_attr evt_reset = {
+		.type = KVM_XEN_ATTR_TYPE_EVTCHN,
+		.u.evtchn.flags = KVM_XEN_EVTCHN_RESET,
+	};
+	vm_ioctl(vm, KVM_XEN_HVM_SET_ATTR, &evt_reset);
+
 	alarm(0);
 	clock_gettime(CLOCK_REALTIME, &max_ts);
 
-- 
GitLab


From 02d9a04da453984b16f4a585ad808cf961df495e Mon Sep 17 00:00:00 2001
From: Paolo Bonzini <pbonzini@redhat.com>
Date: Wed, 28 Dec 2022 06:00:22 -0500
Subject: [PATCH 765/875] Documentation: kvm: clarify SRCU locking order

Currently only the locking order of SRCU vs kvm->slots_arch_lock
and kvm->slots_lock is documented.  Extend this to kvm->lock
since Xen emulation got it terribly wrong.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 Documentation/virt/kvm/locking.rst | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/Documentation/virt/kvm/locking.rst b/Documentation/virt/kvm/locking.rst
index 845a561629f19..a3ca76f9be751 100644
--- a/Documentation/virt/kvm/locking.rst
+++ b/Documentation/virt/kvm/locking.rst
@@ -16,17 +16,26 @@ The acquisition orders for mutexes are as follows:
 - kvm->slots_lock is taken outside kvm->irq_lock, though acquiring
   them together is quite rare.
 
-- Unlike kvm->slots_lock, kvm->slots_arch_lock is released before
-  synchronize_srcu(&kvm->srcu).  Therefore kvm->slots_arch_lock
-  can be taken inside a kvm->srcu read-side critical section,
-  while kvm->slots_lock cannot.
-
 - kvm->mn_active_invalidate_count ensures that pairs of
   invalidate_range_start() and invalidate_range_end() callbacks
   use the same memslots array.  kvm->slots_lock and kvm->slots_arch_lock
   are taken on the waiting side in install_new_memslots, so MMU notifiers
   must not take either kvm->slots_lock or kvm->slots_arch_lock.
 
+For SRCU:
+
+- ``synchronize_srcu(&kvm->srcu)`` is called _inside_
+  the kvm->slots_lock critical section, therefore kvm->slots_lock
+  cannot be taken inside a kvm->srcu read-side critical section.
+  Instead, kvm->slots_arch_lock is released before the call
+  to ``synchronize_srcu()`` and _can_ be taken inside a
+  kvm->srcu read-side critical section.
+
+- kvm->lock is taken inside kvm->srcu, therefore
+  ``synchronize_srcu(&kvm->srcu)`` cannot be called inside
+  a kvm->lock critical section.  If you cannot delay the
+  call until after kvm->lock is released, use ``call_srcu``.
+
 On x86:
 
 - vcpu->mutex is taken outside kvm->arch.hyperv.hv_lock
-- 
GitLab


From 9deb1e9fb88b1120a908676fa33bdf9e2eeaefce Mon Sep 17 00:00:00 2001
From: Daniil Tatianin <d-tatianin@yandex-team.ru>
Date: Mon, 26 Dec 2022 14:48:23 +0300
Subject: [PATCH 766/875] net/ethtool/ioctl: return -EOPNOTSUPP if we have no
 phy stats

It's not very useful to copy back an empty ethtool_stats struct and
return 0 if we didn't actually have any stats. This also allows for
further simplification of this function in the future commits.

Signed-off-by: Daniil Tatianin <d-tatianin@yandex-team.ru>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/ethtool/ioctl.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/net/ethtool/ioctl.c b/net/ethtool/ioctl.c
index c2f1a542e6fa9..932fa8225b2f3 100644
--- a/net/ethtool/ioctl.c
+++ b/net/ethtool/ioctl.c
@@ -2099,7 +2099,8 @@ static int ethtool_get_phy_stats(struct net_device *dev, void __user *useraddr)
 		return n_stats;
 	if (n_stats > S32_MAX / sizeof(u64))
 		return -ENOMEM;
-	WARN_ON_ONCE(!n_stats);
+	if (WARN_ON_ONCE(!n_stats))
+		return -EOPNOTSUPP;
 
 	if (copy_from_user(&stats, useraddr, sizeof(stats)))
 		return -EFAULT;
-- 
GitLab


From fd4778581d61d8848b532f8cdc9b325138748437 Mon Sep 17 00:00:00 2001
From: Daniil Tatianin <d-tatianin@yandex-team.ru>
Date: Mon, 26 Dec 2022 14:48:24 +0300
Subject: [PATCH 767/875] net/ethtool/ioctl: remove if n_stats checks from
 ethtool_get_phy_stats

Now that we always early return if we don't have any stats we can remove
these checks as they're no longer necessary.

Signed-off-by: Daniil Tatianin <d-tatianin@yandex-team.ru>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/ethtool/ioctl.c | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/net/ethtool/ioctl.c b/net/ethtool/ioctl.c
index 932fa8225b2f3..85f0cffdcec8a 100644
--- a/net/ethtool/ioctl.c
+++ b/net/ethtool/ioctl.c
@@ -2107,28 +2107,24 @@ static int ethtool_get_phy_stats(struct net_device *dev, void __user *useraddr)
 
 	stats.n_stats = n_stats;
 
-	if (n_stats) {
-		data = vzalloc(array_size(n_stats, sizeof(u64)));
-		if (!data)
-			return -ENOMEM;
+	data = vzalloc(array_size(n_stats, sizeof(u64)));
+	if (!data)
+		return -ENOMEM;
 
-		if (phydev && !ops->get_ethtool_phy_stats &&
-		    phy_ops && phy_ops->get_stats) {
-			ret = phy_ops->get_stats(phydev, &stats, data);
-			if (ret < 0)
-				goto out;
-		} else {
-			ops->get_ethtool_phy_stats(dev, &stats, data);
-		}
+	if (phydev && !ops->get_ethtool_phy_stats &&
+		phy_ops && phy_ops->get_stats) {
+		ret = phy_ops->get_stats(phydev, &stats, data);
+		if (ret < 0)
+			goto out;
 	} else {
-		data = NULL;
+		ops->get_ethtool_phy_stats(dev, &stats, data);
 	}
 
 	ret = -EFAULT;
 	if (copy_to_user(useraddr, &stats, sizeof(stats)))
 		goto out;
 	useraddr += sizeof(stats);
-	if (n_stats && copy_to_user(useraddr, data, array_size(n_stats, sizeof(u64))))
+	if (copy_to_user(useraddr, data, array_size(n_stats, sizeof(u64))))
 		goto out;
 	ret = 0;
 
-- 
GitLab


From 201ed315f9676809cd5b20a39206e964106d4f27 Mon Sep 17 00:00:00 2001
From: Daniil Tatianin <d-tatianin@yandex-team.ru>
Date: Mon, 26 Dec 2022 14:48:25 +0300
Subject: [PATCH 768/875] net/ethtool/ioctl: split ethtool_get_phy_stats into
 multiple helpers

So that it's easier to follow and make sense of the branching and
various conditions.

Stats retrieval has been split into two separate functions
ethtool_get_phy_stats_phydev & ethtool_get_phy_stats_ethtool.
The former attempts to retrieve the stats using phydev & phy_ops, while
the latter uses ethtool_ops.

Actual n_stats validation & array allocation has been moved into a new
ethtool_vzalloc_stats_array helper.

This also fixes a potential NULL dereference of
ops->get_ethtool_phy_stats where it was getting called in an else branch
unconditionally without making sure it was actually present.

Found by Linux Verification Center (linuxtesting.org) with the SVACE
static analysis tool.

Signed-off-by: Daniil Tatianin <d-tatianin@yandex-team.ru>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/ethtool/ioctl.c | 102 ++++++++++++++++++++++++++++++--------------
 1 file changed, 69 insertions(+), 33 deletions(-)

diff --git a/net/ethtool/ioctl.c b/net/ethtool/ioctl.c
index 85f0cffdcec8a..646b3e490c71a 100644
--- a/net/ethtool/ioctl.c
+++ b/net/ethtool/ioctl.c
@@ -2078,23 +2078,8 @@ static int ethtool_get_stats(struct net_device *dev, void __user *useraddr)
 	return ret;
 }
 
-static int ethtool_get_phy_stats(struct net_device *dev, void __user *useraddr)
+static int ethtool_vzalloc_stats_array(int n_stats, u64 **data)
 {
-	const struct ethtool_phy_ops *phy_ops = ethtool_phy_ops;
-	const struct ethtool_ops *ops = dev->ethtool_ops;
-	struct phy_device *phydev = dev->phydev;
-	struct ethtool_stats stats;
-	u64 *data;
-	int ret, n_stats;
-
-	if (!phydev && (!ops->get_ethtool_phy_stats || !ops->get_sset_count))
-		return -EOPNOTSUPP;
-
-	if (phydev && !ops->get_ethtool_phy_stats &&
-	    phy_ops && phy_ops->get_sset_count)
-		n_stats = phy_ops->get_sset_count(phydev);
-	else
-		n_stats = ops->get_sset_count(dev, ETH_SS_PHY_STATS);
 	if (n_stats < 0)
 		return n_stats;
 	if (n_stats > S32_MAX / sizeof(u64))
@@ -2102,31 +2087,82 @@ static int ethtool_get_phy_stats(struct net_device *dev, void __user *useraddr)
 	if (WARN_ON_ONCE(!n_stats))
 		return -EOPNOTSUPP;
 
+	*data = vzalloc(array_size(n_stats, sizeof(u64)));
+	if (!*data)
+		return -ENOMEM;
+
+	return 0;
+}
+
+static int ethtool_get_phy_stats_phydev(struct phy_device *phydev,
+					 struct ethtool_stats *stats,
+					 u64 **data)
+ {
+	const struct ethtool_phy_ops *phy_ops = ethtool_phy_ops;
+	int n_stats, ret;
+
+	if (!phy_ops || !phy_ops->get_sset_count || !phy_ops->get_stats)
+		return -EOPNOTSUPP;
+
+	n_stats = phy_ops->get_sset_count(phydev);
+
+	ret = ethtool_vzalloc_stats_array(n_stats, data);
+	if (ret)
+		return ret;
+
+	stats->n_stats = n_stats;
+	return phy_ops->get_stats(phydev, stats, *data);
+}
+
+static int ethtool_get_phy_stats_ethtool(struct net_device *dev,
+					  struct ethtool_stats *stats,
+					  u64 **data)
+{
+	const struct ethtool_ops *ops = dev->ethtool_ops;
+	int n_stats, ret;
+
+	if (!ops || !ops->get_sset_count || ops->get_ethtool_phy_stats)
+		return -EOPNOTSUPP;
+
+	n_stats = ops->get_sset_count(dev, ETH_SS_PHY_STATS);
+
+	ret = ethtool_vzalloc_stats_array(n_stats, data);
+	if (ret)
+		return ret;
+
+	stats->n_stats = n_stats;
+	ops->get_ethtool_phy_stats(dev, stats, *data);
+
+	return 0;
+}
+
+static int ethtool_get_phy_stats(struct net_device *dev, void __user *useraddr)
+{
+	struct phy_device *phydev = dev->phydev;
+	struct ethtool_stats stats;
+	u64 *data = NULL;
+	int ret = -EOPNOTSUPP;
+
 	if (copy_from_user(&stats, useraddr, sizeof(stats)))
 		return -EFAULT;
 
-	stats.n_stats = n_stats;
+	if (phydev)
+		ret = ethtool_get_phy_stats_phydev(phydev, &stats, &data);
 
-	data = vzalloc(array_size(n_stats, sizeof(u64)));
-	if (!data)
-		return -ENOMEM;
+	if (ret == -EOPNOTSUPP)
+		ret = ethtool_get_phy_stats_ethtool(dev, &stats, &data);
 
-	if (phydev && !ops->get_ethtool_phy_stats &&
-		phy_ops && phy_ops->get_stats) {
-		ret = phy_ops->get_stats(phydev, &stats, data);
-		if (ret < 0)
-			goto out;
-	} else {
-		ops->get_ethtool_phy_stats(dev, &stats, data);
-	}
+	if (ret)
+		goto out;
 
-	ret = -EFAULT;
-	if (copy_to_user(useraddr, &stats, sizeof(stats)))
+	if (copy_to_user(useraddr, &stats, sizeof(stats))) {
+		ret = -EFAULT;
 		goto out;
+	}
+
 	useraddr += sizeof(stats);
-	if (copy_to_user(useraddr, data, array_size(n_stats, sizeof(u64))))
-		goto out;
-	ret = 0;
+	if (copy_to_user(useraddr, data, array_size(stats.n_stats, sizeof(u64))))
+		ret = -EFAULT;
 
  out:
 	vfree(data);
-- 
GitLab


From ad425666a1f05d9b215a84cf010c3789b2ea8206 Mon Sep 17 00:00:00 2001
From: Chunhao Lin <hau@realtek.com>
Date: Mon, 26 Dec 2022 20:31:52 +0800
Subject: [PATCH 769/875] r8169: move rtl_wol_enable_rx() and
 rtl_prepare_power_down()

There is no functional change. Moving these two functions for following
patch "r8169: fix dmar pte write access is not set error".

Signed-off-by: Chunhao Lin <hau@realtek.com>
Reviewed-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/realtek/r8169_main.c | 44 +++++++++++------------
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c
index a9dcc98b6af18..acc2500342cab 100644
--- a/drivers/net/ethernet/realtek/r8169_main.c
+++ b/drivers/net/ethernet/realtek/r8169_main.c
@@ -2210,28 +2210,6 @@ static int rtl_set_mac_address(struct net_device *dev, void *p)
 	return 0;
 }
 
-static void rtl_wol_enable_rx(struct rtl8169_private *tp)
-{
-	if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
-		RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
-			AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
-}
-
-static void rtl_prepare_power_down(struct rtl8169_private *tp)
-{
-	if (tp->dash_type != RTL_DASH_NONE)
-		return;
-
-	if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
-	    tp->mac_version == RTL_GIGA_MAC_VER_33)
-		rtl_ephy_write(tp, 0x19, 0xff64);
-
-	if (device_may_wakeup(tp_to_dev(tp))) {
-		phy_speed_down(tp->phydev, false);
-		rtl_wol_enable_rx(tp);
-	}
-}
-
 static void rtl_init_rxcfg(struct rtl8169_private *tp)
 {
 	switch (tp->mac_version) {
@@ -2455,6 +2433,28 @@ static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
 	rtl_wait_txrx_fifo_empty(tp);
 }
 
+static void rtl_wol_enable_rx(struct rtl8169_private *tp)
+{
+	if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
+		RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
+			AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
+}
+
+static void rtl_prepare_power_down(struct rtl8169_private *tp)
+{
+	if (tp->dash_type != RTL_DASH_NONE)
+		return;
+
+	if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
+	    tp->mac_version == RTL_GIGA_MAC_VER_33)
+		rtl_ephy_write(tp, 0x19, 0xff64);
+
+	if (device_may_wakeup(tp_to_dev(tp))) {
+		phy_speed_down(tp->phydev, false);
+		rtl_wol_enable_rx(tp);
+	}
+}
+
 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
 {
 	u32 val = TX_DMA_BURST << TxDMAShift |
-- 
GitLab


From bb41c13c05c23d9bc46b4e37d8914078c6a40e3a Mon Sep 17 00:00:00 2001
From: Chunhao Lin <hau@realtek.com>
Date: Mon, 26 Dec 2022 20:31:53 +0800
Subject: [PATCH 770/875] r8169: fix dmar pte write access is not set error

When close device, if wol is enabled, rx will be enabled. When open
device it will cause rx packet to be dma to the wrong memory address
after pci_set_master() and system log will show blow messages.

DMAR: DRHD: handling fault status reg 3
DMAR: [DMA Write] Request device [02:00.0] PASID ffffffff fault addr
ffdd4000 [fault reason 05] PTE Write access is not set

In this patch, driver disable tx/rx when close device. If wol is
enabled, only enable rx filter and disable rxdv_gate(if support) to
let hardware only receive packet to fifo but not to dma it.

Signed-off-by: Chunhao Lin <hau@realtek.com>
Reviewed-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/realtek/r8169_main.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c
index acc2500342cab..24592d9725230 100644
--- a/drivers/net/ethernet/realtek/r8169_main.c
+++ b/drivers/net/ethernet/realtek/r8169_main.c
@@ -2438,6 +2438,9 @@ static void rtl_wol_enable_rx(struct rtl8169_private *tp)
 	if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
 		RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
 			AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
+
+	if (tp->mac_version >= RTL_GIGA_MAC_VER_40)
+		rtl_disable_rxdvgate(tp);
 }
 
 static void rtl_prepare_power_down(struct rtl8169_private *tp)
@@ -3872,7 +3875,7 @@ static void rtl8169_tx_clear(struct rtl8169_private *tp)
 	netdev_reset_queue(tp->dev);
 }
 
-static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)
+static void rtl8169_cleanup(struct rtl8169_private *tp)
 {
 	napi_disable(&tp->napi);
 
@@ -3884,9 +3887,6 @@ static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)
 
 	rtl_rx_close(tp);
 
-	if (going_down && tp->dev->wol_enabled)
-		goto no_reset;
-
 	switch (tp->mac_version) {
 	case RTL_GIGA_MAC_VER_28:
 	case RTL_GIGA_MAC_VER_31:
@@ -3907,7 +3907,7 @@ static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)
 	}
 
 	rtl_hw_reset(tp);
-no_reset:
+
 	rtl8169_tx_clear(tp);
 	rtl8169_init_ring_indexes(tp);
 }
@@ -3918,7 +3918,7 @@ static void rtl_reset_work(struct rtl8169_private *tp)
 
 	netif_stop_queue(tp->dev);
 
-	rtl8169_cleanup(tp, false);
+	rtl8169_cleanup(tp);
 
 	for (i = 0; i < NUM_RX_DESC; i++)
 		rtl8169_mark_to_asic(tp->RxDescArray + i);
@@ -4605,7 +4605,7 @@ static void rtl8169_down(struct rtl8169_private *tp)
 	pci_clear_master(tp->pci_dev);
 	rtl_pci_commit(tp);
 
-	rtl8169_cleanup(tp, true);
+	rtl8169_cleanup(tp);
 	rtl_disable_exit_l1(tp);
 	rtl_prepare_power_down(tp);
 }
-- 
GitLab


From c2052189f19bd98c80b5d46dc6e42330d2b3b35d Mon Sep 17 00:00:00 2001
From: Xuezhi Zhang <zhangxuezhi1@coolpad.com>
Date: Tue, 27 Dec 2022 19:03:52 +0800
Subject: [PATCH 771/875] s390/qeth: convert sysfs snprintf to sysfs_emit

Follow the advice of the Documentation/filesystems/sysfs.rst
and show() should only use sysfs_emit() or sysfs_emit_at()
when formatting the value to be returned to user space.

Signed-off-by: Xuezhi Zhang <zhangxuezhi1@coolpad.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/s390/net/qeth_core_sys.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/s390/net/qeth_core_sys.c b/drivers/s390/net/qeth_core_sys.c
index 406be169173ce..d1adc4b831936 100644
--- a/drivers/s390/net/qeth_core_sys.c
+++ b/drivers/s390/net/qeth_core_sys.c
@@ -410,13 +410,13 @@ static ssize_t qeth_dev_isolation_show(struct device *dev,
 
 	switch (card->options.isolation) {
 	case ISOLATION_MODE_NONE:
-		return snprintf(buf, 6, "%s\n", ATTR_QETH_ISOLATION_NONE);
+		return sysfs_emit(buf, "%s\n", ATTR_QETH_ISOLATION_NONE);
 	case ISOLATION_MODE_FWD:
-		return snprintf(buf, 9, "%s\n", ATTR_QETH_ISOLATION_FWD);
+		return sysfs_emit(buf, "%s\n", ATTR_QETH_ISOLATION_FWD);
 	case ISOLATION_MODE_DROP:
-		return snprintf(buf, 6, "%s\n", ATTR_QETH_ISOLATION_DROP);
+		return sysfs_emit(buf, "%s\n", ATTR_QETH_ISOLATION_DROP);
 	default:
-		return snprintf(buf, 5, "%s\n", "N/A");
+		return sysfs_emit(buf, "%s\n", "N/A");
 	}
 }
 
@@ -500,9 +500,9 @@ static ssize_t qeth_hw_trap_show(struct device *dev,
 	struct qeth_card *card = dev_get_drvdata(dev);
 
 	if (card->info.hwtrap)
-		return snprintf(buf, 5, "arm\n");
+		return sysfs_emit(buf, "arm\n");
 	else
-		return snprintf(buf, 8, "disarm\n");
+		return sysfs_emit(buf, "disarm\n");
 }
 
 static ssize_t qeth_hw_trap_store(struct device *dev,
-- 
GitLab


From 40cab44b9089a41f71bbd0eff753eb91d5dafd68 Mon Sep 17 00:00:00 2001
From: Pedro Tammela <pctammela@mojatatu.com>
Date: Tue, 27 Dec 2022 11:04:59 -0300
Subject: [PATCH 772/875] net/sched: fix retpoline wrapper compilation on
 configs without tc filters

Rudi reports a compilation failure on x86_64 when CONFIG_NET_CLS or
CONFIG_NET_CLS_ACT is not set but CONFIG_RETPOLINE is set.
A misplaced '#endif' was causing the issue.

Fixes: 7f0e810220e2 ("net/sched: add retpoline wrapper for tc")

Tested-by: Rudi Heitbaum <rudi@heitbaum.com>
Signed-off-by: Pedro Tammela <pctammela@mojatatu.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 include/net/tc_wrapper.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/net/tc_wrapper.h b/include/net/tc_wrapper.h
index ceed2fc089ffa..d323fffb839aa 100644
--- a/include/net/tc_wrapper.h
+++ b/include/net/tc_wrapper.h
@@ -216,6 +216,8 @@ skip:
 	return tp->classify(skb, tp, res);
 }
 
+#endif /* CONFIG_NET_CLS */
+
 static inline void tc_wrapper_init(void)
 {
 #ifdef CONFIG_X86
@@ -224,8 +226,6 @@ static inline void tc_wrapper_init(void)
 #endif
 }
 
-#endif /* CONFIG_NET_CLS */
-
 #else
 
 #define TC_INDIRECT_SCOPE static
-- 
GitLab


From 129c48cde6c9e519d033305649665427c6cac494 Mon Sep 17 00:00:00 2001
From: Paolo Bonzini <pbonzini@redhat.com>
Date: Wed, 30 Nov 2022 13:11:47 -0500
Subject: [PATCH 773/875] KVM: selftests: restore special vmmcall code layout
 needed by the harness

Commit 8fda37cf3d41 ("KVM: selftests: Stuff RAX/RCX with 'safe' values
in vmmcall()/vmcall()", 2022-11-21) broke the svm_nested_soft_inject_test
because it placed a "pop rbp" instruction after vmmcall.  While this is
correct and mimics what is done in the VMX case, this particular test
expects a ud2 instruction right after the vmmcall, so that it can skip
over it in the L1 part of the test.

Inline a suitably-modified version of vmmcall() to restore the
functionality of the test.

Fixes: 8fda37cf3d41 ("KVM: selftests: Stuff RAX/RCX with 'safe' values in vmmcall()/vmcall()"
Cc: Vitaly Kuznetsov <vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Sean Christopherson <seanjc@google.com>
Reviewed-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
Message-Id: <20221130181147.9911-1-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 .../kvm/x86_64/svm_nested_soft_inject_test.c        | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/tools/testing/selftests/kvm/x86_64/svm_nested_soft_inject_test.c b/tools/testing/selftests/kvm/x86_64/svm_nested_soft_inject_test.c
index e497ace629c19..b34980d45648a 100644
--- a/tools/testing/selftests/kvm/x86_64/svm_nested_soft_inject_test.c
+++ b/tools/testing/selftests/kvm/x86_64/svm_nested_soft_inject_test.c
@@ -41,8 +41,17 @@ static void guest_int_handler(struct ex_regs *regs)
 static void l2_guest_code_int(void)
 {
 	GUEST_ASSERT_1(int_fired == 1, int_fired);
-	vmmcall();
-	ud2();
+
+	/*
+         * Same as the vmmcall() function, but with a ud2 sneaked after the
+         * vmmcall.  The caller injects an exception with the return address
+         * increased by 2, so the "pop rbp" must be after the ud2 and we cannot
+	 * use vmmcall() directly.
+         */
+	__asm__ __volatile__("push %%rbp; vmmcall; ud2; pop %%rbp"
+                             : : "a"(0xdeadbeef), "c"(0xbeefdead)
+                             : "rbx", "rdx", "rsi", "rdi", "r8", "r9",
+                               "r10", "r11", "r12", "r13", "r14", "r15");
 
 	GUEST_ASSERT_1(bp_fired == 1, bp_fired);
 	hlt();
-- 
GitLab


From 090ddad4c7a9fefd647c762093a555870a19c8b2 Mon Sep 17 00:00:00 2001
From: Takashi Iwai <tiwai@suse.de>
Date: Wed, 28 Dec 2022 13:57:14 +0100
Subject: [PATCH 774/875] ALSA: hda/hdmi: Static PCM mapping again with AMD
 HDMI codecs

The recent code refactoring for HD-audio HDMI codec driver caused a
regression on AMD/ATI HDMI codecs; namely, PulseAudioand pipewire
don't recognize HDMI outputs any longer while the direct output via
ALSA raw access still works.

The problem turned out that, after the code refactoring, the driver
assumes only the dynamic PCM assignment, and when a PCM stream that
still isn't assigned to any pin gets opened, the driver tries to
assign any free converter to the PCM stream.  This behavior is OK for
Intel and other codecs, as they have arbitrary connections between
pins and converters.  OTOH, on AMD chips that have a 1:1 mapping
between pins and converters, this may end up with blocking the open of
the next PCM stream for the pin that is tied with the formerly taken
converter.

Also, with the code refactoring, more PCM streams are exposed than
necessary as we assume all converters can be used, while this isn't
true for AMD case.  This may change the PCM stream assignment and
confuse users as well.

This patch fixes those problems by:

- Introducing a flag spec->static_pcm_mapping, and if it's set, the
  driver applies the static mapping between pins and converters at the
  probe time
- Limiting the number of PCM streams per pins, too; this avoids the
  superfluous PCM streams

Fixes: ef6f5494faf6 ("ALSA: hda/hdmi: Use only dynamic PCM device allocation")
Cc: <stable@vger.kernel.org>
Link: https://bugzilla.kernel.org/show_bug.cgi?id=216836
Co-developed-by: Jaroslav Kysela <perex@perex.cz>
Signed-off-by: Jaroslav Kysela <perex@perex.cz>
Link: https://lore.kernel.org/r/20221228125714.16329-1-tiwai@suse.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
 sound/pci/hda/patch_hdmi.c | 27 +++++++++++++++++++--------
 1 file changed, 19 insertions(+), 8 deletions(-)

diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
index 8015e44712678..386dd9d9143f9 100644
--- a/sound/pci/hda/patch_hdmi.c
+++ b/sound/pci/hda/patch_hdmi.c
@@ -167,6 +167,7 @@ struct hdmi_spec {
 	struct hdmi_ops ops;
 
 	bool dyn_pin_out;
+	bool static_pcm_mapping;
 	/* hdmi interrupt trigger control flag for Nvidia codec */
 	bool hdmi_intr_trig_ctrl;
 	bool nv_dp_workaround; /* workaround DP audio infoframe for Nvidia */
@@ -1525,13 +1526,16 @@ static void update_eld(struct hda_codec *codec,
 	 */
 	pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
 
-	if (eld->eld_valid) {
-		hdmi_attach_hda_pcm(spec, per_pin);
-		hdmi_pcm_setup_pin(spec, per_pin);
-	} else {
-		hdmi_pcm_reset_pin(spec, per_pin);
-		hdmi_detach_hda_pcm(spec, per_pin);
+	if (!spec->static_pcm_mapping) {
+		if (eld->eld_valid) {
+			hdmi_attach_hda_pcm(spec, per_pin);
+			hdmi_pcm_setup_pin(spec, per_pin);
+		} else {
+			hdmi_pcm_reset_pin(spec, per_pin);
+			hdmi_detach_hda_pcm(spec, per_pin);
+		}
 	}
+
 	/* if pcm_idx == -1, it means this is in monitor connection event
 	 * we can get the correct pcm_idx now.
 	 */
@@ -2281,8 +2285,8 @@ static int generic_hdmi_build_pcms(struct hda_codec *codec)
 	struct hdmi_spec *spec = codec->spec;
 	int idx, pcm_num;
 
-	/* limit the PCM devices to the codec converters */
-	pcm_num = spec->num_cvts;
+	/* limit the PCM devices to the codec converters or available PINs */
+	pcm_num = min(spec->num_cvts, spec->num_pins);
 	codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num);
 
 	for (idx = 0; idx < pcm_num; idx++) {
@@ -2379,6 +2383,11 @@ static int generic_hdmi_build_controls(struct hda_codec *codec)
 		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
 		struct hdmi_eld *pin_eld = &per_pin->sink_eld;
 
+		if (spec->static_pcm_mapping) {
+			hdmi_attach_hda_pcm(spec, per_pin);
+			hdmi_pcm_setup_pin(spec, per_pin);
+		}
+
 		pin_eld->eld_valid = false;
 		hdmi_present_sense(per_pin, 0);
 	}
@@ -4419,6 +4428,8 @@ static int patch_atihdmi(struct hda_codec *codec)
 
 	spec = codec->spec;
 
+	spec->static_pcm_mapping = true;
+
 	spec->ops.pin_get_eld = atihdmi_pin_get_eld;
 	spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
 	spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
-- 
GitLab


From 8ca4fc323d2e4ab9dabbdd57633af40b0c7e6af9 Mon Sep 17 00:00:00 2001
From: Christoph Hellwig <hch@lst.de>
Date: Mon, 12 Dec 2022 11:09:55 +0100
Subject: [PATCH 775/875] docs, nvme: add a feature and quirk policy document

This adds a document about what specification features are supported by
the Linux NVMe driver, and what qualifies for a quirk if an implementation
has problems following the specification.

Signed-off-by: Jens Axboe <axboe@kernel.dk>
Signed-off-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Sagi Grimberg <sagi@grimberg.me>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
Acked-by: Jonathan Corbet <corbet@lwn.net>
---
 .../maintainer/maintainer-entry-profile.rst   |  1 +
 .../nvme/feature-and-quirk-policy.rst         | 77 +++++++++++++++++++
 MAINTAINERS                                   |  1 +
 3 files changed, 79 insertions(+)
 create mode 100644 Documentation/nvme/feature-and-quirk-policy.rst

diff --git a/Documentation/maintainer/maintainer-entry-profile.rst b/Documentation/maintainer/maintainer-entry-profile.rst
index 93b2ae6c34a99..cfd37f31077f6 100644
--- a/Documentation/maintainer/maintainer-entry-profile.rst
+++ b/Documentation/maintainer/maintainer-entry-profile.rst
@@ -104,3 +104,4 @@ to do something different in the near future.
    ../riscv/patch-acceptance
    ../driver-api/media/maintainer-entry-profile
    ../driver-api/vfio-pci-device-specific-driver-acceptance
+   ../nvme/feature-and-quirk-policy
diff --git a/Documentation/nvme/feature-and-quirk-policy.rst b/Documentation/nvme/feature-and-quirk-policy.rst
new file mode 100644
index 0000000000000..c01d836d8e415
--- /dev/null
+++ b/Documentation/nvme/feature-and-quirk-policy.rst
@@ -0,0 +1,77 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=======================================
+Linux NVMe feature and and quirk policy
+=======================================
+
+This file explains the policy used to decide what is supported by the
+Linux NVMe driver and what is not.
+
+
+Introduction
+============
+
+NVM Express is an open collection of standards and information.
+
+The Linux NVMe host driver in drivers/nvme/host/ supports devices
+implementing the NVM Express (NVMe) family of specifications, which
+currently consists of a number of documents:
+
+ - the NVMe Base specification
+ - various Command Set specifications (e.g. NVM Command Set)
+ - various Transport specifications (e.g. PCIe, Fibre Channel, RDMA, TCP)
+ - the NVMe Management Interface specification
+
+See https://nvmexpress.org/developers/ for the NVMe specifications.
+
+
+Supported features
+==================
+
+NVMe is a large suite of specifications, and contains features that are only
+useful or suitable for specific use-cases. It is important to note that Linux
+does not aim to implement every feature in the specification.  Every additional
+feature implemented introduces more code, more maintenance and potentially more
+bugs.  Hence there is an inherent tradeoff between functionality and
+maintainability of the NVMe host driver.
+
+Any feature implemented in the Linux NVMe host driver must support the
+following requirements:
+
+  1. The feature is specified in a release version of an official NVMe
+     specification, or in a ratified Technical Proposal (TP) that is
+     available on NVMe website. Or if it is not directly related to the
+     on-wire protocol, does not contradict any of the NVMe specifications.
+  2. Does not conflict with the Linux architecture, nor the design of the
+     NVMe host driver.
+  3. Has a clear, indisputable value-proposition and a wide consensus across
+     the community.
+
+Vendor specific extensions are generally not supported in the NVMe host
+driver.
+
+It is strongly recommended to work with the Linux NVMe and block layer
+maintainers and get feedback on specification changes that are intended
+to be used by the Linux NVMe host driver in order to avoid conflict at a
+later stage.
+
+
+Quirks
+======
+
+Sometimes implementations of open standards fail to correctly implement parts
+of the standards.  Linux uses identifier-based quirks to work around such
+implementation bugs.  The intent of quirks is to deal with widely available
+hardware, usually consumer, which Linux users can't use without these quirks.
+Typically these implementations are not or only superficially tested with Linux
+by the hardware manufacturer.
+
+The Linux NVMe maintainers decide ad hoc whether to quirk implementations
+based on the impact of the problem to Linux users and how it impacts
+maintainability of the driver.  In general quirks are a last resort, if no
+firmware updates or other workarounds are available from the vendor.
+
+Quirks will not be added to the Linux kernel for hardware that isn't available
+on the mass market.  Hardware that fails qualification for enterprise Linux
+distributions, ChromeOS, Android or other consumers of the Linux kernel
+should be fixed before it is shipped instead of relying on Linux quirks.
diff --git a/MAINTAINERS b/MAINTAINERS
index bb77a3ed9d542..d53b3a6cdc67d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14827,6 +14827,7 @@ L:	linux-nvme@lists.infradead.org
 S:	Supported
 W:	http://git.infradead.org/nvme.git
 T:	git://git.infradead.org/nvme.git
+F:	Documentation/nvme/
 F:	drivers/nvme/host/
 F:	drivers/nvme/common/
 F:	include/linux/nvme*
-- 
GitLab


From 685e6311637e46f3212439ce2789f8a300e5050f Mon Sep 17 00:00:00 2001
From: Christoph Hellwig <hch@lst.de>
Date: Wed, 21 Dec 2022 10:30:45 +0100
Subject: [PATCH 776/875] nvme: fix the NVME_CMD_EFFECTS_CSE_MASK definition

3 << 16 does not generate the correct mask for bits 16, 17 and 18.
Use the GENMASK macro to generate the correct mask instead.

Fixes: 84fef62d135b ("nvme: check admin passthru command effects")
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Sagi Grimberg <sagi@grimberg.me>
Reviewed-by: Kanchan Joshi <joshi.k@samsung.com>
---
 include/linux/nvme.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/linux/nvme.h b/include/linux/nvme.h
index d6be2a6861000..d1cd53f2b6abd 100644
--- a/include/linux/nvme.h
+++ b/include/linux/nvme.h
@@ -7,6 +7,7 @@
 #ifndef _LINUX_NVME_H
 #define _LINUX_NVME_H
 
+#include <linux/bits.h>
 #include <linux/types.h>
 #include <linux/uuid.h>
 
@@ -639,7 +640,7 @@ enum {
 	NVME_CMD_EFFECTS_NCC		= 1 << 2,
 	NVME_CMD_EFFECTS_NIC		= 1 << 3,
 	NVME_CMD_EFFECTS_CCC		= 1 << 4,
-	NVME_CMD_EFFECTS_CSE_MASK	= 3 << 16,
+	NVME_CMD_EFFECTS_CSE_MASK	= GENMASK(18, 16),
 	NVME_CMD_EFFECTS_UUID_SEL	= 1 << 19,
 };
 
-- 
GitLab


From 61f37154c599cf9f2f84dcbd9be842f8645a7099 Mon Sep 17 00:00:00 2001
From: Christoph Hellwig <hch@lst.de>
Date: Mon, 12 Dec 2022 15:20:04 +0100
Subject: [PATCH 777/875] nvmet: use NVME_CMD_EFFECTS_CSUPP instead of open
 coding it

Use NVME_CMD_EFFECTS_CSUPP instead of open coding it and assign a
single value to multiple array entries instead of repeated assignments.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Sagi Grimberg <sagi@grimberg.me>
Reviewed-by: Kanchan Joshi <joshi.k@samsung.com>
Reviewed-by: Chaitanya Kulkarni <kch@nvidia.com>
---
 drivers/nvme/target/admin-cmd.c | 35 ++++++++++++++++++---------------
 1 file changed, 19 insertions(+), 16 deletions(-)

diff --git a/drivers/nvme/target/admin-cmd.c b/drivers/nvme/target/admin-cmd.c
index 53a004ea320c1..111a5cb6403fb 100644
--- a/drivers/nvme/target/admin-cmd.c
+++ b/drivers/nvme/target/admin-cmd.c
@@ -164,26 +164,29 @@ out:
 
 static void nvmet_get_cmd_effects_nvm(struct nvme_effects_log *log)
 {
-	log->acs[nvme_admin_get_log_page]	= cpu_to_le32(1 << 0);
-	log->acs[nvme_admin_identify]		= cpu_to_le32(1 << 0);
-	log->acs[nvme_admin_abort_cmd]		= cpu_to_le32(1 << 0);
-	log->acs[nvme_admin_set_features]	= cpu_to_le32(1 << 0);
-	log->acs[nvme_admin_get_features]	= cpu_to_le32(1 << 0);
-	log->acs[nvme_admin_async_event]	= cpu_to_le32(1 << 0);
-	log->acs[nvme_admin_keep_alive]		= cpu_to_le32(1 << 0);
-
-	log->iocs[nvme_cmd_read]		= cpu_to_le32(1 << 0);
-	log->iocs[nvme_cmd_write]		= cpu_to_le32(1 << 0);
-	log->iocs[nvme_cmd_flush]		= cpu_to_le32(1 << 0);
-	log->iocs[nvme_cmd_dsm]			= cpu_to_le32(1 << 0);
-	log->iocs[nvme_cmd_write_zeroes]	= cpu_to_le32(1 << 0);
+	log->acs[nvme_admin_get_log_page] =
+	log->acs[nvme_admin_identify] =
+	log->acs[nvme_admin_abort_cmd] =
+	log->acs[nvme_admin_set_features] =
+	log->acs[nvme_admin_get_features] =
+	log->acs[nvme_admin_async_event] =
+	log->acs[nvme_admin_keep_alive] =
+		cpu_to_le32(NVME_CMD_EFFECTS_CSUPP);
+
+	log->iocs[nvme_cmd_read] =
+	log->iocs[nvme_cmd_write] =
+	log->iocs[nvme_cmd_flush] =
+	log->iocs[nvme_cmd_dsm]	=
+	log->iocs[nvme_cmd_write_zeroes] =
+		cpu_to_le32(NVME_CMD_EFFECTS_CSUPP);
 }
 
 static void nvmet_get_cmd_effects_zns(struct nvme_effects_log *log)
 {
-	log->iocs[nvme_cmd_zone_append]		= cpu_to_le32(1 << 0);
-	log->iocs[nvme_cmd_zone_mgmt_send]	= cpu_to_le32(1 << 0);
-	log->iocs[nvme_cmd_zone_mgmt_recv]	= cpu_to_le32(1 << 0);
+	log->iocs[nvme_cmd_zone_append] =
+	log->iocs[nvme_cmd_zone_mgmt_send] =
+	log->iocs[nvme_cmd_zone_mgmt_recv] =
+		cpu_to_le32(NVME_CMD_EFFECTS_CSUPP);
 }
 
 static void nvmet_execute_get_log_cmd_effects_ns(struct nvmet_req *req)
-- 
GitLab


From f2d1421391bba0b15684d2379a47a089f0e561d0 Mon Sep 17 00:00:00 2001
From: Christoph Hellwig <hch@lst.de>
Date: Mon, 12 Dec 2022 15:20:56 +0100
Subject: [PATCH 778/875] nvmet: set the LBCC bit for commands that modify data

Write, Write Zeroes, Zone append and a Zone Reset through
Zone Management Send modify the logical block content of a namespace,
so make sure the LBCC bit is reported for them.

Fixes: b5d0b38c0475 ("nvmet: add Command Set Identifier support")
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Sagi Grimberg <sagi@grimberg.me>
Reviewed-by: Kanchan Joshi <joshi.k@samsung.com>
Reviewed-by: Chaitanya Kulkarni <kch@nvidia.com>
---
 drivers/nvme/target/admin-cmd.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/nvme/target/admin-cmd.c b/drivers/nvme/target/admin-cmd.c
index 111a5cb6403fb..6a54ed6fb1214 100644
--- a/drivers/nvme/target/admin-cmd.c
+++ b/drivers/nvme/target/admin-cmd.c
@@ -174,17 +174,19 @@ static void nvmet_get_cmd_effects_nvm(struct nvme_effects_log *log)
 		cpu_to_le32(NVME_CMD_EFFECTS_CSUPP);
 
 	log->iocs[nvme_cmd_read] =
-	log->iocs[nvme_cmd_write] =
 	log->iocs[nvme_cmd_flush] =
 	log->iocs[nvme_cmd_dsm]	=
-	log->iocs[nvme_cmd_write_zeroes] =
 		cpu_to_le32(NVME_CMD_EFFECTS_CSUPP);
+	log->iocs[nvme_cmd_write] =
+	log->iocs[nvme_cmd_write_zeroes] =
+		cpu_to_le32(NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC);
 }
 
 static void nvmet_get_cmd_effects_zns(struct nvme_effects_log *log)
 {
 	log->iocs[nvme_cmd_zone_append] =
 	log->iocs[nvme_cmd_zone_mgmt_send] =
+		cpu_to_le32(NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC);
 	log->iocs[nvme_cmd_zone_mgmt_recv] =
 		cpu_to_le32(NVME_CMD_EFFECTS_CSUPP);
 }
-- 
GitLab


From 2a459f6933e1c459bffb7cc73fd6c900edc714bd Mon Sep 17 00:00:00 2001
From: Christoph Hellwig <hch@lst.de>
Date: Wed, 21 Dec 2022 09:51:19 +0100
Subject: [PATCH 779/875] nvmet: don't defer passthrough commands with trivial
 effects to the workqueue

Mask out the "Command Supported" and "Logical Block Content Change" bits
and only defer execution of commands that have non-trivial effects to
the workqueue for synchronous execution.  This allows to execute admin
commands asynchronously on controllers that provide a Command Supported
and Effects log page, and will keep allowing to execute Write commands
asynchronously once command effects on I/O commands are taken into
account.

Fixes: c1fef73f793b ("nvmet: add passthru code to process commands")
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Sagi Grimberg <sagi@grimberg.me>
Reviewed-by: Kanchan Joshi <joshi.k@samsung.com>
---
 drivers/nvme/target/passthru.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/nvme/target/passthru.c b/drivers/nvme/target/passthru.c
index 79af5140af8bf..adc0958755d66 100644
--- a/drivers/nvme/target/passthru.c
+++ b/drivers/nvme/target/passthru.c
@@ -334,14 +334,13 @@ static void nvmet_passthru_execute_cmd(struct nvmet_req *req)
 	}
 
 	/*
-	 * If there are effects for the command we are about to execute, or
-	 * an end_req function we need to use nvme_execute_passthru_rq()
-	 * synchronously in a work item seeing the end_req function and
-	 * nvme_passthru_end() can't be called in the request done callback
-	 * which is typically in interrupt context.
+	 * If a command needs post-execution fixups, or there are any
+	 * non-trivial effects, make sure to execute the command synchronously
+	 * in a workqueue so that nvme_passthru_end gets called.
 	 */
 	effects = nvme_command_effects(ctrl, ns, req->cmd->common.opcode);
-	if (req->p.use_workqueue || effects) {
+	if (req->p.use_workqueue ||
+	    (effects & ~(NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC))) {
 		INIT_WORK(&req->p.work, nvmet_passthru_execute_cmd_work);
 		req->p.rq = rq;
 		queue_work(nvmet_wq, &req->p.work);
-- 
GitLab


From 831ed60c2aca2d7c517b2da22897a90224a97d27 Mon Sep 17 00:00:00 2001
From: Christoph Hellwig <hch@lst.de>
Date: Wed, 21 Dec 2022 10:12:17 +0100
Subject: [PATCH 780/875] nvme: also return I/O command effects from
 nvme_command_effects

To be able to use the Commands Supported and Effects Log for allowing
unprivileged passtrough, it needs to be corretly reported for I/O
commands as well.  Return the I/O command effects from
nvme_command_effects, and also add a default list of effects for the
NVM command set.  For other command sets, the Commands Supported and
Effects log is required to be present already.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Kanchan Joshi <joshi.k@samsung.com>
---
 drivers/nvme/host/core.c | 32 ++++++++++++++++++++++++++------
 1 file changed, 26 insertions(+), 6 deletions(-)

diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c
index cda1361e6d4fb..d307ae4d8a575 100644
--- a/drivers/nvme/host/core.c
+++ b/drivers/nvme/host/core.c
@@ -1074,6 +1074,18 @@ static u32 nvme_known_admin_effects(u8 opcode)
 	return 0;
 }
 
+static u32 nvme_known_nvm_effects(u8 opcode)
+{
+	switch (opcode) {
+	case nvme_cmd_write:
+	case nvme_cmd_write_zeroes:
+	case nvme_cmd_write_uncor:
+		 return NVME_CMD_EFFECTS_LBCC;
+	default:
+		return 0;
+	}
+}
+
 u32 nvme_command_effects(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u8 opcode)
 {
 	u32 effects = 0;
@@ -1081,16 +1093,24 @@ u32 nvme_command_effects(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u8 opcode)
 	if (ns) {
 		if (ns->head->effects)
 			effects = le32_to_cpu(ns->head->effects->iocs[opcode]);
+		if (ns->head->ids.csi == NVME_CAP_CSS_NVM)
+			effects |= nvme_known_nvm_effects(opcode);
 		if (effects & ~(NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC))
 			dev_warn_once(ctrl->device,
-				"IO command:%02x has unhandled effects:%08x\n",
+				"IO command:%02x has unusual effects:%08x\n",
 				opcode, effects);
-		return 0;
-	}
 
-	if (ctrl->effects)
-		effects = le32_to_cpu(ctrl->effects->acs[opcode]);
-	effects |= nvme_known_admin_effects(opcode);
+		/*
+		 * NVME_CMD_EFFECTS_CSE_MASK causes a freeze all I/O queues,
+		 * which would deadlock when done on an I/O command.  Note that
+		 * We already warn about an unusual effect above.
+		 */
+		effects &= ~NVME_CMD_EFFECTS_CSE_MASK;
+	} else {
+		if (ctrl->effects)
+			effects = le32_to_cpu(ctrl->effects->acs[opcode]);
+		effects |= nvme_known_admin_effects(opcode);
+	}
 
 	return effects;
 }
-- 
GitLab


From 6f99ac04c469b5d0a180a4ccea99d25d5dc9d21c Mon Sep 17 00:00:00 2001
From: Christoph Hellwig <hch@lst.de>
Date: Tue, 13 Dec 2022 16:13:38 +0100
Subject: [PATCH 781/875] nvme: consult the CSE log page for unprivileged
 passthrough

Commands like Write Zeros can change the contents of a namespaces without
actually transferring data.  To protect against this, check the Commands
Supported and Effects log is supported by the controller for any
unprivileg command passthrough and refuse unprivileged passthrough if the
command has any effects that can change data or metadata.

Note: While the Commands Support and Effects log page has only been
mandatory since NVMe 2.0, it is widely supported because Windows requires
it for any command passthrough from userspace.

Fixes: e4fbcf32c860 ("nvme: identify-namespace without CAP_SYS_ADMIN")
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Sagi Grimberg <sagi@grimberg.me>
Reviewed-by: Kanchan Joshi <joshi.k@samsung.com>
---
 drivers/nvme/host/ioctl.c | 28 ++++++++++++++++++++++++----
 include/linux/nvme.h      |  1 +
 2 files changed, 25 insertions(+), 4 deletions(-)

diff --git a/drivers/nvme/host/ioctl.c b/drivers/nvme/host/ioctl.c
index 9ddda571f0461..a8639919237e6 100644
--- a/drivers/nvme/host/ioctl.c
+++ b/drivers/nvme/host/ioctl.c
@@ -11,6 +11,8 @@
 static bool nvme_cmd_allowed(struct nvme_ns *ns, struct nvme_command *c,
 		fmode_t mode)
 {
+	u32 effects;
+
 	if (capable(CAP_SYS_ADMIN))
 		return true;
 
@@ -43,11 +45,29 @@ static bool nvme_cmd_allowed(struct nvme_ns *ns, struct nvme_command *c,
 	}
 
 	/*
-	 * Only allow I/O commands that transfer data to the controller if the
-	 * special file is open for writing, but always allow I/O commands that
-	 * transfer data from the controller.
+	 * Check if the controller provides a Commands Supported and Effects log
+	 * and marks this command as supported.  If not reject unprivileged
+	 * passthrough.
+	 */
+	effects = nvme_command_effects(ns->ctrl, ns, c->common.opcode);
+	if (!(effects & NVME_CMD_EFFECTS_CSUPP))
+		return false;
+
+	/*
+	 * Don't allow passthrough for command that have intrusive (or unknown)
+	 * effects.
+	 */
+	if (effects & ~(NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC |
+			NVME_CMD_EFFECTS_UUID_SEL |
+			NVME_CMD_EFFECTS_SCOPE_MASK))
+		return false;
+
+	/*
+	 * Only allow I/O commands that transfer data to the controller or that
+	 * change the logical block contents if the file descriptor is open for
+	 * writing.
 	 */
-	if (nvme_is_write(c))
+	if (nvme_is_write(c) || (effects & NVME_CMD_EFFECTS_LBCC))
 		return mode & FMODE_WRITE;
 	return true;
 }
diff --git a/include/linux/nvme.h b/include/linux/nvme.h
index d1cd53f2b6abd..4fad4aa245fb0 100644
--- a/include/linux/nvme.h
+++ b/include/linux/nvme.h
@@ -642,6 +642,7 @@ enum {
 	NVME_CMD_EFFECTS_CCC		= 1 << 4,
 	NVME_CMD_EFFECTS_CSE_MASK	= GENMASK(18, 16),
 	NVME_CMD_EFFECTS_UUID_SEL	= 1 << 19,
+	NVME_CMD_EFFECTS_SCOPE_MASK	= GENMASK(31, 20),
 };
 
 struct nvme_effects_log {
-- 
GitLab


From 76807fcd73b818eb9f245ef1035aed34ecdd9813 Mon Sep 17 00:00:00 2001
From: Sagi Grimberg <sagi@grimberg.me>
Date: Sun, 25 Dec 2022 13:28:51 +0200
Subject: [PATCH 782/875] nvme-auth: fix smatch warning complaints

When initializing auth context, there may be no secrets passed
by the user. Make return code explicit when returning successfully.

smatch warnings:
drivers/nvme/host/auth.c:950 nvme_auth_init_ctrl() warn: missing error code? 'ret'

Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <error27@gmail.com>
Signed-off-by: Sagi Grimberg <sagi@grimberg.me>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/nvme/host/auth.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/nvme/host/auth.c b/drivers/nvme/host/auth.c
index bb0abbe4491cd..4424f53a8a0a3 100644
--- a/drivers/nvme/host/auth.c
+++ b/drivers/nvme/host/auth.c
@@ -953,7 +953,7 @@ int nvme_auth_init_ctrl(struct nvme_ctrl *ctrl)
 		goto err_free_dhchap_secret;
 
 	if (!ctrl->opts->dhchap_secret && !ctrl->opts->dhchap_ctrl_secret)
-		return ret;
+		return 0;
 
 	ctrl->dhchap_ctxs = kvcalloc(ctrl_max_dhchaps(ctrl),
 				sizeof(*chap), GFP_KERNEL);
-- 
GitLab


From 1f0ae22ab470946143485a02cc1cd7e05c0f9120 Mon Sep 17 00:00:00 2001
From: Moshe Shemesh <moshe@nvidia.com>
Date: Mon, 12 Dec 2022 10:42:15 +0200
Subject: [PATCH 783/875] net/mlx5: E-Switch, properly handle ingress tagged
 packets on VST

Fix SRIOV VST mode behavior to insert cvlan when a guest tag is already
present in the frame. Previous VST mode behavior was to drop packets or
override existing tag, depending on the device version.

In this patch we fix this behavior by correctly building the HW steering
rule with a push vlan action, or for older devices we ask the FW to stack
the vlan when a vlan is already present.

Fixes: 07bab9502641 ("net/mlx5: E-Switch, Refactor eswitch ingress acl codes")
Fixes: dfcb1ed3c331 ("net/mlx5: E-Switch, Vport ingress/egress ACLs rules for VST mode")
Signed-off-by: Moshe Shemesh <moshe@nvidia.com>
Reviewed-by: Mark Bloch <mbloch@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
 .../mellanox/mlx5/core/esw/acl/egress_lgcy.c  |  7 +++-
 .../mellanox/mlx5/core/esw/acl/ingress_lgcy.c | 33 ++++++++++++++++---
 .../net/ethernet/mellanox/mlx5/core/eswitch.c | 30 ++++++++++++-----
 .../net/ethernet/mellanox/mlx5/core/eswitch.h |  6 ++++
 include/linux/mlx5/device.h                   |  5 +++
 include/linux/mlx5/mlx5_ifc.h                 |  3 +-
 6 files changed, 68 insertions(+), 16 deletions(-)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/acl/egress_lgcy.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/acl/egress_lgcy.c
index 60a73990017c2..6b4c9ffad95b2 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/esw/acl/egress_lgcy.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/acl/egress_lgcy.c
@@ -67,6 +67,7 @@ static void esw_acl_egress_lgcy_groups_destroy(struct mlx5_vport *vport)
 int esw_acl_egress_lgcy_setup(struct mlx5_eswitch *esw,
 			      struct mlx5_vport *vport)
 {
+	bool vst_mode_steering = esw_vst_mode_is_steering(esw);
 	struct mlx5_flow_destination drop_ctr_dst = {};
 	struct mlx5_flow_destination *dst = NULL;
 	struct mlx5_fc *drop_counter = NULL;
@@ -77,6 +78,7 @@ int esw_acl_egress_lgcy_setup(struct mlx5_eswitch *esw,
 	 */
 	int table_size = 2;
 	int dest_num = 0;
+	int actions_flag;
 	int err = 0;
 
 	if (vport->egress.legacy.drop_counter) {
@@ -119,8 +121,11 @@ int esw_acl_egress_lgcy_setup(struct mlx5_eswitch *esw,
 		  vport->vport, vport->info.vlan, vport->info.qos);
 
 	/* Allowed vlan rule */
+	actions_flag = MLX5_FLOW_CONTEXT_ACTION_ALLOW;
+	if (vst_mode_steering)
+		actions_flag |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
 	err = esw_egress_acl_vlan_create(esw, vport, NULL, vport->info.vlan,
-					 MLX5_FLOW_CONTEXT_ACTION_ALLOW);
+					 actions_flag);
 	if (err)
 		goto out;
 
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/acl/ingress_lgcy.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/acl/ingress_lgcy.c
index b1a5199260f69..093ed86a0acd8 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/esw/acl/ingress_lgcy.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/acl/ingress_lgcy.c
@@ -139,11 +139,14 @@ static void esw_acl_ingress_lgcy_groups_destroy(struct mlx5_vport *vport)
 int esw_acl_ingress_lgcy_setup(struct mlx5_eswitch *esw,
 			       struct mlx5_vport *vport)
 {
+	bool vst_mode_steering = esw_vst_mode_is_steering(esw);
 	struct mlx5_flow_destination drop_ctr_dst = {};
 	struct mlx5_flow_destination *dst = NULL;
 	struct mlx5_flow_act flow_act = {};
 	struct mlx5_flow_spec *spec = NULL;
 	struct mlx5_fc *counter = NULL;
+	bool vst_check_cvlan = false;
+	bool vst_push_cvlan = false;
 	/* The ingress acl table contains 4 groups
 	 * (2 active rules at the same time -
 	 *      1 allow rule from one of the first 3 groups.
@@ -203,7 +206,26 @@ int esw_acl_ingress_lgcy_setup(struct mlx5_eswitch *esw,
 		goto out;
 	}
 
-	if (vport->info.vlan || vport->info.qos)
+	if ((vport->info.vlan || vport->info.qos)) {
+		if (vst_mode_steering)
+			vst_push_cvlan = true;
+		else if (!MLX5_CAP_ESW(esw->dev, vport_cvlan_insert_always))
+			vst_check_cvlan = true;
+	}
+
+	if (vst_check_cvlan || vport->info.spoofchk)
+		spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
+
+	/* Create ingress allow rule */
+	flow_act.action = MLX5_FLOW_CONTEXT_ACTION_ALLOW;
+	if (vst_push_cvlan) {
+		flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
+		flow_act.vlan[0].prio = vport->info.qos;
+		flow_act.vlan[0].vid = vport->info.vlan;
+		flow_act.vlan[0].ethtype = ETH_P_8021Q;
+	}
+
+	if (vst_check_cvlan)
 		MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria,
 				 outer_headers.cvlan_tag);
 
@@ -218,9 +240,6 @@ int esw_acl_ingress_lgcy_setup(struct mlx5_eswitch *esw,
 		ether_addr_copy(smac_v, vport->info.mac);
 	}
 
-	/* Create ingress allow rule */
-	spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
-	flow_act.action = MLX5_FLOW_CONTEXT_ACTION_ALLOW;
 	vport->ingress.allow_rule = mlx5_add_flow_rules(vport->ingress.acl, spec,
 							&flow_act, NULL, 0);
 	if (IS_ERR(vport->ingress.allow_rule)) {
@@ -232,6 +251,9 @@ int esw_acl_ingress_lgcy_setup(struct mlx5_eswitch *esw,
 		goto out;
 	}
 
+	if (!vst_check_cvlan && !vport->info.spoofchk)
+		goto out;
+
 	memset(&flow_act, 0, sizeof(flow_act));
 	flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
 	/* Attach drop flow counter */
@@ -257,7 +279,8 @@ int esw_acl_ingress_lgcy_setup(struct mlx5_eswitch *esw,
 	return 0;
 
 out:
-	esw_acl_ingress_lgcy_cleanup(esw, vport);
+	if (err)
+		esw_acl_ingress_lgcy_cleanup(esw, vport);
 	kvfree(spec);
 	return err;
 }
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c
index 527e4bffda8d4..0dfd5742c6fe9 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c
@@ -161,10 +161,17 @@ static int modify_esw_vport_cvlan(struct mlx5_core_dev *dev, u16 vport,
 			 esw_vport_context.vport_cvlan_strip, 1);
 
 	if (set_flags & SET_VLAN_INSERT) {
-		/* insert only if no vlan in packet */
-		MLX5_SET(modify_esw_vport_context_in, in,
-			 esw_vport_context.vport_cvlan_insert, 1);
-
+		if (MLX5_CAP_ESW(dev, vport_cvlan_insert_always)) {
+			/* insert either if vlan exist in packet or not */
+			MLX5_SET(modify_esw_vport_context_in, in,
+				 esw_vport_context.vport_cvlan_insert,
+				 MLX5_VPORT_CVLAN_INSERT_ALWAYS);
+		} else {
+			/* insert only if no vlan in packet */
+			MLX5_SET(modify_esw_vport_context_in, in,
+				 esw_vport_context.vport_cvlan_insert,
+				 MLX5_VPORT_CVLAN_INSERT_WHEN_NO_CVLAN);
+		}
 		MLX5_SET(modify_esw_vport_context_in, in,
 			 esw_vport_context.cvlan_pcp, qos);
 		MLX5_SET(modify_esw_vport_context_in, in,
@@ -809,6 +816,7 @@ out_free:
 
 static int esw_vport_setup(struct mlx5_eswitch *esw, struct mlx5_vport *vport)
 {
+	bool vst_mode_steering = esw_vst_mode_is_steering(esw);
 	u16 vport_num = vport->vport;
 	int flags;
 	int err;
@@ -839,8 +847,9 @@ static int esw_vport_setup(struct mlx5_eswitch *esw, struct mlx5_vport *vport)
 
 	flags = (vport->info.vlan || vport->info.qos) ?
 		SET_VLAN_STRIP | SET_VLAN_INSERT : 0;
-	modify_esw_vport_cvlan(esw->dev, vport_num, vport->info.vlan,
-			       vport->info.qos, flags);
+	if (esw->mode == MLX5_ESWITCH_OFFLOADS || !vst_mode_steering)
+		modify_esw_vport_cvlan(esw->dev, vport_num, vport->info.vlan,
+				       vport->info.qos, flags);
 
 	return 0;
 
@@ -1848,6 +1857,7 @@ int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
 				  u16 vport, u16 vlan, u8 qos, u8 set_flags)
 {
 	struct mlx5_vport *evport = mlx5_eswitch_get_vport(esw, vport);
+	bool vst_mode_steering = esw_vst_mode_is_steering(esw);
 	int err = 0;
 
 	if (IS_ERR(evport))
@@ -1855,9 +1865,11 @@ int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
 	if (vlan > 4095 || qos > 7)
 		return -EINVAL;
 
-	err = modify_esw_vport_cvlan(esw->dev, vport, vlan, qos, set_flags);
-	if (err)
-		return err;
+	if (esw->mode == MLX5_ESWITCH_OFFLOADS || !vst_mode_steering) {
+		err = modify_esw_vport_cvlan(esw->dev, vport, vlan, qos, set_flags);
+		if (err)
+			return err;
+	}
 
 	evport->info.vlan = vlan;
 	evport->info.qos = qos;
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h
index 5a85a5d32be7e..92644fbb50816 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h
@@ -527,6 +527,12 @@ int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
 int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
 				  u16 vport, u16 vlan, u8 qos, u8 set_flags);
 
+static inline bool esw_vst_mode_is_steering(struct mlx5_eswitch *esw)
+{
+	return (MLX5_CAP_ESW_EGRESS_ACL(esw->dev, pop_vlan) &&
+		MLX5_CAP_ESW_INGRESS_ACL(esw->dev, push_vlan));
+}
+
 static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev,
 						       u8 vlan_depth)
 {
diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index 5fe5d198b57ad..29d4b201c7b26 100644
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -1090,6 +1090,11 @@ enum {
 	MLX5_VPORT_ADMIN_STATE_AUTO  = 0x2,
 };
 
+enum {
+	MLX5_VPORT_CVLAN_INSERT_WHEN_NO_CVLAN  = 0x1,
+	MLX5_VPORT_CVLAN_INSERT_ALWAYS         = 0x3,
+};
+
 enum {
 	MLX5_L3_PROT_TYPE_IPV4		= 0,
 	MLX5_L3_PROT_TYPE_IPV6		= 1,
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index f3d1c62c98ddc..a9ee7bc59c901 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -913,7 +913,8 @@ struct mlx5_ifc_e_switch_cap_bits {
 	u8         vport_svlan_insert[0x1];
 	u8         vport_cvlan_insert_if_not_exist[0x1];
 	u8         vport_cvlan_insert_overwrite[0x1];
-	u8         reserved_at_5[0x2];
+	u8         reserved_at_5[0x1];
+	u8         vport_cvlan_insert_always[0x1];
 	u8         esw_shared_ingress_acl[0x1];
 	u8         esw_uplink_ingress_acl[0x1];
 	u8         root_ft_on_other_esw[0x1];
-- 
GitLab


From 2a35b2c2e6a252eda2134aae6a756861d9299531 Mon Sep 17 00:00:00 2001
From: Jiri Pirko <jiri@nvidia.com>
Date: Tue, 18 Oct 2022 12:51:52 +0200
Subject: [PATCH 784/875] net/mlx5: Add forgotten cleanup calls into
 mlx5_init_once() error path

There are two cleanup calls missing in mlx5_init_once() error path.
Add them making the error path flow to be the same as
mlx5_cleanup_once().

Fixes: 52ec462eca9b ("net/mlx5: Add reserved-gids support")
Fixes: 7c39afb394c7 ("net/mlx5: PTP code migration to driver core section")
Signed-off-by: Jiri Pirko <jiri@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
 drivers/net/ethernet/mellanox/mlx5/core/main.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c
index 7f5db13e3550c..ec5652f31dda1 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/main.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c
@@ -1050,6 +1050,8 @@ err_rl_cleanup:
 err_tables_cleanup:
 	mlx5_geneve_destroy(dev->geneve);
 	mlx5_vxlan_destroy(dev->vxlan);
+	mlx5_cleanup_clock(dev);
+	mlx5_cleanup_reserved_gids(dev);
 	mlx5_cq_debugfs_cleanup(dev);
 	mlx5_fw_reset_cleanup(dev);
 err_events_cleanup:
-- 
GitLab


From 44aee8ea15ac205490a41b00cbafcccbf9f7f82b Mon Sep 17 00:00:00 2001
From: Shay Drory <shayd@nvidia.com>
Date: Sun, 18 Dec 2022 12:42:14 +0200
Subject: [PATCH 785/875] net/mlx5: Fix io_eq_size and event_eq_size params
 validation

io_eq_size and event_eq_size params are of param type
DEVLINK_PARAM_TYPE_U32. But, the validation callback is addressing them
as DEVLINK_PARAM_TYPE_U16.

This cause mismatch in validation in big-endian systems, in which
values in range were rejected while 268500991 was accepted.
Fix it by checking the U32 value in the validation callback.

Fixes: 0844fa5f7b89 ("net/mlx5: Let user configure io_eq_size param")
Signed-off-by: Shay Drory <shayd@nvidia.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
 drivers/net/ethernet/mellanox/mlx5/core/devlink.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/devlink.c b/drivers/net/ethernet/mellanox/mlx5/core/devlink.c
index ddb197970c22c..be59bb35d795c 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/devlink.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/devlink.c
@@ -563,7 +563,7 @@ static int mlx5_devlink_eq_depth_validate(struct devlink *devlink, u32 id,
 					  union devlink_param_value val,
 					  struct netlink_ext_ack *extack)
 {
-	return (val.vu16 >= 64 && val.vu16 <= 4096) ? 0 : -EINVAL;
+	return (val.vu32 >= 64 && val.vu32 <= 4096) ? 0 : -EINVAL;
 }
 
 static const struct devlink_param mlx5_devlink_params[] = {
-- 
GitLab


From 9078e843efec530f279a155f262793c58b0746bd Mon Sep 17 00:00:00 2001
From: Shay Drory <shayd@nvidia.com>
Date: Thu, 24 Nov 2022 13:34:12 +0200
Subject: [PATCH 786/875] net/mlx5: Avoid recovery in probe flows

Currently, recovery is done without considering whether the device is
still in probe flow.
This may lead to recovery before device have finished probed
successfully. e.g.: while mlx5_init_one() is running. Recovery flow is
using functionality that is loaded only by mlx5_init_one(), and there
is no point in running recovery without mlx5_init_one() finished
successfully.

Fix it by waiting for probe flow to finish and checking whether the
device is probed before trying to perform recovery.

Fixes: 51d138c2610a ("net/mlx5: Fix health error state handling")
Signed-off-by: Shay Drory <shayd@nvidia.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
 drivers/net/ethernet/mellanox/mlx5/core/health.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/health.c b/drivers/net/ethernet/mellanox/mlx5/core/health.c
index 86ed87d704f7d..96417c5feed76 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/health.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/health.c
@@ -674,6 +674,12 @@ static void mlx5_fw_fatal_reporter_err_work(struct work_struct *work)
 	dev = container_of(priv, struct mlx5_core_dev, priv);
 	devlink = priv_to_devlink(dev);
 
+	mutex_lock(&dev->intf_state_mutex);
+	if (test_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags)) {
+		mlx5_core_err(dev, "health works are not permitted at this stage\n");
+		return;
+	}
+	mutex_unlock(&dev->intf_state_mutex);
 	enter_error_state(dev, false);
 	if (IS_ERR_OR_NULL(health->fw_fatal_reporter)) {
 		devl_lock(devlink);
-- 
GitLab


From c4ad5f2bdad56265b23d3635494ecdb205431807 Mon Sep 17 00:00:00 2001
From: Shay Drory <shayd@nvidia.com>
Date: Wed, 9 Nov 2022 14:42:59 +0200
Subject: [PATCH 787/875] net/mlx5: Fix RoCE setting at HCA level

mlx5 PF can disable RoCE for its VFs and SFs. In such case RoCE is
marked as unsupported on those VFs/SFs.
The cited patch added an option for disable (and enable) RoCE at HCA
level. However, that commit didn't check whether RoCE is supported on
the HCA and enabled user to try and set RoCE to on.
Fix it by checking whether the HCA supports RoCE.

Fixes: fbfa97b4d79f ("net/mlx5: Disable roce at HCA level")
Signed-off-by: Shay Drory <shayd@nvidia.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
 drivers/net/ethernet/mellanox/mlx5/core/devlink.c | 2 +-
 drivers/net/ethernet/mellanox/mlx5/core/main.c    | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/devlink.c b/drivers/net/ethernet/mellanox/mlx5/core/devlink.c
index be59bb35d795c..5bd83c0275f82 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/devlink.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/devlink.c
@@ -468,7 +468,7 @@ static int mlx5_devlink_enable_roce_validate(struct devlink *devlink, u32 id,
 	bool new_state = val.vbool;
 
 	if (new_state && !MLX5_CAP_GEN(dev, roce) &&
-	    !MLX5_CAP_GEN(dev, roce_rw_supported)) {
+	    !(MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce))) {
 		NL_SET_ERR_MSG_MOD(extack, "Device doesn't support RoCE");
 		return -EOPNOTSUPP;
 	}
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c
index ec5652f31dda1..df134f6d32dc5 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/main.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c
@@ -613,7 +613,7 @@ static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
 		MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix,
 			 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix));
 
-	if (MLX5_CAP_GEN(dev, roce_rw_supported))
+	if (MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce))
 		MLX5_SET(cmd_hca_cap, set_hca_cap, roce,
 			 mlx5_is_roce_on(dev));
 
-- 
GitLab


From b12d581e83e3ae1080c32ab83f123005bd89a840 Mon Sep 17 00:00:00 2001
From: Dragos Tatulea <dtatulea@nvidia.com>
Date: Mon, 28 Nov 2022 15:24:21 +0200
Subject: [PATCH 788/875] net/mlx5e: IPoIB, Don't allow CQE compression to be
 turned on by default

mlx5e_build_nic_params will turn CQE compression on if the hardware
capability is enabled and the slow_pci_heuristic condition is detected.
As IPoIB doesn't support CQE compression, make sure to disable the
feature in the IPoIB profile init.

Please note that the feature is not exposed to the user for IPoIB
interfaces, so it can't be subsequently turned on.

Fixes: b797a684b0dd ("net/mlx5e: Enable CQE compression when PCI is slower than link")
Signed-off-by: Dragos Tatulea <dtatulea@nvidia.com>
Reviewed-by: Gal Pressman <gal@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
 drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c b/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c
index 7c5c500fd215e..2c73c8445e630 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c
@@ -71,6 +71,10 @@ static void mlx5i_build_nic_params(struct mlx5_core_dev *mdev,
 	params->packet_merge.type = MLX5E_PACKET_MERGE_NONE;
 	params->hard_mtu = MLX5_IB_GRH_BYTES + MLX5_IPOIB_HARD_LEN;
 	params->tunneled_offload_en = false;
+
+	/* CQE compression is not supported for IPoIB */
+	params->rx_cqe_compress_def = false;
+	MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
 }
 
 /* Called directly after IPoIB netdevice was created to initialize SW structs */
-- 
GitLab


From f8c18a5749cf917096f75dd59885b7a0fe9298ba Mon Sep 17 00:00:00 2001
From: Tariq Toukan <tariqt@nvidia.com>
Date: Sun, 27 Nov 2022 09:21:28 +0200
Subject: [PATCH 789/875] net/mlx5e: Fix RX reporter for XSK RQs

RX reporter mistakenly reads from the regular (inactive) RQ
when XSK RQ is active. Fix it here.

Fixes: 3db4c85cde7a ("net/mlx5e: xsk: Use queue indices starting from 0 for XSK queues")
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Reviewed-by: Gal Pressman <gal@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
 drivers/net/ethernet/mellanox/mlx5/core/en/reporter_rx.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_rx.c
index 5f6f95ad6888c..1ae15b8536a85 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_rx.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_rx.c
@@ -459,7 +459,11 @@ static int mlx5e_rx_reporter_diagnose(struct devlink_health_reporter *reporter,
 		goto unlock;
 
 	for (i = 0; i < priv->channels.num; i++) {
-		struct mlx5e_rq *rq = &priv->channels.c[i]->rq;
+		struct mlx5e_channel *c = priv->channels.c[i];
+		struct mlx5e_rq *rq;
+
+		rq = test_bit(MLX5E_CHANNEL_STATE_XSK, c->state) ?
+			&c->xskrq : &c->rq;
 
 		err = mlx5e_rx_reporter_build_diagnose_output(rq, fmsg);
 		if (err)
-- 
GitLab


From 849190e3e4ccf452fbe2240eace30a9ca83fb8d2 Mon Sep 17 00:00:00 2001
From: Chris Mi <cmi@nvidia.com>
Date: Mon, 28 Nov 2022 13:54:29 +0800
Subject: [PATCH 790/875] net/mlx5e: CT: Fix ct debugfs folder name

Need to use sprintf to build a string instead of sscanf. Otherwise
dirname is null and both "ct_nic" and "ct_fdb" won't be created.
But its redundant anyway as driver could be in switchdev mode but
still add nic rules. So use "ct" as folder name.

Fixes: 77422a8f6f61 ("net/mlx5e: CT: Add ct driver counters")
Signed-off-by: Chris Mi <cmi@nvidia.com>
Reviewed-by: Roi Dayan <roid@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
 drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c
index a69849e0deed7..313df8232db70 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c
@@ -2103,14 +2103,9 @@ out_err:
 static void
 mlx5_ct_tc_create_dbgfs(struct mlx5_tc_ct_priv *ct_priv)
 {
-	bool is_fdb = ct_priv->ns_type == MLX5_FLOW_NAMESPACE_FDB;
 	struct mlx5_tc_ct_debugfs *ct_dbgfs = &ct_priv->debugfs;
-	char dirname[16] = {};
 
-	if (sscanf(dirname, "ct_%s", is_fdb ? "fdb" : "nic") < 0)
-		return;
-
-	ct_dbgfs->root = debugfs_create_dir(dirname, mlx5_debugfs_get_dev_root(ct_priv->dev));
+	ct_dbgfs->root = debugfs_create_dir("ct", mlx5_debugfs_get_dev_root(ct_priv->dev));
 	debugfs_create_atomic_t("offloaded", 0400, ct_dbgfs->root,
 				&ct_dbgfs->stats.offloaded);
 	debugfs_create_atomic_t("rx_dropped", 0400, ct_dbgfs->root,
-- 
GitLab


From 2951b2e142ecf6e0115df785ba91e91b6da74602 Mon Sep 17 00:00:00 2001
From: Chris Mi <cmi@nvidia.com>
Date: Mon, 5 Dec 2022 09:22:50 +0800
Subject: [PATCH 791/875] net/mlx5e: Always clear dest encap in
 neigh-update-del

The cited commit introduced a bug for multiple encapsulations flow.
If one dest encap becomes invalid, the flow is set slow path flag.
But when other dests encap become invalid, they are not cleared due
to slow path flag of the flow. When neigh-update-add is running, it
will use invalid encap.

Fix it by checking slow path flag after clearing dest encap.

Fixes: 9a5f9cc794e1 ("net/mlx5e: Fix possible use-after-free deleting fdb rule")
Signed-off-by: Chris Mi <cmi@nvidia.com>
Reviewed-by: Roi Dayan <roid@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
 .../net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c    | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c
index ff73d25bc6eb8..2aaf8ab857b8f 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c
@@ -222,7 +222,7 @@ void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
 	int err;
 
 	list_for_each_entry(flow, flow_list, tmp_list) {
-		if (!mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, SLOW))
+		if (!mlx5e_is_offloaded_flow(flow))
 			continue;
 
 		attr = mlx5e_tc_get_encap_attr(flow);
@@ -231,6 +231,13 @@ void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
 		esw_attr->dests[flow->tmp_entry_index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
 		esw_attr->dests[flow->tmp_entry_index].pkt_reformat = NULL;
 
+		/* Clear pkt_reformat before checking slow path flag. Because
+		 * in next iteration, the same flow is already set slow path
+		 * flag, but still need to clear the pkt_reformat.
+		 */
+		if (flow_flag_test(flow, SLOW))
+			continue;
+
 		/* update from encap rule to slow path rule */
 		spec = &flow->attr->parse_attr->spec;
 		rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec);
-- 
GitLab


From 1e267ab88dc44c48f556218f7b7f14c76f7aa066 Mon Sep 17 00:00:00 2001
From: Adham Faris <afaris@nvidia.com>
Date: Wed, 14 Dec 2022 16:02:57 +0200
Subject: [PATCH 792/875] net/mlx5e: Fix hw mtu initializing at XDP SQ
 allocation

Current xdp xmit functions logic (mlx5e_xmit_xdp_frame_mpwqe or
mlx5e_xmit_xdp_frame), validates xdp packet length by comparing it to
hw mtu (configured at xdp sq allocation) before xmiting it. This check
does not account for ethernet fcs length (calculated and filled by the
nic). Hence, when we try sending packets with length > (hw-mtu -
ethernet-fcs-size), the device port drops it and tx_errors_phy is
incremented. Desired behavior is to catch these packets and drop them
by the driver.

Fix this behavior in XDP SQ allocation function (mlx5e_alloc_xdpsq) by
subtracting ethernet FCS header size (4 Bytes) from current hw mtu
value, since ethernet FCS is calculated and written to ethernet frames
by the nic.

Fixes: d8bec2b29a82 ("net/mlx5e: Support bpf_xdp_adjust_head()")
Signed-off-by: Adham Faris <afaris@nvidia.com>
Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
 drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
index 8d36e2de53a99..cff5f2e29e1e2 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
@@ -1305,7 +1305,7 @@ static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 	sq->channel   = c;
 	sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
 	sq->min_inline_mode = params->tx_min_inline_mode;
-	sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
+	sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu) - ETH_FCS_LEN;
 	sq->xsk_pool  = xsk_pool;
 
 	sq->stats = sq->xsk_pool ?
-- 
GitLab


From e54638a8380bd9c146a883035fffd0a821813682 Mon Sep 17 00:00:00 2001
From: Maor Dickman <maord@nvidia.com>
Date: Sun, 1 Aug 2021 14:45:17 +0300
Subject: [PATCH 793/875] net/mlx5e: Set geneve_tlv_option_0_exist when
 matching on geneve option

The cited patch added support of matching on geneve option by setting
geneve_tlv_option_0_data mask and key but didn't set geneve_tlv_option_0_exist
bit which is required on some HWs when matching geneve_tlv_option_0_data parameter,
this may cause in some cases for packets to wrongly match on rules with different
geneve option.

Example of such case is packet with geneve_tlv_object class=789 and data=456
will wrongly match on rule with match geneve_tlv_object class=123 and data=456.

Fix it by setting geneve_tlv_option_0_exist bit when supported by the HW when matching
on geneve_tlv_option_0_data parameter.

Fixes: 9272e3df3023 ("net/mlx5e: Geneve, Add support for encap/decap flows offload")
Signed-off-by: Maor Dickman <maord@nvidia.com>
Reviewed-by: Roi Dayan <roid@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
 drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_geneve.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_geneve.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_geneve.c
index f5b26f5a7de46..054d80c4e65cf 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_geneve.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_geneve.c
@@ -273,6 +273,11 @@ static int mlx5e_tc_tun_parse_geneve_options(struct mlx5e_priv *priv,
 		 geneve_tlv_option_0_data, be32_to_cpu(opt_data_key));
 	MLX5_SET(fte_match_set_misc3, misc_3_c,
 		 geneve_tlv_option_0_data, be32_to_cpu(opt_data_mask));
+	if (MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
+				       ft_field_support.geneve_tlv_option_0_exist)) {
+		MLX5_SET_TO_ONES(fte_match_set_misc, misc_c, geneve_tlv_option_0_exist);
+		MLX5_SET_TO_ONES(fte_match_set_misc, misc_v, geneve_tlv_option_0_exist);
+	}
 
 	spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_3;
 
-- 
GitLab


From 4d1c1379d71777ddeda3e54f8fc26e9ecbfd1009 Mon Sep 17 00:00:00 2001
From: Eli Cohen <elic@nvidia.com>
Date: Thu, 15 Dec 2022 14:28:34 +0200
Subject: [PATCH 794/875] net/mlx5: Lag, fix failure to cancel delayed bond
 work

Commit 0d4e8ed139d8 ("net/mlx5: Lag, avoid lockdep warnings")
accidentally removed a call to cancel delayed bond work thus it may
cause queued delay to expire and fall on an already destroyed work
queue.

Fix by restoring the call cancel_delayed_work_sync() before
destroying the workqueue.

This prevents call trace such as this:

[  329.230417] BUG: kernel NULL pointer dereference, address: 0000000000000000
 [  329.231444] #PF: supervisor write access in kernel mode
 [  329.232233] #PF: error_code(0x0002) - not-present page
 [  329.233007] PGD 0 P4D 0
 [  329.233476] Oops: 0002 [#1] SMP
 [  329.234012] CPU: 5 PID: 145 Comm: kworker/u20:4 Tainted: G OE      6.0.0-rc5_mlnx #1
 [  329.235282] Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS rel-1.13.0-0-gf21b5a4aeb02-prebuilt.qemu.org 04/01/2014
 [  329.236868] Workqueue: mlx5_cmd_0000:08:00.1 cmd_work_handler [mlx5_core]
 [  329.237886] RIP: 0010:_raw_spin_lock+0xc/0x20
 [  329.238585] Code: f0 0f b1 17 75 02 f3 c3 89 c6 e9 6f 3c 5f ff 66 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 0f 1f 44 00 00 31 c0 ba 01 00 00 00 <f0> 0f b1 17 75 02 f3 c3 89 c6 e9 45 3c 5f ff 0f 1f 44 00 00 0f 1f
 [  329.241156] RSP: 0018:ffffc900001b0e98 EFLAGS: 00010046
 [  329.241940] RAX: 0000000000000000 RBX: ffffffff82374ae0 RCX: 0000000000000000
 [  329.242954] RDX: 0000000000000001 RSI: 0000000000000014 RDI: 0000000000000000
 [  329.243974] RBP: ffff888106ccf000 R08: ffff8881004000c8 R09: ffff888100400000
 [  329.244990] R10: 0000000000000000 R11: ffffffff826669f8 R12: 0000000000002000
 [  329.246009] R13: 0000000000000005 R14: ffff888100aa7ce0 R15: ffff88852ca80000
 [  329.247030] FS:  0000000000000000(0000) GS:ffff88852ca80000(0000) knlGS:0000000000000000
 [  329.248260] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
 [  329.249111] CR2: 0000000000000000 CR3: 000000016d675001 CR4: 0000000000770ee0
 [  329.250133] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
 [  329.251152] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
 [  329.252176] PKRU: 55555554

Fixes: 0d4e8ed139d8 ("net/mlx5: Lag, avoid lockdep warnings")
Signed-off-by: Eli Cohen <elic@nvidia.com>
Reviewed-by: Maor Dickman <maord@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
 drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c
index 32c3e0a649a75..ad32b80e85018 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c
@@ -228,6 +228,7 @@ static void mlx5_ldev_free(struct kref *ref)
 	if (ldev->nb.notifier_call)
 		unregister_netdevice_notifier_net(&init_net, &ldev->nb);
 	mlx5_lag_mp_cleanup(ldev);
+	cancel_delayed_work_sync(&ldev->bond_work);
 	destroy_workqueue(ldev->wq);
 	mlx5_lag_mpesw_cleanup(ldev);
 	mutex_destroy(&ldev->lock);
-- 
GitLab


From 9ed1d9aeef5842ecacb660fce933613b58af1e00 Mon Sep 17 00:00:00 2001
From: Chuang Wang <nashuiliang@gmail.com>
Date: Sat, 24 Dec 2022 21:31:46 +0800
Subject: [PATCH 795/875] bpf: Fix panic due to wrong pageattr of im->image

In the scenario where livepatch and kretfunc coexist, the pageattr of
im->image is rox after arch_prepare_bpf_trampoline in
bpf_trampoline_update, and then modify_fentry or register_fentry returns
-EAGAIN from bpf_tramp_ftrace_ops_func, the BPF_TRAMP_F_ORIG_STACK flag
will be configured, and arch_prepare_bpf_trampoline will be re-executed.

At this time, because the pageattr of im->image is rox,
arch_prepare_bpf_trampoline will read and write im->image, which causes
a fault. as follows:

  insmod livepatch-sample.ko    # samples/livepatch/livepatch-sample.c
  bpftrace -e 'kretfunc:cmdline_proc_show {}'

BUG: unable to handle page fault for address: ffffffffa0206000
PGD 322d067 P4D 322d067 PUD 322e063 PMD 1297e067 PTE d428061
Oops: 0003 [#1] PREEMPT SMP PTI
CPU: 2 PID: 270 Comm: bpftrace Tainted: G            E K    6.1.0 #5
RIP: 0010:arch_prepare_bpf_trampoline+0xed/0x8c0
RSP: 0018:ffffc90001083ad8 EFLAGS: 00010202
RAX: ffffffffa0206000 RBX: 0000000000000020 RCX: 0000000000000000
RDX: ffffffffa0206001 RSI: ffffffffa0206000 RDI: 0000000000000030
RBP: ffffc90001083b70 R08: 0000000000000066 R09: ffff88800f51b400
R10: 000000002e72c6e5 R11: 00000000d0a15080 R12: ffff8880110a68c8
R13: 0000000000000000 R14: ffff88800f51b400 R15: ffffffff814fec10
FS:  00007f87bc0dc780(0000) GS:ffff88803e600000(0000) knlGS:0000000000000000
CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: ffffffffa0206000 CR3: 0000000010b70000 CR4: 00000000000006e0
DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
Call Trace:
<TASK>
 bpf_trampoline_update+0x25a/0x6b0
 __bpf_trampoline_link_prog+0x101/0x240
 bpf_trampoline_link_prog+0x2d/0x50
 bpf_tracing_prog_attach+0x24c/0x530
 bpf_raw_tp_link_attach+0x73/0x1d0
 __sys_bpf+0x100e/0x2570
 __x64_sys_bpf+0x1c/0x30
 do_syscall_64+0x5b/0x80
 entry_SYSCALL_64_after_hwframe+0x63/0xcd

With this patch, when modify_fentry or register_fentry returns -EAGAIN
from bpf_tramp_ftrace_ops_func, the pageattr of im->image will be reset
to nx+rw.

Cc: stable@vger.kernel.org
Fixes: 00963a2e75a8 ("bpf: Support bpf_trampoline on functions with IPMODIFY (e.g. livepatch)")
Signed-off-by: Chuang Wang <nashuiliang@gmail.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Acked-by: Song Liu <song@kernel.org>
Link: https://lore.kernel.org/r/20221224133146.780578-1-nashuiliang@gmail.com
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
---
 kernel/bpf/trampoline.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/kernel/bpf/trampoline.c b/kernel/bpf/trampoline.c
index 11f5ec0b80165..d0ed7d6f5eec5 100644
--- a/kernel/bpf/trampoline.c
+++ b/kernel/bpf/trampoline.c
@@ -488,6 +488,10 @@ again:
 		/* reset fops->func and fops->trampoline for re-register */
 		tr->fops->func = NULL;
 		tr->fops->trampoline = 0;
+
+		/* reset im->image memory attr for arch_prepare_bpf_trampoline */
+		set_memory_nx((long)im->image, 1);
+		set_memory_rw((long)im->image, 1);
 		goto again;
 	}
 #endif
-- 
GitLab


From 8f161ca1105a6af6614333f13aa7be4aab8b633a Mon Sep 17 00:00:00 2001
From: Alexei Starovoitov <ast@kernel.org>
Date: Wed, 28 Dec 2022 13:55:57 -0800
Subject: [PATCH 796/875] selftests/bpf: Temporarily disable part of
 btf_dump:var_data test.

Commit 7443b296e699 ("x86/percpu: Move cpu_number next to current_task")
moved global per_cpu variable 'cpu_number' into pcpu_hot structure.
Therefore this part of var_data test is no longer valid.
Disable it until better solution is found.

Signed-off-by: Alexei Starovoitov <ast@kernel.org>
---
 tools/testing/selftests/bpf/prog_tests/btf_dump.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/testing/selftests/bpf/prog_tests/btf_dump.c b/tools/testing/selftests/bpf/prog_tests/btf_dump.c
index 0ba2e8b9c6ace..e9ea38aa8248b 100644
--- a/tools/testing/selftests/bpf/prog_tests/btf_dump.c
+++ b/tools/testing/selftests/bpf/prog_tests/btf_dump.c
@@ -801,7 +801,7 @@ static void test_btf_dump_struct_data(struct btf *btf, struct btf_dump *d,
 static void test_btf_dump_var_data(struct btf *btf, struct btf_dump *d,
 				   char *str)
 {
-#if defined(__i386__) || defined(__x86_64__) || defined(__aarch64__)
+#if 0
 	TEST_BTF_DUMP_VAR(btf, d, NULL, str, "cpu_number", int, BTF_F_COMPACT,
 			  "int cpu_number = (int)100", 100);
 #endif
-- 
GitLab


From 7ff94f276f8ea05df82eb115225e9b26f47a3347 Mon Sep 17 00:00:00 2001
From: Kui-Feng Lee <kuifeng@meta.com>
Date: Fri, 16 Dec 2022 14:18:54 -0800
Subject: [PATCH 797/875] bpf: keep a reference to the mm, in case the task is
 dead.

Fix the system crash that happens when a task iterator travel through
vma of tasks.

In task iterators, we used to access mm by following the pointer on
the task_struct; however, the death of a task will clear the pointer,
even though we still hold the task_struct.  That can cause an
unexpected crash for a null pointer when an iterator is visiting a
task that dies during the visit.  Keeping a reference of mm on the
iterator ensures we always have a valid pointer to mm.

Co-developed-by: Song Liu <song@kernel.org>
Signed-off-by: Song Liu <song@kernel.org>
Signed-off-by: Kui-Feng Lee <kuifeng@meta.com>
Reported-by: Nathan Slingerland <slinger@meta.com>
Acked-by: Yonghong Song <yhs@fb.com>
Link: https://lore.kernel.org/r/20221216221855.4122288-2-kuifeng@meta.com
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
---
 kernel/bpf/task_iter.c | 39 +++++++++++++++++++++++++++------------
 1 file changed, 27 insertions(+), 12 deletions(-)

diff --git a/kernel/bpf/task_iter.c b/kernel/bpf/task_iter.c
index c2a2182ce5702..c4ab9d6cdbe9c 100644
--- a/kernel/bpf/task_iter.c
+++ b/kernel/bpf/task_iter.c
@@ -438,6 +438,7 @@ struct bpf_iter_seq_task_vma_info {
 	 */
 	struct bpf_iter_seq_task_common common;
 	struct task_struct *task;
+	struct mm_struct *mm;
 	struct vm_area_struct *vma;
 	u32 tid;
 	unsigned long prev_vm_start;
@@ -456,16 +457,19 @@ task_vma_seq_get_next(struct bpf_iter_seq_task_vma_info *info)
 	enum bpf_task_vma_iter_find_op op;
 	struct vm_area_struct *curr_vma;
 	struct task_struct *curr_task;
+	struct mm_struct *curr_mm;
 	u32 saved_tid = info->tid;
 
 	/* If this function returns a non-NULL vma, it holds a reference to
-	 * the task_struct, and holds read lock on vma->mm->mmap_lock.
+	 * the task_struct, holds a refcount on mm->mm_users, and holds
+	 * read lock on vma->mm->mmap_lock.
 	 * If this function returns NULL, it does not hold any reference or
 	 * lock.
 	 */
 	if (info->task) {
 		curr_task = info->task;
 		curr_vma = info->vma;
+		curr_mm = info->mm;
 		/* In case of lock contention, drop mmap_lock to unblock
 		 * the writer.
 		 *
@@ -504,13 +508,15 @@ task_vma_seq_get_next(struct bpf_iter_seq_task_vma_info *info)
 		 *    4.2) VMA2 and VMA2' covers different ranges, process
 		 *         VMA2'.
 		 */
-		if (mmap_lock_is_contended(curr_task->mm)) {
+		if (mmap_lock_is_contended(curr_mm)) {
 			info->prev_vm_start = curr_vma->vm_start;
 			info->prev_vm_end = curr_vma->vm_end;
 			op = task_vma_iter_find_vma;
-			mmap_read_unlock(curr_task->mm);
-			if (mmap_read_lock_killable(curr_task->mm))
+			mmap_read_unlock(curr_mm);
+			if (mmap_read_lock_killable(curr_mm)) {
+				mmput(curr_mm);
 				goto finish;
+			}
 		} else {
 			op = task_vma_iter_next_vma;
 		}
@@ -535,42 +541,47 @@ again:
 			op = task_vma_iter_find_vma;
 		}
 
-		if (!curr_task->mm)
+		curr_mm = get_task_mm(curr_task);
+		if (!curr_mm)
 			goto next_task;
 
-		if (mmap_read_lock_killable(curr_task->mm))
+		if (mmap_read_lock_killable(curr_mm)) {
+			mmput(curr_mm);
 			goto finish;
+		}
 	}
 
 	switch (op) {
 	case task_vma_iter_first_vma:
-		curr_vma = find_vma(curr_task->mm, 0);
+		curr_vma = find_vma(curr_mm, 0);
 		break;
 	case task_vma_iter_next_vma:
-		curr_vma = find_vma(curr_task->mm, curr_vma->vm_end);
+		curr_vma = find_vma(curr_mm, curr_vma->vm_end);
 		break;
 	case task_vma_iter_find_vma:
 		/* We dropped mmap_lock so it is necessary to use find_vma
 		 * to find the next vma. This is similar to the  mechanism
 		 * in show_smaps_rollup().
 		 */
-		curr_vma = find_vma(curr_task->mm, info->prev_vm_end - 1);
+		curr_vma = find_vma(curr_mm, info->prev_vm_end - 1);
 		/* case 1) and 4.2) above just use curr_vma */
 
 		/* check for case 2) or case 4.1) above */
 		if (curr_vma &&
 		    curr_vma->vm_start == info->prev_vm_start &&
 		    curr_vma->vm_end == info->prev_vm_end)
-			curr_vma = find_vma(curr_task->mm, curr_vma->vm_end);
+			curr_vma = find_vma(curr_mm, curr_vma->vm_end);
 		break;
 	}
 	if (!curr_vma) {
 		/* case 3) above, or case 2) 4.1) with vma->next == NULL */
-		mmap_read_unlock(curr_task->mm);
+		mmap_read_unlock(curr_mm);
+		mmput(curr_mm);
 		goto next_task;
 	}
 	info->task = curr_task;
 	info->vma = curr_vma;
+	info->mm = curr_mm;
 	return curr_vma;
 
 next_task:
@@ -579,6 +590,7 @@ next_task:
 
 	put_task_struct(curr_task);
 	info->task = NULL;
+	info->mm = NULL;
 	info->tid++;
 	goto again;
 
@@ -587,6 +599,7 @@ finish:
 		put_task_struct(curr_task);
 	info->task = NULL;
 	info->vma = NULL;
+	info->mm = NULL;
 	return NULL;
 }
 
@@ -658,7 +671,9 @@ static void task_vma_seq_stop(struct seq_file *seq, void *v)
 		 */
 		info->prev_vm_start = ~0UL;
 		info->prev_vm_end = info->vma->vm_end;
-		mmap_read_unlock(info->task->mm);
+		mmap_read_unlock(info->mm);
+		mmput(info->mm);
+		info->mm = NULL;
 		put_task_struct(info->task);
 		info->task = NULL;
 	}
-- 
GitLab


From b7793c8db7d9beb903bb42f52872b5b46abdcb88 Mon Sep 17 00:00:00 2001
From: Kui-Feng Lee <kuifeng@meta.com>
Date: Fri, 16 Dec 2022 14:18:55 -0800
Subject: [PATCH 798/875] selftests/bpf: add a test for iter/task_vma for
 short-lived processes

When a task iterator traverses vma(s), it is possible task->mm might
become invalid in the middle of traversal and this may cause kernel
misbehave (e.g., crash)

This test case creates iterators repeatedly and forks short-lived
processes in the background to detect this bug.  The test will last
for 3 seconds to get the chance to trigger the issue.

Signed-off-by: Kui-Feng Lee <kuifeng@meta.com>
Acked-by: Yonghong Song <yhs@fb.com>
Link: https://lore.kernel.org/r/20221216221855.4122288-3-kuifeng@meta.com
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
---
 .../selftests/bpf/prog_tests/bpf_iter.c       | 73 +++++++++++++++++++
 1 file changed, 73 insertions(+)

diff --git a/tools/testing/selftests/bpf/prog_tests/bpf_iter.c b/tools/testing/selftests/bpf/prog_tests/bpf_iter.c
index 6f8ed61fc4b4a..3af6450763e9a 100644
--- a/tools/testing/selftests/bpf/prog_tests/bpf_iter.c
+++ b/tools/testing/selftests/bpf/prog_tests/bpf_iter.c
@@ -1465,6 +1465,77 @@ out:
 	bpf_iter_task_vma__destroy(skel);
 }
 
+static void test_task_vma_dead_task(void)
+{
+	struct bpf_iter_task_vma *skel;
+	int wstatus, child_pid = -1;
+	time_t start_tm, cur_tm;
+	int err, iter_fd = -1;
+	int wait_sec = 3;
+
+	skel = bpf_iter_task_vma__open();
+	if (!ASSERT_OK_PTR(skel, "bpf_iter_task_vma__open"))
+		return;
+
+	skel->bss->pid = getpid();
+
+	err = bpf_iter_task_vma__load(skel);
+	if (!ASSERT_OK(err, "bpf_iter_task_vma__load"))
+		goto out;
+
+	skel->links.proc_maps = bpf_program__attach_iter(
+		skel->progs.proc_maps, NULL);
+
+	if (!ASSERT_OK_PTR(skel->links.proc_maps, "bpf_program__attach_iter")) {
+		skel->links.proc_maps = NULL;
+		goto out;
+	}
+
+	start_tm = time(NULL);
+	cur_tm = start_tm;
+
+	child_pid = fork();
+	if (child_pid == 0) {
+		/* Fork short-lived processes in the background. */
+		while (cur_tm < start_tm + wait_sec) {
+			system("echo > /dev/null");
+			cur_tm = time(NULL);
+		}
+		exit(0);
+	}
+
+	if (!ASSERT_GE(child_pid, 0, "fork_child"))
+		goto out;
+
+	while (cur_tm < start_tm + wait_sec) {
+		iter_fd = bpf_iter_create(bpf_link__fd(skel->links.proc_maps));
+		if (!ASSERT_GE(iter_fd, 0, "create_iter"))
+			goto out;
+
+		/* Drain all data from iter_fd. */
+		while (cur_tm < start_tm + wait_sec) {
+			err = read_fd_into_buffer(iter_fd, task_vma_output, CMP_BUFFER_SIZE);
+			if (!ASSERT_GE(err, 0, "read_iter_fd"))
+				goto out;
+
+			cur_tm = time(NULL);
+
+			if (err == 0)
+				break;
+		}
+
+		close(iter_fd);
+		iter_fd = -1;
+	}
+
+	check_bpf_link_info(skel->progs.proc_maps);
+
+out:
+	waitpid(child_pid, &wstatus, 0);
+	close(iter_fd);
+	bpf_iter_task_vma__destroy(skel);
+}
+
 void test_bpf_sockmap_map_iter_fd(void)
 {
 	struct bpf_iter_sockmap *skel;
@@ -1586,6 +1657,8 @@ void test_bpf_iter(void)
 		test_task_file();
 	if (test__start_subtest("task_vma"))
 		test_task_vma();
+	if (test__start_subtest("task_vma_dead_task"))
+		test_task_vma_dead_task();
 	if (test__start_subtest("task_btf"))
 		test_task_btf();
 	if (test__start_subtest("tcp4"))
-- 
GitLab


From 45435d8da71f9f3e6860e6e6ea9667b6ec17ec64 Mon Sep 17 00:00:00 2001
From: Kees Cook <keescook@chromium.org>
Date: Fri, 23 Dec 2022 10:28:44 -0800
Subject: [PATCH 799/875] bpf: Always use maximal size for copy_array()

Instead of counting on prior allocations to have sized allocations to
the next kmalloc bucket size, always perform a krealloc that is at least
ksize(dst) in size (which is a no-op), so the size can be correctly
tracked by all the various allocation size trackers (KASAN,
__alloc_size, etc).

Reported-by: Hyunwoo Kim <v4bel@theori.io>
Link: https://lore.kernel.org/bpf/20221223094551.GA1439509@ubuntu
Fixes: ceb35b666d42 ("bpf/verifier: Use kmalloc_size_roundup() to match ksize() usage")
Cc: Alexei Starovoitov <ast@kernel.org>
Cc: Daniel Borkmann <daniel@iogearbox.net>
Cc: John Fastabend <john.fastabend@gmail.com>
Cc: Andrii Nakryiko <andrii@kernel.org>
Cc: Martin KaFai Lau <martin.lau@linux.dev>
Cc: Song Liu <song@kernel.org>
Cc: Yonghong Song <yhs@fb.com>
Cc: KP Singh <kpsingh@kernel.org>
Cc: Stanislav Fomichev <sdf@google.com>
Cc: Hao Luo <haoluo@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: bpf@vger.kernel.org
Signed-off-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/r/20221223182836.never.866-kees@kernel.org
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
---
 kernel/bpf/verifier.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c
index 243d06ce68426..85f96c1e9f62f 100644
--- a/kernel/bpf/verifier.c
+++ b/kernel/bpf/verifier.c
@@ -1054,6 +1054,8 @@ static void print_insn_state(struct bpf_verifier_env *env,
  */
 static void *copy_array(void *dst, const void *src, size_t n, size_t size, gfp_t flags)
 {
+	size_t alloc_bytes;
+	void *orig = dst;
 	size_t bytes;
 
 	if (ZERO_OR_NULL_PTR(src))
@@ -1062,11 +1064,11 @@ static void *copy_array(void *dst, const void *src, size_t n, size_t size, gfp_t
 	if (unlikely(check_mul_overflow(n, size, &bytes)))
 		return NULL;
 
-	if (ksize(dst) < ksize(src)) {
-		kfree(dst);
-		dst = kmalloc_track_caller(kmalloc_size_roundup(bytes), flags);
-		if (!dst)
-			return NULL;
+	alloc_bytes = max(ksize(orig), kmalloc_size_roundup(bytes));
+	dst = krealloc(orig, alloc_bytes, flags);
+	if (!dst) {
+		kfree(orig);
+		return NULL;
 	}
 
 	memcpy(dst, src, bytes);
-- 
GitLab


From da8daff9405e55baa1f797b77a7c629a89f4d764 Mon Sep 17 00:00:00 2001
From: Bhaskar Chowdhury <unixbhaskar@gmail.com>
Date: Sat, 17 Dec 2022 11:21:48 +0530
Subject: [PATCH 800/875] kconfig: Add static text for search information in
 help menu

Add few static text to explain how one can bring up the search dialog
box by pressing the forward slash key anywhere on this interface.

Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
---
 scripts/kconfig/mconf.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/scripts/kconfig/mconf.c b/scripts/kconfig/mconf.c
index 9c549683c6275..e67e0db50b2e2 100644
--- a/scripts/kconfig/mconf.c
+++ b/scripts/kconfig/mconf.c
@@ -161,6 +161,12 @@ static const char mconf_readme[] =
 "(especially with a larger number of unrolled categories) than the\n"
 "default mode.\n"
 "\n"
+
+"Search\n"
+"-------\n"
+"Pressing the forward-slash (/) anywhere brings up a search dialog box.\n"
+"\n"
+
 "Different color themes available\n"
 "--------------------------------\n"
 "It is possible to select different color themes using the variable\n"
-- 
GitLab


From 936a192f974018b4f6040f6f77b1cc1e75bd8666 Mon Sep 17 00:00:00 2001
From: Kuniyuki Iwashima <kuniyu@amazon.com>
Date: Mon, 26 Dec 2022 22:27:52 +0900
Subject: [PATCH 801/875] tcp: Add TIME_WAIT sockets in bhash2.

Jiri Slaby reported regression of bind() with a simple repro. [0]

The repro creates a TIME_WAIT socket and tries to bind() a new socket
with the same local address and port.  Before commit 28044fc1d495 ("net:
Add a bhash2 table hashed by port and address"), the bind() failed with
-EADDRINUSE, but now it succeeds.

The cited commit should have put TIME_WAIT sockets into bhash2; otherwise,
inet_bhash2_conflict() misses TIME_WAIT sockets when validating bind()
requests if the address is not a wildcard one.

The straight option is to move sk_bind2_node from struct sock to struct
sock_common to add twsk to bhash2 as implemented as RFC. [1]  However, the
binary layout change in the struct sock could affect performances moving
hot fields on different cachelines.

To avoid that, we add another TIME_WAIT list in inet_bind2_bucket and check
it while validating bind().

[0]: https://lore.kernel.org/netdev/6b971a4e-c7d8-411e-1f92-fda29b5b2fb9@kernel.org/
[1]: https://lore.kernel.org/netdev/20221221151258.25748-2-kuniyu@amazon.com/

Fixes: 28044fc1d495 ("net: Add a bhash2 table hashed by port and address")
Reported-by: Jiri Slaby <jirislaby@kernel.org>
Suggested-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Kuniyuki Iwashima <kuniyu@amazon.com>
Acked-by: Joanne Koong <joannelkoong@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 include/net/inet_hashtables.h    |  4 ++++
 include/net/inet_timewait_sock.h |  5 +++++
 net/ipv4/inet_connection_sock.c  | 26 ++++++++++++++++++++++----
 net/ipv4/inet_hashtables.c       |  8 +++++---
 net/ipv4/inet_timewait_sock.c    | 31 +++++++++++++++++++++++++++++--
 5 files changed, 65 insertions(+), 9 deletions(-)

diff --git a/include/net/inet_hashtables.h b/include/net/inet_hashtables.h
index 69174093078f0..99bd823e97f62 100644
--- a/include/net/inet_hashtables.h
+++ b/include/net/inet_hashtables.h
@@ -108,6 +108,10 @@ struct inet_bind2_bucket {
 	struct hlist_node	node;
 	/* List of sockets hashed to this bucket */
 	struct hlist_head	owners;
+	/* bhash has twsk in owners, but bhash2 has twsk in
+	 * deathrow not to add a member in struct sock_common.
+	 */
+	struct hlist_head	deathrow;
 };
 
 static inline struct net *ib_net(const struct inet_bind_bucket *ib)
diff --git a/include/net/inet_timewait_sock.h b/include/net/inet_timewait_sock.h
index 5b47545f22d39..4a8e578405cb3 100644
--- a/include/net/inet_timewait_sock.h
+++ b/include/net/inet_timewait_sock.h
@@ -73,9 +73,14 @@ struct inet_timewait_sock {
 	u32			tw_priority;
 	struct timer_list	tw_timer;
 	struct inet_bind_bucket	*tw_tb;
+	struct inet_bind2_bucket	*tw_tb2;
+	struct hlist_node		tw_bind2_node;
 };
 #define tw_tclass tw_tos
 
+#define twsk_for_each_bound_bhash2(__tw, list) \
+	hlist_for_each_entry(__tw, list, tw_bind2_node)
+
 static inline struct inet_timewait_sock *inet_twsk(const struct sock *sk)
 {
 	return (struct inet_timewait_sock *)sk;
diff --git a/net/ipv4/inet_connection_sock.c b/net/ipv4/inet_connection_sock.c
index b366ab9148f2d..848ffc3e0239c 100644
--- a/net/ipv4/inet_connection_sock.c
+++ b/net/ipv4/inet_connection_sock.c
@@ -173,22 +173,40 @@ static bool inet_bind_conflict(const struct sock *sk, struct sock *sk2,
 	return false;
 }
 
+static bool __inet_bhash2_conflict(const struct sock *sk, struct sock *sk2,
+				   kuid_t sk_uid, bool relax,
+				   bool reuseport_cb_ok, bool reuseport_ok)
+{
+	if (sk->sk_family == AF_INET && ipv6_only_sock(sk2))
+		return false;
+
+	return inet_bind_conflict(sk, sk2, sk_uid, relax,
+				  reuseport_cb_ok, reuseport_ok);
+}
+
 static bool inet_bhash2_conflict(const struct sock *sk,
 				 const struct inet_bind2_bucket *tb2,
 				 kuid_t sk_uid,
 				 bool relax, bool reuseport_cb_ok,
 				 bool reuseport_ok)
 {
+	struct inet_timewait_sock *tw2;
 	struct sock *sk2;
 
 	sk_for_each_bound_bhash2(sk2, &tb2->owners) {
-		if (sk->sk_family == AF_INET && ipv6_only_sock(sk2))
-			continue;
+		if (__inet_bhash2_conflict(sk, sk2, sk_uid, relax,
+					   reuseport_cb_ok, reuseport_ok))
+			return true;
+	}
 
-		if (inet_bind_conflict(sk, sk2, sk_uid, relax,
-				       reuseport_cb_ok, reuseport_ok))
+	twsk_for_each_bound_bhash2(tw2, &tb2->deathrow) {
+		sk2 = (struct sock *)tw2;
+
+		if (__inet_bhash2_conflict(sk, sk2, sk_uid, relax,
+					   reuseport_cb_ok, reuseport_ok))
 			return true;
 	}
+
 	return false;
 }
 
diff --git a/net/ipv4/inet_hashtables.c b/net/ipv4/inet_hashtables.c
index d039b4e732a31..24a38b56fab9e 100644
--- a/net/ipv4/inet_hashtables.c
+++ b/net/ipv4/inet_hashtables.c
@@ -116,6 +116,7 @@ static void inet_bind2_bucket_init(struct inet_bind2_bucket *tb,
 #endif
 		tb->rcv_saddr = sk->sk_rcv_saddr;
 	INIT_HLIST_HEAD(&tb->owners);
+	INIT_HLIST_HEAD(&tb->deathrow);
 	hlist_add_head(&tb->node, &head->chain);
 }
 
@@ -137,7 +138,7 @@ struct inet_bind2_bucket *inet_bind2_bucket_create(struct kmem_cache *cachep,
 /* Caller must hold hashbucket lock for this tb with local BH disabled */
 void inet_bind2_bucket_destroy(struct kmem_cache *cachep, struct inet_bind2_bucket *tb)
 {
-	if (hlist_empty(&tb->owners)) {
+	if (hlist_empty(&tb->owners) && hlist_empty(&tb->deathrow)) {
 		__hlist_del(&tb->node);
 		kmem_cache_free(cachep, tb);
 	}
@@ -1103,15 +1104,16 @@ ok:
 	/* Head lock still held and bh's disabled */
 	inet_bind_hash(sk, tb, tb2, port);
 
-	spin_unlock(&head2->lock);
-
 	if (sk_unhashed(sk)) {
 		inet_sk(sk)->inet_sport = htons(port);
 		inet_ehash_nolisten(sk, (struct sock *)tw, NULL);
 	}
 	if (tw)
 		inet_twsk_bind_unhash(tw, hinfo);
+
+	spin_unlock(&head2->lock);
 	spin_unlock(&head->lock);
+
 	if (tw)
 		inet_twsk_deschedule_put(tw);
 	local_bh_enable();
diff --git a/net/ipv4/inet_timewait_sock.c b/net/ipv4/inet_timewait_sock.c
index 66fc940f9521a..1d77d992e6e77 100644
--- a/net/ipv4/inet_timewait_sock.c
+++ b/net/ipv4/inet_timewait_sock.c
@@ -29,6 +29,7 @@
 void inet_twsk_bind_unhash(struct inet_timewait_sock *tw,
 			  struct inet_hashinfo *hashinfo)
 {
+	struct inet_bind2_bucket *tb2 = tw->tw_tb2;
 	struct inet_bind_bucket *tb = tw->tw_tb;
 
 	if (!tb)
@@ -37,6 +38,11 @@ void inet_twsk_bind_unhash(struct inet_timewait_sock *tw,
 	__hlist_del(&tw->tw_bind_node);
 	tw->tw_tb = NULL;
 	inet_bind_bucket_destroy(hashinfo->bind_bucket_cachep, tb);
+
+	__hlist_del(&tw->tw_bind2_node);
+	tw->tw_tb2 = NULL;
+	inet_bind2_bucket_destroy(hashinfo->bind2_bucket_cachep, tb2);
+
 	__sock_put((struct sock *)tw);
 }
 
@@ -45,7 +51,7 @@ static void inet_twsk_kill(struct inet_timewait_sock *tw)
 {
 	struct inet_hashinfo *hashinfo = tw->tw_dr->hashinfo;
 	spinlock_t *lock = inet_ehash_lockp(hashinfo, tw->tw_hash);
-	struct inet_bind_hashbucket *bhead;
+	struct inet_bind_hashbucket *bhead, *bhead2;
 
 	spin_lock(lock);
 	sk_nulls_del_node_init_rcu((struct sock *)tw);
@@ -54,9 +60,13 @@ static void inet_twsk_kill(struct inet_timewait_sock *tw)
 	/* Disassociate with bind bucket. */
 	bhead = &hashinfo->bhash[inet_bhashfn(twsk_net(tw), tw->tw_num,
 			hashinfo->bhash_size)];
+	bhead2 = inet_bhashfn_portaddr(hashinfo, (struct sock *)tw,
+				       twsk_net(tw), tw->tw_num);
 
 	spin_lock(&bhead->lock);
+	spin_lock(&bhead2->lock);
 	inet_twsk_bind_unhash(tw, hashinfo);
+	spin_unlock(&bhead2->lock);
 	spin_unlock(&bhead->lock);
 
 	refcount_dec(&tw->tw_dr->tw_refcount);
@@ -93,6 +103,12 @@ static void inet_twsk_add_bind_node(struct inet_timewait_sock *tw,
 	hlist_add_head(&tw->tw_bind_node, list);
 }
 
+static void inet_twsk_add_bind2_node(struct inet_timewait_sock *tw,
+				     struct hlist_head *list)
+{
+	hlist_add_head(&tw->tw_bind2_node, list);
+}
+
 /*
  * Enter the time wait state. This is called with locally disabled BH.
  * Essentially we whip up a timewait bucket, copy the relevant info into it
@@ -105,17 +121,28 @@ void inet_twsk_hashdance(struct inet_timewait_sock *tw, struct sock *sk,
 	const struct inet_connection_sock *icsk = inet_csk(sk);
 	struct inet_ehash_bucket *ehead = inet_ehash_bucket(hashinfo, sk->sk_hash);
 	spinlock_t *lock = inet_ehash_lockp(hashinfo, sk->sk_hash);
-	struct inet_bind_hashbucket *bhead;
+	struct inet_bind_hashbucket *bhead, *bhead2;
+
 	/* Step 1: Put TW into bind hash. Original socket stays there too.
 	   Note, that any socket with inet->num != 0 MUST be bound in
 	   binding cache, even if it is closed.
 	 */
 	bhead = &hashinfo->bhash[inet_bhashfn(twsk_net(tw), inet->inet_num,
 			hashinfo->bhash_size)];
+	bhead2 = inet_bhashfn_portaddr(hashinfo, sk, twsk_net(tw), inet->inet_num);
+
 	spin_lock(&bhead->lock);
+	spin_lock(&bhead2->lock);
+
 	tw->tw_tb = icsk->icsk_bind_hash;
 	WARN_ON(!icsk->icsk_bind_hash);
 	inet_twsk_add_bind_node(tw, &tw->tw_tb->owners);
+
+	tw->tw_tb2 = icsk->icsk_bind2_hash;
+	WARN_ON(!icsk->icsk_bind2_hash);
+	inet_twsk_add_bind2_node(tw, &tw->tw_tb2->deathrow);
+
+	spin_unlock(&bhead2->lock);
 	spin_unlock(&bhead->lock);
 
 	spin_lock(lock);
-- 
GitLab


From 2c042e8e54efb2b8e25ed0cb28224e79948dc8ce Mon Sep 17 00:00:00 2001
From: Kuniyuki Iwashima <kuniyu@amazon.com>
Date: Mon, 26 Dec 2022 22:27:53 +0900
Subject: [PATCH 802/875] tcp: Add selftest for bind() and TIME_WAIT.

bhash2 split the bind() validation logic into wildcard and non-wildcard
cases.  Let's add a test to catch future regression.

Before the previous patch:

  # ./bind_timewait
  TAP version 13
  1..2
  # Starting 2 tests from 3 test cases.
  #  RUN           bind_timewait.localhost.1 ...
  # bind_timewait.c:87:1:Expected ret (0) == -1 (-1)
  # 1: Test terminated by assertion
  #          FAIL  bind_timewait.localhost.1
  not ok 1 bind_timewait.localhost.1
  #  RUN           bind_timewait.addrany.1 ...
  #            OK  bind_timewait.addrany.1
  ok 2 bind_timewait.addrany.1
  # FAILED: 1 / 2 tests passed.
  # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0

After:

  # ./bind_timewait
  TAP version 13
  1..2
  # Starting 2 tests from 3 test cases.
  #  RUN           bind_timewait.localhost.1 ...
  #            OK  bind_timewait.localhost.1
  ok 1 bind_timewait.localhost.1
  #  RUN           bind_timewait.addrany.1 ...
  #            OK  bind_timewait.addrany.1
  ok 2 bind_timewait.addrany.1
  # PASSED: 2 / 2 tests passed.
  # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0

Signed-off-by: Kuniyuki Iwashima <kuniyu@amazon.com>
Acked-by: Joanne Koong <joannelkoong@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 tools/testing/selftests/net/.gitignore      |  1 +
 tools/testing/selftests/net/bind_timewait.c | 92 +++++++++++++++++++++
 2 files changed, 93 insertions(+)
 create mode 100644 tools/testing/selftests/net/bind_timewait.c

diff --git a/tools/testing/selftests/net/.gitignore b/tools/testing/selftests/net/.gitignore
index 9cc84114741d3..a6911cae368c7 100644
--- a/tools/testing/selftests/net/.gitignore
+++ b/tools/testing/selftests/net/.gitignore
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
 bind_bhash
+bind_timewait
 csum
 cmsg_sender
 diag_uid
diff --git a/tools/testing/selftests/net/bind_timewait.c b/tools/testing/selftests/net/bind_timewait.c
new file mode 100644
index 0000000000000..cb9fdf51ea59f
--- /dev/null
+++ b/tools/testing/selftests/net/bind_timewait.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright Amazon.com Inc. or its affiliates. */
+
+#include <sys/socket.h>
+#include <netinet/in.h>
+
+#include "../kselftest_harness.h"
+
+FIXTURE(bind_timewait)
+{
+	struct sockaddr_in addr;
+	socklen_t addrlen;
+};
+
+FIXTURE_VARIANT(bind_timewait)
+{
+	__u32 addr_const;
+};
+
+FIXTURE_VARIANT_ADD(bind_timewait, localhost)
+{
+	.addr_const = INADDR_LOOPBACK
+};
+
+FIXTURE_VARIANT_ADD(bind_timewait, addrany)
+{
+	.addr_const = INADDR_ANY
+};
+
+FIXTURE_SETUP(bind_timewait)
+{
+	self->addr.sin_family = AF_INET;
+	self->addr.sin_port = 0;
+	self->addr.sin_addr.s_addr = htonl(variant->addr_const);
+	self->addrlen = sizeof(self->addr);
+}
+
+FIXTURE_TEARDOWN(bind_timewait)
+{
+}
+
+void create_timewait_socket(struct __test_metadata *_metadata,
+			    FIXTURE_DATA(bind_timewait) *self)
+{
+	int server_fd, client_fd, child_fd, ret;
+	struct sockaddr_in addr;
+	socklen_t addrlen;
+
+	server_fd = socket(AF_INET, SOCK_STREAM, 0);
+	ASSERT_GT(server_fd, 0);
+
+	ret = bind(server_fd, (struct sockaddr *)&self->addr, self->addrlen);
+	ASSERT_EQ(ret, 0);
+
+	ret = listen(server_fd, 1);
+	ASSERT_EQ(ret, 0);
+
+	ret = getsockname(server_fd, (struct sockaddr *)&self->addr, &self->addrlen);
+	ASSERT_EQ(ret, 0);
+
+	client_fd = socket(AF_INET, SOCK_STREAM, 0);
+	ASSERT_GT(client_fd, 0);
+
+	ret = connect(client_fd, (struct sockaddr *)&self->addr, self->addrlen);
+	ASSERT_EQ(ret, 0);
+
+	addrlen = sizeof(addr);
+	child_fd = accept(server_fd, (struct sockaddr *)&addr, &addrlen);
+	ASSERT_GT(child_fd, 0);
+
+	close(child_fd);
+	close(client_fd);
+	close(server_fd);
+}
+
+TEST_F(bind_timewait, 1)
+{
+	int fd, ret;
+
+	create_timewait_socket(_metadata, self);
+
+	fd = socket(AF_INET, SOCK_STREAM, 0);
+	ASSERT_GT(fd, 0);
+
+	ret = bind(fd, (struct sockaddr *)&self->addr, self->addrlen);
+	ASSERT_EQ(ret, -1);
+	ASSERT_EQ(errno, EADDRINUSE);
+
+	close(fd);
+}
+
+TEST_HARNESS_MAIN
-- 
GitLab


From 6b57bffa5f675a01c7981ed271e8521e87441abd Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Tue, 27 Dec 2022 22:45:07 +0100
Subject: [PATCH 803/875] net: ethernet: broadcom: bcm63xx_enet: Drop empty
 platform remove function
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

A remove callback just returning 0 is equivalent to no remove callback
at all. So drop the useless function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/broadcom/bcm63xx_enet.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/net/ethernet/broadcom/bcm63xx_enet.c b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
index d91fdb0c2649d..2cf96892e5650 100644
--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
@@ -2784,17 +2784,11 @@ static int bcm_enet_shared_probe(struct platform_device *pdev)
 	return 0;
 }
 
-static int bcm_enet_shared_remove(struct platform_device *pdev)
-{
-	return 0;
-}
-
 /* this "shared" driver is needed because both macs share a single
  * address space
  */
 struct platform_driver bcm63xx_enet_shared_driver = {
 	.probe	= bcm_enet_shared_probe,
-	.remove	= bcm_enet_shared_remove,
 	.driver	= {
 		.name	= "bcm63xx_enet_shared",
 		.owner  = THIS_MODULE,
-- 
GitLab


From af691c94d022440476b76560d310d6fea790cc60 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Date: Tue, 27 Dec 2022 22:45:08 +0100
Subject: [PATCH 804/875] net: ethernet: freescale: enetc: Drop empty platform
 remove function
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

A remove callback just returning 0 is equivalent to no remove callback
at all. So drop the useless function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/freescale/enetc/enetc_ierb.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/net/ethernet/freescale/enetc/enetc_ierb.c b/drivers/net/ethernet/freescale/enetc/enetc_ierb.c
index 91f02c5050285..b307bef4dc298 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc_ierb.c
+++ b/drivers/net/ethernet/freescale/enetc/enetc_ierb.c
@@ -127,11 +127,6 @@ static int enetc_ierb_probe(struct platform_device *pdev)
 	return 0;
 }
 
-static int enetc_ierb_remove(struct platform_device *pdev)
-{
-	return 0;
-}
-
 static const struct of_device_id enetc_ierb_match[] = {
 	{ .compatible = "fsl,ls1028a-enetc-ierb", },
 	{},
@@ -144,7 +139,6 @@ static struct platform_driver enetc_ierb_driver = {
 		.of_match_table = enetc_ierb_match,
 	},
 	.probe = enetc_ierb_probe,
-	.remove = enetc_ierb_remove,
 };
 
 module_platform_driver(enetc_ierb_driver);
-- 
GitLab


From fec7352117fa301bfbc31bacc14bb9a579376b36 Mon Sep 17 00:00:00 2001
From: Jian Shen <shenjian15@huawei.com>
Date: Wed, 28 Dec 2022 14:27:49 +0800
Subject: [PATCH 805/875] net: hns3: refine the handling for VF heartbeat

Currently, the PF check the VF alive by the KEEP_ALVE
mailbox from VF. VF keep sending the mailbox per 2
seconds. Once PF lost the mailbox for more than 8
seconds, it will regards the VF is abnormal, and stop
notifying the state change to VF, include link state,
vf mac, reset, even though it receives the KEEP_ALIVE
mailbox again. It's inreasonable.

This patch fixes it. PF will record the state change which
need to notify VF when lost the VF's KEEP_ALIVE mailbox.
And notify VF when receive the mailbox again. Introduce a
new flag HCLGE_VPORT_STATE_INITED, used to distinguish the
case whether VF driver loaded or not. For VF will query
these states when initializing, so it's unnecessary to
notify it in this case.

Fixes: aa5c4f175be6 ("net: hns3: add reset handling for VF when doing PF reset")
Signed-off-by: Jian Shen <shenjian15@huawei.com>
Signed-off-by: Hao Lan <lanhao@huawei.com>
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 .../hisilicon/hns3/hns3pf/hclge_main.c        | 57 +++++++++++----
 .../hisilicon/hns3/hns3pf/hclge_main.h        |  7 ++
 .../hisilicon/hns3/hns3pf/hclge_mbx.c         | 71 ++++++++++++++++---
 3 files changed, 112 insertions(+), 23 deletions(-)

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index 6c2742f59c777..07ad5f35219e2 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -3910,9 +3910,17 @@ static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset)
 			return ret;
 		}
 
-		if (!reset || !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
+		if (!reset ||
+		    !test_bit(HCLGE_VPORT_STATE_INITED, &vport->state))
 			continue;
 
+		if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) &&
+		    hdev->reset_type == HNAE3_FUNC_RESET) {
+			set_bit(HCLGE_VPORT_NEED_NOTIFY_RESET,
+				&vport->need_notify);
+			continue;
+		}
+
 		/* Inform VF to process the reset.
 		 * hclge_inform_reset_assert_to_vf may fail if VF
 		 * driver is not loaded.
@@ -4609,18 +4617,25 @@ static void hclge_reset_service_task(struct hclge_dev *hdev)
 
 static void hclge_update_vport_alive(struct hclge_dev *hdev)
 {
+#define HCLGE_ALIVE_SECONDS_NORMAL		8
+
+	unsigned long alive_time = HCLGE_ALIVE_SECONDS_NORMAL * HZ;
 	int i;
 
 	/* start from vport 1 for PF is always alive */
 	for (i = 1; i < hdev->num_alloc_vport; i++) {
 		struct hclge_vport *vport = &hdev->vport[i];
 
-		if (time_after(jiffies, vport->last_active_jiffies + 8 * HZ))
+		if (!test_bit(HCLGE_VPORT_STATE_INITED, &vport->state) ||
+		    !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
+			continue;
+		if (time_after(jiffies, vport->last_active_jiffies +
+			       alive_time)) {
 			clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
-
-		/* If vf is not alive, set to default value */
-		if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
-			vport->mps = HCLGE_MAC_DEFAULT_FRAME;
+			dev_warn(&hdev->pdev->dev,
+				 "VF %u heartbeat timeout\n",
+				 i - HCLGE_VF_VPORT_START_NUM);
+		}
 	}
 }
 
@@ -8064,9 +8079,11 @@ int hclge_vport_start(struct hclge_vport *vport)
 {
 	struct hclge_dev *hdev = vport->back;
 
+	set_bit(HCLGE_VPORT_STATE_INITED, &vport->state);
 	set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
 	set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
 	vport->last_active_jiffies = jiffies;
+	vport->need_notify = 0;
 
 	if (test_bit(vport->vport_id, hdev->vport_config_block)) {
 		if (vport->vport_id) {
@@ -8084,7 +8101,9 @@ int hclge_vport_start(struct hclge_vport *vport)
 
 void hclge_vport_stop(struct hclge_vport *vport)
 {
+	clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state);
 	clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
+	vport->need_notify = 0;
 }
 
 static int hclge_client_start(struct hnae3_handle *handle)
@@ -9208,7 +9227,8 @@ static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf,
 		return 0;
 	}
 
-	dev_info(&hdev->pdev->dev, "MAC of VF %d has been set to %s\n",
+	dev_info(&hdev->pdev->dev,
+		 "MAC of VF %d has been set to %s, will be active after VF reset\n",
 		 vf, format_mac_addr);
 	return 0;
 }
@@ -10465,12 +10485,16 @@ static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
 	 * for DEVICE_VERSION_V3, vf doesn't need to know about the port based
 	 * VLAN state.
 	 */
-	if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3 &&
-	    test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
-		(void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0],
-							vport->vport_id,
-							state, &vlan_info);
-
+	if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) {
+		if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
+			(void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0],
+								vport->vport_id,
+								state,
+								&vlan_info);
+		else
+			set_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN,
+				&vport->need_notify);
+	}
 	return 0;
 }
 
@@ -11941,7 +11965,7 @@ static void hclge_reset_vport_state(struct hclge_dev *hdev)
 	int i;
 
 	for (i = 0; i < hdev->num_alloc_vport; i++) {
-		hclge_vport_stop(vport);
+		clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
 		vport++;
 	}
 }
@@ -12955,6 +12979,11 @@ static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid)
 	struct hclge_vlan_info vlan_info;
 	int ret;
 
+	clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state);
+	clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
+	vport->need_notify = 0;
+	vport->mps = 0;
+
 	/* after disable sriov, clean VF rate configured by PF */
 	ret = hclge_tm_qs_shaper_cfg(vport, 0);
 	if (ret)
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
index 495b639b0dc24..13f23d606e77b 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
@@ -995,9 +995,15 @@ enum HCLGE_VPORT_STATE {
 	HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
 	HCLGE_VPORT_STATE_PROMISC_CHANGE,
 	HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
+	HCLGE_VPORT_STATE_INITED,
 	HCLGE_VPORT_STATE_MAX
 };
 
+enum HCLGE_VPORT_NEED_NOTIFY {
+	HCLGE_VPORT_NEED_NOTIFY_RESET,
+	HCLGE_VPORT_NEED_NOTIFY_VF_VLAN,
+};
+
 struct hclge_vlan_info {
 	u16 vlan_proto; /* so far support 802.1Q only */
 	u16 qos;
@@ -1044,6 +1050,7 @@ struct hclge_vport {
 	struct hnae3_handle roce;
 
 	unsigned long state;
+	unsigned long need_notify;
 	unsigned long last_active_jiffies;
 	u32 mps; /* Max packet size */
 	struct hclge_vf_info vf_info;
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
index a7b06c63143cc..04ff9bf121853 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
@@ -124,17 +124,26 @@ static int hclge_send_mbx_msg(struct hclge_vport *vport, u8 *msg, u16 msg_len,
 	return status;
 }
 
+static int hclge_inform_vf_reset(struct hclge_vport *vport, u16 reset_type)
+{
+	__le16 msg_data;
+	u8 dest_vfid;
+
+	dest_vfid = (u8)vport->vport_id;
+	msg_data = cpu_to_le16(reset_type);
+
+	/* send this requested info to VF */
+	return hclge_send_mbx_msg(vport, (u8 *)&msg_data, sizeof(msg_data),
+				  HCLGE_MBX_ASSERTING_RESET, dest_vfid);
+}
+
 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport)
 {
 	struct hclge_dev *hdev = vport->back;
-	__le16 msg_data;
 	u16 reset_type;
-	u8 dest_vfid;
 
 	BUILD_BUG_ON(HNAE3_MAX_RESET > U16_MAX);
 
-	dest_vfid = (u8)vport->vport_id;
-
 	if (hdev->reset_type == HNAE3_FUNC_RESET)
 		reset_type = HNAE3_VF_PF_FUNC_RESET;
 	else if (hdev->reset_type == HNAE3_FLR_RESET)
@@ -142,11 +151,7 @@ int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport)
 	else
 		reset_type = HNAE3_VF_FUNC_RESET;
 
-	msg_data = cpu_to_le16(reset_type);
-
-	/* send this requested info to VF */
-	return hclge_send_mbx_msg(vport, (u8 *)&msg_data, sizeof(msg_data),
-				  HCLGE_MBX_ASSERTING_RESET, dest_vfid);
+	return hclge_inform_vf_reset(vport, reset_type);
 }
 
 static void hclge_free_vector_ring_chain(struct hnae3_ring_chain_node *head)
@@ -652,9 +657,56 @@ static int hclge_reset_vf(struct hclge_vport *vport)
 	return hclge_func_reset_cmd(hdev, vport->vport_id);
 }
 
+static void hclge_notify_vf_config(struct hclge_vport *vport)
+{
+	struct hclge_dev *hdev = vport->back;
+	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+	struct hclge_port_base_vlan_config *vlan_cfg;
+	int ret;
+
+	hclge_push_vf_link_status(vport);
+	if (test_bit(HCLGE_VPORT_NEED_NOTIFY_RESET, &vport->need_notify)) {
+		ret = hclge_inform_vf_reset(vport, HNAE3_VF_PF_FUNC_RESET);
+		if (ret) {
+			dev_err(&hdev->pdev->dev,
+				"failed to inform VF %u reset!",
+				vport->vport_id - HCLGE_VF_VPORT_START_NUM);
+			return;
+		}
+		vport->need_notify = 0;
+		return;
+	}
+
+	if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3 &&
+	    test_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN, &vport->need_notify)) {
+		vlan_cfg = &vport->port_base_vlan_cfg;
+		ret = hclge_push_vf_port_base_vlan_info(&hdev->vport[0],
+							vport->vport_id,
+							vlan_cfg->state,
+							&vlan_cfg->vlan_info);
+		if (ret) {
+			dev_err(&hdev->pdev->dev,
+				"failed to inform VF %u port base vlan!",
+				vport->vport_id - HCLGE_VF_VPORT_START_NUM);
+			return;
+		}
+		clear_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN, &vport->need_notify);
+	}
+}
+
 static void hclge_vf_keep_alive(struct hclge_vport *vport)
 {
+	struct hclge_dev *hdev = vport->back;
+
 	vport->last_active_jiffies = jiffies;
+
+	if (test_bit(HCLGE_VPORT_STATE_INITED, &vport->state) &&
+	    !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) {
+		set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
+		dev_info(&hdev->pdev->dev, "VF %u is alive!",
+			 vport->vport_id - HCLGE_VF_VPORT_START_NUM);
+		hclge_notify_vf_config(vport);
+	}
 }
 
 static int hclge_set_vf_mtu(struct hclge_vport *vport,
@@ -954,6 +1006,7 @@ static int hclge_mbx_vf_uninit_handler(struct hclge_mbx_ops_param *param)
 	hclge_rm_vport_all_mac_table(param->vport, true,
 				     HCLGE_MAC_ADDR_MC);
 	hclge_rm_vport_all_vlan_table(param->vport, true);
+	param->vport->mps = 0;
 	return 0;
 }
 
-- 
GitLab


From d530ece70f16f912e1d1bfeea694246ab78b0a4b Mon Sep 17 00:00:00 2001
From: Jiguang Xiao <jiguang.xiao@windriver.com>
Date: Wed, 28 Dec 2022 16:14:47 +0800
Subject: [PATCH 806/875] net: amd-xgbe: add missed tasklet_kill

The driver does not call tasklet_kill in several places.
Add the calls to fix it.

Fixes: 85b85c853401 ("amd-xgbe: Re-issue interrupt if interrupt status not cleared")
Signed-off-by: Jiguang Xiao <jiguang.xiao@windriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/amd/xgbe/xgbe-drv.c  | 3 +++
 drivers/net/ethernet/amd/xgbe/xgbe-i2c.c  | 4 +++-
 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c | 4 +++-
 3 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c
index 7b666106feee9..614c0278419bc 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c
@@ -1064,6 +1064,9 @@ static void xgbe_free_irqs(struct xgbe_prv_data *pdata)
 
 	devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
 
+	tasklet_kill(&pdata->tasklet_dev);
+	tasklet_kill(&pdata->tasklet_ecc);
+
 	if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
 		devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
 
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-i2c.c b/drivers/net/ethernet/amd/xgbe/xgbe-i2c.c
index 22d4fc547a0a3..a9ccc4258ee50 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-i2c.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-i2c.c
@@ -447,8 +447,10 @@ static void xgbe_i2c_stop(struct xgbe_prv_data *pdata)
 	xgbe_i2c_disable(pdata);
 	xgbe_i2c_clear_all_interrupts(pdata);
 
-	if (pdata->dev_irq != pdata->i2c_irq)
+	if (pdata->dev_irq != pdata->i2c_irq) {
 		devm_free_irq(pdata->dev, pdata->i2c_irq, pdata);
+		tasklet_kill(&pdata->tasklet_i2c);
+	}
 }
 
 static int xgbe_i2c_start(struct xgbe_prv_data *pdata)
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c b/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c
index 4e97b48695220..0c5c1b1556830 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c
@@ -1390,8 +1390,10 @@ static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
 	/* Disable auto-negotiation */
 	xgbe_an_disable_all(pdata);
 
-	if (pdata->dev_irq != pdata->an_irq)
+	if (pdata->dev_irq != pdata->an_irq) {
 		devm_free_irq(pdata->dev, pdata->an_irq, pdata);
+		tasklet_kill(&pdata->tasklet_an);
+	}
 
 	pdata->phy_if.phy_impl.stop(pdata);
 
-- 
GitLab


From 1573c6882018f69991aead951d09423ce978adac Mon Sep 17 00:00:00 2001
From: Po-Hsu Lin <po-hsu.lin@canonical.com>
Date: Thu, 29 Dec 2022 13:41:06 +0800
Subject: [PATCH 807/875] selftests: net: fix cmsg_so_mark.sh test hang

This cmsg_so_mark.sh test will hang on non-amd64 systems because of the
infinity loop for argument parsing in cmsg_sender.

Variable "o" in cs_parse_args() for taking getopt() should be an int,
otherwise it will be 255 when getopt() returns -1 on non-amd64 system
and thus causing infinity loop.

Link: https://lore.kernel.org/lkml/CA+G9fYsM2k7mrF7W4V_TrZ-qDauWM394=8yEJ=-t1oUg8_40YA@mail.gmail.com/t/
Signed-off-by: Po-Hsu Lin <po-hsu.lin@canonical.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 tools/testing/selftests/net/cmsg_sender.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/testing/selftests/net/cmsg_sender.c b/tools/testing/selftests/net/cmsg_sender.c
index 75dd83e39207b..24b21b15ed3fb 100644
--- a/tools/testing/selftests/net/cmsg_sender.c
+++ b/tools/testing/selftests/net/cmsg_sender.c
@@ -110,7 +110,7 @@ static void __attribute__((noreturn)) cs_usage(const char *bin)
 
 static void cs_parse_args(int argc, char *argv[])
 {
-	char o;
+	int o;
 
 	while ((o = getopt(argc, argv, "46sS:p:m:M:d:tf:F:c:C:l:L:H:")) != -1) {
 		switch (o) {
-- 
GitLab


From 332b49ff637d6c1a75b971022a8b992cf3c57db1 Mon Sep 17 00:00:00 2001
From: David Arinzon <darinzon@amazon.com>
Date: Thu, 29 Dec 2022 07:30:05 +0000
Subject: [PATCH 808/875] net: ena: Fix toeplitz initial hash value

On driver initialization, RSS hash initial value is set to zero,
instead of the default value. This happens because we pass NULL as
the RSS key parameter, which caused us to never initialize
the RSS hash value.

This patch fixes it by making sure the initial value is set, no matter
what the value of the RSS key is.

Fixes: 91a65b7d3ed8 ("net: ena: fix potential crash when rxfh key is NULL")
Signed-off-by: Nati Koler <nkoler@amazon.com>
Signed-off-by: David Arinzon <darinzon@amazon.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/amazon/ena/ena_com.c | 29 +++++++----------------
 1 file changed, 9 insertions(+), 20 deletions(-)

diff --git a/drivers/net/ethernet/amazon/ena/ena_com.c b/drivers/net/ethernet/amazon/ena/ena_com.c
index 8c8b4c88c7dea..451c3a1b62553 100644
--- a/drivers/net/ethernet/amazon/ena/ena_com.c
+++ b/drivers/net/ethernet/amazon/ena/ena_com.c
@@ -2400,29 +2400,18 @@ int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
 		return -EOPNOTSUPP;
 	}
 
-	switch (func) {
-	case ENA_ADMIN_TOEPLITZ:
-		if (key) {
-			if (key_len != sizeof(hash_key->key)) {
-				netdev_err(ena_dev->net_device,
-					   "key len (%u) doesn't equal the supported size (%zu)\n",
-					   key_len, sizeof(hash_key->key));
-				return -EINVAL;
-			}
-			memcpy(hash_key->key, key, key_len);
-			rss->hash_init_val = init_val;
-			hash_key->key_parts = key_len / sizeof(hash_key->key[0]);
+	if ((func == ENA_ADMIN_TOEPLITZ) && key) {
+		if (key_len != sizeof(hash_key->key)) {
+			netdev_err(ena_dev->net_device,
+				   "key len (%u) doesn't equal the supported size (%zu)\n",
+				   key_len, sizeof(hash_key->key));
+			return -EINVAL;
 		}
-		break;
-	case ENA_ADMIN_CRC32:
-		rss->hash_init_val = init_val;
-		break;
-	default:
-		netdev_err(ena_dev->net_device, "Invalid hash function (%d)\n",
-			   func);
-		return -EINVAL;
+		memcpy(hash_key->key, key, key_len);
+		hash_key->key_parts = key_len / sizeof(hash_key->key[0]);
 	}
 
+	rss->hash_init_val = init_val;
 	old_func = rss->hash_func;
 	rss->hash_func = func;
 	rc = ena_com_set_hash_function(ena_dev);
-- 
GitLab


From 9c9e539956fa67efb8a65e32b72a853740b33445 Mon Sep 17 00:00:00 2001
From: David Arinzon <darinzon@amazon.com>
Date: Thu, 29 Dec 2022 07:30:06 +0000
Subject: [PATCH 809/875] net: ena: Don't register memory info on XDP exchange

Since the queues aren't destroyed when we only exchange XDP programs,
there's no need to re-register them again.

Fixes: 548c4940b9f1 ("net: ena: Implement XDP_TX action")
Signed-off-by: Shay Agroskin <shayagr@amazon.com>
Signed-off-by: David Arinzon <darinzon@amazon.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/amazon/ena/ena_netdev.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.c b/drivers/net/ethernet/amazon/ena/ena_netdev.c
index a95529a69cbb6..6ba9b06719a08 100644
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.c
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.c
@@ -512,16 +512,18 @@ static void ena_xdp_exchange_program_rx_in_range(struct ena_adapter *adapter,
 						 struct bpf_prog *prog,
 						 int first, int count)
 {
+	struct bpf_prog *old_bpf_prog;
 	struct ena_ring *rx_ring;
 	int i = 0;
 
 	for (i = first; i < count; i++) {
 		rx_ring = &adapter->rx_ring[i];
-		xchg(&rx_ring->xdp_bpf_prog, prog);
-		if (prog) {
+		old_bpf_prog = xchg(&rx_ring->xdp_bpf_prog, prog);
+
+		if (!old_bpf_prog && prog) {
 			ena_xdp_register_rxq_info(rx_ring);
 			rx_ring->rx_headroom = XDP_PACKET_HEADROOM;
-		} else {
+		} else if (old_bpf_prog && !prog) {
 			ena_xdp_unregister_rxq_info(rx_ring);
 			rx_ring->rx_headroom = NET_SKB_PAD;
 		}
-- 
GitLab


From c7f5e34d906320fdc996afa616676161c029cc02 Mon Sep 17 00:00:00 2001
From: David Arinzon <darinzon@amazon.com>
Date: Thu, 29 Dec 2022 07:30:07 +0000
Subject: [PATCH 810/875] net: ena: Account for the number of processed bytes
 in XDP

The size of packets that were forwarded or dropped by XDP wasn't added
to the total processed bytes statistic.

Fixes: 548c4940b9f1 ("net: ena: Implement XDP_TX action")
Signed-off-by: Shay Agroskin <shayagr@amazon.com>
Signed-off-by: David Arinzon <darinzon@amazon.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/amazon/ena/ena_netdev.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.c b/drivers/net/ethernet/amazon/ena/ena_netdev.c
index 6ba9b06719a08..9ae86bd3d457b 100644
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.c
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.c
@@ -1719,6 +1719,7 @@ static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi,
 			}
 			if (xdp_verdict != XDP_PASS) {
 				xdp_flags |= xdp_verdict;
+				total_len += ena_rx_ctx.ena_bufs[0].len;
 				res_budget--;
 				continue;
 			}
-- 
GitLab


From 59811faa2c54dbcf44d575b5a8f6e7077da88dc2 Mon Sep 17 00:00:00 2001
From: David Arinzon <darinzon@amazon.com>
Date: Thu, 29 Dec 2022 07:30:08 +0000
Subject: [PATCH 811/875] net: ena: Use bitmask to indicate packet redirection

Redirecting packets with XDP Redirect is done in two phases:
1. A packet is passed by the driver to the kernel using
   xdp_do_redirect().
2. After finishing polling for new packets the driver lets the kernel
   know that it can now process the redirected packet using
   xdp_do_flush_map().
   The packets' redirection is handled in the napi context of the
   queue that called xdp_do_redirect()

To avoid calling xdp_do_flush_map() each time the driver first checks
whether any packets were redirected, using
	xdp_flags |= xdp_verdict;
and
	if (xdp_flags & XDP_REDIRECT)
	    xdp_do_flush_map()

essentially treating XDP instructions as a bitmask, which isn't the case:
    enum xdp_action {
	    XDP_ABORTED = 0,
	    XDP_DROP,
	    XDP_PASS,
	    XDP_TX,
	    XDP_REDIRECT,
    };

Given the current possible values of xdp_action, the current design
doesn't have a bug (since XDP_REDIRECT = 100b), but it is still
flawed.

This patch makes the driver use a bitmask instead, to avoid future
issues.

Fixes: a318c70ad152 ("net: ena: introduce XDP redirect implementation")
Signed-off-by: Shay Agroskin <shayagr@amazon.com>
Signed-off-by: David Arinzon <darinzon@amazon.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/amazon/ena/ena_netdev.c | 26 ++++++++++++--------
 drivers/net/ethernet/amazon/ena/ena_netdev.h |  9 +++++++
 2 files changed, 25 insertions(+), 10 deletions(-)

diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.c b/drivers/net/ethernet/amazon/ena/ena_netdev.c
index 9ae86bd3d457b..a67f55e5f7554 100644
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.c
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.c
@@ -374,9 +374,9 @@ static int ena_xdp_xmit(struct net_device *dev, int n,
 
 static int ena_xdp_execute(struct ena_ring *rx_ring, struct xdp_buff *xdp)
 {
+	u32 verdict = ENA_XDP_PASS;
 	struct bpf_prog *xdp_prog;
 	struct ena_ring *xdp_ring;
-	u32 verdict = XDP_PASS;
 	struct xdp_frame *xdpf;
 	u64 *xdp_stat;
 
@@ -393,7 +393,7 @@ static int ena_xdp_execute(struct ena_ring *rx_ring, struct xdp_buff *xdp)
 		if (unlikely(!xdpf)) {
 			trace_xdp_exception(rx_ring->netdev, xdp_prog, verdict);
 			xdp_stat = &rx_ring->rx_stats.xdp_aborted;
-			verdict = XDP_ABORTED;
+			verdict = ENA_XDP_DROP;
 			break;
 		}
 
@@ -409,29 +409,35 @@ static int ena_xdp_execute(struct ena_ring *rx_ring, struct xdp_buff *xdp)
 
 		spin_unlock(&xdp_ring->xdp_tx_lock);
 		xdp_stat = &rx_ring->rx_stats.xdp_tx;
+		verdict = ENA_XDP_TX;
 		break;
 	case XDP_REDIRECT:
 		if (likely(!xdp_do_redirect(rx_ring->netdev, xdp, xdp_prog))) {
 			xdp_stat = &rx_ring->rx_stats.xdp_redirect;
+			verdict = ENA_XDP_REDIRECT;
 			break;
 		}
 		trace_xdp_exception(rx_ring->netdev, xdp_prog, verdict);
 		xdp_stat = &rx_ring->rx_stats.xdp_aborted;
-		verdict = XDP_ABORTED;
+		verdict = ENA_XDP_DROP;
 		break;
 	case XDP_ABORTED:
 		trace_xdp_exception(rx_ring->netdev, xdp_prog, verdict);
 		xdp_stat = &rx_ring->rx_stats.xdp_aborted;
+		verdict = ENA_XDP_DROP;
 		break;
 	case XDP_DROP:
 		xdp_stat = &rx_ring->rx_stats.xdp_drop;
+		verdict = ENA_XDP_DROP;
 		break;
 	case XDP_PASS:
 		xdp_stat = &rx_ring->rx_stats.xdp_pass;
+		verdict = ENA_XDP_PASS;
 		break;
 	default:
 		bpf_warn_invalid_xdp_action(rx_ring->netdev, xdp_prog, verdict);
 		xdp_stat = &rx_ring->rx_stats.xdp_invalid;
+		verdict = ENA_XDP_DROP;
 	}
 
 	ena_increase_stat(xdp_stat, 1, &rx_ring->syncp);
@@ -1621,12 +1627,12 @@ static int ena_xdp_handle_buff(struct ena_ring *rx_ring, struct xdp_buff *xdp)
 	 * we expect, then we simply drop it
 	 */
 	if (unlikely(rx_ring->ena_bufs[0].len > ENA_XDP_MAX_MTU))
-		return XDP_DROP;
+		return ENA_XDP_DROP;
 
 	ret = ena_xdp_execute(rx_ring, xdp);
 
 	/* The xdp program might expand the headers */
-	if (ret == XDP_PASS) {
+	if (ret == ENA_XDP_PASS) {
 		rx_info->page_offset = xdp->data - xdp->data_hard_start;
 		rx_ring->ena_bufs[0].len = xdp->data_end - xdp->data;
 	}
@@ -1665,7 +1671,7 @@ static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi,
 	xdp_init_buff(&xdp, ENA_PAGE_SIZE, &rx_ring->xdp_rxq);
 
 	do {
-		xdp_verdict = XDP_PASS;
+		xdp_verdict = ENA_XDP_PASS;
 		skb = NULL;
 		ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
 		ena_rx_ctx.max_bufs = rx_ring->sgl_size;
@@ -1693,7 +1699,7 @@ static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi,
 			xdp_verdict = ena_xdp_handle_buff(rx_ring, &xdp);
 
 		/* allocate skb and fill it */
-		if (xdp_verdict == XDP_PASS)
+		if (xdp_verdict == ENA_XDP_PASS)
 			skb = ena_rx_skb(rx_ring,
 					 rx_ring->ena_bufs,
 					 ena_rx_ctx.descs,
@@ -1711,13 +1717,13 @@ static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi,
 				/* Packets was passed for transmission, unmap it
 				 * from RX side.
 				 */
-				if (xdp_verdict == XDP_TX || xdp_verdict == XDP_REDIRECT) {
+				if (xdp_verdict & ENA_XDP_FORWARDED) {
 					ena_unmap_rx_buff(rx_ring,
 							  &rx_ring->rx_buffer_info[req_id]);
 					rx_ring->rx_buffer_info[req_id].page = NULL;
 				}
 			}
-			if (xdp_verdict != XDP_PASS) {
+			if (xdp_verdict != ENA_XDP_PASS) {
 				xdp_flags |= xdp_verdict;
 				total_len += ena_rx_ctx.ena_bufs[0].len;
 				res_budget--;
@@ -1763,7 +1769,7 @@ static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi,
 		ena_refill_rx_bufs(rx_ring, refill_required);
 	}
 
-	if (xdp_flags & XDP_REDIRECT)
+	if (xdp_flags & ENA_XDP_REDIRECT)
 		xdp_do_flush_map();
 
 	return work_done;
diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.h b/drivers/net/ethernet/amazon/ena/ena_netdev.h
index 1bdce99bf6888..290ae9bf47ee4 100644
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.h
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.h
@@ -409,6 +409,15 @@ enum ena_xdp_errors_t {
 	ENA_XDP_NO_ENOUGH_QUEUES,
 };
 
+enum ENA_XDP_ACTIONS {
+	ENA_XDP_PASS		= 0,
+	ENA_XDP_TX		= BIT(0),
+	ENA_XDP_REDIRECT	= BIT(1),
+	ENA_XDP_DROP		= BIT(2)
+};
+
+#define ENA_XDP_FORWARDED (ENA_XDP_TX | ENA_XDP_REDIRECT)
+
 static inline bool ena_xdp_present(struct ena_adapter *adapter)
 {
 	return !!adapter->xdp_bpf_prog;
-- 
GitLab


From c7062aaee099f2f43d6f07a71744b44b94b94b34 Mon Sep 17 00:00:00 2001
From: David Arinzon <darinzon@amazon.com>
Date: Thu, 29 Dec 2022 07:30:09 +0000
Subject: [PATCH 812/875] net: ena: Fix rx_copybreak value update

Make the upper bound on rx_copybreak tighter, by
making sure it is smaller than the minimum of mtu and
ENA_PAGE_SIZE. With the current upper bound of mtu,
rx_copybreak can be larger than a page. Such large
rx_copybreak will not bring any performance benefit to
the user and therefore makes no sense.

In addition, the value update was only reflected in
the adapter structure, but not applied for each ring,
causing it to not take effect.

Fixes: 1738cd3ed342 ("net: ena: Add a driver for Amazon Elastic Network Adapters (ENA)")
Signed-off-by: Osama Abboud <osamaabb@amazon.com>
Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
Signed-off-by: David Arinzon <darinzon@amazon.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/amazon/ena/ena_ethtool.c |  6 +-----
 drivers/net/ethernet/amazon/ena/ena_netdev.c  | 18 ++++++++++++++++++
 drivers/net/ethernet/amazon/ena/ena_netdev.h  |  2 ++
 3 files changed, 21 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/amazon/ena/ena_ethtool.c b/drivers/net/ethernet/amazon/ena/ena_ethtool.c
index 48ae6d810f8f9..8da79eedc057c 100644
--- a/drivers/net/ethernet/amazon/ena/ena_ethtool.c
+++ b/drivers/net/ethernet/amazon/ena/ena_ethtool.c
@@ -887,11 +887,7 @@ static int ena_set_tunable(struct net_device *netdev,
 	switch (tuna->id) {
 	case ETHTOOL_RX_COPYBREAK:
 		len = *(u32 *)data;
-		if (len > adapter->netdev->mtu) {
-			ret = -EINVAL;
-			break;
-		}
-		adapter->rx_copybreak = len;
+		ret = ena_set_rx_copybreak(adapter, len);
 		break;
 	default:
 		ret = -EINVAL;
diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.c b/drivers/net/ethernet/amazon/ena/ena_netdev.c
index a67f55e5f7554..80a726932e810 100644
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.c
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.c
@@ -2814,6 +2814,24 @@ int ena_update_queue_sizes(struct ena_adapter *adapter,
 	return dev_was_up ? ena_up(adapter) : 0;
 }
 
+int ena_set_rx_copybreak(struct ena_adapter *adapter, u32 rx_copybreak)
+{
+	struct ena_ring *rx_ring;
+	int i;
+
+	if (rx_copybreak > min_t(u16, adapter->netdev->mtu, ENA_PAGE_SIZE))
+		return -EINVAL;
+
+	adapter->rx_copybreak = rx_copybreak;
+
+	for (i = 0; i < adapter->num_io_queues; i++) {
+		rx_ring = &adapter->rx_ring[i];
+		rx_ring->rx_copybreak = rx_copybreak;
+	}
+
+	return 0;
+}
+
 int ena_update_queue_count(struct ena_adapter *adapter, u32 new_channel_count)
 {
 	struct ena_com_dev *ena_dev = adapter->ena_dev;
diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.h b/drivers/net/ethernet/amazon/ena/ena_netdev.h
index 290ae9bf47ee4..f9d862b630fad 100644
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.h
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.h
@@ -392,6 +392,8 @@ int ena_update_queue_sizes(struct ena_adapter *adapter,
 
 int ena_update_queue_count(struct ena_adapter *adapter, u32 new_channel_count);
 
+int ena_set_rx_copybreak(struct ena_adapter *adapter, u32 rx_copybreak);
+
 int ena_get_sset_count(struct net_device *netdev, int sset);
 
 static inline void ena_reset_device(struct ena_adapter *adapter,
-- 
GitLab


From e712f3e4920b3a1a5e6b536827d118e14862896c Mon Sep 17 00:00:00 2001
From: David Arinzon <darinzon@amazon.com>
Date: Thu, 29 Dec 2022 07:30:10 +0000
Subject: [PATCH 813/875] net: ena: Set default value for RX interrupt
 moderation

RX ring can be NULL in XDP use cases where only TX queues
are configured. In this scenario, the RX interrupt moderation
value sent to the device remains in its default value of 0.

In this change, setting the default value of the RX interrupt
moderation to be the same as of the TX.

Fixes: 548c4940b9f1 ("net: ena: Implement XDP_TX action")
Signed-off-by: David Arinzon <darinzon@amazon.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/amazon/ena/ena_netdev.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.c b/drivers/net/ethernet/amazon/ena/ena_netdev.c
index 80a726932e810..99f80c2d560a5 100644
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.c
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.c
@@ -1823,8 +1823,9 @@ static void ena_adjust_adaptive_rx_intr_moderation(struct ena_napi *ena_napi)
 static void ena_unmask_interrupt(struct ena_ring *tx_ring,
 					struct ena_ring *rx_ring)
 {
+	u32 rx_interval = tx_ring->smoothed_interval;
 	struct ena_eth_io_intr_reg intr_reg;
-	u32 rx_interval = 0;
+
 	/* Rx ring can be NULL when for XDP tx queues which don't have an
 	 * accompanying rx_ring pair.
 	 */
-- 
GitLab


From a8ee104f986e720cea52133885cc822d459398c7 Mon Sep 17 00:00:00 2001
From: David Arinzon <darinzon@amazon.com>
Date: Thu, 29 Dec 2022 07:30:11 +0000
Subject: [PATCH 814/875] net: ena: Update NUMA TPH hint register upon NUMA
 node update

The device supports a PCIe optimization hint, which indicates on
which NUMA the queue is currently processed. This hint is utilized
by PCIe in order to reduce its access time by accessing the
correct NUMA resources and maintaining cache coherence.

The driver calls the register update for the hint (called TPH -
TLP Processing Hint) during the NAPI loop.

Though the update is expected upon a NUMA change (when a queue
is moved from one NUMA to the other), the current logic performs
a register update when the queue is moved to a different CPU,
but the CPU is not necessarily in a different NUMA.

The changes include:
1. Performing the TPH update only when the queue has switched
a NUMA node.
2. Moving the TPH update call to be triggered only when NAPI was
scheduled from interrupt context, as opposed to a busy-polling loop.
This is due to the fact that during busy-polling, the frequency
of CPU switches for a particular queue is significantly higher,
thus, the likelihood to switch NUMA is much higher. Therefore,
providing the frequent updates to the device upon a NUMA update
are unlikely to be beneficial.

Fixes: 1738cd3ed342 ("net: ena: Add a driver for Amazon Elastic Network Adapters (ENA)")
Signed-off-by: David Arinzon <darinzon@amazon.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/amazon/ena/ena_netdev.c | 27 +++++++++++++-------
 drivers/net/ethernet/amazon/ena/ena_netdev.h |  6 +++--
 2 files changed, 22 insertions(+), 11 deletions(-)

diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.c b/drivers/net/ethernet/amazon/ena/ena_netdev.c
index 99f80c2d560a5..e8ad5ea31affe 100644
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.c
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.c
@@ -680,6 +680,7 @@ static void ena_init_io_rings_common(struct ena_adapter *adapter,
 	ring->ena_dev = adapter->ena_dev;
 	ring->per_napi_packets = 0;
 	ring->cpu = 0;
+	ring->numa_node = 0;
 	ring->no_interrupt_event_cnt = 0;
 	u64_stats_init(&ring->syncp);
 }
@@ -783,6 +784,7 @@ static int ena_setup_tx_resources(struct ena_adapter *adapter, int qid)
 	tx_ring->next_to_use = 0;
 	tx_ring->next_to_clean = 0;
 	tx_ring->cpu = ena_irq->cpu;
+	tx_ring->numa_node = node;
 	return 0;
 
 err_push_buf_intermediate_buf:
@@ -915,6 +917,7 @@ static int ena_setup_rx_resources(struct ena_adapter *adapter,
 	rx_ring->next_to_clean = 0;
 	rx_ring->next_to_use = 0;
 	rx_ring->cpu = ena_irq->cpu;
+	rx_ring->numa_node = node;
 
 	return 0;
 }
@@ -1863,20 +1866,27 @@ static void ena_update_ring_numa_node(struct ena_ring *tx_ring,
 	if (likely(tx_ring->cpu == cpu))
 		goto out;
 
+	tx_ring->cpu = cpu;
+	if (rx_ring)
+		rx_ring->cpu = cpu;
+
 	numa_node = cpu_to_node(cpu);
+
+	if (likely(tx_ring->numa_node == numa_node))
+		goto out;
+
 	put_cpu();
 
 	if (numa_node != NUMA_NO_NODE) {
 		ena_com_update_numa_node(tx_ring->ena_com_io_cq, numa_node);
-		if (rx_ring)
+		tx_ring->numa_node = numa_node;
+		if (rx_ring) {
+			rx_ring->numa_node = numa_node;
 			ena_com_update_numa_node(rx_ring->ena_com_io_cq,
 						 numa_node);
+		}
 	}
 
-	tx_ring->cpu = cpu;
-	if (rx_ring)
-		rx_ring->cpu = cpu;
-
 	return;
 out:
 	put_cpu();
@@ -1997,11 +2007,10 @@ static int ena_io_poll(struct napi_struct *napi, int budget)
 			if (ena_com_get_adaptive_moderation_enabled(rx_ring->ena_dev))
 				ena_adjust_adaptive_rx_intr_moderation(ena_napi);
 
+			ena_update_ring_numa_node(tx_ring, rx_ring);
 			ena_unmask_interrupt(tx_ring, rx_ring);
 		}
 
-		ena_update_ring_numa_node(tx_ring, rx_ring);
-
 		ret = rx_work_done;
 	} else {
 		ret = budget;
@@ -2386,7 +2395,7 @@ static int ena_create_io_tx_queue(struct ena_adapter *adapter, int qid)
 	ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
 	ctx.msix_vector = msix_vector;
 	ctx.queue_size = tx_ring->ring_size;
-	ctx.numa_node = cpu_to_node(tx_ring->cpu);
+	ctx.numa_node = tx_ring->numa_node;
 
 	rc = ena_com_create_io_queue(ena_dev, &ctx);
 	if (rc) {
@@ -2454,7 +2463,7 @@ static int ena_create_io_rx_queue(struct ena_adapter *adapter, int qid)
 	ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
 	ctx.msix_vector = msix_vector;
 	ctx.queue_size = rx_ring->ring_size;
-	ctx.numa_node = cpu_to_node(rx_ring->cpu);
+	ctx.numa_node = rx_ring->numa_node;
 
 	rc = ena_com_create_io_queue(ena_dev, &ctx);
 	if (rc) {
diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.h b/drivers/net/ethernet/amazon/ena/ena_netdev.h
index f9d862b630fad..2cb141079474c 100644
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.h
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.h
@@ -262,9 +262,11 @@ struct ena_ring {
 	bool disable_meta_caching;
 	u16 no_interrupt_event_cnt;
 
-	/* cpu for TPH */
+	/* cpu and NUMA for TPH */
 	int cpu;
-	 /* number of tx/rx_buffer_info's entries */
+	int numa_node;
+
+	/* number of tx/rx_buffer_info's entries */
 	int ring_size;
 
 	enum ena_admin_placement_policy_type tx_mem_queue_type;
-- 
GitLab


From d039535850ee47079d59527e96be18d8e0daa84b Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Thu, 29 Dec 2022 10:29:25 +0400
Subject: [PATCH 815/875] net: phy: xgmiitorgmii: Fix refcount leak in
 xgmiitorgmii_probe

of_phy_find_device() return device node with refcount incremented.
Call put_device() to relese it when not needed anymore.

Fixes: ab4e6ee578e8 ("net: phy: xgmiitorgmii: Check phy_driver ready before accessing")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/phy/xilinx_gmii2rgmii.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/phy/xilinx_gmii2rgmii.c b/drivers/net/phy/xilinx_gmii2rgmii.c
index 8dcb49ed1f3d9..7fd9fe6a602bc 100644
--- a/drivers/net/phy/xilinx_gmii2rgmii.c
+++ b/drivers/net/phy/xilinx_gmii2rgmii.c
@@ -105,6 +105,7 @@ static int xgmiitorgmii_probe(struct mdio_device *mdiodev)
 
 	if (!priv->phy_dev->drv) {
 		dev_info(dev, "Attached phy not ready\n");
+		put_device(&priv->phy_dev->mdio.dev);
 		return -EPROBE_DEFER;
 	}
 
-- 
GitLab


From c5bc073668206c73c20798eb6d978b5e9db5b16f Mon Sep 17 00:00:00 2001
From: Andrzej Hajda <andrzej.hajda@intel.com>
Date: Wed, 14 Dec 2022 08:54:39 +0100
Subject: [PATCH 816/875] drm/i915: fix TLB invalidation for Gen12.50 video and
 compute engines

In case of Gen12.50 video and compute engines, TLB_INV registers are
masked - to modify one bit, corresponding bit in upper half of the register
must be enabled, otherwise nothing happens.

Fixes: 77fa9efc16a9 ("drm/i915/xehp: Create separate reg definitions for new MCR registers")
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221214075439.402485-1-andrzej.hajda@intel.com
(cherry picked from commit 4d5cf7b1680a1e6db327e3c935ef58325cbedb2c)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 767e329e1cc5f..9c18b5f2e7892 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1109,9 +1109,15 @@ static void mmio_invalidate_full(struct intel_gt *gt)
 			continue;
 
 		if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+			u32 val = BIT(engine->instance);
+
+			if (engine->class == VIDEO_DECODE_CLASS ||
+			    engine->class == VIDEO_ENHANCEMENT_CLASS ||
+			    engine->class == COMPUTE_CLASS)
+				val = _MASKED_BIT_ENABLE(val);
 			intel_gt_mcr_multicast_write_fw(gt,
 							xehp_regs[engine->class],
-							BIT(engine->instance));
+							val);
 		} else {
 			rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
 			if (!i915_mmio_reg_offset(rb.reg))
-- 
GitLab


From fff758698842fb6722be37498d8773e0fb47f000 Mon Sep 17 00:00:00 2001
From: Lucas De Marchi <lucas.demarchi@intel.com>
Date: Wed, 14 Dec 2022 11:49:44 -0800
Subject: [PATCH 817/875] drm/i915: Remove __maybe_unused from mtl_info

The attribute __maybe_unused should remain only until the respective
info is not in the pciidlist. The info can't be added together
with its definition because that would cause the driver to automatically
probe for the device, while it's still not ready for that. However once
pciidlist contains it, the attribute can be removed.

Fixes: 7835303982d1 ("drm/i915/mtl: Add MeteorLake PCI IDs")
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221214194944.3670344-1-lucas.demarchi@intel.com
(cherry picked from commit 50490ce05b7a50b0bd4108fa7d6db3ca2972fa83)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 6da9784fe4a24..ccd1f864aa196 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1129,7 +1129,6 @@ static const struct intel_gt_definition xelpmp_extra_gt[] = {
 	{}
 };
 
-__maybe_unused
 static const struct intel_device_info mtl_info = {
 	XE_HP_FEATURES,
 	XE_LPDP_FEATURES,
-- 
GitLab


From 3f882f2d4f689627c1566c2c92087bc3ff734953 Mon Sep 17 00:00:00 2001
From: Matthew Auld <matthew.auld@intel.com>
Date: Fri, 16 Dec 2022 11:34:56 +0000
Subject: [PATCH 818/875] drm/i915: improve the catch-all evict to handle lock
 contention
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The catch-all evict can fail due to object lock contention, since it
only goes as far as trylocking the object, due to us already holding the
vm->mutex. Doing a full object lock here can deadlock, since the
vm->mutex is always our inner lock. Add another execbuf pass which drops
the vm->mutex and then tries to grab the object will the full lock,
before then retrying the eviction. This should be good enough for now to
fix the immediate regression with userspace seeing -ENOSPC from execbuf
due to contended object locks during GTT eviction.

v2 (Mani)
  - Also revamp the docs for the different passes.

Testcase: igt@gem_ppgtt@shrink-vs-evict-*
Fixes: 7e00897be8bf ("drm/i915: Add object locking to i915_gem_evict_for_node and i915_gem_evict_something, v2.")
References: https://gitlab.freedesktop.org/drm/intel/-/issues/7627
References: https://gitlab.freedesktop.org/drm/intel/-/issues/7570
References: https://bugzilla.mozilla.org/show_bug.cgi?id=1779558
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Mani Milani <mani@chromium.org>
Cc: <stable@vger.kernel.org> # v5.18+
Reviewed-by: Mani Milani <mani@chromium.org>
Tested-by: Mani Milani <mani@chromium.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20221216113456.414183-1-matthew.auld@intel.com
(cherry picked from commit 801fa7a81f6da533cc5442fc40e32c72b76cd42a)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 .../gpu/drm/i915/gem/i915_gem_execbuffer.c    | 59 +++++++++++++++----
 drivers/gpu/drm/i915/gem/i915_gem_mman.c      |  2 +-
 drivers/gpu/drm/i915/i915_gem_evict.c         | 37 ++++++++----
 drivers/gpu/drm/i915/i915_gem_evict.h         |  4 +-
 drivers/gpu/drm/i915/i915_vma.c               |  2 +-
 .../gpu/drm/i915/selftests/i915_gem_evict.c   |  4 +-
 6 files changed, 82 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index da09767fda070..f266b68cf012c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -730,32 +730,69 @@ static int eb_reserve(struct i915_execbuffer *eb)
 	bool unpinned;
 
 	/*
-	 * Attempt to pin all of the buffers into the GTT.
-	 * This is done in 2 phases:
+	 * We have one more buffers that we couldn't bind, which could be due to
+	 * various reasons. To resolve this we have 4 passes, with every next
+	 * level turning the screws tighter:
 	 *
-	 * 1. Unbind all objects that do not match the GTT constraints for
-	 *    the execbuffer (fenceable, mappable, alignment etc).
-	 * 2. Bind new objects.
+	 * 0. Unbind all objects that do not match the GTT constraints for the
+	 * execbuffer (fenceable, mappable, alignment etc). Bind all new
+	 * objects.  This avoids unnecessary unbinding of later objects in order
+	 * to make room for the earlier objects *unless* we need to defragment.
 	 *
-	 * This avoid unnecessary unbinding of later objects in order to make
-	 * room for the earlier objects *unless* we need to defragment.
+	 * 1. Reorder the buffers, where objects with the most restrictive
+	 * placement requirements go first (ignoring fixed location buffers for
+	 * now).  For example, objects needing the mappable aperture (the first
+	 * 256M of GTT), should go first vs objects that can be placed just
+	 * about anywhere. Repeat the previous pass.
 	 *
-	 * Defragmenting is skipped if all objects are pinned at a fixed location.
+	 * 2. Consider buffers that are pinned at a fixed location. Also try to
+	 * evict the entire VM this time, leaving only objects that we were
+	 * unable to lock. Try again to bind the buffers. (still using the new
+	 * buffer order).
+	 *
+	 * 3. We likely have object lock contention for one or more stubborn
+	 * objects in the VM, for which we need to evict to make forward
+	 * progress (perhaps we are fighting the shrinker?). When evicting the
+	 * VM this time around, anything that we can't lock we now track using
+	 * the busy_bo, using the full lock (after dropping the vm->mutex to
+	 * prevent deadlocks), instead of trylock. We then continue to evict the
+	 * VM, this time with the stubborn object locked, which we can now
+	 * hopefully unbind (if still bound in the VM). Repeat until the VM is
+	 * evicted. Finally we should be able bind everything.
 	 */
-	for (pass = 0; pass <= 2; pass++) {
+	for (pass = 0; pass <= 3; pass++) {
 		int pin_flags = PIN_USER | PIN_VALIDATE;
 
 		if (pass == 0)
 			pin_flags |= PIN_NONBLOCK;
 
 		if (pass >= 1)
-			unpinned = eb_unbind(eb, pass == 2);
+			unpinned = eb_unbind(eb, pass >= 2);
 
 		if (pass == 2) {
 			err = mutex_lock_interruptible(&eb->context->vm->mutex);
 			if (!err) {
-				err = i915_gem_evict_vm(eb->context->vm, &eb->ww);
+				err = i915_gem_evict_vm(eb->context->vm, &eb->ww, NULL);
+				mutex_unlock(&eb->context->vm->mutex);
+			}
+			if (err)
+				return err;
+		}
+
+		if (pass == 3) {
+retry:
+			err = mutex_lock_interruptible(&eb->context->vm->mutex);
+			if (!err) {
+				struct drm_i915_gem_object *busy_bo = NULL;
+
+				err = i915_gem_evict_vm(eb->context->vm, &eb->ww, &busy_bo);
 				mutex_unlock(&eb->context->vm->mutex);
+				if (err && busy_bo) {
+					err = i915_gem_object_lock(busy_bo, &eb->ww);
+					i915_gem_object_put(busy_bo);
+					if (!err)
+						goto retry;
+				}
 			}
 			if (err)
 				return err;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index c29efdef8313a..0ad44f3868ded 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -369,7 +369,7 @@ retry:
 		if (vma == ERR_PTR(-ENOSPC)) {
 			ret = mutex_lock_interruptible(&ggtt->vm.mutex);
 			if (!ret) {
-				ret = i915_gem_evict_vm(&ggtt->vm, &ww);
+				ret = i915_gem_evict_vm(&ggtt->vm, &ww, NULL);
 				mutex_unlock(&ggtt->vm.mutex);
 			}
 			if (ret)
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c
index f025ee4fa5261..a4b4d9b7d26c7 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -416,6 +416,11 @@ int i915_gem_evict_for_node(struct i915_address_space *vm,
  * @vm: Address space to cleanse
  * @ww: An optional struct i915_gem_ww_ctx. If not NULL, i915_gem_evict_vm
  * will be able to evict vma's locked by the ww as well.
+ * @busy_bo: Optional pointer to struct drm_i915_gem_object. If not NULL, then
+ * in the event i915_gem_evict_vm() is unable to trylock an object for eviction,
+ * then @busy_bo will point to it. -EBUSY is also returned. The caller must drop
+ * the vm->mutex, before trying again to acquire the contended lock. The caller
+ * also owns a reference to the object.
  *
  * This function evicts all vmas from a vm.
  *
@@ -425,7 +430,8 @@ int i915_gem_evict_for_node(struct i915_address_space *vm,
  * To clarify: This is for freeing up virtual address space, not for freeing
  * memory in e.g. the shrinker.
  */
-int i915_gem_evict_vm(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww)
+int i915_gem_evict_vm(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww,
+		      struct drm_i915_gem_object **busy_bo)
 {
 	int ret = 0;
 
@@ -457,15 +463,22 @@ int i915_gem_evict_vm(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww)
 			 * the resv is shared among multiple objects, we still
 			 * need the object ref.
 			 */
-			if (dying_vma(vma) ||
+			if (!i915_gem_object_get_rcu(vma->obj) ||
 			    (ww && (dma_resv_locking_ctx(vma->obj->base.resv) == &ww->ctx))) {
 				__i915_vma_pin(vma);
 				list_add(&vma->evict_link, &locked_eviction_list);
 				continue;
 			}
 
-			if (!i915_gem_object_trylock(vma->obj, ww))
+			if (!i915_gem_object_trylock(vma->obj, ww)) {
+				if (busy_bo) {
+					*busy_bo = vma->obj; /* holds ref */
+					ret = -EBUSY;
+					break;
+				}
+				i915_gem_object_put(vma->obj);
 				continue;
+			}
 
 			__i915_vma_pin(vma);
 			list_add(&vma->evict_link, &eviction_list);
@@ -473,25 +486,29 @@ int i915_gem_evict_vm(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww)
 		if (list_empty(&eviction_list) && list_empty(&locked_eviction_list))
 			break;
 
-		ret = 0;
 		/* Unbind locked objects first, before unlocking the eviction_list */
 		list_for_each_entry_safe(vma, vn, &locked_eviction_list, evict_link) {
 			__i915_vma_unpin(vma);
 
-			if (ret == 0)
+			if (ret == 0) {
 				ret = __i915_vma_unbind(vma);
-			if (ret != -EINTR) /* "Get me out of here!" */
-				ret = 0;
+				if (ret != -EINTR) /* "Get me out of here!" */
+					ret = 0;
+			}
+			if (!dying_vma(vma))
+				i915_gem_object_put(vma->obj);
 		}
 
 		list_for_each_entry_safe(vma, vn, &eviction_list, evict_link) {
 			__i915_vma_unpin(vma);
-			if (ret == 0)
+			if (ret == 0) {
 				ret = __i915_vma_unbind(vma);
-			if (ret != -EINTR) /* "Get me out of here!" */
-				ret = 0;
+				if (ret != -EINTR) /* "Get me out of here!" */
+					ret = 0;
+			}
 
 			i915_gem_object_unlock(vma->obj);
+			i915_gem_object_put(vma->obj);
 		}
 	} while (ret == 0);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.h b/drivers/gpu/drm/i915/i915_gem_evict.h
index e593c530f9bd7..bf0ee0e4fe608 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.h
+++ b/drivers/gpu/drm/i915/i915_gem_evict.h
@@ -11,6 +11,7 @@
 struct drm_mm_node;
 struct i915_address_space;
 struct i915_gem_ww_ctx;
+struct drm_i915_gem_object;
 
 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
 					  struct i915_gem_ww_ctx *ww,
@@ -23,6 +24,7 @@ int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
 					 struct drm_mm_node *node,
 					 unsigned int flags);
 int i915_gem_evict_vm(struct i915_address_space *vm,
-		      struct i915_gem_ww_ctx *ww);
+		      struct i915_gem_ww_ctx *ww,
+		      struct drm_i915_gem_object **busy_bo);
 
 #endif /* __I915_GEM_EVICT_H__ */
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 703fee6b5f752..3a33be5401ed2 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -1566,7 +1566,7 @@ static int __i915_ggtt_pin(struct i915_vma *vma, struct i915_gem_ww_ctx *ww,
 			 * locked objects when called from execbuf when pinning
 			 * is removed. This would probably regress badly.
 			 */
-			i915_gem_evict_vm(vm, NULL);
+			i915_gem_evict_vm(vm, NULL, NULL);
 			mutex_unlock(&vm->mutex);
 		}
 	} while (1);
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
index 8c6517d29b8e0..37068542aafe7 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
@@ -344,7 +344,7 @@ static int igt_evict_vm(void *arg)
 
 	/* Everything is pinned, nothing should happen */
 	mutex_lock(&ggtt->vm.mutex);
-	err = i915_gem_evict_vm(&ggtt->vm, NULL);
+	err = i915_gem_evict_vm(&ggtt->vm, NULL, NULL);
 	mutex_unlock(&ggtt->vm.mutex);
 	if (err) {
 		pr_err("i915_gem_evict_vm on a full GGTT returned err=%d]\n",
@@ -356,7 +356,7 @@ static int igt_evict_vm(void *arg)
 
 	for_i915_gem_ww(&ww, err, false) {
 		mutex_lock(&ggtt->vm.mutex);
-		err = i915_gem_evict_vm(&ggtt->vm, &ww);
+		err = i915_gem_evict_vm(&ggtt->vm, &ww, NULL);
 		mutex_unlock(&ggtt->vm.mutex);
 	}
 
-- 
GitLab


From 11ce8fd8fd8718247f17475802639cd7e2d3765c Mon Sep 17 00:00:00 2001
From: John Harrison <John.C.Harrison@Intel.com>
Date: Wed, 21 Dec 2022 11:30:31 -0800
Subject: [PATCH 819/875] drm/i915/uc: Fix two issues with over-size firmware
 files
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

In the case where a firmware file is too large (e.g. someone
downloaded a web page ASCII dump from github...), the firmware object
is released but the pointer is not zerod. If no other firmware file
was found then release would be called again leading to a double kfree.

Also, the size check was only being applied to the initial firmware
load not any of the subsequent attempts. So move the check into a
wrapper that is used for all loads.

Fixes: 016241168dc5 ("drm/i915/uc: use different ggtt pin offsets for uc loads")
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221221193031.687266-4-John.C.Harrison@Intel.com
(cherry picked from commit 4071d98b296a5bc5fd4b15ec651bd05800ec9510)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 42 ++++++++++++++++--------
 1 file changed, 28 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 0c80ba51a4bdc..2bcdd192f8147 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -545,6 +545,32 @@ static int check_ccs_header(struct intel_gt *gt,
 	return 0;
 }
 
+static int try_firmware_load(struct intel_uc_fw *uc_fw, const struct firmware **fw)
+{
+	struct intel_gt *gt = __uc_fw_to_gt(uc_fw);
+	struct device *dev = gt->i915->drm.dev;
+	int err;
+
+	err = firmware_request_nowarn(fw, uc_fw->file_selected.path, dev);
+
+	if (err)
+		return err;
+
+	if ((*fw)->size > INTEL_UC_RSVD_GGTT_PER_FW) {
+		drm_err(&gt->i915->drm,
+			"%s firmware %s: size (%zuKB) exceeds max supported size (%uKB)\n",
+			intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
+			(*fw)->size / SZ_1K, INTEL_UC_RSVD_GGTT_PER_FW / SZ_1K);
+
+		/* try to find another blob to load */
+		release_firmware(*fw);
+		*fw = NULL;
+		return -ENOENT;
+	}
+
+	return 0;
+}
+
 /**
  * intel_uc_fw_fetch - fetch uC firmware
  * @uc_fw: uC firmware
@@ -558,7 +584,6 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
 	struct intel_gt *gt = __uc_fw_to_gt(uc_fw);
 	struct drm_i915_private *i915 = gt->i915;
 	struct intel_uc_fw_file file_ideal;
-	struct device *dev = i915->drm.dev;
 	struct drm_i915_gem_object *obj;
 	const struct firmware *fw = NULL;
 	bool old_ver = false;
@@ -574,20 +599,9 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
 	__force_fw_fetch_failures(uc_fw, -EINVAL);
 	__force_fw_fetch_failures(uc_fw, -ESTALE);
 
-	err = firmware_request_nowarn(&fw, uc_fw->file_selected.path, dev);
+	err = try_firmware_load(uc_fw, &fw);
 	memcpy(&file_ideal, &uc_fw->file_wanted, sizeof(file_ideal));
 
-	if (!err && fw->size > INTEL_UC_RSVD_GGTT_PER_FW) {
-		drm_err(&i915->drm,
-			"%s firmware %s: size (%zuKB) exceeds max supported size (%uKB)\n",
-			intel_uc_fw_type_repr(uc_fw->type), uc_fw->file_selected.path,
-			fw->size / SZ_1K, INTEL_UC_RSVD_GGTT_PER_FW / SZ_1K);
-
-		/* try to find another blob to load */
-		release_firmware(fw);
-		err = -ENOENT;
-	}
-
 	/* Any error is terminal if overriding. Don't bother searching for older versions */
 	if (err && intel_uc_fw_is_overridden(uc_fw))
 		goto fail;
@@ -608,7 +622,7 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
 			break;
 		}
 
-		err = firmware_request_nowarn(&fw, uc_fw->file_selected.path, dev);
+		err = try_firmware_load(uc_fw, &fw);
 	}
 
 	if (err)
-- 
GitLab


From 99cb0d917ffa1ab628bb67364ca9b162c07699b1 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <masahiroy@kernel.org>
Date: Tue, 27 Dec 2022 03:45:37 +0900
Subject: [PATCH 820/875] arch: fix broken BuildID for arm64 and riscv

Dennis Gilmore reports that the BuildID is missing in the arm64 vmlinux
since commit 994b7ac1697b ("arm64: remove special treatment for the
link order of head.o").

The issue is that the type of .notes section, which contains the BuildID,
changed from NOTES to PROGBITS.

Ard Biesheuvel figured out that whichever object gets linked first gets
to decide the type of a section. The PROGBITS type is the result of the
compiler emitting .note.GNU-stack as PROGBITS rather than NOTE.

While Ard provided a fix for arm64, I want to fix this globally because
the same issue is happening on riscv since commit 2348e6bf4421 ("riscv:
remove special treatment for the link order of head.o"). This problem
will happen in general for other architectures if they start to drop
unneeded entries from scripts/head-object-list.txt.

Discard .note.GNU-stack in include/asm-generic/vmlinux.lds.h.

Link: https://lore.kernel.org/lkml/CAABkxwuQoz1CTbyb57n0ZX65eSYiTonFCU8-LCQc=74D=xE=rA@mail.gmail.com/
Fixes: 994b7ac1697b ("arm64: remove special treatment for the link order of head.o")
Fixes: 2348e6bf4421 ("riscv: remove special treatment for the link order of head.o")
Reported-by: Dennis Gilmore <dennis@ausil.us>
Suggested-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 include/asm-generic/vmlinux.lds.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index a94219e9916f1..659bf3b31c911 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -891,7 +891,12 @@
 #define PRINTK_INDEX
 #endif
 
+/*
+ * Discard .note.GNU-stack, which is emitted as PROGBITS by the compiler.
+ * Otherwise, the type of .notes section would become PROGBITS instead of NOTES.
+ */
 #define NOTES								\
+	/DISCARD/ : { *(.note.GNU-stack) }				\
 	.notes : AT(ADDR(.notes) - LOAD_OFFSET) {			\
 		BOUNDED_SECTION_BY(.note.*, _notes)			\
 	} NOTES_HEADERS							\
-- 
GitLab


From 924d28b39e3b62ad5e97751585aed7c89f8c43ee Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <masahiroy@kernel.org>
Date: Tue, 27 Dec 2022 03:54:44 +0900
Subject: [PATCH 821/875] .gitignore: ignore *.rpm

Previously, *.rpm files were created under $HOME/rpmbuild/, but since
commit 8818039f959b ("kbuild: add ability to make source rpm buildable
using koji"), srcrpm-pkg creates the source rpm in the kernel tree
because it sets '_srcrpmdir'.

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
---
 .gitignore | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.gitignore b/.gitignore
index 3ec73ead6757e..20dce5c3b9e0f 100644
--- a/.gitignore
+++ b/.gitignore
@@ -39,6 +39,7 @@
 *.o.*
 *.patch
 *.rmeta
+*.rpm
 *.rsi
 *.s
 *.so
-- 
GitLab


From 9c9b55a59416a87fc73c479d78cb3218076dbc30 Mon Sep 17 00:00:00 2001
From: Jun ASAKA <JunASAKA@zzy040330.moe>
Date: Tue, 27 Dec 2022 17:21:57 +0800
Subject: [PATCH 822/875] kbuild: add a missing line for help message

The help message line for building the source RPM package was missing.
Added it.

Signed-off-by: Jun ASAKA <JunASAKA@zzy040330.moe>
Reviewed-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
---
 scripts/Makefile.package | 1 +
 1 file changed, 1 insertion(+)

diff --git a/scripts/Makefile.package b/scripts/Makefile.package
index 539e9f765d64d..525a2820976fd 100644
--- a/scripts/Makefile.package
+++ b/scripts/Makefile.package
@@ -158,6 +158,7 @@ $(perf-tar-pkgs):
 PHONY += help
 help:
 	@echo '  rpm-pkg             - Build both source and binary RPM kernel packages'
+	@echo '  srcrpm-pkg          - Build only the source kernel RPM package'
 	@echo '  binrpm-pkg          - Build only the binary kernel RPM package'
 	@echo '  deb-pkg             - Build both source and binary deb kernel packages'
 	@echo '  bindeb-pkg          - Build only the binary kernel deb package'
-- 
GitLab


From 63ffe00d8c939eda1a8fa87484ca4537e13a20b7 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Tue, 27 Dec 2022 15:48:21 -0600
Subject: [PATCH 823/875] kbuild: Fix running modpost with musl libc

commit 3d57e1b7b1d4 ("kbuild: refactor the prerequisites of the modpost
rule") moved 'vmlinux.o' inside modpost-args, possibly before some of
the other options. However, getopt() in musl libc follows POSIX and
stops looking for options upon reaching the first non-option argument.
As a result, the '-T' option is misinterpreted as a positional argument,
and the build fails:

  make -f ./scripts/Makefile.modpost
     scripts/mod/modpost   -E   -o Module.symvers vmlinux.o -T modules.order
  -T: No such file or directory
  make[1]: *** [scripts/Makefile.modpost:137: Module.symvers] Error 1
  make: *** [Makefile:1960: modpost] Error 2

The fix is to move all options before 'vmlinux.o' in modpost-args.

Fixes: 3d57e1b7b1d4 ("kbuild: refactor the prerequisites of the modpost rule")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
---
 scripts/Makefile.modpost | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/scripts/Makefile.modpost b/scripts/Makefile.modpost
index 5eb5e8280379a..0ee296cf520c2 100644
--- a/scripts/Makefile.modpost
+++ b/scripts/Makefile.modpost
@@ -55,6 +55,17 @@ ifneq ($(findstring i,$(filter-out --%,$(MAKEFLAGS))),)
 modpost-args += -n
 endif
 
+ifneq ($(KBUILD_MODPOST_WARN)$(missing-input),)
+modpost-args += -w
+endif
+
+# Read out modules.order to pass in modpost.
+# Otherwise, allmodconfig would fail with "Argument list too long".
+ifdef KBUILD_MODULES
+modpost-args += -T $(MODORDER)
+modpost-deps += $(MODORDER)
+endif
+
 ifeq ($(KBUILD_EXTMOD),)
 
 # Generate the list of in-tree objects in vmlinux
@@ -113,17 +124,6 @@ modpost-args += -e $(addprefix -i , $(KBUILD_EXTRA_SYMBOLS))
 
 endif # ($(KBUILD_EXTMOD),)
 
-ifneq ($(KBUILD_MODPOST_WARN)$(missing-input),)
-modpost-args += -w
-endif
-
-ifdef KBUILD_MODULES
-modpost-args += -T $(MODORDER)
-modpost-deps += $(MODORDER)
-endif
-
-# Read out modules.order to pass in modpost.
-# Otherwise, allmodconfig would fail with "Argument list too long".
 quiet_cmd_modpost = MODPOST $@
       cmd_modpost = \
 	$(if $(missing-input), \
-- 
GitLab


From 02a893bc99757d75b7abb43b74f210dfa3df8c4b Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <masahiroy@kernel.org>
Date: Thu, 29 Dec 2022 04:10:14 +0900
Subject: [PATCH 824/875] kbuild: rpm-pkg: add libelf-devel as alternative for
 BuildRequires

Guoqing Jiang reports that openSUSE cannot compile the kernel rpm due
to "BuildRequires: elfutils-libelf-devel" added by commit 8818039f959b
("kbuild: add ability to make source rpm buildable using koji").
The relevant package name in openSUSE is libelf-devel.

Add it as an alternative package.

BTW, if it is impossible to solve the build requirement, the final
resort would be:

    $ make RPMOPTS=--nodeps rpm-pkg

This passes --nodeps to the rpmbuild command so it will not verify
build dependencies. This is useful to test rpm builds on non-rpm
system. On Debian/Ubuntu, for example, you can install rpmbuild by
'apt-get install rpm'.

NOTE1:
  Likewise, it is possible to bypass the build dependency check for
  debian package builds:

    $ make DPKG_FLAGS=-d deb-pkg

NOTE2:
  The 'or' operator is supported since RPM 4.13. So, old distros such
  as CentOS 7 will break. I suggest installing newer rpmbuild in such
  cases.

Link: https://lore.kernel.org/linux-kbuild/ee227d24-9c94-bfa3-166a-4ee6b5dfea09@linux.dev/T/#u
Fixes: 8818039f959b ("kbuild: add ability to make source rpm buildable using koji")
Reported-by: Guoqing Jiang <guoqing.jiang@linux.dev>
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Reviewed-by: Nathan Chancellor <nathan@kernel.org>
Tested-by: Guoqing Jiang <guoqing.jiang@linux.dev>
Acked-by: Jonathan Toppins <jtoppins@redhat.com>
---
 scripts/package/mkspec | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/scripts/package/mkspec b/scripts/package/mkspec
index dda00a948a01d..adab28fa7f892 100755
--- a/scripts/package/mkspec
+++ b/scripts/package/mkspec
@@ -51,7 +51,8 @@ sed -e '/^DEL/d' -e 's/^\t*//' <<EOF
 	URL: https://www.kernel.org
 $S	Source: kernel-$__KERNELRELEASE.tar.gz
 	Provides: $PROVIDES
-$S	BuildRequires: bc binutils bison dwarves elfutils-libelf-devel flex
+$S	BuildRequires: bc binutils bison dwarves
+$S	BuildRequires: (elfutils-libelf-devel or libelf-devel) flex
 $S	BuildRequires: gcc make openssl openssl-devel perl python3 rsync
 
 	# $UTS_MACHINE as a fallback of _arch in case
-- 
GitLab


From aa4847dbcdabfe80a1cff96480e4b3c8076a0356 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <masahiroy@kernel.org>
Date: Thu, 29 Dec 2022 21:16:42 +0900
Subject: [PATCH 825/875] kbuild: sort single-targets alphabetically again

This was previously alphabetically sorted. Sort it again.

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Reviewed-by: Miguel Ojeda <ojeda@kernel.org>
Reviewed-by: Nathan Chancellor <nathan@kernel.org>
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index d4b6af8c09e9c..a5133e422f69b 100644
--- a/Makefile
+++ b/Makefile
@@ -297,7 +297,7 @@ no-compiler-targets := $(no-dot-config-targets) install dtbs_install \
 			headers_install modules_install kernelrelease image_name
 no-sync-config-targets := $(no-dot-config-targets) %install kernelrelease \
 			  image_name
-single-targets := %.a %.i %.rsi %.ko %.lds %.ll %.lst %.mod %.o %.s %.symtypes %/
+single-targets := %.a %.i %.ko %.lds %.ll %.lst %.mod %.o %.rsi %.s %.symtypes %/
 
 config-build	:=
 mixed-build	:=
-- 
GitLab


From 6a5e25fc3e0b94301734e8abb1d311a1e02d360d Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <masahiroy@kernel.org>
Date: Fri, 30 Dec 2022 17:16:42 +0900
Subject: [PATCH 826/875] fixdep: remove unneeded <stdarg.h> inclusion

This is unneeded since commit 69304379ff03 ("fixdep: use fflush() and
ferror() to ensure successful write to files").

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
---
 scripts/basic/fixdep.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/scripts/basic/fixdep.c b/scripts/basic/fixdep.c
index 2328f9a641dad..f932aeaba71a2 100644
--- a/scripts/basic/fixdep.c
+++ b/scripts/basic/fixdep.c
@@ -94,7 +94,6 @@
 #include <unistd.h>
 #include <fcntl.h>
 #include <string.h>
-#include <stdarg.h>
 #include <stdlib.h>
 #include <stdio.h>
 #include <ctype.h>
-- 
GitLab


From 963bbdb32b47cfa67a449e715e1dcc525fbd01fc Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Mon, 19 Dec 2022 12:59:55 +0200
Subject: [PATCH 827/875] drm/i915/dsi: add support for ICL+ native MIPI GPIO
 sequence
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Starting from ICL, the default for MIPI GPIO sequences seems to be using
native GPIOs i.e. GPIOs available in the GPU. These native GPIOs reuse
many pins that quite frankly seem scary to poke based on the VBT
sequences. We pretty much have to trust that the board is configured
such that the relevant HPD, PP_CONTROL and GPIO bits aren't used for
anything else.

MIPI sequence v4 also adds a flag to fall back to non-native sequences.

v5:
- Wrap SHOTPLUG_CTL_DDI modification in spin_lock() in icp_irq_handler()
  too (Ville)
- References instead of Closes issue 6131 because this does not fix everything

v4:
- Wrap SHOTPLUG_CTL_DDI modification in spin_lock_irq() (Ville)

v3:
- Fix -Wbitwise-conditional-parentheses (kernel test robot <lkp@intel.com>)

v2:
- Fix HPD pin output set (impacts GPIOs 0 and 5)
- Fix GPIO data output direction set (impacts GPIOs 4 and 9)
- Reduce register accesses to single intel_de_rwm()

References: https://gitlab.freedesktop.org/drm/intel/-/issues/6131
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221219105955.4014451-1-jani.nikula@intel.com
(cherry picked from commit f087cfe6fcff58044f7aa3b284965af47f472fb0)
Cc: stable@vger.kernel.org # 6.1
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 94 +++++++++++++++++++-
 drivers/gpu/drm/i915/i915_irq.c              |  3 +
 drivers/gpu/drm/i915/i915_reg.h              |  1 +
 3 files changed, 95 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index fce69fa446d58..41f025f089d9f 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -41,9 +41,11 @@
 
 #include "i915_drv.h"
 #include "i915_reg.h"
+#include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_dsi.h"
 #include "intel_dsi_vbt.h"
+#include "intel_gmbus_regs.h"
 #include "vlv_dsi.h"
 #include "vlv_dsi_regs.h"
 #include "vlv_sideband.h"
@@ -377,6 +379,85 @@ static void icl_exec_gpio(struct intel_connector *connector,
 	drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
 }
 
+enum {
+	MIPI_RESET_1 = 0,
+	MIPI_AVDD_EN_1,
+	MIPI_BKLT_EN_1,
+	MIPI_AVEE_EN_1,
+	MIPI_VIO_EN_1,
+	MIPI_RESET_2,
+	MIPI_AVDD_EN_2,
+	MIPI_BKLT_EN_2,
+	MIPI_AVEE_EN_2,
+	MIPI_VIO_EN_2,
+};
+
+static void icl_native_gpio_set_value(struct drm_i915_private *dev_priv,
+				      int gpio, bool value)
+{
+	int index;
+
+	if (drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 11 && gpio >= MIPI_RESET_2))
+		return;
+
+	switch (gpio) {
+	case MIPI_RESET_1:
+	case MIPI_RESET_2:
+		index = gpio == MIPI_RESET_1 ? HPD_PORT_A : HPD_PORT_B;
+
+		/*
+		 * Disable HPD to set the pin to output, and set output
+		 * value. The HPD pin should not be enabled for DSI anyway,
+		 * assuming the board design and VBT are sane, and the pin isn't
+		 * used by a non-DSI encoder.
+		 *
+		 * The locking protects against concurrent SHOTPLUG_CTL_DDI
+		 * modifications in irq setup and handling.
+		 */
+		spin_lock_irq(&dev_priv->irq_lock);
+		intel_de_rmw(dev_priv, SHOTPLUG_CTL_DDI,
+			     SHOTPLUG_CTL_DDI_HPD_ENABLE(index) |
+			     SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index),
+			     value ? SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index) : 0);
+		spin_unlock_irq(&dev_priv->irq_lock);
+		break;
+	case MIPI_AVDD_EN_1:
+	case MIPI_AVDD_EN_2:
+		index = gpio == MIPI_AVDD_EN_1 ? 0 : 1;
+
+		intel_de_rmw(dev_priv, PP_CONTROL(index), PANEL_POWER_ON,
+			     value ? PANEL_POWER_ON : 0);
+		break;
+	case MIPI_BKLT_EN_1:
+	case MIPI_BKLT_EN_2:
+		index = gpio == MIPI_AVDD_EN_1 ? 0 : 1;
+
+		intel_de_rmw(dev_priv, PP_CONTROL(index), EDP_BLC_ENABLE,
+			     value ? EDP_BLC_ENABLE : 0);
+		break;
+	case MIPI_AVEE_EN_1:
+	case MIPI_AVEE_EN_2:
+		index = gpio == MIPI_AVEE_EN_1 ? 1 : 2;
+
+		intel_de_rmw(dev_priv, GPIO(dev_priv, index),
+			     GPIO_CLOCK_VAL_OUT,
+			     GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT |
+			     GPIO_CLOCK_VAL_MASK | (value ? GPIO_CLOCK_VAL_OUT : 0));
+		break;
+	case MIPI_VIO_EN_1:
+	case MIPI_VIO_EN_2:
+		index = gpio == MIPI_VIO_EN_1 ? 1 : 2;
+
+		intel_de_rmw(dev_priv, GPIO(dev_priv, index),
+			     GPIO_DATA_VAL_OUT,
+			     GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT |
+			     GPIO_DATA_VAL_MASK | (value ? GPIO_DATA_VAL_OUT : 0));
+		break;
+	default:
+		MISSING_CASE(gpio);
+	}
+}
+
 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 {
 	struct drm_device *dev = intel_dsi->base.base.dev;
@@ -384,8 +465,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 	struct intel_connector *connector = intel_dsi->attached_connector;
 	u8 gpio_source, gpio_index = 0, gpio_number;
 	bool value;
-
-	drm_dbg_kms(&dev_priv->drm, "\n");
+	bool native = DISPLAY_VER(dev_priv) >= 11;
 
 	if (connector->panel.vbt.dsi.seq_version >= 3)
 		gpio_index = *data++;
@@ -398,10 +478,18 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 	else
 		gpio_source = 0;
 
+	if (connector->panel.vbt.dsi.seq_version >= 4 && *data & BIT(1))
+		native = false;
+
 	/* pull up/down */
 	value = *data++ & 1;
 
-	if (DISPLAY_VER(dev_priv) >= 11)
+	drm_dbg_kms(&dev_priv->drm, "GPIO index %u, number %u, source %u, native %s, set to %s\n",
+		    gpio_index, gpio_number, gpio_source, str_yes_no(native), str_on_off(value));
+
+	if (native)
+		icl_native_gpio_set_value(dev_priv, gpio_number, value);
+	else if (DISPLAY_VER(dev_priv) >= 11)
 		icl_exec_gpio(connector, gpio_source, gpio_index, value);
 	else if (IS_VALLEYVIEW(dev_priv))
 		vlv_exec_gpio(connector, gpio_source, gpio_number, value);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index edfe363af8389..91c5339860412 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1974,7 +1974,10 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 	if (ddi_hotplug_trigger) {
 		u32 dig_hotplug_reg;
 
+		/* Locking due to DSI native GPIO sequences */
+		spin_lock(&dev_priv->irq_lock);
 		dig_hotplug_reg = intel_uncore_rmw(&dev_priv->uncore, SHOTPLUG_CTL_DDI, 0, 0);
+		spin_unlock(&dev_priv->irq_lock);
 
 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
 				   ddi_hotplug_trigger, dig_hotplug_reg,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8e1892d147741..9161768725449 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5988,6 +5988,7 @@
 
 #define SHOTPLUG_CTL_DDI				_MMIO(0xc4030)
 #define   SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin)			(0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define   SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin)		(0x4 << (_HPD_PIN_DDI(hpd_pin) * 4))
 #define   SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin)		(0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
 #define   SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin)		(0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
 #define   SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin)		(0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
-- 
GitLab


From 6217e9f05a74df48c77ee68993d587cdfdb1feb7 Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@intel.com>
Date: Tue, 20 Dec 2022 16:01:05 +0200
Subject: [PATCH 828/875] drm/i915/dsi: fix MIPI_BKLT_EN_1 native GPIO index
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Due to copy-paste fail, MIPI_BKLT_EN_1 would always use PPS index 1,
never 0. Fix the sloppiest commit in recent memory.

Fixes: 963bbdb32b47 ("drm/i915/dsi: add support for ICL+ native MIPI GPIO sequence")
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221220140105.313333-1-jani.nikula@intel.com
(cherry picked from commit a561933c571798868b5fa42198427a7e6df56c09)
Cc: stable@vger.kernel.org # 6.1
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index 41f025f089d9f..2cbc1292ab382 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -430,7 +430,7 @@ static void icl_native_gpio_set_value(struct drm_i915_private *dev_priv,
 		break;
 	case MIPI_BKLT_EN_1:
 	case MIPI_BKLT_EN_2:
-		index = gpio == MIPI_AVDD_EN_1 ? 0 : 1;
+		index = gpio == MIPI_BKLT_EN_1 ? 0 : 1;
 
 		intel_de_rmw(dev_priv, PP_CONTROL(index), EDP_BLC_ENABLE,
 			     value ? EDP_BLC_ENABLE : 0);
-- 
GitLab


From ba2dc1cb5491712a6946d0595cf11ba463f50e64 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Thu, 29 Dec 2022 17:45:01 +0100
Subject: [PATCH 829/875] gpiolib: Fix using uninitialized lookup-flags on ACPI
 platforms

Commit 8eb1f71e7acc ("gpiolib: consolidate GPIO lookups") refactors
fwnode_get_named_gpiod() and gpiod_get_index() into a unified
gpiod_find_and_request() helper.

The old functions both initialized their local lookupflags variable to
GPIO_LOOKUP_FLAGS_DEFAULT, but the new code leaves it uninitialized.

This is a problem for at least ACPI platforms, where acpi_find_gpio()
only does a bunch of *lookupflags |= GPIO_* statements and thus relies
on the variable being initialized.

The variable not being initialized leads to:

1. Potentially the wrong flags getting used
2. The check for conflicting lookup flags in gpiod_configure_flags():
   "multiple pull-up, pull-down or pull-disable enabled, invalid config"
   sometimes triggering, making the GPIO unavailable

Restore the initialization of lookupflags to GPIO_LOOKUP_FLAGS_DEFAULT
to fix this.

Fixes: 8eb1f71e7acc ("gpiolib: consolidate GPIO lookups")
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
 drivers/gpio/gpiolib.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 5a66d9616d7cc..939c776b94881 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -3905,8 +3905,8 @@ static struct gpio_desc *gpiod_find_and_request(struct device *consumer,
 						const char *label,
 						bool platform_lookup_allowed)
 {
+	unsigned long lookupflags = GPIO_LOOKUP_FLAGS_DEFAULT;
 	struct gpio_desc *desc = ERR_PTR(-ENOENT);
-	unsigned long lookupflags;
 	int ret;
 
 	if (!IS_ERR_OR_NULL(fwnode))
-- 
GitLab


From 90fee3dd5bfc1b9f4c8c0ba6cd2a35c9d79ca4de Mon Sep 17 00:00:00 2001
From: Haibo Chen <haibo.chen@nxp.com>
Date: Sun, 11 Dec 2022 00:05:58 +0200
Subject: [PATCH 830/875] gpio: pca953x: avoid to use uninitialized value
 pinctrl

There is a variable pinctrl declared without initializer. And then
has the case (switch operation chose the default case) to directly
use this uninitialized value, this is not a safe behavior. So here
initialize the pinctrl as 0 to avoid this issue.
This is reported by Coverity.

Fixes: 13c5d4ce8060 ("gpio: pca953x: Add support for PCAL6534")
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
 drivers/gpio/gpio-pca953x.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
index a59d61cd44b2e..5299e5bb76d6e 100644
--- a/drivers/gpio/gpio-pca953x.c
+++ b/drivers/gpio/gpio-pca953x.c
@@ -474,6 +474,9 @@ static u8 pcal6534_recalc_addr(struct pca953x_chip *chip, int reg, int off)
 	case PCAL6524_DEBOUNCE:
 		pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x1c;
 		break;
+	default:
+		pinctrl = 0;
+		break;
 	}
 
 	return pinctrl + addr + (off / BANK_SZ);
-- 
GitLab


From 2788938b794633fc1865c805764bed196e01f97e Mon Sep 17 00:00:00 2001
From: Cixi Geng <cixi.geng1@unisoc.com>
Date: Thu, 29 Dec 2022 22:55:43 +0800
Subject: [PATCH 831/875] gpio: eic-sprd: Make the irqchip immutable

Remove the irq_chip from pmic_eic structure,
use the various calls by defining the statically
irq_chip structure.

Signed-off-by: Cixi Geng <cixi.geng1@unisoc.com>
Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
 drivers/gpio/gpio-eic-sprd.c | 23 ++++++++++++++---------
 1 file changed, 14 insertions(+), 9 deletions(-)

diff --git a/drivers/gpio/gpio-eic-sprd.c b/drivers/gpio/gpio-eic-sprd.c
index 8d722e026e9c9..84352a6f4973b 100644
--- a/drivers/gpio/gpio-eic-sprd.c
+++ b/drivers/gpio/gpio-eic-sprd.c
@@ -91,7 +91,6 @@ enum sprd_eic_type {
 
 struct sprd_eic {
 	struct gpio_chip chip;
-	struct irq_chip intc;
 	void __iomem *base[SPRD_EIC_MAX_BANK];
 	enum sprd_eic_type type;
 	spinlock_t lock;
@@ -255,6 +254,8 @@ static void sprd_eic_irq_mask(struct irq_data *data)
 	default:
 		dev_err(chip->parent, "Unsupported EIC type.\n");
 	}
+
+	gpiochip_disable_irq(chip, offset);
 }
 
 static void sprd_eic_irq_unmask(struct irq_data *data)
@@ -263,6 +264,8 @@ static void sprd_eic_irq_unmask(struct irq_data *data)
 	struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
 	u32 offset = irqd_to_hwirq(data);
 
+	gpiochip_enable_irq(chip, offset);
+
 	switch (sprd_eic->type) {
 	case SPRD_EIC_DEBOUNCE:
 		sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 1);
@@ -564,6 +567,15 @@ static void sprd_eic_irq_handler(struct irq_desc *desc)
 	chained_irq_exit(ic, desc);
 }
 
+static const struct irq_chip sprd_eic_irq = {
+	.name		= "sprd-eic",
+	.irq_ack	= sprd_eic_irq_ack,
+	.irq_mask	= sprd_eic_irq_mask,
+	.irq_unmask	= sprd_eic_irq_unmask,
+	.irq_set_type	= sprd_eic_irq_set_type,
+	.flags		= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
+	GPIOCHIP_IRQ_RESOURCE_HELPERS,
+};
 static int sprd_eic_probe(struct platform_device *pdev)
 {
 	const struct sprd_eic_variant_data *pdata;
@@ -626,15 +638,8 @@ static int sprd_eic_probe(struct platform_device *pdev)
 		break;
 	}
 
-	sprd_eic->intc.name = dev_name(&pdev->dev);
-	sprd_eic->intc.irq_ack = sprd_eic_irq_ack;
-	sprd_eic->intc.irq_mask = sprd_eic_irq_mask;
-	sprd_eic->intc.irq_unmask = sprd_eic_irq_unmask;
-	sprd_eic->intc.irq_set_type = sprd_eic_irq_set_type;
-	sprd_eic->intc.flags = IRQCHIP_SKIP_SET_WAKE;
-
 	irq = &sprd_eic->chip.irq;
-	irq->chip = &sprd_eic->intc;
+	gpio_irq_chip_set_chip(irq, &sprd_eic_irq);
 	irq->handler = handle_bad_irq;
 	irq->default_type = IRQ_TYPE_NONE;
 	irq->parent_handler = sprd_eic_irq_handler;
-- 
GitLab


From be43eea7de5a3977ac3d13fbfb9e505fab475e97 Mon Sep 17 00:00:00 2001
From: Cixi Geng <cixi.geng1@unisoc.com>
Date: Thu, 29 Dec 2022 22:55:44 +0800
Subject: [PATCH 832/875] gpio: pmic-eic-sprd: Make the irqchip immutable

Remove the irq_chip from pmic_eic structure,
use the various calls by defining the statically
irq_chip structure.

Signed-off-by: Cixi Geng <cixi.geng1@unisoc.com>
Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
 drivers/gpio/gpio-pmic-eic-sprd.c | 29 ++++++++++++++++++-----------
 1 file changed, 18 insertions(+), 11 deletions(-)

diff --git a/drivers/gpio/gpio-pmic-eic-sprd.c b/drivers/gpio/gpio-pmic-eic-sprd.c
index e518490c4b681..c3e4d90f6b183 100644
--- a/drivers/gpio/gpio-pmic-eic-sprd.c
+++ b/drivers/gpio/gpio-pmic-eic-sprd.c
@@ -47,7 +47,6 @@ enum {
 /**
  * struct sprd_pmic_eic - PMIC EIC controller
  * @chip: the gpio_chip structure.
- * @intc: the irq_chip structure.
  * @map:  the regmap from the parent device.
  * @offset: the EIC controller's offset address of the PMIC.
  * @reg: the array to cache the EIC registers.
@@ -56,7 +55,6 @@ enum {
  */
 struct sprd_pmic_eic {
 	struct gpio_chip chip;
-	struct irq_chip intc;
 	struct regmap *map;
 	u32 offset;
 	u8 reg[CACHE_NR_REGS];
@@ -151,15 +149,21 @@ static void sprd_pmic_eic_irq_mask(struct irq_data *data)
 {
 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
+	u32 offset = irqd_to_hwirq(data);
 
 	pmic_eic->reg[REG_IE] = 0;
 	pmic_eic->reg[REG_TRIG] = 0;
+
+	gpiochip_disable_irq(chip, offset);
 }
 
 static void sprd_pmic_eic_irq_unmask(struct irq_data *data)
 {
 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
+	u32 offset = irqd_to_hwirq(data);
+
+	gpiochip_enable_irq(chip, offset);
 
 	pmic_eic->reg[REG_IE] = 1;
 	pmic_eic->reg[REG_TRIG] = 1;
@@ -292,6 +296,17 @@ static irqreturn_t sprd_pmic_eic_irq_handler(int irq, void *data)
 	return IRQ_HANDLED;
 }
 
+static const struct irq_chip pmic_eic_irq_chip = {
+	.name			= "sprd-pmic-eic",
+	.irq_mask		= sprd_pmic_eic_irq_mask,
+	.irq_unmask		= sprd_pmic_eic_irq_unmask,
+	.irq_set_type		= sprd_pmic_eic_irq_set_type,
+	.irq_bus_lock		= sprd_pmic_eic_bus_lock,
+	.irq_bus_sync_unlock	= sprd_pmic_eic_bus_sync_unlock,
+	.flags			= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
+	GPIOCHIP_IRQ_RESOURCE_HELPERS,
+};
+
 static int sprd_pmic_eic_probe(struct platform_device *pdev)
 {
 	struct gpio_irq_chip *irq;
@@ -338,16 +353,8 @@ static int sprd_pmic_eic_probe(struct platform_device *pdev)
 	pmic_eic->chip.set = sprd_pmic_eic_set;
 	pmic_eic->chip.get = sprd_pmic_eic_get;
 
-	pmic_eic->intc.name = dev_name(&pdev->dev);
-	pmic_eic->intc.irq_mask = sprd_pmic_eic_irq_mask;
-	pmic_eic->intc.irq_unmask = sprd_pmic_eic_irq_unmask;
-	pmic_eic->intc.irq_set_type = sprd_pmic_eic_irq_set_type;
-	pmic_eic->intc.irq_bus_lock = sprd_pmic_eic_bus_lock;
-	pmic_eic->intc.irq_bus_sync_unlock = sprd_pmic_eic_bus_sync_unlock;
-	pmic_eic->intc.flags = IRQCHIP_SKIP_SET_WAKE;
-
 	irq = &pmic_eic->chip.irq;
-	irq->chip = &pmic_eic->intc;
+	gpio_irq_chip_set_chip(irq, &pmic_eic_irq_chip);
 	irq->threaded = true;
 
 	ret = devm_gpiochip_add_data(&pdev->dev, &pmic_eic->chip, pmic_eic);
-- 
GitLab


From 9883ddf9d68db5332f08dfc7283db69f69f8d6d2 Mon Sep 17 00:00:00 2001
From: Cixi Geng <cixi.geng1@unisoc.com>
Date: Thu, 29 Dec 2022 22:55:45 +0800
Subject: [PATCH 833/875] gpio: sprd: Make the irqchip immutable

Make the struct irq_chip const, flag it as IRQCHIP_IMMUTABLE, add the
new helper functions, and call the appropriate gpiolib functions.

Signed-off-by: Cixi Geng <cixi.geng1@unisoc.com>
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Julia Lawall <julia.lawall@lip6.fr>
Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
 drivers/gpio/gpio-sprd.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpio/gpio-sprd.c b/drivers/gpio/gpio-sprd.c
index 9bff63990eee4..072b4e6532164 100644
--- a/drivers/gpio/gpio-sprd.c
+++ b/drivers/gpio/gpio-sprd.c
@@ -120,6 +120,7 @@ static void sprd_gpio_irq_mask(struct irq_data *data)
 	u32 offset = irqd_to_hwirq(data);
 
 	sprd_gpio_update(chip, offset, SPRD_GPIO_IE, 0);
+	gpiochip_disable_irq(chip, offset);
 }
 
 static void sprd_gpio_irq_ack(struct irq_data *data)
@@ -136,6 +137,7 @@ static void sprd_gpio_irq_unmask(struct irq_data *data)
 	u32 offset = irqd_to_hwirq(data);
 
 	sprd_gpio_update(chip, offset, SPRD_GPIO_IE, 1);
+	gpiochip_enable_irq(chip, offset);
 }
 
 static int sprd_gpio_irq_set_type(struct irq_data *data,
@@ -205,13 +207,14 @@ static void sprd_gpio_irq_handler(struct irq_desc *desc)
 	chained_irq_exit(ic, desc);
 }
 
-static struct irq_chip sprd_gpio_irqchip = {
+static const struct irq_chip sprd_gpio_irqchip = {
 	.name = "sprd-gpio",
 	.irq_ack = sprd_gpio_irq_ack,
 	.irq_mask = sprd_gpio_irq_mask,
 	.irq_unmask = sprd_gpio_irq_unmask,
 	.irq_set_type = sprd_gpio_irq_set_type,
-	.flags = IRQCHIP_SKIP_SET_WAKE,
+	.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
+	GPIOCHIP_IRQ_RESOURCE_HELPERS,
 };
 
 static int sprd_gpio_probe(struct platform_device *pdev)
@@ -245,7 +248,7 @@ static int sprd_gpio_probe(struct platform_device *pdev)
 	sprd_gpio->chip.direction_output = sprd_gpio_direction_output;
 
 	irq = &sprd_gpio->chip.irq;
-	irq->chip = &sprd_gpio_irqchip;
+	gpio_irq_chip_set_chip(irq, &sprd_gpio_irqchip);
 	irq->handler = handle_bad_irq;
 	irq->default_type = IRQ_TYPE_NONE;
 	irq->parent_handler = sprd_gpio_irq_handler;
-- 
GitLab


From 9807ae69746196ee4bbffe7d22d22ab2b61c6ed0 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 29 Dec 2022 17:33:32 +0100
Subject: [PATCH 834/875] net: dsa: qca8k: fix wrong length value for mgmt eth
 packet

The assumption that Documentation was right about how this value work was
wrong. It was discovered that the length value of the mgmt header is in
step of word size.

As an example to process 4 byte of data the correct length to set is 2.
To process 8 byte 4, 12 byte 6, 16 byte 8...

Odd values will always return the next size on the ack packet.
(length of 3 (6 byte) will always return 8 bytes of data)

This means that a value of 15 (0xf) actually means reading/writing 32 bytes
of data instead of 16 bytes. This behaviour is totally absent and not
documented in the switch Documentation.

In fact from Documentation the max value that mgmt eth can process is
16 byte of data while in reality it can process 32 bytes at once.

To handle this we always round up the length after deviding it for word
size. We check if the result is odd and we round another time to align
to what the switch will provide in the ack packet.
The workaround for the length limit of 15 is still needed as the length
reg max value is 0xf(15)

Reported-by: Ronald Wahl <ronald.wahl@raritan.com>
Tested-by: Ronald Wahl <ronald.wahl@raritan.com>
Fixes: 90386223f44e ("net: dsa: qca8k: add support for larger read/write size with mgmt Ethernet")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Cc: stable@vger.kernel.org # v5.18+
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/dsa/qca/qca8k-8xxx.c | 45 +++++++++++++++++++++++++-------
 1 file changed, 35 insertions(+), 10 deletions(-)

diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8xxx.c
index c5c3b4e92f28b..46151320b2a8f 100644
--- a/drivers/net/dsa/qca/qca8k-8xxx.c
+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
@@ -146,7 +146,16 @@ static void qca8k_rw_reg_ack_handler(struct dsa_switch *ds, struct sk_buff *skb)
 
 	command = get_unaligned_le32(&mgmt_ethhdr->command);
 	cmd = FIELD_GET(QCA_HDR_MGMT_CMD, command);
+
 	len = FIELD_GET(QCA_HDR_MGMT_LENGTH, command);
+	/* Special case for len of 15 as this is the max value for len and needs to
+	 * be increased before converting it from word to dword.
+	 */
+	if (len == 15)
+		len++;
+
+	/* We can ignore odd value, we always round up them in the alloc function. */
+	len *= sizeof(u16);
 
 	/* Make sure the seq match the requested packet */
 	if (get_unaligned_le32(&mgmt_ethhdr->seq) == mgmt_eth_data->seq)
@@ -193,17 +202,33 @@ static struct sk_buff *qca8k_alloc_mdio_header(enum mdio_cmd cmd, u32 reg, u32 *
 	if (!skb)
 		return NULL;
 
-	/* Max value for len reg is 15 (0xf) but the switch actually return 16 byte
-	 * Actually for some reason the steps are:
-	 * 0: nothing
-	 * 1-4: first 4 byte
-	 * 5-6: first 12 byte
-	 * 7-15: all 16 byte
+	/* Hdr mgmt length value is in step of word size.
+	 * As an example to process 4 byte of data the correct length to set is 2.
+	 * To process 8 byte 4, 12 byte 6, 16 byte 8...
+	 *
+	 * Odd values will always return the next size on the ack packet.
+	 * (length of 3 (6 byte) will always return 8 bytes of data)
+	 *
+	 * This means that a value of 15 (0xf) actually means reading/writing 32 bytes
+	 * of data.
+	 *
+	 * To correctly calculate the length we devide the requested len by word and
+	 * round up.
+	 * On the ack function we can skip the odd check as we already handle the
+	 * case here.
+	 */
+	real_len = DIV_ROUND_UP(len, sizeof(u16));
+
+	/* We check if the result len is odd and we round up another time to
+	 * the next size. (length of 3 will be increased to 4 as switch will always
+	 * return 8 bytes)
 	 */
-	if (len == 16)
-		real_len = 15;
-	else
-		real_len = len;
+	if (real_len % sizeof(u16) != 0)
+		real_len++;
+
+	/* Max reg value is 0xf(15) but switch will always return the next size (32 byte) */
+	if (real_len == 16)
+		real_len--;
 
 	skb_reset_mac_header(skb);
 	skb_set_network_header(skb, skb->len);
-- 
GitLab


From d9dba91be71f03cc75bcf39fc0d5d99ff33f1ae0 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 29 Dec 2022 17:33:33 +0100
Subject: [PATCH 835/875] net: dsa: tag_qca: fix wrong MGMT_DATA2 size

It was discovered that MGMT_DATA2 can contain up to 28 bytes of data
instead of the 12 bytes written in the Documentation by accounting the
limit of 16 bytes declared in Documentation subtracting the first 4 byte
in the packet header.

Update the define with the real world value.

Tested-by: Ronald Wahl <ronald.wahl@raritan.com>
Fixes: c2ee8181fddb ("net: dsa: tag_qca: add define for handling mgmt Ethernet packet")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Cc: stable@vger.kernel.org # v5.18+
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 include/linux/dsa/tag_qca.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/linux/dsa/tag_qca.h b/include/linux/dsa/tag_qca.h
index b1b5720d89a59..ee657452f122a 100644
--- a/include/linux/dsa/tag_qca.h
+++ b/include/linux/dsa/tag_qca.h
@@ -45,8 +45,8 @@ struct sk_buff;
 					QCA_HDR_MGMT_COMMAND_LEN + \
 					QCA_HDR_MGMT_DATA1_LEN)
 
-#define QCA_HDR_MGMT_DATA2_LEN		12 /* Other 12 byte for the mdio data */
-#define QCA_HDR_MGMT_PADDING_LEN	34 /* Padding to reach the min Ethernet packet */
+#define QCA_HDR_MGMT_DATA2_LEN		28 /* Other 28 byte for the mdio data */
+#define QCA_HDR_MGMT_PADDING_LEN	18 /* Padding to reach the min Ethernet packet */
 
 #define QCA_HDR_MGMT_PKT_LEN		(QCA_HDR_MGMT_HEADER_LEN + \
 					QCA_HDR_LEN + \
-- 
GitLab


From 03cb9e6d0b32b768e3d9d473c5c4ca1100877664 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 29 Dec 2022 17:33:34 +0100
Subject: [PATCH 836/875] Revert "net: dsa: qca8k: cache lo and hi for mdio
 write"

This reverts commit 2481d206fae7884cd07014fd1318e63af35e99eb.

The Documentation is very confusing about the topic.
The cache logic for hi and lo is wrong and actually miss some regs to be
actually written.

What the Documentation actually intended was that it's possible to skip
writing hi OR lo if half of the reg is not needed to be written or read.

Revert the change in favor of a better and correct implementation.

Reported-by: Ronald Wahl <ronald.wahl@raritan.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Cc: stable@vger.kernel.org # v5.18+
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/dsa/qca/qca8k-8xxx.c | 61 +++++++-------------------------
 drivers/net/dsa/qca/qca8k.h      |  5 ---
 2 files changed, 12 insertions(+), 54 deletions(-)

diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8xxx.c
index 46151320b2a8f..fbcd5c2b13aeb 100644
--- a/drivers/net/dsa/qca/qca8k-8xxx.c
+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
@@ -36,44 +36,6 @@ qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
 	*page = regaddr & 0x3ff;
 }
 
-static int
-qca8k_set_lo(struct qca8k_priv *priv, int phy_id, u32 regnum, u16 lo)
-{
-	u16 *cached_lo = &priv->mdio_cache.lo;
-	struct mii_bus *bus = priv->bus;
-	int ret;
-
-	if (lo == *cached_lo)
-		return 0;
-
-	ret = bus->write(bus, phy_id, regnum, lo);
-	if (ret < 0)
-		dev_err_ratelimited(&bus->dev,
-				    "failed to write qca8k 32bit lo register\n");
-
-	*cached_lo = lo;
-	return 0;
-}
-
-static int
-qca8k_set_hi(struct qca8k_priv *priv, int phy_id, u32 regnum, u16 hi)
-{
-	u16 *cached_hi = &priv->mdio_cache.hi;
-	struct mii_bus *bus = priv->bus;
-	int ret;
-
-	if (hi == *cached_hi)
-		return 0;
-
-	ret = bus->write(bus, phy_id, regnum, hi);
-	if (ret < 0)
-		dev_err_ratelimited(&bus->dev,
-				    "failed to write qca8k 32bit hi register\n");
-
-	*cached_hi = hi;
-	return 0;
-}
-
 static int
 qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
 {
@@ -97,7 +59,7 @@ qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
 }
 
 static void
-qca8k_mii_write32(struct qca8k_priv *priv, int phy_id, u32 regnum, u32 val)
+qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
 {
 	u16 lo, hi;
 	int ret;
@@ -105,9 +67,12 @@ qca8k_mii_write32(struct qca8k_priv *priv, int phy_id, u32 regnum, u32 val)
 	lo = val & 0xffff;
 	hi = (u16)(val >> 16);
 
-	ret = qca8k_set_lo(priv, phy_id, regnum, lo);
+	ret = bus->write(bus, phy_id, regnum, lo);
 	if (ret >= 0)
-		ret = qca8k_set_hi(priv, phy_id, regnum + 1, hi);
+		ret = bus->write(bus, phy_id, regnum + 1, hi);
+	if (ret < 0)
+		dev_err_ratelimited(&bus->dev,
+				    "failed to write qca8k 32bit register\n");
 }
 
 static int
@@ -442,7 +407,7 @@ qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
 	if (ret < 0)
 		goto exit;
 
-	qca8k_mii_write32(priv, 0x10 | r2, r1, val);
+	qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 
 exit:
 	mutex_unlock(&bus->mdio_lock);
@@ -475,7 +440,7 @@ qca8k_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, uint32_t write_
 
 	val &= ~mask;
 	val |= write_val;
-	qca8k_mii_write32(priv, 0x10 | r2, r1, val);
+	qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 
 exit:
 	mutex_unlock(&bus->mdio_lock);
@@ -750,14 +715,14 @@ qca8k_mdio_write(struct qca8k_priv *priv, int phy, int regnum, u16 data)
 	if (ret)
 		goto exit;
 
-	qca8k_mii_write32(priv, 0x10 | r2, r1, val);
+	qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 
 	ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
 				   QCA8K_MDIO_MASTER_BUSY);
 
 exit:
 	/* even if the busy_wait timeouts try to clear the MASTER_EN */
-	qca8k_mii_write32(priv, 0x10 | r2, r1, 0);
+	qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
 
 	mutex_unlock(&bus->mdio_lock);
 
@@ -787,7 +752,7 @@ qca8k_mdio_read(struct qca8k_priv *priv, int phy, int regnum)
 	if (ret)
 		goto exit;
 
-	qca8k_mii_write32(priv, 0x10 | r2, r1, val);
+	qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 
 	ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
 				   QCA8K_MDIO_MASTER_BUSY);
@@ -798,7 +763,7 @@ qca8k_mdio_read(struct qca8k_priv *priv, int phy, int regnum)
 
 exit:
 	/* even if the busy_wait timeouts try to clear the MASTER_EN */
-	qca8k_mii_write32(priv, 0x10 | r2, r1, 0);
+	qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
 
 	mutex_unlock(&bus->mdio_lock);
 
@@ -1968,8 +1933,6 @@ qca8k_sw_probe(struct mdio_device *mdiodev)
 	}
 
 	priv->mdio_cache.page = 0xffff;
-	priv->mdio_cache.lo = 0xffff;
-	priv->mdio_cache.hi = 0xffff;
 
 	/* Check the detected switch id */
 	ret = qca8k_read_switch_id(priv);
diff --git a/drivers/net/dsa/qca/qca8k.h b/drivers/net/dsa/qca/qca8k.h
index 0b7a5cb123216..03514f7a20bec 100644
--- a/drivers/net/dsa/qca/qca8k.h
+++ b/drivers/net/dsa/qca/qca8k.h
@@ -375,11 +375,6 @@ struct qca8k_mdio_cache {
  * mdio writes
  */
 	u16 page;
-/* lo and hi can also be cached and from Documentation we can skip one
- * extra mdio write if lo or hi is didn't change.
- */
-	u16 lo;
-	u16 hi;
 };
 
 struct qca8k_pcs {
-- 
GitLab


From cfbd6de588ef659c198083205dc954a6d3ed2aec Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 29 Dec 2022 17:33:35 +0100
Subject: [PATCH 837/875] net: dsa: qca8k: introduce single mii read/write
 lo/hi

It may be useful to read/write just the lo or hi half of a reg.

This is especially useful for phy poll with the use of mdio master.
The mdio master reg is composed by the first 16 bit related to setup and
the other half with the returned data or data to write.

Refactor the mii function to permit single mii read/write of lo or hi
half of the reg.

Tested-by: Ronald Wahl <ronald.wahl@raritan.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/dsa/qca/qca8k-8xxx.c | 106 ++++++++++++++++++++++++-------
 1 file changed, 84 insertions(+), 22 deletions(-)

diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8xxx.c
index fbcd5c2b13aeb..92c4bfef7c974 100644
--- a/drivers/net/dsa/qca/qca8k-8xxx.c
+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
@@ -37,42 +37,104 @@ qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
 }
 
 static int
-qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
+qca8k_mii_write_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
 {
 	int ret;
+	u16 lo;
 
-	ret = bus->read(bus, phy_id, regnum);
-	if (ret >= 0) {
-		*val = ret;
-		ret = bus->read(bus, phy_id, regnum + 1);
-		*val |= ret << 16;
-	}
+	lo = val & 0xffff;
+	ret = bus->write(bus, phy_id, regnum, lo);
+	if (ret < 0)
+		dev_err_ratelimited(&bus->dev,
+				    "failed to write qca8k 32bit lo register\n");
 
-	if (ret < 0) {
+	return ret;
+}
+
+static int
+qca8k_mii_write_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
+{
+	int ret;
+	u16 hi;
+
+	hi = (u16)(val >> 16);
+	ret = bus->write(bus, phy_id, regnum, hi);
+	if (ret < 0)
 		dev_err_ratelimited(&bus->dev,
-				    "failed to read qca8k 32bit register\n");
-		*val = 0;
-		return ret;
-	}
+				    "failed to write qca8k 32bit hi register\n");
+
+	return ret;
+}
+
+static int
+qca8k_mii_read_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
+{
+	int ret;
+
+	ret = bus->read(bus, phy_id, regnum);
+	if (ret < 0)
+		goto err;
 
+	*val = ret & 0xffff;
 	return 0;
+
+err:
+	dev_err_ratelimited(&bus->dev,
+			    "failed to read qca8k 32bit lo register\n");
+	*val = 0;
+
+	return ret;
 }
 
-static void
-qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
+static int
+qca8k_mii_read_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
 {
-	u16 lo, hi;
 	int ret;
 
-	lo = val & 0xffff;
-	hi = (u16)(val >> 16);
+	ret = bus->read(bus, phy_id, regnum);
+	if (ret < 0)
+		goto err;
 
-	ret = bus->write(bus, phy_id, regnum, lo);
-	if (ret >= 0)
-		ret = bus->write(bus, phy_id, regnum + 1, hi);
+	*val = ret << 16;
+	return 0;
+
+err:
+	dev_err_ratelimited(&bus->dev,
+			    "failed to read qca8k 32bit hi register\n");
+	*val = 0;
+
+	return ret;
+}
+
+static int
+qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
+{
+	u32 hi, lo;
+	int ret;
+
+	*val = 0;
+
+	ret = qca8k_mii_read_lo(bus, phy_id, regnum, &lo);
 	if (ret < 0)
-		dev_err_ratelimited(&bus->dev,
-				    "failed to write qca8k 32bit register\n");
+		goto err;
+
+	ret = qca8k_mii_read_hi(bus, phy_id, regnum + 1, &hi);
+	if (ret < 0)
+		goto err;
+
+	*val = lo | hi;
+
+err:
+	return ret;
+}
+
+static void
+qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
+{
+	if (qca8k_mii_write_lo(bus, phy_id, regnum, val) < 0)
+		return;
+
+	qca8k_mii_write_hi(bus, phy_id, regnum + 1, val);
 }
 
 static int
-- 
GitLab


From a4165830ca237f2b3318faf62562bce8ce12a389 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 29 Dec 2022 17:33:36 +0100
Subject: [PATCH 838/875] net: dsa: qca8k: improve mdio master read/write by
 using single lo/hi

Improve mdio master read/write by using singe mii read/write lo/hi.

In a read and write we need to poll the mdio master regs in a busy loop
to check for a specific bit present in the upper half of the reg. We can
ignore the other half since it won't contain useful data. This will save
an additional useless read for each read and write operation.

In a read operation the returned data is present in the mdio master reg
lower half. We can ignore the other half since it won't contain useful
data. This will save an additional useless read for each read operation.

In a read operation it's needed to just set the hi half of the mdio
master reg as the lo half will be replaced by the result. This will save
an additional useless write for each read operation.

Tested-by: Ronald Wahl <ronald.wahl@raritan.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/dsa/qca/qca8k-8xxx.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8xxx.c
index 92c4bfef7c974..2f224b166bbb3 100644
--- a/drivers/net/dsa/qca/qca8k-8xxx.c
+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
@@ -740,9 +740,9 @@ qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask)
 
 	qca8k_split_addr(reg, &r1, &r2, &page);
 
-	ret = read_poll_timeout(qca8k_mii_read32, ret1, !(val & mask), 0,
+	ret = read_poll_timeout(qca8k_mii_read_hi, ret1, !(val & mask), 0,
 				QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
-				bus, 0x10 | r2, r1, &val);
+				bus, 0x10 | r2, r1 + 1, &val);
 
 	/* Check if qca8k_read has failed for a different reason
 	 * before returnting -ETIMEDOUT
@@ -784,7 +784,7 @@ qca8k_mdio_write(struct qca8k_priv *priv, int phy, int regnum, u16 data)
 
 exit:
 	/* even if the busy_wait timeouts try to clear the MASTER_EN */
-	qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
+	qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, 0);
 
 	mutex_unlock(&bus->mdio_lock);
 
@@ -814,18 +814,18 @@ qca8k_mdio_read(struct qca8k_priv *priv, int phy, int regnum)
 	if (ret)
 		goto exit;
 
-	qca8k_mii_write32(bus, 0x10 | r2, r1, val);
+	qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, val);
 
 	ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
 				   QCA8K_MDIO_MASTER_BUSY);
 	if (ret)
 		goto exit;
 
-	ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
+	ret = qca8k_mii_read_lo(bus, 0x10 | r2, r1, &val);
 
 exit:
 	/* even if the busy_wait timeouts try to clear the MASTER_EN */
-	qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
+	qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, 0);
 
 	mutex_unlock(&bus->mdio_lock);
 
-- 
GitLab


From 6d4cfcf97986cc67635630a2bc1f8d5c92ecdbba Mon Sep 17 00:00:00 2001
From: Sean Anderson <sean.anderson@seco.com>
Date: Thu, 29 Dec 2022 15:21:20 -0500
Subject: [PATCH 839/875] net: phy: Update documentation for get_rate_matching

Now that phylink no longer calls phy_get_rate_matching with
PHY_INTERFACE_MODE_NA, phys no longer need to support it. Remove the
documentation mandating support.

Fixes: 7642cc28fd37 ("net: phylink: fix PHY validation with rate adaption")
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 include/linux/phy.h | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/include/linux/phy.h b/include/linux/phy.h
index 71eeb4e3b1fde..6378c997ded56 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -826,10 +826,7 @@ struct phy_driver {
 	 * whether to advertise lower-speed modes for that interface. It is
 	 * assumed that if a rate matching mode is supported on an interface,
 	 * then that interface's rate can be adapted to all slower link speeds
-	 * supported by the phy. If iface is %PHY_INTERFACE_MODE_NA, and the phy
-	 * supports any kind of rate matching for any interface, then it must
-	 * return that rate matching mode (preferring %RATE_MATCH_PAUSE to
-	 * %RATE_MATCH_CRS). If the interface is not supported, this should
+	 * supported by the phy. If the interface is not supported, this should
 	 * return %RATE_MATCH_NONE.
 	 */
 	int (*get_rate_matching)(struct phy_device *phydev,
-- 
GitLab


From 9c4d7f45d60745a1cea0e841fa5e3444c398d2f1 Mon Sep 17 00:00:00 2001
From: Po-Hsu Lin <po-hsu.lin@canonical.com>
Date: Fri, 30 Dec 2022 17:18:28 +0800
Subject: [PATCH 840/875] selftests: net: fix cleanup_v6() for
 arp_ndisc_evict_nocarrier

The cleanup_v6() will cause the arp_ndisc_evict_nocarrier script exit
with 255 (No such file or directory), even the tests are good:

 # selftests: net: arp_ndisc_evict_nocarrier.sh
 # run arp_evict_nocarrier=1 test
 # RTNETLINK answers: File exists
 # ok
 # run arp_evict_nocarrier=0 test
 # RTNETLINK answers: File exists
 # ok
 # run all.arp_evict_nocarrier=0 test
 # RTNETLINK answers: File exists
 # ok
 # run ndisc_evict_nocarrier=1 test
 # ok
 # run ndisc_evict_nocarrier=0 test
 # ok
 # run all.ndisc_evict_nocarrier=0 test
 # ok
 not ok 1 selftests: net: arp_ndisc_evict_nocarrier.sh # exit=255

This is because it's trying to modify the parameter for ipv4 instead.

Also, tests for ipv6 (run_ndisc_evict_nocarrier_enabled() and
run_ndisc_evict_nocarrier_disabled() are working on veth1, reflect
this fact in cleanup_v6().

Fixes: f86ca07eb531 ("selftests: net: add arp_ndisc_evict_nocarrier")
Signed-off-by: Po-Hsu Lin <po-hsu.lin@canonical.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 tools/testing/selftests/net/arp_ndisc_evict_nocarrier.sh | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/testing/selftests/net/arp_ndisc_evict_nocarrier.sh b/tools/testing/selftests/net/arp_ndisc_evict_nocarrier.sh
index b5af08af85595..b4ec1eeee6c90 100755
--- a/tools/testing/selftests/net/arp_ndisc_evict_nocarrier.sh
+++ b/tools/testing/selftests/net/arp_ndisc_evict_nocarrier.sh
@@ -24,8 +24,8 @@ cleanup_v6()
     ip netns del me
     ip netns del peer
 
-    sysctl -w net.ipv4.conf.veth0.ndisc_evict_nocarrier=1 >/dev/null 2>&1
-    sysctl -w net.ipv4.conf.all.ndisc_evict_nocarrier=1 >/dev/null 2>&1
+    sysctl -w net.ipv6.conf.veth1.ndisc_evict_nocarrier=1 >/dev/null 2>&1
+    sysctl -w net.ipv6.conf.all.ndisc_evict_nocarrier=1 >/dev/null 2>&1
 }
 
 create_ns()
-- 
GitLab


From 1856628baa17032531916984808d1bdfd62700d4 Mon Sep 17 00:00:00 2001
From: Po-Hsu Lin <po-hsu.lin@canonical.com>
Date: Fri, 30 Dec 2022 17:18:29 +0800
Subject: [PATCH 841/875] selftests: net: return non-zero for failures reported
 in arp_ndisc_evict_nocarrier

Return non-zero return value if there is any failure reported in this
script during the test. Otherwise it can only reflect the status of
the last command.

Fixes: f86ca07eb531 ("selftests: net: add arp_ndisc_evict_nocarrier")
Signed-off-by: Po-Hsu Lin <po-hsu.lin@canonical.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 .../selftests/net/arp_ndisc_evict_nocarrier.sh        | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/tools/testing/selftests/net/arp_ndisc_evict_nocarrier.sh b/tools/testing/selftests/net/arp_ndisc_evict_nocarrier.sh
index b4ec1eeee6c90..4a110bb01e53e 100755
--- a/tools/testing/selftests/net/arp_ndisc_evict_nocarrier.sh
+++ b/tools/testing/selftests/net/arp_ndisc_evict_nocarrier.sh
@@ -18,6 +18,7 @@ readonly V4_ADDR1=10.0.10.2
 readonly V6_ADDR0=2001:db8:91::1
 readonly V6_ADDR1=2001:db8:91::2
 nsid=100
+ret=0
 
 cleanup_v6()
 {
@@ -61,7 +62,7 @@ setup_v6() {
     if [ $? -ne 0 ]; then
         cleanup_v6
         echo "failed"
-        exit
+        exit 1
     fi
 
     # Set veth2 down, which will put veth1 in NOCARRIER state
@@ -88,7 +89,7 @@ setup_v4() {
     if [ $? -ne 0 ]; then
         cleanup_v4
         echo "failed"
-        exit
+        exit 1
     fi
 
     # Set veth1 down, which will put veth0 in NOCARRIER state
@@ -115,6 +116,7 @@ run_arp_evict_nocarrier_enabled() {
 
     if [ $? -eq 0 ];then
         echo "failed"
+        ret=1
     else
         echo "ok"
     fi
@@ -134,6 +136,7 @@ run_arp_evict_nocarrier_disabled() {
         echo "ok"
     else
         echo "failed"
+        ret=1
     fi
 
     cleanup_v4
@@ -164,6 +167,7 @@ run_ndisc_evict_nocarrier_enabled() {
 
     if [ $? -eq 0 ];then
         echo "failed"
+        ret=1
     else
         echo "ok"
     fi
@@ -182,6 +186,7 @@ run_ndisc_evict_nocarrier_disabled() {
         echo "ok"
     else
         echo "failed"
+        ret=1
     fi
 
     cleanup_v6
@@ -198,6 +203,7 @@ run_ndisc_evict_nocarrier_disabled_all() {
         echo "ok"
     else
         echo "failed"
+        ret=1
     fi
 
     cleanup_v6
@@ -218,3 +224,4 @@ if [ "$(id -u)" -ne 0 ];then
 fi
 
 run_all_tests
+exit $ret
-- 
GitLab


From d9d71a89f28d27ac772c429b37d52668d011df7a Mon Sep 17 00:00:00 2001
From: Alex Elder <elder@linaro.org>
Date: Fri, 30 Dec 2022 16:33:04 -0600
Subject: [PATCH 842/875] net: ipa: use proper endpoint mask for suspend

It is now possible for a system to have more than 32 endpoints.  As
a result, registers related to endpoint suspend are parameterized,
with 32 endpoints represented in one more registers.

In ipa_interrupt_suspend_control(), the IPA_SUSPEND_EN register
offset is determined properly, but the bit mask used still assumes
the number of enpoints won't exceed 32.  This is a bug.  Fix it.

Fixes: f298ba785e2d ("net: ipa: add a parameter to suspend registers")
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ipa/ipa_interrupt.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/net/ipa/ipa_interrupt.c b/drivers/net/ipa/ipa_interrupt.c
index a49f66efacb87..d458a35839cce 100644
--- a/drivers/net/ipa/ipa_interrupt.c
+++ b/drivers/net/ipa/ipa_interrupt.c
@@ -132,10 +132,10 @@ static void ipa_interrupt_suspend_control(struct ipa_interrupt *interrupt,
 					  u32 endpoint_id, bool enable)
 {
 	struct ipa *ipa = interrupt->ipa;
+	u32 mask = BIT(endpoint_id % 32);
 	u32 unit = endpoint_id / 32;
 	const struct ipa_reg *reg;
 	u32 offset;
-	u32 mask;
 	u32 val;
 
 	WARN_ON(!test_bit(endpoint_id, ipa->available));
@@ -148,7 +148,6 @@ static void ipa_interrupt_suspend_control(struct ipa_interrupt *interrupt,
 	offset = ipa_reg_n_offset(reg, unit);
 	val = ioread32(ipa->reg_virt + offset);
 
-	mask = BIT(endpoint_id);
 	if (enable)
 		val |= mask;
 	else
-- 
GitLab


From a3542b0ccd58f9fd42f34afa9daea435279a7c1c Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sat, 31 Dec 2022 16:05:46 -0600
Subject: [PATCH 843/875] dt-bindings: net: sun8i-emac: Add phy-supply property

This property has always been supported by the Linux driver; see
commit 9f93ac8d4085 ("net-next: stmmac: Add dwmac-sun8i"). In fact, the
original driver submission includes the phy-supply code but no mention
of it in the binding, so the omission appears to be accidental. In
addition, the property is documented in the binding for the previous
hardware generation, allwinner,sun7i-a20-gmac.

Document phy-supply in the binding to fix devicetree validation for the
25+ boards that already use this property.

Fixes: 0441bde003be ("dt-bindings: net-next: Add DT bindings documentation for Allwinner dwmac-sun8i")
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml     | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
index 1432fda3b603f..47bc2057e6292 100644
--- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
+++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
@@ -40,6 +40,9 @@ properties:
   clock-names:
     const: stmmaceth
 
+  phy-supply:
+    description: PHY regulator
+
   syscon:
     $ref: /schemas/types.yaml#/definitions/phandle
     description:
-- 
GitLab


From 91e2286160edd29d3fea8efff2dcda7df321878d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20Grzelak?= <mig@semihalf.com>
Date: Thu, 29 Dec 2022 15:22:19 +0100
Subject: [PATCH 844/875] dt-bindings: net: marvell,orion-mdio: Fix examples
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

As stated in marvell-orion-mdio.txt deleted in commit 0781434af811f
("dt-bindings: net: orion-mdio: Convert to JSON schema") if
'interrupts' property is present, width of 'reg' should be 0x84.
Otherwise, width of 'reg' should be 0x4. Fix 'examples:' and add
constraints checking whether 'interrupts' property is present
and validate it against fixed values in reg.

Signed-off-by: Michał Grzelak <mig@semihalf.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 .../bindings/net/marvell,orion-mdio.yaml      | 30 ++++++++++++++++---
 1 file changed, 26 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/marvell,orion-mdio.yaml b/Documentation/devicetree/bindings/net/marvell,orion-mdio.yaml
index d2906b4a0f595..e35da8b01dc25 100644
--- a/Documentation/devicetree/bindings/net/marvell,orion-mdio.yaml
+++ b/Documentation/devicetree/bindings/net/marvell,orion-mdio.yaml
@@ -16,9 +16,6 @@ description: |
   8k has a second unit which provides an interface with the xMDIO bus. This
   driver handles these interfaces.
 
-allOf:
-  - $ref: "mdio.yaml#"
-
 properties:
   compatible:
     enum:
@@ -39,13 +36,38 @@ required:
   - compatible
   - reg
 
+allOf:
+  - $ref: mdio.yaml#
+
+  - if:
+      required:
+        - interrupts
+
+    then:
+      properties:
+        reg:
+          items:
+            - items:
+                - $ref: /schemas/types.yaml#/definitions/cell
+                - const: 0x84
+
+    else:
+      properties:
+        reg:
+          items:
+            - items:
+                - $ref: /schemas/types.yaml#/definitions/cell
+                - enum:
+                    - 0x4
+                    - 0x10
+
 unevaluatedProperties: false
 
 examples:
   - |
     mdio@d0072004 {
       compatible = "marvell,orion-mdio";
-      reg = <0xd0072004 0x4>;
+      reg = <0xd0072004 0x84>;
       #address-cells = <1>;
       #size-cells = <0>;
       interrupts = <30>;
-- 
GitLab


From 88603b6dc419445847923fcb7fe5080067a30f98 Mon Sep 17 00:00:00 2001
From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sun, 1 Jan 2023 13:53:16 -0800
Subject: [PATCH 845/875] Linux 6.2-rc2

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index a5133e422f69b..c05b4fb7121e5 100644
--- a/Makefile
+++ b/Makefile
@@ -2,7 +2,7 @@
 VERSION = 6
 PATCHLEVEL = 2
 SUBLEVEL = 0
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
 NAME = Hurr durr I'ma ninja sloth
 
 # *DOCUMENTATION*
-- 
GitLab


From 694175cd8a1643cde3acb45c9294bca44a8e08e9 Mon Sep 17 00:00:00 2001
From: Miaoqian Lin <linmq006@gmail.com>
Date: Mon, 2 Jan 2023 12:20:39 +0400
Subject: [PATCH 846/875] gpio: sifive: Fix refcount leak in sifive_gpio_probe

of_irq_find_parent() returns a node pointer with refcount incremented,
We should use of_node_put() on it when not needed anymore.
Add missing of_node_put() to avoid refcount leak.

Fixes: 96868dce644d ("gpio/sifive: Add GPIO driver for SiFive SoCs")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
 drivers/gpio/gpio-sifive.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpio/gpio-sifive.c b/drivers/gpio/gpio-sifive.c
index 238f3210970cf..bc5660f61c570 100644
--- a/drivers/gpio/gpio-sifive.c
+++ b/drivers/gpio/gpio-sifive.c
@@ -215,6 +215,7 @@ static int sifive_gpio_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 	parent = irq_find_host(irq_parent);
+	of_node_put(irq_parent);
 	if (!parent) {
 		dev_err(dev, "no IRQ parent domain\n");
 		return -ENODEV;
-- 
GitLab


From a2965c7be0522eaa18808684b7b82b248515511b Mon Sep 17 00:00:00 2001
From: Jamal Hadi Salim <jhs@mojatatu.com>
Date: Sun, 1 Jan 2023 16:57:43 -0500
Subject: [PATCH 847/875] net: sched: atm: dont intepret cls results when asked
 to drop

If asked to drop a packet via TC_ACT_SHOT it is unsafe to assume
res.class contains a valid pointer
Fixes: b0188d4dbe5f ("[NET_SCHED]: sch_atm: Lindent")

Signed-off-by: Jamal Hadi Salim <jhs@mojatatu.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/sched/sch_atm.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/net/sched/sch_atm.c b/net/sched/sch_atm.c
index f52255fea652b..4a981ca90b0bf 100644
--- a/net/sched/sch_atm.c
+++ b/net/sched/sch_atm.c
@@ -393,10 +393,13 @@ static int atm_tc_enqueue(struct sk_buff *skb, struct Qdisc *sch,
 				result = tcf_classify(skb, NULL, fl, &res, true);
 				if (result < 0)
 					continue;
+				if (result == TC_ACT_SHOT)
+					goto done;
+
 				flow = (struct atm_flow_data *)res.class;
 				if (!flow)
 					flow = lookup_flow(sch, res.classid);
-				goto done;
+				goto drop;
 			}
 		}
 		flow = NULL;
-- 
GitLab


From caa4b35b4317d5147b3ab0fbdc9c075c7d2e9c12 Mon Sep 17 00:00:00 2001
From: Jamal Hadi Salim <jhs@mojatatu.com>
Date: Sun, 1 Jan 2023 16:57:44 -0500
Subject: [PATCH 848/875] net: sched: cbq: dont intepret cls results when asked
 to drop

If asked to drop a packet via TC_ACT_SHOT it is unsafe to assume that
res.class contains a valid pointer

Sample splat reported by Kyle Zeng

[    5.405624] 0: reclassify loop, rule prio 0, protocol 800
[    5.406326] ==================================================================
[    5.407240] BUG: KASAN: slab-out-of-bounds in cbq_enqueue+0x54b/0xea0
[    5.407987] Read of size 1 at addr ffff88800e3122aa by task poc/299
[    5.408731]
[    5.408897] CPU: 0 PID: 299 Comm: poc Not tainted 5.10.155+ #15
[    5.409516] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996),
BIOS 1.15.0-1 04/01/2014
[    5.410439] Call Trace:
[    5.410764]  dump_stack+0x87/0xcd
[    5.411153]  print_address_description+0x7a/0x6b0
[    5.411687]  ? vprintk_func+0xb9/0xc0
[    5.411905]  ? printk+0x76/0x96
[    5.412110]  ? cbq_enqueue+0x54b/0xea0
[    5.412323]  kasan_report+0x17d/0x220
[    5.412591]  ? cbq_enqueue+0x54b/0xea0
[    5.412803]  __asan_report_load1_noabort+0x10/0x20
[    5.413119]  cbq_enqueue+0x54b/0xea0
[    5.413400]  ? __kasan_check_write+0x10/0x20
[    5.413679]  __dev_queue_xmit+0x9c0/0x1db0
[    5.413922]  dev_queue_xmit+0xc/0x10
[    5.414136]  ip_finish_output2+0x8bc/0xcd0
[    5.414436]  __ip_finish_output+0x472/0x7a0
[    5.414692]  ip_finish_output+0x5c/0x190
[    5.414940]  ip_output+0x2d8/0x3c0
[    5.415150]  ? ip_mc_finish_output+0x320/0x320
[    5.415429]  __ip_queue_xmit+0x753/0x1760
[    5.415664]  ip_queue_xmit+0x47/0x60
[    5.415874]  __tcp_transmit_skb+0x1ef9/0x34c0
[    5.416129]  tcp_connect+0x1f5e/0x4cb0
[    5.416347]  tcp_v4_connect+0xc8d/0x18c0
[    5.416577]  __inet_stream_connect+0x1ae/0xb40
[    5.416836]  ? local_bh_enable+0x11/0x20
[    5.417066]  ? lock_sock_nested+0x175/0x1d0
[    5.417309]  inet_stream_connect+0x5d/0x90
[    5.417548]  ? __inet_stream_connect+0xb40/0xb40
[    5.417817]  __sys_connect+0x260/0x2b0
[    5.418037]  __x64_sys_connect+0x76/0x80
[    5.418267]  do_syscall_64+0x31/0x50
[    5.418477]  entry_SYSCALL_64_after_hwframe+0x61/0xc6
[    5.418770] RIP: 0033:0x473bb7
[    5.418952] Code: 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00
00 00 90 f3 0f 1e fa 64 8b 04 25 18 00 00 00 85 c0 75 10 b8 2a 00 00
00 0f 05 <48> 3d 00 f0 ff ff 77 51 c3 48 83 ec 18 89 54 24 0c 48 89 34
24 89
[    5.420046] RSP: 002b:00007fffd20eb0f8 EFLAGS: 00000246 ORIG_RAX:
000000000000002a
[    5.420472] RAX: ffffffffffffffda RBX: 00007fffd20eb578 RCX: 0000000000473bb7
[    5.420872] RDX: 0000000000000010 RSI: 00007fffd20eb110 RDI: 0000000000000007
[    5.421271] RBP: 00007fffd20eb150 R08: 0000000000000001 R09: 0000000000000004
[    5.421671] R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000001
[    5.422071] R13: 00007fffd20eb568 R14: 00000000004fc740 R15: 0000000000000002
[    5.422471]
[    5.422562] Allocated by task 299:
[    5.422782]  __kasan_kmalloc+0x12d/0x160
[    5.423007]  kasan_kmalloc+0x5/0x10
[    5.423208]  kmem_cache_alloc_trace+0x201/0x2e0
[    5.423492]  tcf_proto_create+0x65/0x290
[    5.423721]  tc_new_tfilter+0x137e/0x1830
[    5.423957]  rtnetlink_rcv_msg+0x730/0x9f0
[    5.424197]  netlink_rcv_skb+0x166/0x300
[    5.424428]  rtnetlink_rcv+0x11/0x20
[    5.424639]  netlink_unicast+0x673/0x860
[    5.424870]  netlink_sendmsg+0x6af/0x9f0
[    5.425100]  __sys_sendto+0x58d/0x5a0
[    5.425315]  __x64_sys_sendto+0xda/0xf0
[    5.425539]  do_syscall_64+0x31/0x50
[    5.425764]  entry_SYSCALL_64_after_hwframe+0x61/0xc6
[    5.426065]
[    5.426157] The buggy address belongs to the object at ffff88800e312200
[    5.426157]  which belongs to the cache kmalloc-128 of size 128
[    5.426955] The buggy address is located 42 bytes to the right of
[    5.426955]  128-byte region [ffff88800e312200, ffff88800e312280)
[    5.427688] The buggy address belongs to the page:
[    5.427992] page:000000009875fabc refcount:1 mapcount:0
mapping:0000000000000000 index:0x0 pfn:0xe312
[    5.428562] flags: 0x100000000000200(slab)
[    5.428812] raw: 0100000000000200 dead000000000100 dead000000000122
ffff888007843680
[    5.429325] raw: 0000000000000000 0000000000100010 00000001ffffffff
ffff88800e312401
[    5.429875] page dumped because: kasan: bad access detected
[    5.430214] page->mem_cgroup:ffff88800e312401
[    5.430471]
[    5.430564] Memory state around the buggy address:
[    5.430846]  ffff88800e312180: fc fc fc fc fc fc fc fc fc fc fc fc
fc fc fc fc
[    5.431267]  ffff88800e312200: 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 fc
[    5.431705] >ffff88800e312280: fc fc fc fc fc fc fc fc fc fc fc fc
fc fc fc fc
[    5.432123]                                   ^
[    5.432391]  ffff88800e312300: 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 fc
[    5.432810]  ffff88800e312380: fc fc fc fc fc fc fc fc fc fc fc fc
fc fc fc fc
[    5.433229] ==================================================================
[    5.433648] Disabling lock debugging due to kernel taint

Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
Reported-by: Kyle Zeng <zengyhkyle@gmail.com>
Signed-off-by: Jamal Hadi Salim <jhs@mojatatu.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/sched/sch_cbq.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/net/sched/sch_cbq.c b/net/sched/sch_cbq.c
index 6568e17c4c634..36db5f6782f2c 100644
--- a/net/sched/sch_cbq.c
+++ b/net/sched/sch_cbq.c
@@ -230,6 +230,8 @@ cbq_classify(struct sk_buff *skb, struct Qdisc *sch, int *qerr)
 		result = tcf_classify(skb, NULL, fl, &res, true);
 		if (!fl || result < 0)
 			goto fallback;
+		if (result == TC_ACT_SHOT)
+			return NULL;
 
 		cl = (void *)res.class;
 		if (!cl) {
@@ -250,8 +252,6 @@ cbq_classify(struct sk_buff *skb, struct Qdisc *sch, int *qerr)
 		case TC_ACT_TRAP:
 			*qerr = NET_XMIT_SUCCESS | __NET_XMIT_STOLEN;
 			fallthrough;
-		case TC_ACT_SHOT:
-			return NULL;
 		case TC_ACT_RECLASSIFY:
 			return cbq_reclassify(skb, cl);
 		}
-- 
GitLab


From 43d253781f6321c6a07a5fe4ee72103a679a5f6b Mon Sep 17 00:00:00 2001
From: Randy Dunlap <rdunlap@infradead.org>
Date: Sun, 1 Jan 2023 23:17:37 -0800
Subject: [PATCH 849/875] net: sched: htb: fix htb_classify() kernel-doc

Fix W=1 kernel-doc warning:

net/sched/sch_htb.c:214: warning: expecting prototype for htb_classify(). Prototype was for HTB_DIRECT() instead

by moving the HTB_DIRECT() macro above the function.
Add kernel-doc notation for function parameters as well.

Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Jamal Hadi Salim <jhs@mojatatu.com>
Cc: Cong Wang <xiyou.wangcong@gmail.com>
Cc: Jiri Pirko <jiri@resnulli.us>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Eric Dumazet <edumazet@google.com>
Cc: Jakub Kicinski <kuba@kernel.org>
Cc: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 net/sched/sch_htb.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/net/sched/sch_htb.c b/net/sched/sch_htb.c
index e5b4bbf3ce3d5..2238edece1a46 100644
--- a/net/sched/sch_htb.c
+++ b/net/sched/sch_htb.c
@@ -199,8 +199,14 @@ static unsigned long htb_search(struct Qdisc *sch, u32 handle)
 {
 	return (unsigned long)htb_find(handle, sch);
 }
+
+#define HTB_DIRECT ((struct htb_class *)-1L)
+
 /**
  * htb_classify - classify a packet into class
+ * @skb: the socket buffer
+ * @sch: the active queue discipline
+ * @qerr: pointer for returned status code
  *
  * It returns NULL if the packet should be dropped or -1 if the packet
  * should be passed directly thru. In all other cases leaf class is returned.
@@ -211,8 +217,6 @@ static unsigned long htb_search(struct Qdisc *sch, u32 handle)
  * have no valid leaf we try to use MAJOR:default leaf. It still unsuccessful
  * then finish and return direct queue.
  */
-#define HTB_DIRECT ((struct htb_class *)-1L)
-
 static struct htb_class *htb_classify(struct sk_buff *skb, struct Qdisc *sch,
 				      int *qerr)
 {
-- 
GitLab


From 06bf62944144a92d83dd14fd1378d2a288259561 Mon Sep 17 00:00:00 2001
From: Ido Schimmel <idosch@nvidia.com>
Date: Mon, 2 Jan 2023 08:55:56 +0200
Subject: [PATCH 850/875] vxlan: Fix memory leaks in error path

The memory allocated by vxlan_vnigroup_init() is not freed in the error
path, leading to memory leaks [1]. Fix by calling
vxlan_vnigroup_uninit() in the error path.

The leaks can be reproduced by annotating gro_cells_init() with
ALLOW_ERROR_INJECTION() and then running:

 # echo "100" > /sys/kernel/debug/fail_function/probability
 # echo "1" > /sys/kernel/debug/fail_function/times
 # echo "gro_cells_init" > /sys/kernel/debug/fail_function/inject
 # printf %#x -12 > /sys/kernel/debug/fail_function/gro_cells_init/retval
 # ip link add name vxlan0 type vxlan dstport 4789 external vnifilter
 RTNETLINK answers: Cannot allocate memory

[1]
unreferenced object 0xffff88810db84a00 (size 512):
  comm "ip", pid 330, jiffies 4295010045 (age 66.016s)
  hex dump (first 32 bytes):
    f8 d5 76 0e 81 88 ff ff 01 00 00 00 00 00 00 02  ..v.............
    03 00 04 00 48 00 00 00 00 00 00 01 04 00 01 00  ....H...........
  backtrace:
    [<ffffffff81a3097a>] kmalloc_trace+0x2a/0x60
    [<ffffffff82f049fc>] vxlan_vnigroup_init+0x4c/0x160
    [<ffffffff82ecd69e>] vxlan_init+0x1ae/0x280
    [<ffffffff836858ca>] register_netdevice+0x57a/0x16d0
    [<ffffffff82ef67b7>] __vxlan_dev_create+0x7c7/0xa50
    [<ffffffff82ef6ce6>] vxlan_newlink+0xd6/0x130
    [<ffffffff836d02ab>] __rtnl_newlink+0x112b/0x18a0
    [<ffffffff836d0a8c>] rtnl_newlink+0x6c/0xa0
    [<ffffffff836c0ddf>] rtnetlink_rcv_msg+0x43f/0xd40
    [<ffffffff83908ce0>] netlink_rcv_skb+0x170/0x440
    [<ffffffff839066af>] netlink_unicast+0x53f/0x810
    [<ffffffff839072d8>] netlink_sendmsg+0x958/0xe70
    [<ffffffff835c319f>] ____sys_sendmsg+0x78f/0xa90
    [<ffffffff835cd6da>] ___sys_sendmsg+0x13a/0x1e0
    [<ffffffff835cd94c>] __sys_sendmsg+0x11c/0x1f0
    [<ffffffff8424da78>] do_syscall_64+0x38/0x80
unreferenced object 0xffff88810e76d5f8 (size 192):
  comm "ip", pid 330, jiffies 4295010045 (age 66.016s)
  hex dump (first 32 bytes):
    04 00 00 00 00 00 00 00 db e1 4f e7 00 00 00 00  ..........O.....
    08 d6 76 0e 81 88 ff ff 08 d6 76 0e 81 88 ff ff  ..v.......v.....
  backtrace:
    [<ffffffff81a3162e>] __kmalloc_node+0x4e/0x90
    [<ffffffff81a0e166>] kvmalloc_node+0xa6/0x1f0
    [<ffffffff8276e1a3>] bucket_table_alloc.isra.0+0x83/0x460
    [<ffffffff8276f18b>] rhashtable_init+0x43b/0x7c0
    [<ffffffff82f04a1c>] vxlan_vnigroup_init+0x6c/0x160
    [<ffffffff82ecd69e>] vxlan_init+0x1ae/0x280
    [<ffffffff836858ca>] register_netdevice+0x57a/0x16d0
    [<ffffffff82ef67b7>] __vxlan_dev_create+0x7c7/0xa50
    [<ffffffff82ef6ce6>] vxlan_newlink+0xd6/0x130
    [<ffffffff836d02ab>] __rtnl_newlink+0x112b/0x18a0
    [<ffffffff836d0a8c>] rtnl_newlink+0x6c/0xa0
    [<ffffffff836c0ddf>] rtnetlink_rcv_msg+0x43f/0xd40
    [<ffffffff83908ce0>] netlink_rcv_skb+0x170/0x440
    [<ffffffff839066af>] netlink_unicast+0x53f/0x810
    [<ffffffff839072d8>] netlink_sendmsg+0x958/0xe70
    [<ffffffff835c319f>] ____sys_sendmsg+0x78f/0xa90

Fixes: f9c4bb0b245c ("vxlan: vni filtering support on collect metadata device")
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Reviewed-by: Nikolay Aleksandrov <razor@blackwall.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/vxlan/vxlan_core.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/net/vxlan/vxlan_core.c b/drivers/net/vxlan/vxlan_core.c
index 92224b36787a8..b1b179effe2a1 100644
--- a/drivers/net/vxlan/vxlan_core.c
+++ b/drivers/net/vxlan/vxlan_core.c
@@ -2917,16 +2917,23 @@ static int vxlan_init(struct net_device *dev)
 		vxlan_vnigroup_init(vxlan);
 
 	dev->tstats = netdev_alloc_pcpu_stats(struct pcpu_sw_netstats);
-	if (!dev->tstats)
-		return -ENOMEM;
+	if (!dev->tstats) {
+		err = -ENOMEM;
+		goto err_vnigroup_uninit;
+	}
 
 	err = gro_cells_init(&vxlan->gro_cells, dev);
-	if (err) {
-		free_percpu(dev->tstats);
-		return err;
-	}
+	if (err)
+		goto err_free_percpu;
 
 	return 0;
+
+err_free_percpu:
+	free_percpu(dev->tstats);
+err_vnigroup_uninit:
+	if (vxlan->cfg.flags & VXLAN_F_VNIFILTER)
+		vxlan_vnigroup_uninit(vxlan);
+	return err;
 }
 
 static void vxlan_fdb_delete_default(struct vxlan_dev *vxlan, __be32 vni)
-- 
GitLab


From 588ab2dc25f60efeb516b4abedb6c551949cc185 Mon Sep 17 00:00:00 2001
From: Horatiu Vultur <horatiu.vultur@microchip.com>
Date: Mon, 2 Jan 2023 13:12:15 +0100
Subject: [PATCH 851/875] net: sparx5: Fix reading of the MAC address

There is an issue with the checking of the return value of
'of_get_mac_address', which returns 0 on success and negative value on
failure. The driver interpretated the result the opposite way. Therefore
if there was a MAC address defined in the DT, then the driver was
generating a random MAC address otherwise it would use address 0.
Fix this by checking correctly the return value of 'of_get_mac_address'

Fixes: b74ef9f9cb91 ("net: sparx5: Do not use mac_addr uninitialized in mchp_sparx5_probe()")
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
index d25f4f09faa06..3c5d4fe993737 100644
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
@@ -834,7 +834,7 @@ static int mchp_sparx5_probe(struct platform_device *pdev)
 	if (err)
 		goto cleanup_config;
 
-	if (!of_get_mac_address(np, sparx5->base_mac)) {
+	if (of_get_mac_address(np, sparx5->base_mac)) {
 		dev_info(sparx5->dev, "MAC addr was not set, use random MAC\n");
 		eth_random_addr(sparx5->base_mac);
 		sparx5->base_mac[5] = 0;
-- 
GitLab


From a31d47be64b9b74f8cfedffe03e0a8a1f9e51f23 Mon Sep 17 00:00:00 2001
From: Jozsef Kadlecsik <kadlec@netfilter.org>
Date: Fri, 30 Dec 2022 13:24:37 +0100
Subject: [PATCH 852/875] netfilter: ipset: fix hash:net,port,net hang with /0
 subnet
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The hash:net,port,net set type supports /0 subnets. However, the patch
commit 5f7b51bf09baca8e titled "netfilter: ipset: Limit the maximal range
of consecutive elements to add/delete" did not take into account it and
resulted in an endless loop. The bug is actually older but the patch
5f7b51bf09baca8e brings it out earlier.

Handle /0 subnets properly in hash:net,port,net set types.

Fixes: 5f7b51bf09ba ("netfilter: ipset: Limit the maximal range of consecutive elements to add/delete")
Reported-by: Марк Коренберг <socketpair@gmail.com>
Signed-off-by: Jozsef Kadlecsik <kadlec@netfilter.org>
Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
---
 net/netfilter/ipset/ip_set_hash_netportnet.c | 40 ++++++++++----------
 1 file changed, 21 insertions(+), 19 deletions(-)

diff --git a/net/netfilter/ipset/ip_set_hash_netportnet.c b/net/netfilter/ipset/ip_set_hash_netportnet.c
index 19bcdb3141f6e..005a7ce87217e 100644
--- a/net/netfilter/ipset/ip_set_hash_netportnet.c
+++ b/net/netfilter/ipset/ip_set_hash_netportnet.c
@@ -173,17 +173,26 @@ hash_netportnet4_kadt(struct ip_set *set, const struct sk_buff *skb,
 	return adtfn(set, &e, &ext, &opt->ext, opt->cmdflags);
 }
 
+static u32
+hash_netportnet4_range_to_cidr(u32 from, u32 to, u8 *cidr)
+{
+	if (from == 0 && to == UINT_MAX) {
+		*cidr = 0;
+		return to;
+	}
+	return ip_set_range_to_cidr(from, to, cidr);
+}
+
 static int
 hash_netportnet4_uadt(struct ip_set *set, struct nlattr *tb[],
 		      enum ipset_adt adt, u32 *lineno, u32 flags, bool retried)
 {
-	const struct hash_netportnet4 *h = set->data;
+	struct hash_netportnet4 *h = set->data;
 	ipset_adtfn adtfn = set->variant->adt[adt];
 	struct hash_netportnet4_elem e = { };
 	struct ip_set_ext ext = IP_SET_INIT_UEXT(set);
 	u32 ip = 0, ip_to = 0, p = 0, port, port_to;
-	u32 ip2_from = 0, ip2_to = 0, ip2, ipn;
-	u64 n = 0, m = 0;
+	u32 ip2_from = 0, ip2_to = 0, ip2, i = 0;
 	bool with_ports = false;
 	int ret;
 
@@ -285,19 +294,6 @@ hash_netportnet4_uadt(struct ip_set *set, struct nlattr *tb[],
 	} else {
 		ip_set_mask_from_to(ip2_from, ip2_to, e.cidr[1]);
 	}
-	ipn = ip;
-	do {
-		ipn = ip_set_range_to_cidr(ipn, ip_to, &e.cidr[0]);
-		n++;
-	} while (ipn++ < ip_to);
-	ipn = ip2_from;
-	do {
-		ipn = ip_set_range_to_cidr(ipn, ip2_to, &e.cidr[1]);
-		m++;
-	} while (ipn++ < ip2_to);
-
-	if (n*m*(port_to - port + 1) > IPSET_MAX_RANGE)
-		return -ERANGE;
 
 	if (retried) {
 		ip = ntohl(h->next.ip[0]);
@@ -310,13 +306,19 @@ hash_netportnet4_uadt(struct ip_set *set, struct nlattr *tb[],
 
 	do {
 		e.ip[0] = htonl(ip);
-		ip = ip_set_range_to_cidr(ip, ip_to, &e.cidr[0]);
+		ip = hash_netportnet4_range_to_cidr(ip, ip_to, &e.cidr[0]);
 		for (; p <= port_to; p++) {
 			e.port = htons(p);
 			do {
+				i++;
 				e.ip[1] = htonl(ip2);
-				ip2 = ip_set_range_to_cidr(ip2, ip2_to,
-							   &e.cidr[1]);
+				if (i > IPSET_MAX_RANGE) {
+					hash_netportnet4_data_next(&h->next,
+								   &e);
+					return -ERANGE;
+				}
+				ip2 = hash_netportnet4_range_to_cidr(ip2,
+							ip2_to, &e.cidr[1]);
 				ret = adtfn(set, &e, &ext, &ext, flags);
 				if (ret && !ip_set_eexist(ret, flags))
 					return ret;
-- 
GitLab


From 5e29dc36bd5e2166b834ceb19990d9e68a734d7d Mon Sep 17 00:00:00 2001
From: Jozsef Kadlecsik <kadlec@netfilter.org>
Date: Fri, 30 Dec 2022 13:24:38 +0100
Subject: [PATCH 853/875] netfilter: ipset: Rework long task execution when
 adding/deleting entries

When adding/deleting large number of elements in one step in ipset, it can
take a reasonable amount of time and can result in soft lockup errors. The
patch 5f7b51bf09ba ("netfilter: ipset: Limit the maximal range of
consecutive elements to add/delete") tried to fix it by limiting the max
elements to process at all. However it was not enough, it is still possible
that we get hung tasks. Lowering the limit is not reasonable, so the
approach in this patch is as follows: rely on the method used at resizing
sets and save the state when we reach a smaller internal batch limit,
unlock/lock and proceed from the saved state. Thus we can avoid long
continuous tasks and at the same time removed the limit to add/delete large
number of elements in one step.

The nfnl mutex is held during the whole operation which prevents one to
issue other ipset commands in parallel.

Fixes: 5f7b51bf09ba ("netfilter: ipset: Limit the maximal range of consecutive elements to add/delete")
Reported-by: syzbot+9204e7399656300bf271@syzkaller.appspotmail.com
Signed-off-by: Jozsef Kadlecsik <kadlec@netfilter.org>
Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
---
 include/linux/netfilter/ipset/ip_set.h      |  2 +-
 net/netfilter/ipset/ip_set_core.c           |  7 ++++---
 net/netfilter/ipset/ip_set_hash_ip.c        | 14 ++++++-------
 net/netfilter/ipset/ip_set_hash_ipmark.c    | 13 ++++++------
 net/netfilter/ipset/ip_set_hash_ipport.c    | 13 ++++++------
 net/netfilter/ipset/ip_set_hash_ipportip.c  | 13 ++++++------
 net/netfilter/ipset/ip_set_hash_ipportnet.c | 13 +++++++-----
 net/netfilter/ipset/ip_set_hash_net.c       | 17 +++++++--------
 net/netfilter/ipset/ip_set_hash_netiface.c  | 15 ++++++--------
 net/netfilter/ipset/ip_set_hash_netnet.c    | 23 +++++++--------------
 net/netfilter/ipset/ip_set_hash_netport.c   | 19 +++++++----------
 11 files changed, 68 insertions(+), 81 deletions(-)

diff --git a/include/linux/netfilter/ipset/ip_set.h b/include/linux/netfilter/ipset/ip_set.h
index ab934ad951a87..e8c350a3ade15 100644
--- a/include/linux/netfilter/ipset/ip_set.h
+++ b/include/linux/netfilter/ipset/ip_set.h
@@ -197,7 +197,7 @@ struct ip_set_region {
 };
 
 /* Max range where every element is added/deleted in one step */
-#define IPSET_MAX_RANGE		(1<<20)
+#define IPSET_MAX_RANGE		(1<<14)
 
 /* The max revision number supported by any set type + 1 */
 #define IPSET_REVISION_MAX	9
diff --git a/net/netfilter/ipset/ip_set_core.c b/net/netfilter/ipset/ip_set_core.c
index e7ba5b6dd2b7c..46ebee9400dab 100644
--- a/net/netfilter/ipset/ip_set_core.c
+++ b/net/netfilter/ipset/ip_set_core.c
@@ -1698,9 +1698,10 @@ call_ad(struct net *net, struct sock *ctnl, struct sk_buff *skb,
 		ret = set->variant->uadt(set, tb, adt, &lineno, flags, retried);
 		ip_set_unlock(set);
 		retried = true;
-	} while (ret == -EAGAIN &&
-		 set->variant->resize &&
-		 (ret = set->variant->resize(set, retried)) == 0);
+	} while (ret == -ERANGE ||
+		 (ret == -EAGAIN &&
+		  set->variant->resize &&
+		  (ret = set->variant->resize(set, retried)) == 0));
 
 	if (!ret || (ret == -IPSET_ERR_EXIST && eexist))
 		return 0;
diff --git a/net/netfilter/ipset/ip_set_hash_ip.c b/net/netfilter/ipset/ip_set_hash_ip.c
index e30513cefd90e..c9f4e38596632 100644
--- a/net/netfilter/ipset/ip_set_hash_ip.c
+++ b/net/netfilter/ipset/ip_set_hash_ip.c
@@ -100,11 +100,11 @@ static int
 hash_ip4_uadt(struct ip_set *set, struct nlattr *tb[],
 	      enum ipset_adt adt, u32 *lineno, u32 flags, bool retried)
 {
-	const struct hash_ip4 *h = set->data;
+	struct hash_ip4 *h = set->data;
 	ipset_adtfn adtfn = set->variant->adt[adt];
 	struct hash_ip4_elem e = { 0 };
 	struct ip_set_ext ext = IP_SET_INIT_UEXT(set);
-	u32 ip = 0, ip_to = 0, hosts;
+	u32 ip = 0, ip_to = 0, hosts, i = 0;
 	int ret = 0;
 
 	if (tb[IPSET_ATTR_LINENO])
@@ -149,14 +149,14 @@ hash_ip4_uadt(struct ip_set *set, struct nlattr *tb[],
 
 	hosts = h->netmask == 32 ? 1 : 2 << (32 - h->netmask - 1);
 
-	/* 64bit division is not allowed on 32bit */
-	if (((u64)ip_to - ip + 1) >> (32 - h->netmask) > IPSET_MAX_RANGE)
-		return -ERANGE;
-
 	if (retried)
 		ip = ntohl(h->next.ip);
-	for (; ip <= ip_to;) {
+	for (; ip <= ip_to; i++) {
 		e.ip = htonl(ip);
+		if (i > IPSET_MAX_RANGE) {
+			hash_ip4_data_next(&h->next, &e);
+			return -ERANGE;
+		}
 		ret = adtfn(set, &e, &ext, &ext, flags);
 		if (ret && !ip_set_eexist(ret, flags))
 			return ret;
diff --git a/net/netfilter/ipset/ip_set_hash_ipmark.c b/net/netfilter/ipset/ip_set_hash_ipmark.c
index 153de3457423e..a22ec1a6f6ec8 100644
--- a/net/netfilter/ipset/ip_set_hash_ipmark.c
+++ b/net/netfilter/ipset/ip_set_hash_ipmark.c
@@ -97,11 +97,11 @@ static int
 hash_ipmark4_uadt(struct ip_set *set, struct nlattr *tb[],
 		  enum ipset_adt adt, u32 *lineno, u32 flags, bool retried)
 {
-	const struct hash_ipmark4 *h = set->data;
+	struct hash_ipmark4 *h = set->data;
 	ipset_adtfn adtfn = set->variant->adt[adt];
 	struct hash_ipmark4_elem e = { };
 	struct ip_set_ext ext = IP_SET_INIT_UEXT(set);
-	u32 ip, ip_to = 0;
+	u32 ip, ip_to = 0, i = 0;
 	int ret;
 
 	if (tb[IPSET_ATTR_LINENO])
@@ -148,13 +148,14 @@ hash_ipmark4_uadt(struct ip_set *set, struct nlattr *tb[],
 		ip_set_mask_from_to(ip, ip_to, cidr);
 	}
 
-	if (((u64)ip_to - ip + 1) > IPSET_MAX_RANGE)
-		return -ERANGE;
-
 	if (retried)
 		ip = ntohl(h->next.ip);
-	for (; ip <= ip_to; ip++) {
+	for (; ip <= ip_to; ip++, i++) {
 		e.ip = htonl(ip);
+		if (i > IPSET_MAX_RANGE) {
+			hash_ipmark4_data_next(&h->next, &e);
+			return -ERANGE;
+		}
 		ret = adtfn(set, &e, &ext, &ext, flags);
 
 		if (ret && !ip_set_eexist(ret, flags))
diff --git a/net/netfilter/ipset/ip_set_hash_ipport.c b/net/netfilter/ipset/ip_set_hash_ipport.c
index 2ffbd0b78a8c5..e977b5a9c48dc 100644
--- a/net/netfilter/ipset/ip_set_hash_ipport.c
+++ b/net/netfilter/ipset/ip_set_hash_ipport.c
@@ -112,11 +112,11 @@ static int
 hash_ipport4_uadt(struct ip_set *set, struct nlattr *tb[],
 		  enum ipset_adt adt, u32 *lineno, u32 flags, bool retried)
 {
-	const struct hash_ipport4 *h = set->data;
+	struct hash_ipport4 *h = set->data;
 	ipset_adtfn adtfn = set->variant->adt[adt];
 	struct hash_ipport4_elem e = { .ip = 0 };
 	struct ip_set_ext ext = IP_SET_INIT_UEXT(set);
-	u32 ip, ip_to = 0, p = 0, port, port_to;
+	u32 ip, ip_to = 0, p = 0, port, port_to, i = 0;
 	bool with_ports = false;
 	int ret;
 
@@ -184,17 +184,18 @@ hash_ipport4_uadt(struct ip_set *set, struct nlattr *tb[],
 			swap(port, port_to);
 	}
 
-	if (((u64)ip_to - ip + 1)*(port_to - port + 1) > IPSET_MAX_RANGE)
-		return -ERANGE;
-
 	if (retried)
 		ip = ntohl(h->next.ip);
 	for (; ip <= ip_to; ip++) {
 		p = retried && ip == ntohl(h->next.ip) ? ntohs(h->next.port)
 						       : port;
-		for (; p <= port_to; p++) {
+		for (; p <= port_to; p++, i++) {
 			e.ip = htonl(ip);
 			e.port = htons(p);
+			if (i > IPSET_MAX_RANGE) {
+				hash_ipport4_data_next(&h->next, &e);
+				return -ERANGE;
+			}
 			ret = adtfn(set, &e, &ext, &ext, flags);
 
 			if (ret && !ip_set_eexist(ret, flags))
diff --git a/net/netfilter/ipset/ip_set_hash_ipportip.c b/net/netfilter/ipset/ip_set_hash_ipportip.c
index 334fb1ad0e86c..39a01934b1536 100644
--- a/net/netfilter/ipset/ip_set_hash_ipportip.c
+++ b/net/netfilter/ipset/ip_set_hash_ipportip.c
@@ -108,11 +108,11 @@ static int
 hash_ipportip4_uadt(struct ip_set *set, struct nlattr *tb[],
 		    enum ipset_adt adt, u32 *lineno, u32 flags, bool retried)
 {
-	const struct hash_ipportip4 *h = set->data;
+	struct hash_ipportip4 *h = set->data;
 	ipset_adtfn adtfn = set->variant->adt[adt];
 	struct hash_ipportip4_elem e = { .ip = 0 };
 	struct ip_set_ext ext = IP_SET_INIT_UEXT(set);
-	u32 ip, ip_to = 0, p = 0, port, port_to;
+	u32 ip, ip_to = 0, p = 0, port, port_to, i = 0;
 	bool with_ports = false;
 	int ret;
 
@@ -180,17 +180,18 @@ hash_ipportip4_uadt(struct ip_set *set, struct nlattr *tb[],
 			swap(port, port_to);
 	}
 
-	if (((u64)ip_to - ip + 1)*(port_to - port + 1) > IPSET_MAX_RANGE)
-		return -ERANGE;
-
 	if (retried)
 		ip = ntohl(h->next.ip);
 	for (; ip <= ip_to; ip++) {
 		p = retried && ip == ntohl(h->next.ip) ? ntohs(h->next.port)
 						       : port;
-		for (; p <= port_to; p++) {
+		for (; p <= port_to; p++, i++) {
 			e.ip = htonl(ip);
 			e.port = htons(p);
+			if (i > IPSET_MAX_RANGE) {
+				hash_ipportip4_data_next(&h->next, &e);
+				return -ERANGE;
+			}
 			ret = adtfn(set, &e, &ext, &ext, flags);
 
 			if (ret && !ip_set_eexist(ret, flags))
diff --git a/net/netfilter/ipset/ip_set_hash_ipportnet.c b/net/netfilter/ipset/ip_set_hash_ipportnet.c
index 7df94f437f600..5c6de605a9fb7 100644
--- a/net/netfilter/ipset/ip_set_hash_ipportnet.c
+++ b/net/netfilter/ipset/ip_set_hash_ipportnet.c
@@ -160,12 +160,12 @@ static int
 hash_ipportnet4_uadt(struct ip_set *set, struct nlattr *tb[],
 		     enum ipset_adt adt, u32 *lineno, u32 flags, bool retried)
 {
-	const struct hash_ipportnet4 *h = set->data;
+	struct hash_ipportnet4 *h = set->data;
 	ipset_adtfn adtfn = set->variant->adt[adt];
 	struct hash_ipportnet4_elem e = { .cidr = HOST_MASK - 1 };
 	struct ip_set_ext ext = IP_SET_INIT_UEXT(set);
 	u32 ip = 0, ip_to = 0, p = 0, port, port_to;
-	u32 ip2_from = 0, ip2_to = 0, ip2;
+	u32 ip2_from = 0, ip2_to = 0, ip2, i = 0;
 	bool with_ports = false;
 	u8 cidr;
 	int ret;
@@ -253,9 +253,6 @@ hash_ipportnet4_uadt(struct ip_set *set, struct nlattr *tb[],
 			swap(port, port_to);
 	}
 
-	if (((u64)ip_to - ip + 1)*(port_to - port + 1) > IPSET_MAX_RANGE)
-		return -ERANGE;
-
 	ip2_to = ip2_from;
 	if (tb[IPSET_ATTR_IP2_TO]) {
 		ret = ip_set_get_hostipaddr4(tb[IPSET_ATTR_IP2_TO], &ip2_to);
@@ -282,9 +279,15 @@ hash_ipportnet4_uadt(struct ip_set *set, struct nlattr *tb[],
 		for (; p <= port_to; p++) {
 			e.port = htons(p);
 			do {
+				i++;
 				e.ip2 = htonl(ip2);
 				ip2 = ip_set_range_to_cidr(ip2, ip2_to, &cidr);
 				e.cidr = cidr - 1;
+				if (i > IPSET_MAX_RANGE) {
+					hash_ipportnet4_data_next(&h->next,
+								  &e);
+					return -ERANGE;
+				}
 				ret = adtfn(set, &e, &ext, &ext, flags);
 
 				if (ret && !ip_set_eexist(ret, flags))
diff --git a/net/netfilter/ipset/ip_set_hash_net.c b/net/netfilter/ipset/ip_set_hash_net.c
index 1422739d9aa25..ce0a9ce5a91f1 100644
--- a/net/netfilter/ipset/ip_set_hash_net.c
+++ b/net/netfilter/ipset/ip_set_hash_net.c
@@ -136,11 +136,11 @@ static int
 hash_net4_uadt(struct ip_set *set, struct nlattr *tb[],
 	       enum ipset_adt adt, u32 *lineno, u32 flags, bool retried)
 {
-	const struct hash_net4 *h = set->data;
+	struct hash_net4 *h = set->data;
 	ipset_adtfn adtfn = set->variant->adt[adt];
 	struct hash_net4_elem e = { .cidr = HOST_MASK };
 	struct ip_set_ext ext = IP_SET_INIT_UEXT(set);
-	u32 ip = 0, ip_to = 0, ipn, n = 0;
+	u32 ip = 0, ip_to = 0, i = 0;
 	int ret;
 
 	if (tb[IPSET_ATTR_LINENO])
@@ -188,19 +188,16 @@ hash_net4_uadt(struct ip_set *set, struct nlattr *tb[],
 		if (ip + UINT_MAX == ip_to)
 			return -IPSET_ERR_HASH_RANGE;
 	}
-	ipn = ip;
-	do {
-		ipn = ip_set_range_to_cidr(ipn, ip_to, &e.cidr);
-		n++;
-	} while (ipn++ < ip_to);
-
-	if (n > IPSET_MAX_RANGE)
-		return -ERANGE;
 
 	if (retried)
 		ip = ntohl(h->next.ip);
 	do {
+		i++;
 		e.ip = htonl(ip);
+		if (i > IPSET_MAX_RANGE) {
+			hash_net4_data_next(&h->next, &e);
+			return -ERANGE;
+		}
 		ip = ip_set_range_to_cidr(ip, ip_to, &e.cidr);
 		ret = adtfn(set, &e, &ext, &ext, flags);
 		if (ret && !ip_set_eexist(ret, flags))
diff --git a/net/netfilter/ipset/ip_set_hash_netiface.c b/net/netfilter/ipset/ip_set_hash_netiface.c
index 9810f5bf63f5e..0310732862362 100644
--- a/net/netfilter/ipset/ip_set_hash_netiface.c
+++ b/net/netfilter/ipset/ip_set_hash_netiface.c
@@ -202,7 +202,7 @@ hash_netiface4_uadt(struct ip_set *set, struct nlattr *tb[],
 	ipset_adtfn adtfn = set->variant->adt[adt];
 	struct hash_netiface4_elem e = { .cidr = HOST_MASK, .elem = 1 };
 	struct ip_set_ext ext = IP_SET_INIT_UEXT(set);
-	u32 ip = 0, ip_to = 0, ipn, n = 0;
+	u32 ip = 0, ip_to = 0, i = 0;
 	int ret;
 
 	if (tb[IPSET_ATTR_LINENO])
@@ -256,19 +256,16 @@ hash_netiface4_uadt(struct ip_set *set, struct nlattr *tb[],
 	} else {
 		ip_set_mask_from_to(ip, ip_to, e.cidr);
 	}
-	ipn = ip;
-	do {
-		ipn = ip_set_range_to_cidr(ipn, ip_to, &e.cidr);
-		n++;
-	} while (ipn++ < ip_to);
-
-	if (n > IPSET_MAX_RANGE)
-		return -ERANGE;
 
 	if (retried)
 		ip = ntohl(h->next.ip);
 	do {
+		i++;
 		e.ip = htonl(ip);
+		if (i > IPSET_MAX_RANGE) {
+			hash_netiface4_data_next(&h->next, &e);
+			return -ERANGE;
+		}
 		ip = ip_set_range_to_cidr(ip, ip_to, &e.cidr);
 		ret = adtfn(set, &e, &ext, &ext, flags);
 
diff --git a/net/netfilter/ipset/ip_set_hash_netnet.c b/net/netfilter/ipset/ip_set_hash_netnet.c
index cdfb78c6e0d3d..8fbe649c9dd3d 100644
--- a/net/netfilter/ipset/ip_set_hash_netnet.c
+++ b/net/netfilter/ipset/ip_set_hash_netnet.c
@@ -166,13 +166,12 @@ static int
 hash_netnet4_uadt(struct ip_set *set, struct nlattr *tb[],
 		  enum ipset_adt adt, u32 *lineno, u32 flags, bool retried)
 {
-	const struct hash_netnet4 *h = set->data;
+	struct hash_netnet4 *h = set->data;
 	ipset_adtfn adtfn = set->variant->adt[adt];
 	struct hash_netnet4_elem e = { };
 	struct ip_set_ext ext = IP_SET_INIT_UEXT(set);
 	u32 ip = 0, ip_to = 0;
-	u32 ip2 = 0, ip2_from = 0, ip2_to = 0, ipn;
-	u64 n = 0, m = 0;
+	u32 ip2 = 0, ip2_from = 0, ip2_to = 0, i = 0;
 	int ret;
 
 	if (tb[IPSET_ATTR_LINENO])
@@ -248,19 +247,6 @@ hash_netnet4_uadt(struct ip_set *set, struct nlattr *tb[],
 	} else {
 		ip_set_mask_from_to(ip2_from, ip2_to, e.cidr[1]);
 	}
-	ipn = ip;
-	do {
-		ipn = ip_set_range_to_cidr(ipn, ip_to, &e.cidr[0]);
-		n++;
-	} while (ipn++ < ip_to);
-	ipn = ip2_from;
-	do {
-		ipn = ip_set_range_to_cidr(ipn, ip2_to, &e.cidr[1]);
-		m++;
-	} while (ipn++ < ip2_to);
-
-	if (n*m > IPSET_MAX_RANGE)
-		return -ERANGE;
 
 	if (retried) {
 		ip = ntohl(h->next.ip[0]);
@@ -273,7 +259,12 @@ hash_netnet4_uadt(struct ip_set *set, struct nlattr *tb[],
 		e.ip[0] = htonl(ip);
 		ip = ip_set_range_to_cidr(ip, ip_to, &e.cidr[0]);
 		do {
+			i++;
 			e.ip[1] = htonl(ip2);
+			if (i > IPSET_MAX_RANGE) {
+				hash_netnet4_data_next(&h->next, &e);
+				return -ERANGE;
+			}
 			ip2 = ip_set_range_to_cidr(ip2, ip2_to, &e.cidr[1]);
 			ret = adtfn(set, &e, &ext, &ext, flags);
 			if (ret && !ip_set_eexist(ret, flags))
diff --git a/net/netfilter/ipset/ip_set_hash_netport.c b/net/netfilter/ipset/ip_set_hash_netport.c
index 09cf72eb37f8d..d1a0628df4ef3 100644
--- a/net/netfilter/ipset/ip_set_hash_netport.c
+++ b/net/netfilter/ipset/ip_set_hash_netport.c
@@ -154,12 +154,11 @@ static int
 hash_netport4_uadt(struct ip_set *set, struct nlattr *tb[],
 		   enum ipset_adt adt, u32 *lineno, u32 flags, bool retried)
 {
-	const struct hash_netport4 *h = set->data;
+	struct hash_netport4 *h = set->data;
 	ipset_adtfn adtfn = set->variant->adt[adt];
 	struct hash_netport4_elem e = { .cidr = HOST_MASK - 1 };
 	struct ip_set_ext ext = IP_SET_INIT_UEXT(set);
-	u32 port, port_to, p = 0, ip = 0, ip_to = 0, ipn;
-	u64 n = 0;
+	u32 port, port_to, p = 0, ip = 0, ip_to = 0, i = 0;
 	bool with_ports = false;
 	u8 cidr;
 	int ret;
@@ -236,14 +235,6 @@ hash_netport4_uadt(struct ip_set *set, struct nlattr *tb[],
 	} else {
 		ip_set_mask_from_to(ip, ip_to, e.cidr + 1);
 	}
-	ipn = ip;
-	do {
-		ipn = ip_set_range_to_cidr(ipn, ip_to, &cidr);
-		n++;
-	} while (ipn++ < ip_to);
-
-	if (n*(port_to - port + 1) > IPSET_MAX_RANGE)
-		return -ERANGE;
 
 	if (retried) {
 		ip = ntohl(h->next.ip);
@@ -255,8 +246,12 @@ hash_netport4_uadt(struct ip_set *set, struct nlattr *tb[],
 		e.ip = htonl(ip);
 		ip = ip_set_range_to_cidr(ip, ip_to, &cidr);
 		e.cidr = cidr - 1;
-		for (; p <= port_to; p++) {
+		for (; p <= port_to; p++, i++) {
 			e.port = htons(p);
+			if (i > IPSET_MAX_RANGE) {
+				hash_netport4_data_next(&h->next, &e);
+				return -ERANGE;
+			}
 			ret = adtfn(set, &e, &ext, &ext, flags);
 			if (ret && !ip_set_eexist(ret, flags))
 				return ret;
-- 
GitLab


From f685dd7a8025f2554f73748cfdb8143a21fb92c7 Mon Sep 17 00:00:00 2001
From: Paul Menzel <pmenzel@molgen.mpg.de>
Date: Mon, 2 Jan 2023 14:57:30 +0100
Subject: [PATCH 854/875] fbdev: matroxfb: G200eW: Increase max memory from 1
 MB to 16 MB
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Commit 62d89a7d49af ("video: fbdev: matroxfb: set maxvram of vbG200eW to
the same as vbG200 to avoid black screen") accidently decreases the
maximum memory size for the Matrox G200eW (102b:0532) from 8 MB to 1 MB
by missing one zero. This caused the driver initialization to fail with
the messages below, as the minimum required VRAM size is 2 MB:

     [    9.436420] matroxfb: Matrox MGA-G200eW (PCI) detected
     [    9.444502] matroxfb: cannot determine memory size
     [    9.449316] matroxfb: probe of 0000:0a:03.0 failed with error -1

So, add the missing 0 to make it the intended 16 MB. Successfully tested on
the Dell PowerEdge R910/0KYD3D, BIOS 2.10.0 08/29/2013, that the warning is
gone.

While at it, add a leading 0 to the maxdisplayable entry, so it’s aligned
properly. The value could probably also be increased from 8 MB to 16 MB, as
the G200 uses the same values, but I have not checked any datasheet.

Note, matroxfb is obsolete and superseded by the maintained DRM driver
mga200, which is used by default on most systems where both drivers are
available. Therefore, on most systems it was only a cosmetic issue.

Fixes: 62d89a7d49af ("video: fbdev: matroxfb: set maxvram of vbG200eW to the same as vbG200 to avoid black screen")
Link: https://lore.kernel.org/linux-fbdev/972999d3-b75d-5680-fcef-6e6905c52ac5@suse.de/T/#mb6953a9995ebd18acc8552f99d6db39787aec775
Cc: it+linux-fbdev@molgen.mpg.de
Cc: Z. Liu <liuzx@knownsec.com>
Cc: Rich Felker <dalias@libc.org>
Cc: stable@vger.kernel.org
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Signed-off-by: Helge Deller <deller@gmx.de>
---
 drivers/video/fbdev/matrox/matroxfb_base.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/video/fbdev/matrox/matroxfb_base.c b/drivers/video/fbdev/matrox/matroxfb_base.c
index 0d3cee7ae7268..a043a737ea9f7 100644
--- a/drivers/video/fbdev/matrox/matroxfb_base.c
+++ b/drivers/video/fbdev/matrox/matroxfb_base.c
@@ -1378,8 +1378,8 @@ static struct video_board vbG200 = {
 	.lowlevel = &matrox_G100
 };
 static struct video_board vbG200eW = {
-	.maxvram = 0x100000,
-	.maxdisplayable = 0x800000,
+	.maxvram = 0x1000000,
+	.maxdisplayable = 0x0800000,
 	.accelID = FB_ACCEL_MATROX_MGAG200,
 	.lowlevel = &matrox_G100
 };
-- 
GitLab


From cad853374d85fe678d721512cecfabd7636e51f3 Mon Sep 17 00:00:00 2001
From: Jeff Layton <jlayton@kernel.org>
Date: Tue, 13 Dec 2022 13:08:26 -0500
Subject: [PATCH 855/875] nfsd: fix handling of readdir in v4root vs. mount
 upcall timeout

If v4 READDIR operation hits a mountpoint and gets back an error,
then it will include that entry in the reply and set RDATTR_ERROR for it
to the error.

That's fine for "normal" exported filesystems, but on the v4root, we
need to be more careful to only expose the existence of dentries that
lead to exports.

If the mountd upcall times out while checking to see whether a
mountpoint on the v4root is exported, then we have no recourse other
than to fail the whole operation.

Cc: Steve Dickson <steved@redhat.com>
Link: https://bugzilla.kernel.org/show_bug.cgi?id=216777
Reported-by: JianHong Yin <yin-jianhong@163.com>
Signed-off-by: Jeff Layton <jlayton@kernel.org>
Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
Cc: <stable@vger.kernel.org>
---
 fs/nfsd/nfs4xdr.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/fs/nfsd/nfs4xdr.c b/fs/nfsd/nfs4xdr.c
index 2b4ae858c89be..ebb4d02a42ce6 100644
--- a/fs/nfsd/nfs4xdr.c
+++ b/fs/nfsd/nfs4xdr.c
@@ -3629,6 +3629,17 @@ nfsd4_encode_dirent(void *ccdv, const char *name, int namlen,
 	case nfserr_noent:
 		xdr_truncate_encode(xdr, start_offset);
 		goto skip_entry;
+	case nfserr_jukebox:
+		/*
+		 * The pseudoroot should only display dentries that lead to
+		 * exports. If we get EJUKEBOX here, then we can't tell whether
+		 * this entry should be included. Just fail the whole READDIR
+		 * with NFS4ERR_DELAY in that case, and hope that the situation
+		 * will resolve itself by the client's next attempt.
+		 */
+		if (cd->rd_fhp->fh_export->ex_flags & NFSEXP_V4ROOT)
+			goto fail;
+		fallthrough;
 	default:
 		/*
 		 * If the client requested the RDATTR_ERROR attribute,
-- 
GitLab


From d00dd2f2645dca04cf399d8fc692f3f69b6dd996 Mon Sep 17 00:00:00 2001
From: Takashi Iwai <tiwai@suse.de>
Date: Tue, 22 Nov 2022 12:51:22 +0100
Subject: [PATCH 856/875] x86/kexec: Fix double-free of elf header buffer

After

  b3e34a47f989 ("x86/kexec: fix memory leak of elf header buffer"),

freeing image->elf_headers in the error path of crash_load_segments()
is not needed because kimage_file_post_load_cleanup() will take
care of that later. And not clearing it could result in a double-free.

Drop the superfluous vfree() call at the error path of
crash_load_segments().

Fixes: b3e34a47f989 ("x86/kexec: fix memory leak of elf header buffer")
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Acked-by: Baoquan He <bhe@redhat.com>
Acked-by: Vlastimil Babka <vbabka@suse.cz>
Cc: <stable@kernel.org>
Link: https://lore.kernel.org/r/20221122115122.13937-1-tiwai@suse.de
---
 arch/x86/kernel/crash.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/x86/kernel/crash.c b/arch/x86/kernel/crash.c
index 9730c88530fc8..305514431f26e 100644
--- a/arch/x86/kernel/crash.c
+++ b/arch/x86/kernel/crash.c
@@ -401,10 +401,8 @@ int crash_load_segments(struct kimage *image)
 	kbuf.buf_align = ELF_CORE_HEADER_ALIGN;
 	kbuf.mem = KEXEC_BUF_MEM_UNKNOWN;
 	ret = kexec_add_buffer(&kbuf);
-	if (ret) {
-		vfree((void *)image->elf_headers);
+	if (ret)
 		return ret;
-	}
 	image->elf_load_addr = kbuf.mem;
 	pr_debug("Loaded ELF headers at 0x%lx bufsz=0x%lx memsz=0x%lx\n",
 		 image->elf_load_addr, kbuf.bufsz, kbuf.memsz);
-- 
GitLab


From 0226635c304cfd5c9db9b78c259cb713819b057e Mon Sep 17 00:00:00 2001
From: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp>
Date: Mon, 2 Jan 2023 23:05:33 +0900
Subject: [PATCH 857/875] fs/ntfs3: don't hold ni_lock when calling
 truncate_setsize()

syzbot is reporting hung task at do_user_addr_fault() [1], for there is
a silent deadlock between PG_locked bit and ni_lock lock.

Since filemap_update_page() calls filemap_read_folio() after calling
folio_trylock() which will set PG_locked bit, ntfs_truncate() must not
call truncate_setsize() which will wait for PG_locked bit to be cleared
when holding ni_lock lock.

Link: https://lore.kernel.org/all/00000000000060d41f05f139aa44@google.com/
Link: https://syzkaller.appspot.com/bug?extid=bed15dbf10294aa4f2ae [1]
Reported-by: syzbot <syzbot+bed15dbf10294aa4f2ae@syzkaller.appspotmail.com>
Debugged-by: Linus Torvalds <torvalds@linux-foundation.org>
Co-developed-by: Hillf Danton <hdanton@sina.com>
Signed-off-by: Hillf Danton <hdanton@sina.com>
Signed-off-by: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp>
Fixes: 4342306f0f0d ("fs/ntfs3: Add file operations and implementation")
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
---
 fs/ntfs3/file.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/fs/ntfs3/file.c b/fs/ntfs3/file.c
index e5399ebc3a2b2..d294cd9756887 100644
--- a/fs/ntfs3/file.c
+++ b/fs/ntfs3/file.c
@@ -390,10 +390,10 @@ static int ntfs_truncate(struct inode *inode, loff_t new_size)
 
 	new_valid = ntfs_up_block(sb, min_t(u64, ni->i_valid, new_size));
 
-	ni_lock(ni);
-
 	truncate_setsize(inode, new_size);
 
+	ni_lock(ni);
+
 	down_write(&ni->file.run_lock);
 	err = attr_set_size(ni, ATTR_DATA, NULL, 0, &ni->file.run, new_size,
 			    &new_valid, ni->mi.sbi->options->prealloc, NULL);
-- 
GitLab


From 9c807965483f42df1d053b7436eedd6cf28ece6f Mon Sep 17 00:00:00 2001
From: Daniil Tatianin <d-tatianin@yandex-team.ru>
Date: Mon, 2 Jan 2023 12:53:35 +0300
Subject: [PATCH 858/875] drivers/net/bonding/bond_3ad: return when there's no
 aggregator

Otherwise we would dereference a NULL aggregator pointer when calling
__set_agg_ports_ready on the line below.

Found by Linux Verification Center (linuxtesting.org) with the SVACE
static analysis tool.

Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
Signed-off-by: Daniil Tatianin <d-tatianin@yandex-team.ru>
Reviewed-by: Jiri Pirko <jiri@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/bonding/bond_3ad.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/bonding/bond_3ad.c b/drivers/net/bonding/bond_3ad.c
index 455b555275f12..c99ffe6c683a3 100644
--- a/drivers/net/bonding/bond_3ad.c
+++ b/drivers/net/bonding/bond_3ad.c
@@ -1549,6 +1549,7 @@ static void ad_port_selection_logic(struct port *port, bool *update_slave_arr)
 			slave_err(bond->dev, port->slave->dev,
 				  "Port %d did not find a suitable aggregator\n",
 				  port->actor_port_number);
+			return;
 		}
 	}
 	/* if all aggregator's ports are READY_N == TRUE, set ready=TRUE
-- 
GitLab


From 4af1b64f80fbe1275fb02c5f1c0cef099a4a231f Mon Sep 17 00:00:00 2001
From: Geetha sowjanya <gakula@marvell.com>
Date: Tue, 3 Jan 2023 09:20:12 +0530
Subject: [PATCH 859/875] octeontx2-pf: Fix lmtst ID used in aura free

Current code uses per_cpu pointer to get the lmtst_id mapped to
the core on which aura_free() is executed. Using per_cpu pointer
without preemption disable causing mismatch between lmtst_id and
core on which pointer gets freed. This patch fixes the issue by
disabling preemption around aura_free.

Fixes: ef6c8da71eaf ("octeontx2-pf: cn10K: Reserve LMTST lines per core")
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 .../marvell/octeontx2/nic/otx2_common.c       | 30 +++++++++++++------
 1 file changed, 21 insertions(+), 9 deletions(-)

diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
index 9e10e7471b887..88f8772a61cd5 100644
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
@@ -1012,6 +1012,7 @@ static void otx2_pool_refill_task(struct work_struct *work)
 	rbpool = cq->rbpool;
 	free_ptrs = cq->pool_ptrs;
 
+	get_cpu();
 	while (cq->pool_ptrs) {
 		if (otx2_alloc_rbuf(pfvf, rbpool, &bufptr)) {
 			/* Schedule a WQ if we fails to free atleast half of the
@@ -1031,6 +1032,7 @@ static void otx2_pool_refill_task(struct work_struct *work)
 		pfvf->hw_ops->aura_freeptr(pfvf, qidx, bufptr + OTX2_HEAD_ROOM);
 		cq->pool_ptrs--;
 	}
+	put_cpu();
 	cq->refill_task_sched = false;
 }
 
@@ -1368,6 +1370,7 @@ int otx2_sq_aura_pool_init(struct otx2_nic *pfvf)
 	if (err)
 		goto fail;
 
+	get_cpu();
 	/* Allocate pointers and free them to aura/pool */
 	for (qidx = 0; qidx < hw->tot_tx_queues; qidx++) {
 		pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
@@ -1376,18 +1379,24 @@ int otx2_sq_aura_pool_init(struct otx2_nic *pfvf)
 		sq = &qset->sq[qidx];
 		sq->sqb_count = 0;
 		sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(*sq->sqb_ptrs), GFP_KERNEL);
-		if (!sq->sqb_ptrs)
-			return -ENOMEM;
+		if (!sq->sqb_ptrs) {
+			err = -ENOMEM;
+			goto err_mem;
+		}
 
 		for (ptr = 0; ptr < num_sqbs; ptr++) {
-			if (otx2_alloc_rbuf(pfvf, pool, &bufptr))
-				return -ENOMEM;
+			err = otx2_alloc_rbuf(pfvf, pool, &bufptr);
+			if (err)
+				goto err_mem;
 			pfvf->hw_ops->aura_freeptr(pfvf, pool_id, bufptr);
 			sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr;
 		}
 	}
 
-	return 0;
+err_mem:
+	put_cpu();
+	return err ? -ENOMEM : 0;
+
 fail:
 	otx2_mbox_reset(&pfvf->mbox.mbox, 0);
 	otx2_aura_pool_free(pfvf);
@@ -1426,18 +1435,21 @@ int otx2_rq_aura_pool_init(struct otx2_nic *pfvf)
 	if (err)
 		goto fail;
 
+	get_cpu();
 	/* Allocate pointers and free them to aura/pool */
 	for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) {
 		pool = &pfvf->qset.pool[pool_id];
 		for (ptr = 0; ptr < num_ptrs; ptr++) {
-			if (otx2_alloc_rbuf(pfvf, pool, &bufptr))
-				return -ENOMEM;
+			err = otx2_alloc_rbuf(pfvf, pool, &bufptr);
+			if (err)
+				goto err_mem;
 			pfvf->hw_ops->aura_freeptr(pfvf, pool_id,
 						   bufptr + OTX2_HEAD_ROOM);
 		}
 	}
-
-	return 0;
+err_mem:
+	put_cpu();
+	return err ? -ENOMEM : 0;
 fail:
 	otx2_mbox_reset(&pfvf->mbox.mbox, 0);
 	otx2_aura_pool_free(pfvf);
-- 
GitLab


From 7dc61838541928895abae6d2355258e02a251bba Mon Sep 17 00:00:00 2001
From: Sean Anderson <seanga2@gmail.com>
Date: Tue, 3 Jan 2023 01:50:38 -0500
Subject: [PATCH 860/875] net: dpaa: Fix dtsec check for PCS availability

We want to fail if the PCS is not available, not if it is available. Fix
this condition.

Fixes: 5d93cfcf7360 ("net: dpaa: Convert to phylink")
Reported-by: Christian Zigotzky <info@xenosoft.de>
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Jiri Pirko <jiri@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/ethernet/freescale/fman/fman_dtsec.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/freescale/fman/fman_dtsec.c b/drivers/net/ethernet/freescale/fman/fman_dtsec.c
index d00bae15a9017..d528ca681b6f4 100644
--- a/drivers/net/ethernet/freescale/fman/fman_dtsec.c
+++ b/drivers/net/ethernet/freescale/fman/fman_dtsec.c
@@ -1430,7 +1430,7 @@ int dtsec_initialization(struct mac_device *mac_dev,
 	dtsec->dtsec_drv_param->tx_pad_crc = true;
 
 	phy_node = of_parse_phandle(mac_node, "tbi-handle", 0);
-	if (!phy_node || of_device_is_available(phy_node)) {
+	if (!phy_node || !of_device_is_available(phy_node)) {
 		of_node_put(phy_node);
 		err = -EINVAL;
 		dev_err_probe(mac_dev->dev, err,
-- 
GitLab


From c7dd13805f8b8fc1ce3b6d40f6aff47e66b72ad2 Mon Sep 17 00:00:00 2001
From: Szymon Heidrich <szymon.heidrich@gmail.com>
Date: Tue, 3 Jan 2023 10:17:09 +0100
Subject: [PATCH 861/875] usb: rndis_host: Secure rndis_query check against int
 overflow

Variables off and len typed as uint32 in rndis_query function
are controlled by incoming RNDIS response message thus their
value may be manipulated. Setting off to a unexpectetly large
value will cause the sum with len and 8 to overflow and pass
the implemented validation step. Consequently the response
pointer will be referring to a location past the expected
buffer boundaries allowing information leakage e.g. via
RNDIS_OID_802_3_PERMANENT_ADDRESS OID.

Fixes: ddda08624013 ("USB: rndis_host, various cleanups")
Signed-off-by: Szymon Heidrich <szymon.heidrich@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 drivers/net/usb/rndis_host.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/usb/rndis_host.c b/drivers/net/usb/rndis_host.c
index f79333fe17836..7b3739b29c8f7 100644
--- a/drivers/net/usb/rndis_host.c
+++ b/drivers/net/usb/rndis_host.c
@@ -255,7 +255,8 @@ static int rndis_query(struct usbnet *dev, struct usb_interface *intf,
 
 	off = le32_to_cpu(u.get_c->offset);
 	len = le32_to_cpu(u.get_c->len);
-	if (unlikely((8 + off + len) > CONTROL_BUFFER_SIZE))
+	if (unlikely((off > CONTROL_BUFFER_SIZE - 8) ||
+		     (len > CONTROL_BUFFER_SIZE - 8 - off)))
 		goto response_error;
 
 	if (*reply_len != -1 && len != *reply_len)
-- 
GitLab


From 55d235361fccef573990dfa5724ab453866e7816 Mon Sep 17 00:00:00 2001
From: Mikulas Patocka <mpatocka@redhat.com>
Date: Tue, 3 Jan 2023 10:24:11 -0500
Subject: [PATCH 862/875] x86/asm: Fix an assembler warning with current
 binutils

Fix a warning: "found `movsd'; assuming `movsl' was meant"

Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: linux-kernel@vger.kernel.org
---
 arch/x86/lib/iomap_copy_64.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/lib/iomap_copy_64.S b/arch/x86/lib/iomap_copy_64.S
index a1f9416bf67a5..6ff2f56cb0f71 100644
--- a/arch/x86/lib/iomap_copy_64.S
+++ b/arch/x86/lib/iomap_copy_64.S
@@ -10,6 +10,6 @@
  */
 SYM_FUNC_START(__iowrite32_copy)
 	movl %edx,%ecx
-	rep movsd
+	rep movsl
 	RET
 SYM_FUNC_END(__iowrite32_copy)
-- 
GitLab


From b3d83066cbebc76dbac8a5fca931f64b4c6fff34 Mon Sep 17 00:00:00 2001
From: Chao Yu <chao@kernel.org>
Date: Fri, 30 Dec 2022 23:43:32 +0800
Subject: [PATCH 863/875] f2fs: fix to avoid NULL pointer dereference in
 f2fs_issue_flush()

With below two cases, it will cause NULL pointer dereference when
accessing SM_I(sbi)->fcc_info in f2fs_issue_flush().

a) If kthread_run() fails in f2fs_create_flush_cmd_control(), it will
release SM_I(sbi)->fcc_info,

- mount -o noflush_merge /dev/vda /mnt/f2fs
- mount -o remount,flush_merge /dev/vda /mnt/f2fs  -- kthread_run() fails
- dd if=/dev/zero of=/mnt/f2fs/file bs=4k count=1 conv=fsync

b) we will never allocate memory for SM_I(sbi)->fcc_info w/ below
testcase,

- mount -o ro /dev/vda /mnt/f2fs
- mount -o rw,remount /dev/vda /mnt/f2fs
- dd if=/dev/zero of=/mnt/f2fs/file bs=4k count=1 conv=fsync

In order to fix this issue, let change as below:
- fix error path handling in f2fs_create_flush_cmd_control().
- allocate SM_I(sbi)->fcc_info even if readonly is on.

Signed-off-by: Chao Yu <chao@kernel.org>
Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
---
 fs/f2fs/segment.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/fs/f2fs/segment.c b/fs/f2fs/segment.c
index 25ddea478fc1a..c3f8c8208eeca 100644
--- a/fs/f2fs/segment.c
+++ b/fs/f2fs/segment.c
@@ -663,8 +663,7 @@ init_thread:
 	if (IS_ERR(fcc->f2fs_issue_flush)) {
 		int err = PTR_ERR(fcc->f2fs_issue_flush);
 
-		kfree(fcc);
-		SM_I(sbi)->fcc_info = NULL;
+		fcc->f2fs_issue_flush = NULL;
 		return err;
 	}
 
@@ -5138,11 +5137,9 @@ int f2fs_build_segment_manager(struct f2fs_sb_info *sbi)
 
 	init_f2fs_rwsem(&sm_info->curseg_lock);
 
-	if (!f2fs_readonly(sbi->sb)) {
-		err = f2fs_create_flush_cmd_control(sbi);
-		if (err)
-			return err;
-	}
+	err = f2fs_create_flush_cmd_control(sbi);
+	if (err)
+		return err;
 
 	err = create_discard_cmd_control(sbi);
 	if (err)
-- 
GitLab


From fe59109ae5c0b34a8c7c07f693fc501b12b57787 Mon Sep 17 00:00:00 2001
From: Jaegeuk Kim <jaegeuk@kernel.org>
Date: Fri, 16 Dec 2022 14:05:44 -0800
Subject: [PATCH 864/875] f2fs: initialize extent_cache parameter

This can avoid confusing tracepoint values.

Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
---
 fs/f2fs/data.c         | 2 +-
 fs/f2fs/extent_cache.c | 2 +-
 fs/f2fs/file.c         | 2 +-
 fs/f2fs/segment.c      | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/fs/f2fs/data.c b/fs/f2fs/data.c
index 6e43e19c7d1ca..97e816590cd95 100644
--- a/fs/f2fs/data.c
+++ b/fs/f2fs/data.c
@@ -2183,7 +2183,7 @@ int f2fs_read_multi_pages(struct compress_ctx *cc, struct bio **bio_ret,
 	sector_t last_block_in_file;
 	const unsigned blocksize = blks_to_bytes(inode, 1);
 	struct decompress_io_ctx *dic = NULL;
-	struct extent_info ei = {0, };
+	struct extent_info ei = {};
 	bool from_dnode = true;
 	int i;
 	int ret = 0;
diff --git a/fs/f2fs/extent_cache.c b/fs/f2fs/extent_cache.c
index 1bd38a78ebba9..3aa2f82960455 100644
--- a/fs/f2fs/extent_cache.c
+++ b/fs/f2fs/extent_cache.c
@@ -938,7 +938,7 @@ out:
 
 static void __update_extent_cache(struct dnode_of_data *dn, enum extent_type type)
 {
-	struct extent_info ei;
+	struct extent_info ei = {};
 
 	if (!__may_extent_tree(dn->inode, type))
 		return;
diff --git a/fs/f2fs/file.c b/fs/f2fs/file.c
index a6c4012798860..ecbc8c135b494 100644
--- a/fs/f2fs/file.c
+++ b/fs/f2fs/file.c
@@ -2559,7 +2559,7 @@ static int f2fs_defragment_range(struct f2fs_sb_info *sbi,
 	struct f2fs_map_blocks map = { .m_next_extent = NULL,
 					.m_seg_type = NO_CHECK_TYPE,
 					.m_may_create = false };
-	struct extent_info ei = {0, };
+	struct extent_info ei = {};
 	pgoff_t pg_start, pg_end, next_pgofs;
 	unsigned int blk_per_seg = sbi->blocks_per_seg;
 	unsigned int total = 0, sec_num;
diff --git a/fs/f2fs/segment.c b/fs/f2fs/segment.c
index c3f8c8208eeca..ae3c4e5474efa 100644
--- a/fs/f2fs/segment.c
+++ b/fs/f2fs/segment.c
@@ -3160,7 +3160,7 @@ static int __get_segment_type_4(struct f2fs_io_info *fio)
 static int __get_age_segment_type(struct inode *inode, pgoff_t pgofs)
 {
 	struct f2fs_sb_info *sbi = F2FS_I_SB(inode);
-	struct extent_info ei;
+	struct extent_info ei = {};
 
 	if (f2fs_lookup_age_extent_cache(inode, pgofs, &ei)) {
 		if (!ei.age)
-- 
GitLab


From ed2724765e58e3310d3de48f4a1761631b3dd640 Mon Sep 17 00:00:00 2001
From: Jaegeuk Kim <jaegeuk@kernel.org>
Date: Fri, 16 Dec 2022 14:41:54 -0800
Subject: [PATCH 865/875] f2fs: don't mix to use union values in extent_info

Let's explicitly use the defined values in block_age case only.

Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
---
 fs/f2fs/extent_cache.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/fs/f2fs/extent_cache.c b/fs/f2fs/extent_cache.c
index 3aa2f82960455..cc3fed04dd6f7 100644
--- a/fs/f2fs/extent_cache.c
+++ b/fs/f2fs/extent_cache.c
@@ -881,7 +881,8 @@ static unsigned long long __calculate_block_age(unsigned long long new,
 }
 
 /* This returns a new age and allocated blocks in ei */
-static int __get_new_block_age(struct inode *inode, struct extent_info *ei)
+static int __get_new_block_age(struct inode *inode, struct extent_info *ei,
+						block_t blkaddr)
 {
 	struct f2fs_sb_info *sbi = F2FS_I_SB(inode);
 	loff_t f_size = i_size_read(inode);
@@ -894,7 +895,7 @@ static int __get_new_block_age(struct inode *inode, struct extent_info *ei)
 	 * block here.
 	 */
 	if ((f_size >> PAGE_SHIFT) == ei->fofs && f_size & (PAGE_SIZE - 1) &&
-			ei->blk == NEW_ADDR)
+			blkaddr == NEW_ADDR)
 		return -EINVAL;
 
 	if (__lookup_extent_tree(inode, ei->fofs, ei, EX_BLOCK_AGE)) {
@@ -915,14 +916,14 @@ static int __get_new_block_age(struct inode *inode, struct extent_info *ei)
 		return 0;
 	}
 
-	f2fs_bug_on(sbi, ei->blk == NULL_ADDR);
+	f2fs_bug_on(sbi, blkaddr == NULL_ADDR);
 
 	/* the data block was allocated for the first time */
-	if (ei->blk == NEW_ADDR)
+	if (blkaddr == NEW_ADDR)
 		goto out;
 
-	if (__is_valid_data_blkaddr(ei->blk) &&
-			!f2fs_is_valid_blkaddr(sbi, ei->blk, DATA_GENERIC_ENHANCE)) {
+	if (__is_valid_data_blkaddr(blkaddr) &&
+	    !f2fs_is_valid_blkaddr(sbi, blkaddr, DATA_GENERIC_ENHANCE)) {
 		f2fs_bug_on(sbi, 1);
 		return -EINVAL;
 	}
@@ -953,8 +954,7 @@ static void __update_extent_cache(struct dnode_of_data *dn, enum extent_type typ
 		else
 			ei.blk = dn->data_blkaddr;
 	} else if (type == EX_BLOCK_AGE) {
-		ei.blk = dn->data_blkaddr;
-		if (__get_new_block_age(dn->inode, &ei))
+		if (__get_new_block_age(dn->inode, &ei, dn->data_blkaddr))
 			return;
 	}
 	__update_extent_tree_range(dn->inode, &ei, type);
-- 
GitLab


From 22a341b43036415718f2d50f5f98b2f891fe17e9 Mon Sep 17 00:00:00 2001
From: Jaegeuk Kim <jaegeuk@kernel.org>
Date: Fri, 16 Dec 2022 16:36:36 -0800
Subject: [PATCH 866/875] f2fs: should use a temp extent_info for lookup

Otherwise, __lookup_extent_tree() will override the given extent_info which will
be used by caller.

Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
---
 fs/f2fs/extent_cache.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/fs/f2fs/extent_cache.c b/fs/f2fs/extent_cache.c
index cc3fed04dd6f7..7b191ff656319 100644
--- a/fs/f2fs/extent_cache.c
+++ b/fs/f2fs/extent_cache.c
@@ -888,6 +888,7 @@ static int __get_new_block_age(struct inode *inode, struct extent_info *ei,
 	loff_t f_size = i_size_read(inode);
 	unsigned long long cur_blocks =
 				atomic64_read(&sbi->allocated_data_blocks);
+	struct extent_info tei = *ei;	/* only fofs and len are valid */
 
 	/*
 	 * When I/O is not aligned to a PAGE_SIZE, update will happen to the last
@@ -898,17 +899,17 @@ static int __get_new_block_age(struct inode *inode, struct extent_info *ei,
 			blkaddr == NEW_ADDR)
 		return -EINVAL;
 
-	if (__lookup_extent_tree(inode, ei->fofs, ei, EX_BLOCK_AGE)) {
+	if (__lookup_extent_tree(inode, ei->fofs, &tei, EX_BLOCK_AGE)) {
 		unsigned long long cur_age;
 
-		if (cur_blocks >= ei->last_blocks)
-			cur_age = cur_blocks - ei->last_blocks;
+		if (cur_blocks >= tei.last_blocks)
+			cur_age = cur_blocks - tei.last_blocks;
 		else
 			/* allocated_data_blocks overflow */
-			cur_age = ULLONG_MAX - ei->last_blocks + cur_blocks;
+			cur_age = ULLONG_MAX - tei.last_blocks + cur_blocks;
 
-		if (ei->age)
-			ei->age = __calculate_block_age(cur_age, ei->age);
+		if (tei.age)
+			ei->age = __calculate_block_age(cur_age, tei.age);
 		else
 			ei->age = cur_age;
 		ei->last_blocks = cur_blocks;
-- 
GitLab


From df9d44b645b83fffccfb4e28c1f93376585fdec8 Mon Sep 17 00:00:00 2001
From: Jaegeuk Kim <jaegeuk@kernel.org>
Date: Wed, 21 Dec 2022 16:14:10 -0800
Subject: [PATCH 867/875] f2fs: let's avoid panic if extent_tree is not created

This patch avoids the below panic.

pc : __lookup_extent_tree+0xd8/0x760
lr : f2fs_do_write_data_page+0x104/0x87c
sp : ffffffc010cbb3c0
x29: ffffffc010cbb3e0 x28: 0000000000000000
x27: ffffff8803e7f020 x26: ffffff8803e7ed40
x25: ffffff8803e7f020 x24: ffffffc010cbb460
x23: ffffffc010cbb480 x22: 0000000000000000
x21: 0000000000000000 x20: ffffffff22e90900
x19: 0000000000000000 x18: ffffffc010c5d080
x17: 0000000000000000 x16: 0000000000000020
x15: ffffffdb1acdbb88 x14: ffffff888759e2b0
x13: 0000000000000000 x12: ffffff802da49000
x11: 000000000a001200 x10: ffffff8803e7ed40
x9 : ffffff8023195800 x8 : ffffff802da49078
x7 : 0000000000000001 x6 : 0000000000000000
x5 : 0000000000000006 x4 : ffffffc010cbba28
x3 : 0000000000000000 x2 : ffffffc010cbb480
x1 : 0000000000000000 x0 : ffffff8803e7ed40
Call trace:
 __lookup_extent_tree+0xd8/0x760
 f2fs_do_write_data_page+0x104/0x87c
 f2fs_write_single_data_page+0x420/0xb60
 f2fs_write_cache_pages+0x418/0xb1c
 __f2fs_write_data_pages+0x428/0x58c
 f2fs_write_data_pages+0x30/0x40
 do_writepages+0x88/0x190
 __writeback_single_inode+0x48/0x448
 writeback_sb_inodes+0x468/0x9e8
 __writeback_inodes_wb+0xb8/0x2a4
 wb_writeback+0x33c/0x740
 wb_do_writeback+0x2b4/0x400
 wb_workfn+0xe4/0x34c
 process_one_work+0x24c/0x5bc
 worker_thread+0x3e8/0xa50
 kthread+0x150/0x1b4

Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
---
 fs/f2fs/extent_cache.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/fs/f2fs/extent_cache.c b/fs/f2fs/extent_cache.c
index 7b191ff656319..342af24b2f8cf 100644
--- a/fs/f2fs/extent_cache.c
+++ b/fs/f2fs/extent_cache.c
@@ -546,7 +546,8 @@ static bool __lookup_extent_tree(struct inode *inode, pgoff_t pgofs,
 	struct extent_node *en;
 	bool ret = false;
 
-	f2fs_bug_on(sbi, !et);
+	if (!et)
+		return false;
 
 	trace_f2fs_lookup_extent_tree_start(inode, pgofs, type);
 
-- 
GitLab


From 72bb8f8cc088730c4d84117a6906f458c2fc64bb Mon Sep 17 00:00:00 2001
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
Date: Sun, 1 Jan 2023 17:29:04 +0100
Subject: [PATCH 868/875] x86/insn: Avoid namespace clash by separating
 instruction decoder MMIO type from MMIO trace type

Both <linux/mmiotrace.h> and <asm/insn-eval.h> define various MMIO_ enum constants,
whose namespace overlaps.

Rename the <asm/insn-eval.h> ones to have a INSN_ prefix, so that the headers can be
used from the same source file.

Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20230101162910.710293-2-Jason@zx2c4.com
---
 arch/x86/coco/tdx/tdx.c          | 26 +++++++++++++-------------
 arch/x86/include/asm/insn-eval.h | 18 +++++++++---------
 arch/x86/kernel/sev.c            | 18 +++++++++---------
 arch/x86/lib/insn-eval.c         | 20 ++++++++++----------
 4 files changed, 41 insertions(+), 41 deletions(-)

diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c
index cfd4c95b9f045..669d9e4f29015 100644
--- a/arch/x86/coco/tdx/tdx.c
+++ b/arch/x86/coco/tdx/tdx.c
@@ -386,8 +386,8 @@ static int handle_mmio(struct pt_regs *regs, struct ve_info *ve)
 {
 	unsigned long *reg, val, vaddr;
 	char buffer[MAX_INSN_SIZE];
+	enum insn_mmio_type mmio;
 	struct insn insn = {};
-	enum mmio_type mmio;
 	int size, extend_size;
 	u8 extend_val = 0;
 
@@ -402,10 +402,10 @@ static int handle_mmio(struct pt_regs *regs, struct ve_info *ve)
 		return -EINVAL;
 
 	mmio = insn_decode_mmio(&insn, &size);
-	if (WARN_ON_ONCE(mmio == MMIO_DECODE_FAILED))
+	if (WARN_ON_ONCE(mmio == INSN_MMIO_DECODE_FAILED))
 		return -EINVAL;
 
-	if (mmio != MMIO_WRITE_IMM && mmio != MMIO_MOVS) {
+	if (mmio != INSN_MMIO_WRITE_IMM && mmio != INSN_MMIO_MOVS) {
 		reg = insn_get_modrm_reg_ptr(&insn, regs);
 		if (!reg)
 			return -EINVAL;
@@ -426,23 +426,23 @@ static int handle_mmio(struct pt_regs *regs, struct ve_info *ve)
 
 	/* Handle writes first */
 	switch (mmio) {
-	case MMIO_WRITE:
+	case INSN_MMIO_WRITE:
 		memcpy(&val, reg, size);
 		if (!mmio_write(size, ve->gpa, val))
 			return -EIO;
 		return insn.length;
-	case MMIO_WRITE_IMM:
+	case INSN_MMIO_WRITE_IMM:
 		val = insn.immediate.value;
 		if (!mmio_write(size, ve->gpa, val))
 			return -EIO;
 		return insn.length;
-	case MMIO_READ:
-	case MMIO_READ_ZERO_EXTEND:
-	case MMIO_READ_SIGN_EXTEND:
+	case INSN_MMIO_READ:
+	case INSN_MMIO_READ_ZERO_EXTEND:
+	case INSN_MMIO_READ_SIGN_EXTEND:
 		/* Reads are handled below */
 		break;
-	case MMIO_MOVS:
-	case MMIO_DECODE_FAILED:
+	case INSN_MMIO_MOVS:
+	case INSN_MMIO_DECODE_FAILED:
 		/*
 		 * MMIO was accessed with an instruction that could not be
 		 * decoded or handled properly. It was likely not using io.h
@@ -459,15 +459,15 @@ static int handle_mmio(struct pt_regs *regs, struct ve_info *ve)
 		return -EIO;
 
 	switch (mmio) {
-	case MMIO_READ:
+	case INSN_MMIO_READ:
 		/* Zero-extend for 32-bit operation */
 		extend_size = size == 4 ? sizeof(*reg) : 0;
 		break;
-	case MMIO_READ_ZERO_EXTEND:
+	case INSN_MMIO_READ_ZERO_EXTEND:
 		/* Zero extend based on operand size */
 		extend_size = insn.opnd_bytes;
 		break;
-	case MMIO_READ_SIGN_EXTEND:
+	case INSN_MMIO_READ_SIGN_EXTEND:
 		/* Sign extend based on operand size */
 		extend_size = insn.opnd_bytes;
 		if (size == 1 && val & BIT(7))
diff --git a/arch/x86/include/asm/insn-eval.h b/arch/x86/include/asm/insn-eval.h
index f07faa61c7f31..54368a43abf67 100644
--- a/arch/x86/include/asm/insn-eval.h
+++ b/arch/x86/include/asm/insn-eval.h
@@ -32,16 +32,16 @@ int insn_fetch_from_user_inatomic(struct pt_regs *regs,
 bool insn_decode_from_regs(struct insn *insn, struct pt_regs *regs,
 			   unsigned char buf[MAX_INSN_SIZE], int buf_size);
 
-enum mmio_type {
-	MMIO_DECODE_FAILED,
-	MMIO_WRITE,
-	MMIO_WRITE_IMM,
-	MMIO_READ,
-	MMIO_READ_ZERO_EXTEND,
-	MMIO_READ_SIGN_EXTEND,
-	MMIO_MOVS,
+enum insn_mmio_type {
+	INSN_MMIO_DECODE_FAILED,
+	INSN_MMIO_WRITE,
+	INSN_MMIO_WRITE_IMM,
+	INSN_MMIO_READ,
+	INSN_MMIO_READ_ZERO_EXTEND,
+	INSN_MMIO_READ_SIGN_EXTEND,
+	INSN_MMIO_MOVS,
 };
 
-enum mmio_type insn_decode_mmio(struct insn *insn, int *bytes);
+enum insn_mmio_type insn_decode_mmio(struct insn *insn, int *bytes);
 
 #endif /* _ASM_X86_INSN_EVAL_H */
diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c
index a428c62330d37..679026a640efd 100644
--- a/arch/x86/kernel/sev.c
+++ b/arch/x86/kernel/sev.c
@@ -1536,32 +1536,32 @@ static enum es_result vc_handle_mmio_movs(struct es_em_ctxt *ctxt,
 static enum es_result vc_handle_mmio(struct ghcb *ghcb, struct es_em_ctxt *ctxt)
 {
 	struct insn *insn = &ctxt->insn;
+	enum insn_mmio_type mmio;
 	unsigned int bytes = 0;
-	enum mmio_type mmio;
 	enum es_result ret;
 	u8 sign_byte;
 	long *reg_data;
 
 	mmio = insn_decode_mmio(insn, &bytes);
-	if (mmio == MMIO_DECODE_FAILED)
+	if (mmio == INSN_MMIO_DECODE_FAILED)
 		return ES_DECODE_FAILED;
 
-	if (mmio != MMIO_WRITE_IMM && mmio != MMIO_MOVS) {
+	if (mmio != INSN_MMIO_WRITE_IMM && mmio != INSN_MMIO_MOVS) {
 		reg_data = insn_get_modrm_reg_ptr(insn, ctxt->regs);
 		if (!reg_data)
 			return ES_DECODE_FAILED;
 	}
 
 	switch (mmio) {
-	case MMIO_WRITE:
+	case INSN_MMIO_WRITE:
 		memcpy(ghcb->shared_buffer, reg_data, bytes);
 		ret = vc_do_mmio(ghcb, ctxt, bytes, false);
 		break;
-	case MMIO_WRITE_IMM:
+	case INSN_MMIO_WRITE_IMM:
 		memcpy(ghcb->shared_buffer, insn->immediate1.bytes, bytes);
 		ret = vc_do_mmio(ghcb, ctxt, bytes, false);
 		break;
-	case MMIO_READ:
+	case INSN_MMIO_READ:
 		ret = vc_do_mmio(ghcb, ctxt, bytes, true);
 		if (ret)
 			break;
@@ -1572,7 +1572,7 @@ static enum es_result vc_handle_mmio(struct ghcb *ghcb, struct es_em_ctxt *ctxt)
 
 		memcpy(reg_data, ghcb->shared_buffer, bytes);
 		break;
-	case MMIO_READ_ZERO_EXTEND:
+	case INSN_MMIO_READ_ZERO_EXTEND:
 		ret = vc_do_mmio(ghcb, ctxt, bytes, true);
 		if (ret)
 			break;
@@ -1581,7 +1581,7 @@ static enum es_result vc_handle_mmio(struct ghcb *ghcb, struct es_em_ctxt *ctxt)
 		memset(reg_data, 0, insn->opnd_bytes);
 		memcpy(reg_data, ghcb->shared_buffer, bytes);
 		break;
-	case MMIO_READ_SIGN_EXTEND:
+	case INSN_MMIO_READ_SIGN_EXTEND:
 		ret = vc_do_mmio(ghcb, ctxt, bytes, true);
 		if (ret)
 			break;
@@ -1600,7 +1600,7 @@ static enum es_result vc_handle_mmio(struct ghcb *ghcb, struct es_em_ctxt *ctxt)
 		memset(reg_data, sign_byte, insn->opnd_bytes);
 		memcpy(reg_data, ghcb->shared_buffer, bytes);
 		break;
-	case MMIO_MOVS:
+	case INSN_MMIO_MOVS:
 		ret = vc_handle_mmio_movs(ctxt, bytes);
 		break;
 	default:
diff --git a/arch/x86/lib/insn-eval.c b/arch/x86/lib/insn-eval.c
index 21104c41cba04..558a605929db5 100644
--- a/arch/x86/lib/insn-eval.c
+++ b/arch/x86/lib/insn-eval.c
@@ -1595,16 +1595,16 @@ bool insn_decode_from_regs(struct insn *insn, struct pt_regs *regs,
  * Returns:
  *
  * Type of the instruction. Size of the memory operand is stored in
- * @bytes. If decode failed, MMIO_DECODE_FAILED returned.
+ * @bytes. If decode failed, INSN_MMIO_DECODE_FAILED returned.
  */
-enum mmio_type insn_decode_mmio(struct insn *insn, int *bytes)
+enum insn_mmio_type insn_decode_mmio(struct insn *insn, int *bytes)
 {
-	enum mmio_type type = MMIO_DECODE_FAILED;
+	enum insn_mmio_type type = INSN_MMIO_DECODE_FAILED;
 
 	*bytes = 0;
 
 	if (insn_get_opcode(insn))
-		return MMIO_DECODE_FAILED;
+		return INSN_MMIO_DECODE_FAILED;
 
 	switch (insn->opcode.bytes[0]) {
 	case 0x88: /* MOV m8,r8 */
@@ -1613,7 +1613,7 @@ enum mmio_type insn_decode_mmio(struct insn *insn, int *bytes)
 	case 0x89: /* MOV m16/m32/m64, r16/m32/m64 */
 		if (!*bytes)
 			*bytes = insn->opnd_bytes;
-		type = MMIO_WRITE;
+		type = INSN_MMIO_WRITE;
 		break;
 
 	case 0xc6: /* MOV m8, imm8 */
@@ -1622,7 +1622,7 @@ enum mmio_type insn_decode_mmio(struct insn *insn, int *bytes)
 	case 0xc7: /* MOV m16/m32/m64, imm16/imm32/imm64 */
 		if (!*bytes)
 			*bytes = insn->opnd_bytes;
-		type = MMIO_WRITE_IMM;
+		type = INSN_MMIO_WRITE_IMM;
 		break;
 
 	case 0x8a: /* MOV r8, m8 */
@@ -1631,7 +1631,7 @@ enum mmio_type insn_decode_mmio(struct insn *insn, int *bytes)
 	case 0x8b: /* MOV r16/r32/r64, m16/m32/m64 */
 		if (!*bytes)
 			*bytes = insn->opnd_bytes;
-		type = MMIO_READ;
+		type = INSN_MMIO_READ;
 		break;
 
 	case 0xa4: /* MOVS m8, m8 */
@@ -1640,7 +1640,7 @@ enum mmio_type insn_decode_mmio(struct insn *insn, int *bytes)
 	case 0xa5: /* MOVS m16/m32/m64, m16/m32/m64 */
 		if (!*bytes)
 			*bytes = insn->opnd_bytes;
-		type = MMIO_MOVS;
+		type = INSN_MMIO_MOVS;
 		break;
 
 	case 0x0f: /* Two-byte instruction */
@@ -1651,7 +1651,7 @@ enum mmio_type insn_decode_mmio(struct insn *insn, int *bytes)
 		case 0xb7: /* MOVZX r32/r64, m16 */
 			if (!*bytes)
 				*bytes = 2;
-			type = MMIO_READ_ZERO_EXTEND;
+			type = INSN_MMIO_READ_ZERO_EXTEND;
 			break;
 
 		case 0xbe: /* MOVSX r16/r32/r64, m8 */
@@ -1660,7 +1660,7 @@ enum mmio_type insn_decode_mmio(struct insn *insn, int *bytes)
 		case 0xbf: /* MOVSX r32/r64, m16 */
 			if (!*bytes)
 				*bytes = 2;
-			type = MMIO_READ_SIGN_EXTEND;
+			type = INSN_MMIO_READ_SIGN_EXTEND;
 			break;
 		}
 		break;
-- 
GitLab


From 558016722e9d5bc0ac79c246ccd14a8a4eb028d4 Mon Sep 17 00:00:00 2001
From: "Srivatsa S. Bhat (VMware)" <srivatsa@csail.mit.edu>
Date: Tue, 3 Jan 2023 14:09:41 -0800
Subject: [PATCH 869/875] MAINTAINERS: Update maintainers for ptp_vmw driver

Vivek has decided to transfer the maintainership of the VMware virtual
PTP clock driver (ptp_vmw) to Srivatsa and Deep. Update the
MAINTAINERS file to reflect this change, and also add Alexey as a
reviewer for the driver.

Signed-off-by: Srivatsa S. Bhat (VMware) <srivatsa@csail.mit.edu>
Acked-by: Vivek Thampi <vivek@vivekthampi.com>
Acked-by: Deep Shah <sdeep@vmware.com>
Acked-by: Alexey Makhalov <amakhalov@vmware.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 MAINTAINERS | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 7f0b7181e60a5..758878c0eddf3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22243,7 +22243,9 @@ F:	drivers/scsi/vmw_pvscsi.c
 F:	drivers/scsi/vmw_pvscsi.h
 
 VMWARE VIRTUAL PTP CLOCK DRIVER
-M:	Vivek Thampi <vithampi@vmware.com>
+M:	Srivatsa S. Bhat (VMware) <srivatsa@csail.mit.edu>
+M:	Deep Shah <sdeep@vmware.com>
+R:	Alexey Makhalov <amakhalov@vmware.com>
 R:	VMware PV-Drivers Reviewers <pv-drivers@vmware.com>
 L:	netdev@vger.kernel.org
 S:	Supported
-- 
GitLab


From a664ec9158eeddd75121d39c9a0758016097fa96 Mon Sep 17 00:00:00 2001
From: Rodrigo Branco <bsdaemon@google.com>
Date: Tue, 3 Jan 2023 14:17:51 -0600
Subject: [PATCH 870/875] x86/bugs: Flush IBP in ib_prctl_set()

We missed the window between the TIF flag update and the next reschedule.

Signed-off-by: Rodrigo Branco <bsdaemon@google.com>
Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: <stable@vger.kernel.org>
---
 arch/x86/kernel/cpu/bugs.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index d970ddb0cc65b..bca0bd8f48464 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -1981,6 +1981,8 @@ static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
 		if (ctrl == PR_SPEC_FORCE_DISABLE)
 			task_set_spec_ib_force_disable(task);
 		task_update_spec_tif(task);
+		if (task == current)
+			indirect_branch_prediction_barrier();
 		break;
 	default:
 		return -ERANGE;
-- 
GitLab


From 5401c3e0992860b11fb4b25796e4c4f1921740df Mon Sep 17 00:00:00 2001
From: Caleb Sander <csander@purestorage.com>
Date: Tue, 3 Jan 2023 16:30:21 -0700
Subject: [PATCH 871/875] qed: allow sleep in qed_mcp_trace_dump()

By default, qed_mcp_cmd_and_union() delays 10us at a time in a loop
that can run 500K times, so calls to qed_mcp_nvm_rd_cmd()
may block the current thread for over 5s.
We observed thread scheduling delays over 700ms in production,
with stacktraces pointing to this code as the culprit.

qed_mcp_trace_dump() is called from ethtool, so sleeping is permitted.
It already can sleep in qed_mcp_halt(), which calls qed_mcp_cmd().
Add a "can sleep" parameter to qed_find_nvram_image() and
qed_nvram_read() so they can sleep during qed_mcp_trace_dump().
qed_mcp_trace_get_meta_info() and qed_mcp_trace_read_meta(),
called only by qed_mcp_trace_dump(), allow these functions to sleep.
I can't tell if the other caller (qed_grc_dump_mcp_hw_dump()) can sleep,
so keep b_can_sleep set to false when it calls these functions.

An example stacktrace from a custom warning we added to the kernel
showing a thread that has not scheduled despite long needing resched:
[ 2745.362925,17] ------------[ cut here ]------------
[ 2745.362941,17] WARNING: CPU: 23 PID: 5640 at arch/x86/kernel/irq.c:233 do_IRQ+0x15e/0x1a0()
[ 2745.362946,17] Thread not rescheduled for 744 ms after irq 99
[ 2745.362956,17] Modules linked in: ...
[ 2745.363339,17] CPU: 23 PID: 5640 Comm: lldpd Tainted: P           O    4.4.182+ #202104120910+6d1da174272d.61x
[ 2745.363343,17] Hardware name: FOXCONN MercuryB/Quicksilver Controller, BIOS H11P1N09 07/08/2020
[ 2745.363346,17]  0000000000000000 ffff885ec07c3ed8 ffffffff8131eb2f ffff885ec07c3f20
[ 2745.363358,17]  ffffffff81d14f64 ffff885ec07c3f10 ffffffff81072ac2 ffff88be98ed0000
[ 2745.363369,17]  0000000000000063 0000000000000174 0000000000000074 0000000000000000
[ 2745.363379,17] Call Trace:
[ 2745.363382,17]  <IRQ>  [<ffffffff8131eb2f>] dump_stack+0x8e/0xcf
[ 2745.363393,17]  [<ffffffff81072ac2>] warn_slowpath_common+0x82/0xc0
[ 2745.363398,17]  [<ffffffff81072b4c>] warn_slowpath_fmt+0x4c/0x50
[ 2745.363404,17]  [<ffffffff810d5a8e>] ? rcu_irq_exit+0xae/0xc0
[ 2745.363408,17]  [<ffffffff817c99fe>] do_IRQ+0x15e/0x1a0
[ 2745.363413,17]  [<ffffffff817c7ac9>] common_interrupt+0x89/0x89
[ 2745.363416,17]  <EOI>  [<ffffffff8132aa74>] ? delay_tsc+0x24/0x50
[ 2745.363425,17]  [<ffffffff8132aa04>] __udelay+0x34/0x40
[ 2745.363457,17]  [<ffffffffa04d45ff>] qed_mcp_cmd_and_union+0x36f/0x7d0 [qed]
[ 2745.363473,17]  [<ffffffffa04d5ced>] qed_mcp_nvm_rd_cmd+0x4d/0x90 [qed]
[ 2745.363490,17]  [<ffffffffa04e1dc7>] qed_mcp_trace_dump+0x4a7/0x630 [qed]
[ 2745.363504,17]  [<ffffffffa04e2556>] ? qed_fw_asserts_dump+0x1d6/0x1f0 [qed]
[ 2745.363520,17]  [<ffffffffa04e4ea7>] qed_dbg_mcp_trace_get_dump_buf_size+0x37/0x80 [qed]
[ 2745.363536,17]  [<ffffffffa04ea881>] qed_dbg_feature_size+0x61/0xa0 [qed]
[ 2745.363551,17]  [<ffffffffa04eb427>] qed_dbg_all_data_size+0x247/0x260 [qed]
[ 2745.363560,17]  [<ffffffffa0482c10>] qede_get_regs_len+0x30/0x40 [qede]
[ 2745.363566,17]  [<ffffffff816c9783>] ethtool_get_drvinfo+0xe3/0x190
[ 2745.363570,17]  [<ffffffff816cc152>] dev_ethtool+0x1362/0x2140
[ 2745.363575,17]  [<ffffffff8109bcc6>] ? finish_task_switch+0x76/0x260
[ 2745.363580,17]  [<ffffffff817c2116>] ? __schedule+0x3c6/0x9d0
[ 2745.363585,17]  [<ffffffff810dbd50>] ? hrtimer_start_range_ns+0x1d0/0x370
[ 2745.363589,17]  [<ffffffff816c1e5b>] ? dev_get_by_name_rcu+0x6b/0x90
[ 2745.363594,17]  [<ffffffff816de6a8>] dev_ioctl+0xe8/0x710
[ 2745.363599,17]  [<ffffffff816a58a8>] sock_do_ioctl+0x48/0x60
[ 2745.363603,17]  [<ffffffff816a5d87>] sock_ioctl+0x1c7/0x280
[ 2745.363608,17]  [<ffffffff8111f393>] ? seccomp_phase1+0x83/0x220
[ 2745.363612,17]  [<ffffffff811e3503>] do_vfs_ioctl+0x2b3/0x4e0
[ 2745.363616,17]  [<ffffffff811e3771>] SyS_ioctl+0x41/0x70
[ 2745.363619,17]  [<ffffffff817c6ffe>] entry_SYSCALL_64_fastpath+0x1e/0x79
[ 2745.363622,17] ---[ end trace f6954aa440266421 ]---

Fixes: c965db4446291 ("qed: Add support for debug data collection")
Signed-off-by: Caleb Sander <csander@purestorage.com>
Acked-by: Alok Prasad <palok@marvell.com>
Link: https://lore.kernel.org/r/20230103233021.1457646-1-csander@purestorage.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/ethernet/qlogic/qed/qed_debug.c | 28 +++++++++++++++------
 1 file changed, 20 insertions(+), 8 deletions(-)

diff --git a/drivers/net/ethernet/qlogic/qed/qed_debug.c b/drivers/net/ethernet/qlogic/qed/qed_debug.c
index 86ecb080b1536..cdcead614e9fa 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_debug.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_debug.c
@@ -1832,7 +1832,8 @@ static enum dbg_status qed_find_nvram_image(struct qed_hwfn *p_hwfn,
 					    struct qed_ptt *p_ptt,
 					    u32 image_type,
 					    u32 *nvram_offset_bytes,
-					    u32 *nvram_size_bytes)
+					    u32 *nvram_size_bytes,
+					    bool b_can_sleep)
 {
 	u32 ret_mcp_resp, ret_mcp_param, ret_txn_size;
 	struct mcp_file_att file_att;
@@ -1846,7 +1847,8 @@ static enum dbg_status qed_find_nvram_image(struct qed_hwfn *p_hwfn,
 					&ret_mcp_resp,
 					&ret_mcp_param,
 					&ret_txn_size,
-					(u32 *)&file_att, false);
+					(u32 *)&file_att,
+					b_can_sleep);
 
 	/* Check response */
 	if (nvm_result || (ret_mcp_resp & FW_MSG_CODE_MASK) !=
@@ -1873,7 +1875,9 @@ static enum dbg_status qed_find_nvram_image(struct qed_hwfn *p_hwfn,
 static enum dbg_status qed_nvram_read(struct qed_hwfn *p_hwfn,
 				      struct qed_ptt *p_ptt,
 				      u32 nvram_offset_bytes,
-				      u32 nvram_size_bytes, u32 *ret_buf)
+				      u32 nvram_size_bytes,
+				      u32 *ret_buf,
+				      bool b_can_sleep)
 {
 	u32 ret_mcp_resp, ret_mcp_param, ret_read_size, bytes_to_copy;
 	s32 bytes_left = nvram_size_bytes;
@@ -1899,7 +1903,7 @@ static enum dbg_status qed_nvram_read(struct qed_hwfn *p_hwfn,
 				       &ret_mcp_resp,
 				       &ret_mcp_param, &ret_read_size,
 				       (u32 *)((u8 *)ret_buf + read_offset),
-				       false))
+				       b_can_sleep))
 			return DBG_STATUS_NVRAM_READ_FAILED;
 
 		/* Check response */
@@ -3380,7 +3384,8 @@ static u32 qed_grc_dump_mcp_hw_dump(struct qed_hwfn *p_hwfn,
 				      p_ptt,
 				      NVM_TYPE_HW_DUMP_OUT,
 				      &hw_dump_offset_bytes,
-				      &hw_dump_size_bytes);
+				      &hw_dump_size_bytes,
+				      false);
 	if (status != DBG_STATUS_OK)
 		return 0;
 
@@ -3397,7 +3402,9 @@ static u32 qed_grc_dump_mcp_hw_dump(struct qed_hwfn *p_hwfn,
 		status = qed_nvram_read(p_hwfn,
 					p_ptt,
 					hw_dump_offset_bytes,
-					hw_dump_size_bytes, dump_buf + offset);
+					hw_dump_size_bytes,
+					dump_buf + offset,
+					false);
 		if (status != DBG_STATUS_OK) {
 			DP_NOTICE(p_hwfn,
 				  "Failed to read MCP HW Dump image from NVRAM\n");
@@ -4123,7 +4130,9 @@ static enum dbg_status qed_mcp_trace_get_meta_info(struct qed_hwfn *p_hwfn,
 	return qed_find_nvram_image(p_hwfn,
 				    p_ptt,
 				    nvram_image_type,
-				    trace_meta_offset, trace_meta_size);
+				    trace_meta_offset,
+				    trace_meta_size,
+				    true);
 }
 
 /* Reads the MCP Trace meta data from NVRAM into the specified buffer */
@@ -4139,7 +4148,10 @@ static enum dbg_status qed_mcp_trace_read_meta(struct qed_hwfn *p_hwfn,
 	/* Read meta data from NVRAM */
 	status = qed_nvram_read(p_hwfn,
 				p_ptt,
-				nvram_offset_in_bytes, size_in_bytes, buf);
+				nvram_offset_in_bytes,
+				size_in_bytes,
+				buf,
+				true);
 	if (status != DBG_STATUS_OK)
 		return status;
 
-- 
GitLab


From 2c02d41d71f90a5168391b6a5f2954112ba2307c Mon Sep 17 00:00:00 2001
From: Paolo Abeni <pabeni@redhat.com>
Date: Tue, 3 Jan 2023 12:19:17 +0100
Subject: [PATCH 872/875] net/ulp: prevent ULP without clone op from entering
 the LISTEN status

When an ULP-enabled socket enters the LISTEN status, the listener ULP data
pointer is copied inside the child/accepted sockets by sk_clone_lock().

The relevant ULP can take care of de-duplicating the context pointer via
the clone() operation, but only MPTCP and SMC implement such op.

Other ULPs may end-up with a double-free at socket disposal time.

We can't simply clear the ULP data at clone time, as TLS replaces the
socket ops with custom ones assuming a valid TLS ULP context is
available.

Instead completely prevent clone-less ULP sockets from entering the
LISTEN status.

Fixes: 734942cc4ea6 ("tcp: ULP infrastructure")
Reported-by: slipper <slipper.alive@gmail.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Link: https://lore.kernel.org/r/4b80c3d1dbe3d0ab072f80450c202d9bc88b4b03.1672740602.git.pabeni@redhat.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 net/ipv4/inet_connection_sock.c | 14 ++++++++++++++
 net/ipv4/tcp_ulp.c              |  4 ++++
 2 files changed, 18 insertions(+)

diff --git a/net/ipv4/inet_connection_sock.c b/net/ipv4/inet_connection_sock.c
index 848ffc3e0239c..d1f8375793983 100644
--- a/net/ipv4/inet_connection_sock.c
+++ b/net/ipv4/inet_connection_sock.c
@@ -1200,12 +1200,26 @@ void inet_csk_prepare_forced_close(struct sock *sk)
 }
 EXPORT_SYMBOL(inet_csk_prepare_forced_close);
 
+static int inet_ulp_can_listen(const struct sock *sk)
+{
+	const struct inet_connection_sock *icsk = inet_csk(sk);
+
+	if (icsk->icsk_ulp_ops && !icsk->icsk_ulp_ops->clone)
+		return -EINVAL;
+
+	return 0;
+}
+
 int inet_csk_listen_start(struct sock *sk)
 {
 	struct inet_connection_sock *icsk = inet_csk(sk);
 	struct inet_sock *inet = inet_sk(sk);
 	int err;
 
+	err = inet_ulp_can_listen(sk);
+	if (unlikely(err))
+		return err;
+
 	reqsk_queue_alloc(&icsk->icsk_accept_queue);
 
 	sk->sk_ack_backlog = 0;
diff --git a/net/ipv4/tcp_ulp.c b/net/ipv4/tcp_ulp.c
index 9ae50b1bd8444..05b6077b9f2c3 100644
--- a/net/ipv4/tcp_ulp.c
+++ b/net/ipv4/tcp_ulp.c
@@ -139,6 +139,10 @@ static int __tcp_set_ulp(struct sock *sk, const struct tcp_ulp_ops *ulp_ops)
 	if (sk->sk_socket)
 		clear_bit(SOCK_SUPPORT_ZC, &sk->sk_socket->flags);
 
+	err = -EINVAL;
+	if (!ulp_ops->clone && sk->sk_state == TCP_LISTEN)
+		goto out_err;
+
 	err = ulp_ops->init(sk);
 	if (err)
 		goto out_err;
-- 
GitLab


From 1ac88557447088ccd15eb2f2520ce46d463c8e0b Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Tue, 3 Jan 2023 19:27:36 +0000
Subject: [PATCH 873/875] inet: control sockets should not use current thread
 task_frag

Because ICMP handlers run from softirq contexts,
they must not use current thread task_frag.

Previously, all sockets allocated by inet_ctl_sock_create()
would use the per-socket page fragment, with no chance of
recursion.

Fixes: 98123866fcf3 ("Treewide: Stop corrupting socket's task_frag")
Reported-by: syzbot+bebc6f1acdf4cbb79b03@syzkaller.appspotmail.com
Signed-off-by: Eric Dumazet <edumazet@google.com>
Cc: Benjamin Coddington <bcodding@redhat.com>
Acked-by: Guillaume Nault <gnault@redhat.com>
Link: https://lore.kernel.org/r/20230103192736.454149-1-edumazet@google.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 net/ipv4/af_inet.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/net/ipv4/af_inet.c b/net/ipv4/af_inet.c
index ab4a06be489b5..6c0ec27899431 100644
--- a/net/ipv4/af_inet.c
+++ b/net/ipv4/af_inet.c
@@ -1665,6 +1665,7 @@ int inet_ctl_sock_create(struct sock **sk, unsigned short family,
 	if (rc == 0) {
 		*sk = sock->sk;
 		(*sk)->sk_allocation = GFP_ATOMIC;
+		(*sk)->sk_use_task_frag = false;
 		/*
 		 * Unhash it so that IP input processing does not even see it,
 		 * we do not wish this socket to see incoming packets.
-- 
GitLab


From fe69230f05897b3de758427b574fc98025dfc907 Mon Sep 17 00:00:00 2001
From: Zhengchao Shao <shaozhengchao@huawei.com>
Date: Wed, 4 Jan 2023 14:51:46 +0800
Subject: [PATCH 874/875] caif: fix memory leak in cfctrl_linkup_request()

When linktype is unknown or kzalloc failed in cfctrl_linkup_request(),
pkt is not released. Add release process to error path.

Fixes: b482cd2053e3 ("net-caif: add CAIF core protocol stack")
Fixes: 8d545c8f958f ("caif: Disconnect without waiting for response")
Signed-off-by: Zhengchao Shao <shaozhengchao@huawei.com>
Reviewed-by: Jiri Pirko <jiri@nvidia.com>
Link: https://lore.kernel.org/r/20230104065146.1153009-1-shaozhengchao@huawei.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
---
 net/caif/cfctrl.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/net/caif/cfctrl.c b/net/caif/cfctrl.c
index cc405d8c7c303..8480684f27625 100644
--- a/net/caif/cfctrl.c
+++ b/net/caif/cfctrl.c
@@ -269,11 +269,15 @@ int cfctrl_linkup_request(struct cflayer *layer,
 	default:
 		pr_warn("Request setup of bad link type = %d\n",
 			param->linktype);
+		cfpkt_destroy(pkt);
 		return -EINVAL;
 	}
 	req = kzalloc(sizeof(*req), GFP_KERNEL);
-	if (!req)
+	if (!req) {
+		cfpkt_destroy(pkt);
 		return -ENOMEM;
+	}
+
 	req->client_layer = user_layer;
 	req->cmd = CFCTRL_CMD_LINK_SETUP;
 	req->param = *param;
-- 
GitLab


From 634cf6ead93988b0da9ac054521ab63a3ba189db Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Thu, 15 Dec 2022 18:02:28 +0100
Subject: [PATCH 875/875] fbdev: omapfb: avoid stack overflow warning

The dsi_irq_stats structure is a little too big to fit on the
stack of a 32-bit task, depending on the specific gcc options:

fbdev/omap2/omapfb/dss/dsi.c: In function 'dsi_dump_dsidev_irqs':
fbdev/omap2/omapfb/dss/dsi.c:1621:1: error: the frame size of 1064 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]

Since this is only a debugfs file, performance is not critical,
so just dynamically allocate it, and print an error message
in there in place of a failure code when the allocation fails.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Helge Deller <deller@gmx.de>
---
 drivers/video/fbdev/omap2/omapfb/dss/dsi.c | 28 ++++++++++++++--------
 1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/drivers/video/fbdev/omap2/omapfb/dss/dsi.c b/drivers/video/fbdev/omap2/omapfb/dss/dsi.c
index 54b0f034c2edf..7cddb7b8ae344 100644
--- a/drivers/video/fbdev/omap2/omapfb/dss/dsi.c
+++ b/drivers/video/fbdev/omap2/omapfb/dss/dsi.c
@@ -1536,22 +1536,28 @@ static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
 {
 	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 	unsigned long flags;
-	struct dsi_irq_stats stats;
+	struct dsi_irq_stats *stats;
+
+	stats = kzalloc(sizeof(*stats), GFP_KERNEL);
+	if (!stats) {
+		seq_printf(s, "out of memory\n");
+		return;
+	}
 
 	spin_lock_irqsave(&dsi->irq_stats_lock, flags);
 
-	stats = dsi->irq_stats;
+	*stats = dsi->irq_stats;
 	memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
 	dsi->irq_stats.last_reset = jiffies;
 
 	spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
 
 	seq_printf(s, "period %u ms\n",
-			jiffies_to_msecs(jiffies - stats.last_reset));
+			jiffies_to_msecs(jiffies - stats->last_reset));
 
-	seq_printf(s, "irqs %d\n", stats.irq_count);
+	seq_printf(s, "irqs %d\n", stats->irq_count);
 #define PIS(x) \
-	seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1])
+	seq_printf(s, "%-20s %10d\n", #x, stats->dsi_irqs[ffs(DSI_IRQ_##x)-1])
 
 	seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
 	PIS(VC0);
@@ -1575,10 +1581,10 @@ static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
 
 #define PIS(x) \
 	seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
-			stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
-			stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
-			stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
-			stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
+			stats->vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
+			stats->vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
+			stats->vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
+			stats->vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
 
 	seq_printf(s, "-- VC interrupts --\n");
 	PIS(CS);
@@ -1594,7 +1600,7 @@ static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
 
 #define PIS(x) \
 	seq_printf(s, "%-20s %10d\n", #x, \
-			stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
+			stats->cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
 
 	seq_printf(s, "-- CIO interrupts --\n");
 	PIS(ERRSYNCESC1);
@@ -1618,6 +1624,8 @@ static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
 	PIS(ULPSACTIVENOT_ALL0);
 	PIS(ULPSACTIVENOT_ALL1);
 #undef PIS
+
+	kfree(stats);
 }
 
 static void dsi1_dump_irqs(struct seq_file *s)
-- 
GitLab